--- old/src/cpu/zero/vm/icache_zero.hpp	2010-11-16 18:04:13.000000000 +0100
+++ new/src/cpu/zero/vm/icache_zero.hpp	2010-11-16 18:04:13.000000000 +0100
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003, 2004, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
  * Copyright 2007, 2009 Red Hat, Inc.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
@@ -23,6 +23,9 @@
  *
  */
 
+#ifndef CPU_ZERO_VM_ICACHE_ZERO_HPP
+#define CPU_ZERO_VM_ICACHE_ZERO_HPP
+
 // Interface for updating the instruction cache.  Whenever the VM
 // modifies code, part of the processor instruction cache potentially
 // has to be flushed.  This implementation is empty: Zero never deals
@@ -34,3 +37,5 @@
   static void invalidate_word(address addr) {}
   static void invalidate_range(address start, int nbytes) {}
 };
+
+#endif // CPU_ZERO_VM_ICACHE_ZERO_HPP