1 //
2 // Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
242
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
246
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
256
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
260
261 static int sizeof_FFree_Float_Stack_All = -1;
262
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
267
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
273
274 //
275 // Compute padding required for nodes which need alignment
276 //
277
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
285
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
294
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
303
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
315
316 // EMIT_OPCODE()
317 void emit_opcode(CodeBuffer &cbuf, int code) {
318 cbuf.insts()->emit_int8((unsigned char) code);
319 }
320
321 // EMIT_OPCODE() w/ relocation information
322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
324 emit_opcode(cbuf, code);
325 }
326
327 // EMIT_D8()
328 void emit_d8(CodeBuffer &cbuf, int d8) {
329 cbuf.insts()->emit_int8((unsigned char) d8);
330 }
331
332 // EMIT_D16()
333 void emit_d16(CodeBuffer &cbuf, int d16) {
334 cbuf.insts()->emit_int16(d16);
335 }
336
337 // EMIT_D32()
338 void emit_d32(CodeBuffer &cbuf, int d32) {
339 cbuf.insts()->emit_int32(d32);
340 }
341
342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
344 int format) {
345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
346 cbuf.insts()->emit_int32(d32);
347 }
348
349 // emit 32 bit value and construct relocation entry from RelocationHolder
350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
351 int format) {
352 #ifdef ASSERT
353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
355 }
356 #endif
357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
358 cbuf.insts()->emit_int32(d32);
359 }
360
361 // Access stack slot for load or store
362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
364 if( -128 <= disp && disp <= 127 ) {
365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
367 emit_d8 (cbuf, disp); // Displacement // R/M byte
368 } else {
369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
371 emit_d32(cbuf, disp); // Displacement // R/M byte
372 }
373 }
374
375 // rRegI ereg, memory mem) %{ // emit_reg_mem
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
377 // There is no index & no scale, use form without SIB byte
378 if ((index == 0x4) &&
379 (scale == 0) && (base != ESP_enc)) {
380 // If no displacement, mode is 0x0; unless base is [EBP]
381 if ( (displace == 0) && (base != EBP_enc) ) {
382 emit_rm(cbuf, 0x0, reg_encoding, base);
383 }
384 else { // If 8-bit displacement, mode 0x1
385 if ((displace >= -128) && (displace <= 127)
386 && (disp_reloc == relocInfo::none) ) {
387 emit_rm(cbuf, 0x1, reg_encoding, base);
388 emit_d8(cbuf, displace);
389 }
390 else { // If 32-bit displacement
391 if (base == -1) { // Special flag for absolute address
392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
393 // (manual lies; no SIB needed here)
394 if ( disp_reloc != relocInfo::none ) {
395 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
396 } else {
397 emit_d32 (cbuf, displace);
398 }
399 }
400 else { // Normal base + offset
401 emit_rm(cbuf, 0x2, reg_encoding, base);
402 if ( disp_reloc != relocInfo::none ) {
403 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
404 } else {
405 emit_d32 (cbuf, displace);
406 }
407 }
408 }
409 }
410 }
411 else { // Else, encode with the SIB byte
412 // If no displacement, mode is 0x0; unless base is [EBP]
413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 }
417 else { // If 8-bit displacement, mode 0x1
418 if ((displace >= -128) && (displace <= 127)
419 && (disp_reloc == relocInfo::none) ) {
420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, base);
422 emit_d8(cbuf, displace);
423 }
424 else { // If 32-bit displacement
425 if (base == 0x04 ) {
426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
427 emit_rm(cbuf, scale, index, 0x04);
428 } else {
429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
430 emit_rm(cbuf, scale, index, base);
431 }
432 if ( disp_reloc != relocInfo::none ) {
433 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441
442
443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
444 if( dst_encoding == src_encoding ) {
445 // reg-reg copy, use an empty encoding
446 } else {
447 emit_opcode( cbuf, 0x8B );
448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
449 }
450 }
451
452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
453 Label exit;
454 __ jccb(Assembler::noParity, exit);
455 __ pushf();
456 //
457 // comiss/ucomiss instructions set ZF,PF,CF flags and
458 // zero OF,AF,SF for NaN values.
459 // Fixup flags by zeroing ZF,PF so that compare of NaN
460 // values returns 'less than' result (CF is set).
461 // Leave the rest of flags unchanged.
462 //
463 // 7 6 5 4 3 2 1 0
464 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
465 // 0 0 1 0 1 0 1 1 (0x2B)
466 //
467 __ andl(Address(rsp, 0), 0xffffff2b);
468 __ popf();
469 __ bind(exit);
470 }
471
472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
473 Label done;
474 __ movl(dst, -1);
475 __ jcc(Assembler::parity, done);
476 __ jcc(Assembler::below, done);
477 __ setb(Assembler::notEqual, dst);
478 __ movzbl(dst, dst);
479 __ bind(done);
480 }
481
482
483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
485
486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset
488 }
489
490 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
491 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
492 ShouldNotReachHere();
493 }
494
495 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
496 // Empty encoding
497 }
498
499 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
500 return 0;
501 }
502
503 #ifndef PRODUCT
504 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
505 st->print("# MachConstantBaseNode (empty encoding)");
506 }
507 #endif
508
509
510 //=============================================================================
511 #ifndef PRODUCT
512 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
513 Compile* C = ra_->C;
514
515 int framesize = C->frame_size_in_bytes();
516 int bangsize = C->bang_size_in_bytes();
517 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
518 // Remove wordSize for return addr which is already pushed.
519 framesize -= wordSize;
520
521 if (C->need_stack_bang(bangsize)) {
522 framesize -= wordSize;
523 st->print("# stack bang (%d bytes)", bangsize);
524 st->print("\n\t");
525 st->print("PUSH EBP\t# Save EBP");
526 if (framesize) {
527 st->print("\n\t");
528 st->print("SUB ESP, #%d\t# Create frame",framesize);
529 }
530 } else {
531 st->print("SUB ESP, #%d\t# Create frame",framesize);
532 st->print("\n\t");
533 framesize -= wordSize;
534 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
535 }
536
537 if (VerifyStackAtCalls) {
538 st->print("\n\t");
539 framesize -= wordSize;
540 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
541 }
542
543 if( C->in_24_bit_fp_mode() ) {
544 st->print("\n\t");
545 st->print("FLDCW \t# load 24 bit fpu control word");
546 }
547 if (UseSSE >= 2 && VerifyFPU) {
548 st->print("\n\t");
549 st->print("# verify FPU stack (must be clean on entry)");
550 }
551
552 #ifdef ASSERT
553 if (VerifyStackAtCalls) {
554 st->print("\n\t");
555 st->print("# stack alignment check");
556 }
557 #endif
558 st->cr();
559 }
560 #endif
561
562
563 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
564 Compile* C = ra_->C;
565 MacroAssembler _masm(&cbuf);
566
567 int framesize = C->frame_size_in_bytes();
568 int bangsize = C->bang_size_in_bytes();
569
570 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, C->in_24_bit_fp_mode());
571
572 C->set_frame_complete(cbuf.insts_size());
573
574 if (C->has_mach_constant_base_node()) {
575 // NOTE: We set the table base offset here because users might be
576 // emitted before MachConstantBaseNode.
577 Compile::ConstantTable& constant_table = C->constant_table();
578 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
579 }
580 }
581
582 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
583 return MachNode::size(ra_); // too many variables; just compute it the hard way
584 }
585
586 int MachPrologNode::reloc() const {
587 return 0; // a large enough number
588 }
589
590 //=============================================================================
591 #ifndef PRODUCT
592 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
593 Compile *C = ra_->C;
594 int framesize = C->frame_size_in_bytes();
595 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
596 // Remove two words for return addr and rbp,
597 framesize -= 2*wordSize;
598
599 if (C->max_vector_size() > 16) {
600 st->print("VZEROUPPER");
601 st->cr(); st->print("\t");
602 }
603 if (C->in_24_bit_fp_mode()) {
604 st->print("FLDCW standard control word");
605 st->cr(); st->print("\t");
606 }
607 if (framesize) {
608 st->print("ADD ESP,%d\t# Destroy frame",framesize);
609 st->cr(); st->print("\t");
610 }
611 st->print_cr("POPL EBP"); st->print("\t");
612 if (do_polling() && C->is_method_compilation()) {
613 st->print("TEST PollPage,EAX\t! Poll Safepoint");
614 st->cr(); st->print("\t");
615 }
616 }
617 #endif
618
619 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
620 Compile *C = ra_->C;
621
622 if (C->max_vector_size() > 16) {
623 // Clear upper bits of YMM registers when current compiled code uses
624 // wide vectors to avoid AVX <-> SSE transition penalty during call.
625 MacroAssembler masm(&cbuf);
626 masm.vzeroupper();
627 }
628 // If method set FPU control word, restore to standard control word
629 if (C->in_24_bit_fp_mode()) {
630 MacroAssembler masm(&cbuf);
631 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
632 }
633
634 int framesize = C->frame_size_in_bytes();
635 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
636 // Remove two words for return addr and rbp,
637 framesize -= 2*wordSize;
638
639 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
640
641 if (framesize >= 128) {
642 emit_opcode(cbuf, 0x81); // add SP, #framesize
643 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
644 emit_d32(cbuf, framesize);
645 } else if (framesize) {
646 emit_opcode(cbuf, 0x83); // add SP, #framesize
647 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
648 emit_d8(cbuf, framesize);
649 }
650
651 emit_opcode(cbuf, 0x58 | EBP_enc);
652
653 if (do_polling() && C->is_method_compilation()) {
654 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
655 emit_opcode(cbuf,0x85);
656 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
657 emit_d32(cbuf, (intptr_t)os::get_polling_page());
658 }
659 }
660
661 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
662 Compile *C = ra_->C;
663 // If method set FPU control word, restore to standard control word
664 int size = C->in_24_bit_fp_mode() ? 6 : 0;
665 if (C->max_vector_size() > 16) size += 3; // vzeroupper
666 if (do_polling() && C->is_method_compilation()) size += 6;
667
668 int framesize = C->frame_size_in_bytes();
669 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
670 // Remove two words for return addr and rbp,
671 framesize -= 2*wordSize;
672
673 size++; // popl rbp,
674
675 if (framesize >= 128) {
676 size += 6;
677 } else {
678 size += framesize ? 3 : 0;
679 }
680 return size;
681 }
682
683 int MachEpilogNode::reloc() const {
684 return 0; // a large enough number
685 }
686
687 const Pipeline * MachEpilogNode::pipeline() const {
688 return MachNode::pipeline_class();
689 }
690
691 int MachEpilogNode::safepoint_offset() const { return 0; }
692
693 //=============================================================================
694
695 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
696 static enum RC rc_class( OptoReg::Name reg ) {
697
698 if( !OptoReg::is_valid(reg) ) return rc_bad;
699 if (OptoReg::is_stack(reg)) return rc_stack;
700
701 VMReg r = OptoReg::as_VMReg(reg);
702 if (r->is_Register()) return rc_int;
703 if (r->is_FloatRegister()) {
704 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
705 return rc_float;
706 }
707 assert(r->is_XMMRegister(), "must be");
708 return rc_xmm;
709 }
710
711 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
712 int opcode, const char *op_str, int size, outputStream* st ) {
713 if( cbuf ) {
714 emit_opcode (*cbuf, opcode );
715 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
716 #ifndef PRODUCT
717 } else if( !do_size ) {
718 if( size != 0 ) st->print("\n\t");
719 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
720 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
721 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
722 } else { // FLD, FST, PUSH, POP
723 st->print("%s [ESP + #%d]",op_str,offset);
724 }
725 #endif
726 }
727 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
728 return size+3+offset_size;
729 }
730
731 // Helper for XMM registers. Extra opcode bits, limited syntax.
732 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
733 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
734 if (cbuf) {
735 MacroAssembler _masm(cbuf);
736 if (reg_lo+1 == reg_hi) { // double move?
737 if (is_load) {
738 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
739 } else {
740 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
741 }
742 } else {
743 if (is_load) {
744 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
745 } else {
746 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
747 }
748 }
749 #ifndef PRODUCT
750 } else if (!do_size) {
751 if (size != 0) st->print("\n\t");
752 if (reg_lo+1 == reg_hi) { // double move?
753 if (is_load) st->print("%s %s,[ESP + #%d]",
754 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
755 Matcher::regName[reg_lo], offset);
756 else st->print("MOVSD [ESP + #%d],%s",
757 offset, Matcher::regName[reg_lo]);
758 } else {
759 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
760 Matcher::regName[reg_lo], offset);
761 else st->print("MOVSS [ESP + #%d],%s",
762 offset, Matcher::regName[reg_lo]);
763 }
764 #endif
765 }
766 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
767 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
768 return size+5+offset_size;
769 }
770
771
772 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
773 int src_hi, int dst_hi, int size, outputStream* st ) {
774 if (cbuf) {
775 MacroAssembler _masm(cbuf);
776 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
777 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
778 as_XMMRegister(Matcher::_regEncode[src_lo]));
779 } else {
780 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
781 as_XMMRegister(Matcher::_regEncode[src_lo]));
782 }
783 #ifndef PRODUCT
784 } else if (!do_size) {
785 if (size != 0) st->print("\n\t");
786 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
787 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
788 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
789 } else {
790 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
791 }
792 } else {
793 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
794 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
795 } else {
796 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
797 }
798 }
799 #endif
800 }
801 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
802 // Only MOVAPS SSE prefix uses 1 byte.
803 int sz = 4;
804 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
805 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
806 return size + sz;
807 }
808
809 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
810 int src_hi, int dst_hi, int size, outputStream* st ) {
811 // 32-bit
812 if (cbuf) {
813 MacroAssembler _masm(cbuf);
814 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
815 as_Register(Matcher::_regEncode[src_lo]));
816 #ifndef PRODUCT
817 } else if (!do_size) {
818 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
819 #endif
820 }
821 return 4;
822 }
823
824
825 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
826 int src_hi, int dst_hi, int size, outputStream* st ) {
827 // 32-bit
828 if (cbuf) {
829 MacroAssembler _masm(cbuf);
830 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
831 as_XMMRegister(Matcher::_regEncode[src_lo]));
832 #ifndef PRODUCT
833 } else if (!do_size) {
834 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
835 #endif
836 }
837 return 4;
838 }
839
840 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
841 if( cbuf ) {
842 emit_opcode(*cbuf, 0x8B );
843 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
844 #ifndef PRODUCT
845 } else if( !do_size ) {
846 if( size != 0 ) st->print("\n\t");
847 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
848 #endif
849 }
850 return size+2;
851 }
852
853 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
854 int offset, int size, outputStream* st ) {
855 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
856 if( cbuf ) {
857 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
858 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
859 #ifndef PRODUCT
860 } else if( !do_size ) {
861 if( size != 0 ) st->print("\n\t");
862 st->print("FLD %s",Matcher::regName[src_lo]);
863 #endif
864 }
865 size += 2;
866 }
867
868 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
869 const char *op_str;
870 int op;
871 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
872 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
873 op = 0xDD;
874 } else { // 32-bit store
875 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
876 op = 0xD9;
877 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
878 }
879
880 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
881 }
882
883 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
884 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
885 int src_hi, int dst_hi, uint ireg, outputStream* st);
886
887 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
888 int stack_offset, int reg, uint ireg, outputStream* st);
889
890 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
891 int dst_offset, uint ireg, outputStream* st) {
892 int calc_size = 0;
893 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
894 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
895 switch (ireg) {
896 case Op_VecS:
897 calc_size = 3+src_offset_size + 3+dst_offset_size;
898 break;
899 case Op_VecD:
900 calc_size = 3+src_offset_size + 3+dst_offset_size;
901 src_offset += 4;
902 dst_offset += 4;
903 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
904 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
905 calc_size += 3+src_offset_size + 3+dst_offset_size;
906 break;
907 case Op_VecX:
908 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
909 break;
910 case Op_VecY:
911 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
912 break;
913 default:
914 ShouldNotReachHere();
915 }
916 if (cbuf) {
917 MacroAssembler _masm(cbuf);
918 int offset = __ offset();
919 switch (ireg) {
920 case Op_VecS:
921 __ pushl(Address(rsp, src_offset));
922 __ popl (Address(rsp, dst_offset));
923 break;
924 case Op_VecD:
925 __ pushl(Address(rsp, src_offset));
926 __ popl (Address(rsp, dst_offset));
927 __ pushl(Address(rsp, src_offset+4));
928 __ popl (Address(rsp, dst_offset+4));
929 break;
930 case Op_VecX:
931 __ movdqu(Address(rsp, -16), xmm0);
932 __ movdqu(xmm0, Address(rsp, src_offset));
933 __ movdqu(Address(rsp, dst_offset), xmm0);
934 __ movdqu(xmm0, Address(rsp, -16));
935 break;
936 case Op_VecY:
937 __ vmovdqu(Address(rsp, -32), xmm0);
938 __ vmovdqu(xmm0, Address(rsp, src_offset));
939 __ vmovdqu(Address(rsp, dst_offset), xmm0);
940 __ vmovdqu(xmm0, Address(rsp, -32));
941 break;
942 default:
943 ShouldNotReachHere();
944 }
945 int size = __ offset() - offset;
946 assert(size == calc_size, "incorrect size calculattion");
947 return size;
948 #ifndef PRODUCT
949 } else if (!do_size) {
950 switch (ireg) {
951 case Op_VecS:
952 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
953 "popl [rsp + #%d]",
954 src_offset, dst_offset);
955 break;
956 case Op_VecD:
957 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
958 "popq [rsp + #%d]\n\t"
959 "pushl [rsp + #%d]\n\t"
960 "popq [rsp + #%d]",
961 src_offset, dst_offset, src_offset+4, dst_offset+4);
962 break;
963 case Op_VecX:
964 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
965 "movdqu xmm0, [rsp + #%d]\n\t"
966 "movdqu [rsp + #%d], xmm0\n\t"
967 "movdqu xmm0, [rsp - #16]",
968 src_offset, dst_offset);
969 break;
970 case Op_VecY:
971 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
972 "vmovdqu xmm0, [rsp + #%d]\n\t"
973 "vmovdqu [rsp + #%d], xmm0\n\t"
974 "vmovdqu xmm0, [rsp - #32]",
975 src_offset, dst_offset);
976 break;
977 default:
978 ShouldNotReachHere();
979 }
980 #endif
981 }
982 return calc_size;
983 }
984
985 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
986 // Get registers to move
987 OptoReg::Name src_second = ra_->get_reg_second(in(1));
988 OptoReg::Name src_first = ra_->get_reg_first(in(1));
989 OptoReg::Name dst_second = ra_->get_reg_second(this );
990 OptoReg::Name dst_first = ra_->get_reg_first(this );
991
992 enum RC src_second_rc = rc_class(src_second);
993 enum RC src_first_rc = rc_class(src_first);
994 enum RC dst_second_rc = rc_class(dst_second);
995 enum RC dst_first_rc = rc_class(dst_first);
996
997 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
998
999 // Generate spill code!
1000 int size = 0;
1001
1002 if( src_first == dst_first && src_second == dst_second )
1003 return size; // Self copy, no move
1004
1005 if (bottom_type()->isa_vect() != NULL) {
1006 uint ireg = ideal_reg();
1007 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1008 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1009 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1010 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1011 // mem -> mem
1012 int src_offset = ra_->reg2offset(src_first);
1013 int dst_offset = ra_->reg2offset(dst_first);
1014 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1015 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1016 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1017 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1018 int stack_offset = ra_->reg2offset(dst_first);
1019 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1020 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1021 int stack_offset = ra_->reg2offset(src_first);
1022 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1023 } else {
1024 ShouldNotReachHere();
1025 }
1026 }
1027
1028 // --------------------------------------
1029 // Check for mem-mem move. push/pop to move.
1030 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1031 if( src_second == dst_first ) { // overlapping stack copy ranges
1032 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1033 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1034 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1035 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1036 }
1037 // move low bits
1038 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1039 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1040 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1041 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1042 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1043 }
1044 return size;
1045 }
1046
1047 // --------------------------------------
1048 // Check for integer reg-reg copy
1049 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1050 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1051
1052 // Check for integer store
1053 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1054 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1055
1056 // Check for integer load
1057 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1058 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1059
1060 // Check for integer reg-xmm reg copy
1061 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1062 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1063 "no 64 bit integer-float reg moves" );
1064 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1065 }
1066 // --------------------------------------
1067 // Check for float reg-reg copy
1068 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1069 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1070 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1071 if( cbuf ) {
1072
1073 // Note the mucking with the register encode to compensate for the 0/1
1074 // indexing issue mentioned in a comment in the reg_def sections
1075 // for FPR registers many lines above here.
1076
1077 if( src_first != FPR1L_num ) {
1078 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1079 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1080 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1081 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1082 } else {
1083 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1084 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1085 }
1086 #ifndef PRODUCT
1087 } else if( !do_size ) {
1088 if( size != 0 ) st->print("\n\t");
1089 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1090 else st->print( "FST %s", Matcher::regName[dst_first]);
1091 #endif
1092 }
1093 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1094 }
1095
1096 // Check for float store
1097 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1098 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1099 }
1100
1101 // Check for float load
1102 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1103 int offset = ra_->reg2offset(src_first);
1104 const char *op_str;
1105 int op;
1106 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1107 op_str = "FLD_D";
1108 op = 0xDD;
1109 } else { // 32-bit load
1110 op_str = "FLD_S";
1111 op = 0xD9;
1112 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1113 }
1114 if( cbuf ) {
1115 emit_opcode (*cbuf, op );
1116 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1117 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1118 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1119 #ifndef PRODUCT
1120 } else if( !do_size ) {
1121 if( size != 0 ) st->print("\n\t");
1122 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1123 #endif
1124 }
1125 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1126 return size + 3+offset_size+2;
1127 }
1128
1129 // Check for xmm reg-reg copy
1130 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1131 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1132 (src_first+1 == src_second && dst_first+1 == dst_second),
1133 "no non-adjacent float-moves" );
1134 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1135 }
1136
1137 // Check for xmm reg-integer reg copy
1138 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1139 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1140 "no 64 bit float-integer reg moves" );
1141 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1142 }
1143
1144 // Check for xmm store
1145 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1146 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1147 }
1148
1149 // Check for float xmm load
1150 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1151 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1152 }
1153
1154 // Copy from float reg to xmm reg
1155 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1156 // copy to the top of stack from floating point reg
1157 // and use LEA to preserve flags
1158 if( cbuf ) {
1159 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1160 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1161 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1162 emit_d8(*cbuf,0xF8);
1163 #ifndef PRODUCT
1164 } else if( !do_size ) {
1165 if( size != 0 ) st->print("\n\t");
1166 st->print("LEA ESP,[ESP-8]");
1167 #endif
1168 }
1169 size += 4;
1170
1171 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1172
1173 // Copy from the temp memory to the xmm reg.
1174 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1175
1176 if( cbuf ) {
1177 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1178 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1179 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1180 emit_d8(*cbuf,0x08);
1181 #ifndef PRODUCT
1182 } else if( !do_size ) {
1183 if( size != 0 ) st->print("\n\t");
1184 st->print("LEA ESP,[ESP+8]");
1185 #endif
1186 }
1187 size += 4;
1188 return size;
1189 }
1190
1191 assert( size > 0, "missed a case" );
1192
1193 // --------------------------------------------------------------------
1194 // Check for second bits still needing moving.
1195 if( src_second == dst_second )
1196 return size; // Self copy; no move
1197 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1198
1199 // Check for second word int-int move
1200 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1201 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1202
1203 // Check for second word integer store
1204 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1205 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1206
1207 // Check for second word integer load
1208 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1209 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1210
1211
1212 fatal("Unimplemented");
1213 }
1214
1215 #ifndef PRODUCT
1216 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1217 implementation( NULL, ra_, false, st );
1218 }
1219 #endif
1220
1221 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1222 implementation( &cbuf, ra_, false, NULL );
1223 }
1224
1225 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1226 return implementation( NULL, ra_, true, NULL );
1227 }
1228
1229
1230 //=============================================================================
1231 #ifndef PRODUCT
1232 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1233 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1234 int reg = ra_->get_reg_first(this);
1235 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1236 }
1237 #endif
1238
1239 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1240 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1241 int reg = ra_->get_encode(this);
1242 if( offset >= 128 ) {
1243 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1244 emit_rm(cbuf, 0x2, reg, 0x04);
1245 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1246 emit_d32(cbuf, offset);
1247 }
1248 else {
1249 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1250 emit_rm(cbuf, 0x1, reg, 0x04);
1251 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1252 emit_d8(cbuf, offset);
1253 }
1254 }
1255
1256 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1257 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1258 if( offset >= 128 ) {
1259 return 7;
1260 }
1261 else {
1262 return 4;
1263 }
1264 }
1265
1266 //=============================================================================
1267 #ifndef PRODUCT
1268 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1269 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1270 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1271 st->print_cr("\tNOP");
1272 st->print_cr("\tNOP");
1273 if( !OptoBreakpoint )
1274 st->print_cr("\tNOP");
1275 }
1276 #endif
1277
1278 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1279 MacroAssembler masm(&cbuf);
1280 #ifdef ASSERT
1281 uint insts_size = cbuf.insts_size();
1282 #endif
1283 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1284 masm.jump_cc(Assembler::notEqual,
1285 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1286 /* WARNING these NOPs are critical so that verified entry point is properly
1287 aligned for patching by NativeJump::patch_verified_entry() */
1288 int nops_cnt = 2;
1289 if( !OptoBreakpoint ) // Leave space for int3
1290 nops_cnt += 1;
1291 masm.nop(nops_cnt);
1292
1293 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1294 }
1295
1296 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1297 return OptoBreakpoint ? 11 : 12;
1298 }
1299
1300
1301 //=============================================================================
1302
1303 int Matcher::regnum_to_fpu_offset(int regnum) {
1304 return regnum - 32; // The FP registers are in the second chunk
1305 }
1306
1307 // This is UltraSparc specific, true just means we have fast l2f conversion
1308 const bool Matcher::convL2FSupported(void) {
1309 return true;
1310 }
1311
1312 // Is this branch offset short enough that a short branch can be used?
1313 //
1314 // NOTE: If the platform does not provide any short branch variants, then
1315 // this method should return false for offset 0.
1316 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1317 // The passed offset is relative to address of the branch.
1318 // On 86 a branch displacement is calculated relative to address
1319 // of a next instruction.
1320 offset -= br_size;
1321
1322 // the short version of jmpConUCF2 contains multiple branches,
1323 // making the reach slightly less
1324 if (rule == jmpConUCF2_rule)
1325 return (-126 <= offset && offset <= 125);
1326 return (-128 <= offset && offset <= 127);
1327 }
1328
1329 const bool Matcher::isSimpleConstant64(jlong value) {
1330 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1331 return false;
1332 }
1333
1334 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1335 const bool Matcher::init_array_count_is_in_bytes = false;
1336
1337 // Threshold size for cleararray.
1338 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1339
1340 // Needs 2 CMOV's for longs.
1341 const int Matcher::long_cmove_cost() { return 1; }
1342
1343 // No CMOVF/CMOVD with SSE/SSE2
1344 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1345
1346 // Does the CPU require late expand (see block.cpp for description of late expand)?
1347 const bool Matcher::require_postalloc_expand = false;
1348
1349 // Should the Matcher clone shifts on addressing modes, expecting them to
1350 // be subsumed into complex addressing expressions or compute them into
1351 // registers? True for Intel but false for most RISCs
1352 const bool Matcher::clone_shift_expressions = true;
1353
1354 // Do we need to mask the count passed to shift instructions or does
1355 // the cpu only look at the lower 5/6 bits anyway?
1356 const bool Matcher::need_masked_shift_count = false;
1357
1358 bool Matcher::narrow_oop_use_complex_address() {
1359 ShouldNotCallThis();
1360 return true;
1361 }
1362
1363 bool Matcher::narrow_klass_use_complex_address() {
1364 ShouldNotCallThis();
1365 return true;
1366 }
1367
1368
1369 // Is it better to copy float constants, or load them directly from memory?
1370 // Intel can load a float constant from a direct address, requiring no
1371 // extra registers. Most RISCs will have to materialize an address into a
1372 // register first, so they would do better to copy the constant from stack.
1373 const bool Matcher::rematerialize_float_constants = true;
1374
1375 // If CPU can load and store mis-aligned doubles directly then no fixup is
1376 // needed. Else we split the double into 2 integer pieces and move it
1377 // piece-by-piece. Only happens when passing doubles into C code as the
1378 // Java calling convention forces doubles to be aligned.
1379 const bool Matcher::misaligned_doubles_ok = true;
1380
1381
1382 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1383 // Get the memory operand from the node
1384 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1385 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1386 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1387 uint opcnt = 1; // First operand
1388 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1389 while( idx >= skipped+num_edges ) {
1390 skipped += num_edges;
1391 opcnt++; // Bump operand count
1392 assert( opcnt < numopnds, "Accessing non-existent operand" );
1393 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1394 }
1395
1396 MachOper *memory = node->_opnds[opcnt];
1397 MachOper *new_memory = NULL;
1398 switch (memory->opcode()) {
1399 case DIRECT:
1400 case INDOFFSET32X:
1401 // No transformation necessary.
1402 return;
1403 case INDIRECT:
1404 new_memory = new indirect_win95_safeOper( );
1405 break;
1406 case INDOFFSET8:
1407 new_memory = new indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1408 break;
1409 case INDOFFSET32:
1410 new_memory = new indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1411 break;
1412 case INDINDEXOFFSET:
1413 new_memory = new indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1414 break;
1415 case INDINDEXSCALE:
1416 new_memory = new indIndexScale_win95_safeOper(memory->scale());
1417 break;
1418 case INDINDEXSCALEOFFSET:
1419 new_memory = new indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1420 break;
1421 case LOAD_LONG_INDIRECT:
1422 case LOAD_LONG_INDOFFSET32:
1423 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1424 return;
1425 default:
1426 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1427 return;
1428 }
1429 node->_opnds[opcnt] = new_memory;
1430 }
1431
1432 // Advertise here if the CPU requires explicit rounding operations
1433 // to implement the UseStrictFP mode.
1434 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1435
1436 // Are floats conerted to double when stored to stack during deoptimization?
1437 // On x32 it is stored with convertion only when FPU is used for floats.
1438 bool Matcher::float_in_double() { return (UseSSE == 0); }
1439
1440 // Do ints take an entire long register or just half?
1441 const bool Matcher::int_in_long = false;
1442
1443 // Return whether or not this register is ever used as an argument. This
1444 // function is used on startup to build the trampoline stubs in generateOptoStub.
1445 // Registers not mentioned will be killed by the VM call in the trampoline, and
1446 // arguments in those registers not be available to the callee.
1447 bool Matcher::can_be_java_arg( int reg ) {
1448 if( reg == ECX_num || reg == EDX_num ) return true;
1449 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1450 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1451 return false;
1452 }
1453
1454 bool Matcher::is_spillable_arg( int reg ) {
1455 return can_be_java_arg(reg);
1456 }
1457
1458 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1459 // Use hardware integer DIV instruction when
1460 // it is faster than a code which use multiply.
1461 // Only when constant divisor fits into 32 bit
1462 // (min_jint is excluded to get only correct
1463 // positive 32 bit values from negative).
1464 return VM_Version::has_fast_idiv() &&
1465 (divisor == (int)divisor && divisor != min_jint);
1466 }
1467
1468 // Register for DIVI projection of divmodI
1469 RegMask Matcher::divI_proj_mask() {
1470 return EAX_REG_mask();
1471 }
1472
1473 // Register for MODI projection of divmodI
1474 RegMask Matcher::modI_proj_mask() {
1475 return EDX_REG_mask();
1476 }
1477
1478 // Register for DIVL projection of divmodL
1479 RegMask Matcher::divL_proj_mask() {
1480 ShouldNotReachHere();
1481 return RegMask();
1482 }
1483
1484 // Register for MODL projection of divmodL
1485 RegMask Matcher::modL_proj_mask() {
1486 ShouldNotReachHere();
1487 return RegMask();
1488 }
1489
1490 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1491 return EBP_REG_mask();
1492 }
1493
1494 // Returns true if the high 32 bits of the value is known to be zero.
1495 bool is_operand_hi32_zero(Node* n) {
1496 int opc = n->Opcode();
1497 if (opc == Op_AndL) {
1498 Node* o2 = n->in(2);
1499 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1500 return true;
1501 }
1502 }
1503 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1504 return true;
1505 }
1506 return false;
1507 }
1508
1509 %}
1510
1511 //----------ENCODING BLOCK-----------------------------------------------------
1512 // This block specifies the encoding classes used by the compiler to output
1513 // byte streams. Encoding classes generate functions which are called by
1514 // Machine Instruction Nodes in order to generate the bit encoding of the
1515 // instruction. Operands specify their base encoding interface with the
1516 // interface keyword. There are currently supported four interfaces,
1517 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1518 // operand to generate a function which returns its register number when
1519 // queried. CONST_INTER causes an operand to generate a function which
1520 // returns the value of the constant when queried. MEMORY_INTER causes an
1521 // operand to generate four functions which return the Base Register, the
1522 // Index Register, the Scale Value, and the Offset Value of the operand when
1523 // queried. COND_INTER causes an operand to generate six functions which
1524 // return the encoding code (ie - encoding bits for the instruction)
1525 // associated with each basic boolean condition for a conditional instruction.
1526 // Instructions specify two basic values for encoding. They use the
1527 // ins_encode keyword to specify their encoding class (which must be one of
1528 // the class names specified in the encoding block), and they use the
1529 // opcode keyword to specify, in order, their primary, secondary, and
1530 // tertiary opcode. Only the opcode sections which a particular instruction
1531 // needs for encoding need to be specified.
1532 encode %{
1533 // Build emit functions for each basic byte or larger field in the intel
1534 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1535 // code in the enc_class source block. Emit functions will live in the
1536 // main source block for now. In future, we can generalize this by
1537 // adding a syntax that specifies the sizes of fields in an order,
1538 // so that the adlc can build the emit functions automagically
1539
1540 // Emit primary opcode
1541 enc_class OpcP %{
1542 emit_opcode(cbuf, $primary);
1543 %}
1544
1545 // Emit secondary opcode
1546 enc_class OpcS %{
1547 emit_opcode(cbuf, $secondary);
1548 %}
1549
1550 // Emit opcode directly
1551 enc_class Opcode(immI d8) %{
1552 emit_opcode(cbuf, $d8$$constant);
1553 %}
1554
1555 enc_class SizePrefix %{
1556 emit_opcode(cbuf,0x66);
1557 %}
1558
1559 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1560 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1561 %}
1562
1563 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1564 emit_opcode(cbuf,$opcode$$constant);
1565 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1566 %}
1567
1568 enc_class mov_r32_imm0( rRegI dst ) %{
1569 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1570 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1571 %}
1572
1573 enc_class cdq_enc %{
1574 // Full implementation of Java idiv and irem; checks for
1575 // special case as described in JVM spec., p.243 & p.271.
1576 //
1577 // normal case special case
1578 //
1579 // input : rax,: dividend min_int
1580 // reg: divisor -1
1581 //
1582 // output: rax,: quotient (= rax, idiv reg) min_int
1583 // rdx: remainder (= rax, irem reg) 0
1584 //
1585 // Code sequnce:
1586 //
1587 // 81 F8 00 00 00 80 cmp rax,80000000h
1588 // 0F 85 0B 00 00 00 jne normal_case
1589 // 33 D2 xor rdx,edx
1590 // 83 F9 FF cmp rcx,0FFh
1591 // 0F 84 03 00 00 00 je done
1592 // normal_case:
1593 // 99 cdq
1594 // F7 F9 idiv rax,ecx
1595 // done:
1596 //
1597 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1598 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1599 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1600 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1601 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1602 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1603 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1604 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1605 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1606 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1607 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1608 // normal_case:
1609 emit_opcode(cbuf,0x99); // cdq
1610 // idiv (note: must be emitted by the user of this rule)
1611 // normal:
1612 %}
1613
1614 // Dense encoding for older common ops
1615 enc_class Opc_plus(immI opcode, rRegI reg) %{
1616 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1617 %}
1618
1619
1620 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1621 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1622 // Check for 8-bit immediate, and set sign extend bit in opcode
1623 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1624 emit_opcode(cbuf, $primary | 0x02);
1625 }
1626 else { // If 32-bit immediate
1627 emit_opcode(cbuf, $primary);
1628 }
1629 %}
1630
1631 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1632 // Emit primary opcode and set sign-extend bit
1633 // Check for 8-bit immediate, and set sign extend bit in opcode
1634 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1635 emit_opcode(cbuf, $primary | 0x02); }
1636 else { // If 32-bit immediate
1637 emit_opcode(cbuf, $primary);
1638 }
1639 // Emit r/m byte with secondary opcode, after primary opcode.
1640 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1641 %}
1642
1643 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1644 // Check for 8-bit immediate, and set sign extend bit in opcode
1645 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1646 $$$emit8$imm$$constant;
1647 }
1648 else { // If 32-bit immediate
1649 // Output immediate
1650 $$$emit32$imm$$constant;
1651 }
1652 %}
1653
1654 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1655 // Emit primary opcode and set sign-extend bit
1656 // Check for 8-bit immediate, and set sign extend bit in opcode
1657 int con = (int)$imm$$constant; // Throw away top bits
1658 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1659 // Emit r/m byte with secondary opcode, after primary opcode.
1660 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1661 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1662 else emit_d32(cbuf,con);
1663 %}
1664
1665 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1666 // Emit primary opcode and set sign-extend bit
1667 // Check for 8-bit immediate, and set sign extend bit in opcode
1668 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1669 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1670 // Emit r/m byte with tertiary opcode, after primary opcode.
1671 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1672 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1673 else emit_d32(cbuf,con);
1674 %}
1675
1676 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1677 emit_cc(cbuf, $secondary, $dst$$reg );
1678 %}
1679
1680 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1681 int destlo = $dst$$reg;
1682 int desthi = HIGH_FROM_LOW(destlo);
1683 // bswap lo
1684 emit_opcode(cbuf, 0x0F);
1685 emit_cc(cbuf, 0xC8, destlo);
1686 // bswap hi
1687 emit_opcode(cbuf, 0x0F);
1688 emit_cc(cbuf, 0xC8, desthi);
1689 // xchg lo and hi
1690 emit_opcode(cbuf, 0x87);
1691 emit_rm(cbuf, 0x3, destlo, desthi);
1692 %}
1693
1694 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1695 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1696 %}
1697
1698 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1699 $$$emit8$primary;
1700 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1701 %}
1702
1703 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1704 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1705 emit_d8(cbuf, op >> 8 );
1706 emit_d8(cbuf, op & 255);
1707 %}
1708
1709 // emulate a CMOV with a conditional branch around a MOV
1710 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1711 // Invert sense of branch from sense of CMOV
1712 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1713 emit_d8( cbuf, $brOffs$$constant );
1714 %}
1715
1716 enc_class enc_PartialSubtypeCheck( ) %{
1717 Register Redi = as_Register(EDI_enc); // result register
1718 Register Reax = as_Register(EAX_enc); // super class
1719 Register Recx = as_Register(ECX_enc); // killed
1720 Register Resi = as_Register(ESI_enc); // sub class
1721 Label miss;
1722
1723 MacroAssembler _masm(&cbuf);
1724 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1725 NULL, &miss,
1726 /*set_cond_codes:*/ true);
1727 if ($primary) {
1728 __ xorptr(Redi, Redi);
1729 }
1730 __ bind(miss);
1731 %}
1732
1733 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1734 MacroAssembler masm(&cbuf);
1735 int start = masm.offset();
1736 if (UseSSE >= 2) {
1737 if (VerifyFPU) {
1738 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1739 }
1740 } else {
1741 // External c_calling_convention expects the FPU stack to be 'clean'.
1742 // Compiled code leaves it dirty. Do cleanup now.
1743 masm.empty_FPU_stack();
1744 }
1745 if (sizeof_FFree_Float_Stack_All == -1) {
1746 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1747 } else {
1748 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1749 }
1750 %}
1751
1752 enc_class Verify_FPU_For_Leaf %{
1753 if( VerifyFPU ) {
1754 MacroAssembler masm(&cbuf);
1755 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1756 }
1757 %}
1758
1759 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1760 // This is the instruction starting address for relocation info.
1761 cbuf.set_insts_mark();
1762 $$$emit8$primary;
1763 // CALL directly to the runtime
1764 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1765 runtime_call_Relocation::spec(), RELOC_IMM32 );
1766
1767 if (UseSSE >= 2) {
1768 MacroAssembler _masm(&cbuf);
1769 BasicType rt = tf()->return_type();
1770
1771 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1772 // A C runtime call where the return value is unused. In SSE2+
1773 // mode the result needs to be removed from the FPU stack. It's
1774 // likely that this function call could be removed by the
1775 // optimizer if the C function is a pure function.
1776 __ ffree(0);
1777 } else if (rt == T_FLOAT) {
1778 __ lea(rsp, Address(rsp, -4));
1779 __ fstp_s(Address(rsp, 0));
1780 __ movflt(xmm0, Address(rsp, 0));
1781 __ lea(rsp, Address(rsp, 4));
1782 } else if (rt == T_DOUBLE) {
1783 __ lea(rsp, Address(rsp, -8));
1784 __ fstp_d(Address(rsp, 0));
1785 __ movdbl(xmm0, Address(rsp, 0));
1786 __ lea(rsp, Address(rsp, 8));
1787 }
1788 }
1789 %}
1790
1791
1792 enc_class pre_call_resets %{
1793 // If method sets FPU control word restore it here
1794 debug_only(int off0 = cbuf.insts_size());
1795 if (ra_->C->in_24_bit_fp_mode()) {
1796 MacroAssembler _masm(&cbuf);
1797 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1798 }
1799 if (ra_->C->max_vector_size() > 16) {
1800 // Clear upper bits of YMM registers when current compiled code uses
1801 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1802 MacroAssembler _masm(&cbuf);
1803 __ vzeroupper();
1804 }
1805 debug_only(int off1 = cbuf.insts_size());
1806 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1807 %}
1808
1809 enc_class post_call_FPU %{
1810 // If method sets FPU control word do it here also
1811 if (Compile::current()->in_24_bit_fp_mode()) {
1812 MacroAssembler masm(&cbuf);
1813 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1814 }
1815 %}
1816
1817 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1818 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1819 // who we intended to call.
1820 cbuf.set_insts_mark();
1821 $$$emit8$primary;
1822 if (!_method) {
1823 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1824 runtime_call_Relocation::spec(), RELOC_IMM32 );
1825 } else if (_optimized_virtual) {
1826 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1827 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1828 } else {
1829 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1830 static_call_Relocation::spec(), RELOC_IMM32 );
1831 }
1832 if (_method) { // Emit stub for static call.
1833 CompiledStaticCall::emit_to_interp_stub(cbuf);
1834 }
1835 %}
1836
1837 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1838 MacroAssembler _masm(&cbuf);
1839 __ ic_call((address)$meth$$method);
1840 %}
1841
1842 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1843 int disp = in_bytes(Method::from_compiled_offset());
1844 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1845
1846 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1847 cbuf.set_insts_mark();
1848 $$$emit8$primary;
1849 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1850 emit_d8(cbuf, disp); // Displacement
1851
1852 %}
1853
1854 // Following encoding is no longer used, but may be restored if calling
1855 // convention changes significantly.
1856 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1857 //
1858 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1859 // // int ic_reg = Matcher::inline_cache_reg();
1860 // // int ic_encode = Matcher::_regEncode[ic_reg];
1861 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1862 // // int imo_encode = Matcher::_regEncode[imo_reg];
1863 //
1864 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1865 // // // so we load it immediately before the call
1866 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1867 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1868 //
1869 // // xor rbp,ebp
1870 // emit_opcode(cbuf, 0x33);
1871 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1872 //
1873 // // CALL to interpreter.
1874 // cbuf.set_insts_mark();
1875 // $$$emit8$primary;
1876 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1877 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1878 // %}
1879
1880 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1881 $$$emit8$primary;
1882 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1883 $$$emit8$shift$$constant;
1884 %}
1885
1886 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1887 // Load immediate does not have a zero or sign extended version
1888 // for 8-bit immediates
1889 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1890 $$$emit32$src$$constant;
1891 %}
1892
1893 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1894 // Load immediate does not have a zero or sign extended version
1895 // for 8-bit immediates
1896 emit_opcode(cbuf, $primary + $dst$$reg);
1897 $$$emit32$src$$constant;
1898 %}
1899
1900 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1901 // Load immediate does not have a zero or sign extended version
1902 // for 8-bit immediates
1903 int dst_enc = $dst$$reg;
1904 int src_con = $src$$constant & 0x0FFFFFFFFL;
1905 if (src_con == 0) {
1906 // xor dst, dst
1907 emit_opcode(cbuf, 0x33);
1908 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1909 } else {
1910 emit_opcode(cbuf, $primary + dst_enc);
1911 emit_d32(cbuf, src_con);
1912 }
1913 %}
1914
1915 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1916 // Load immediate does not have a zero or sign extended version
1917 // for 8-bit immediates
1918 int dst_enc = $dst$$reg + 2;
1919 int src_con = ((julong)($src$$constant)) >> 32;
1920 if (src_con == 0) {
1921 // xor dst, dst
1922 emit_opcode(cbuf, 0x33);
1923 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1924 } else {
1925 emit_opcode(cbuf, $primary + dst_enc);
1926 emit_d32(cbuf, src_con);
1927 }
1928 %}
1929
1930
1931 // Encode a reg-reg copy. If it is useless, then empty encoding.
1932 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1933 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1934 %}
1935
1936 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1937 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1938 %}
1939
1940 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1941 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1942 %}
1943
1944 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
1945 $$$emit8$primary;
1946 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1947 %}
1948
1949 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
1950 $$$emit8$secondary;
1951 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1952 %}
1953
1954 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
1955 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1956 %}
1957
1958 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
1959 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1960 %}
1961
1962 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
1963 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
1964 %}
1965
1966 enc_class Con32 (immI src) %{ // Con32(storeImmI)
1967 // Output immediate
1968 $$$emit32$src$$constant;
1969 %}
1970
1971 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
1972 // Output Float immediate bits
1973 jfloat jf = $src$$constant;
1974 int jf_as_bits = jint_cast( jf );
1975 emit_d32(cbuf, jf_as_bits);
1976 %}
1977
1978 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
1979 // Output Float immediate bits
1980 jfloat jf = $src$$constant;
1981 int jf_as_bits = jint_cast( jf );
1982 emit_d32(cbuf, jf_as_bits);
1983 %}
1984
1985 enc_class Con16 (immI src) %{ // Con16(storeImmI)
1986 // Output immediate
1987 $$$emit16$src$$constant;
1988 %}
1989
1990 enc_class Con_d32(immI src) %{
1991 emit_d32(cbuf,$src$$constant);
1992 %}
1993
1994 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
1995 // Output immediate memory reference
1996 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
1997 emit_d32(cbuf, 0x00);
1998 %}
1999
2000 enc_class lock_prefix( ) %{
2001 if( os::is_MP() )
2002 emit_opcode(cbuf,0xF0); // [Lock]
2003 %}
2004
2005 // Cmp-xchg long value.
2006 // Note: we need to swap rbx, and rcx before and after the
2007 // cmpxchg8 instruction because the instruction uses
2008 // rcx as the high order word of the new value to store but
2009 // our register encoding uses rbx,.
2010 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2011
2012 // XCHG rbx,ecx
2013 emit_opcode(cbuf,0x87);
2014 emit_opcode(cbuf,0xD9);
2015 // [Lock]
2016 if( os::is_MP() )
2017 emit_opcode(cbuf,0xF0);
2018 // CMPXCHG8 [Eptr]
2019 emit_opcode(cbuf,0x0F);
2020 emit_opcode(cbuf,0xC7);
2021 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2022 // XCHG rbx,ecx
2023 emit_opcode(cbuf,0x87);
2024 emit_opcode(cbuf,0xD9);
2025 %}
2026
2027 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2028 // [Lock]
2029 if( os::is_MP() )
2030 emit_opcode(cbuf,0xF0);
2031
2032 // CMPXCHG [Eptr]
2033 emit_opcode(cbuf,0x0F);
2034 emit_opcode(cbuf,0xB1);
2035 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2036 %}
2037
2038 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2039 int res_encoding = $res$$reg;
2040
2041 // MOV res,0
2042 emit_opcode( cbuf, 0xB8 + res_encoding);
2043 emit_d32( cbuf, 0 );
2044 // JNE,s fail
2045 emit_opcode(cbuf,0x75);
2046 emit_d8(cbuf, 5 );
2047 // MOV res,1
2048 emit_opcode( cbuf, 0xB8 + res_encoding);
2049 emit_d32( cbuf, 1 );
2050 // fail:
2051 %}
2052
2053 enc_class set_instruction_start( ) %{
2054 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2055 %}
2056
2057 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2058 int reg_encoding = $ereg$$reg;
2059 int base = $mem$$base;
2060 int index = $mem$$index;
2061 int scale = $mem$$scale;
2062 int displace = $mem$$disp;
2063 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2064 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2065 %}
2066
2067 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2068 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2069 int base = $mem$$base;
2070 int index = $mem$$index;
2071 int scale = $mem$$scale;
2072 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2073 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2074 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2075 %}
2076
2077 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2078 int r1, r2;
2079 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2080 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2081 emit_opcode(cbuf,0x0F);
2082 emit_opcode(cbuf,$tertiary);
2083 emit_rm(cbuf, 0x3, r1, r2);
2084 emit_d8(cbuf,$cnt$$constant);
2085 emit_d8(cbuf,$primary);
2086 emit_rm(cbuf, 0x3, $secondary, r1);
2087 emit_d8(cbuf,$cnt$$constant);
2088 %}
2089
2090 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2091 emit_opcode( cbuf, 0x8B ); // Move
2092 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2093 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2094 emit_d8(cbuf,$primary);
2095 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2096 emit_d8(cbuf,$cnt$$constant-32);
2097 }
2098 emit_d8(cbuf,$primary);
2099 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2100 emit_d8(cbuf,31);
2101 %}
2102
2103 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2104 int r1, r2;
2105 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2106 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2107
2108 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2109 emit_rm(cbuf, 0x3, r1, r2);
2110 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2111 emit_opcode(cbuf,$primary);
2112 emit_rm(cbuf, 0x3, $secondary, r1);
2113 emit_d8(cbuf,$cnt$$constant-32);
2114 }
2115 emit_opcode(cbuf,0x33); // XOR r2,r2
2116 emit_rm(cbuf, 0x3, r2, r2);
2117 %}
2118
2119 // Clone of RegMem but accepts an extra parameter to access each
2120 // half of a double in memory; it never needs relocation info.
2121 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2122 emit_opcode(cbuf,$opcode$$constant);
2123 int reg_encoding = $rm_reg$$reg;
2124 int base = $mem$$base;
2125 int index = $mem$$index;
2126 int scale = $mem$$scale;
2127 int displace = $mem$$disp + $disp_for_half$$constant;
2128 relocInfo::relocType disp_reloc = relocInfo::none;
2129 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2130 %}
2131
2132 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2133 //
2134 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2135 // and it never needs relocation information.
2136 // Frequently used to move data between FPU's Stack Top and memory.
2137 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2138 int rm_byte_opcode = $rm_opcode$$constant;
2139 int base = $mem$$base;
2140 int index = $mem$$index;
2141 int scale = $mem$$scale;
2142 int displace = $mem$$disp;
2143 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2144 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2145 %}
2146
2147 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2148 int rm_byte_opcode = $rm_opcode$$constant;
2149 int base = $mem$$base;
2150 int index = $mem$$index;
2151 int scale = $mem$$scale;
2152 int displace = $mem$$disp;
2153 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2154 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2155 %}
2156
2157 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2158 int reg_encoding = $dst$$reg;
2159 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2160 int index = 0x04; // 0x04 indicates no index
2161 int scale = 0x00; // 0x00 indicates no scale
2162 int displace = $src1$$constant; // 0x00 indicates no displacement
2163 relocInfo::relocType disp_reloc = relocInfo::none;
2164 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2165 %}
2166
2167 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2168 // Compare dst,src
2169 emit_opcode(cbuf,0x3B);
2170 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2171 // jmp dst < src around move
2172 emit_opcode(cbuf,0x7C);
2173 emit_d8(cbuf,2);
2174 // move dst,src
2175 emit_opcode(cbuf,0x8B);
2176 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2177 %}
2178
2179 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2180 // Compare dst,src
2181 emit_opcode(cbuf,0x3B);
2182 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2183 // jmp dst > src around move
2184 emit_opcode(cbuf,0x7F);
2185 emit_d8(cbuf,2);
2186 // move dst,src
2187 emit_opcode(cbuf,0x8B);
2188 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2189 %}
2190
2191 enc_class enc_FPR_store(memory mem, regDPR src) %{
2192 // If src is FPR1, we can just FST to store it.
2193 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2194 int reg_encoding = 0x2; // Just store
2195 int base = $mem$$base;
2196 int index = $mem$$index;
2197 int scale = $mem$$scale;
2198 int displace = $mem$$disp;
2199 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2200 if( $src$$reg != FPR1L_enc ) {
2201 reg_encoding = 0x3; // Store & pop
2202 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2203 emit_d8( cbuf, 0xC0-1+$src$$reg );
2204 }
2205 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2206 emit_opcode(cbuf,$primary);
2207 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2208 %}
2209
2210 enc_class neg_reg(rRegI dst) %{
2211 // NEG $dst
2212 emit_opcode(cbuf,0xF7);
2213 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2214 %}
2215
2216 enc_class setLT_reg(eCXRegI dst) %{
2217 // SETLT $dst
2218 emit_opcode(cbuf,0x0F);
2219 emit_opcode(cbuf,0x9C);
2220 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2221 %}
2222
2223 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2224 int tmpReg = $tmp$$reg;
2225
2226 // SUB $p,$q
2227 emit_opcode(cbuf,0x2B);
2228 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2229 // SBB $tmp,$tmp
2230 emit_opcode(cbuf,0x1B);
2231 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2232 // AND $tmp,$y
2233 emit_opcode(cbuf,0x23);
2234 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2235 // ADD $p,$tmp
2236 emit_opcode(cbuf,0x03);
2237 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2238 %}
2239
2240 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2241 // TEST shift,32
2242 emit_opcode(cbuf,0xF7);
2243 emit_rm(cbuf, 0x3, 0, ECX_enc);
2244 emit_d32(cbuf,0x20);
2245 // JEQ,s small
2246 emit_opcode(cbuf, 0x74);
2247 emit_d8(cbuf, 0x04);
2248 // MOV $dst.hi,$dst.lo
2249 emit_opcode( cbuf, 0x8B );
2250 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2251 // CLR $dst.lo
2252 emit_opcode(cbuf, 0x33);
2253 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2254 // small:
2255 // SHLD $dst.hi,$dst.lo,$shift
2256 emit_opcode(cbuf,0x0F);
2257 emit_opcode(cbuf,0xA5);
2258 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2259 // SHL $dst.lo,$shift"
2260 emit_opcode(cbuf,0xD3);
2261 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2262 %}
2263
2264 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2265 // TEST shift,32
2266 emit_opcode(cbuf,0xF7);
2267 emit_rm(cbuf, 0x3, 0, ECX_enc);
2268 emit_d32(cbuf,0x20);
2269 // JEQ,s small
2270 emit_opcode(cbuf, 0x74);
2271 emit_d8(cbuf, 0x04);
2272 // MOV $dst.lo,$dst.hi
2273 emit_opcode( cbuf, 0x8B );
2274 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2275 // CLR $dst.hi
2276 emit_opcode(cbuf, 0x33);
2277 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2278 // small:
2279 // SHRD $dst.lo,$dst.hi,$shift
2280 emit_opcode(cbuf,0x0F);
2281 emit_opcode(cbuf,0xAD);
2282 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2283 // SHR $dst.hi,$shift"
2284 emit_opcode(cbuf,0xD3);
2285 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2286 %}
2287
2288 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2289 // TEST shift,32
2290 emit_opcode(cbuf,0xF7);
2291 emit_rm(cbuf, 0x3, 0, ECX_enc);
2292 emit_d32(cbuf,0x20);
2293 // JEQ,s small
2294 emit_opcode(cbuf, 0x74);
2295 emit_d8(cbuf, 0x05);
2296 // MOV $dst.lo,$dst.hi
2297 emit_opcode( cbuf, 0x8B );
2298 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2299 // SAR $dst.hi,31
2300 emit_opcode(cbuf, 0xC1);
2301 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2302 emit_d8(cbuf, 0x1F );
2303 // small:
2304 // SHRD $dst.lo,$dst.hi,$shift
2305 emit_opcode(cbuf,0x0F);
2306 emit_opcode(cbuf,0xAD);
2307 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2308 // SAR $dst.hi,$shift"
2309 emit_opcode(cbuf,0xD3);
2310 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2311 %}
2312
2313
2314 // ----------------- Encodings for floating point unit -----------------
2315 // May leave result in FPU-TOS or FPU reg depending on opcodes
2316 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2317 $$$emit8$primary;
2318 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2319 %}
2320
2321 // Pop argument in FPR0 with FSTP ST(0)
2322 enc_class PopFPU() %{
2323 emit_opcode( cbuf, 0xDD );
2324 emit_d8( cbuf, 0xD8 );
2325 %}
2326
2327 // !!!!! equivalent to Pop_Reg_F
2328 enc_class Pop_Reg_DPR( regDPR dst ) %{
2329 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2330 emit_d8( cbuf, 0xD8+$dst$$reg );
2331 %}
2332
2333 enc_class Push_Reg_DPR( regDPR dst ) %{
2334 emit_opcode( cbuf, 0xD9 );
2335 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2336 %}
2337
2338 enc_class strictfp_bias1( regDPR dst ) %{
2339 emit_opcode( cbuf, 0xDB ); // FLD m80real
2340 emit_opcode( cbuf, 0x2D );
2341 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2342 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2343 emit_opcode( cbuf, 0xC8+$dst$$reg );
2344 %}
2345
2346 enc_class strictfp_bias2( regDPR dst ) %{
2347 emit_opcode( cbuf, 0xDB ); // FLD m80real
2348 emit_opcode( cbuf, 0x2D );
2349 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2350 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2351 emit_opcode( cbuf, 0xC8+$dst$$reg );
2352 %}
2353
2354 // Special case for moving an integer register to a stack slot.
2355 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2356 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2357 %}
2358
2359 // Special case for moving a register to a stack slot.
2360 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2361 // Opcode already emitted
2362 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2363 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2364 emit_d32(cbuf, $dst$$disp); // Displacement
2365 %}
2366
2367 // Push the integer in stackSlot 'src' onto FP-stack
2368 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2369 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2370 %}
2371
2372 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2373 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2374 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2375 %}
2376
2377 // Same as Pop_Mem_F except for opcode
2378 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2379 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2380 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2381 %}
2382
2383 enc_class Pop_Reg_FPR( regFPR dst ) %{
2384 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2385 emit_d8( cbuf, 0xD8+$dst$$reg );
2386 %}
2387
2388 enc_class Push_Reg_FPR( regFPR dst ) %{
2389 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2390 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2391 %}
2392
2393 // Push FPU's float to a stack-slot, and pop FPU-stack
2394 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2395 int pop = 0x02;
2396 if ($src$$reg != FPR1L_enc) {
2397 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2398 emit_d8( cbuf, 0xC0-1+$src$$reg );
2399 pop = 0x03;
2400 }
2401 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2402 %}
2403
2404 // Push FPU's double to a stack-slot, and pop FPU-stack
2405 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2406 int pop = 0x02;
2407 if ($src$$reg != FPR1L_enc) {
2408 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2409 emit_d8( cbuf, 0xC0-1+$src$$reg );
2410 pop = 0x03;
2411 }
2412 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2413 %}
2414
2415 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2416 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2417 int pop = 0xD0 - 1; // -1 since we skip FLD
2418 if ($src$$reg != FPR1L_enc) {
2419 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2420 emit_d8( cbuf, 0xC0-1+$src$$reg );
2421 pop = 0xD8;
2422 }
2423 emit_opcode( cbuf, 0xDD );
2424 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2425 %}
2426
2427
2428 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2429 // load dst in FPR0
2430 emit_opcode( cbuf, 0xD9 );
2431 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2432 if ($src$$reg != FPR1L_enc) {
2433 // fincstp
2434 emit_opcode (cbuf, 0xD9);
2435 emit_opcode (cbuf, 0xF7);
2436 // swap src with FPR1:
2437 // FXCH FPR1 with src
2438 emit_opcode(cbuf, 0xD9);
2439 emit_d8(cbuf, 0xC8-1+$src$$reg );
2440 // fdecstp
2441 emit_opcode (cbuf, 0xD9);
2442 emit_opcode (cbuf, 0xF6);
2443 }
2444 %}
2445
2446 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2447 MacroAssembler _masm(&cbuf);
2448 __ subptr(rsp, 8);
2449 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2450 __ fld_d(Address(rsp, 0));
2451 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2452 __ fld_d(Address(rsp, 0));
2453 %}
2454
2455 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2456 MacroAssembler _masm(&cbuf);
2457 __ subptr(rsp, 4);
2458 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2459 __ fld_s(Address(rsp, 0));
2460 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2461 __ fld_s(Address(rsp, 0));
2462 %}
2463
2464 enc_class Push_ResultD(regD dst) %{
2465 MacroAssembler _masm(&cbuf);
2466 __ fstp_d(Address(rsp, 0));
2467 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2468 __ addptr(rsp, 8);
2469 %}
2470
2471 enc_class Push_ResultF(regF dst, immI d8) %{
2472 MacroAssembler _masm(&cbuf);
2473 __ fstp_s(Address(rsp, 0));
2474 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2475 __ addptr(rsp, $d8$$constant);
2476 %}
2477
2478 enc_class Push_SrcD(regD src) %{
2479 MacroAssembler _masm(&cbuf);
2480 __ subptr(rsp, 8);
2481 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2482 __ fld_d(Address(rsp, 0));
2483 %}
2484
2485 enc_class push_stack_temp_qword() %{
2486 MacroAssembler _masm(&cbuf);
2487 __ subptr(rsp, 8);
2488 %}
2489
2490 enc_class pop_stack_temp_qword() %{
2491 MacroAssembler _masm(&cbuf);
2492 __ addptr(rsp, 8);
2493 %}
2494
2495 enc_class push_xmm_to_fpr1(regD src) %{
2496 MacroAssembler _masm(&cbuf);
2497 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2498 __ fld_d(Address(rsp, 0));
2499 %}
2500
2501 enc_class Push_Result_Mod_DPR( regDPR src) %{
2502 if ($src$$reg != FPR1L_enc) {
2503 // fincstp
2504 emit_opcode (cbuf, 0xD9);
2505 emit_opcode (cbuf, 0xF7);
2506 // FXCH FPR1 with src
2507 emit_opcode(cbuf, 0xD9);
2508 emit_d8(cbuf, 0xC8-1+$src$$reg );
2509 // fdecstp
2510 emit_opcode (cbuf, 0xD9);
2511 emit_opcode (cbuf, 0xF6);
2512 }
2513 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2514 // // FSTP FPR$dst$$reg
2515 // emit_opcode( cbuf, 0xDD );
2516 // emit_d8( cbuf, 0xD8+$dst$$reg );
2517 %}
2518
2519 enc_class fnstsw_sahf_skip_parity() %{
2520 // fnstsw ax
2521 emit_opcode( cbuf, 0xDF );
2522 emit_opcode( cbuf, 0xE0 );
2523 // sahf
2524 emit_opcode( cbuf, 0x9E );
2525 // jnp ::skip
2526 emit_opcode( cbuf, 0x7B );
2527 emit_opcode( cbuf, 0x05 );
2528 %}
2529
2530 enc_class emitModDPR() %{
2531 // fprem must be iterative
2532 // :: loop
2533 // fprem
2534 emit_opcode( cbuf, 0xD9 );
2535 emit_opcode( cbuf, 0xF8 );
2536 // wait
2537 emit_opcode( cbuf, 0x9b );
2538 // fnstsw ax
2539 emit_opcode( cbuf, 0xDF );
2540 emit_opcode( cbuf, 0xE0 );
2541 // sahf
2542 emit_opcode( cbuf, 0x9E );
2543 // jp ::loop
2544 emit_opcode( cbuf, 0x0F );
2545 emit_opcode( cbuf, 0x8A );
2546 emit_opcode( cbuf, 0xF4 );
2547 emit_opcode( cbuf, 0xFF );
2548 emit_opcode( cbuf, 0xFF );
2549 emit_opcode( cbuf, 0xFF );
2550 %}
2551
2552 enc_class fpu_flags() %{
2553 // fnstsw_ax
2554 emit_opcode( cbuf, 0xDF);
2555 emit_opcode( cbuf, 0xE0);
2556 // test ax,0x0400
2557 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2558 emit_opcode( cbuf, 0xA9 );
2559 emit_d16 ( cbuf, 0x0400 );
2560 // // // This sequence works, but stalls for 12-16 cycles on PPro
2561 // // test rax,0x0400
2562 // emit_opcode( cbuf, 0xA9 );
2563 // emit_d32 ( cbuf, 0x00000400 );
2564 //
2565 // jz exit (no unordered comparison)
2566 emit_opcode( cbuf, 0x74 );
2567 emit_d8 ( cbuf, 0x02 );
2568 // mov ah,1 - treat as LT case (set carry flag)
2569 emit_opcode( cbuf, 0xB4 );
2570 emit_d8 ( cbuf, 0x01 );
2571 // sahf
2572 emit_opcode( cbuf, 0x9E);
2573 %}
2574
2575 enc_class cmpF_P6_fixup() %{
2576 // Fixup the integer flags in case comparison involved a NaN
2577 //
2578 // JNP exit (no unordered comparison, P-flag is set by NaN)
2579 emit_opcode( cbuf, 0x7B );
2580 emit_d8 ( cbuf, 0x03 );
2581 // MOV AH,1 - treat as LT case (set carry flag)
2582 emit_opcode( cbuf, 0xB4 );
2583 emit_d8 ( cbuf, 0x01 );
2584 // SAHF
2585 emit_opcode( cbuf, 0x9E);
2586 // NOP // target for branch to avoid branch to branch
2587 emit_opcode( cbuf, 0x90);
2588 %}
2589
2590 // fnstsw_ax();
2591 // sahf();
2592 // movl(dst, nan_result);
2593 // jcc(Assembler::parity, exit);
2594 // movl(dst, less_result);
2595 // jcc(Assembler::below, exit);
2596 // movl(dst, equal_result);
2597 // jcc(Assembler::equal, exit);
2598 // movl(dst, greater_result);
2599
2600 // less_result = 1;
2601 // greater_result = -1;
2602 // equal_result = 0;
2603 // nan_result = -1;
2604
2605 enc_class CmpF_Result(rRegI dst) %{
2606 // fnstsw_ax();
2607 emit_opcode( cbuf, 0xDF);
2608 emit_opcode( cbuf, 0xE0);
2609 // sahf
2610 emit_opcode( cbuf, 0x9E);
2611 // movl(dst, nan_result);
2612 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2613 emit_d32( cbuf, -1 );
2614 // jcc(Assembler::parity, exit);
2615 emit_opcode( cbuf, 0x7A );
2616 emit_d8 ( cbuf, 0x13 );
2617 // movl(dst, less_result);
2618 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2619 emit_d32( cbuf, -1 );
2620 // jcc(Assembler::below, exit);
2621 emit_opcode( cbuf, 0x72 );
2622 emit_d8 ( cbuf, 0x0C );
2623 // movl(dst, equal_result);
2624 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2625 emit_d32( cbuf, 0 );
2626 // jcc(Assembler::equal, exit);
2627 emit_opcode( cbuf, 0x74 );
2628 emit_d8 ( cbuf, 0x05 );
2629 // movl(dst, greater_result);
2630 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2631 emit_d32( cbuf, 1 );
2632 %}
2633
2634
2635 // Compare the longs and set flags
2636 // BROKEN! Do Not use as-is
2637 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2638 // CMP $src1.hi,$src2.hi
2639 emit_opcode( cbuf, 0x3B );
2640 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2641 // JNE,s done
2642 emit_opcode(cbuf,0x75);
2643 emit_d8(cbuf, 2 );
2644 // CMP $src1.lo,$src2.lo
2645 emit_opcode( cbuf, 0x3B );
2646 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2647 // done:
2648 %}
2649
2650 enc_class convert_int_long( regL dst, rRegI src ) %{
2651 // mov $dst.lo,$src
2652 int dst_encoding = $dst$$reg;
2653 int src_encoding = $src$$reg;
2654 encode_Copy( cbuf, dst_encoding , src_encoding );
2655 // mov $dst.hi,$src
2656 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2657 // sar $dst.hi,31
2658 emit_opcode( cbuf, 0xC1 );
2659 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2660 emit_d8(cbuf, 0x1F );
2661 %}
2662
2663 enc_class convert_long_double( eRegL src ) %{
2664 // push $src.hi
2665 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2666 // push $src.lo
2667 emit_opcode(cbuf, 0x50+$src$$reg );
2668 // fild 64-bits at [SP]
2669 emit_opcode(cbuf,0xdf);
2670 emit_d8(cbuf, 0x6C);
2671 emit_d8(cbuf, 0x24);
2672 emit_d8(cbuf, 0x00);
2673 // pop stack
2674 emit_opcode(cbuf, 0x83); // add SP, #8
2675 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2676 emit_d8(cbuf, 0x8);
2677 %}
2678
2679 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2680 // IMUL EDX:EAX,$src1
2681 emit_opcode( cbuf, 0xF7 );
2682 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2683 // SAR EDX,$cnt-32
2684 int shift_count = ((int)$cnt$$constant) - 32;
2685 if (shift_count > 0) {
2686 emit_opcode(cbuf, 0xC1);
2687 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2688 emit_d8(cbuf, shift_count);
2689 }
2690 %}
2691
2692 // this version doesn't have add sp, 8
2693 enc_class convert_long_double2( eRegL src ) %{
2694 // push $src.hi
2695 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2696 // push $src.lo
2697 emit_opcode(cbuf, 0x50+$src$$reg );
2698 // fild 64-bits at [SP]
2699 emit_opcode(cbuf,0xdf);
2700 emit_d8(cbuf, 0x6C);
2701 emit_d8(cbuf, 0x24);
2702 emit_d8(cbuf, 0x00);
2703 %}
2704
2705 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2706 // Basic idea: long = (long)int * (long)int
2707 // IMUL EDX:EAX, src
2708 emit_opcode( cbuf, 0xF7 );
2709 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2710 %}
2711
2712 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2713 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2714 // MUL EDX:EAX, src
2715 emit_opcode( cbuf, 0xF7 );
2716 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2717 %}
2718
2719 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2720 // Basic idea: lo(result) = lo(x_lo * y_lo)
2721 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2722 // MOV $tmp,$src.lo
2723 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2724 // IMUL $tmp,EDX
2725 emit_opcode( cbuf, 0x0F );
2726 emit_opcode( cbuf, 0xAF );
2727 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2728 // MOV EDX,$src.hi
2729 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2730 // IMUL EDX,EAX
2731 emit_opcode( cbuf, 0x0F );
2732 emit_opcode( cbuf, 0xAF );
2733 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2734 // ADD $tmp,EDX
2735 emit_opcode( cbuf, 0x03 );
2736 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2737 // MUL EDX:EAX,$src.lo
2738 emit_opcode( cbuf, 0xF7 );
2739 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2740 // ADD EDX,ESI
2741 emit_opcode( cbuf, 0x03 );
2742 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2743 %}
2744
2745 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2746 // Basic idea: lo(result) = lo(src * y_lo)
2747 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2748 // IMUL $tmp,EDX,$src
2749 emit_opcode( cbuf, 0x6B );
2750 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2751 emit_d8( cbuf, (int)$src$$constant );
2752 // MOV EDX,$src
2753 emit_opcode(cbuf, 0xB8 + EDX_enc);
2754 emit_d32( cbuf, (int)$src$$constant );
2755 // MUL EDX:EAX,EDX
2756 emit_opcode( cbuf, 0xF7 );
2757 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2758 // ADD EDX,ESI
2759 emit_opcode( cbuf, 0x03 );
2760 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2761 %}
2762
2763 enc_class long_div( eRegL src1, eRegL src2 ) %{
2764 // PUSH src1.hi
2765 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2766 // PUSH src1.lo
2767 emit_opcode(cbuf, 0x50+$src1$$reg );
2768 // PUSH src2.hi
2769 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2770 // PUSH src2.lo
2771 emit_opcode(cbuf, 0x50+$src2$$reg );
2772 // CALL directly to the runtime
2773 cbuf.set_insts_mark();
2774 emit_opcode(cbuf,0xE8); // Call into runtime
2775 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2776 // Restore stack
2777 emit_opcode(cbuf, 0x83); // add SP, #framesize
2778 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2779 emit_d8(cbuf, 4*4);
2780 %}
2781
2782 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2783 // PUSH src1.hi
2784 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2785 // PUSH src1.lo
2786 emit_opcode(cbuf, 0x50+$src1$$reg );
2787 // PUSH src2.hi
2788 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2789 // PUSH src2.lo
2790 emit_opcode(cbuf, 0x50+$src2$$reg );
2791 // CALL directly to the runtime
2792 cbuf.set_insts_mark();
2793 emit_opcode(cbuf,0xE8); // Call into runtime
2794 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2795 // Restore stack
2796 emit_opcode(cbuf, 0x83); // add SP, #framesize
2797 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2798 emit_d8(cbuf, 4*4);
2799 %}
2800
2801 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2802 // MOV $tmp,$src.lo
2803 emit_opcode(cbuf, 0x8B);
2804 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2805 // OR $tmp,$src.hi
2806 emit_opcode(cbuf, 0x0B);
2807 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2808 %}
2809
2810 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2811 // CMP $src1.lo,$src2.lo
2812 emit_opcode( cbuf, 0x3B );
2813 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2814 // JNE,s skip
2815 emit_cc(cbuf, 0x70, 0x5);
2816 emit_d8(cbuf,2);
2817 // CMP $src1.hi,$src2.hi
2818 emit_opcode( cbuf, 0x3B );
2819 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2820 %}
2821
2822 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2823 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2824 emit_opcode( cbuf, 0x3B );
2825 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2826 // MOV $tmp,$src1.hi
2827 emit_opcode( cbuf, 0x8B );
2828 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2829 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2830 emit_opcode( cbuf, 0x1B );
2831 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2832 %}
2833
2834 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2835 // XOR $tmp,$tmp
2836 emit_opcode(cbuf,0x33); // XOR
2837 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2838 // CMP $tmp,$src.lo
2839 emit_opcode( cbuf, 0x3B );
2840 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2841 // SBB $tmp,$src.hi
2842 emit_opcode( cbuf, 0x1B );
2843 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2844 %}
2845
2846 // Sniff, sniff... smells like Gnu Superoptimizer
2847 enc_class neg_long( eRegL dst ) %{
2848 emit_opcode(cbuf,0xF7); // NEG hi
2849 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2850 emit_opcode(cbuf,0xF7); // NEG lo
2851 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2852 emit_opcode(cbuf,0x83); // SBB hi,0
2853 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2854 emit_d8 (cbuf,0 );
2855 %}
2856
2857 enc_class enc_pop_rdx() %{
2858 emit_opcode(cbuf,0x5A);
2859 %}
2860
2861 enc_class enc_rethrow() %{
2862 cbuf.set_insts_mark();
2863 emit_opcode(cbuf, 0xE9); // jmp entry
2864 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
2865 runtime_call_Relocation::spec(), RELOC_IMM32 );
2866 %}
2867
2868
2869 // Convert a double to an int. Java semantics require we do complex
2870 // manglelations in the corner cases. So we set the rounding mode to
2871 // 'zero', store the darned double down as an int, and reset the
2872 // rounding mode to 'nearest'. The hardware throws an exception which
2873 // patches up the correct value directly to the stack.
2874 enc_class DPR2I_encoding( regDPR src ) %{
2875 // Flip to round-to-zero mode. We attempted to allow invalid-op
2876 // exceptions here, so that a NAN or other corner-case value will
2877 // thrown an exception (but normal values get converted at full speed).
2878 // However, I2C adapters and other float-stack manglers leave pending
2879 // invalid-op exceptions hanging. We would have to clear them before
2880 // enabling them and that is more expensive than just testing for the
2881 // invalid value Intel stores down in the corner cases.
2882 emit_opcode(cbuf,0xD9); // FLDCW trunc
2883 emit_opcode(cbuf,0x2D);
2884 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
2885 // Allocate a word
2886 emit_opcode(cbuf,0x83); // SUB ESP,4
2887 emit_opcode(cbuf,0xEC);
2888 emit_d8(cbuf,0x04);
2889 // Encoding assumes a double has been pushed into FPR0.
2890 // Store down the double as an int, popping the FPU stack
2891 emit_opcode(cbuf,0xDB); // FISTP [ESP]
2892 emit_opcode(cbuf,0x1C);
2893 emit_d8(cbuf,0x24);
2894 // Restore the rounding mode; mask the exception
2895 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
2896 emit_opcode(cbuf,0x2D);
2897 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
2898 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
2899 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
2900
2901 // Load the converted int; adjust CPU stack
2902 emit_opcode(cbuf,0x58); // POP EAX
2903 emit_opcode(cbuf,0x3D); // CMP EAX,imm
2904 emit_d32 (cbuf,0x80000000); // 0x80000000
2905 emit_opcode(cbuf,0x75); // JNE around_slow_call
2906 emit_d8 (cbuf,0x07); // Size of slow_call
2907 // Push src onto stack slow-path
2908 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
2909 emit_d8 (cbuf,0xC0-1+$src$$reg );
2910 // CALL directly to the runtime
2911 cbuf.set_insts_mark();
2912 emit_opcode(cbuf,0xE8); // Call into runtime
2913 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2914 // Carry on here...
2915 %}
2916
2917 enc_class DPR2L_encoding( regDPR src ) %{
2918 emit_opcode(cbuf,0xD9); // FLDCW trunc
2919 emit_opcode(cbuf,0x2D);
2920 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
2921 // Allocate a word
2922 emit_opcode(cbuf,0x83); // SUB ESP,8
2923 emit_opcode(cbuf,0xEC);
2924 emit_d8(cbuf,0x08);
2925 // Encoding assumes a double has been pushed into FPR0.
2926 // Store down the double as a long, popping the FPU stack
2927 emit_opcode(cbuf,0xDF); // FISTP [ESP]
2928 emit_opcode(cbuf,0x3C);
2929 emit_d8(cbuf,0x24);
2930 // Restore the rounding mode; mask the exception
2931 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
2932 emit_opcode(cbuf,0x2D);
2933 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
2934 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
2935 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
2936
2937 // Load the converted int; adjust CPU stack
2938 emit_opcode(cbuf,0x58); // POP EAX
2939 emit_opcode(cbuf,0x5A); // POP EDX
2940 emit_opcode(cbuf,0x81); // CMP EDX,imm
2941 emit_d8 (cbuf,0xFA); // rdx
2942 emit_d32 (cbuf,0x80000000); // 0x80000000
2943 emit_opcode(cbuf,0x75); // JNE around_slow_call
2944 emit_d8 (cbuf,0x07+4); // Size of slow_call
2945 emit_opcode(cbuf,0x85); // TEST EAX,EAX
2946 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
2947 emit_opcode(cbuf,0x75); // JNE around_slow_call
2948 emit_d8 (cbuf,0x07); // Size of slow_call
2949 // Push src onto stack slow-path
2950 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
2951 emit_d8 (cbuf,0xC0-1+$src$$reg );
2952 // CALL directly to the runtime
2953 cbuf.set_insts_mark();
2954 emit_opcode(cbuf,0xE8); // Call into runtime
2955 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2956 // Carry on here...
2957 %}
2958
2959 enc_class FMul_ST_reg( eRegFPR src1 ) %{
2960 // Operand was loaded from memory into fp ST (stack top)
2961 // FMUL ST,$src /* D8 C8+i */
2962 emit_opcode(cbuf, 0xD8);
2963 emit_opcode(cbuf, 0xC8 + $src1$$reg);
2964 %}
2965
2966 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
2967 // FADDP ST,src2 /* D8 C0+i */
2968 emit_opcode(cbuf, 0xD8);
2969 emit_opcode(cbuf, 0xC0 + $src2$$reg);
2970 //could use FADDP src2,fpST /* DE C0+i */
2971 %}
2972
2973 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
2974 // FADDP src2,ST /* DE C0+i */
2975 emit_opcode(cbuf, 0xDE);
2976 emit_opcode(cbuf, 0xC0 + $src2$$reg);
2977 %}
2978
2979 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
2980 // Operand has been loaded into fp ST (stack top)
2981 // FSUB ST,$src1
2982 emit_opcode(cbuf, 0xD8);
2983 emit_opcode(cbuf, 0xE0 + $src1$$reg);
2984
2985 // FDIV
2986 emit_opcode(cbuf, 0xD8);
2987 emit_opcode(cbuf, 0xF0 + $src2$$reg);
2988 %}
2989
2990 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
2991 // Operand was loaded from memory into fp ST (stack top)
2992 // FADD ST,$src /* D8 C0+i */
2993 emit_opcode(cbuf, 0xD8);
2994 emit_opcode(cbuf, 0xC0 + $src1$$reg);
2995
2996 // FMUL ST,src2 /* D8 C*+i */
2997 emit_opcode(cbuf, 0xD8);
2998 emit_opcode(cbuf, 0xC8 + $src2$$reg);
2999 %}
3000
3001
3002 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3003 // Operand was loaded from memory into fp ST (stack top)
3004 // FADD ST,$src /* D8 C0+i */
3005 emit_opcode(cbuf, 0xD8);
3006 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3007
3008 // FMULP src2,ST /* DE C8+i */
3009 emit_opcode(cbuf, 0xDE);
3010 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3011 %}
3012
3013 // Atomically load the volatile long
3014 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3015 emit_opcode(cbuf,0xDF);
3016 int rm_byte_opcode = 0x05;
3017 int base = $mem$$base;
3018 int index = $mem$$index;
3019 int scale = $mem$$scale;
3020 int displace = $mem$$disp;
3021 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3022 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3023 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3024 %}
3025
3026 // Volatile Store Long. Must be atomic, so move it into
3027 // the FP TOS and then do a 64-bit FIST. Has to probe the
3028 // target address before the store (for null-ptr checks)
3029 // so the memory operand is used twice in the encoding.
3030 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3031 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3032 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3033 emit_opcode(cbuf,0xDF);
3034 int rm_byte_opcode = 0x07;
3035 int base = $mem$$base;
3036 int index = $mem$$index;
3037 int scale = $mem$$scale;
3038 int displace = $mem$$disp;
3039 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3040 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3041 %}
3042
3043 // Safepoint Poll. This polls the safepoint page, and causes an
3044 // exception if it is not readable. Unfortunately, it kills the condition code
3045 // in the process
3046 // We current use TESTL [spp],EDI
3047 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3048
3049 enc_class Safepoint_Poll() %{
3050 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3051 emit_opcode(cbuf,0x85);
3052 emit_rm (cbuf, 0x0, 0x7, 0x5);
3053 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3054 %}
3055 %}
3056
3057
3058 //----------FRAME--------------------------------------------------------------
3059 // Definition of frame structure and management information.
3060 //
3061 // S T A C K L A Y O U T Allocators stack-slot number
3062 // | (to get allocators register number
3063 // G Owned by | | v add OptoReg::stack0())
3064 // r CALLER | |
3065 // o | +--------+ pad to even-align allocators stack-slot
3066 // w V | pad0 | numbers; owned by CALLER
3067 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3068 // h ^ | in | 5
3069 // | | args | 4 Holes in incoming args owned by SELF
3070 // | | | | 3
3071 // | | +--------+
3072 // V | | old out| Empty on Intel, window on Sparc
3073 // | old |preserve| Must be even aligned.
3074 // | SP-+--------+----> Matcher::_old_SP, even aligned
3075 // | | in | 3 area for Intel ret address
3076 // Owned by |preserve| Empty on Sparc.
3077 // SELF +--------+
3078 // | | pad2 | 2 pad to align old SP
3079 // | +--------+ 1
3080 // | | locks | 0
3081 // | +--------+----> OptoReg::stack0(), even aligned
3082 // | | pad1 | 11 pad to align new SP
3083 // | +--------+
3084 // | | | 10
3085 // | | spills | 9 spills
3086 // V | | 8 (pad0 slot for callee)
3087 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3088 // ^ | out | 7
3089 // | | args | 6 Holes in outgoing args owned by CALLEE
3090 // Owned by +--------+
3091 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3092 // | new |preserve| Must be even-aligned.
3093 // | SP-+--------+----> Matcher::_new_SP, even aligned
3094 // | | |
3095 //
3096 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3097 // known from SELF's arguments and the Java calling convention.
3098 // Region 6-7 is determined per call site.
3099 // Note 2: If the calling convention leaves holes in the incoming argument
3100 // area, those holes are owned by SELF. Holes in the outgoing area
3101 // are owned by the CALLEE. Holes should not be nessecary in the
3102 // incoming area, as the Java calling convention is completely under
3103 // the control of the AD file. Doubles can be sorted and packed to
3104 // avoid holes. Holes in the outgoing arguments may be nessecary for
3105 // varargs C calling conventions.
3106 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3107 // even aligned with pad0 as needed.
3108 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3109 // region 6-11 is even aligned; it may be padded out more so that
3110 // the region from SP to FP meets the minimum stack alignment.
3111
3112 frame %{
3113 // What direction does stack grow in (assumed to be same for C & Java)
3114 stack_direction(TOWARDS_LOW);
3115
3116 // These three registers define part of the calling convention
3117 // between compiled code and the interpreter.
3118 inline_cache_reg(EAX); // Inline Cache Register
3119 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3120
3121 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3122 cisc_spilling_operand_name(indOffset32);
3123
3124 // Number of stack slots consumed by locking an object
3125 sync_stack_slots(1);
3126
3127 // Compiled code's Frame Pointer
3128 frame_pointer(ESP);
3129 // Interpreter stores its frame pointer in a register which is
3130 // stored to the stack by I2CAdaptors.
3131 // I2CAdaptors convert from interpreted java to compiled java.
3132 interpreter_frame_pointer(EBP);
3133
3134 // Stack alignment requirement
3135 // Alignment size in bytes (128-bit -> 16 bytes)
3136 stack_alignment(StackAlignmentInBytes);
3137
3138 // Number of stack slots between incoming argument block and the start of
3139 // a new frame. The PROLOG must add this many slots to the stack. The
3140 // EPILOG must remove this many slots. Intel needs one slot for
3141 // return address and one for rbp, (must save rbp)
3142 in_preserve_stack_slots(2+VerifyStackAtCalls);
3143
3144 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3145 // for calls to C. Supports the var-args backing area for register parms.
3146 varargs_C_out_slots_killed(0);
3147
3148 // The after-PROLOG location of the return address. Location of
3149 // return address specifies a type (REG or STACK) and a number
3150 // representing the register number (i.e. - use a register name) or
3151 // stack slot.
3152 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3153 // Otherwise, it is above the locks and verification slot and alignment word
3154 return_addr(STACK - 1 +
3155 round_to((Compile::current()->in_preserve_stack_slots() +
3156 Compile::current()->fixed_slots()),
3157 stack_alignment_in_slots()));
3158
3159 // Body of function which returns an integer array locating
3160 // arguments either in registers or in stack slots. Passed an array
3161 // of ideal registers called "sig" and a "length" count. Stack-slot
3162 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3163 // arguments for a CALLEE. Incoming stack arguments are
3164 // automatically biased by the preserve_stack_slots field above.
3165 calling_convention %{
3166 // No difference between ingoing/outgoing just pass false
3167 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3168 %}
3169
3170
3171 // Body of function which returns an integer array locating
3172 // arguments either in registers or in stack slots. Passed an array
3173 // of ideal registers called "sig" and a "length" count. Stack-slot
3174 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3175 // arguments for a CALLEE. Incoming stack arguments are
3176 // automatically biased by the preserve_stack_slots field above.
3177 c_calling_convention %{
3178 // This is obviously always outgoing
3179 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3180 %}
3181
3182 // Location of C & interpreter return values
3183 c_return_value %{
3184 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3185 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3186 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3187
3188 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3189 // that C functions return float and double results in XMM0.
3190 if( ideal_reg == Op_RegD && UseSSE>=2 )
3191 return OptoRegPair(XMM0b_num,XMM0_num);
3192 if( ideal_reg == Op_RegF && UseSSE>=2 )
3193 return OptoRegPair(OptoReg::Bad,XMM0_num);
3194
3195 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3196 %}
3197
3198 // Location of return values
3199 return_value %{
3200 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3201 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3202 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3203 if( ideal_reg == Op_RegD && UseSSE>=2 )
3204 return OptoRegPair(XMM0b_num,XMM0_num);
3205 if( ideal_reg == Op_RegF && UseSSE>=1 )
3206 return OptoRegPair(OptoReg::Bad,XMM0_num);
3207 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3208 %}
3209
3210 %}
3211
3212 //----------ATTRIBUTES---------------------------------------------------------
3213 //----------Operand Attributes-------------------------------------------------
3214 op_attrib op_cost(0); // Required cost attribute
3215
3216 //----------Instruction Attributes---------------------------------------------
3217 ins_attrib ins_cost(100); // Required cost attribute
3218 ins_attrib ins_size(8); // Required size attribute (in bits)
3219 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3220 // non-matching short branch variant of some
3221 // long branch?
3222 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3223 // specifies the alignment that some part of the instruction (not
3224 // necessarily the start) requires. If > 1, a compute_padding()
3225 // function must be provided for the instruction
3226
3227 //----------OPERANDS-----------------------------------------------------------
3228 // Operand definitions must precede instruction definitions for correct parsing
3229 // in the ADLC because operands constitute user defined types which are used in
3230 // instruction definitions.
3231
3232 //----------Simple Operands----------------------------------------------------
3233 // Immediate Operands
3234 // Integer Immediate
3235 operand immI() %{
3236 match(ConI);
3237
3238 op_cost(10);
3239 format %{ %}
3240 interface(CONST_INTER);
3241 %}
3242
3243 // Constant for test vs zero
3244 operand immI0() %{
3245 predicate(n->get_int() == 0);
3246 match(ConI);
3247
3248 op_cost(0);
3249 format %{ %}
3250 interface(CONST_INTER);
3251 %}
3252
3253 // Constant for increment
3254 operand immI1() %{
3255 predicate(n->get_int() == 1);
3256 match(ConI);
3257
3258 op_cost(0);
3259 format %{ %}
3260 interface(CONST_INTER);
3261 %}
3262
3263 // Constant for decrement
3264 operand immI_M1() %{
3265 predicate(n->get_int() == -1);
3266 match(ConI);
3267
3268 op_cost(0);
3269 format %{ %}
3270 interface(CONST_INTER);
3271 %}
3272
3273 // Valid scale values for addressing modes
3274 operand immI2() %{
3275 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3276 match(ConI);
3277
3278 format %{ %}
3279 interface(CONST_INTER);
3280 %}
3281
3282 operand immI8() %{
3283 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3284 match(ConI);
3285
3286 op_cost(5);
3287 format %{ %}
3288 interface(CONST_INTER);
3289 %}
3290
3291 operand immI16() %{
3292 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3293 match(ConI);
3294
3295 op_cost(10);
3296 format %{ %}
3297 interface(CONST_INTER);
3298 %}
3299
3300 // Int Immediate non-negative
3301 operand immU31()
3302 %{
3303 predicate(n->get_int() >= 0);
3304 match(ConI);
3305
3306 op_cost(0);
3307 format %{ %}
3308 interface(CONST_INTER);
3309 %}
3310
3311 // Constant for long shifts
3312 operand immI_32() %{
3313 predicate( n->get_int() == 32 );
3314 match(ConI);
3315
3316 op_cost(0);
3317 format %{ %}
3318 interface(CONST_INTER);
3319 %}
3320
3321 operand immI_1_31() %{
3322 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3323 match(ConI);
3324
3325 op_cost(0);
3326 format %{ %}
3327 interface(CONST_INTER);
3328 %}
3329
3330 operand immI_32_63() %{
3331 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3332 match(ConI);
3333 op_cost(0);
3334
3335 format %{ %}
3336 interface(CONST_INTER);
3337 %}
3338
3339 operand immI_1() %{
3340 predicate( n->get_int() == 1 );
3341 match(ConI);
3342
3343 op_cost(0);
3344 format %{ %}
3345 interface(CONST_INTER);
3346 %}
3347
3348 operand immI_2() %{
3349 predicate( n->get_int() == 2 );
3350 match(ConI);
3351
3352 op_cost(0);
3353 format %{ %}
3354 interface(CONST_INTER);
3355 %}
3356
3357 operand immI_3() %{
3358 predicate( n->get_int() == 3 );
3359 match(ConI);
3360
3361 op_cost(0);
3362 format %{ %}
3363 interface(CONST_INTER);
3364 %}
3365
3366 // Pointer Immediate
3367 operand immP() %{
3368 match(ConP);
3369
3370 op_cost(10);
3371 format %{ %}
3372 interface(CONST_INTER);
3373 %}
3374
3375 // NULL Pointer Immediate
3376 operand immP0() %{
3377 predicate( n->get_ptr() == 0 );
3378 match(ConP);
3379 op_cost(0);
3380
3381 format %{ %}
3382 interface(CONST_INTER);
3383 %}
3384
3385 // Long Immediate
3386 operand immL() %{
3387 match(ConL);
3388
3389 op_cost(20);
3390 format %{ %}
3391 interface(CONST_INTER);
3392 %}
3393
3394 // Long Immediate zero
3395 operand immL0() %{
3396 predicate( n->get_long() == 0L );
3397 match(ConL);
3398 op_cost(0);
3399
3400 format %{ %}
3401 interface(CONST_INTER);
3402 %}
3403
3404 // Long Immediate zero
3405 operand immL_M1() %{
3406 predicate( n->get_long() == -1L );
3407 match(ConL);
3408 op_cost(0);
3409
3410 format %{ %}
3411 interface(CONST_INTER);
3412 %}
3413
3414 // Long immediate from 0 to 127.
3415 // Used for a shorter form of long mul by 10.
3416 operand immL_127() %{
3417 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3418 match(ConL);
3419 op_cost(0);
3420
3421 format %{ %}
3422 interface(CONST_INTER);
3423 %}
3424
3425 // Long Immediate: low 32-bit mask
3426 operand immL_32bits() %{
3427 predicate(n->get_long() == 0xFFFFFFFFL);
3428 match(ConL);
3429 op_cost(0);
3430
3431 format %{ %}
3432 interface(CONST_INTER);
3433 %}
3434
3435 // Long Immediate: low 32-bit mask
3436 operand immL32() %{
3437 predicate(n->get_long() == (int)(n->get_long()));
3438 match(ConL);
3439 op_cost(20);
3440
3441 format %{ %}
3442 interface(CONST_INTER);
3443 %}
3444
3445 //Double Immediate zero
3446 operand immDPR0() %{
3447 // Do additional (and counter-intuitive) test against NaN to work around VC++
3448 // bug that generates code such that NaNs compare equal to 0.0
3449 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
3450 match(ConD);
3451
3452 op_cost(5);
3453 format %{ %}
3454 interface(CONST_INTER);
3455 %}
3456
3457 // Double Immediate one
3458 operand immDPR1() %{
3459 predicate( UseSSE<=1 && n->getd() == 1.0 );
3460 match(ConD);
3461
3462 op_cost(5);
3463 format %{ %}
3464 interface(CONST_INTER);
3465 %}
3466
3467 // Double Immediate
3468 operand immDPR() %{
3469 predicate(UseSSE<=1);
3470 match(ConD);
3471
3472 op_cost(5);
3473 format %{ %}
3474 interface(CONST_INTER);
3475 %}
3476
3477 operand immD() %{
3478 predicate(UseSSE>=2);
3479 match(ConD);
3480
3481 op_cost(5);
3482 format %{ %}
3483 interface(CONST_INTER);
3484 %}
3485
3486 // Double Immediate zero
3487 operand immD0() %{
3488 // Do additional (and counter-intuitive) test against NaN to work around VC++
3489 // bug that generates code such that NaNs compare equal to 0.0 AND do not
3490 // compare equal to -0.0.
3491 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
3492 match(ConD);
3493
3494 format %{ %}
3495 interface(CONST_INTER);
3496 %}
3497
3498 // Float Immediate zero
3499 operand immFPR0() %{
3500 predicate(UseSSE == 0 && n->getf() == 0.0F);
3501 match(ConF);
3502
3503 op_cost(5);
3504 format %{ %}
3505 interface(CONST_INTER);
3506 %}
3507
3508 // Float Immediate one
3509 operand immFPR1() %{
3510 predicate(UseSSE == 0 && n->getf() == 1.0F);
3511 match(ConF);
3512
3513 op_cost(5);
3514 format %{ %}
3515 interface(CONST_INTER);
3516 %}
3517
3518 // Float Immediate
3519 operand immFPR() %{
3520 predicate( UseSSE == 0 );
3521 match(ConF);
3522
3523 op_cost(5);
3524 format %{ %}
3525 interface(CONST_INTER);
3526 %}
3527
3528 // Float Immediate
3529 operand immF() %{
3530 predicate(UseSSE >= 1);
3531 match(ConF);
3532
3533 op_cost(5);
3534 format %{ %}
3535 interface(CONST_INTER);
3536 %}
3537
3538 // Float Immediate zero. Zero and not -0.0
3539 operand immF0() %{
3540 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
3541 match(ConF);
3542
3543 op_cost(5);
3544 format %{ %}
3545 interface(CONST_INTER);
3546 %}
3547
3548 // Immediates for special shifts (sign extend)
3549
3550 // Constants for increment
3551 operand immI_16() %{
3552 predicate( n->get_int() == 16 );
3553 match(ConI);
3554
3555 format %{ %}
3556 interface(CONST_INTER);
3557 %}
3558
3559 operand immI_24() %{
3560 predicate( n->get_int() == 24 );
3561 match(ConI);
3562
3563 format %{ %}
3564 interface(CONST_INTER);
3565 %}
3566
3567 // Constant for byte-wide masking
3568 operand immI_255() %{
3569 predicate( n->get_int() == 255 );
3570 match(ConI);
3571
3572 format %{ %}
3573 interface(CONST_INTER);
3574 %}
3575
3576 // Constant for short-wide masking
3577 operand immI_65535() %{
3578 predicate(n->get_int() == 65535);
3579 match(ConI);
3580
3581 format %{ %}
3582 interface(CONST_INTER);
3583 %}
3584
3585 // Register Operands
3586 // Integer Register
3587 operand rRegI() %{
3588 constraint(ALLOC_IN_RC(int_reg));
3589 match(RegI);
3590 match(xRegI);
3591 match(eAXRegI);
3592 match(eBXRegI);
3593 match(eCXRegI);
3594 match(eDXRegI);
3595 match(eDIRegI);
3596 match(eSIRegI);
3597
3598 format %{ %}
3599 interface(REG_INTER);
3600 %}
3601
3602 // Subset of Integer Register
3603 operand xRegI(rRegI reg) %{
3604 constraint(ALLOC_IN_RC(int_x_reg));
3605 match(reg);
3606 match(eAXRegI);
3607 match(eBXRegI);
3608 match(eCXRegI);
3609 match(eDXRegI);
3610
3611 format %{ %}
3612 interface(REG_INTER);
3613 %}
3614
3615 // Special Registers
3616 operand eAXRegI(xRegI reg) %{
3617 constraint(ALLOC_IN_RC(eax_reg));
3618 match(reg);
3619 match(rRegI);
3620
3621 format %{ "EAX" %}
3622 interface(REG_INTER);
3623 %}
3624
3625 // Special Registers
3626 operand eBXRegI(xRegI reg) %{
3627 constraint(ALLOC_IN_RC(ebx_reg));
3628 match(reg);
3629 match(rRegI);
3630
3631 format %{ "EBX" %}
3632 interface(REG_INTER);
3633 %}
3634
3635 operand eCXRegI(xRegI reg) %{
3636 constraint(ALLOC_IN_RC(ecx_reg));
3637 match(reg);
3638 match(rRegI);
3639
3640 format %{ "ECX" %}
3641 interface(REG_INTER);
3642 %}
3643
3644 operand eDXRegI(xRegI reg) %{
3645 constraint(ALLOC_IN_RC(edx_reg));
3646 match(reg);
3647 match(rRegI);
3648
3649 format %{ "EDX" %}
3650 interface(REG_INTER);
3651 %}
3652
3653 operand eDIRegI(xRegI reg) %{
3654 constraint(ALLOC_IN_RC(edi_reg));
3655 match(reg);
3656 match(rRegI);
3657
3658 format %{ "EDI" %}
3659 interface(REG_INTER);
3660 %}
3661
3662 operand naxRegI() %{
3663 constraint(ALLOC_IN_RC(nax_reg));
3664 match(RegI);
3665 match(eCXRegI);
3666 match(eDXRegI);
3667 match(eSIRegI);
3668 match(eDIRegI);
3669
3670 format %{ %}
3671 interface(REG_INTER);
3672 %}
3673
3674 operand nadxRegI() %{
3675 constraint(ALLOC_IN_RC(nadx_reg));
3676 match(RegI);
3677 match(eBXRegI);
3678 match(eCXRegI);
3679 match(eSIRegI);
3680 match(eDIRegI);
3681
3682 format %{ %}
3683 interface(REG_INTER);
3684 %}
3685
3686 operand ncxRegI() %{
3687 constraint(ALLOC_IN_RC(ncx_reg));
3688 match(RegI);
3689 match(eAXRegI);
3690 match(eDXRegI);
3691 match(eSIRegI);
3692 match(eDIRegI);
3693
3694 format %{ %}
3695 interface(REG_INTER);
3696 %}
3697
3698 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
3699 // //
3700 operand eSIRegI(xRegI reg) %{
3701 constraint(ALLOC_IN_RC(esi_reg));
3702 match(reg);
3703 match(rRegI);
3704
3705 format %{ "ESI" %}
3706 interface(REG_INTER);
3707 %}
3708
3709 // Pointer Register
3710 operand anyRegP() %{
3711 constraint(ALLOC_IN_RC(any_reg));
3712 match(RegP);
3713 match(eAXRegP);
3714 match(eBXRegP);
3715 match(eCXRegP);
3716 match(eDIRegP);
3717 match(eRegP);
3718
3719 format %{ %}
3720 interface(REG_INTER);
3721 %}
3722
3723 operand eRegP() %{
3724 constraint(ALLOC_IN_RC(int_reg));
3725 match(RegP);
3726 match(eAXRegP);
3727 match(eBXRegP);
3728 match(eCXRegP);
3729 match(eDIRegP);
3730
3731 format %{ %}
3732 interface(REG_INTER);
3733 %}
3734
3735 // On windows95, EBP is not safe to use for implicit null tests.
3736 operand eRegP_no_EBP() %{
3737 constraint(ALLOC_IN_RC(int_reg_no_rbp));
3738 match(RegP);
3739 match(eAXRegP);
3740 match(eBXRegP);
3741 match(eCXRegP);
3742 match(eDIRegP);
3743
3744 op_cost(100);
3745 format %{ %}
3746 interface(REG_INTER);
3747 %}
3748
3749 operand naxRegP() %{
3750 constraint(ALLOC_IN_RC(nax_reg));
3751 match(RegP);
3752 match(eBXRegP);
3753 match(eDXRegP);
3754 match(eCXRegP);
3755 match(eSIRegP);
3756 match(eDIRegP);
3757
3758 format %{ %}
3759 interface(REG_INTER);
3760 %}
3761
3762 operand nabxRegP() %{
3763 constraint(ALLOC_IN_RC(nabx_reg));
3764 match(RegP);
3765 match(eCXRegP);
3766 match(eDXRegP);
3767 match(eSIRegP);
3768 match(eDIRegP);
3769
3770 format %{ %}
3771 interface(REG_INTER);
3772 %}
3773
3774 operand pRegP() %{
3775 constraint(ALLOC_IN_RC(p_reg));
3776 match(RegP);
3777 match(eBXRegP);
3778 match(eDXRegP);
3779 match(eSIRegP);
3780 match(eDIRegP);
3781
3782 format %{ %}
3783 interface(REG_INTER);
3784 %}
3785
3786 // Special Registers
3787 // Return a pointer value
3788 operand eAXRegP(eRegP reg) %{
3789 constraint(ALLOC_IN_RC(eax_reg));
3790 match(reg);
3791 format %{ "EAX" %}
3792 interface(REG_INTER);
3793 %}
3794
3795 // Used in AtomicAdd
3796 operand eBXRegP(eRegP reg) %{
3797 constraint(ALLOC_IN_RC(ebx_reg));
3798 match(reg);
3799 format %{ "EBX" %}
3800 interface(REG_INTER);
3801 %}
3802
3803 // Tail-call (interprocedural jump) to interpreter
3804 operand eCXRegP(eRegP reg) %{
3805 constraint(ALLOC_IN_RC(ecx_reg));
3806 match(reg);
3807 format %{ "ECX" %}
3808 interface(REG_INTER);
3809 %}
3810
3811 operand eSIRegP(eRegP reg) %{
3812 constraint(ALLOC_IN_RC(esi_reg));
3813 match(reg);
3814 format %{ "ESI" %}
3815 interface(REG_INTER);
3816 %}
3817
3818 // Used in rep stosw
3819 operand eDIRegP(eRegP reg) %{
3820 constraint(ALLOC_IN_RC(edi_reg));
3821 match(reg);
3822 format %{ "EDI" %}
3823 interface(REG_INTER);
3824 %}
3825
3826 operand eBPRegP() %{
3827 constraint(ALLOC_IN_RC(ebp_reg));
3828 match(RegP);
3829 format %{ "EBP" %}
3830 interface(REG_INTER);
3831 %}
3832
3833 operand eRegL() %{
3834 constraint(ALLOC_IN_RC(long_reg));
3835 match(RegL);
3836 match(eADXRegL);
3837
3838 format %{ %}
3839 interface(REG_INTER);
3840 %}
3841
3842 operand eADXRegL( eRegL reg ) %{
3843 constraint(ALLOC_IN_RC(eadx_reg));
3844 match(reg);
3845
3846 format %{ "EDX:EAX" %}
3847 interface(REG_INTER);
3848 %}
3849
3850 operand eBCXRegL( eRegL reg ) %{
3851 constraint(ALLOC_IN_RC(ebcx_reg));
3852 match(reg);
3853
3854 format %{ "EBX:ECX" %}
3855 interface(REG_INTER);
3856 %}
3857
3858 // Special case for integer high multiply
3859 operand eADXRegL_low_only() %{
3860 constraint(ALLOC_IN_RC(eadx_reg));
3861 match(RegL);
3862
3863 format %{ "EAX" %}
3864 interface(REG_INTER);
3865 %}
3866
3867 // Flags register, used as output of compare instructions
3868 operand eFlagsReg() %{
3869 constraint(ALLOC_IN_RC(int_flags));
3870 match(RegFlags);
3871
3872 format %{ "EFLAGS" %}
3873 interface(REG_INTER);
3874 %}
3875
3876 // Flags register, used as output of FLOATING POINT compare instructions
3877 operand eFlagsRegU() %{
3878 constraint(ALLOC_IN_RC(int_flags));
3879 match(RegFlags);
3880
3881 format %{ "EFLAGS_U" %}
3882 interface(REG_INTER);
3883 %}
3884
3885 operand eFlagsRegUCF() %{
3886 constraint(ALLOC_IN_RC(int_flags));
3887 match(RegFlags);
3888 predicate(false);
3889
3890 format %{ "EFLAGS_U_CF" %}
3891 interface(REG_INTER);
3892 %}
3893
3894 // Condition Code Register used by long compare
3895 operand flagsReg_long_LTGE() %{
3896 constraint(ALLOC_IN_RC(int_flags));
3897 match(RegFlags);
3898 format %{ "FLAGS_LTGE" %}
3899 interface(REG_INTER);
3900 %}
3901 operand flagsReg_long_EQNE() %{
3902 constraint(ALLOC_IN_RC(int_flags));
3903 match(RegFlags);
3904 format %{ "FLAGS_EQNE" %}
3905 interface(REG_INTER);
3906 %}
3907 operand flagsReg_long_LEGT() %{
3908 constraint(ALLOC_IN_RC(int_flags));
3909 match(RegFlags);
3910 format %{ "FLAGS_LEGT" %}
3911 interface(REG_INTER);
3912 %}
3913
3914 // Float register operands
3915 operand regDPR() %{
3916 predicate( UseSSE < 2 );
3917 constraint(ALLOC_IN_RC(fp_dbl_reg));
3918 match(RegD);
3919 match(regDPR1);
3920 match(regDPR2);
3921 format %{ %}
3922 interface(REG_INTER);
3923 %}
3924
3925 operand regDPR1(regDPR reg) %{
3926 predicate( UseSSE < 2 );
3927 constraint(ALLOC_IN_RC(fp_dbl_reg0));
3928 match(reg);
3929 format %{ "FPR1" %}
3930 interface(REG_INTER);
3931 %}
3932
3933 operand regDPR2(regDPR reg) %{
3934 predicate( UseSSE < 2 );
3935 constraint(ALLOC_IN_RC(fp_dbl_reg1));
3936 match(reg);
3937 format %{ "FPR2" %}
3938 interface(REG_INTER);
3939 %}
3940
3941 operand regnotDPR1(regDPR reg) %{
3942 predicate( UseSSE < 2 );
3943 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
3944 match(reg);
3945 format %{ %}
3946 interface(REG_INTER);
3947 %}
3948
3949 // Float register operands
3950 operand regFPR() %{
3951 predicate( UseSSE < 2 );
3952 constraint(ALLOC_IN_RC(fp_flt_reg));
3953 match(RegF);
3954 match(regFPR1);
3955 format %{ %}
3956 interface(REG_INTER);
3957 %}
3958
3959 // Float register operands
3960 operand regFPR1(regFPR reg) %{
3961 predicate( UseSSE < 2 );
3962 constraint(ALLOC_IN_RC(fp_flt_reg0));
3963 match(reg);
3964 format %{ "FPR1" %}
3965 interface(REG_INTER);
3966 %}
3967
3968 // XMM Float register operands
3969 operand regF() %{
3970 predicate( UseSSE>=1 );
3971 constraint(ALLOC_IN_RC(float_reg));
3972 match(RegF);
3973 format %{ %}
3974 interface(REG_INTER);
3975 %}
3976
3977 // XMM Double register operands
3978 operand regD() %{
3979 predicate( UseSSE>=2 );
3980 constraint(ALLOC_IN_RC(double_reg));
3981 match(RegD);
3982 format %{ %}
3983 interface(REG_INTER);
3984 %}
3985
3986
3987 //----------Memory Operands----------------------------------------------------
3988 // Direct Memory Operand
3989 operand direct(immP addr) %{
3990 match(addr);
3991
3992 format %{ "[$addr]" %}
3993 interface(MEMORY_INTER) %{
3994 base(0xFFFFFFFF);
3995 index(0x4);
3996 scale(0x0);
3997 disp($addr);
3998 %}
3999 %}
4000
4001 // Indirect Memory Operand
4002 operand indirect(eRegP reg) %{
4003 constraint(ALLOC_IN_RC(int_reg));
4004 match(reg);
4005
4006 format %{ "[$reg]" %}
4007 interface(MEMORY_INTER) %{
4008 base($reg);
4009 index(0x4);
4010 scale(0x0);
4011 disp(0x0);
4012 %}
4013 %}
4014
4015 // Indirect Memory Plus Short Offset Operand
4016 operand indOffset8(eRegP reg, immI8 off) %{
4017 match(AddP reg off);
4018
4019 format %{ "[$reg + $off]" %}
4020 interface(MEMORY_INTER) %{
4021 base($reg);
4022 index(0x4);
4023 scale(0x0);
4024 disp($off);
4025 %}
4026 %}
4027
4028 // Indirect Memory Plus Long Offset Operand
4029 operand indOffset32(eRegP reg, immI off) %{
4030 match(AddP reg off);
4031
4032 format %{ "[$reg + $off]" %}
4033 interface(MEMORY_INTER) %{
4034 base($reg);
4035 index(0x4);
4036 scale(0x0);
4037 disp($off);
4038 %}
4039 %}
4040
4041 // Indirect Memory Plus Long Offset Operand
4042 operand indOffset32X(rRegI reg, immP off) %{
4043 match(AddP off reg);
4044
4045 format %{ "[$reg + $off]" %}
4046 interface(MEMORY_INTER) %{
4047 base($reg);
4048 index(0x4);
4049 scale(0x0);
4050 disp($off);
4051 %}
4052 %}
4053
4054 // Indirect Memory Plus Index Register Plus Offset Operand
4055 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4056 match(AddP (AddP reg ireg) off);
4057
4058 op_cost(10);
4059 format %{"[$reg + $off + $ireg]" %}
4060 interface(MEMORY_INTER) %{
4061 base($reg);
4062 index($ireg);
4063 scale(0x0);
4064 disp($off);
4065 %}
4066 %}
4067
4068 // Indirect Memory Plus Index Register Plus Offset Operand
4069 operand indIndex(eRegP reg, rRegI ireg) %{
4070 match(AddP reg ireg);
4071
4072 op_cost(10);
4073 format %{"[$reg + $ireg]" %}
4074 interface(MEMORY_INTER) %{
4075 base($reg);
4076 index($ireg);
4077 scale(0x0);
4078 disp(0x0);
4079 %}
4080 %}
4081
4082 // // -------------------------------------------------------------------------
4083 // // 486 architecture doesn't support "scale * index + offset" with out a base
4084 // // -------------------------------------------------------------------------
4085 // // Scaled Memory Operands
4086 // // Indirect Memory Times Scale Plus Offset Operand
4087 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4088 // match(AddP off (LShiftI ireg scale));
4089 //
4090 // op_cost(10);
4091 // format %{"[$off + $ireg << $scale]" %}
4092 // interface(MEMORY_INTER) %{
4093 // base(0x4);
4094 // index($ireg);
4095 // scale($scale);
4096 // disp($off);
4097 // %}
4098 // %}
4099
4100 // Indirect Memory Times Scale Plus Index Register
4101 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4102 match(AddP reg (LShiftI ireg scale));
4103
4104 op_cost(10);
4105 format %{"[$reg + $ireg << $scale]" %}
4106 interface(MEMORY_INTER) %{
4107 base($reg);
4108 index($ireg);
4109 scale($scale);
4110 disp(0x0);
4111 %}
4112 %}
4113
4114 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4115 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4116 match(AddP (AddP reg (LShiftI ireg scale)) off);
4117
4118 op_cost(10);
4119 format %{"[$reg + $off + $ireg << $scale]" %}
4120 interface(MEMORY_INTER) %{
4121 base($reg);
4122 index($ireg);
4123 scale($scale);
4124 disp($off);
4125 %}
4126 %}
4127
4128 //----------Load Long Memory Operands------------------------------------------
4129 // The load-long idiom will use it's address expression again after loading
4130 // the first word of the long. If the load-long destination overlaps with
4131 // registers used in the addressing expression, the 2nd half will be loaded
4132 // from a clobbered address. Fix this by requiring that load-long use
4133 // address registers that do not overlap with the load-long target.
4134
4135 // load-long support
4136 operand load_long_RegP() %{
4137 constraint(ALLOC_IN_RC(esi_reg));
4138 match(RegP);
4139 match(eSIRegP);
4140 op_cost(100);
4141 format %{ %}
4142 interface(REG_INTER);
4143 %}
4144
4145 // Indirect Memory Operand Long
4146 operand load_long_indirect(load_long_RegP reg) %{
4147 constraint(ALLOC_IN_RC(esi_reg));
4148 match(reg);
4149
4150 format %{ "[$reg]" %}
4151 interface(MEMORY_INTER) %{
4152 base($reg);
4153 index(0x4);
4154 scale(0x0);
4155 disp(0x0);
4156 %}
4157 %}
4158
4159 // Indirect Memory Plus Long Offset Operand
4160 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4161 match(AddP reg off);
4162
4163 format %{ "[$reg + $off]" %}
4164 interface(MEMORY_INTER) %{
4165 base($reg);
4166 index(0x4);
4167 scale(0x0);
4168 disp($off);
4169 %}
4170 %}
4171
4172 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4173
4174
4175 //----------Special Memory Operands--------------------------------------------
4176 // Stack Slot Operand - This operand is used for loading and storing temporary
4177 // values on the stack where a match requires a value to
4178 // flow through memory.
4179 operand stackSlotP(sRegP reg) %{
4180 constraint(ALLOC_IN_RC(stack_slots));
4181 // No match rule because this operand is only generated in matching
4182 format %{ "[$reg]" %}
4183 interface(MEMORY_INTER) %{
4184 base(0x4); // ESP
4185 index(0x4); // No Index
4186 scale(0x0); // No Scale
4187 disp($reg); // Stack Offset
4188 %}
4189 %}
4190
4191 operand stackSlotI(sRegI reg) %{
4192 constraint(ALLOC_IN_RC(stack_slots));
4193 // No match rule because this operand is only generated in matching
4194 format %{ "[$reg]" %}
4195 interface(MEMORY_INTER) %{
4196 base(0x4); // ESP
4197 index(0x4); // No Index
4198 scale(0x0); // No Scale
4199 disp($reg); // Stack Offset
4200 %}
4201 %}
4202
4203 operand stackSlotF(sRegF reg) %{
4204 constraint(ALLOC_IN_RC(stack_slots));
4205 // No match rule because this operand is only generated in matching
4206 format %{ "[$reg]" %}
4207 interface(MEMORY_INTER) %{
4208 base(0x4); // ESP
4209 index(0x4); // No Index
4210 scale(0x0); // No Scale
4211 disp($reg); // Stack Offset
4212 %}
4213 %}
4214
4215 operand stackSlotD(sRegD reg) %{
4216 constraint(ALLOC_IN_RC(stack_slots));
4217 // No match rule because this operand is only generated in matching
4218 format %{ "[$reg]" %}
4219 interface(MEMORY_INTER) %{
4220 base(0x4); // ESP
4221 index(0x4); // No Index
4222 scale(0x0); // No Scale
4223 disp($reg); // Stack Offset
4224 %}
4225 %}
4226
4227 operand stackSlotL(sRegL reg) %{
4228 constraint(ALLOC_IN_RC(stack_slots));
4229 // No match rule because this operand is only generated in matching
4230 format %{ "[$reg]" %}
4231 interface(MEMORY_INTER) %{
4232 base(0x4); // ESP
4233 index(0x4); // No Index
4234 scale(0x0); // No Scale
4235 disp($reg); // Stack Offset
4236 %}
4237 %}
4238
4239 //----------Memory Operands - Win95 Implicit Null Variants----------------
4240 // Indirect Memory Operand
4241 operand indirect_win95_safe(eRegP_no_EBP reg)
4242 %{
4243 constraint(ALLOC_IN_RC(int_reg));
4244 match(reg);
4245
4246 op_cost(100);
4247 format %{ "[$reg]" %}
4248 interface(MEMORY_INTER) %{
4249 base($reg);
4250 index(0x4);
4251 scale(0x0);
4252 disp(0x0);
4253 %}
4254 %}
4255
4256 // Indirect Memory Plus Short Offset Operand
4257 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4258 %{
4259 match(AddP reg off);
4260
4261 op_cost(100);
4262 format %{ "[$reg + $off]" %}
4263 interface(MEMORY_INTER) %{
4264 base($reg);
4265 index(0x4);
4266 scale(0x0);
4267 disp($off);
4268 %}
4269 %}
4270
4271 // Indirect Memory Plus Long Offset Operand
4272 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4273 %{
4274 match(AddP reg off);
4275
4276 op_cost(100);
4277 format %{ "[$reg + $off]" %}
4278 interface(MEMORY_INTER) %{
4279 base($reg);
4280 index(0x4);
4281 scale(0x0);
4282 disp($off);
4283 %}
4284 %}
4285
4286 // Indirect Memory Plus Index Register Plus Offset Operand
4287 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4288 %{
4289 match(AddP (AddP reg ireg) off);
4290
4291 op_cost(100);
4292 format %{"[$reg + $off + $ireg]" %}
4293 interface(MEMORY_INTER) %{
4294 base($reg);
4295 index($ireg);
4296 scale(0x0);
4297 disp($off);
4298 %}
4299 %}
4300
4301 // Indirect Memory Times Scale Plus Index Register
4302 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4303 %{
4304 match(AddP reg (LShiftI ireg scale));
4305
4306 op_cost(100);
4307 format %{"[$reg + $ireg << $scale]" %}
4308 interface(MEMORY_INTER) %{
4309 base($reg);
4310 index($ireg);
4311 scale($scale);
4312 disp(0x0);
4313 %}
4314 %}
4315
4316 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4317 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4318 %{
4319 match(AddP (AddP reg (LShiftI ireg scale)) off);
4320
4321 op_cost(100);
4322 format %{"[$reg + $off + $ireg << $scale]" %}
4323 interface(MEMORY_INTER) %{
4324 base($reg);
4325 index($ireg);
4326 scale($scale);
4327 disp($off);
4328 %}
4329 %}
4330
4331 //----------Conditional Branch Operands----------------------------------------
4332 // Comparison Op - This is the operation of the comparison, and is limited to
4333 // the following set of codes:
4334 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4335 //
4336 // Other attributes of the comparison, such as unsignedness, are specified
4337 // by the comparison instruction that sets a condition code flags register.
4338 // That result is represented by a flags operand whose subtype is appropriate
4339 // to the unsignedness (etc.) of the comparison.
4340 //
4341 // Later, the instruction which matches both the Comparison Op (a Bool) and
4342 // the flags (produced by the Cmp) specifies the coding of the comparison op
4343 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4344
4345 // Comparision Code
4346 operand cmpOp() %{
4347 match(Bool);
4348
4349 format %{ "" %}
4350 interface(COND_INTER) %{
4351 equal(0x4, "e");
4352 not_equal(0x5, "ne");
4353 less(0xC, "l");
4354 greater_equal(0xD, "ge");
4355 less_equal(0xE, "le");
4356 greater(0xF, "g");
4357 overflow(0x0, "o");
4358 no_overflow(0x1, "no");
4359 %}
4360 %}
4361
4362 // Comparison Code, unsigned compare. Used by FP also, with
4363 // C2 (unordered) turned into GT or LT already. The other bits
4364 // C0 and C3 are turned into Carry & Zero flags.
4365 operand cmpOpU() %{
4366 match(Bool);
4367
4368 format %{ "" %}
4369 interface(COND_INTER) %{
4370 equal(0x4, "e");
4371 not_equal(0x5, "ne");
4372 less(0x2, "b");
4373 greater_equal(0x3, "nb");
4374 less_equal(0x6, "be");
4375 greater(0x7, "nbe");
4376 overflow(0x0, "o");
4377 no_overflow(0x1, "no");
4378 %}
4379 %}
4380
4381 // Floating comparisons that don't require any fixup for the unordered case
4382 operand cmpOpUCF() %{
4383 match(Bool);
4384 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4385 n->as_Bool()->_test._test == BoolTest::ge ||
4386 n->as_Bool()->_test._test == BoolTest::le ||
4387 n->as_Bool()->_test._test == BoolTest::gt);
4388 format %{ "" %}
4389 interface(COND_INTER) %{
4390 equal(0x4, "e");
4391 not_equal(0x5, "ne");
4392 less(0x2, "b");
4393 greater_equal(0x3, "nb");
4394 less_equal(0x6, "be");
4395 greater(0x7, "nbe");
4396 overflow(0x0, "o");
4397 no_overflow(0x1, "no");
4398 %}
4399 %}
4400
4401
4402 // Floating comparisons that can be fixed up with extra conditional jumps
4403 operand cmpOpUCF2() %{
4404 match(Bool);
4405 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4406 n->as_Bool()->_test._test == BoolTest::eq);
4407 format %{ "" %}
4408 interface(COND_INTER) %{
4409 equal(0x4, "e");
4410 not_equal(0x5, "ne");
4411 less(0x2, "b");
4412 greater_equal(0x3, "nb");
4413 less_equal(0x6, "be");
4414 greater(0x7, "nbe");
4415 overflow(0x0, "o");
4416 no_overflow(0x1, "no");
4417 %}
4418 %}
4419
4420 // Comparison Code for FP conditional move
4421 operand cmpOp_fcmov() %{
4422 match(Bool);
4423
4424 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4425 n->as_Bool()->_test._test != BoolTest::no_overflow);
4426 format %{ "" %}
4427 interface(COND_INTER) %{
4428 equal (0x0C8);
4429 not_equal (0x1C8);
4430 less (0x0C0);
4431 greater_equal(0x1C0);
4432 less_equal (0x0D0);
4433 greater (0x1D0);
4434 overflow(0x0, "o"); // not really supported by the instruction
4435 no_overflow(0x1, "no"); // not really supported by the instruction
4436 %}
4437 %}
4438
4439 // Comparision Code used in long compares
4440 operand cmpOp_commute() %{
4441 match(Bool);
4442
4443 format %{ "" %}
4444 interface(COND_INTER) %{
4445 equal(0x4, "e");
4446 not_equal(0x5, "ne");
4447 less(0xF, "g");
4448 greater_equal(0xE, "le");
4449 less_equal(0xD, "ge");
4450 greater(0xC, "l");
4451 overflow(0x0, "o");
4452 no_overflow(0x1, "no");
4453 %}
4454 %}
4455
4456 //----------OPERAND CLASSES----------------------------------------------------
4457 // Operand Classes are groups of operands that are used as to simplify
4458 // instruction definitions by not requiring the AD writer to specify separate
4459 // instructions for every form of operand when the instruction accepts
4460 // multiple operand types with the same basic encoding and format. The classic
4461 // case of this is memory operands.
4462
4463 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
4464 indIndex, indIndexScale, indIndexScaleOffset);
4465
4466 // Long memory operations are encoded in 2 instructions and a +4 offset.
4467 // This means some kind of offset is always required and you cannot use
4468 // an oop as the offset (done when working on static globals).
4469 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
4470 indIndex, indIndexScale, indIndexScaleOffset);
4471
4472
4473 //----------PIPELINE-----------------------------------------------------------
4474 // Rules which define the behavior of the target architectures pipeline.
4475 pipeline %{
4476
4477 //----------ATTRIBUTES---------------------------------------------------------
4478 attributes %{
4479 variable_size_instructions; // Fixed size instructions
4480 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4481 instruction_unit_size = 1; // An instruction is 1 bytes long
4482 instruction_fetch_unit_size = 16; // The processor fetches one line
4483 instruction_fetch_units = 1; // of 16 bytes
4484
4485 // List of nop instructions
4486 nops( MachNop );
4487 %}
4488
4489 //----------RESOURCES----------------------------------------------------------
4490 // Resources are the functional units available to the machine
4491
4492 // Generic P2/P3 pipeline
4493 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4494 // 3 instructions decoded per cycle.
4495 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4496 // 2 ALU op, only ALU0 handles mul/div instructions.
4497 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4498 MS0, MS1, MEM = MS0 | MS1,
4499 BR, FPU,
4500 ALU0, ALU1, ALU = ALU0 | ALU1 );
4501
4502 //----------PIPELINE DESCRIPTION-----------------------------------------------
4503 // Pipeline Description specifies the stages in the machine's pipeline
4504
4505 // Generic P2/P3 pipeline
4506 pipe_desc(S0, S1, S2, S3, S4, S5);
4507
4508 //----------PIPELINE CLASSES---------------------------------------------------
4509 // Pipeline Classes describe the stages in which input and output are
4510 // referenced by the hardware pipeline.
4511
4512 // Naming convention: ialu or fpu
4513 // Then: _reg
4514 // Then: _reg if there is a 2nd register
4515 // Then: _long if it's a pair of instructions implementing a long
4516 // Then: _fat if it requires the big decoder
4517 // Or: _mem if it requires the big decoder and a memory unit.
4518
4519 // Integer ALU reg operation
4520 pipe_class ialu_reg(rRegI dst) %{
4521 single_instruction;
4522 dst : S4(write);
4523 dst : S3(read);
4524 DECODE : S0; // any decoder
4525 ALU : S3; // any alu
4526 %}
4527
4528 // Long ALU reg operation
4529 pipe_class ialu_reg_long(eRegL dst) %{
4530 instruction_count(2);
4531 dst : S4(write);
4532 dst : S3(read);
4533 DECODE : S0(2); // any 2 decoders
4534 ALU : S3(2); // both alus
4535 %}
4536
4537 // Integer ALU reg operation using big decoder
4538 pipe_class ialu_reg_fat(rRegI dst) %{
4539 single_instruction;
4540 dst : S4(write);
4541 dst : S3(read);
4542 D0 : S0; // big decoder only
4543 ALU : S3; // any alu
4544 %}
4545
4546 // Long ALU reg operation using big decoder
4547 pipe_class ialu_reg_long_fat(eRegL dst) %{
4548 instruction_count(2);
4549 dst : S4(write);
4550 dst : S3(read);
4551 D0 : S0(2); // big decoder only; twice
4552 ALU : S3(2); // any 2 alus
4553 %}
4554
4555 // Integer ALU reg-reg operation
4556 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
4557 single_instruction;
4558 dst : S4(write);
4559 src : S3(read);
4560 DECODE : S0; // any decoder
4561 ALU : S3; // any alu
4562 %}
4563
4564 // Long ALU reg-reg operation
4565 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
4566 instruction_count(2);
4567 dst : S4(write);
4568 src : S3(read);
4569 DECODE : S0(2); // any 2 decoders
4570 ALU : S3(2); // both alus
4571 %}
4572
4573 // Integer ALU reg-reg operation
4574 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
4575 single_instruction;
4576 dst : S4(write);
4577 src : S3(read);
4578 D0 : S0; // big decoder only
4579 ALU : S3; // any alu
4580 %}
4581
4582 // Long ALU reg-reg operation
4583 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
4584 instruction_count(2);
4585 dst : S4(write);
4586 src : S3(read);
4587 D0 : S0(2); // big decoder only; twice
4588 ALU : S3(2); // both alus
4589 %}
4590
4591 // Integer ALU reg-mem operation
4592 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
4593 single_instruction;
4594 dst : S5(write);
4595 mem : S3(read);
4596 D0 : S0; // big decoder only
4597 ALU : S4; // any alu
4598 MEM : S3; // any mem
4599 %}
4600
4601 // Long ALU reg-mem operation
4602 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
4603 instruction_count(2);
4604 dst : S5(write);
4605 mem : S3(read);
4606 D0 : S0(2); // big decoder only; twice
4607 ALU : S4(2); // any 2 alus
4608 MEM : S3(2); // both mems
4609 %}
4610
4611 // Integer mem operation (prefetch)
4612 pipe_class ialu_mem(memory mem)
4613 %{
4614 single_instruction;
4615 mem : S3(read);
4616 D0 : S0; // big decoder only
4617 MEM : S3; // any mem
4618 %}
4619
4620 // Integer Store to Memory
4621 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
4622 single_instruction;
4623 mem : S3(read);
4624 src : S5(read);
4625 D0 : S0; // big decoder only
4626 ALU : S4; // any alu
4627 MEM : S3;
4628 %}
4629
4630 // Long Store to Memory
4631 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
4632 instruction_count(2);
4633 mem : S3(read);
4634 src : S5(read);
4635 D0 : S0(2); // big decoder only; twice
4636 ALU : S4(2); // any 2 alus
4637 MEM : S3(2); // Both mems
4638 %}
4639
4640 // Integer Store to Memory
4641 pipe_class ialu_mem_imm(memory mem) %{
4642 single_instruction;
4643 mem : S3(read);
4644 D0 : S0; // big decoder only
4645 ALU : S4; // any alu
4646 MEM : S3;
4647 %}
4648
4649 // Integer ALU0 reg-reg operation
4650 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
4651 single_instruction;
4652 dst : S4(write);
4653 src : S3(read);
4654 D0 : S0; // Big decoder only
4655 ALU0 : S3; // only alu0
4656 %}
4657
4658 // Integer ALU0 reg-mem operation
4659 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
4660 single_instruction;
4661 dst : S5(write);
4662 mem : S3(read);
4663 D0 : S0; // big decoder only
4664 ALU0 : S4; // ALU0 only
4665 MEM : S3; // any mem
4666 %}
4667
4668 // Integer ALU reg-reg operation
4669 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
4670 single_instruction;
4671 cr : S4(write);
4672 src1 : S3(read);
4673 src2 : S3(read);
4674 DECODE : S0; // any decoder
4675 ALU : S3; // any alu
4676 %}
4677
4678 // Integer ALU reg-imm operation
4679 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
4680 single_instruction;
4681 cr : S4(write);
4682 src1 : S3(read);
4683 DECODE : S0; // any decoder
4684 ALU : S3; // any alu
4685 %}
4686
4687 // Integer ALU reg-mem operation
4688 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
4689 single_instruction;
4690 cr : S4(write);
4691 src1 : S3(read);
4692 src2 : S3(read);
4693 D0 : S0; // big decoder only
4694 ALU : S4; // any alu
4695 MEM : S3;
4696 %}
4697
4698 // Conditional move reg-reg
4699 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
4700 instruction_count(4);
4701 y : S4(read);
4702 q : S3(read);
4703 p : S3(read);
4704 DECODE : S0(4); // any decoder
4705 %}
4706
4707 // Conditional move reg-reg
4708 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
4709 single_instruction;
4710 dst : S4(write);
4711 src : S3(read);
4712 cr : S3(read);
4713 DECODE : S0; // any decoder
4714 %}
4715
4716 // Conditional move reg-mem
4717 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
4718 single_instruction;
4719 dst : S4(write);
4720 src : S3(read);
4721 cr : S3(read);
4722 DECODE : S0; // any decoder
4723 MEM : S3;
4724 %}
4725
4726 // Conditional move reg-reg long
4727 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
4728 single_instruction;
4729 dst : S4(write);
4730 src : S3(read);
4731 cr : S3(read);
4732 DECODE : S0(2); // any 2 decoders
4733 %}
4734
4735 // Conditional move double reg-reg
4736 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
4737 single_instruction;
4738 dst : S4(write);
4739 src : S3(read);
4740 cr : S3(read);
4741 DECODE : S0; // any decoder
4742 %}
4743
4744 // Float reg-reg operation
4745 pipe_class fpu_reg(regDPR dst) %{
4746 instruction_count(2);
4747 dst : S3(read);
4748 DECODE : S0(2); // any 2 decoders
4749 FPU : S3;
4750 %}
4751
4752 // Float reg-reg operation
4753 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
4754 instruction_count(2);
4755 dst : S4(write);
4756 src : S3(read);
4757 DECODE : S0(2); // any 2 decoders
4758 FPU : S3;
4759 %}
4760
4761 // Float reg-reg operation
4762 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
4763 instruction_count(3);
4764 dst : S4(write);
4765 src1 : S3(read);
4766 src2 : S3(read);
4767 DECODE : S0(3); // any 3 decoders
4768 FPU : S3(2);
4769 %}
4770
4771 // Float reg-reg operation
4772 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
4773 instruction_count(4);
4774 dst : S4(write);
4775 src1 : S3(read);
4776 src2 : S3(read);
4777 src3 : S3(read);
4778 DECODE : S0(4); // any 3 decoders
4779 FPU : S3(2);
4780 %}
4781
4782 // Float reg-reg operation
4783 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
4784 instruction_count(4);
4785 dst : S4(write);
4786 src1 : S3(read);
4787 src2 : S3(read);
4788 src3 : S3(read);
4789 DECODE : S1(3); // any 3 decoders
4790 D0 : S0; // Big decoder only
4791 FPU : S3(2);
4792 MEM : S3;
4793 %}
4794
4795 // Float reg-mem operation
4796 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
4797 instruction_count(2);
4798 dst : S5(write);
4799 mem : S3(read);
4800 D0 : S0; // big decoder only
4801 DECODE : S1; // any decoder for FPU POP
4802 FPU : S4;
4803 MEM : S3; // any mem
4804 %}
4805
4806 // Float reg-mem operation
4807 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
4808 instruction_count(3);
4809 dst : S5(write);
4810 src1 : S3(read);
4811 mem : S3(read);
4812 D0 : S0; // big decoder only
4813 DECODE : S1(2); // any decoder for FPU POP
4814 FPU : S4;
4815 MEM : S3; // any mem
4816 %}
4817
4818 // Float mem-reg operation
4819 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
4820 instruction_count(2);
4821 src : S5(read);
4822 mem : S3(read);
4823 DECODE : S0; // any decoder for FPU PUSH
4824 D0 : S1; // big decoder only
4825 FPU : S4;
4826 MEM : S3; // any mem
4827 %}
4828
4829 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
4830 instruction_count(3);
4831 src1 : S3(read);
4832 src2 : S3(read);
4833 mem : S3(read);
4834 DECODE : S0(2); // any decoder for FPU PUSH
4835 D0 : S1; // big decoder only
4836 FPU : S4;
4837 MEM : S3; // any mem
4838 %}
4839
4840 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
4841 instruction_count(3);
4842 src1 : S3(read);
4843 src2 : S3(read);
4844 mem : S4(read);
4845 DECODE : S0; // any decoder for FPU PUSH
4846 D0 : S0(2); // big decoder only
4847 FPU : S4;
4848 MEM : S3(2); // any mem
4849 %}
4850
4851 pipe_class fpu_mem_mem(memory dst, memory src1) %{
4852 instruction_count(2);
4853 src1 : S3(read);
4854 dst : S4(read);
4855 D0 : S0(2); // big decoder only
4856 MEM : S3(2); // any mem
4857 %}
4858
4859 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
4860 instruction_count(3);
4861 src1 : S3(read);
4862 src2 : S3(read);
4863 dst : S4(read);
4864 D0 : S0(3); // big decoder only
4865 FPU : S4;
4866 MEM : S3(3); // any mem
4867 %}
4868
4869 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
4870 instruction_count(3);
4871 src1 : S4(read);
4872 mem : S4(read);
4873 DECODE : S0; // any decoder for FPU PUSH
4874 D0 : S0(2); // big decoder only
4875 FPU : S4;
4876 MEM : S3(2); // any mem
4877 %}
4878
4879 // Float load constant
4880 pipe_class fpu_reg_con(regDPR dst) %{
4881 instruction_count(2);
4882 dst : S5(write);
4883 D0 : S0; // big decoder only for the load
4884 DECODE : S1; // any decoder for FPU POP
4885 FPU : S4;
4886 MEM : S3; // any mem
4887 %}
4888
4889 // Float load constant
4890 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
4891 instruction_count(3);
4892 dst : S5(write);
4893 src : S3(read);
4894 D0 : S0; // big decoder only for the load
4895 DECODE : S1(2); // any decoder for FPU POP
4896 FPU : S4;
4897 MEM : S3; // any mem
4898 %}
4899
4900 // UnConditional branch
4901 pipe_class pipe_jmp( label labl ) %{
4902 single_instruction;
4903 BR : S3;
4904 %}
4905
4906 // Conditional branch
4907 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
4908 single_instruction;
4909 cr : S1(read);
4910 BR : S3;
4911 %}
4912
4913 // Allocation idiom
4914 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
4915 instruction_count(1); force_serialization;
4916 fixed_latency(6);
4917 heap_ptr : S3(read);
4918 DECODE : S0(3);
4919 D0 : S2;
4920 MEM : S3;
4921 ALU : S3(2);
4922 dst : S5(write);
4923 BR : S5;
4924 %}
4925
4926 // Generic big/slow expanded idiom
4927 pipe_class pipe_slow( ) %{
4928 instruction_count(10); multiple_bundles; force_serialization;
4929 fixed_latency(100);
4930 D0 : S0(2);
4931 MEM : S3(2);
4932 %}
4933
4934 // The real do-nothing guy
4935 pipe_class empty( ) %{
4936 instruction_count(0);
4937 %}
4938
4939 // Define the class for the Nop node
4940 define %{
4941 MachNop = empty;
4942 %}
4943
4944 %}
4945
4946 //----------INSTRUCTIONS-------------------------------------------------------
4947 //
4948 // match -- States which machine-independent subtree may be replaced
4949 // by this instruction.
4950 // ins_cost -- The estimated cost of this instruction is used by instruction
4951 // selection to identify a minimum cost tree of machine
4952 // instructions that matches a tree of machine-independent
4953 // instructions.
4954 // format -- A string providing the disassembly for this instruction.
4955 // The value of an instruction's operand may be inserted
4956 // by referring to it with a '$' prefix.
4957 // opcode -- Three instruction opcodes may be provided. These are referred
4958 // to within an encode class as $primary, $secondary, and $tertiary
4959 // respectively. The primary opcode is commonly used to
4960 // indicate the type of machine instruction, while secondary
4961 // and tertiary are often used for prefix options or addressing
4962 // modes.
4963 // ins_encode -- A list of encode classes with parameters. The encode class
4964 // name must have been defined in an 'enc_class' specification
4965 // in the encode section of the architecture description.
4966
4967 //----------BSWAP-Instruction--------------------------------------------------
4968 instruct bytes_reverse_int(rRegI dst) %{
4969 match(Set dst (ReverseBytesI dst));
4970
4971 format %{ "BSWAP $dst" %}
4972 opcode(0x0F, 0xC8);
4973 ins_encode( OpcP, OpcSReg(dst) );
4974 ins_pipe( ialu_reg );
4975 %}
4976
4977 instruct bytes_reverse_long(eRegL dst) %{
4978 match(Set dst (ReverseBytesL dst));
4979
4980 format %{ "BSWAP $dst.lo\n\t"
4981 "BSWAP $dst.hi\n\t"
4982 "XCHG $dst.lo $dst.hi" %}
4983
4984 ins_cost(125);
4985 ins_encode( bswap_long_bytes(dst) );
4986 ins_pipe( ialu_reg_reg);
4987 %}
4988
4989 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
4990 match(Set dst (ReverseBytesUS dst));
4991 effect(KILL cr);
4992
4993 format %{ "BSWAP $dst\n\t"
4994 "SHR $dst,16\n\t" %}
4995 ins_encode %{
4996 __ bswapl($dst$$Register);
4997 __ shrl($dst$$Register, 16);
4998 %}
4999 ins_pipe( ialu_reg );
5000 %}
5001
5002 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5003 match(Set dst (ReverseBytesS dst));
5004 effect(KILL cr);
5005
5006 format %{ "BSWAP $dst\n\t"
5007 "SAR $dst,16\n\t" %}
5008 ins_encode %{
5009 __ bswapl($dst$$Register);
5010 __ sarl($dst$$Register, 16);
5011 %}
5012 ins_pipe( ialu_reg );
5013 %}
5014
5015
5016 //---------- Zeros Count Instructions ------------------------------------------
5017
5018 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5019 predicate(UseCountLeadingZerosInstruction);
5020 match(Set dst (CountLeadingZerosI src));
5021 effect(KILL cr);
5022
5023 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5024 ins_encode %{
5025 __ lzcntl($dst$$Register, $src$$Register);
5026 %}
5027 ins_pipe(ialu_reg);
5028 %}
5029
5030 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5031 predicate(!UseCountLeadingZerosInstruction);
5032 match(Set dst (CountLeadingZerosI src));
5033 effect(KILL cr);
5034
5035 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5036 "JNZ skip\n\t"
5037 "MOV $dst, -1\n"
5038 "skip:\n\t"
5039 "NEG $dst\n\t"
5040 "ADD $dst, 31" %}
5041 ins_encode %{
5042 Register Rdst = $dst$$Register;
5043 Register Rsrc = $src$$Register;
5044 Label skip;
5045 __ bsrl(Rdst, Rsrc);
5046 __ jccb(Assembler::notZero, skip);
5047 __ movl(Rdst, -1);
5048 __ bind(skip);
5049 __ negl(Rdst);
5050 __ addl(Rdst, BitsPerInt - 1);
5051 %}
5052 ins_pipe(ialu_reg);
5053 %}
5054
5055 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5056 predicate(UseCountLeadingZerosInstruction);
5057 match(Set dst (CountLeadingZerosL src));
5058 effect(TEMP dst, KILL cr);
5059
5060 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5061 "JNC done\n\t"
5062 "LZCNT $dst, $src.lo\n\t"
5063 "ADD $dst, 32\n"
5064 "done:" %}
5065 ins_encode %{
5066 Register Rdst = $dst$$Register;
5067 Register Rsrc = $src$$Register;
5068 Label done;
5069 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5070 __ jccb(Assembler::carryClear, done);
5071 __ lzcntl(Rdst, Rsrc);
5072 __ addl(Rdst, BitsPerInt);
5073 __ bind(done);
5074 %}
5075 ins_pipe(ialu_reg);
5076 %}
5077
5078 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5079 predicate(!UseCountLeadingZerosInstruction);
5080 match(Set dst (CountLeadingZerosL src));
5081 effect(TEMP dst, KILL cr);
5082
5083 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5084 "JZ msw_is_zero\n\t"
5085 "ADD $dst, 32\n\t"
5086 "JMP not_zero\n"
5087 "msw_is_zero:\n\t"
5088 "BSR $dst, $src.lo\n\t"
5089 "JNZ not_zero\n\t"
5090 "MOV $dst, -1\n"
5091 "not_zero:\n\t"
5092 "NEG $dst\n\t"
5093 "ADD $dst, 63\n" %}
5094 ins_encode %{
5095 Register Rdst = $dst$$Register;
5096 Register Rsrc = $src$$Register;
5097 Label msw_is_zero;
5098 Label not_zero;
5099 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5100 __ jccb(Assembler::zero, msw_is_zero);
5101 __ addl(Rdst, BitsPerInt);
5102 __ jmpb(not_zero);
5103 __ bind(msw_is_zero);
5104 __ bsrl(Rdst, Rsrc);
5105 __ jccb(Assembler::notZero, not_zero);
5106 __ movl(Rdst, -1);
5107 __ bind(not_zero);
5108 __ negl(Rdst);
5109 __ addl(Rdst, BitsPerLong - 1);
5110 %}
5111 ins_pipe(ialu_reg);
5112 %}
5113
5114 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5115 predicate(UseCountTrailingZerosInstruction);
5116 match(Set dst (CountTrailingZerosI src));
5117 effect(KILL cr);
5118
5119 format %{ "TZCNT $dst, $src\t# count trailing zeros (int)" %}
5120 ins_encode %{
5121 __ tzcntl($dst$$Register, $src$$Register);
5122 %}
5123 ins_pipe(ialu_reg);
5124 %}
5125
5126 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, eFlagsReg cr) %{
5127 predicate(!UseCountTrailingZerosInstruction);
5128 match(Set dst (CountTrailingZerosI src));
5129 effect(KILL cr);
5130
5131 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5132 "JNZ done\n\t"
5133 "MOV $dst, 32\n"
5134 "done:" %}
5135 ins_encode %{
5136 Register Rdst = $dst$$Register;
5137 Label done;
5138 __ bsfl(Rdst, $src$$Register);
5139 __ jccb(Assembler::notZero, done);
5140 __ movl(Rdst, BitsPerInt);
5141 __ bind(done);
5142 %}
5143 ins_pipe(ialu_reg);
5144 %}
5145
5146 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5147 predicate(UseCountTrailingZerosInstruction);
5148 match(Set dst (CountTrailingZerosL src));
5149 effect(TEMP dst, KILL cr);
5150
5151 format %{ "TZCNT $dst, $src.lo\t# count trailing zeros (long) \n\t"
5152 "JNC done\n\t"
5153 "TZCNT $dst, $src.hi\n\t"
5154 "ADD $dst, 32\n"
5155 "done:" %}
5156 ins_encode %{
5157 Register Rdst = $dst$$Register;
5158 Register Rsrc = $src$$Register;
5159 Label done;
5160 __ tzcntl(Rdst, Rsrc);
5161 __ jccb(Assembler::carryClear, done);
5162 __ tzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5163 __ addl(Rdst, BitsPerInt);
5164 __ bind(done);
5165 %}
5166 ins_pipe(ialu_reg);
5167 %}
5168
5169 instruct countTrailingZerosL_bsf(rRegI dst, eRegL src, eFlagsReg cr) %{
5170 predicate(!UseCountTrailingZerosInstruction);
5171 match(Set dst (CountTrailingZerosL src));
5172 effect(TEMP dst, KILL cr);
5173
5174 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5175 "JNZ done\n\t"
5176 "BSF $dst, $src.hi\n\t"
5177 "JNZ msw_not_zero\n\t"
5178 "MOV $dst, 32\n"
5179 "msw_not_zero:\n\t"
5180 "ADD $dst, 32\n"
5181 "done:" %}
5182 ins_encode %{
5183 Register Rdst = $dst$$Register;
5184 Register Rsrc = $src$$Register;
5185 Label msw_not_zero;
5186 Label done;
5187 __ bsfl(Rdst, Rsrc);
5188 __ jccb(Assembler::notZero, done);
5189 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5190 __ jccb(Assembler::notZero, msw_not_zero);
5191 __ movl(Rdst, BitsPerInt);
5192 __ bind(msw_not_zero);
5193 __ addl(Rdst, BitsPerInt);
5194 __ bind(done);
5195 %}
5196 ins_pipe(ialu_reg);
5197 %}
5198
5199
5200 //---------- Population Count Instructions -------------------------------------
5201
5202 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5203 predicate(UsePopCountInstruction);
5204 match(Set dst (PopCountI src));
5205 effect(KILL cr);
5206
5207 format %{ "POPCNT $dst, $src" %}
5208 ins_encode %{
5209 __ popcntl($dst$$Register, $src$$Register);
5210 %}
5211 ins_pipe(ialu_reg);
5212 %}
5213
5214 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5215 predicate(UsePopCountInstruction);
5216 match(Set dst (PopCountI (LoadI mem)));
5217 effect(KILL cr);
5218
5219 format %{ "POPCNT $dst, $mem" %}
5220 ins_encode %{
5221 __ popcntl($dst$$Register, $mem$$Address);
5222 %}
5223 ins_pipe(ialu_reg);
5224 %}
5225
5226 // Note: Long.bitCount(long) returns an int.
5227 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5228 predicate(UsePopCountInstruction);
5229 match(Set dst (PopCountL src));
5230 effect(KILL cr, TEMP tmp, TEMP dst);
5231
5232 format %{ "POPCNT $dst, $src.lo\n\t"
5233 "POPCNT $tmp, $src.hi\n\t"
5234 "ADD $dst, $tmp" %}
5235 ins_encode %{
5236 __ popcntl($dst$$Register, $src$$Register);
5237 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5238 __ addl($dst$$Register, $tmp$$Register);
5239 %}
5240 ins_pipe(ialu_reg);
5241 %}
5242
5243 // Note: Long.bitCount(long) returns an int.
5244 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5245 predicate(UsePopCountInstruction);
5246 match(Set dst (PopCountL (LoadL mem)));
5247 effect(KILL cr, TEMP tmp, TEMP dst);
5248
5249 format %{ "POPCNT $dst, $mem\n\t"
5250 "POPCNT $tmp, $mem+4\n\t"
5251 "ADD $dst, $tmp" %}
5252 ins_encode %{
5253 //__ popcntl($dst$$Register, $mem$$Address$$first);
5254 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5255 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5256 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5257 __ addl($dst$$Register, $tmp$$Register);
5258 %}
5259 ins_pipe(ialu_reg);
5260 %}
5261
5262
5263 //----------Load/Store/Move Instructions---------------------------------------
5264 //----------Load Instructions--------------------------------------------------
5265 // Load Byte (8bit signed)
5266 instruct loadB(xRegI dst, memory mem) %{
5267 match(Set dst (LoadB mem));
5268
5269 ins_cost(125);
5270 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5271
5272 ins_encode %{
5273 __ movsbl($dst$$Register, $mem$$Address);
5274 %}
5275
5276 ins_pipe(ialu_reg_mem);
5277 %}
5278
5279 // Load Byte (8bit signed) into Long Register
5280 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5281 match(Set dst (ConvI2L (LoadB mem)));
5282 effect(KILL cr);
5283
5284 ins_cost(375);
5285 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5286 "MOV $dst.hi,$dst.lo\n\t"
5287 "SAR $dst.hi,7" %}
5288
5289 ins_encode %{
5290 __ movsbl($dst$$Register, $mem$$Address);
5291 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5292 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5293 %}
5294
5295 ins_pipe(ialu_reg_mem);
5296 %}
5297
5298 // Load Unsigned Byte (8bit UNsigned)
5299 instruct loadUB(xRegI dst, memory mem) %{
5300 match(Set dst (LoadUB mem));
5301
5302 ins_cost(125);
5303 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5304
5305 ins_encode %{
5306 __ movzbl($dst$$Register, $mem$$Address);
5307 %}
5308
5309 ins_pipe(ialu_reg_mem);
5310 %}
5311
5312 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5313 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5314 match(Set dst (ConvI2L (LoadUB mem)));
5315 effect(KILL cr);
5316
5317 ins_cost(250);
5318 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5319 "XOR $dst.hi,$dst.hi" %}
5320
5321 ins_encode %{
5322 Register Rdst = $dst$$Register;
5323 __ movzbl(Rdst, $mem$$Address);
5324 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5325 %}
5326
5327 ins_pipe(ialu_reg_mem);
5328 %}
5329
5330 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5331 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5332 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5333 effect(KILL cr);
5334
5335 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5336 "XOR $dst.hi,$dst.hi\n\t"
5337 "AND $dst.lo,$mask" %}
5338 ins_encode %{
5339 Register Rdst = $dst$$Register;
5340 __ movzbl(Rdst, $mem$$Address);
5341 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5342 __ andl(Rdst, $mask$$constant);
5343 %}
5344 ins_pipe(ialu_reg_mem);
5345 %}
5346
5347 // Load Short (16bit signed)
5348 instruct loadS(rRegI dst, memory mem) %{
5349 match(Set dst (LoadS mem));
5350
5351 ins_cost(125);
5352 format %{ "MOVSX $dst,$mem\t# short" %}
5353
5354 ins_encode %{
5355 __ movswl($dst$$Register, $mem$$Address);
5356 %}
5357
5358 ins_pipe(ialu_reg_mem);
5359 %}
5360
5361 // Load Short (16 bit signed) to Byte (8 bit signed)
5362 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5363 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5364
5365 ins_cost(125);
5366 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5367 ins_encode %{
5368 __ movsbl($dst$$Register, $mem$$Address);
5369 %}
5370 ins_pipe(ialu_reg_mem);
5371 %}
5372
5373 // Load Short (16bit signed) into Long Register
5374 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5375 match(Set dst (ConvI2L (LoadS mem)));
5376 effect(KILL cr);
5377
5378 ins_cost(375);
5379 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5380 "MOV $dst.hi,$dst.lo\n\t"
5381 "SAR $dst.hi,15" %}
5382
5383 ins_encode %{
5384 __ movswl($dst$$Register, $mem$$Address);
5385 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5386 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5387 %}
5388
5389 ins_pipe(ialu_reg_mem);
5390 %}
5391
5392 // Load Unsigned Short/Char (16bit unsigned)
5393 instruct loadUS(rRegI dst, memory mem) %{
5394 match(Set dst (LoadUS mem));
5395
5396 ins_cost(125);
5397 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5398
5399 ins_encode %{
5400 __ movzwl($dst$$Register, $mem$$Address);
5401 %}
5402
5403 ins_pipe(ialu_reg_mem);
5404 %}
5405
5406 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5407 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5408 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5409
5410 ins_cost(125);
5411 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5412 ins_encode %{
5413 __ movsbl($dst$$Register, $mem$$Address);
5414 %}
5415 ins_pipe(ialu_reg_mem);
5416 %}
5417
5418 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5419 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5420 match(Set dst (ConvI2L (LoadUS mem)));
5421 effect(KILL cr);
5422
5423 ins_cost(250);
5424 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5425 "XOR $dst.hi,$dst.hi" %}
5426
5427 ins_encode %{
5428 __ movzwl($dst$$Register, $mem$$Address);
5429 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5430 %}
5431
5432 ins_pipe(ialu_reg_mem);
5433 %}
5434
5435 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5436 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5437 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5438 effect(KILL cr);
5439
5440 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5441 "XOR $dst.hi,$dst.hi" %}
5442 ins_encode %{
5443 Register Rdst = $dst$$Register;
5444 __ movzbl(Rdst, $mem$$Address);
5445 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5446 %}
5447 ins_pipe(ialu_reg_mem);
5448 %}
5449
5450 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
5451 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
5452 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5453 effect(KILL cr);
5454
5455 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5456 "XOR $dst.hi,$dst.hi\n\t"
5457 "AND $dst.lo,$mask" %}
5458 ins_encode %{
5459 Register Rdst = $dst$$Register;
5460 __ movzwl(Rdst, $mem$$Address);
5461 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5462 __ andl(Rdst, $mask$$constant);
5463 %}
5464 ins_pipe(ialu_reg_mem);
5465 %}
5466
5467 // Load Integer
5468 instruct loadI(rRegI dst, memory mem) %{
5469 match(Set dst (LoadI mem));
5470
5471 ins_cost(125);
5472 format %{ "MOV $dst,$mem\t# int" %}
5473
5474 ins_encode %{
5475 __ movl($dst$$Register, $mem$$Address);
5476 %}
5477
5478 ins_pipe(ialu_reg_mem);
5479 %}
5480
5481 // Load Integer (32 bit signed) to Byte (8 bit signed)
5482 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5483 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5484
5485 ins_cost(125);
5486 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
5487 ins_encode %{
5488 __ movsbl($dst$$Register, $mem$$Address);
5489 %}
5490 ins_pipe(ialu_reg_mem);
5491 %}
5492
5493 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5494 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5495 match(Set dst (AndI (LoadI mem) mask));
5496
5497 ins_cost(125);
5498 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
5499 ins_encode %{
5500 __ movzbl($dst$$Register, $mem$$Address);
5501 %}
5502 ins_pipe(ialu_reg_mem);
5503 %}
5504
5505 // Load Integer (32 bit signed) to Short (16 bit signed)
5506 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5507 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5508
5509 ins_cost(125);
5510 format %{ "MOVSX $dst, $mem\t# int -> short" %}
5511 ins_encode %{
5512 __ movswl($dst$$Register, $mem$$Address);
5513 %}
5514 ins_pipe(ialu_reg_mem);
5515 %}
5516
5517 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5518 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5519 match(Set dst (AndI (LoadI mem) mask));
5520
5521 ins_cost(125);
5522 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
5523 ins_encode %{
5524 __ movzwl($dst$$Register, $mem$$Address);
5525 %}
5526 ins_pipe(ialu_reg_mem);
5527 %}
5528
5529 // Load Integer into Long Register
5530 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
5531 match(Set dst (ConvI2L (LoadI mem)));
5532 effect(KILL cr);
5533
5534 ins_cost(375);
5535 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
5536 "MOV $dst.hi,$dst.lo\n\t"
5537 "SAR $dst.hi,31" %}
5538
5539 ins_encode %{
5540 __ movl($dst$$Register, $mem$$Address);
5541 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5542 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
5543 %}
5544
5545 ins_pipe(ialu_reg_mem);
5546 %}
5547
5548 // Load Integer with mask 0xFF into Long Register
5549 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5550 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5551 effect(KILL cr);
5552
5553 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
5554 "XOR $dst.hi,$dst.hi" %}
5555 ins_encode %{
5556 Register Rdst = $dst$$Register;
5557 __ movzbl(Rdst, $mem$$Address);
5558 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5559 %}
5560 ins_pipe(ialu_reg_mem);
5561 %}
5562
5563 // Load Integer with mask 0xFFFF into Long Register
5564 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
5565 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5566 effect(KILL cr);
5567
5568 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
5569 "XOR $dst.hi,$dst.hi" %}
5570 ins_encode %{
5571 Register Rdst = $dst$$Register;
5572 __ movzwl(Rdst, $mem$$Address);
5573 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5574 %}
5575 ins_pipe(ialu_reg_mem);
5576 %}
5577
5578 // Load Integer with 31-bit mask into Long Register
5579 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
5580 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5581 effect(KILL cr);
5582
5583 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
5584 "XOR $dst.hi,$dst.hi\n\t"
5585 "AND $dst.lo,$mask" %}
5586 ins_encode %{
5587 Register Rdst = $dst$$Register;
5588 __ movl(Rdst, $mem$$Address);
5589 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5590 __ andl(Rdst, $mask$$constant);
5591 %}
5592 ins_pipe(ialu_reg_mem);
5593 %}
5594
5595 // Load Unsigned Integer into Long Register
5596 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
5597 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5598 effect(KILL cr);
5599
5600 ins_cost(250);
5601 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
5602 "XOR $dst.hi,$dst.hi" %}
5603
5604 ins_encode %{
5605 __ movl($dst$$Register, $mem$$Address);
5606 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5607 %}
5608
5609 ins_pipe(ialu_reg_mem);
5610 %}
5611
5612 // Load Long. Cannot clobber address while loading, so restrict address
5613 // register to ESI
5614 instruct loadL(eRegL dst, load_long_memory mem) %{
5615 predicate(!((LoadLNode*)n)->require_atomic_access());
5616 match(Set dst (LoadL mem));
5617
5618 ins_cost(250);
5619 format %{ "MOV $dst.lo,$mem\t# long\n\t"
5620 "MOV $dst.hi,$mem+4" %}
5621
5622 ins_encode %{
5623 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
5624 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
5625 __ movl($dst$$Register, Amemlo);
5626 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
5627 %}
5628
5629 ins_pipe(ialu_reg_long_mem);
5630 %}
5631
5632 // Volatile Load Long. Must be atomic, so do 64-bit FILD
5633 // then store it down to the stack and reload on the int
5634 // side.
5635 instruct loadL_volatile(stackSlotL dst, memory mem) %{
5636 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
5637 match(Set dst (LoadL mem));
5638
5639 ins_cost(200);
5640 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
5641 "FISTp $dst" %}
5642 ins_encode(enc_loadL_volatile(mem,dst));
5643 ins_pipe( fpu_reg_mem );
5644 %}
5645
5646 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
5647 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
5648 match(Set dst (LoadL mem));
5649 effect(TEMP tmp);
5650 ins_cost(180);
5651 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
5652 "MOVSD $dst,$tmp" %}
5653 ins_encode %{
5654 __ movdbl($tmp$$XMMRegister, $mem$$Address);
5655 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
5656 %}
5657 ins_pipe( pipe_slow );
5658 %}
5659
5660 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
5661 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
5662 match(Set dst (LoadL mem));
5663 effect(TEMP tmp);
5664 ins_cost(160);
5665 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
5666 "MOVD $dst.lo,$tmp\n\t"
5667 "PSRLQ $tmp,32\n\t"
5668 "MOVD $dst.hi,$tmp" %}
5669 ins_encode %{
5670 __ movdbl($tmp$$XMMRegister, $mem$$Address);
5671 __ movdl($dst$$Register, $tmp$$XMMRegister);
5672 __ psrlq($tmp$$XMMRegister, 32);
5673 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
5674 %}
5675 ins_pipe( pipe_slow );
5676 %}
5677
5678 // Load Range
5679 instruct loadRange(rRegI dst, memory mem) %{
5680 match(Set dst (LoadRange mem));
5681
5682 ins_cost(125);
5683 format %{ "MOV $dst,$mem" %}
5684 opcode(0x8B);
5685 ins_encode( OpcP, RegMem(dst,mem));
5686 ins_pipe( ialu_reg_mem );
5687 %}
5688
5689
5690 // Load Pointer
5691 instruct loadP(eRegP dst, memory mem) %{
5692 match(Set dst (LoadP mem));
5693
5694 ins_cost(125);
5695 format %{ "MOV $dst,$mem" %}
5696 opcode(0x8B);
5697 ins_encode( OpcP, RegMem(dst,mem));
5698 ins_pipe( ialu_reg_mem );
5699 %}
5700
5701 // Load Klass Pointer
5702 instruct loadKlass(eRegP dst, memory mem) %{
5703 match(Set dst (LoadKlass mem));
5704
5705 ins_cost(125);
5706 format %{ "MOV $dst,$mem" %}
5707 opcode(0x8B);
5708 ins_encode( OpcP, RegMem(dst,mem));
5709 ins_pipe( ialu_reg_mem );
5710 %}
5711
5712 // Load Double
5713 instruct loadDPR(regDPR dst, memory mem) %{
5714 predicate(UseSSE<=1);
5715 match(Set dst (LoadD mem));
5716
5717 ins_cost(150);
5718 format %{ "FLD_D ST,$mem\n\t"
5719 "FSTP $dst" %}
5720 opcode(0xDD); /* DD /0 */
5721 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5722 Pop_Reg_DPR(dst) );
5723 ins_pipe( fpu_reg_mem );
5724 %}
5725
5726 // Load Double to XMM
5727 instruct loadD(regD dst, memory mem) %{
5728 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
5729 match(Set dst (LoadD mem));
5730 ins_cost(145);
5731 format %{ "MOVSD $dst,$mem" %}
5732 ins_encode %{
5733 __ movdbl ($dst$$XMMRegister, $mem$$Address);
5734 %}
5735 ins_pipe( pipe_slow );
5736 %}
5737
5738 instruct loadD_partial(regD dst, memory mem) %{
5739 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
5740 match(Set dst (LoadD mem));
5741 ins_cost(145);
5742 format %{ "MOVLPD $dst,$mem" %}
5743 ins_encode %{
5744 __ movdbl ($dst$$XMMRegister, $mem$$Address);
5745 %}
5746 ins_pipe( pipe_slow );
5747 %}
5748
5749 // Load to XMM register (single-precision floating point)
5750 // MOVSS instruction
5751 instruct loadF(regF dst, memory mem) %{
5752 predicate(UseSSE>=1);
5753 match(Set dst (LoadF mem));
5754 ins_cost(145);
5755 format %{ "MOVSS $dst,$mem" %}
5756 ins_encode %{
5757 __ movflt ($dst$$XMMRegister, $mem$$Address);
5758 %}
5759 ins_pipe( pipe_slow );
5760 %}
5761
5762 // Load Float
5763 instruct loadFPR(regFPR dst, memory mem) %{
5764 predicate(UseSSE==0);
5765 match(Set dst (LoadF mem));
5766
5767 ins_cost(150);
5768 format %{ "FLD_S ST,$mem\n\t"
5769 "FSTP $dst" %}
5770 opcode(0xD9); /* D9 /0 */
5771 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5772 Pop_Reg_FPR(dst) );
5773 ins_pipe( fpu_reg_mem );
5774 %}
5775
5776 // Load Effective Address
5777 instruct leaP8(eRegP dst, indOffset8 mem) %{
5778 match(Set dst mem);
5779
5780 ins_cost(110);
5781 format %{ "LEA $dst,$mem" %}
5782 opcode(0x8D);
5783 ins_encode( OpcP, RegMem(dst,mem));
5784 ins_pipe( ialu_reg_reg_fat );
5785 %}
5786
5787 instruct leaP32(eRegP dst, indOffset32 mem) %{
5788 match(Set dst mem);
5789
5790 ins_cost(110);
5791 format %{ "LEA $dst,$mem" %}
5792 opcode(0x8D);
5793 ins_encode( OpcP, RegMem(dst,mem));
5794 ins_pipe( ialu_reg_reg_fat );
5795 %}
5796
5797 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
5798 match(Set dst mem);
5799
5800 ins_cost(110);
5801 format %{ "LEA $dst,$mem" %}
5802 opcode(0x8D);
5803 ins_encode( OpcP, RegMem(dst,mem));
5804 ins_pipe( ialu_reg_reg_fat );
5805 %}
5806
5807 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
5808 match(Set dst mem);
5809
5810 ins_cost(110);
5811 format %{ "LEA $dst,$mem" %}
5812 opcode(0x8D);
5813 ins_encode( OpcP, RegMem(dst,mem));
5814 ins_pipe( ialu_reg_reg_fat );
5815 %}
5816
5817 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
5818 match(Set dst mem);
5819
5820 ins_cost(110);
5821 format %{ "LEA $dst,$mem" %}
5822 opcode(0x8D);
5823 ins_encode( OpcP, RegMem(dst,mem));
5824 ins_pipe( ialu_reg_reg_fat );
5825 %}
5826
5827 // Load Constant
5828 instruct loadConI(rRegI dst, immI src) %{
5829 match(Set dst src);
5830
5831 format %{ "MOV $dst,$src" %}
5832 ins_encode( LdImmI(dst, src) );
5833 ins_pipe( ialu_reg_fat );
5834 %}
5835
5836 // Load Constant zero
5837 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
5838 match(Set dst src);
5839 effect(KILL cr);
5840
5841 ins_cost(50);
5842 format %{ "XOR $dst,$dst" %}
5843 opcode(0x33); /* + rd */
5844 ins_encode( OpcP, RegReg( dst, dst ) );
5845 ins_pipe( ialu_reg );
5846 %}
5847
5848 instruct loadConP(eRegP dst, immP src) %{
5849 match(Set dst src);
5850
5851 format %{ "MOV $dst,$src" %}
5852 opcode(0xB8); /* + rd */
5853 ins_encode( LdImmP(dst, src) );
5854 ins_pipe( ialu_reg_fat );
5855 %}
5856
5857 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
5858 match(Set dst src);
5859 effect(KILL cr);
5860 ins_cost(200);
5861 format %{ "MOV $dst.lo,$src.lo\n\t"
5862 "MOV $dst.hi,$src.hi" %}
5863 opcode(0xB8);
5864 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
5865 ins_pipe( ialu_reg_long_fat );
5866 %}
5867
5868 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
5869 match(Set dst src);
5870 effect(KILL cr);
5871 ins_cost(150);
5872 format %{ "XOR $dst.lo,$dst.lo\n\t"
5873 "XOR $dst.hi,$dst.hi" %}
5874 opcode(0x33,0x33);
5875 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
5876 ins_pipe( ialu_reg_long );
5877 %}
5878
5879 // The instruction usage is guarded by predicate in operand immFPR().
5880 instruct loadConFPR(regFPR dst, immFPR con) %{
5881 match(Set dst con);
5882 ins_cost(125);
5883 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
5884 "FSTP $dst" %}
5885 ins_encode %{
5886 __ fld_s($constantaddress($con));
5887 __ fstp_d($dst$$reg);
5888 %}
5889 ins_pipe(fpu_reg_con);
5890 %}
5891
5892 // The instruction usage is guarded by predicate in operand immFPR0().
5893 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
5894 match(Set dst con);
5895 ins_cost(125);
5896 format %{ "FLDZ ST\n\t"
5897 "FSTP $dst" %}
5898 ins_encode %{
5899 __ fldz();
5900 __ fstp_d($dst$$reg);
5901 %}
5902 ins_pipe(fpu_reg_con);
5903 %}
5904
5905 // The instruction usage is guarded by predicate in operand immFPR1().
5906 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
5907 match(Set dst con);
5908 ins_cost(125);
5909 format %{ "FLD1 ST\n\t"
5910 "FSTP $dst" %}
5911 ins_encode %{
5912 __ fld1();
5913 __ fstp_d($dst$$reg);
5914 %}
5915 ins_pipe(fpu_reg_con);
5916 %}
5917
5918 // The instruction usage is guarded by predicate in operand immF().
5919 instruct loadConF(regF dst, immF con) %{
5920 match(Set dst con);
5921 ins_cost(125);
5922 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
5923 ins_encode %{
5924 __ movflt($dst$$XMMRegister, $constantaddress($con));
5925 %}
5926 ins_pipe(pipe_slow);
5927 %}
5928
5929 // The instruction usage is guarded by predicate in operand immF0().
5930 instruct loadConF0(regF dst, immF0 src) %{
5931 match(Set dst src);
5932 ins_cost(100);
5933 format %{ "XORPS $dst,$dst\t# float 0.0" %}
5934 ins_encode %{
5935 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5936 %}
5937 ins_pipe(pipe_slow);
5938 %}
5939
5940 // The instruction usage is guarded by predicate in operand immDPR().
5941 instruct loadConDPR(regDPR dst, immDPR con) %{
5942 match(Set dst con);
5943 ins_cost(125);
5944
5945 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
5946 "FSTP $dst" %}
5947 ins_encode %{
5948 __ fld_d($constantaddress($con));
5949 __ fstp_d($dst$$reg);
5950 %}
5951 ins_pipe(fpu_reg_con);
5952 %}
5953
5954 // The instruction usage is guarded by predicate in operand immDPR0().
5955 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
5956 match(Set dst con);
5957 ins_cost(125);
5958
5959 format %{ "FLDZ ST\n\t"
5960 "FSTP $dst" %}
5961 ins_encode %{
5962 __ fldz();
5963 __ fstp_d($dst$$reg);
5964 %}
5965 ins_pipe(fpu_reg_con);
5966 %}
5967
5968 // The instruction usage is guarded by predicate in operand immDPR1().
5969 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
5970 match(Set dst con);
5971 ins_cost(125);
5972
5973 format %{ "FLD1 ST\n\t"
5974 "FSTP $dst" %}
5975 ins_encode %{
5976 __ fld1();
5977 __ fstp_d($dst$$reg);
5978 %}
5979 ins_pipe(fpu_reg_con);
5980 %}
5981
5982 // The instruction usage is guarded by predicate in operand immD().
5983 instruct loadConD(regD dst, immD con) %{
5984 match(Set dst con);
5985 ins_cost(125);
5986 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
5987 ins_encode %{
5988 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5989 %}
5990 ins_pipe(pipe_slow);
5991 %}
5992
5993 // The instruction usage is guarded by predicate in operand immD0().
5994 instruct loadConD0(regD dst, immD0 src) %{
5995 match(Set dst src);
5996 ins_cost(100);
5997 format %{ "XORPD $dst,$dst\t# double 0.0" %}
5998 ins_encode %{
5999 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6000 %}
6001 ins_pipe( pipe_slow );
6002 %}
6003
6004 // Load Stack Slot
6005 instruct loadSSI(rRegI dst, stackSlotI src) %{
6006 match(Set dst src);
6007 ins_cost(125);
6008
6009 format %{ "MOV $dst,$src" %}
6010 opcode(0x8B);
6011 ins_encode( OpcP, RegMem(dst,src));
6012 ins_pipe( ialu_reg_mem );
6013 %}
6014
6015 instruct loadSSL(eRegL dst, stackSlotL src) %{
6016 match(Set dst src);
6017
6018 ins_cost(200);
6019 format %{ "MOV $dst,$src.lo\n\t"
6020 "MOV $dst+4,$src.hi" %}
6021 opcode(0x8B, 0x8B);
6022 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6023 ins_pipe( ialu_mem_long_reg );
6024 %}
6025
6026 // Load Stack Slot
6027 instruct loadSSP(eRegP dst, stackSlotP src) %{
6028 match(Set dst src);
6029 ins_cost(125);
6030
6031 format %{ "MOV $dst,$src" %}
6032 opcode(0x8B);
6033 ins_encode( OpcP, RegMem(dst,src));
6034 ins_pipe( ialu_reg_mem );
6035 %}
6036
6037 // Load Stack Slot
6038 instruct loadSSF(regFPR dst, stackSlotF src) %{
6039 match(Set dst src);
6040 ins_cost(125);
6041
6042 format %{ "FLD_S $src\n\t"
6043 "FSTP $dst" %}
6044 opcode(0xD9); /* D9 /0, FLD m32real */
6045 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6046 Pop_Reg_FPR(dst) );
6047 ins_pipe( fpu_reg_mem );
6048 %}
6049
6050 // Load Stack Slot
6051 instruct loadSSD(regDPR dst, stackSlotD src) %{
6052 match(Set dst src);
6053 ins_cost(125);
6054
6055 format %{ "FLD_D $src\n\t"
6056 "FSTP $dst" %}
6057 opcode(0xDD); /* DD /0, FLD m64real */
6058 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6059 Pop_Reg_DPR(dst) );
6060 ins_pipe( fpu_reg_mem );
6061 %}
6062
6063 // Prefetch instructions for allocation.
6064 // Must be safe to execute with invalid address (cannot fault).
6065
6066 instruct prefetchAlloc0( memory mem ) %{
6067 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6068 match(PrefetchAllocation mem);
6069 ins_cost(0);
6070 size(0);
6071 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6072 ins_encode();
6073 ins_pipe(empty);
6074 %}
6075
6076 instruct prefetchAlloc( memory mem ) %{
6077 predicate(AllocatePrefetchInstr==3);
6078 match( PrefetchAllocation mem );
6079 ins_cost(100);
6080
6081 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6082 ins_encode %{
6083 __ prefetchw($mem$$Address);
6084 %}
6085 ins_pipe(ialu_mem);
6086 %}
6087
6088 instruct prefetchAllocNTA( memory mem ) %{
6089 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6090 match(PrefetchAllocation mem);
6091 ins_cost(100);
6092
6093 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6094 ins_encode %{
6095 __ prefetchnta($mem$$Address);
6096 %}
6097 ins_pipe(ialu_mem);
6098 %}
6099
6100 instruct prefetchAllocT0( memory mem ) %{
6101 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6102 match(PrefetchAllocation mem);
6103 ins_cost(100);
6104
6105 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6106 ins_encode %{
6107 __ prefetcht0($mem$$Address);
6108 %}
6109 ins_pipe(ialu_mem);
6110 %}
6111
6112 instruct prefetchAllocT2( memory mem ) %{
6113 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6114 match(PrefetchAllocation mem);
6115 ins_cost(100);
6116
6117 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6118 ins_encode %{
6119 __ prefetcht2($mem$$Address);
6120 %}
6121 ins_pipe(ialu_mem);
6122 %}
6123
6124 //----------Store Instructions-------------------------------------------------
6125
6126 // Store Byte
6127 instruct storeB(memory mem, xRegI src) %{
6128 match(Set mem (StoreB mem src));
6129
6130 ins_cost(125);
6131 format %{ "MOV8 $mem,$src" %}
6132 opcode(0x88);
6133 ins_encode( OpcP, RegMem( src, mem ) );
6134 ins_pipe( ialu_mem_reg );
6135 %}
6136
6137 // Store Char/Short
6138 instruct storeC(memory mem, rRegI src) %{
6139 match(Set mem (StoreC mem src));
6140
6141 ins_cost(125);
6142 format %{ "MOV16 $mem,$src" %}
6143 opcode(0x89, 0x66);
6144 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6145 ins_pipe( ialu_mem_reg );
6146 %}
6147
6148 // Store Integer
6149 instruct storeI(memory mem, rRegI src) %{
6150 match(Set mem (StoreI mem src));
6151
6152 ins_cost(125);
6153 format %{ "MOV $mem,$src" %}
6154 opcode(0x89);
6155 ins_encode( OpcP, RegMem( src, mem ) );
6156 ins_pipe( ialu_mem_reg );
6157 %}
6158
6159 // Store Long
6160 instruct storeL(long_memory mem, eRegL src) %{
6161 predicate(!((StoreLNode*)n)->require_atomic_access());
6162 match(Set mem (StoreL mem src));
6163
6164 ins_cost(200);
6165 format %{ "MOV $mem,$src.lo\n\t"
6166 "MOV $mem+4,$src.hi" %}
6167 opcode(0x89, 0x89);
6168 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6169 ins_pipe( ialu_mem_long_reg );
6170 %}
6171
6172 // Store Long to Integer
6173 instruct storeL2I(memory mem, eRegL src) %{
6174 match(Set mem (StoreI mem (ConvL2I src)));
6175
6176 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6177 ins_encode %{
6178 __ movl($mem$$Address, $src$$Register);
6179 %}
6180 ins_pipe(ialu_mem_reg);
6181 %}
6182
6183 // Volatile Store Long. Must be atomic, so move it into
6184 // the FP TOS and then do a 64-bit FIST. Has to probe the
6185 // target address before the store (for null-ptr checks)
6186 // so the memory operand is used twice in the encoding.
6187 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6188 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6189 match(Set mem (StoreL mem src));
6190 effect( KILL cr );
6191 ins_cost(400);
6192 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6193 "FILD $src\n\t"
6194 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6195 opcode(0x3B);
6196 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6197 ins_pipe( fpu_reg_mem );
6198 %}
6199
6200 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6201 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6202 match(Set mem (StoreL mem src));
6203 effect( TEMP tmp, KILL cr );
6204 ins_cost(380);
6205 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6206 "MOVSD $tmp,$src\n\t"
6207 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6208 ins_encode %{
6209 __ cmpl(rax, $mem$$Address);
6210 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6211 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6212 %}
6213 ins_pipe( pipe_slow );
6214 %}
6215
6216 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6217 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6218 match(Set mem (StoreL mem src));
6219 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6220 ins_cost(360);
6221 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6222 "MOVD $tmp,$src.lo\n\t"
6223 "MOVD $tmp2,$src.hi\n\t"
6224 "PUNPCKLDQ $tmp,$tmp2\n\t"
6225 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6226 ins_encode %{
6227 __ cmpl(rax, $mem$$Address);
6228 __ movdl($tmp$$XMMRegister, $src$$Register);
6229 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6230 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6231 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6232 %}
6233 ins_pipe( pipe_slow );
6234 %}
6235
6236 // Store Pointer; for storing unknown oops and raw pointers
6237 instruct storeP(memory mem, anyRegP src) %{
6238 match(Set mem (StoreP mem src));
6239
6240 ins_cost(125);
6241 format %{ "MOV $mem,$src" %}
6242 opcode(0x89);
6243 ins_encode( OpcP, RegMem( src, mem ) );
6244 ins_pipe( ialu_mem_reg );
6245 %}
6246
6247 // Store Integer Immediate
6248 instruct storeImmI(memory mem, immI src) %{
6249 match(Set mem (StoreI mem src));
6250
6251 ins_cost(150);
6252 format %{ "MOV $mem,$src" %}
6253 opcode(0xC7); /* C7 /0 */
6254 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6255 ins_pipe( ialu_mem_imm );
6256 %}
6257
6258 // Store Short/Char Immediate
6259 instruct storeImmI16(memory mem, immI16 src) %{
6260 predicate(UseStoreImmI16);
6261 match(Set mem (StoreC mem src));
6262
6263 ins_cost(150);
6264 format %{ "MOV16 $mem,$src" %}
6265 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6266 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6267 ins_pipe( ialu_mem_imm );
6268 %}
6269
6270 // Store Pointer Immediate; null pointers or constant oops that do not
6271 // need card-mark barriers.
6272 instruct storeImmP(memory mem, immP src) %{
6273 match(Set mem (StoreP mem src));
6274
6275 ins_cost(150);
6276 format %{ "MOV $mem,$src" %}
6277 opcode(0xC7); /* C7 /0 */
6278 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6279 ins_pipe( ialu_mem_imm );
6280 %}
6281
6282 // Store Byte Immediate
6283 instruct storeImmB(memory mem, immI8 src) %{
6284 match(Set mem (StoreB mem src));
6285
6286 ins_cost(150);
6287 format %{ "MOV8 $mem,$src" %}
6288 opcode(0xC6); /* C6 /0 */
6289 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6290 ins_pipe( ialu_mem_imm );
6291 %}
6292
6293 // Store CMS card-mark Immediate
6294 instruct storeImmCM(memory mem, immI8 src) %{
6295 match(Set mem (StoreCM mem src));
6296
6297 ins_cost(150);
6298 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6299 opcode(0xC6); /* C6 /0 */
6300 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6301 ins_pipe( ialu_mem_imm );
6302 %}
6303
6304 // Store Double
6305 instruct storeDPR( memory mem, regDPR1 src) %{
6306 predicate(UseSSE<=1);
6307 match(Set mem (StoreD mem src));
6308
6309 ins_cost(100);
6310 format %{ "FST_D $mem,$src" %}
6311 opcode(0xDD); /* DD /2 */
6312 ins_encode( enc_FPR_store(mem,src) );
6313 ins_pipe( fpu_mem_reg );
6314 %}
6315
6316 // Store double does rounding on x86
6317 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6318 predicate(UseSSE<=1);
6319 match(Set mem (StoreD mem (RoundDouble src)));
6320
6321 ins_cost(100);
6322 format %{ "FST_D $mem,$src\t# round" %}
6323 opcode(0xDD); /* DD /2 */
6324 ins_encode( enc_FPR_store(mem,src) );
6325 ins_pipe( fpu_mem_reg );
6326 %}
6327
6328 // Store XMM register to memory (double-precision floating points)
6329 // MOVSD instruction
6330 instruct storeD(memory mem, regD src) %{
6331 predicate(UseSSE>=2);
6332 match(Set mem (StoreD mem src));
6333 ins_cost(95);
6334 format %{ "MOVSD $mem,$src" %}
6335 ins_encode %{
6336 __ movdbl($mem$$Address, $src$$XMMRegister);
6337 %}
6338 ins_pipe( pipe_slow );
6339 %}
6340
6341 // Store XMM register to memory (single-precision floating point)
6342 // MOVSS instruction
6343 instruct storeF(memory mem, regF src) %{
6344 predicate(UseSSE>=1);
6345 match(Set mem (StoreF mem src));
6346 ins_cost(95);
6347 format %{ "MOVSS $mem,$src" %}
6348 ins_encode %{
6349 __ movflt($mem$$Address, $src$$XMMRegister);
6350 %}
6351 ins_pipe( pipe_slow );
6352 %}
6353
6354 // Store Float
6355 instruct storeFPR( memory mem, regFPR1 src) %{
6356 predicate(UseSSE==0);
6357 match(Set mem (StoreF mem src));
6358
6359 ins_cost(100);
6360 format %{ "FST_S $mem,$src" %}
6361 opcode(0xD9); /* D9 /2 */
6362 ins_encode( enc_FPR_store(mem,src) );
6363 ins_pipe( fpu_mem_reg );
6364 %}
6365
6366 // Store Float does rounding on x86
6367 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
6368 predicate(UseSSE==0);
6369 match(Set mem (StoreF mem (RoundFloat src)));
6370
6371 ins_cost(100);
6372 format %{ "FST_S $mem,$src\t# round" %}
6373 opcode(0xD9); /* D9 /2 */
6374 ins_encode( enc_FPR_store(mem,src) );
6375 ins_pipe( fpu_mem_reg );
6376 %}
6377
6378 // Store Float does rounding on x86
6379 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
6380 predicate(UseSSE<=1);
6381 match(Set mem (StoreF mem (ConvD2F src)));
6382
6383 ins_cost(100);
6384 format %{ "FST_S $mem,$src\t# D-round" %}
6385 opcode(0xD9); /* D9 /2 */
6386 ins_encode( enc_FPR_store(mem,src) );
6387 ins_pipe( fpu_mem_reg );
6388 %}
6389
6390 // Store immediate Float value (it is faster than store from FPU register)
6391 // The instruction usage is guarded by predicate in operand immFPR().
6392 instruct storeFPR_imm( memory mem, immFPR src) %{
6393 match(Set mem (StoreF mem src));
6394
6395 ins_cost(50);
6396 format %{ "MOV $mem,$src\t# store float" %}
6397 opcode(0xC7); /* C7 /0 */
6398 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
6399 ins_pipe( ialu_mem_imm );
6400 %}
6401
6402 // Store immediate Float value (it is faster than store from XMM register)
6403 // The instruction usage is guarded by predicate in operand immF().
6404 instruct storeF_imm( memory mem, immF src) %{
6405 match(Set mem (StoreF mem src));
6406
6407 ins_cost(50);
6408 format %{ "MOV $mem,$src\t# store float" %}
6409 opcode(0xC7); /* C7 /0 */
6410 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
6411 ins_pipe( ialu_mem_imm );
6412 %}
6413
6414 // Store Integer to stack slot
6415 instruct storeSSI(stackSlotI dst, rRegI src) %{
6416 match(Set dst src);
6417
6418 ins_cost(100);
6419 format %{ "MOV $dst,$src" %}
6420 opcode(0x89);
6421 ins_encode( OpcPRegSS( dst, src ) );
6422 ins_pipe( ialu_mem_reg );
6423 %}
6424
6425 // Store Integer to stack slot
6426 instruct storeSSP(stackSlotP dst, eRegP src) %{
6427 match(Set dst src);
6428
6429 ins_cost(100);
6430 format %{ "MOV $dst,$src" %}
6431 opcode(0x89);
6432 ins_encode( OpcPRegSS( dst, src ) );
6433 ins_pipe( ialu_mem_reg );
6434 %}
6435
6436 // Store Long to stack slot
6437 instruct storeSSL(stackSlotL dst, eRegL src) %{
6438 match(Set dst src);
6439
6440 ins_cost(200);
6441 format %{ "MOV $dst,$src.lo\n\t"
6442 "MOV $dst+4,$src.hi" %}
6443 opcode(0x89, 0x89);
6444 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
6445 ins_pipe( ialu_mem_long_reg );
6446 %}
6447
6448 //----------MemBar Instructions-----------------------------------------------
6449 // Memory barrier flavors
6450
6451 instruct membar_acquire() %{
6452 match(MemBarAcquire);
6453 match(LoadFence);
6454 ins_cost(400);
6455
6456 size(0);
6457 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6458 ins_encode();
6459 ins_pipe(empty);
6460 %}
6461
6462 instruct membar_acquire_lock() %{
6463 match(MemBarAcquireLock);
6464 ins_cost(0);
6465
6466 size(0);
6467 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6468 ins_encode( );
6469 ins_pipe(empty);
6470 %}
6471
6472 instruct membar_release() %{
6473 match(MemBarRelease);
6474 match(StoreFence);
6475 ins_cost(400);
6476
6477 size(0);
6478 format %{ "MEMBAR-release ! (empty encoding)" %}
6479 ins_encode( );
6480 ins_pipe(empty);
6481 %}
6482
6483 instruct membar_release_lock() %{
6484 match(MemBarReleaseLock);
6485 ins_cost(0);
6486
6487 size(0);
6488 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6489 ins_encode( );
6490 ins_pipe(empty);
6491 %}
6492
6493 instruct membar_volatile(eFlagsReg cr) %{
6494 match(MemBarVolatile);
6495 effect(KILL cr);
6496 ins_cost(400);
6497
6498 format %{
6499 $$template
6500 if (os::is_MP()) {
6501 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
6502 } else {
6503 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6504 }
6505 %}
6506 ins_encode %{
6507 __ membar(Assembler::StoreLoad);
6508 %}
6509 ins_pipe(pipe_slow);
6510 %}
6511
6512 instruct unnecessary_membar_volatile() %{
6513 match(MemBarVolatile);
6514 predicate(Matcher::post_store_load_barrier(n));
6515 ins_cost(0);
6516
6517 size(0);
6518 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6519 ins_encode( );
6520 ins_pipe(empty);
6521 %}
6522
6523 instruct membar_storestore() %{
6524 match(MemBarStoreStore);
6525 ins_cost(0);
6526
6527 size(0);
6528 format %{ "MEMBAR-storestore (empty encoding)" %}
6529 ins_encode( );
6530 ins_pipe(empty);
6531 %}
6532
6533 //----------Move Instructions--------------------------------------------------
6534 instruct castX2P(eAXRegP dst, eAXRegI src) %{
6535 match(Set dst (CastX2P src));
6536 format %{ "# X2P $dst, $src" %}
6537 ins_encode( /*empty encoding*/ );
6538 ins_cost(0);
6539 ins_pipe(empty);
6540 %}
6541
6542 instruct castP2X(rRegI dst, eRegP src ) %{
6543 match(Set dst (CastP2X src));
6544 ins_cost(50);
6545 format %{ "MOV $dst, $src\t# CastP2X" %}
6546 ins_encode( enc_Copy( dst, src) );
6547 ins_pipe( ialu_reg_reg );
6548 %}
6549
6550 //----------Conditional Move---------------------------------------------------
6551 // Conditional move
6552 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
6553 predicate(!VM_Version::supports_cmov() );
6554 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6555 ins_cost(200);
6556 format %{ "J$cop,us skip\t# signed cmove\n\t"
6557 "MOV $dst,$src\n"
6558 "skip:" %}
6559 ins_encode %{
6560 Label Lskip;
6561 // Invert sense of branch from sense of CMOV
6562 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6563 __ movl($dst$$Register, $src$$Register);
6564 __ bind(Lskip);
6565 %}
6566 ins_pipe( pipe_cmov_reg );
6567 %}
6568
6569 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
6570 predicate(!VM_Version::supports_cmov() );
6571 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6572 ins_cost(200);
6573 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
6574 "MOV $dst,$src\n"
6575 "skip:" %}
6576 ins_encode %{
6577 Label Lskip;
6578 // Invert sense of branch from sense of CMOV
6579 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6580 __ movl($dst$$Register, $src$$Register);
6581 __ bind(Lskip);
6582 %}
6583 ins_pipe( pipe_cmov_reg );
6584 %}
6585
6586 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
6587 predicate(VM_Version::supports_cmov() );
6588 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6589 ins_cost(200);
6590 format %{ "CMOV$cop $dst,$src" %}
6591 opcode(0x0F,0x40);
6592 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6593 ins_pipe( pipe_cmov_reg );
6594 %}
6595
6596 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
6597 predicate(VM_Version::supports_cmov() );
6598 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6599 ins_cost(200);
6600 format %{ "CMOV$cop $dst,$src" %}
6601 opcode(0x0F,0x40);
6602 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6603 ins_pipe( pipe_cmov_reg );
6604 %}
6605
6606 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
6607 predicate(VM_Version::supports_cmov() );
6608 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6609 ins_cost(200);
6610 expand %{
6611 cmovI_regU(cop, cr, dst, src);
6612 %}
6613 %}
6614
6615 // Conditional move
6616 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
6617 predicate(VM_Version::supports_cmov() );
6618 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6619 ins_cost(250);
6620 format %{ "CMOV$cop $dst,$src" %}
6621 opcode(0x0F,0x40);
6622 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6623 ins_pipe( pipe_cmov_mem );
6624 %}
6625
6626 // Conditional move
6627 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
6628 predicate(VM_Version::supports_cmov() );
6629 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6630 ins_cost(250);
6631 format %{ "CMOV$cop $dst,$src" %}
6632 opcode(0x0F,0x40);
6633 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6634 ins_pipe( pipe_cmov_mem );
6635 %}
6636
6637 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
6638 predicate(VM_Version::supports_cmov() );
6639 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6640 ins_cost(250);
6641 expand %{
6642 cmovI_memU(cop, cr, dst, src);
6643 %}
6644 %}
6645
6646 // Conditional move
6647 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
6648 predicate(VM_Version::supports_cmov() );
6649 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6650 ins_cost(200);
6651 format %{ "CMOV$cop $dst,$src\t# ptr" %}
6652 opcode(0x0F,0x40);
6653 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6654 ins_pipe( pipe_cmov_reg );
6655 %}
6656
6657 // Conditional move (non-P6 version)
6658 // Note: a CMoveP is generated for stubs and native wrappers
6659 // regardless of whether we are on a P6, so we
6660 // emulate a cmov here
6661 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
6662 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6663 ins_cost(300);
6664 format %{ "Jn$cop skip\n\t"
6665 "MOV $dst,$src\t# pointer\n"
6666 "skip:" %}
6667 opcode(0x8b);
6668 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
6669 ins_pipe( pipe_cmov_reg );
6670 %}
6671
6672 // Conditional move
6673 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
6674 predicate(VM_Version::supports_cmov() );
6675 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6676 ins_cost(200);
6677 format %{ "CMOV$cop $dst,$src\t# ptr" %}
6678 opcode(0x0F,0x40);
6679 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6680 ins_pipe( pipe_cmov_reg );
6681 %}
6682
6683 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
6684 predicate(VM_Version::supports_cmov() );
6685 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6686 ins_cost(200);
6687 expand %{
6688 cmovP_regU(cop, cr, dst, src);
6689 %}
6690 %}
6691
6692 // DISABLED: Requires the ADLC to emit a bottom_type call that
6693 // correctly meets the two pointer arguments; one is an incoming
6694 // register but the other is a memory operand. ALSO appears to
6695 // be buggy with implicit null checks.
6696 //
6697 //// Conditional move
6698 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
6699 // predicate(VM_Version::supports_cmov() );
6700 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6701 // ins_cost(250);
6702 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6703 // opcode(0x0F,0x40);
6704 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6705 // ins_pipe( pipe_cmov_mem );
6706 //%}
6707 //
6708 //// Conditional move
6709 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
6710 // predicate(VM_Version::supports_cmov() );
6711 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6712 // ins_cost(250);
6713 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6714 // opcode(0x0F,0x40);
6715 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6716 // ins_pipe( pipe_cmov_mem );
6717 //%}
6718
6719 // Conditional move
6720 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
6721 predicate(UseSSE<=1);
6722 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6723 ins_cost(200);
6724 format %{ "FCMOV$cop $dst,$src\t# double" %}
6725 opcode(0xDA);
6726 ins_encode( enc_cmov_dpr(cop,src) );
6727 ins_pipe( pipe_cmovDPR_reg );
6728 %}
6729
6730 // Conditional move
6731 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
6732 predicate(UseSSE==0);
6733 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6734 ins_cost(200);
6735 format %{ "FCMOV$cop $dst,$src\t# float" %}
6736 opcode(0xDA);
6737 ins_encode( enc_cmov_dpr(cop,src) );
6738 ins_pipe( pipe_cmovDPR_reg );
6739 %}
6740
6741 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
6742 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
6743 predicate(UseSSE<=1);
6744 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6745 ins_cost(200);
6746 format %{ "Jn$cop skip\n\t"
6747 "MOV $dst,$src\t# double\n"
6748 "skip:" %}
6749 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
6750 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
6751 ins_pipe( pipe_cmovDPR_reg );
6752 %}
6753
6754 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
6755 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
6756 predicate(UseSSE==0);
6757 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6758 ins_cost(200);
6759 format %{ "Jn$cop skip\n\t"
6760 "MOV $dst,$src\t# float\n"
6761 "skip:" %}
6762 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
6763 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
6764 ins_pipe( pipe_cmovDPR_reg );
6765 %}
6766
6767 // No CMOVE with SSE/SSE2
6768 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
6769 predicate (UseSSE>=1);
6770 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6771 ins_cost(200);
6772 format %{ "Jn$cop skip\n\t"
6773 "MOVSS $dst,$src\t# float\n"
6774 "skip:" %}
6775 ins_encode %{
6776 Label skip;
6777 // Invert sense of branch from sense of CMOV
6778 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6779 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6780 __ bind(skip);
6781 %}
6782 ins_pipe( pipe_slow );
6783 %}
6784
6785 // No CMOVE with SSE/SSE2
6786 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
6787 predicate (UseSSE>=2);
6788 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6789 ins_cost(200);
6790 format %{ "Jn$cop skip\n\t"
6791 "MOVSD $dst,$src\t# float\n"
6792 "skip:" %}
6793 ins_encode %{
6794 Label skip;
6795 // Invert sense of branch from sense of CMOV
6796 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6797 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6798 __ bind(skip);
6799 %}
6800 ins_pipe( pipe_slow );
6801 %}
6802
6803 // unsigned version
6804 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
6805 predicate (UseSSE>=1);
6806 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6807 ins_cost(200);
6808 format %{ "Jn$cop skip\n\t"
6809 "MOVSS $dst,$src\t# float\n"
6810 "skip:" %}
6811 ins_encode %{
6812 Label skip;
6813 // Invert sense of branch from sense of CMOV
6814 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6815 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6816 __ bind(skip);
6817 %}
6818 ins_pipe( pipe_slow );
6819 %}
6820
6821 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
6822 predicate (UseSSE>=1);
6823 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6824 ins_cost(200);
6825 expand %{
6826 fcmovF_regU(cop, cr, dst, src);
6827 %}
6828 %}
6829
6830 // unsigned version
6831 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
6832 predicate (UseSSE>=2);
6833 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6834 ins_cost(200);
6835 format %{ "Jn$cop skip\n\t"
6836 "MOVSD $dst,$src\t# float\n"
6837 "skip:" %}
6838 ins_encode %{
6839 Label skip;
6840 // Invert sense of branch from sense of CMOV
6841 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6842 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6843 __ bind(skip);
6844 %}
6845 ins_pipe( pipe_slow );
6846 %}
6847
6848 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
6849 predicate (UseSSE>=2);
6850 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6851 ins_cost(200);
6852 expand %{
6853 fcmovD_regU(cop, cr, dst, src);
6854 %}
6855 %}
6856
6857 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
6858 predicate(VM_Version::supports_cmov() );
6859 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6860 ins_cost(200);
6861 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
6862 "CMOV$cop $dst.hi,$src.hi" %}
6863 opcode(0x0F,0x40);
6864 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
6865 ins_pipe( pipe_cmov_reg_long );
6866 %}
6867
6868 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
6869 predicate(VM_Version::supports_cmov() );
6870 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6871 ins_cost(200);
6872 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
6873 "CMOV$cop $dst.hi,$src.hi" %}
6874 opcode(0x0F,0x40);
6875 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
6876 ins_pipe( pipe_cmov_reg_long );
6877 %}
6878
6879 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
6880 predicate(VM_Version::supports_cmov() );
6881 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6882 ins_cost(200);
6883 expand %{
6884 cmovL_regU(cop, cr, dst, src);
6885 %}
6886 %}
6887
6888 //----------Arithmetic Instructions--------------------------------------------
6889 //----------Addition Instructions----------------------------------------------
6890
6891 // Integer Addition Instructions
6892 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
6893 match(Set dst (AddI dst src));
6894 effect(KILL cr);
6895
6896 size(2);
6897 format %{ "ADD $dst,$src" %}
6898 opcode(0x03);
6899 ins_encode( OpcP, RegReg( dst, src) );
6900 ins_pipe( ialu_reg_reg );
6901 %}
6902
6903 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
6904 match(Set dst (AddI dst src));
6905 effect(KILL cr);
6906
6907 format %{ "ADD $dst,$src" %}
6908 opcode(0x81, 0x00); /* /0 id */
6909 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
6910 ins_pipe( ialu_reg );
6911 %}
6912
6913 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
6914 predicate(UseIncDec);
6915 match(Set dst (AddI dst src));
6916 effect(KILL cr);
6917
6918 size(1);
6919 format %{ "INC $dst" %}
6920 opcode(0x40); /* */
6921 ins_encode( Opc_plus( primary, dst ) );
6922 ins_pipe( ialu_reg );
6923 %}
6924
6925 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
6926 match(Set dst (AddI src0 src1));
6927 ins_cost(110);
6928
6929 format %{ "LEA $dst,[$src0 + $src1]" %}
6930 opcode(0x8D); /* 0x8D /r */
6931 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
6932 ins_pipe( ialu_reg_reg );
6933 %}
6934
6935 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
6936 match(Set dst (AddP src0 src1));
6937 ins_cost(110);
6938
6939 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
6940 opcode(0x8D); /* 0x8D /r */
6941 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
6942 ins_pipe( ialu_reg_reg );
6943 %}
6944
6945 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
6946 predicate(UseIncDec);
6947 match(Set dst (AddI dst src));
6948 effect(KILL cr);
6949
6950 size(1);
6951 format %{ "DEC $dst" %}
6952 opcode(0x48); /* */
6953 ins_encode( Opc_plus( primary, dst ) );
6954 ins_pipe( ialu_reg );
6955 %}
6956
6957 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
6958 match(Set dst (AddP dst src));
6959 effect(KILL cr);
6960
6961 size(2);
6962 format %{ "ADD $dst,$src" %}
6963 opcode(0x03);
6964 ins_encode( OpcP, RegReg( dst, src) );
6965 ins_pipe( ialu_reg_reg );
6966 %}
6967
6968 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
6969 match(Set dst (AddP dst src));
6970 effect(KILL cr);
6971
6972 format %{ "ADD $dst,$src" %}
6973 opcode(0x81,0x00); /* Opcode 81 /0 id */
6974 // ins_encode( RegImm( dst, src) );
6975 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
6976 ins_pipe( ialu_reg );
6977 %}
6978
6979 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
6980 match(Set dst (AddI dst (LoadI src)));
6981 effect(KILL cr);
6982
6983 ins_cost(125);
6984 format %{ "ADD $dst,$src" %}
6985 opcode(0x03);
6986 ins_encode( OpcP, RegMem( dst, src) );
6987 ins_pipe( ialu_reg_mem );
6988 %}
6989
6990 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
6991 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6992 effect(KILL cr);
6993
6994 ins_cost(150);
6995 format %{ "ADD $dst,$src" %}
6996 opcode(0x01); /* Opcode 01 /r */
6997 ins_encode( OpcP, RegMem( src, dst ) );
6998 ins_pipe( ialu_mem_reg );
6999 %}
7000
7001 // Add Memory with Immediate
7002 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7003 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7004 effect(KILL cr);
7005
7006 ins_cost(125);
7007 format %{ "ADD $dst,$src" %}
7008 opcode(0x81); /* Opcode 81 /0 id */
7009 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7010 ins_pipe( ialu_mem_imm );
7011 %}
7012
7013 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7014 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7015 effect(KILL cr);
7016
7017 ins_cost(125);
7018 format %{ "INC $dst" %}
7019 opcode(0xFF); /* Opcode FF /0 */
7020 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7021 ins_pipe( ialu_mem_imm );
7022 %}
7023
7024 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7025 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7026 effect(KILL cr);
7027
7028 ins_cost(125);
7029 format %{ "DEC $dst" %}
7030 opcode(0xFF); /* Opcode FF /1 */
7031 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7032 ins_pipe( ialu_mem_imm );
7033 %}
7034
7035
7036 instruct checkCastPP( eRegP dst ) %{
7037 match(Set dst (CheckCastPP dst));
7038
7039 size(0);
7040 format %{ "#checkcastPP of $dst" %}
7041 ins_encode( /*empty encoding*/ );
7042 ins_pipe( empty );
7043 %}
7044
7045 instruct castPP( eRegP dst ) %{
7046 match(Set dst (CastPP dst));
7047 format %{ "#castPP of $dst" %}
7048 ins_encode( /*empty encoding*/ );
7049 ins_pipe( empty );
7050 %}
7051
7052 instruct castII( rRegI dst ) %{
7053 match(Set dst (CastII dst));
7054 format %{ "#castII of $dst" %}
7055 ins_encode( /*empty encoding*/ );
7056 ins_cost(0);
7057 ins_pipe( empty );
7058 %}
7059
7060
7061 // Load-locked - same as a regular pointer load when used with compare-swap
7062 instruct loadPLocked(eRegP dst, memory mem) %{
7063 match(Set dst (LoadPLocked mem));
7064
7065 ins_cost(125);
7066 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7067 opcode(0x8B);
7068 ins_encode( OpcP, RegMem(dst,mem));
7069 ins_pipe( ialu_reg_mem );
7070 %}
7071
7072 // Conditional-store of the updated heap-top.
7073 // Used during allocation of the shared heap.
7074 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7075 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7076 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7077 // EAX is killed if there is contention, but then it's also unused.
7078 // In the common case of no contention, EAX holds the new oop address.
7079 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7080 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7081 ins_pipe( pipe_cmpxchg );
7082 %}
7083
7084 // Conditional-store of an int value.
7085 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7086 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7087 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7088 effect(KILL oldval);
7089 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7090 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7091 ins_pipe( pipe_cmpxchg );
7092 %}
7093
7094 // Conditional-store of a long value.
7095 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7096 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7097 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7098 effect(KILL oldval);
7099 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7100 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7101 "XCHG EBX,ECX"
7102 %}
7103 ins_encode %{
7104 // Note: we need to swap rbx, and rcx before and after the
7105 // cmpxchg8 instruction because the instruction uses
7106 // rcx as the high order word of the new value to store but
7107 // our register encoding uses rbx.
7108 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7109 if( os::is_MP() )
7110 __ lock();
7111 __ cmpxchg8($mem$$Address);
7112 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7113 %}
7114 ins_pipe( pipe_cmpxchg );
7115 %}
7116
7117 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7118
7119 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7120 predicate(VM_Version::supports_cx8());
7121 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7122 effect(KILL cr, KILL oldval);
7123 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7124 "MOV $res,0\n\t"
7125 "JNE,s fail\n\t"
7126 "MOV $res,1\n"
7127 "fail:" %}
7128 ins_encode( enc_cmpxchg8(mem_ptr),
7129 enc_flags_ne_to_boolean(res) );
7130 ins_pipe( pipe_cmpxchg );
7131 %}
7132
7133 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7134 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7135 effect(KILL cr, KILL oldval);
7136 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7137 "MOV $res,0\n\t"
7138 "JNE,s fail\n\t"
7139 "MOV $res,1\n"
7140 "fail:" %}
7141 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7142 ins_pipe( pipe_cmpxchg );
7143 %}
7144
7145 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7146 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7147 effect(KILL cr, KILL oldval);
7148 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7149 "MOV $res,0\n\t"
7150 "JNE,s fail\n\t"
7151 "MOV $res,1\n"
7152 "fail:" %}
7153 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7154 ins_pipe( pipe_cmpxchg );
7155 %}
7156
7157 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7158 predicate(n->as_LoadStore()->result_not_used());
7159 match(Set dummy (GetAndAddI mem add));
7160 effect(KILL cr);
7161 format %{ "ADDL [$mem],$add" %}
7162 ins_encode %{
7163 if (os::is_MP()) { __ lock(); }
7164 __ addl($mem$$Address, $add$$constant);
7165 %}
7166 ins_pipe( pipe_cmpxchg );
7167 %}
7168
7169 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7170 match(Set newval (GetAndAddI mem newval));
7171 effect(KILL cr);
7172 format %{ "XADDL [$mem],$newval" %}
7173 ins_encode %{
7174 if (os::is_MP()) { __ lock(); }
7175 __ xaddl($mem$$Address, $newval$$Register);
7176 %}
7177 ins_pipe( pipe_cmpxchg );
7178 %}
7179
7180 instruct xchgI( memory mem, rRegI newval) %{
7181 match(Set newval (GetAndSetI mem newval));
7182 format %{ "XCHGL $newval,[$mem]" %}
7183 ins_encode %{
7184 __ xchgl($newval$$Register, $mem$$Address);
7185 %}
7186 ins_pipe( pipe_cmpxchg );
7187 %}
7188
7189 instruct xchgP( memory mem, pRegP newval) %{
7190 match(Set newval (GetAndSetP mem newval));
7191 format %{ "XCHGL $newval,[$mem]" %}
7192 ins_encode %{
7193 __ xchgl($newval$$Register, $mem$$Address);
7194 %}
7195 ins_pipe( pipe_cmpxchg );
7196 %}
7197
7198 //----------Subtraction Instructions-------------------------------------------
7199
7200 // Integer Subtraction Instructions
7201 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7202 match(Set dst (SubI dst src));
7203 effect(KILL cr);
7204
7205 size(2);
7206 format %{ "SUB $dst,$src" %}
7207 opcode(0x2B);
7208 ins_encode( OpcP, RegReg( dst, src) );
7209 ins_pipe( ialu_reg_reg );
7210 %}
7211
7212 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7213 match(Set dst (SubI dst src));
7214 effect(KILL cr);
7215
7216 format %{ "SUB $dst,$src" %}
7217 opcode(0x81,0x05); /* Opcode 81 /5 */
7218 // ins_encode( RegImm( dst, src) );
7219 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7220 ins_pipe( ialu_reg );
7221 %}
7222
7223 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7224 match(Set dst (SubI dst (LoadI src)));
7225 effect(KILL cr);
7226
7227 ins_cost(125);
7228 format %{ "SUB $dst,$src" %}
7229 opcode(0x2B);
7230 ins_encode( OpcP, RegMem( dst, src) );
7231 ins_pipe( ialu_reg_mem );
7232 %}
7233
7234 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7235 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7236 effect(KILL cr);
7237
7238 ins_cost(150);
7239 format %{ "SUB $dst,$src" %}
7240 opcode(0x29); /* Opcode 29 /r */
7241 ins_encode( OpcP, RegMem( src, dst ) );
7242 ins_pipe( ialu_mem_reg );
7243 %}
7244
7245 // Subtract from a pointer
7246 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7247 match(Set dst (AddP dst (SubI zero src)));
7248 effect(KILL cr);
7249
7250 size(2);
7251 format %{ "SUB $dst,$src" %}
7252 opcode(0x2B);
7253 ins_encode( OpcP, RegReg( dst, src) );
7254 ins_pipe( ialu_reg_reg );
7255 %}
7256
7257 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7258 match(Set dst (SubI zero dst));
7259 effect(KILL cr);
7260
7261 size(2);
7262 format %{ "NEG $dst" %}
7263 opcode(0xF7,0x03); // Opcode F7 /3
7264 ins_encode( OpcP, RegOpc( dst ) );
7265 ins_pipe( ialu_reg );
7266 %}
7267
7268 //----------Multiplication/Division Instructions-------------------------------
7269 // Integer Multiplication Instructions
7270 // Multiply Register
7271 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7272 match(Set dst (MulI dst src));
7273 effect(KILL cr);
7274
7275 size(3);
7276 ins_cost(300);
7277 format %{ "IMUL $dst,$src" %}
7278 opcode(0xAF, 0x0F);
7279 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7280 ins_pipe( ialu_reg_reg_alu0 );
7281 %}
7282
7283 // Multiply 32-bit Immediate
7284 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7285 match(Set dst (MulI src imm));
7286 effect(KILL cr);
7287
7288 ins_cost(300);
7289 format %{ "IMUL $dst,$src,$imm" %}
7290 opcode(0x69); /* 69 /r id */
7291 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7292 ins_pipe( ialu_reg_reg_alu0 );
7293 %}
7294
7295 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7296 match(Set dst src);
7297 effect(KILL cr);
7298
7299 // Note that this is artificially increased to make it more expensive than loadConL
7300 ins_cost(250);
7301 format %{ "MOV EAX,$src\t// low word only" %}
7302 opcode(0xB8);
7303 ins_encode( LdImmL_Lo(dst, src) );
7304 ins_pipe( ialu_reg_fat );
7305 %}
7306
7307 // Multiply by 32-bit Immediate, taking the shifted high order results
7308 // (special case for shift by 32)
7309 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7310 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7311 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7312 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7313 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7314 effect(USE src1, KILL cr);
7315
7316 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7317 ins_cost(0*100 + 1*400 - 150);
7318 format %{ "IMUL EDX:EAX,$src1" %}
7319 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7320 ins_pipe( pipe_slow );
7321 %}
7322
7323 // Multiply by 32-bit Immediate, taking the shifted high order results
7324 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7325 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7326 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7327 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7328 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7329 effect(USE src1, KILL cr);
7330
7331 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7332 ins_cost(1*100 + 1*400 - 150);
7333 format %{ "IMUL EDX:EAX,$src1\n\t"
7334 "SAR EDX,$cnt-32" %}
7335 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7336 ins_pipe( pipe_slow );
7337 %}
7338
7339 // Multiply Memory 32-bit Immediate
7340 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7341 match(Set dst (MulI (LoadI src) imm));
7342 effect(KILL cr);
7343
7344 ins_cost(300);
7345 format %{ "IMUL $dst,$src,$imm" %}
7346 opcode(0x69); /* 69 /r id */
7347 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7348 ins_pipe( ialu_reg_mem_alu0 );
7349 %}
7350
7351 // Multiply Memory
7352 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
7353 match(Set dst (MulI dst (LoadI src)));
7354 effect(KILL cr);
7355
7356 ins_cost(350);
7357 format %{ "IMUL $dst,$src" %}
7358 opcode(0xAF, 0x0F);
7359 ins_encode( OpcS, OpcP, RegMem( dst, src) );
7360 ins_pipe( ialu_reg_mem_alu0 );
7361 %}
7362
7363 // Multiply Register Int to Long
7364 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
7365 // Basic Idea: long = (long)int * (long)int
7366 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
7367 effect(DEF dst, USE src, USE src1, KILL flags);
7368
7369 ins_cost(300);
7370 format %{ "IMUL $dst,$src1" %}
7371
7372 ins_encode( long_int_multiply( dst, src1 ) );
7373 ins_pipe( ialu_reg_reg_alu0 );
7374 %}
7375
7376 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
7377 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
7378 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
7379 effect(KILL flags);
7380
7381 ins_cost(300);
7382 format %{ "MUL $dst,$src1" %}
7383
7384 ins_encode( long_uint_multiply(dst, src1) );
7385 ins_pipe( ialu_reg_reg_alu0 );
7386 %}
7387
7388 // Multiply Register Long
7389 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7390 match(Set dst (MulL dst src));
7391 effect(KILL cr, TEMP tmp);
7392 ins_cost(4*100+3*400);
7393 // Basic idea: lo(result) = lo(x_lo * y_lo)
7394 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
7395 format %{ "MOV $tmp,$src.lo\n\t"
7396 "IMUL $tmp,EDX\n\t"
7397 "MOV EDX,$src.hi\n\t"
7398 "IMUL EDX,EAX\n\t"
7399 "ADD $tmp,EDX\n\t"
7400 "MUL EDX:EAX,$src.lo\n\t"
7401 "ADD EDX,$tmp" %}
7402 ins_encode( long_multiply( dst, src, tmp ) );
7403 ins_pipe( pipe_slow );
7404 %}
7405
7406 // Multiply Register Long where the left operand's high 32 bits are zero
7407 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7408 predicate(is_operand_hi32_zero(n->in(1)));
7409 match(Set dst (MulL dst src));
7410 effect(KILL cr, TEMP tmp);
7411 ins_cost(2*100+2*400);
7412 // Basic idea: lo(result) = lo(x_lo * y_lo)
7413 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
7414 format %{ "MOV $tmp,$src.hi\n\t"
7415 "IMUL $tmp,EAX\n\t"
7416 "MUL EDX:EAX,$src.lo\n\t"
7417 "ADD EDX,$tmp" %}
7418 ins_encode %{
7419 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
7420 __ imull($tmp$$Register, rax);
7421 __ mull($src$$Register);
7422 __ addl(rdx, $tmp$$Register);
7423 %}
7424 ins_pipe( pipe_slow );
7425 %}
7426
7427 // Multiply Register Long where the right operand's high 32 bits are zero
7428 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7429 predicate(is_operand_hi32_zero(n->in(2)));
7430 match(Set dst (MulL dst src));
7431 effect(KILL cr, TEMP tmp);
7432 ins_cost(2*100+2*400);
7433 // Basic idea: lo(result) = lo(x_lo * y_lo)
7434 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
7435 format %{ "MOV $tmp,$src.lo\n\t"
7436 "IMUL $tmp,EDX\n\t"
7437 "MUL EDX:EAX,$src.lo\n\t"
7438 "ADD EDX,$tmp" %}
7439 ins_encode %{
7440 __ movl($tmp$$Register, $src$$Register);
7441 __ imull($tmp$$Register, rdx);
7442 __ mull($src$$Register);
7443 __ addl(rdx, $tmp$$Register);
7444 %}
7445 ins_pipe( pipe_slow );
7446 %}
7447
7448 // Multiply Register Long where the left and the right operands' high 32 bits are zero
7449 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
7450 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
7451 match(Set dst (MulL dst src));
7452 effect(KILL cr);
7453 ins_cost(1*400);
7454 // Basic idea: lo(result) = lo(x_lo * y_lo)
7455 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
7456 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
7457 ins_encode %{
7458 __ mull($src$$Register);
7459 %}
7460 ins_pipe( pipe_slow );
7461 %}
7462
7463 // Multiply Register Long by small constant
7464 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
7465 match(Set dst (MulL dst src));
7466 effect(KILL cr, TEMP tmp);
7467 ins_cost(2*100+2*400);
7468 size(12);
7469 // Basic idea: lo(result) = lo(src * EAX)
7470 // hi(result) = hi(src * EAX) + lo(src * EDX)
7471 format %{ "IMUL $tmp,EDX,$src\n\t"
7472 "MOV EDX,$src\n\t"
7473 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
7474 "ADD EDX,$tmp" %}
7475 ins_encode( long_multiply_con( dst, src, tmp ) );
7476 ins_pipe( pipe_slow );
7477 %}
7478
7479 // Integer DIV with Register
7480 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
7481 match(Set rax (DivI rax div));
7482 effect(KILL rdx, KILL cr);
7483 size(26);
7484 ins_cost(30*100+10*100);
7485 format %{ "CMP EAX,0x80000000\n\t"
7486 "JNE,s normal\n\t"
7487 "XOR EDX,EDX\n\t"
7488 "CMP ECX,-1\n\t"
7489 "JE,s done\n"
7490 "normal: CDQ\n\t"
7491 "IDIV $div\n\t"
7492 "done:" %}
7493 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7494 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7495 ins_pipe( ialu_reg_reg_alu0 );
7496 %}
7497
7498 // Divide Register Long
7499 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
7500 match(Set dst (DivL src1 src2));
7501 effect( KILL cr, KILL cx, KILL bx );
7502 ins_cost(10000);
7503 format %{ "PUSH $src1.hi\n\t"
7504 "PUSH $src1.lo\n\t"
7505 "PUSH $src2.hi\n\t"
7506 "PUSH $src2.lo\n\t"
7507 "CALL SharedRuntime::ldiv\n\t"
7508 "ADD ESP,16" %}
7509 ins_encode( long_div(src1,src2) );
7510 ins_pipe( pipe_slow );
7511 %}
7512
7513 // Integer DIVMOD with Register, both quotient and mod results
7514 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
7515 match(DivModI rax div);
7516 effect(KILL cr);
7517 size(26);
7518 ins_cost(30*100+10*100);
7519 format %{ "CMP EAX,0x80000000\n\t"
7520 "JNE,s normal\n\t"
7521 "XOR EDX,EDX\n\t"
7522 "CMP ECX,-1\n\t"
7523 "JE,s done\n"
7524 "normal: CDQ\n\t"
7525 "IDIV $div\n\t"
7526 "done:" %}
7527 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7528 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7529 ins_pipe( pipe_slow );
7530 %}
7531
7532 // Integer MOD with Register
7533 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
7534 match(Set rdx (ModI rax div));
7535 effect(KILL rax, KILL cr);
7536
7537 size(26);
7538 ins_cost(300);
7539 format %{ "CDQ\n\t"
7540 "IDIV $div" %}
7541 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7542 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7543 ins_pipe( ialu_reg_reg_alu0 );
7544 %}
7545
7546 // Remainder Register Long
7547 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
7548 match(Set dst (ModL src1 src2));
7549 effect( KILL cr, KILL cx, KILL bx );
7550 ins_cost(10000);
7551 format %{ "PUSH $src1.hi\n\t"
7552 "PUSH $src1.lo\n\t"
7553 "PUSH $src2.hi\n\t"
7554 "PUSH $src2.lo\n\t"
7555 "CALL SharedRuntime::lrem\n\t"
7556 "ADD ESP,16" %}
7557 ins_encode( long_mod(src1,src2) );
7558 ins_pipe( pipe_slow );
7559 %}
7560
7561 // Divide Register Long (no special case since divisor != -1)
7562 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
7563 match(Set dst (DivL dst imm));
7564 effect( TEMP tmp, TEMP tmp2, KILL cr );
7565 ins_cost(1000);
7566 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
7567 "XOR $tmp2,$tmp2\n\t"
7568 "CMP $tmp,EDX\n\t"
7569 "JA,s fast\n\t"
7570 "MOV $tmp2,EAX\n\t"
7571 "MOV EAX,EDX\n\t"
7572 "MOV EDX,0\n\t"
7573 "JLE,s pos\n\t"
7574 "LNEG EAX : $tmp2\n\t"
7575 "DIV $tmp # unsigned division\n\t"
7576 "XCHG EAX,$tmp2\n\t"
7577 "DIV $tmp\n\t"
7578 "LNEG $tmp2 : EAX\n\t"
7579 "JMP,s done\n"
7580 "pos:\n\t"
7581 "DIV $tmp\n\t"
7582 "XCHG EAX,$tmp2\n"
7583 "fast:\n\t"
7584 "DIV $tmp\n"
7585 "done:\n\t"
7586 "MOV EDX,$tmp2\n\t"
7587 "NEG EDX:EAX # if $imm < 0" %}
7588 ins_encode %{
7589 int con = (int)$imm$$constant;
7590 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
7591 int pcon = (con > 0) ? con : -con;
7592 Label Lfast, Lpos, Ldone;
7593
7594 __ movl($tmp$$Register, pcon);
7595 __ xorl($tmp2$$Register,$tmp2$$Register);
7596 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
7597 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
7598
7599 __ movl($tmp2$$Register, $dst$$Register); // save
7600 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7601 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
7602 __ jccb(Assembler::lessEqual, Lpos); // result is positive
7603
7604 // Negative dividend.
7605 // convert value to positive to use unsigned division
7606 __ lneg($dst$$Register, $tmp2$$Register);
7607 __ divl($tmp$$Register);
7608 __ xchgl($dst$$Register, $tmp2$$Register);
7609 __ divl($tmp$$Register);
7610 // revert result back to negative
7611 __ lneg($tmp2$$Register, $dst$$Register);
7612 __ jmpb(Ldone);
7613
7614 __ bind(Lpos);
7615 __ divl($tmp$$Register); // Use unsigned division
7616 __ xchgl($dst$$Register, $tmp2$$Register);
7617 // Fallthrow for final divide, tmp2 has 32 bit hi result
7618
7619 __ bind(Lfast);
7620 // fast path: src is positive
7621 __ divl($tmp$$Register); // Use unsigned division
7622
7623 __ bind(Ldone);
7624 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
7625 if (con < 0) {
7626 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
7627 }
7628 %}
7629 ins_pipe( pipe_slow );
7630 %}
7631
7632 // Remainder Register Long (remainder fit into 32 bits)
7633 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
7634 match(Set dst (ModL dst imm));
7635 effect( TEMP tmp, TEMP tmp2, KILL cr );
7636 ins_cost(1000);
7637 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
7638 "CMP $tmp,EDX\n\t"
7639 "JA,s fast\n\t"
7640 "MOV $tmp2,EAX\n\t"
7641 "MOV EAX,EDX\n\t"
7642 "MOV EDX,0\n\t"
7643 "JLE,s pos\n\t"
7644 "LNEG EAX : $tmp2\n\t"
7645 "DIV $tmp # unsigned division\n\t"
7646 "MOV EAX,$tmp2\n\t"
7647 "DIV $tmp\n\t"
7648 "NEG EDX\n\t"
7649 "JMP,s done\n"
7650 "pos:\n\t"
7651 "DIV $tmp\n\t"
7652 "MOV EAX,$tmp2\n"
7653 "fast:\n\t"
7654 "DIV $tmp\n"
7655 "done:\n\t"
7656 "MOV EAX,EDX\n\t"
7657 "SAR EDX,31\n\t" %}
7658 ins_encode %{
7659 int con = (int)$imm$$constant;
7660 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
7661 int pcon = (con > 0) ? con : -con;
7662 Label Lfast, Lpos, Ldone;
7663
7664 __ movl($tmp$$Register, pcon);
7665 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
7666 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
7667
7668 __ movl($tmp2$$Register, $dst$$Register); // save
7669 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7670 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
7671 __ jccb(Assembler::lessEqual, Lpos); // result is positive
7672
7673 // Negative dividend.
7674 // convert value to positive to use unsigned division
7675 __ lneg($dst$$Register, $tmp2$$Register);
7676 __ divl($tmp$$Register);
7677 __ movl($dst$$Register, $tmp2$$Register);
7678 __ divl($tmp$$Register);
7679 // revert remainder back to negative
7680 __ negl(HIGH_FROM_LOW($dst$$Register));
7681 __ jmpb(Ldone);
7682
7683 __ bind(Lpos);
7684 __ divl($tmp$$Register);
7685 __ movl($dst$$Register, $tmp2$$Register);
7686
7687 __ bind(Lfast);
7688 // fast path: src is positive
7689 __ divl($tmp$$Register);
7690
7691 __ bind(Ldone);
7692 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7693 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
7694
7695 %}
7696 ins_pipe( pipe_slow );
7697 %}
7698
7699 // Integer Shift Instructions
7700 // Shift Left by one
7701 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7702 match(Set dst (LShiftI dst shift));
7703 effect(KILL cr);
7704
7705 size(2);
7706 format %{ "SHL $dst,$shift" %}
7707 opcode(0xD1, 0x4); /* D1 /4 */
7708 ins_encode( OpcP, RegOpc( dst ) );
7709 ins_pipe( ialu_reg );
7710 %}
7711
7712 // Shift Left by 8-bit immediate
7713 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7714 match(Set dst (LShiftI dst shift));
7715 effect(KILL cr);
7716
7717 size(3);
7718 format %{ "SHL $dst,$shift" %}
7719 opcode(0xC1, 0x4); /* C1 /4 ib */
7720 ins_encode( RegOpcImm( dst, shift) );
7721 ins_pipe( ialu_reg );
7722 %}
7723
7724 // Shift Left by variable
7725 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7726 match(Set dst (LShiftI dst shift));
7727 effect(KILL cr);
7728
7729 size(2);
7730 format %{ "SHL $dst,$shift" %}
7731 opcode(0xD3, 0x4); /* D3 /4 */
7732 ins_encode( OpcP, RegOpc( dst ) );
7733 ins_pipe( ialu_reg_reg );
7734 %}
7735
7736 // Arithmetic shift right by one
7737 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7738 match(Set dst (RShiftI dst shift));
7739 effect(KILL cr);
7740
7741 size(2);
7742 format %{ "SAR $dst,$shift" %}
7743 opcode(0xD1, 0x7); /* D1 /7 */
7744 ins_encode( OpcP, RegOpc( dst ) );
7745 ins_pipe( ialu_reg );
7746 %}
7747
7748 // Arithmetic shift right by one
7749 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
7750 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7751 effect(KILL cr);
7752 format %{ "SAR $dst,$shift" %}
7753 opcode(0xD1, 0x7); /* D1 /7 */
7754 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
7755 ins_pipe( ialu_mem_imm );
7756 %}
7757
7758 // Arithmetic Shift Right by 8-bit immediate
7759 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7760 match(Set dst (RShiftI dst shift));
7761 effect(KILL cr);
7762
7763 size(3);
7764 format %{ "SAR $dst,$shift" %}
7765 opcode(0xC1, 0x7); /* C1 /7 ib */
7766 ins_encode( RegOpcImm( dst, shift ) );
7767 ins_pipe( ialu_mem_imm );
7768 %}
7769
7770 // Arithmetic Shift Right by 8-bit immediate
7771 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
7772 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7773 effect(KILL cr);
7774
7775 format %{ "SAR $dst,$shift" %}
7776 opcode(0xC1, 0x7); /* C1 /7 ib */
7777 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
7778 ins_pipe( ialu_mem_imm );
7779 %}
7780
7781 // Arithmetic Shift Right by variable
7782 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7783 match(Set dst (RShiftI dst shift));
7784 effect(KILL cr);
7785
7786 size(2);
7787 format %{ "SAR $dst,$shift" %}
7788 opcode(0xD3, 0x7); /* D3 /7 */
7789 ins_encode( OpcP, RegOpc( dst ) );
7790 ins_pipe( ialu_reg_reg );
7791 %}
7792
7793 // Logical shift right by one
7794 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7795 match(Set dst (URShiftI dst shift));
7796 effect(KILL cr);
7797
7798 size(2);
7799 format %{ "SHR $dst,$shift" %}
7800 opcode(0xD1, 0x5); /* D1 /5 */
7801 ins_encode( OpcP, RegOpc( dst ) );
7802 ins_pipe( ialu_reg );
7803 %}
7804
7805 // Logical Shift Right by 8-bit immediate
7806 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7807 match(Set dst (URShiftI dst shift));
7808 effect(KILL cr);
7809
7810 size(3);
7811 format %{ "SHR $dst,$shift" %}
7812 opcode(0xC1, 0x5); /* C1 /5 ib */
7813 ins_encode( RegOpcImm( dst, shift) );
7814 ins_pipe( ialu_reg );
7815 %}
7816
7817
7818 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
7819 // This idiom is used by the compiler for the i2b bytecode.
7820 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
7821 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
7822
7823 size(3);
7824 format %{ "MOVSX $dst,$src :8" %}
7825 ins_encode %{
7826 __ movsbl($dst$$Register, $src$$Register);
7827 %}
7828 ins_pipe(ialu_reg_reg);
7829 %}
7830
7831 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
7832 // This idiom is used by the compiler the i2s bytecode.
7833 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
7834 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
7835
7836 size(3);
7837 format %{ "MOVSX $dst,$src :16" %}
7838 ins_encode %{
7839 __ movswl($dst$$Register, $src$$Register);
7840 %}
7841 ins_pipe(ialu_reg_reg);
7842 %}
7843
7844
7845 // Logical Shift Right by variable
7846 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7847 match(Set dst (URShiftI dst shift));
7848 effect(KILL cr);
7849
7850 size(2);
7851 format %{ "SHR $dst,$shift" %}
7852 opcode(0xD3, 0x5); /* D3 /5 */
7853 ins_encode( OpcP, RegOpc( dst ) );
7854 ins_pipe( ialu_reg_reg );
7855 %}
7856
7857
7858 //----------Logical Instructions-----------------------------------------------
7859 //----------Integer Logical Instructions---------------------------------------
7860 // And Instructions
7861 // And Register with Register
7862 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7863 match(Set dst (AndI dst src));
7864 effect(KILL cr);
7865
7866 size(2);
7867 format %{ "AND $dst,$src" %}
7868 opcode(0x23);
7869 ins_encode( OpcP, RegReg( dst, src) );
7870 ins_pipe( ialu_reg_reg );
7871 %}
7872
7873 // And Register with Immediate
7874 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7875 match(Set dst (AndI dst src));
7876 effect(KILL cr);
7877
7878 format %{ "AND $dst,$src" %}
7879 opcode(0x81,0x04); /* Opcode 81 /4 */
7880 // ins_encode( RegImm( dst, src) );
7881 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7882 ins_pipe( ialu_reg );
7883 %}
7884
7885 // And Register with Memory
7886 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7887 match(Set dst (AndI dst (LoadI src)));
7888 effect(KILL cr);
7889
7890 ins_cost(125);
7891 format %{ "AND $dst,$src" %}
7892 opcode(0x23);
7893 ins_encode( OpcP, RegMem( dst, src) );
7894 ins_pipe( ialu_reg_mem );
7895 %}
7896
7897 // And Memory with Register
7898 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7899 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
7900 effect(KILL cr);
7901
7902 ins_cost(150);
7903 format %{ "AND $dst,$src" %}
7904 opcode(0x21); /* Opcode 21 /r */
7905 ins_encode( OpcP, RegMem( src, dst ) );
7906 ins_pipe( ialu_mem_reg );
7907 %}
7908
7909 // And Memory with Immediate
7910 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7911 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
7912 effect(KILL cr);
7913
7914 ins_cost(125);
7915 format %{ "AND $dst,$src" %}
7916 opcode(0x81, 0x4); /* Opcode 81 /4 id */
7917 // ins_encode( MemImm( dst, src) );
7918 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
7919 ins_pipe( ialu_mem_imm );
7920 %}
7921
7922 // BMI1 instructions
7923 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, eFlagsReg cr) %{
7924 match(Set dst (AndI (XorI src1 minus_1) src2));
7925 predicate(UseBMI1Instructions);
7926 effect(KILL cr);
7927
7928 format %{ "ANDNL $dst, $src1, $src2" %}
7929
7930 ins_encode %{
7931 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
7932 %}
7933 ins_pipe(ialu_reg);
7934 %}
7935
7936 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{
7937 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) ));
7938 predicate(UseBMI1Instructions);
7939 effect(KILL cr);
7940
7941 ins_cost(125);
7942 format %{ "ANDNL $dst, $src1, $src2" %}
7943
7944 ins_encode %{
7945 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
7946 %}
7947 ins_pipe(ialu_reg_mem);
7948 %}
7949
7950 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{
7951 match(Set dst (AndI (SubI imm_zero src) src));
7952 predicate(UseBMI1Instructions);
7953 effect(KILL cr);
7954
7955 format %{ "BLSIL $dst, $src" %}
7956
7957 ins_encode %{
7958 __ blsil($dst$$Register, $src$$Register);
7959 %}
7960 ins_pipe(ialu_reg);
7961 %}
7962
7963 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{
7964 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
7965 predicate(UseBMI1Instructions);
7966 effect(KILL cr);
7967
7968 ins_cost(125);
7969 format %{ "BLSIL $dst, $src" %}
7970
7971 ins_encode %{
7972 __ blsil($dst$$Register, $src$$Address);
7973 %}
7974 ins_pipe(ialu_reg_mem);
7975 %}
7976
7977 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
7978 %{
7979 match(Set dst (XorI (AddI src minus_1) src));
7980 predicate(UseBMI1Instructions);
7981 effect(KILL cr);
7982
7983 format %{ "BLSMSKL $dst, $src" %}
7984
7985 ins_encode %{
7986 __ blsmskl($dst$$Register, $src$$Register);
7987 %}
7988
7989 ins_pipe(ialu_reg);
7990 %}
7991
7992 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
7993 %{
7994 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ));
7995 predicate(UseBMI1Instructions);
7996 effect(KILL cr);
7997
7998 ins_cost(125);
7999 format %{ "BLSMSKL $dst, $src" %}
8000
8001 ins_encode %{
8002 __ blsmskl($dst$$Register, $src$$Address);
8003 %}
8004
8005 ins_pipe(ialu_reg_mem);
8006 %}
8007
8008 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8009 %{
8010 match(Set dst (AndI (AddI src minus_1) src) );
8011 predicate(UseBMI1Instructions);
8012 effect(KILL cr);
8013
8014 format %{ "BLSRL $dst, $src" %}
8015
8016 ins_encode %{
8017 __ blsrl($dst$$Register, $src$$Register);
8018 %}
8019
8020 ins_pipe(ialu_reg);
8021 %}
8022
8023 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
8024 %{
8025 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ));
8026 predicate(UseBMI1Instructions);
8027 effect(KILL cr);
8028
8029 ins_cost(125);
8030 format %{ "BLSRL $dst, $src" %}
8031
8032 ins_encode %{
8033 __ blsrl($dst$$Register, $src$$Address);
8034 %}
8035
8036 ins_pipe(ialu_reg_mem);
8037 %}
8038
8039 // Or Instructions
8040 // Or Register with Register
8041 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8042 match(Set dst (OrI dst src));
8043 effect(KILL cr);
8044
8045 size(2);
8046 format %{ "OR $dst,$src" %}
8047 opcode(0x0B);
8048 ins_encode( OpcP, RegReg( dst, src) );
8049 ins_pipe( ialu_reg_reg );
8050 %}
8051
8052 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8053 match(Set dst (OrI dst (CastP2X src)));
8054 effect(KILL cr);
8055
8056 size(2);
8057 format %{ "OR $dst,$src" %}
8058 opcode(0x0B);
8059 ins_encode( OpcP, RegReg( dst, src) );
8060 ins_pipe( ialu_reg_reg );
8061 %}
8062
8063
8064 // Or Register with Immediate
8065 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8066 match(Set dst (OrI dst src));
8067 effect(KILL cr);
8068
8069 format %{ "OR $dst,$src" %}
8070 opcode(0x81,0x01); /* Opcode 81 /1 id */
8071 // ins_encode( RegImm( dst, src) );
8072 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8073 ins_pipe( ialu_reg );
8074 %}
8075
8076 // Or Register with Memory
8077 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8078 match(Set dst (OrI dst (LoadI src)));
8079 effect(KILL cr);
8080
8081 ins_cost(125);
8082 format %{ "OR $dst,$src" %}
8083 opcode(0x0B);
8084 ins_encode( OpcP, RegMem( dst, src) );
8085 ins_pipe( ialu_reg_mem );
8086 %}
8087
8088 // Or Memory with Register
8089 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8090 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8091 effect(KILL cr);
8092
8093 ins_cost(150);
8094 format %{ "OR $dst,$src" %}
8095 opcode(0x09); /* Opcode 09 /r */
8096 ins_encode( OpcP, RegMem( src, dst ) );
8097 ins_pipe( ialu_mem_reg );
8098 %}
8099
8100 // Or Memory with Immediate
8101 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8102 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8103 effect(KILL cr);
8104
8105 ins_cost(125);
8106 format %{ "OR $dst,$src" %}
8107 opcode(0x81,0x1); /* Opcode 81 /1 id */
8108 // ins_encode( MemImm( dst, src) );
8109 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8110 ins_pipe( ialu_mem_imm );
8111 %}
8112
8113 // ROL/ROR
8114 // ROL expand
8115 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8116 effect(USE_DEF dst, USE shift, KILL cr);
8117
8118 format %{ "ROL $dst, $shift" %}
8119 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8120 ins_encode( OpcP, RegOpc( dst ));
8121 ins_pipe( ialu_reg );
8122 %}
8123
8124 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8125 effect(USE_DEF dst, USE shift, KILL cr);
8126
8127 format %{ "ROL $dst, $shift" %}
8128 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8129 ins_encode( RegOpcImm(dst, shift) );
8130 ins_pipe(ialu_reg);
8131 %}
8132
8133 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8134 effect(USE_DEF dst, USE shift, KILL cr);
8135
8136 format %{ "ROL $dst, $shift" %}
8137 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8138 ins_encode(OpcP, RegOpc(dst));
8139 ins_pipe( ialu_reg_reg );
8140 %}
8141 // end of ROL expand
8142
8143 // ROL 32bit by one once
8144 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8145 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8146
8147 expand %{
8148 rolI_eReg_imm1(dst, lshift, cr);
8149 %}
8150 %}
8151
8152 // ROL 32bit var by imm8 once
8153 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8154 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8155 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8156
8157 expand %{
8158 rolI_eReg_imm8(dst, lshift, cr);
8159 %}
8160 %}
8161
8162 // ROL 32bit var by var once
8163 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8164 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8165
8166 expand %{
8167 rolI_eReg_CL(dst, shift, cr);
8168 %}
8169 %}
8170
8171 // ROL 32bit var by var once
8172 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8173 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8174
8175 expand %{
8176 rolI_eReg_CL(dst, shift, cr);
8177 %}
8178 %}
8179
8180 // ROR expand
8181 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8182 effect(USE_DEF dst, USE shift, KILL cr);
8183
8184 format %{ "ROR $dst, $shift" %}
8185 opcode(0xD1,0x1); /* Opcode D1 /1 */
8186 ins_encode( OpcP, RegOpc( dst ) );
8187 ins_pipe( ialu_reg );
8188 %}
8189
8190 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8191 effect (USE_DEF dst, USE shift, KILL cr);
8192
8193 format %{ "ROR $dst, $shift" %}
8194 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8195 ins_encode( RegOpcImm(dst, shift) );
8196 ins_pipe( ialu_reg );
8197 %}
8198
8199 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8200 effect(USE_DEF dst, USE shift, KILL cr);
8201
8202 format %{ "ROR $dst, $shift" %}
8203 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8204 ins_encode(OpcP, RegOpc(dst));
8205 ins_pipe( ialu_reg_reg );
8206 %}
8207 // end of ROR expand
8208
8209 // ROR right once
8210 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8211 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8212
8213 expand %{
8214 rorI_eReg_imm1(dst, rshift, cr);
8215 %}
8216 %}
8217
8218 // ROR 32bit by immI8 once
8219 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8220 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8221 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8222
8223 expand %{
8224 rorI_eReg_imm8(dst, rshift, cr);
8225 %}
8226 %}
8227
8228 // ROR 32bit var by var once
8229 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8230 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8231
8232 expand %{
8233 rorI_eReg_CL(dst, shift, cr);
8234 %}
8235 %}
8236
8237 // ROR 32bit var by var once
8238 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8239 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8240
8241 expand %{
8242 rorI_eReg_CL(dst, shift, cr);
8243 %}
8244 %}
8245
8246 // Xor Instructions
8247 // Xor Register with Register
8248 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8249 match(Set dst (XorI dst src));
8250 effect(KILL cr);
8251
8252 size(2);
8253 format %{ "XOR $dst,$src" %}
8254 opcode(0x33);
8255 ins_encode( OpcP, RegReg( dst, src) );
8256 ins_pipe( ialu_reg_reg );
8257 %}
8258
8259 // Xor Register with Immediate -1
8260 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8261 match(Set dst (XorI dst imm));
8262
8263 size(2);
8264 format %{ "NOT $dst" %}
8265 ins_encode %{
8266 __ notl($dst$$Register);
8267 %}
8268 ins_pipe( ialu_reg );
8269 %}
8270
8271 // Xor Register with Immediate
8272 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8273 match(Set dst (XorI dst src));
8274 effect(KILL cr);
8275
8276 format %{ "XOR $dst,$src" %}
8277 opcode(0x81,0x06); /* Opcode 81 /6 id */
8278 // ins_encode( RegImm( dst, src) );
8279 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8280 ins_pipe( ialu_reg );
8281 %}
8282
8283 // Xor Register with Memory
8284 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8285 match(Set dst (XorI dst (LoadI src)));
8286 effect(KILL cr);
8287
8288 ins_cost(125);
8289 format %{ "XOR $dst,$src" %}
8290 opcode(0x33);
8291 ins_encode( OpcP, RegMem(dst, src) );
8292 ins_pipe( ialu_reg_mem );
8293 %}
8294
8295 // Xor Memory with Register
8296 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8297 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8298 effect(KILL cr);
8299
8300 ins_cost(150);
8301 format %{ "XOR $dst,$src" %}
8302 opcode(0x31); /* Opcode 31 /r */
8303 ins_encode( OpcP, RegMem( src, dst ) );
8304 ins_pipe( ialu_mem_reg );
8305 %}
8306
8307 // Xor Memory with Immediate
8308 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8309 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8310 effect(KILL cr);
8311
8312 ins_cost(125);
8313 format %{ "XOR $dst,$src" %}
8314 opcode(0x81,0x6); /* Opcode 81 /6 id */
8315 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8316 ins_pipe( ialu_mem_imm );
8317 %}
8318
8319 //----------Convert Int to Boolean---------------------------------------------
8320
8321 instruct movI_nocopy(rRegI dst, rRegI src) %{
8322 effect( DEF dst, USE src );
8323 format %{ "MOV $dst,$src" %}
8324 ins_encode( enc_Copy( dst, src) );
8325 ins_pipe( ialu_reg_reg );
8326 %}
8327
8328 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8329 effect( USE_DEF dst, USE src, KILL cr );
8330
8331 size(4);
8332 format %{ "NEG $dst\n\t"
8333 "ADC $dst,$src" %}
8334 ins_encode( neg_reg(dst),
8335 OpcRegReg(0x13,dst,src) );
8336 ins_pipe( ialu_reg_reg_long );
8337 %}
8338
8339 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8340 match(Set dst (Conv2B src));
8341
8342 expand %{
8343 movI_nocopy(dst,src);
8344 ci2b(dst,src,cr);
8345 %}
8346 %}
8347
8348 instruct movP_nocopy(rRegI dst, eRegP src) %{
8349 effect( DEF dst, USE src );
8350 format %{ "MOV $dst,$src" %}
8351 ins_encode( enc_Copy( dst, src) );
8352 ins_pipe( ialu_reg_reg );
8353 %}
8354
8355 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8356 effect( USE_DEF dst, USE src, KILL cr );
8357 format %{ "NEG $dst\n\t"
8358 "ADC $dst,$src" %}
8359 ins_encode( neg_reg(dst),
8360 OpcRegReg(0x13,dst,src) );
8361 ins_pipe( ialu_reg_reg_long );
8362 %}
8363
8364 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8365 match(Set dst (Conv2B src));
8366
8367 expand %{
8368 movP_nocopy(dst,src);
8369 cp2b(dst,src,cr);
8370 %}
8371 %}
8372
8373 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
8374 match(Set dst (CmpLTMask p q));
8375 effect(KILL cr);
8376 ins_cost(400);
8377
8378 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8379 format %{ "XOR $dst,$dst\n\t"
8380 "CMP $p,$q\n\t"
8381 "SETlt $dst\n\t"
8382 "NEG $dst" %}
8383 ins_encode %{
8384 Register Rp = $p$$Register;
8385 Register Rq = $q$$Register;
8386 Register Rd = $dst$$Register;
8387 Label done;
8388 __ xorl(Rd, Rd);
8389 __ cmpl(Rp, Rq);
8390 __ setb(Assembler::less, Rd);
8391 __ negl(Rd);
8392 %}
8393
8394 ins_pipe(pipe_slow);
8395 %}
8396
8397 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
8398 match(Set dst (CmpLTMask dst zero));
8399 effect(DEF dst, KILL cr);
8400 ins_cost(100);
8401
8402 format %{ "SAR $dst,31\t# cmpLTMask0" %}
8403 ins_encode %{
8404 __ sarl($dst$$Register, 31);
8405 %}
8406 ins_pipe(ialu_reg);
8407 %}
8408
8409 /* better to save a register than avoid a branch */
8410 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8411 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8412 effect(KILL cr);
8413 ins_cost(400);
8414 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
8415 "JGE done\n\t"
8416 "ADD $p,$y\n"
8417 "done: " %}
8418 ins_encode %{
8419 Register Rp = $p$$Register;
8420 Register Rq = $q$$Register;
8421 Register Ry = $y$$Register;
8422 Label done;
8423 __ subl(Rp, Rq);
8424 __ jccb(Assembler::greaterEqual, done);
8425 __ addl(Rp, Ry);
8426 __ bind(done);
8427 %}
8428
8429 ins_pipe(pipe_cmplt);
8430 %}
8431
8432 /* better to save a register than avoid a branch */
8433 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8434 match(Set y (AndI (CmpLTMask p q) y));
8435 effect(KILL cr);
8436
8437 ins_cost(300);
8438
8439 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
8440 "JLT done\n\t"
8441 "XORL $y, $y\n"
8442 "done: " %}
8443 ins_encode %{
8444 Register Rp = $p$$Register;
8445 Register Rq = $q$$Register;
8446 Register Ry = $y$$Register;
8447 Label done;
8448 __ cmpl(Rp, Rq);
8449 __ jccb(Assembler::less, done);
8450 __ xorl(Ry, Ry);
8451 __ bind(done);
8452 %}
8453
8454 ins_pipe(pipe_cmplt);
8455 %}
8456
8457 /* If I enable this, I encourage spilling in the inner loop of compress.
8458 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
8459 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8460 */
8461 //----------Overflow Math Instructions-----------------------------------------
8462
8463 instruct overflowAddI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8464 %{
8465 match(Set cr (OverflowAddI op1 op2));
8466 effect(DEF cr, USE_KILL op1, USE op2);
8467
8468 format %{ "ADD $op1, $op2\t# overflow check int" %}
8469
8470 ins_encode %{
8471 __ addl($op1$$Register, $op2$$Register);
8472 %}
8473 ins_pipe(ialu_reg_reg);
8474 %}
8475
8476 instruct overflowAddI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2)
8477 %{
8478 match(Set cr (OverflowAddI op1 op2));
8479 effect(DEF cr, USE_KILL op1, USE op2);
8480
8481 format %{ "ADD $op1, $op2\t# overflow check int" %}
8482
8483 ins_encode %{
8484 __ addl($op1$$Register, $op2$$constant);
8485 %}
8486 ins_pipe(ialu_reg_reg);
8487 %}
8488
8489 instruct overflowSubI_rReg(eFlagsReg cr, rRegI op1, rRegI op2)
8490 %{
8491 match(Set cr (OverflowSubI op1 op2));
8492
8493 format %{ "CMP $op1, $op2\t# overflow check int" %}
8494 ins_encode %{
8495 __ cmpl($op1$$Register, $op2$$Register);
8496 %}
8497 ins_pipe(ialu_reg_reg);
8498 %}
8499
8500 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2)
8501 %{
8502 match(Set cr (OverflowSubI op1 op2));
8503
8504 format %{ "CMP $op1, $op2\t# overflow check int" %}
8505 ins_encode %{
8506 __ cmpl($op1$$Register, $op2$$constant);
8507 %}
8508 ins_pipe(ialu_reg_reg);
8509 %}
8510
8511 instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2)
8512 %{
8513 match(Set cr (OverflowSubI zero op2));
8514 effect(DEF cr, USE_KILL op2);
8515
8516 format %{ "NEG $op2\t# overflow check int" %}
8517 ins_encode %{
8518 __ negl($op2$$Register);
8519 %}
8520 ins_pipe(ialu_reg_reg);
8521 %}
8522
8523 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8524 %{
8525 match(Set cr (OverflowMulI op1 op2));
8526 effect(DEF cr, USE_KILL op1, USE op2);
8527
8528 format %{ "IMUL $op1, $op2\t# overflow check int" %}
8529 ins_encode %{
8530 __ imull($op1$$Register, $op2$$Register);
8531 %}
8532 ins_pipe(ialu_reg_reg_alu0);
8533 %}
8534
8535 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
8536 %{
8537 match(Set cr (OverflowMulI op1 op2));
8538 effect(DEF cr, TEMP tmp, USE op1, USE op2);
8539
8540 format %{ "IMUL $tmp, $op1, $op2\t# overflow check int" %}
8541 ins_encode %{
8542 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
8543 %}
8544 ins_pipe(ialu_reg_reg_alu0);
8545 %}
8546
8547 //----------Long Instructions------------------------------------------------
8548 // Add Long Register with Register
8549 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8550 match(Set dst (AddL dst src));
8551 effect(KILL cr);
8552 ins_cost(200);
8553 format %{ "ADD $dst.lo,$src.lo\n\t"
8554 "ADC $dst.hi,$src.hi" %}
8555 opcode(0x03, 0x13);
8556 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8557 ins_pipe( ialu_reg_reg_long );
8558 %}
8559
8560 // Add Long Register with Immediate
8561 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8562 match(Set dst (AddL dst src));
8563 effect(KILL cr);
8564 format %{ "ADD $dst.lo,$src.lo\n\t"
8565 "ADC $dst.hi,$src.hi" %}
8566 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8567 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8568 ins_pipe( ialu_reg_long );
8569 %}
8570
8571 // Add Long Register with Memory
8572 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8573 match(Set dst (AddL dst (LoadL mem)));
8574 effect(KILL cr);
8575 ins_cost(125);
8576 format %{ "ADD $dst.lo,$mem\n\t"
8577 "ADC $dst.hi,$mem+4" %}
8578 opcode(0x03, 0x13);
8579 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8580 ins_pipe( ialu_reg_long_mem );
8581 %}
8582
8583 // Subtract Long Register with Register.
8584 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8585 match(Set dst (SubL dst src));
8586 effect(KILL cr);
8587 ins_cost(200);
8588 format %{ "SUB $dst.lo,$src.lo\n\t"
8589 "SBB $dst.hi,$src.hi" %}
8590 opcode(0x2B, 0x1B);
8591 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8592 ins_pipe( ialu_reg_reg_long );
8593 %}
8594
8595 // Subtract Long Register with Immediate
8596 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8597 match(Set dst (SubL dst src));
8598 effect(KILL cr);
8599 format %{ "SUB $dst.lo,$src.lo\n\t"
8600 "SBB $dst.hi,$src.hi" %}
8601 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
8602 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8603 ins_pipe( ialu_reg_long );
8604 %}
8605
8606 // Subtract Long Register with Memory
8607 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8608 match(Set dst (SubL dst (LoadL mem)));
8609 effect(KILL cr);
8610 ins_cost(125);
8611 format %{ "SUB $dst.lo,$mem\n\t"
8612 "SBB $dst.hi,$mem+4" %}
8613 opcode(0x2B, 0x1B);
8614 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8615 ins_pipe( ialu_reg_long_mem );
8616 %}
8617
8618 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
8619 match(Set dst (SubL zero dst));
8620 effect(KILL cr);
8621 ins_cost(300);
8622 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
8623 ins_encode( neg_long(dst) );
8624 ins_pipe( ialu_reg_reg_long );
8625 %}
8626
8627 // And Long Register with Register
8628 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8629 match(Set dst (AndL dst src));
8630 effect(KILL cr);
8631 format %{ "AND $dst.lo,$src.lo\n\t"
8632 "AND $dst.hi,$src.hi" %}
8633 opcode(0x23,0x23);
8634 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8635 ins_pipe( ialu_reg_reg_long );
8636 %}
8637
8638 // And Long Register with Immediate
8639 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8640 match(Set dst (AndL dst src));
8641 effect(KILL cr);
8642 format %{ "AND $dst.lo,$src.lo\n\t"
8643 "AND $dst.hi,$src.hi" %}
8644 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
8645 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8646 ins_pipe( ialu_reg_long );
8647 %}
8648
8649 // And Long Register with Memory
8650 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8651 match(Set dst (AndL dst (LoadL mem)));
8652 effect(KILL cr);
8653 ins_cost(125);
8654 format %{ "AND $dst.lo,$mem\n\t"
8655 "AND $dst.hi,$mem+4" %}
8656 opcode(0x23, 0x23);
8657 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8658 ins_pipe( ialu_reg_long_mem );
8659 %}
8660
8661 // BMI1 instructions
8662 instruct andnL_eReg_eReg_eReg(eRegL dst, eRegL src1, eRegL src2, immL_M1 minus_1, eFlagsReg cr) %{
8663 match(Set dst (AndL (XorL src1 minus_1) src2));
8664 predicate(UseBMI1Instructions);
8665 effect(KILL cr, TEMP dst);
8666
8667 format %{ "ANDNL $dst.lo, $src1.lo, $src2.lo\n\t"
8668 "ANDNL $dst.hi, $src1.hi, $src2.hi"
8669 %}
8670
8671 ins_encode %{
8672 Register Rdst = $dst$$Register;
8673 Register Rsrc1 = $src1$$Register;
8674 Register Rsrc2 = $src2$$Register;
8675 __ andnl(Rdst, Rsrc1, Rsrc2);
8676 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), HIGH_FROM_LOW(Rsrc2));
8677 %}
8678 ins_pipe(ialu_reg_reg_long);
8679 %}
8680
8681 instruct andnL_eReg_eReg_mem(eRegL dst, eRegL src1, memory src2, immL_M1 minus_1, eFlagsReg cr) %{
8682 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2) ));
8683 predicate(UseBMI1Instructions);
8684 effect(KILL cr, TEMP dst);
8685
8686 ins_cost(125);
8687 format %{ "ANDNL $dst.lo, $src1.lo, $src2\n\t"
8688 "ANDNL $dst.hi, $src1.hi, $src2+4"
8689 %}
8690
8691 ins_encode %{
8692 Register Rdst = $dst$$Register;
8693 Register Rsrc1 = $src1$$Register;
8694 Address src2_hi = Address::make_raw($src2$$base, $src2$$index, $src2$$scale, $src2$$disp + 4, relocInfo::none);
8695
8696 __ andnl(Rdst, Rsrc1, $src2$$Address);
8697 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), src2_hi);
8698 %}
8699 ins_pipe(ialu_reg_mem);
8700 %}
8701
8702 instruct blsiL_eReg_eReg(eRegL dst, eRegL src, immL0 imm_zero, eFlagsReg cr) %{
8703 match(Set dst (AndL (SubL imm_zero src) src));
8704 predicate(UseBMI1Instructions);
8705 effect(KILL cr, TEMP dst);
8706
8707 format %{ "MOVL $dst.hi, 0\n\t"
8708 "BLSIL $dst.lo, $src.lo\n\t"
8709 "JNZ done\n\t"
8710 "BLSIL $dst.hi, $src.hi\n"
8711 "done:"
8712 %}
8713
8714 ins_encode %{
8715 Label done;
8716 Register Rdst = $dst$$Register;
8717 Register Rsrc = $src$$Register;
8718 __ movl(HIGH_FROM_LOW(Rdst), 0);
8719 __ blsil(Rdst, Rsrc);
8720 __ jccb(Assembler::notZero, done);
8721 __ blsil(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8722 __ bind(done);
8723 %}
8724 ins_pipe(ialu_reg);
8725 %}
8726
8727 instruct blsiL_eReg_mem(eRegL dst, memory src, immL0 imm_zero, eFlagsReg cr) %{
8728 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
8729 predicate(UseBMI1Instructions);
8730 effect(KILL cr, TEMP dst);
8731
8732 ins_cost(125);
8733 format %{ "MOVL $dst.hi, 0\n\t"
8734 "BLSIL $dst.lo, $src\n\t"
8735 "JNZ done\n\t"
8736 "BLSIL $dst.hi, $src+4\n"
8737 "done:"
8738 %}
8739
8740 ins_encode %{
8741 Label done;
8742 Register Rdst = $dst$$Register;
8743 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8744
8745 __ movl(HIGH_FROM_LOW(Rdst), 0);
8746 __ blsil(Rdst, $src$$Address);
8747 __ jccb(Assembler::notZero, done);
8748 __ blsil(HIGH_FROM_LOW(Rdst), src_hi);
8749 __ bind(done);
8750 %}
8751 ins_pipe(ialu_reg_mem);
8752 %}
8753
8754 instruct blsmskL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
8755 %{
8756 match(Set dst (XorL (AddL src minus_1) src));
8757 predicate(UseBMI1Instructions);
8758 effect(KILL cr, TEMP dst);
8759
8760 format %{ "MOVL $dst.hi, 0\n\t"
8761 "BLSMSKL $dst.lo, $src.lo\n\t"
8762 "JNC done\n\t"
8763 "BLSMSKL $dst.hi, $src.hi\n"
8764 "done:"
8765 %}
8766
8767 ins_encode %{
8768 Label done;
8769 Register Rdst = $dst$$Register;
8770 Register Rsrc = $src$$Register;
8771 __ movl(HIGH_FROM_LOW(Rdst), 0);
8772 __ blsmskl(Rdst, Rsrc);
8773 __ jccb(Assembler::carryClear, done);
8774 __ blsmskl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8775 __ bind(done);
8776 %}
8777
8778 ins_pipe(ialu_reg);
8779 %}
8780
8781 instruct blsmskL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
8782 %{
8783 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ));
8784 predicate(UseBMI1Instructions);
8785 effect(KILL cr, TEMP dst);
8786
8787 ins_cost(125);
8788 format %{ "MOVL $dst.hi, 0\n\t"
8789 "BLSMSKL $dst.lo, $src\n\t"
8790 "JNC done\n\t"
8791 "BLSMSKL $dst.hi, $src+4\n"
8792 "done:"
8793 %}
8794
8795 ins_encode %{
8796 Label done;
8797 Register Rdst = $dst$$Register;
8798 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8799
8800 __ movl(HIGH_FROM_LOW(Rdst), 0);
8801 __ blsmskl(Rdst, $src$$Address);
8802 __ jccb(Assembler::carryClear, done);
8803 __ blsmskl(HIGH_FROM_LOW(Rdst), src_hi);
8804 __ bind(done);
8805 %}
8806
8807 ins_pipe(ialu_reg_mem);
8808 %}
8809
8810 instruct blsrL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
8811 %{
8812 match(Set dst (AndL (AddL src minus_1) src) );
8813 predicate(UseBMI1Instructions);
8814 effect(KILL cr, TEMP dst);
8815
8816 format %{ "MOVL $dst.hi, $src.hi\n\t"
8817 "BLSRL $dst.lo, $src.lo\n\t"
8818 "JNC done\n\t"
8819 "BLSRL $dst.hi, $src.hi\n"
8820 "done:"
8821 %}
8822
8823 ins_encode %{
8824 Label done;
8825 Register Rdst = $dst$$Register;
8826 Register Rsrc = $src$$Register;
8827 __ movl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8828 __ blsrl(Rdst, Rsrc);
8829 __ jccb(Assembler::carryClear, done);
8830 __ blsrl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8831 __ bind(done);
8832 %}
8833
8834 ins_pipe(ialu_reg);
8835 %}
8836
8837 instruct blsrL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
8838 %{
8839 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src) ));
8840 predicate(UseBMI1Instructions);
8841 effect(KILL cr, TEMP dst);
8842
8843 ins_cost(125);
8844 format %{ "MOVL $dst.hi, $src+4\n\t"
8845 "BLSRL $dst.lo, $src\n\t"
8846 "JNC done\n\t"
8847 "BLSRL $dst.hi, $src+4\n"
8848 "done:"
8849 %}
8850
8851 ins_encode %{
8852 Label done;
8853 Register Rdst = $dst$$Register;
8854 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8855 __ movl(HIGH_FROM_LOW(Rdst), src_hi);
8856 __ blsrl(Rdst, $src$$Address);
8857 __ jccb(Assembler::carryClear, done);
8858 __ blsrl(HIGH_FROM_LOW(Rdst), src_hi);
8859 __ bind(done);
8860 %}
8861
8862 ins_pipe(ialu_reg_mem);
8863 %}
8864
8865 // Or Long Register with Register
8866 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8867 match(Set dst (OrL dst src));
8868 effect(KILL cr);
8869 format %{ "OR $dst.lo,$src.lo\n\t"
8870 "OR $dst.hi,$src.hi" %}
8871 opcode(0x0B,0x0B);
8872 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8873 ins_pipe( ialu_reg_reg_long );
8874 %}
8875
8876 // Or Long Register with Immediate
8877 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8878 match(Set dst (OrL dst src));
8879 effect(KILL cr);
8880 format %{ "OR $dst.lo,$src.lo\n\t"
8881 "OR $dst.hi,$src.hi" %}
8882 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
8883 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8884 ins_pipe( ialu_reg_long );
8885 %}
8886
8887 // Or Long Register with Memory
8888 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8889 match(Set dst (OrL dst (LoadL mem)));
8890 effect(KILL cr);
8891 ins_cost(125);
8892 format %{ "OR $dst.lo,$mem\n\t"
8893 "OR $dst.hi,$mem+4" %}
8894 opcode(0x0B,0x0B);
8895 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8896 ins_pipe( ialu_reg_long_mem );
8897 %}
8898
8899 // Xor Long Register with Register
8900 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8901 match(Set dst (XorL dst src));
8902 effect(KILL cr);
8903 format %{ "XOR $dst.lo,$src.lo\n\t"
8904 "XOR $dst.hi,$src.hi" %}
8905 opcode(0x33,0x33);
8906 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8907 ins_pipe( ialu_reg_reg_long );
8908 %}
8909
8910 // Xor Long Register with Immediate -1
8911 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
8912 match(Set dst (XorL dst imm));
8913 format %{ "NOT $dst.lo\n\t"
8914 "NOT $dst.hi" %}
8915 ins_encode %{
8916 __ notl($dst$$Register);
8917 __ notl(HIGH_FROM_LOW($dst$$Register));
8918 %}
8919 ins_pipe( ialu_reg_long );
8920 %}
8921
8922 // Xor Long Register with Immediate
8923 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8924 match(Set dst (XorL dst src));
8925 effect(KILL cr);
8926 format %{ "XOR $dst.lo,$src.lo\n\t"
8927 "XOR $dst.hi,$src.hi" %}
8928 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
8929 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8930 ins_pipe( ialu_reg_long );
8931 %}
8932
8933 // Xor Long Register with Memory
8934 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8935 match(Set dst (XorL dst (LoadL mem)));
8936 effect(KILL cr);
8937 ins_cost(125);
8938 format %{ "XOR $dst.lo,$mem\n\t"
8939 "XOR $dst.hi,$mem+4" %}
8940 opcode(0x33,0x33);
8941 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8942 ins_pipe( ialu_reg_long_mem );
8943 %}
8944
8945 // Shift Left Long by 1
8946 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
8947 predicate(UseNewLongLShift);
8948 match(Set dst (LShiftL dst cnt));
8949 effect(KILL cr);
8950 ins_cost(100);
8951 format %{ "ADD $dst.lo,$dst.lo\n\t"
8952 "ADC $dst.hi,$dst.hi" %}
8953 ins_encode %{
8954 __ addl($dst$$Register,$dst$$Register);
8955 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8956 %}
8957 ins_pipe( ialu_reg_long );
8958 %}
8959
8960 // Shift Left Long by 2
8961 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
8962 predicate(UseNewLongLShift);
8963 match(Set dst (LShiftL dst cnt));
8964 effect(KILL cr);
8965 ins_cost(100);
8966 format %{ "ADD $dst.lo,$dst.lo\n\t"
8967 "ADC $dst.hi,$dst.hi\n\t"
8968 "ADD $dst.lo,$dst.lo\n\t"
8969 "ADC $dst.hi,$dst.hi" %}
8970 ins_encode %{
8971 __ addl($dst$$Register,$dst$$Register);
8972 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8973 __ addl($dst$$Register,$dst$$Register);
8974 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8975 %}
8976 ins_pipe( ialu_reg_long );
8977 %}
8978
8979 // Shift Left Long by 3
8980 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
8981 predicate(UseNewLongLShift);
8982 match(Set dst (LShiftL dst cnt));
8983 effect(KILL cr);
8984 ins_cost(100);
8985 format %{ "ADD $dst.lo,$dst.lo\n\t"
8986 "ADC $dst.hi,$dst.hi\n\t"
8987 "ADD $dst.lo,$dst.lo\n\t"
8988 "ADC $dst.hi,$dst.hi\n\t"
8989 "ADD $dst.lo,$dst.lo\n\t"
8990 "ADC $dst.hi,$dst.hi" %}
8991 ins_encode %{
8992 __ addl($dst$$Register,$dst$$Register);
8993 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8994 __ addl($dst$$Register,$dst$$Register);
8995 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8996 __ addl($dst$$Register,$dst$$Register);
8997 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8998 %}
8999 ins_pipe( ialu_reg_long );
9000 %}
9001
9002 // Shift Left Long by 1-31
9003 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9004 match(Set dst (LShiftL dst cnt));
9005 effect(KILL cr);
9006 ins_cost(200);
9007 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9008 "SHL $dst.lo,$cnt" %}
9009 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9010 ins_encode( move_long_small_shift(dst,cnt) );
9011 ins_pipe( ialu_reg_long );
9012 %}
9013
9014 // Shift Left Long by 32-63
9015 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9016 match(Set dst (LShiftL dst cnt));
9017 effect(KILL cr);
9018 ins_cost(300);
9019 format %{ "MOV $dst.hi,$dst.lo\n"
9020 "\tSHL $dst.hi,$cnt-32\n"
9021 "\tXOR $dst.lo,$dst.lo" %}
9022 opcode(0xC1, 0x4); /* C1 /4 ib */
9023 ins_encode( move_long_big_shift_clr(dst,cnt) );
9024 ins_pipe( ialu_reg_long );
9025 %}
9026
9027 // Shift Left Long by variable
9028 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9029 match(Set dst (LShiftL dst shift));
9030 effect(KILL cr);
9031 ins_cost(500+200);
9032 size(17);
9033 format %{ "TEST $shift,32\n\t"
9034 "JEQ,s small\n\t"
9035 "MOV $dst.hi,$dst.lo\n\t"
9036 "XOR $dst.lo,$dst.lo\n"
9037 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9038 "SHL $dst.lo,$shift" %}
9039 ins_encode( shift_left_long( dst, shift ) );
9040 ins_pipe( pipe_slow );
9041 %}
9042
9043 // Shift Right Long by 1-31
9044 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9045 match(Set dst (URShiftL dst cnt));
9046 effect(KILL cr);
9047 ins_cost(200);
9048 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9049 "SHR $dst.hi,$cnt" %}
9050 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9051 ins_encode( move_long_small_shift(dst,cnt) );
9052 ins_pipe( ialu_reg_long );
9053 %}
9054
9055 // Shift Right Long by 32-63
9056 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9057 match(Set dst (URShiftL dst cnt));
9058 effect(KILL cr);
9059 ins_cost(300);
9060 format %{ "MOV $dst.lo,$dst.hi\n"
9061 "\tSHR $dst.lo,$cnt-32\n"
9062 "\tXOR $dst.hi,$dst.hi" %}
9063 opcode(0xC1, 0x5); /* C1 /5 ib */
9064 ins_encode( move_long_big_shift_clr(dst,cnt) );
9065 ins_pipe( ialu_reg_long );
9066 %}
9067
9068 // Shift Right Long by variable
9069 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9070 match(Set dst (URShiftL dst shift));
9071 effect(KILL cr);
9072 ins_cost(600);
9073 size(17);
9074 format %{ "TEST $shift,32\n\t"
9075 "JEQ,s small\n\t"
9076 "MOV $dst.lo,$dst.hi\n\t"
9077 "XOR $dst.hi,$dst.hi\n"
9078 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9079 "SHR $dst.hi,$shift" %}
9080 ins_encode( shift_right_long( dst, shift ) );
9081 ins_pipe( pipe_slow );
9082 %}
9083
9084 // Shift Right Long by 1-31
9085 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9086 match(Set dst (RShiftL dst cnt));
9087 effect(KILL cr);
9088 ins_cost(200);
9089 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9090 "SAR $dst.hi,$cnt" %}
9091 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9092 ins_encode( move_long_small_shift(dst,cnt) );
9093 ins_pipe( ialu_reg_long );
9094 %}
9095
9096 // Shift Right Long by 32-63
9097 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9098 match(Set dst (RShiftL dst cnt));
9099 effect(KILL cr);
9100 ins_cost(300);
9101 format %{ "MOV $dst.lo,$dst.hi\n"
9102 "\tSAR $dst.lo,$cnt-32\n"
9103 "\tSAR $dst.hi,31" %}
9104 opcode(0xC1, 0x7); /* C1 /7 ib */
9105 ins_encode( move_long_big_shift_sign(dst,cnt) );
9106 ins_pipe( ialu_reg_long );
9107 %}
9108
9109 // Shift Right arithmetic Long by variable
9110 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9111 match(Set dst (RShiftL dst shift));
9112 effect(KILL cr);
9113 ins_cost(600);
9114 size(18);
9115 format %{ "TEST $shift,32\n\t"
9116 "JEQ,s small\n\t"
9117 "MOV $dst.lo,$dst.hi\n\t"
9118 "SAR $dst.hi,31\n"
9119 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9120 "SAR $dst.hi,$shift" %}
9121 ins_encode( shift_right_arith_long( dst, shift ) );
9122 ins_pipe( pipe_slow );
9123 %}
9124
9125
9126 //----------Double Instructions------------------------------------------------
9127 // Double Math
9128
9129 // Compare & branch
9130
9131 // P6 version of float compare, sets condition codes in EFLAGS
9132 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9133 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9134 match(Set cr (CmpD src1 src2));
9135 effect(KILL rax);
9136 ins_cost(150);
9137 format %{ "FLD $src1\n\t"
9138 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9139 "JNP exit\n\t"
9140 "MOV ah,1 // saw a NaN, set CF\n\t"
9141 "SAHF\n"
9142 "exit:\tNOP // avoid branch to branch" %}
9143 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9144 ins_encode( Push_Reg_DPR(src1),
9145 OpcP, RegOpc(src2),
9146 cmpF_P6_fixup );
9147 ins_pipe( pipe_slow );
9148 %}
9149
9150 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9151 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9152 match(Set cr (CmpD src1 src2));
9153 ins_cost(150);
9154 format %{ "FLD $src1\n\t"
9155 "FUCOMIP ST,$src2 // P6 instruction" %}
9156 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9157 ins_encode( Push_Reg_DPR(src1),
9158 OpcP, RegOpc(src2));
9159 ins_pipe( pipe_slow );
9160 %}
9161
9162 // Compare & branch
9163 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9164 predicate(UseSSE<=1);
9165 match(Set cr (CmpD src1 src2));
9166 effect(KILL rax);
9167 ins_cost(200);
9168 format %{ "FLD $src1\n\t"
9169 "FCOMp $src2\n\t"
9170 "FNSTSW AX\n\t"
9171 "TEST AX,0x400\n\t"
9172 "JZ,s flags\n\t"
9173 "MOV AH,1\t# unordered treat as LT\n"
9174 "flags:\tSAHF" %}
9175 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9176 ins_encode( Push_Reg_DPR(src1),
9177 OpcP, RegOpc(src2),
9178 fpu_flags);
9179 ins_pipe( pipe_slow );
9180 %}
9181
9182 // Compare vs zero into -1,0,1
9183 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9184 predicate(UseSSE<=1);
9185 match(Set dst (CmpD3 src1 zero));
9186 effect(KILL cr, KILL rax);
9187 ins_cost(280);
9188 format %{ "FTSTD $dst,$src1" %}
9189 opcode(0xE4, 0xD9);
9190 ins_encode( Push_Reg_DPR(src1),
9191 OpcS, OpcP, PopFPU,
9192 CmpF_Result(dst));
9193 ins_pipe( pipe_slow );
9194 %}
9195
9196 // Compare into -1,0,1
9197 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9198 predicate(UseSSE<=1);
9199 match(Set dst (CmpD3 src1 src2));
9200 effect(KILL cr, KILL rax);
9201 ins_cost(300);
9202 format %{ "FCMPD $dst,$src1,$src2" %}
9203 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9204 ins_encode( Push_Reg_DPR(src1),
9205 OpcP, RegOpc(src2),
9206 CmpF_Result(dst));
9207 ins_pipe( pipe_slow );
9208 %}
9209
9210 // float compare and set condition codes in EFLAGS by XMM regs
9211 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9212 predicate(UseSSE>=2);
9213 match(Set cr (CmpD src1 src2));
9214 ins_cost(145);
9215 format %{ "UCOMISD $src1,$src2\n\t"
9216 "JNP,s exit\n\t"
9217 "PUSHF\t# saw NaN, set CF\n\t"
9218 "AND [rsp], #0xffffff2b\n\t"
9219 "POPF\n"
9220 "exit:" %}
9221 ins_encode %{
9222 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9223 emit_cmpfp_fixup(_masm);
9224 %}
9225 ins_pipe( pipe_slow );
9226 %}
9227
9228 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9229 predicate(UseSSE>=2);
9230 match(Set cr (CmpD src1 src2));
9231 ins_cost(100);
9232 format %{ "UCOMISD $src1,$src2" %}
9233 ins_encode %{
9234 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9235 %}
9236 ins_pipe( pipe_slow );
9237 %}
9238
9239 // float compare and set condition codes in EFLAGS by XMM regs
9240 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9241 predicate(UseSSE>=2);
9242 match(Set cr (CmpD src1 (LoadD src2)));
9243 ins_cost(145);
9244 format %{ "UCOMISD $src1,$src2\n\t"
9245 "JNP,s exit\n\t"
9246 "PUSHF\t# saw NaN, set CF\n\t"
9247 "AND [rsp], #0xffffff2b\n\t"
9248 "POPF\n"
9249 "exit:" %}
9250 ins_encode %{
9251 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9252 emit_cmpfp_fixup(_masm);
9253 %}
9254 ins_pipe( pipe_slow );
9255 %}
9256
9257 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9258 predicate(UseSSE>=2);
9259 match(Set cr (CmpD src1 (LoadD src2)));
9260 ins_cost(100);
9261 format %{ "UCOMISD $src1,$src2" %}
9262 ins_encode %{
9263 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9264 %}
9265 ins_pipe( pipe_slow );
9266 %}
9267
9268 // Compare into -1,0,1 in XMM
9269 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9270 predicate(UseSSE>=2);
9271 match(Set dst (CmpD3 src1 src2));
9272 effect(KILL cr);
9273 ins_cost(255);
9274 format %{ "UCOMISD $src1, $src2\n\t"
9275 "MOV $dst, #-1\n\t"
9276 "JP,s done\n\t"
9277 "JB,s done\n\t"
9278 "SETNE $dst\n\t"
9279 "MOVZB $dst, $dst\n"
9280 "done:" %}
9281 ins_encode %{
9282 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9283 emit_cmpfp3(_masm, $dst$$Register);
9284 %}
9285 ins_pipe( pipe_slow );
9286 %}
9287
9288 // Compare into -1,0,1 in XMM and memory
9289 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9290 predicate(UseSSE>=2);
9291 match(Set dst (CmpD3 src1 (LoadD src2)));
9292 effect(KILL cr);
9293 ins_cost(275);
9294 format %{ "UCOMISD $src1, $src2\n\t"
9295 "MOV $dst, #-1\n\t"
9296 "JP,s done\n\t"
9297 "JB,s done\n\t"
9298 "SETNE $dst\n\t"
9299 "MOVZB $dst, $dst\n"
9300 "done:" %}
9301 ins_encode %{
9302 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9303 emit_cmpfp3(_masm, $dst$$Register);
9304 %}
9305 ins_pipe( pipe_slow );
9306 %}
9307
9308
9309 instruct subDPR_reg(regDPR dst, regDPR src) %{
9310 predicate (UseSSE <=1);
9311 match(Set dst (SubD dst src));
9312
9313 format %{ "FLD $src\n\t"
9314 "DSUBp $dst,ST" %}
9315 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9316 ins_cost(150);
9317 ins_encode( Push_Reg_DPR(src),
9318 OpcP, RegOpc(dst) );
9319 ins_pipe( fpu_reg_reg );
9320 %}
9321
9322 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9323 predicate (UseSSE <=1);
9324 match(Set dst (RoundDouble (SubD src1 src2)));
9325 ins_cost(250);
9326
9327 format %{ "FLD $src2\n\t"
9328 "DSUB ST,$src1\n\t"
9329 "FSTP_D $dst\t# D-round" %}
9330 opcode(0xD8, 0x5);
9331 ins_encode( Push_Reg_DPR(src2),
9332 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9333 ins_pipe( fpu_mem_reg_reg );
9334 %}
9335
9336
9337 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9338 predicate (UseSSE <=1);
9339 match(Set dst (SubD dst (LoadD src)));
9340 ins_cost(150);
9341
9342 format %{ "FLD $src\n\t"
9343 "DSUBp $dst,ST" %}
9344 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9345 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9346 OpcP, RegOpc(dst) );
9347 ins_pipe( fpu_reg_mem );
9348 %}
9349
9350 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9351 predicate (UseSSE<=1);
9352 match(Set dst (AbsD src));
9353 ins_cost(100);
9354 format %{ "FABS" %}
9355 opcode(0xE1, 0xD9);
9356 ins_encode( OpcS, OpcP );
9357 ins_pipe( fpu_reg_reg );
9358 %}
9359
9360 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9361 predicate(UseSSE<=1);
9362 match(Set dst (NegD src));
9363 ins_cost(100);
9364 format %{ "FCHS" %}
9365 opcode(0xE0, 0xD9);
9366 ins_encode( OpcS, OpcP );
9367 ins_pipe( fpu_reg_reg );
9368 %}
9369
9370 instruct addDPR_reg(regDPR dst, regDPR src) %{
9371 predicate(UseSSE<=1);
9372 match(Set dst (AddD dst src));
9373 format %{ "FLD $src\n\t"
9374 "DADD $dst,ST" %}
9375 size(4);
9376 ins_cost(150);
9377 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9378 ins_encode( Push_Reg_DPR(src),
9379 OpcP, RegOpc(dst) );
9380 ins_pipe( fpu_reg_reg );
9381 %}
9382
9383
9384 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9385 predicate(UseSSE<=1);
9386 match(Set dst (RoundDouble (AddD src1 src2)));
9387 ins_cost(250);
9388
9389 format %{ "FLD $src2\n\t"
9390 "DADD ST,$src1\n\t"
9391 "FSTP_D $dst\t# D-round" %}
9392 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9393 ins_encode( Push_Reg_DPR(src2),
9394 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9395 ins_pipe( fpu_mem_reg_reg );
9396 %}
9397
9398
9399 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9400 predicate(UseSSE<=1);
9401 match(Set dst (AddD dst (LoadD src)));
9402 ins_cost(150);
9403
9404 format %{ "FLD $src\n\t"
9405 "DADDp $dst,ST" %}
9406 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9407 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9408 OpcP, RegOpc(dst) );
9409 ins_pipe( fpu_reg_mem );
9410 %}
9411
9412 // add-to-memory
9413 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9414 predicate(UseSSE<=1);
9415 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9416 ins_cost(150);
9417
9418 format %{ "FLD_D $dst\n\t"
9419 "DADD ST,$src\n\t"
9420 "FST_D $dst" %}
9421 opcode(0xDD, 0x0);
9422 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9423 Opcode(0xD8), RegOpc(src),
9424 set_instruction_start,
9425 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9426 ins_pipe( fpu_reg_mem );
9427 %}
9428
9429 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9430 predicate(UseSSE<=1);
9431 match(Set dst (AddD dst con));
9432 ins_cost(125);
9433 format %{ "FLD1\n\t"
9434 "DADDp $dst,ST" %}
9435 ins_encode %{
9436 __ fld1();
9437 __ faddp($dst$$reg);
9438 %}
9439 ins_pipe(fpu_reg);
9440 %}
9441
9442 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9443 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9444 match(Set dst (AddD dst con));
9445 ins_cost(200);
9446 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9447 "DADDp $dst,ST" %}
9448 ins_encode %{
9449 __ fld_d($constantaddress($con));
9450 __ faddp($dst$$reg);
9451 %}
9452 ins_pipe(fpu_reg_mem);
9453 %}
9454
9455 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9456 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9457 match(Set dst (RoundDouble (AddD src con)));
9458 ins_cost(200);
9459 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9460 "DADD ST,$src\n\t"
9461 "FSTP_D $dst\t# D-round" %}
9462 ins_encode %{
9463 __ fld_d($constantaddress($con));
9464 __ fadd($src$$reg);
9465 __ fstp_d(Address(rsp, $dst$$disp));
9466 %}
9467 ins_pipe(fpu_mem_reg_con);
9468 %}
9469
9470 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9471 predicate(UseSSE<=1);
9472 match(Set dst (MulD dst src));
9473 format %{ "FLD $src\n\t"
9474 "DMULp $dst,ST" %}
9475 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9476 ins_cost(150);
9477 ins_encode( Push_Reg_DPR(src),
9478 OpcP, RegOpc(dst) );
9479 ins_pipe( fpu_reg_reg );
9480 %}
9481
9482 // Strict FP instruction biases argument before multiply then
9483 // biases result to avoid double rounding of subnormals.
9484 //
9485 // scale arg1 by multiplying arg1 by 2^(-15360)
9486 // load arg2
9487 // multiply scaled arg1 by arg2
9488 // rescale product by 2^(15360)
9489 //
9490 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9491 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9492 match(Set dst (MulD dst src));
9493 ins_cost(1); // Select this instruction for all strict FP double multiplies
9494
9495 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9496 "DMULp $dst,ST\n\t"
9497 "FLD $src\n\t"
9498 "DMULp $dst,ST\n\t"
9499 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9500 "DMULp $dst,ST\n\t" %}
9501 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9502 ins_encode( strictfp_bias1(dst),
9503 Push_Reg_DPR(src),
9504 OpcP, RegOpc(dst),
9505 strictfp_bias2(dst) );
9506 ins_pipe( fpu_reg_reg );
9507 %}
9508
9509 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9510 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9511 match(Set dst (MulD dst con));
9512 ins_cost(200);
9513 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9514 "DMULp $dst,ST" %}
9515 ins_encode %{
9516 __ fld_d($constantaddress($con));
9517 __ fmulp($dst$$reg);
9518 %}
9519 ins_pipe(fpu_reg_mem);
9520 %}
9521
9522
9523 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9524 predicate( UseSSE<=1 );
9525 match(Set dst (MulD dst (LoadD src)));
9526 ins_cost(200);
9527 format %{ "FLD_D $src\n\t"
9528 "DMULp $dst,ST" %}
9529 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9530 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9531 OpcP, RegOpc(dst) );
9532 ins_pipe( fpu_reg_mem );
9533 %}
9534
9535 //
9536 // Cisc-alternate to reg-reg multiply
9537 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9538 predicate( UseSSE<=1 );
9539 match(Set dst (MulD src (LoadD mem)));
9540 ins_cost(250);
9541 format %{ "FLD_D $mem\n\t"
9542 "DMUL ST,$src\n\t"
9543 "FSTP_D $dst" %}
9544 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9545 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9546 OpcReg_FPR(src),
9547 Pop_Reg_DPR(dst) );
9548 ins_pipe( fpu_reg_reg_mem );
9549 %}
9550
9551
9552 // MACRO3 -- addDPR a mulDPR
9553 // This instruction is a '2-address' instruction in that the result goes
9554 // back to src2. This eliminates a move from the macro; possibly the
9555 // register allocator will have to add it back (and maybe not).
9556 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9557 predicate( UseSSE<=1 );
9558 match(Set src2 (AddD (MulD src0 src1) src2));
9559 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9560 "DMUL ST,$src1\n\t"
9561 "DADDp $src2,ST" %}
9562 ins_cost(250);
9563 opcode(0xDD); /* LoadD DD /0 */
9564 ins_encode( Push_Reg_FPR(src0),
9565 FMul_ST_reg(src1),
9566 FAddP_reg_ST(src2) );
9567 ins_pipe( fpu_reg_reg_reg );
9568 %}
9569
9570
9571 // MACRO3 -- subDPR a mulDPR
9572 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9573 predicate( UseSSE<=1 );
9574 match(Set src2 (SubD (MulD src0 src1) src2));
9575 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9576 "DMUL ST,$src1\n\t"
9577 "DSUBRp $src2,ST" %}
9578 ins_cost(250);
9579 ins_encode( Push_Reg_FPR(src0),
9580 FMul_ST_reg(src1),
9581 Opcode(0xDE), Opc_plus(0xE0,src2));
9582 ins_pipe( fpu_reg_reg_reg );
9583 %}
9584
9585
9586 instruct divDPR_reg(regDPR dst, regDPR src) %{
9587 predicate( UseSSE<=1 );
9588 match(Set dst (DivD dst src));
9589
9590 format %{ "FLD $src\n\t"
9591 "FDIVp $dst,ST" %}
9592 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9593 ins_cost(150);
9594 ins_encode( Push_Reg_DPR(src),
9595 OpcP, RegOpc(dst) );
9596 ins_pipe( fpu_reg_reg );
9597 %}
9598
9599 // Strict FP instruction biases argument before division then
9600 // biases result, to avoid double rounding of subnormals.
9601 //
9602 // scale dividend by multiplying dividend by 2^(-15360)
9603 // load divisor
9604 // divide scaled dividend by divisor
9605 // rescale quotient by 2^(15360)
9606 //
9607 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9608 predicate (UseSSE<=1);
9609 match(Set dst (DivD dst src));
9610 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9611 ins_cost(01);
9612
9613 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9614 "DMULp $dst,ST\n\t"
9615 "FLD $src\n\t"
9616 "FDIVp $dst,ST\n\t"
9617 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9618 "DMULp $dst,ST\n\t" %}
9619 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9620 ins_encode( strictfp_bias1(dst),
9621 Push_Reg_DPR(src),
9622 OpcP, RegOpc(dst),
9623 strictfp_bias2(dst) );
9624 ins_pipe( fpu_reg_reg );
9625 %}
9626
9627 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9628 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9629 match(Set dst (RoundDouble (DivD src1 src2)));
9630
9631 format %{ "FLD $src1\n\t"
9632 "FDIV ST,$src2\n\t"
9633 "FSTP_D $dst\t# D-round" %}
9634 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9635 ins_encode( Push_Reg_DPR(src1),
9636 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9637 ins_pipe( fpu_mem_reg_reg );
9638 %}
9639
9640
9641 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9642 predicate(UseSSE<=1);
9643 match(Set dst (ModD dst src));
9644 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9645
9646 format %{ "DMOD $dst,$src" %}
9647 ins_cost(250);
9648 ins_encode(Push_Reg_Mod_DPR(dst, src),
9649 emitModDPR(),
9650 Push_Result_Mod_DPR(src),
9651 Pop_Reg_DPR(dst));
9652 ins_pipe( pipe_slow );
9653 %}
9654
9655 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9656 predicate(UseSSE>=2);
9657 match(Set dst (ModD src0 src1));
9658 effect(KILL rax, KILL cr);
9659
9660 format %{ "SUB ESP,8\t # DMOD\n"
9661 "\tMOVSD [ESP+0],$src1\n"
9662 "\tFLD_D [ESP+0]\n"
9663 "\tMOVSD [ESP+0],$src0\n"
9664 "\tFLD_D [ESP+0]\n"
9665 "loop:\tFPREM\n"
9666 "\tFWAIT\n"
9667 "\tFNSTSW AX\n"
9668 "\tSAHF\n"
9669 "\tJP loop\n"
9670 "\tFSTP_D [ESP+0]\n"
9671 "\tMOVSD $dst,[ESP+0]\n"
9672 "\tADD ESP,8\n"
9673 "\tFSTP ST0\t # Restore FPU Stack"
9674 %}
9675 ins_cost(250);
9676 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9677 ins_pipe( pipe_slow );
9678 %}
9679
9680 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9681 predicate (UseSSE<=1);
9682 match(Set dst (SinD src));
9683 ins_cost(1800);
9684 format %{ "DSIN $dst" %}
9685 opcode(0xD9, 0xFE);
9686 ins_encode( OpcP, OpcS );
9687 ins_pipe( pipe_slow );
9688 %}
9689
9690 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9691 predicate (UseSSE>=2);
9692 match(Set dst (SinD dst));
9693 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9694 ins_cost(1800);
9695 format %{ "DSIN $dst" %}
9696 opcode(0xD9, 0xFE);
9697 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9698 ins_pipe( pipe_slow );
9699 %}
9700
9701 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9702 predicate (UseSSE<=1);
9703 match(Set dst (CosD src));
9704 ins_cost(1800);
9705 format %{ "DCOS $dst" %}
9706 opcode(0xD9, 0xFF);
9707 ins_encode( OpcP, OpcS );
9708 ins_pipe( pipe_slow );
9709 %}
9710
9711 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9712 predicate (UseSSE>=2);
9713 match(Set dst (CosD dst));
9714 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9715 ins_cost(1800);
9716 format %{ "DCOS $dst" %}
9717 opcode(0xD9, 0xFF);
9718 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9719 ins_pipe( pipe_slow );
9720 %}
9721
9722 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9723 predicate (UseSSE<=1);
9724 match(Set dst(TanD src));
9725 format %{ "DTAN $dst" %}
9726 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9727 Opcode(0xDD), Opcode(0xD8)); // fstp st
9728 ins_pipe( pipe_slow );
9729 %}
9730
9731 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9732 predicate (UseSSE>=2);
9733 match(Set dst(TanD dst));
9734 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9735 format %{ "DTAN $dst" %}
9736 ins_encode( Push_SrcD(dst),
9737 Opcode(0xD9), Opcode(0xF2), // fptan
9738 Opcode(0xDD), Opcode(0xD8), // fstp st
9739 Push_ResultD(dst) );
9740 ins_pipe( pipe_slow );
9741 %}
9742
9743 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9744 predicate (UseSSE<=1);
9745 match(Set dst(AtanD dst src));
9746 format %{ "DATA $dst,$src" %}
9747 opcode(0xD9, 0xF3);
9748 ins_encode( Push_Reg_DPR(src),
9749 OpcP, OpcS, RegOpc(dst) );
9750 ins_pipe( pipe_slow );
9751 %}
9752
9753 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9754 predicate (UseSSE>=2);
9755 match(Set dst(AtanD dst src));
9756 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9757 format %{ "DATA $dst,$src" %}
9758 opcode(0xD9, 0xF3);
9759 ins_encode( Push_SrcD(src),
9760 OpcP, OpcS, Push_ResultD(dst) );
9761 ins_pipe( pipe_slow );
9762 %}
9763
9764 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9765 predicate (UseSSE<=1);
9766 match(Set dst (SqrtD src));
9767 format %{ "DSQRT $dst,$src" %}
9768 opcode(0xFA, 0xD9);
9769 ins_encode( Push_Reg_DPR(src),
9770 OpcS, OpcP, Pop_Reg_DPR(dst) );
9771 ins_pipe( pipe_slow );
9772 %}
9773
9774 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9775 predicate (UseSSE<=1);
9776 match(Set Y (PowD X Y)); // Raise X to the Yth power
9777 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9778 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
9779 ins_encode %{
9780 __ subptr(rsp, 8);
9781 __ fld_s($X$$reg - 1);
9782 __ fast_pow();
9783 __ addptr(rsp, 8);
9784 %}
9785 ins_pipe( pipe_slow );
9786 %}
9787
9788 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9789 predicate (UseSSE>=2);
9790 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9791 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9792 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9793 ins_encode %{
9794 __ subptr(rsp, 8);
9795 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9796 __ fld_d(Address(rsp, 0));
9797 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9798 __ fld_d(Address(rsp, 0));
9799 __ fast_pow();
9800 __ fstp_d(Address(rsp, 0));
9801 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9802 __ addptr(rsp, 8);
9803 %}
9804 ins_pipe( pipe_slow );
9805 %}
9806
9807
9808 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9809 predicate (UseSSE<=1);
9810 match(Set dpr1 (ExpD dpr1));
9811 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9812 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
9813 ins_encode %{
9814 __ fast_exp();
9815 %}
9816 ins_pipe( pipe_slow );
9817 %}
9818
9819 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9820 predicate (UseSSE>=2);
9821 match(Set dst (ExpD src));
9822 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9823 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9824 ins_encode %{
9825 __ subptr(rsp, 8);
9826 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9827 __ fld_d(Address(rsp, 0));
9828 __ fast_exp();
9829 __ fstp_d(Address(rsp, 0));
9830 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9831 __ addptr(rsp, 8);
9832 %}
9833 ins_pipe( pipe_slow );
9834 %}
9835
9836 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
9837 predicate (UseSSE<=1);
9838 // The source Double operand on FPU stack
9839 match(Set dst (Log10D src));
9840 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9841 // fxch ; swap ST(0) with ST(1)
9842 // fyl2x ; compute log_10(2) * log_2(x)
9843 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9844 "FXCH \n\t"
9845 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9846 %}
9847 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9848 Opcode(0xD9), Opcode(0xC9), // fxch
9849 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9850
9851 ins_pipe( pipe_slow );
9852 %}
9853
9854 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
9855 predicate (UseSSE>=2);
9856 effect(KILL cr);
9857 match(Set dst (Log10D src));
9858 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9859 // fyl2x ; compute log_10(2) * log_2(x)
9860 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9861 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9862 %}
9863 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9864 Push_SrcD(src),
9865 Opcode(0xD9), Opcode(0xF1), // fyl2x
9866 Push_ResultD(dst));
9867
9868 ins_pipe( pipe_slow );
9869 %}
9870
9871 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
9872 predicate (UseSSE<=1);
9873 // The source Double operand on FPU stack
9874 match(Set dst (LogD src));
9875 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9876 // fxch ; swap ST(0) with ST(1)
9877 // fyl2x ; compute log_e(2) * log_2(x)
9878 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
9879 "FXCH \n\t"
9880 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
9881 %}
9882 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9883 Opcode(0xD9), Opcode(0xC9), // fxch
9884 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9885
9886 ins_pipe( pipe_slow );
9887 %}
9888
9889 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
9890 predicate (UseSSE>=2);
9891 effect(KILL cr);
9892 // The source and result Double operands in XMM registers
9893 match(Set dst (LogD src));
9894 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9895 // fyl2x ; compute log_e(2) * log_2(x)
9896 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
9897 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
9898 %}
9899 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9900 Push_SrcD(src),
9901 Opcode(0xD9), Opcode(0xF1), // fyl2x
9902 Push_ResultD(dst));
9903 ins_pipe( pipe_slow );
9904 %}
9905
9906 //-------------Float Instructions-------------------------------
9907 // Float Math
9908
9909 // Code for float compare:
9910 // fcompp();
9911 // fwait(); fnstsw_ax();
9912 // sahf();
9913 // movl(dst, unordered_result);
9914 // jcc(Assembler::parity, exit);
9915 // movl(dst, less_result);
9916 // jcc(Assembler::below, exit);
9917 // movl(dst, equal_result);
9918 // jcc(Assembler::equal, exit);
9919 // movl(dst, greater_result);
9920 // exit:
9921
9922 // P6 version of float compare, sets condition codes in EFLAGS
9923 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
9924 predicate(VM_Version::supports_cmov() && UseSSE == 0);
9925 match(Set cr (CmpF src1 src2));
9926 effect(KILL rax);
9927 ins_cost(150);
9928 format %{ "FLD $src1\n\t"
9929 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9930 "JNP exit\n\t"
9931 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
9932 "SAHF\n"
9933 "exit:\tNOP // avoid branch to branch" %}
9934 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9935 ins_encode( Push_Reg_DPR(src1),
9936 OpcP, RegOpc(src2),
9937 cmpF_P6_fixup );
9938 ins_pipe( pipe_slow );
9939 %}
9940
9941 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
9942 predicate(VM_Version::supports_cmov() && UseSSE == 0);
9943 match(Set cr (CmpF src1 src2));
9944 ins_cost(100);
9945 format %{ "FLD $src1\n\t"
9946 "FUCOMIP ST,$src2 // P6 instruction" %}
9947 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9948 ins_encode( Push_Reg_DPR(src1),
9949 OpcP, RegOpc(src2));
9950 ins_pipe( pipe_slow );
9951 %}
9952
9953
9954 // Compare & branch
9955 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
9956 predicate(UseSSE == 0);
9957 match(Set cr (CmpF src1 src2));
9958 effect(KILL rax);
9959 ins_cost(200);
9960 format %{ "FLD $src1\n\t"
9961 "FCOMp $src2\n\t"
9962 "FNSTSW AX\n\t"
9963 "TEST AX,0x400\n\t"
9964 "JZ,s flags\n\t"
9965 "MOV AH,1\t# unordered treat as LT\n"
9966 "flags:\tSAHF" %}
9967 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9968 ins_encode( Push_Reg_DPR(src1),
9969 OpcP, RegOpc(src2),
9970 fpu_flags);
9971 ins_pipe( pipe_slow );
9972 %}
9973
9974 // Compare vs zero into -1,0,1
9975 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9976 predicate(UseSSE == 0);
9977 match(Set dst (CmpF3 src1 zero));
9978 effect(KILL cr, KILL rax);
9979 ins_cost(280);
9980 format %{ "FTSTF $dst,$src1" %}
9981 opcode(0xE4, 0xD9);
9982 ins_encode( Push_Reg_DPR(src1),
9983 OpcS, OpcP, PopFPU,
9984 CmpF_Result(dst));
9985 ins_pipe( pipe_slow );
9986 %}
9987
9988 // Compare into -1,0,1
9989 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
9990 predicate(UseSSE == 0);
9991 match(Set dst (CmpF3 src1 src2));
9992 effect(KILL cr, KILL rax);
9993 ins_cost(300);
9994 format %{ "FCMPF $dst,$src1,$src2" %}
9995 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9996 ins_encode( Push_Reg_DPR(src1),
9997 OpcP, RegOpc(src2),
9998 CmpF_Result(dst));
9999 ins_pipe( pipe_slow );
10000 %}
10001
10002 // float compare and set condition codes in EFLAGS by XMM regs
10003 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10004 predicate(UseSSE>=1);
10005 match(Set cr (CmpF src1 src2));
10006 ins_cost(145);
10007 format %{ "UCOMISS $src1,$src2\n\t"
10008 "JNP,s exit\n\t"
10009 "PUSHF\t# saw NaN, set CF\n\t"
10010 "AND [rsp], #0xffffff2b\n\t"
10011 "POPF\n"
10012 "exit:" %}
10013 ins_encode %{
10014 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10015 emit_cmpfp_fixup(_masm);
10016 %}
10017 ins_pipe( pipe_slow );
10018 %}
10019
10020 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10021 predicate(UseSSE>=1);
10022 match(Set cr (CmpF src1 src2));
10023 ins_cost(100);
10024 format %{ "UCOMISS $src1,$src2" %}
10025 ins_encode %{
10026 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10027 %}
10028 ins_pipe( pipe_slow );
10029 %}
10030
10031 // float compare and set condition codes in EFLAGS by XMM regs
10032 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10033 predicate(UseSSE>=1);
10034 match(Set cr (CmpF src1 (LoadF src2)));
10035 ins_cost(165);
10036 format %{ "UCOMISS $src1,$src2\n\t"
10037 "JNP,s exit\n\t"
10038 "PUSHF\t# saw NaN, set CF\n\t"
10039 "AND [rsp], #0xffffff2b\n\t"
10040 "POPF\n"
10041 "exit:" %}
10042 ins_encode %{
10043 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10044 emit_cmpfp_fixup(_masm);
10045 %}
10046 ins_pipe( pipe_slow );
10047 %}
10048
10049 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10050 predicate(UseSSE>=1);
10051 match(Set cr (CmpF src1 (LoadF src2)));
10052 ins_cost(100);
10053 format %{ "UCOMISS $src1,$src2" %}
10054 ins_encode %{
10055 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10056 %}
10057 ins_pipe( pipe_slow );
10058 %}
10059
10060 // Compare into -1,0,1 in XMM
10061 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10062 predicate(UseSSE>=1);
10063 match(Set dst (CmpF3 src1 src2));
10064 effect(KILL cr);
10065 ins_cost(255);
10066 format %{ "UCOMISS $src1, $src2\n\t"
10067 "MOV $dst, #-1\n\t"
10068 "JP,s done\n\t"
10069 "JB,s done\n\t"
10070 "SETNE $dst\n\t"
10071 "MOVZB $dst, $dst\n"
10072 "done:" %}
10073 ins_encode %{
10074 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10075 emit_cmpfp3(_masm, $dst$$Register);
10076 %}
10077 ins_pipe( pipe_slow );
10078 %}
10079
10080 // Compare into -1,0,1 in XMM and memory
10081 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10082 predicate(UseSSE>=1);
10083 match(Set dst (CmpF3 src1 (LoadF src2)));
10084 effect(KILL cr);
10085 ins_cost(275);
10086 format %{ "UCOMISS $src1, $src2\n\t"
10087 "MOV $dst, #-1\n\t"
10088 "JP,s done\n\t"
10089 "JB,s done\n\t"
10090 "SETNE $dst\n\t"
10091 "MOVZB $dst, $dst\n"
10092 "done:" %}
10093 ins_encode %{
10094 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10095 emit_cmpfp3(_masm, $dst$$Register);
10096 %}
10097 ins_pipe( pipe_slow );
10098 %}
10099
10100 // Spill to obtain 24-bit precision
10101 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10102 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10103 match(Set dst (SubF src1 src2));
10104
10105 format %{ "FSUB $dst,$src1 - $src2" %}
10106 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10107 ins_encode( Push_Reg_FPR(src1),
10108 OpcReg_FPR(src2),
10109 Pop_Mem_FPR(dst) );
10110 ins_pipe( fpu_mem_reg_reg );
10111 %}
10112 //
10113 // This instruction does not round to 24-bits
10114 instruct subFPR_reg(regFPR dst, regFPR src) %{
10115 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10116 match(Set dst (SubF dst src));
10117
10118 format %{ "FSUB $dst,$src" %}
10119 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10120 ins_encode( Push_Reg_FPR(src),
10121 OpcP, RegOpc(dst) );
10122 ins_pipe( fpu_reg_reg );
10123 %}
10124
10125 // Spill to obtain 24-bit precision
10126 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10127 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10128 match(Set dst (AddF src1 src2));
10129
10130 format %{ "FADD $dst,$src1,$src2" %}
10131 opcode(0xD8, 0x0); /* D8 C0+i */
10132 ins_encode( Push_Reg_FPR(src2),
10133 OpcReg_FPR(src1),
10134 Pop_Mem_FPR(dst) );
10135 ins_pipe( fpu_mem_reg_reg );
10136 %}
10137 //
10138 // This instruction does not round to 24-bits
10139 instruct addFPR_reg(regFPR dst, regFPR src) %{
10140 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10141 match(Set dst (AddF dst src));
10142
10143 format %{ "FLD $src\n\t"
10144 "FADDp $dst,ST" %}
10145 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10146 ins_encode( Push_Reg_FPR(src),
10147 OpcP, RegOpc(dst) );
10148 ins_pipe( fpu_reg_reg );
10149 %}
10150
10151 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10152 predicate(UseSSE==0);
10153 match(Set dst (AbsF src));
10154 ins_cost(100);
10155 format %{ "FABS" %}
10156 opcode(0xE1, 0xD9);
10157 ins_encode( OpcS, OpcP );
10158 ins_pipe( fpu_reg_reg );
10159 %}
10160
10161 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10162 predicate(UseSSE==0);
10163 match(Set dst (NegF src));
10164 ins_cost(100);
10165 format %{ "FCHS" %}
10166 opcode(0xE0, 0xD9);
10167 ins_encode( OpcS, OpcP );
10168 ins_pipe( fpu_reg_reg );
10169 %}
10170
10171 // Cisc-alternate to addFPR_reg
10172 // Spill to obtain 24-bit precision
10173 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10174 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10175 match(Set dst (AddF src1 (LoadF src2)));
10176
10177 format %{ "FLD $src2\n\t"
10178 "FADD ST,$src1\n\t"
10179 "FSTP_S $dst" %}
10180 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10181 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10182 OpcReg_FPR(src1),
10183 Pop_Mem_FPR(dst) );
10184 ins_pipe( fpu_mem_reg_mem );
10185 %}
10186 //
10187 // Cisc-alternate to addFPR_reg
10188 // This instruction does not round to 24-bits
10189 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10190 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10191 match(Set dst (AddF dst (LoadF src)));
10192
10193 format %{ "FADD $dst,$src" %}
10194 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10195 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10196 OpcP, RegOpc(dst) );
10197 ins_pipe( fpu_reg_mem );
10198 %}
10199
10200 // // Following two instructions for _222_mpegaudio
10201 // Spill to obtain 24-bit precision
10202 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10203 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10204 match(Set dst (AddF src1 src2));
10205
10206 format %{ "FADD $dst,$src1,$src2" %}
10207 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10208 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10209 OpcReg_FPR(src2),
10210 Pop_Mem_FPR(dst) );
10211 ins_pipe( fpu_mem_reg_mem );
10212 %}
10213
10214 // Cisc-spill variant
10215 // Spill to obtain 24-bit precision
10216 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10217 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10218 match(Set dst (AddF src1 (LoadF src2)));
10219
10220 format %{ "FADD $dst,$src1,$src2 cisc" %}
10221 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10222 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10223 set_instruction_start,
10224 OpcP, RMopc_Mem(secondary,src1),
10225 Pop_Mem_FPR(dst) );
10226 ins_pipe( fpu_mem_mem_mem );
10227 %}
10228
10229 // Spill to obtain 24-bit precision
10230 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10231 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10232 match(Set dst (AddF src1 src2));
10233
10234 format %{ "FADD $dst,$src1,$src2" %}
10235 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10236 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10237 set_instruction_start,
10238 OpcP, RMopc_Mem(secondary,src1),
10239 Pop_Mem_FPR(dst) );
10240 ins_pipe( fpu_mem_mem_mem );
10241 %}
10242
10243
10244 // Spill to obtain 24-bit precision
10245 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10246 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10247 match(Set dst (AddF src con));
10248 format %{ "FLD $src\n\t"
10249 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10250 "FSTP_S $dst" %}
10251 ins_encode %{
10252 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10253 __ fadd_s($constantaddress($con));
10254 __ fstp_s(Address(rsp, $dst$$disp));
10255 %}
10256 ins_pipe(fpu_mem_reg_con);
10257 %}
10258 //
10259 // This instruction does not round to 24-bits
10260 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10261 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10262 match(Set dst (AddF src con));
10263 format %{ "FLD $src\n\t"
10264 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10265 "FSTP $dst" %}
10266 ins_encode %{
10267 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10268 __ fadd_s($constantaddress($con));
10269 __ fstp_d($dst$$reg);
10270 %}
10271 ins_pipe(fpu_reg_reg_con);
10272 %}
10273
10274 // Spill to obtain 24-bit precision
10275 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10276 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10277 match(Set dst (MulF src1 src2));
10278
10279 format %{ "FLD $src1\n\t"
10280 "FMUL $src2\n\t"
10281 "FSTP_S $dst" %}
10282 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10283 ins_encode( Push_Reg_FPR(src1),
10284 OpcReg_FPR(src2),
10285 Pop_Mem_FPR(dst) );
10286 ins_pipe( fpu_mem_reg_reg );
10287 %}
10288 //
10289 // This instruction does not round to 24-bits
10290 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10291 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10292 match(Set dst (MulF src1 src2));
10293
10294 format %{ "FLD $src1\n\t"
10295 "FMUL $src2\n\t"
10296 "FSTP_S $dst" %}
10297 opcode(0xD8, 0x1); /* D8 C8+i */
10298 ins_encode( Push_Reg_FPR(src2),
10299 OpcReg_FPR(src1),
10300 Pop_Reg_FPR(dst) );
10301 ins_pipe( fpu_reg_reg_reg );
10302 %}
10303
10304
10305 // Spill to obtain 24-bit precision
10306 // Cisc-alternate to reg-reg multiply
10307 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10308 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10309 match(Set dst (MulF src1 (LoadF src2)));
10310
10311 format %{ "FLD_S $src2\n\t"
10312 "FMUL $src1\n\t"
10313 "FSTP_S $dst" %}
10314 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10315 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10316 OpcReg_FPR(src1),
10317 Pop_Mem_FPR(dst) );
10318 ins_pipe( fpu_mem_reg_mem );
10319 %}
10320 //
10321 // This instruction does not round to 24-bits
10322 // Cisc-alternate to reg-reg multiply
10323 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10324 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10325 match(Set dst (MulF src1 (LoadF src2)));
10326
10327 format %{ "FMUL $dst,$src1,$src2" %}
10328 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10329 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10330 OpcReg_FPR(src1),
10331 Pop_Reg_FPR(dst) );
10332 ins_pipe( fpu_reg_reg_mem );
10333 %}
10334
10335 // Spill to obtain 24-bit precision
10336 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10337 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10338 match(Set dst (MulF src1 src2));
10339
10340 format %{ "FMUL $dst,$src1,$src2" %}
10341 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10342 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10343 set_instruction_start,
10344 OpcP, RMopc_Mem(secondary,src1),
10345 Pop_Mem_FPR(dst) );
10346 ins_pipe( fpu_mem_mem_mem );
10347 %}
10348
10349 // Spill to obtain 24-bit precision
10350 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10351 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10352 match(Set dst (MulF src con));
10353
10354 format %{ "FLD $src\n\t"
10355 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10356 "FSTP_S $dst" %}
10357 ins_encode %{
10358 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10359 __ fmul_s($constantaddress($con));
10360 __ fstp_s(Address(rsp, $dst$$disp));
10361 %}
10362 ins_pipe(fpu_mem_reg_con);
10363 %}
10364 //
10365 // This instruction does not round to 24-bits
10366 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10367 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10368 match(Set dst (MulF src con));
10369
10370 format %{ "FLD $src\n\t"
10371 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10372 "FSTP $dst" %}
10373 ins_encode %{
10374 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10375 __ fmul_s($constantaddress($con));
10376 __ fstp_d($dst$$reg);
10377 %}
10378 ins_pipe(fpu_reg_reg_con);
10379 %}
10380
10381
10382 //
10383 // MACRO1 -- subsume unshared load into mulFPR
10384 // This instruction does not round to 24-bits
10385 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10386 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10387 match(Set dst (MulF (LoadF mem1) src));
10388
10389 format %{ "FLD $mem1 ===MACRO1===\n\t"
10390 "FMUL ST,$src\n\t"
10391 "FSTP $dst" %}
10392 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10393 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10394 OpcReg_FPR(src),
10395 Pop_Reg_FPR(dst) );
10396 ins_pipe( fpu_reg_reg_mem );
10397 %}
10398 //
10399 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10400 // This instruction does not round to 24-bits
10401 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10402 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10403 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10404 ins_cost(95);
10405
10406 format %{ "FLD $mem1 ===MACRO2===\n\t"
10407 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10408 "FADD ST,$src2\n\t"
10409 "FSTP $dst" %}
10410 opcode(0xD9); /* LoadF D9 /0 */
10411 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10412 FMul_ST_reg(src1),
10413 FAdd_ST_reg(src2),
10414 Pop_Reg_FPR(dst) );
10415 ins_pipe( fpu_reg_mem_reg_reg );
10416 %}
10417
10418 // MACRO3 -- addFPR a mulFPR
10419 // This instruction does not round to 24-bits. It is a '2-address'
10420 // instruction in that the result goes back to src2. This eliminates
10421 // a move from the macro; possibly the register allocator will have
10422 // to add it back (and maybe not).
10423 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10424 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10425 match(Set src2 (AddF (MulF src0 src1) src2));
10426
10427 format %{ "FLD $src0 ===MACRO3===\n\t"
10428 "FMUL ST,$src1\n\t"
10429 "FADDP $src2,ST" %}
10430 opcode(0xD9); /* LoadF D9 /0 */
10431 ins_encode( Push_Reg_FPR(src0),
10432 FMul_ST_reg(src1),
10433 FAddP_reg_ST(src2) );
10434 ins_pipe( fpu_reg_reg_reg );
10435 %}
10436
10437 // MACRO4 -- divFPR subFPR
10438 // This instruction does not round to 24-bits
10439 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10440 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10441 match(Set dst (DivF (SubF src2 src1) src3));
10442
10443 format %{ "FLD $src2 ===MACRO4===\n\t"
10444 "FSUB ST,$src1\n\t"
10445 "FDIV ST,$src3\n\t"
10446 "FSTP $dst" %}
10447 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10448 ins_encode( Push_Reg_FPR(src2),
10449 subFPR_divFPR_encode(src1,src3),
10450 Pop_Reg_FPR(dst) );
10451 ins_pipe( fpu_reg_reg_reg_reg );
10452 %}
10453
10454 // Spill to obtain 24-bit precision
10455 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10456 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10457 match(Set dst (DivF src1 src2));
10458
10459 format %{ "FDIV $dst,$src1,$src2" %}
10460 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10461 ins_encode( Push_Reg_FPR(src1),
10462 OpcReg_FPR(src2),
10463 Pop_Mem_FPR(dst) );
10464 ins_pipe( fpu_mem_reg_reg );
10465 %}
10466 //
10467 // This instruction does not round to 24-bits
10468 instruct divFPR_reg(regFPR dst, regFPR src) %{
10469 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10470 match(Set dst (DivF dst src));
10471
10472 format %{ "FDIV $dst,$src" %}
10473 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10474 ins_encode( Push_Reg_FPR(src),
10475 OpcP, RegOpc(dst) );
10476 ins_pipe( fpu_reg_reg );
10477 %}
10478
10479
10480 // Spill to obtain 24-bit precision
10481 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10482 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10483 match(Set dst (ModF src1 src2));
10484 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10485
10486 format %{ "FMOD $dst,$src1,$src2" %}
10487 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10488 emitModDPR(),
10489 Push_Result_Mod_DPR(src2),
10490 Pop_Mem_FPR(dst));
10491 ins_pipe( pipe_slow );
10492 %}
10493 //
10494 // This instruction does not round to 24-bits
10495 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10496 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10497 match(Set dst (ModF dst src));
10498 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10499
10500 format %{ "FMOD $dst,$src" %}
10501 ins_encode(Push_Reg_Mod_DPR(dst, src),
10502 emitModDPR(),
10503 Push_Result_Mod_DPR(src),
10504 Pop_Reg_FPR(dst));
10505 ins_pipe( pipe_slow );
10506 %}
10507
10508 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10509 predicate(UseSSE>=1);
10510 match(Set dst (ModF src0 src1));
10511 effect(KILL rax, KILL cr);
10512 format %{ "SUB ESP,4\t # FMOD\n"
10513 "\tMOVSS [ESP+0],$src1\n"
10514 "\tFLD_S [ESP+0]\n"
10515 "\tMOVSS [ESP+0],$src0\n"
10516 "\tFLD_S [ESP+0]\n"
10517 "loop:\tFPREM\n"
10518 "\tFWAIT\n"
10519 "\tFNSTSW AX\n"
10520 "\tSAHF\n"
10521 "\tJP loop\n"
10522 "\tFSTP_S [ESP+0]\n"
10523 "\tMOVSS $dst,[ESP+0]\n"
10524 "\tADD ESP,4\n"
10525 "\tFSTP ST0\t # Restore FPU Stack"
10526 %}
10527 ins_cost(250);
10528 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10529 ins_pipe( pipe_slow );
10530 %}
10531
10532
10533 //----------Arithmetic Conversion Instructions---------------------------------
10534 // The conversions operations are all Alpha sorted. Please keep it that way!
10535
10536 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10537 predicate(UseSSE==0);
10538 match(Set dst (RoundFloat src));
10539 ins_cost(125);
10540 format %{ "FST_S $dst,$src\t# F-round" %}
10541 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10542 ins_pipe( fpu_mem_reg );
10543 %}
10544
10545 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10546 predicate(UseSSE<=1);
10547 match(Set dst (RoundDouble src));
10548 ins_cost(125);
10549 format %{ "FST_D $dst,$src\t# D-round" %}
10550 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10551 ins_pipe( fpu_mem_reg );
10552 %}
10553
10554 // Force rounding to 24-bit precision and 6-bit exponent
10555 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10556 predicate(UseSSE==0);
10557 match(Set dst (ConvD2F src));
10558 format %{ "FST_S $dst,$src\t# F-round" %}
10559 expand %{
10560 roundFloat_mem_reg(dst,src);
10561 %}
10562 %}
10563
10564 // Force rounding to 24-bit precision and 6-bit exponent
10565 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10566 predicate(UseSSE==1);
10567 match(Set dst (ConvD2F src));
10568 effect( KILL cr );
10569 format %{ "SUB ESP,4\n\t"
10570 "FST_S [ESP],$src\t# F-round\n\t"
10571 "MOVSS $dst,[ESP]\n\t"
10572 "ADD ESP,4" %}
10573 ins_encode %{
10574 __ subptr(rsp, 4);
10575 if ($src$$reg != FPR1L_enc) {
10576 __ fld_s($src$$reg-1);
10577 __ fstp_s(Address(rsp, 0));
10578 } else {
10579 __ fst_s(Address(rsp, 0));
10580 }
10581 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10582 __ addptr(rsp, 4);
10583 %}
10584 ins_pipe( pipe_slow );
10585 %}
10586
10587 // Force rounding double precision to single precision
10588 instruct convD2F_reg(regF dst, regD src) %{
10589 predicate(UseSSE>=2);
10590 match(Set dst (ConvD2F src));
10591 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10592 ins_encode %{
10593 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10594 %}
10595 ins_pipe( pipe_slow );
10596 %}
10597
10598 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10599 predicate(UseSSE==0);
10600 match(Set dst (ConvF2D src));
10601 format %{ "FST_S $dst,$src\t# D-round" %}
10602 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10603 ins_pipe( fpu_reg_reg );
10604 %}
10605
10606 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10607 predicate(UseSSE==1);
10608 match(Set dst (ConvF2D src));
10609 format %{ "FST_D $dst,$src\t# D-round" %}
10610 expand %{
10611 roundDouble_mem_reg(dst,src);
10612 %}
10613 %}
10614
10615 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10616 predicate(UseSSE==1);
10617 match(Set dst (ConvF2D src));
10618 effect( KILL cr );
10619 format %{ "SUB ESP,4\n\t"
10620 "MOVSS [ESP] $src\n\t"
10621 "FLD_S [ESP]\n\t"
10622 "ADD ESP,4\n\t"
10623 "FSTP $dst\t# D-round" %}
10624 ins_encode %{
10625 __ subptr(rsp, 4);
10626 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10627 __ fld_s(Address(rsp, 0));
10628 __ addptr(rsp, 4);
10629 __ fstp_d($dst$$reg);
10630 %}
10631 ins_pipe( pipe_slow );
10632 %}
10633
10634 instruct convF2D_reg(regD dst, regF src) %{
10635 predicate(UseSSE>=2);
10636 match(Set dst (ConvF2D src));
10637 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10638 ins_encode %{
10639 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10640 %}
10641 ins_pipe( pipe_slow );
10642 %}
10643
10644 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10645 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10646 predicate(UseSSE<=1);
10647 match(Set dst (ConvD2I src));
10648 effect( KILL tmp, KILL cr );
10649 format %{ "FLD $src\t# Convert double to int \n\t"
10650 "FLDCW trunc mode\n\t"
10651 "SUB ESP,4\n\t"
10652 "FISTp [ESP + #0]\n\t"
10653 "FLDCW std/24-bit mode\n\t"
10654 "POP EAX\n\t"
10655 "CMP EAX,0x80000000\n\t"
10656 "JNE,s fast\n\t"
10657 "FLD_D $src\n\t"
10658 "CALL d2i_wrapper\n"
10659 "fast:" %}
10660 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10661 ins_pipe( pipe_slow );
10662 %}
10663
10664 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10665 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10666 predicate(UseSSE>=2);
10667 match(Set dst (ConvD2I src));
10668 effect( KILL tmp, KILL cr );
10669 format %{ "CVTTSD2SI $dst, $src\n\t"
10670 "CMP $dst,0x80000000\n\t"
10671 "JNE,s fast\n\t"
10672 "SUB ESP, 8\n\t"
10673 "MOVSD [ESP], $src\n\t"
10674 "FLD_D [ESP]\n\t"
10675 "ADD ESP, 8\n\t"
10676 "CALL d2i_wrapper\n"
10677 "fast:" %}
10678 ins_encode %{
10679 Label fast;
10680 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10681 __ cmpl($dst$$Register, 0x80000000);
10682 __ jccb(Assembler::notEqual, fast);
10683 __ subptr(rsp, 8);
10684 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10685 __ fld_d(Address(rsp, 0));
10686 __ addptr(rsp, 8);
10687 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10688 __ bind(fast);
10689 %}
10690 ins_pipe( pipe_slow );
10691 %}
10692
10693 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10694 predicate(UseSSE<=1);
10695 match(Set dst (ConvD2L src));
10696 effect( KILL cr );
10697 format %{ "FLD $src\t# Convert double to long\n\t"
10698 "FLDCW trunc mode\n\t"
10699 "SUB ESP,8\n\t"
10700 "FISTp [ESP + #0]\n\t"
10701 "FLDCW std/24-bit mode\n\t"
10702 "POP EAX\n\t"
10703 "POP EDX\n\t"
10704 "CMP EDX,0x80000000\n\t"
10705 "JNE,s fast\n\t"
10706 "TEST EAX,EAX\n\t"
10707 "JNE,s fast\n\t"
10708 "FLD $src\n\t"
10709 "CALL d2l_wrapper\n"
10710 "fast:" %}
10711 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10712 ins_pipe( pipe_slow );
10713 %}
10714
10715 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10716 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10717 predicate (UseSSE>=2);
10718 match(Set dst (ConvD2L src));
10719 effect( KILL cr );
10720 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10721 "MOVSD [ESP],$src\n\t"
10722 "FLD_D [ESP]\n\t"
10723 "FLDCW trunc mode\n\t"
10724 "FISTp [ESP + #0]\n\t"
10725 "FLDCW std/24-bit mode\n\t"
10726 "POP EAX\n\t"
10727 "POP EDX\n\t"
10728 "CMP EDX,0x80000000\n\t"
10729 "JNE,s fast\n\t"
10730 "TEST EAX,EAX\n\t"
10731 "JNE,s fast\n\t"
10732 "SUB ESP,8\n\t"
10733 "MOVSD [ESP],$src\n\t"
10734 "FLD_D [ESP]\n\t"
10735 "ADD ESP,8\n\t"
10736 "CALL d2l_wrapper\n"
10737 "fast:" %}
10738 ins_encode %{
10739 Label fast;
10740 __ subptr(rsp, 8);
10741 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10742 __ fld_d(Address(rsp, 0));
10743 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10744 __ fistp_d(Address(rsp, 0));
10745 // Restore the rounding mode, mask the exception
10746 if (Compile::current()->in_24_bit_fp_mode()) {
10747 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10748 } else {
10749 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10750 }
10751 // Load the converted long, adjust CPU stack
10752 __ pop(rax);
10753 __ pop(rdx);
10754 __ cmpl(rdx, 0x80000000);
10755 __ jccb(Assembler::notEqual, fast);
10756 __ testl(rax, rax);
10757 __ jccb(Assembler::notEqual, fast);
10758 __ subptr(rsp, 8);
10759 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10760 __ fld_d(Address(rsp, 0));
10761 __ addptr(rsp, 8);
10762 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10763 __ bind(fast);
10764 %}
10765 ins_pipe( pipe_slow );
10766 %}
10767
10768 // Convert a double to an int. Java semantics require we do complex
10769 // manglations in the corner cases. So we set the rounding mode to
10770 // 'zero', store the darned double down as an int, and reset the
10771 // rounding mode to 'nearest'. The hardware stores a flag value down
10772 // if we would overflow or converted a NAN; we check for this and
10773 // and go the slow path if needed.
10774 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
10775 predicate(UseSSE==0);
10776 match(Set dst (ConvF2I src));
10777 effect( KILL tmp, KILL cr );
10778 format %{ "FLD $src\t# Convert float to int \n\t"
10779 "FLDCW trunc mode\n\t"
10780 "SUB ESP,4\n\t"
10781 "FISTp [ESP + #0]\n\t"
10782 "FLDCW std/24-bit mode\n\t"
10783 "POP EAX\n\t"
10784 "CMP EAX,0x80000000\n\t"
10785 "JNE,s fast\n\t"
10786 "FLD $src\n\t"
10787 "CALL d2i_wrapper\n"
10788 "fast:" %}
10789 // DPR2I_encoding works for FPR2I
10790 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
10791 ins_pipe( pipe_slow );
10792 %}
10793
10794 // Convert a float in xmm to an int reg.
10795 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
10796 predicate(UseSSE>=1);
10797 match(Set dst (ConvF2I src));
10798 effect( KILL tmp, KILL cr );
10799 format %{ "CVTTSS2SI $dst, $src\n\t"
10800 "CMP $dst,0x80000000\n\t"
10801 "JNE,s fast\n\t"
10802 "SUB ESP, 4\n\t"
10803 "MOVSS [ESP], $src\n\t"
10804 "FLD [ESP]\n\t"
10805 "ADD ESP, 4\n\t"
10806 "CALL d2i_wrapper\n"
10807 "fast:" %}
10808 ins_encode %{
10809 Label fast;
10810 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10811 __ cmpl($dst$$Register, 0x80000000);
10812 __ jccb(Assembler::notEqual, fast);
10813 __ subptr(rsp, 4);
10814 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10815 __ fld_s(Address(rsp, 0));
10816 __ addptr(rsp, 4);
10817 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10818 __ bind(fast);
10819 %}
10820 ins_pipe( pipe_slow );
10821 %}
10822
10823 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
10824 predicate(UseSSE==0);
10825 match(Set dst (ConvF2L src));
10826 effect( KILL cr );
10827 format %{ "FLD $src\t# Convert float to long\n\t"
10828 "FLDCW trunc mode\n\t"
10829 "SUB ESP,8\n\t"
10830 "FISTp [ESP + #0]\n\t"
10831 "FLDCW std/24-bit mode\n\t"
10832 "POP EAX\n\t"
10833 "POP EDX\n\t"
10834 "CMP EDX,0x80000000\n\t"
10835 "JNE,s fast\n\t"
10836 "TEST EAX,EAX\n\t"
10837 "JNE,s fast\n\t"
10838 "FLD $src\n\t"
10839 "CALL d2l_wrapper\n"
10840 "fast:" %}
10841 // DPR2L_encoding works for FPR2L
10842 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
10843 ins_pipe( pipe_slow );
10844 %}
10845
10846 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10847 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
10848 predicate (UseSSE>=1);
10849 match(Set dst (ConvF2L src));
10850 effect( KILL cr );
10851 format %{ "SUB ESP,8\t# Convert float to long\n\t"
10852 "MOVSS [ESP],$src\n\t"
10853 "FLD_S [ESP]\n\t"
10854 "FLDCW trunc mode\n\t"
10855 "FISTp [ESP + #0]\n\t"
10856 "FLDCW std/24-bit mode\n\t"
10857 "POP EAX\n\t"
10858 "POP EDX\n\t"
10859 "CMP EDX,0x80000000\n\t"
10860 "JNE,s fast\n\t"
10861 "TEST EAX,EAX\n\t"
10862 "JNE,s fast\n\t"
10863 "SUB ESP,4\t# Convert float to long\n\t"
10864 "MOVSS [ESP],$src\n\t"
10865 "FLD_S [ESP]\n\t"
10866 "ADD ESP,4\n\t"
10867 "CALL d2l_wrapper\n"
10868 "fast:" %}
10869 ins_encode %{
10870 Label fast;
10871 __ subptr(rsp, 8);
10872 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10873 __ fld_s(Address(rsp, 0));
10874 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10875 __ fistp_d(Address(rsp, 0));
10876 // Restore the rounding mode, mask the exception
10877 if (Compile::current()->in_24_bit_fp_mode()) {
10878 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10879 } else {
10880 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10881 }
10882 // Load the converted long, adjust CPU stack
10883 __ pop(rax);
10884 __ pop(rdx);
10885 __ cmpl(rdx, 0x80000000);
10886 __ jccb(Assembler::notEqual, fast);
10887 __ testl(rax, rax);
10888 __ jccb(Assembler::notEqual, fast);
10889 __ subptr(rsp, 4);
10890 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10891 __ fld_s(Address(rsp, 0));
10892 __ addptr(rsp, 4);
10893 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10894 __ bind(fast);
10895 %}
10896 ins_pipe( pipe_slow );
10897 %}
10898
10899 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
10900 predicate( UseSSE<=1 );
10901 match(Set dst (ConvI2D src));
10902 format %{ "FILD $src\n\t"
10903 "FSTP $dst" %}
10904 opcode(0xDB, 0x0); /* DB /0 */
10905 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
10906 ins_pipe( fpu_reg_mem );
10907 %}
10908
10909 instruct convI2D_reg(regD dst, rRegI src) %{
10910 predicate( UseSSE>=2 && !UseXmmI2D );
10911 match(Set dst (ConvI2D src));
10912 format %{ "CVTSI2SD $dst,$src" %}
10913 ins_encode %{
10914 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10915 %}
10916 ins_pipe( pipe_slow );
10917 %}
10918
10919 instruct convI2D_mem(regD dst, memory mem) %{
10920 predicate( UseSSE>=2 );
10921 match(Set dst (ConvI2D (LoadI mem)));
10922 format %{ "CVTSI2SD $dst,$mem" %}
10923 ins_encode %{
10924 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
10925 %}
10926 ins_pipe( pipe_slow );
10927 %}
10928
10929 instruct convXI2D_reg(regD dst, rRegI src)
10930 %{
10931 predicate( UseSSE>=2 && UseXmmI2D );
10932 match(Set dst (ConvI2D src));
10933
10934 format %{ "MOVD $dst,$src\n\t"
10935 "CVTDQ2PD $dst,$dst\t# i2d" %}
10936 ins_encode %{
10937 __ movdl($dst$$XMMRegister, $src$$Register);
10938 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10939 %}
10940 ins_pipe(pipe_slow); // XXX
10941 %}
10942
10943 instruct convI2DPR_mem(regDPR dst, memory mem) %{
10944 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
10945 match(Set dst (ConvI2D (LoadI mem)));
10946 format %{ "FILD $mem\n\t"
10947 "FSTP $dst" %}
10948 opcode(0xDB); /* DB /0 */
10949 ins_encode( OpcP, RMopc_Mem(0x00,mem),
10950 Pop_Reg_DPR(dst));
10951 ins_pipe( fpu_reg_mem );
10952 %}
10953
10954 // Convert a byte to a float; no rounding step needed.
10955 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
10956 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
10957 match(Set dst (ConvI2F src));
10958 format %{ "FILD $src\n\t"
10959 "FSTP $dst" %}
10960
10961 opcode(0xDB, 0x0); /* DB /0 */
10962 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
10963 ins_pipe( fpu_reg_mem );
10964 %}
10965
10966 // In 24-bit mode, force exponent rounding by storing back out
10967 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
10968 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10969 match(Set dst (ConvI2F src));
10970 ins_cost(200);
10971 format %{ "FILD $src\n\t"
10972 "FSTP_S $dst" %}
10973 opcode(0xDB, 0x0); /* DB /0 */
10974 ins_encode( Push_Mem_I(src),
10975 Pop_Mem_FPR(dst));
10976 ins_pipe( fpu_mem_mem );
10977 %}
10978
10979 // In 24-bit mode, force exponent rounding by storing back out
10980 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
10981 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10982 match(Set dst (ConvI2F (LoadI mem)));
10983 ins_cost(200);
10984 format %{ "FILD $mem\n\t"
10985 "FSTP_S $dst" %}
10986 opcode(0xDB); /* DB /0 */
10987 ins_encode( OpcP, RMopc_Mem(0x00,mem),
10988 Pop_Mem_FPR(dst));
10989 ins_pipe( fpu_mem_mem );
10990 %}
10991
10992 // This instruction does not round to 24-bits
10993 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
10994 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10995 match(Set dst (ConvI2F src));
10996 format %{ "FILD $src\n\t"
10997 "FSTP $dst" %}
10998 opcode(0xDB, 0x0); /* DB /0 */
10999 ins_encode( Push_Mem_I(src),
11000 Pop_Reg_FPR(dst));
11001 ins_pipe( fpu_reg_mem );
11002 %}
11003
11004 // This instruction does not round to 24-bits
11005 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11006 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11007 match(Set dst (ConvI2F (LoadI mem)));
11008 format %{ "FILD $mem\n\t"
11009 "FSTP $dst" %}
11010 opcode(0xDB); /* DB /0 */
11011 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11012 Pop_Reg_FPR(dst));
11013 ins_pipe( fpu_reg_mem );
11014 %}
11015
11016 // Convert an int to a float in xmm; no rounding step needed.
11017 instruct convI2F_reg(regF dst, rRegI src) %{
11018 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11019 match(Set dst (ConvI2F src));
11020 format %{ "CVTSI2SS $dst, $src" %}
11021 ins_encode %{
11022 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11023 %}
11024 ins_pipe( pipe_slow );
11025 %}
11026
11027 instruct convXI2F_reg(regF dst, rRegI src)
11028 %{
11029 predicate( UseSSE>=2 && UseXmmI2F );
11030 match(Set dst (ConvI2F src));
11031
11032 format %{ "MOVD $dst,$src\n\t"
11033 "CVTDQ2PS $dst,$dst\t# i2f" %}
11034 ins_encode %{
11035 __ movdl($dst$$XMMRegister, $src$$Register);
11036 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11037 %}
11038 ins_pipe(pipe_slow); // XXX
11039 %}
11040
11041 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11042 match(Set dst (ConvI2L src));
11043 effect(KILL cr);
11044 ins_cost(375);
11045 format %{ "MOV $dst.lo,$src\n\t"
11046 "MOV $dst.hi,$src\n\t"
11047 "SAR $dst.hi,31" %}
11048 ins_encode(convert_int_long(dst,src));
11049 ins_pipe( ialu_reg_reg_long );
11050 %}
11051
11052 // Zero-extend convert int to long
11053 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11054 match(Set dst (AndL (ConvI2L src) mask) );
11055 effect( KILL flags );
11056 ins_cost(250);
11057 format %{ "MOV $dst.lo,$src\n\t"
11058 "XOR $dst.hi,$dst.hi" %}
11059 opcode(0x33); // XOR
11060 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11061 ins_pipe( ialu_reg_reg_long );
11062 %}
11063
11064 // Zero-extend long
11065 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11066 match(Set dst (AndL src mask) );
11067 effect( KILL flags );
11068 ins_cost(250);
11069 format %{ "MOV $dst.lo,$src.lo\n\t"
11070 "XOR $dst.hi,$dst.hi\n\t" %}
11071 opcode(0x33); // XOR
11072 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11073 ins_pipe( ialu_reg_reg_long );
11074 %}
11075
11076 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11077 predicate (UseSSE<=1);
11078 match(Set dst (ConvL2D src));
11079 effect( KILL cr );
11080 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11081 "PUSH $src.lo\n\t"
11082 "FILD ST,[ESP + #0]\n\t"
11083 "ADD ESP,8\n\t"
11084 "FSTP_D $dst\t# D-round" %}
11085 opcode(0xDF, 0x5); /* DF /5 */
11086 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11087 ins_pipe( pipe_slow );
11088 %}
11089
11090 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11091 predicate (UseSSE>=2);
11092 match(Set dst (ConvL2D src));
11093 effect( KILL cr );
11094 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11095 "PUSH $src.lo\n\t"
11096 "FILD_D [ESP]\n\t"
11097 "FSTP_D [ESP]\n\t"
11098 "MOVSD $dst,[ESP]\n\t"
11099 "ADD ESP,8" %}
11100 opcode(0xDF, 0x5); /* DF /5 */
11101 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11102 ins_pipe( pipe_slow );
11103 %}
11104
11105 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11106 predicate (UseSSE>=1);
11107 match(Set dst (ConvL2F src));
11108 effect( KILL cr );
11109 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11110 "PUSH $src.lo\n\t"
11111 "FILD_D [ESP]\n\t"
11112 "FSTP_S [ESP]\n\t"
11113 "MOVSS $dst,[ESP]\n\t"
11114 "ADD ESP,8" %}
11115 opcode(0xDF, 0x5); /* DF /5 */
11116 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11117 ins_pipe( pipe_slow );
11118 %}
11119
11120 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11121 match(Set dst (ConvL2F src));
11122 effect( KILL cr );
11123 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11124 "PUSH $src.lo\n\t"
11125 "FILD ST,[ESP + #0]\n\t"
11126 "ADD ESP,8\n\t"
11127 "FSTP_S $dst\t# F-round" %}
11128 opcode(0xDF, 0x5); /* DF /5 */
11129 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11130 ins_pipe( pipe_slow );
11131 %}
11132
11133 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11134 match(Set dst (ConvL2I src));
11135 effect( DEF dst, USE src );
11136 format %{ "MOV $dst,$src.lo" %}
11137 ins_encode(enc_CopyL_Lo(dst,src));
11138 ins_pipe( ialu_reg_reg );
11139 %}
11140
11141
11142 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11143 match(Set dst (MoveF2I src));
11144 effect( DEF dst, USE src );
11145 ins_cost(100);
11146 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11147 ins_encode %{
11148 __ movl($dst$$Register, Address(rsp, $src$$disp));
11149 %}
11150 ins_pipe( ialu_reg_mem );
11151 %}
11152
11153 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11154 predicate(UseSSE==0);
11155 match(Set dst (MoveF2I src));
11156 effect( DEF dst, USE src );
11157
11158 ins_cost(125);
11159 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11160 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11161 ins_pipe( fpu_mem_reg );
11162 %}
11163
11164 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11165 predicate(UseSSE>=1);
11166 match(Set dst (MoveF2I src));
11167 effect( DEF dst, USE src );
11168
11169 ins_cost(95);
11170 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11171 ins_encode %{
11172 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11173 %}
11174 ins_pipe( pipe_slow );
11175 %}
11176
11177 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11178 predicate(UseSSE>=2);
11179 match(Set dst (MoveF2I src));
11180 effect( DEF dst, USE src );
11181 ins_cost(85);
11182 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11183 ins_encode %{
11184 __ movdl($dst$$Register, $src$$XMMRegister);
11185 %}
11186 ins_pipe( pipe_slow );
11187 %}
11188
11189 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11190 match(Set dst (MoveI2F src));
11191 effect( DEF dst, USE src );
11192
11193 ins_cost(100);
11194 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11195 ins_encode %{
11196 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11197 %}
11198 ins_pipe( ialu_mem_reg );
11199 %}
11200
11201
11202 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11203 predicate(UseSSE==0);
11204 match(Set dst (MoveI2F src));
11205 effect(DEF dst, USE src);
11206
11207 ins_cost(125);
11208 format %{ "FLD_S $src\n\t"
11209 "FSTP $dst\t# MoveI2F_stack_reg" %}
11210 opcode(0xD9); /* D9 /0, FLD m32real */
11211 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11212 Pop_Reg_FPR(dst) );
11213 ins_pipe( fpu_reg_mem );
11214 %}
11215
11216 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11217 predicate(UseSSE>=1);
11218 match(Set dst (MoveI2F src));
11219 effect( DEF dst, USE src );
11220
11221 ins_cost(95);
11222 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11223 ins_encode %{
11224 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11225 %}
11226 ins_pipe( pipe_slow );
11227 %}
11228
11229 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11230 predicate(UseSSE>=2);
11231 match(Set dst (MoveI2F src));
11232 effect( DEF dst, USE src );
11233
11234 ins_cost(85);
11235 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11236 ins_encode %{
11237 __ movdl($dst$$XMMRegister, $src$$Register);
11238 %}
11239 ins_pipe( pipe_slow );
11240 %}
11241
11242 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11243 match(Set dst (MoveD2L src));
11244 effect(DEF dst, USE src);
11245
11246 ins_cost(250);
11247 format %{ "MOV $dst.lo,$src\n\t"
11248 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11249 opcode(0x8B, 0x8B);
11250 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11251 ins_pipe( ialu_mem_long_reg );
11252 %}
11253
11254 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11255 predicate(UseSSE<=1);
11256 match(Set dst (MoveD2L src));
11257 effect(DEF dst, USE src);
11258
11259 ins_cost(125);
11260 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11261 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11262 ins_pipe( fpu_mem_reg );
11263 %}
11264
11265 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11266 predicate(UseSSE>=2);
11267 match(Set dst (MoveD2L src));
11268 effect(DEF dst, USE src);
11269 ins_cost(95);
11270 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11271 ins_encode %{
11272 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11273 %}
11274 ins_pipe( pipe_slow );
11275 %}
11276
11277 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11278 predicate(UseSSE>=2);
11279 match(Set dst (MoveD2L src));
11280 effect(DEF dst, USE src, TEMP tmp);
11281 ins_cost(85);
11282 format %{ "MOVD $dst.lo,$src\n\t"
11283 "PSHUFLW $tmp,$src,0x4E\n\t"
11284 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11285 ins_encode %{
11286 __ movdl($dst$$Register, $src$$XMMRegister);
11287 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11288 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11289 %}
11290 ins_pipe( pipe_slow );
11291 %}
11292
11293 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11294 match(Set dst (MoveL2D src));
11295 effect(DEF dst, USE src);
11296
11297 ins_cost(200);
11298 format %{ "MOV $dst,$src.lo\n\t"
11299 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11300 opcode(0x89, 0x89);
11301 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11302 ins_pipe( ialu_mem_long_reg );
11303 %}
11304
11305
11306 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11307 predicate(UseSSE<=1);
11308 match(Set dst (MoveL2D src));
11309 effect(DEF dst, USE src);
11310 ins_cost(125);
11311
11312 format %{ "FLD_D $src\n\t"
11313 "FSTP $dst\t# MoveL2D_stack_reg" %}
11314 opcode(0xDD); /* DD /0, FLD m64real */
11315 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11316 Pop_Reg_DPR(dst) );
11317 ins_pipe( fpu_reg_mem );
11318 %}
11319
11320
11321 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11322 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11323 match(Set dst (MoveL2D src));
11324 effect(DEF dst, USE src);
11325
11326 ins_cost(95);
11327 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11328 ins_encode %{
11329 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11330 %}
11331 ins_pipe( pipe_slow );
11332 %}
11333
11334 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11335 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11336 match(Set dst (MoveL2D src));
11337 effect(DEF dst, USE src);
11338
11339 ins_cost(95);
11340 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11341 ins_encode %{
11342 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11343 %}
11344 ins_pipe( pipe_slow );
11345 %}
11346
11347 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11348 predicate(UseSSE>=2);
11349 match(Set dst (MoveL2D src));
11350 effect(TEMP dst, USE src, TEMP tmp);
11351 ins_cost(85);
11352 format %{ "MOVD $dst,$src.lo\n\t"
11353 "MOVD $tmp,$src.hi\n\t"
11354 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11355 ins_encode %{
11356 __ movdl($dst$$XMMRegister, $src$$Register);
11357 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11358 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11359 %}
11360 ins_pipe( pipe_slow );
11361 %}
11362
11363
11364 // =======================================================================
11365 // fast clearing of an array
11366 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11367 predicate(!UseFastStosb);
11368 match(Set dummy (ClearArray cnt base));
11369 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11370 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11371 "SHL ECX,1\t# Convert doublewords to words\n\t"
11372 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11373 ins_encode %{
11374 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11375 %}
11376 ins_pipe( pipe_slow );
11377 %}
11378
11379 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11380 predicate(UseFastStosb);
11381 match(Set dummy (ClearArray cnt base));
11382 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11383 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11384 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
11385 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11386 ins_encode %{
11387 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11388 %}
11389 ins_pipe( pipe_slow );
11390 %}
11391
11392 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11393 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11394 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11395 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11396
11397 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11398 ins_encode %{
11399 __ string_compare($str1$$Register, $str2$$Register,
11400 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11401 $tmp1$$XMMRegister);
11402 %}
11403 ins_pipe( pipe_slow );
11404 %}
11405
11406 // fast string equals
11407 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11408 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11409 match(Set result (StrEquals (Binary str1 str2) cnt));
11410 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11411
11412 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11413 ins_encode %{
11414 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11415 $cnt$$Register, $result$$Register, $tmp3$$Register,
11416 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11417 %}
11418 ins_pipe( pipe_slow );
11419 %}
11420
11421 // fast search of substring with known size.
11422 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11423 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11424 predicate(UseSSE42Intrinsics);
11425 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11426 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11427
11428 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11429 ins_encode %{
11430 int icnt2 = (int)$int_cnt2$$constant;
11431 if (icnt2 >= 8) {
11432 // IndexOf for constant substrings with size >= 8 elements
11433 // which don't need to be loaded through stack.
11434 __ string_indexofC8($str1$$Register, $str2$$Register,
11435 $cnt1$$Register, $cnt2$$Register,
11436 icnt2, $result$$Register,
11437 $vec$$XMMRegister, $tmp$$Register);
11438 } else {
11439 // Small strings are loaded through stack if they cross page boundary.
11440 __ string_indexof($str1$$Register, $str2$$Register,
11441 $cnt1$$Register, $cnt2$$Register,
11442 icnt2, $result$$Register,
11443 $vec$$XMMRegister, $tmp$$Register);
11444 }
11445 %}
11446 ins_pipe( pipe_slow );
11447 %}
11448
11449 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11450 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11451 predicate(UseSSE42Intrinsics);
11452 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11453 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11454
11455 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11456 ins_encode %{
11457 __ string_indexof($str1$$Register, $str2$$Register,
11458 $cnt1$$Register, $cnt2$$Register,
11459 (-1), $result$$Register,
11460 $vec$$XMMRegister, $tmp$$Register);
11461 %}
11462 ins_pipe( pipe_slow );
11463 %}
11464
11465 // fast array equals
11466 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11467 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11468 %{
11469 match(Set result (AryEq ary1 ary2));
11470 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11471 //ins_cost(300);
11472
11473 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11474 ins_encode %{
11475 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11476 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11477 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11478 %}
11479 ins_pipe( pipe_slow );
11480 %}
11481
11482 // encode char[] to byte[] in ISO_8859_1
11483 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11484 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11485 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11486 match(Set result (EncodeISOArray src (Binary dst len)));
11487 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11488
11489 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11490 ins_encode %{
11491 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11492 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11493 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11494 %}
11495 ins_pipe( pipe_slow );
11496 %}
11497
11498
11499 //----------Control Flow Instructions------------------------------------------
11500 // Signed compare Instructions
11501 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11502 match(Set cr (CmpI op1 op2));
11503 effect( DEF cr, USE op1, USE op2 );
11504 format %{ "CMP $op1,$op2" %}
11505 opcode(0x3B); /* Opcode 3B /r */
11506 ins_encode( OpcP, RegReg( op1, op2) );
11507 ins_pipe( ialu_cr_reg_reg );
11508 %}
11509
11510 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11511 match(Set cr (CmpI op1 op2));
11512 effect( DEF cr, USE op1 );
11513 format %{ "CMP $op1,$op2" %}
11514 opcode(0x81,0x07); /* Opcode 81 /7 */
11515 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11516 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11517 ins_pipe( ialu_cr_reg_imm );
11518 %}
11519
11520 // Cisc-spilled version of cmpI_eReg
11521 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11522 match(Set cr (CmpI op1 (LoadI op2)));
11523
11524 format %{ "CMP $op1,$op2" %}
11525 ins_cost(500);
11526 opcode(0x3B); /* Opcode 3B /r */
11527 ins_encode( OpcP, RegMem( op1, op2) );
11528 ins_pipe( ialu_cr_reg_mem );
11529 %}
11530
11531 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11532 match(Set cr (CmpI src zero));
11533 effect( DEF cr, USE src );
11534
11535 format %{ "TEST $src,$src" %}
11536 opcode(0x85);
11537 ins_encode( OpcP, RegReg( src, src ) );
11538 ins_pipe( ialu_cr_reg_imm );
11539 %}
11540
11541 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11542 match(Set cr (CmpI (AndI src con) zero));
11543
11544 format %{ "TEST $src,$con" %}
11545 opcode(0xF7,0x00);
11546 ins_encode( OpcP, RegOpc(src), Con32(con) );
11547 ins_pipe( ialu_cr_reg_imm );
11548 %}
11549
11550 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11551 match(Set cr (CmpI (AndI src mem) zero));
11552
11553 format %{ "TEST $src,$mem" %}
11554 opcode(0x85);
11555 ins_encode( OpcP, RegMem( src, mem ) );
11556 ins_pipe( ialu_cr_reg_mem );
11557 %}
11558
11559 // Unsigned compare Instructions; really, same as signed except they
11560 // produce an eFlagsRegU instead of eFlagsReg.
11561 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11562 match(Set cr (CmpU op1 op2));
11563
11564 format %{ "CMPu $op1,$op2" %}
11565 opcode(0x3B); /* Opcode 3B /r */
11566 ins_encode( OpcP, RegReg( op1, op2) );
11567 ins_pipe( ialu_cr_reg_reg );
11568 %}
11569
11570 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11571 match(Set cr (CmpU op1 op2));
11572
11573 format %{ "CMPu $op1,$op2" %}
11574 opcode(0x81,0x07); /* Opcode 81 /7 */
11575 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11576 ins_pipe( ialu_cr_reg_imm );
11577 %}
11578
11579 // // Cisc-spilled version of cmpU_eReg
11580 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11581 match(Set cr (CmpU op1 (LoadI op2)));
11582
11583 format %{ "CMPu $op1,$op2" %}
11584 ins_cost(500);
11585 opcode(0x3B); /* Opcode 3B /r */
11586 ins_encode( OpcP, RegMem( op1, op2) );
11587 ins_pipe( ialu_cr_reg_mem );
11588 %}
11589
11590 // // Cisc-spilled version of cmpU_eReg
11591 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11592 // match(Set cr (CmpU (LoadI op1) op2));
11593 //
11594 // format %{ "CMPu $op1,$op2" %}
11595 // ins_cost(500);
11596 // opcode(0x39); /* Opcode 39 /r */
11597 // ins_encode( OpcP, RegMem( op1, op2) );
11598 //%}
11599
11600 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11601 match(Set cr (CmpU src zero));
11602
11603 format %{ "TESTu $src,$src" %}
11604 opcode(0x85);
11605 ins_encode( OpcP, RegReg( src, src ) );
11606 ins_pipe( ialu_cr_reg_imm );
11607 %}
11608
11609 // Unsigned pointer compare Instructions
11610 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11611 match(Set cr (CmpP op1 op2));
11612
11613 format %{ "CMPu $op1,$op2" %}
11614 opcode(0x3B); /* Opcode 3B /r */
11615 ins_encode( OpcP, RegReg( op1, op2) );
11616 ins_pipe( ialu_cr_reg_reg );
11617 %}
11618
11619 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11620 match(Set cr (CmpP op1 op2));
11621
11622 format %{ "CMPu $op1,$op2" %}
11623 opcode(0x81,0x07); /* Opcode 81 /7 */
11624 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11625 ins_pipe( ialu_cr_reg_imm );
11626 %}
11627
11628 // // Cisc-spilled version of cmpP_eReg
11629 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11630 match(Set cr (CmpP op1 (LoadP op2)));
11631
11632 format %{ "CMPu $op1,$op2" %}
11633 ins_cost(500);
11634 opcode(0x3B); /* Opcode 3B /r */
11635 ins_encode( OpcP, RegMem( op1, op2) );
11636 ins_pipe( ialu_cr_reg_mem );
11637 %}
11638
11639 // // Cisc-spilled version of cmpP_eReg
11640 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11641 // match(Set cr (CmpP (LoadP op1) op2));
11642 //
11643 // format %{ "CMPu $op1,$op2" %}
11644 // ins_cost(500);
11645 // opcode(0x39); /* Opcode 39 /r */
11646 // ins_encode( OpcP, RegMem( op1, op2) );
11647 //%}
11648
11649 // Compare raw pointer (used in out-of-heap check).
11650 // Only works because non-oop pointers must be raw pointers
11651 // and raw pointers have no anti-dependencies.
11652 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11653 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11654 match(Set cr (CmpP op1 (LoadP op2)));
11655
11656 format %{ "CMPu $op1,$op2" %}
11657 opcode(0x3B); /* Opcode 3B /r */
11658 ins_encode( OpcP, RegMem( op1, op2) );
11659 ins_pipe( ialu_cr_reg_mem );
11660 %}
11661
11662 //
11663 // This will generate a signed flags result. This should be ok
11664 // since any compare to a zero should be eq/neq.
11665 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11666 match(Set cr (CmpP src zero));
11667
11668 format %{ "TEST $src,$src" %}
11669 opcode(0x85);
11670 ins_encode( OpcP, RegReg( src, src ) );
11671 ins_pipe( ialu_cr_reg_imm );
11672 %}
11673
11674 // Cisc-spilled version of testP_reg
11675 // This will generate a signed flags result. This should be ok
11676 // since any compare to a zero should be eq/neq.
11677 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11678 match(Set cr (CmpP (LoadP op) zero));
11679
11680 format %{ "TEST $op,0xFFFFFFFF" %}
11681 ins_cost(500);
11682 opcode(0xF7); /* Opcode F7 /0 */
11683 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11684 ins_pipe( ialu_cr_reg_imm );
11685 %}
11686
11687 // Yanked all unsigned pointer compare operations.
11688 // Pointer compares are done with CmpP which is already unsigned.
11689
11690 //----------Max and Min--------------------------------------------------------
11691 // Min Instructions
11692 ////
11693 // *** Min and Max using the conditional move are slower than the
11694 // *** branch version on a Pentium III.
11695 // // Conditional move for min
11696 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11697 // effect( USE_DEF op2, USE op1, USE cr );
11698 // format %{ "CMOVlt $op2,$op1\t! min" %}
11699 // opcode(0x4C,0x0F);
11700 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11701 // ins_pipe( pipe_cmov_reg );
11702 //%}
11703 //
11704 //// Min Register with Register (P6 version)
11705 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11706 // predicate(VM_Version::supports_cmov() );
11707 // match(Set op2 (MinI op1 op2));
11708 // ins_cost(200);
11709 // expand %{
11710 // eFlagsReg cr;
11711 // compI_eReg(cr,op1,op2);
11712 // cmovI_reg_lt(op2,op1,cr);
11713 // %}
11714 //%}
11715
11716 // Min Register with Register (generic version)
11717 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11718 match(Set dst (MinI dst src));
11719 effect(KILL flags);
11720 ins_cost(300);
11721
11722 format %{ "MIN $dst,$src" %}
11723 opcode(0xCC);
11724 ins_encode( min_enc(dst,src) );
11725 ins_pipe( pipe_slow );
11726 %}
11727
11728 // Max Register with Register
11729 // *** Min and Max using the conditional move are slower than the
11730 // *** branch version on a Pentium III.
11731 // // Conditional move for max
11732 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11733 // effect( USE_DEF op2, USE op1, USE cr );
11734 // format %{ "CMOVgt $op2,$op1\t! max" %}
11735 // opcode(0x4F,0x0F);
11736 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11737 // ins_pipe( pipe_cmov_reg );
11738 //%}
11739 //
11740 // // Max Register with Register (P6 version)
11741 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11742 // predicate(VM_Version::supports_cmov() );
11743 // match(Set op2 (MaxI op1 op2));
11744 // ins_cost(200);
11745 // expand %{
11746 // eFlagsReg cr;
11747 // compI_eReg(cr,op1,op2);
11748 // cmovI_reg_gt(op2,op1,cr);
11749 // %}
11750 //%}
11751
11752 // Max Register with Register (generic version)
11753 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11754 match(Set dst (MaxI dst src));
11755 effect(KILL flags);
11756 ins_cost(300);
11757
11758 format %{ "MAX $dst,$src" %}
11759 opcode(0xCC);
11760 ins_encode( max_enc(dst,src) );
11761 ins_pipe( pipe_slow );
11762 %}
11763
11764 // ============================================================================
11765 // Counted Loop limit node which represents exact final iterator value.
11766 // Note: the resulting value should fit into integer range since
11767 // counted loops have limit check on overflow.
11768 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11769 match(Set limit (LoopLimit (Binary init limit) stride));
11770 effect(TEMP limit_hi, TEMP tmp, KILL flags);
11771 ins_cost(300);
11772
11773 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11774 ins_encode %{
11775 int strd = (int)$stride$$constant;
11776 assert(strd != 1 && strd != -1, "sanity");
11777 int m1 = (strd > 0) ? 1 : -1;
11778 // Convert limit to long (EAX:EDX)
11779 __ cdql();
11780 // Convert init to long (init:tmp)
11781 __ movl($tmp$$Register, $init$$Register);
11782 __ sarl($tmp$$Register, 31);
11783 // $limit - $init
11784 __ subl($limit$$Register, $init$$Register);
11785 __ sbbl($limit_hi$$Register, $tmp$$Register);
11786 // + ($stride - 1)
11787 if (strd > 0) {
11788 __ addl($limit$$Register, (strd - 1));
11789 __ adcl($limit_hi$$Register, 0);
11790 __ movl($tmp$$Register, strd);
11791 } else {
11792 __ addl($limit$$Register, (strd + 1));
11793 __ adcl($limit_hi$$Register, -1);
11794 __ lneg($limit_hi$$Register, $limit$$Register);
11795 __ movl($tmp$$Register, -strd);
11796 }
11797 // signed devision: (EAX:EDX) / pos_stride
11798 __ idivl($tmp$$Register);
11799 if (strd < 0) {
11800 // restore sign
11801 __ negl($tmp$$Register);
11802 }
11803 // (EAX) * stride
11804 __ mull($tmp$$Register);
11805 // + init (ignore upper bits)
11806 __ addl($limit$$Register, $init$$Register);
11807 %}
11808 ins_pipe( pipe_slow );
11809 %}
11810
11811 // ============================================================================
11812 // Branch Instructions
11813 // Jump Table
11814 instruct jumpXtnd(rRegI switch_val) %{
11815 match(Jump switch_val);
11816 ins_cost(350);
11817 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
11818 ins_encode %{
11819 // Jump to Address(table_base + switch_reg)
11820 Address index(noreg, $switch_val$$Register, Address::times_1);
11821 __ jump(ArrayAddress($constantaddress, index));
11822 %}
11823 ins_pipe(pipe_jmp);
11824 %}
11825
11826 // Jump Direct - Label defines a relative address from JMP+1
11827 instruct jmpDir(label labl) %{
11828 match(Goto);
11829 effect(USE labl);
11830
11831 ins_cost(300);
11832 format %{ "JMP $labl" %}
11833 size(5);
11834 ins_encode %{
11835 Label* L = $labl$$label;
11836 __ jmp(*L, false); // Always long jump
11837 %}
11838 ins_pipe( pipe_jmp );
11839 %}
11840
11841 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11842 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
11843 match(If cop cr);
11844 effect(USE labl);
11845
11846 ins_cost(300);
11847 format %{ "J$cop $labl" %}
11848 size(6);
11849 ins_encode %{
11850 Label* L = $labl$$label;
11851 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11852 %}
11853 ins_pipe( pipe_jcc );
11854 %}
11855
11856 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11857 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
11858 match(CountedLoopEnd cop cr);
11859 effect(USE labl);
11860
11861 ins_cost(300);
11862 format %{ "J$cop $labl\t# Loop end" %}
11863 size(6);
11864 ins_encode %{
11865 Label* L = $labl$$label;
11866 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11867 %}
11868 ins_pipe( pipe_jcc );
11869 %}
11870
11871 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11872 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
11873 match(CountedLoopEnd cop cmp);
11874 effect(USE labl);
11875
11876 ins_cost(300);
11877 format %{ "J$cop,u $labl\t# Loop end" %}
11878 size(6);
11879 ins_encode %{
11880 Label* L = $labl$$label;
11881 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11882 %}
11883 ins_pipe( pipe_jcc );
11884 %}
11885
11886 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
11887 match(CountedLoopEnd cop cmp);
11888 effect(USE labl);
11889
11890 ins_cost(200);
11891 format %{ "J$cop,u $labl\t# Loop end" %}
11892 size(6);
11893 ins_encode %{
11894 Label* L = $labl$$label;
11895 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11896 %}
11897 ins_pipe( pipe_jcc );
11898 %}
11899
11900 // Jump Direct Conditional - using unsigned comparison
11901 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
11902 match(If cop cmp);
11903 effect(USE labl);
11904
11905 ins_cost(300);
11906 format %{ "J$cop,u $labl" %}
11907 size(6);
11908 ins_encode %{
11909 Label* L = $labl$$label;
11910 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11911 %}
11912 ins_pipe(pipe_jcc);
11913 %}
11914
11915 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
11916 match(If cop cmp);
11917 effect(USE labl);
11918
11919 ins_cost(200);
11920 format %{ "J$cop,u $labl" %}
11921 size(6);
11922 ins_encode %{
11923 Label* L = $labl$$label;
11924 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11925 %}
11926 ins_pipe(pipe_jcc);
11927 %}
11928
11929 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
11930 match(If cop cmp);
11931 effect(USE labl);
11932
11933 ins_cost(200);
11934 format %{ $$template
11935 if ($cop$$cmpcode == Assembler::notEqual) {
11936 $$emit$$"JP,u $labl\n\t"
11937 $$emit$$"J$cop,u $labl"
11938 } else {
11939 $$emit$$"JP,u done\n\t"
11940 $$emit$$"J$cop,u $labl\n\t"
11941 $$emit$$"done:"
11942 }
11943 %}
11944 ins_encode %{
11945 Label* l = $labl$$label;
11946 if ($cop$$cmpcode == Assembler::notEqual) {
11947 __ jcc(Assembler::parity, *l, false);
11948 __ jcc(Assembler::notEqual, *l, false);
11949 } else if ($cop$$cmpcode == Assembler::equal) {
11950 Label done;
11951 __ jccb(Assembler::parity, done);
11952 __ jcc(Assembler::equal, *l, false);
11953 __ bind(done);
11954 } else {
11955 ShouldNotReachHere();
11956 }
11957 %}
11958 ins_pipe(pipe_jcc);
11959 %}
11960
11961 // ============================================================================
11962 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
11963 // array for an instance of the superklass. Set a hidden internal cache on a
11964 // hit (cache is checked with exposed code in gen_subtype_check()). Return
11965 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
11966 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
11967 match(Set result (PartialSubtypeCheck sub super));
11968 effect( KILL rcx, KILL cr );
11969
11970 ins_cost(1100); // slightly larger than the next version
11971 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
11972 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
11973 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
11974 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
11975 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
11976 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
11977 "XOR $result,$result\t\t Hit: EDI zero\n\t"
11978 "miss:\t" %}
11979
11980 opcode(0x1); // Force a XOR of EDI
11981 ins_encode( enc_PartialSubtypeCheck() );
11982 ins_pipe( pipe_slow );
11983 %}
11984
11985 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
11986 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11987 effect( KILL rcx, KILL result );
11988
11989 ins_cost(1000);
11990 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
11991 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
11992 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
11993 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
11994 "JNE,s miss\t\t# Missed: flags NZ\n\t"
11995 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
11996 "miss:\t" %}
11997
11998 opcode(0x0); // No need to XOR EDI
11999 ins_encode( enc_PartialSubtypeCheck() );
12000 ins_pipe( pipe_slow );
12001 %}
12002
12003 // ============================================================================
12004 // Branch Instructions -- short offset versions
12005 //
12006 // These instructions are used to replace jumps of a long offset (the default
12007 // match) with jumps of a shorter offset. These instructions are all tagged
12008 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12009 // match rules in general matching. Instead, the ADLC generates a conversion
12010 // method in the MachNode which can be used to do in-place replacement of the
12011 // long variant with the shorter variant. The compiler will determine if a
12012 // branch can be taken by the is_short_branch_offset() predicate in the machine
12013 // specific code section of the file.
12014
12015 // Jump Direct - Label defines a relative address from JMP+1
12016 instruct jmpDir_short(label labl) %{
12017 match(Goto);
12018 effect(USE labl);
12019
12020 ins_cost(300);
12021 format %{ "JMP,s $labl" %}
12022 size(2);
12023 ins_encode %{
12024 Label* L = $labl$$label;
12025 __ jmpb(*L);
12026 %}
12027 ins_pipe( pipe_jmp );
12028 ins_short_branch(1);
12029 %}
12030
12031 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12032 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12033 match(If cop cr);
12034 effect(USE labl);
12035
12036 ins_cost(300);
12037 format %{ "J$cop,s $labl" %}
12038 size(2);
12039 ins_encode %{
12040 Label* L = $labl$$label;
12041 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12042 %}
12043 ins_pipe( pipe_jcc );
12044 ins_short_branch(1);
12045 %}
12046
12047 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12048 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12049 match(CountedLoopEnd cop cr);
12050 effect(USE labl);
12051
12052 ins_cost(300);
12053 format %{ "J$cop,s $labl\t# Loop end" %}
12054 size(2);
12055 ins_encode %{
12056 Label* L = $labl$$label;
12057 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12058 %}
12059 ins_pipe( pipe_jcc );
12060 ins_short_branch(1);
12061 %}
12062
12063 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12064 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12065 match(CountedLoopEnd cop cmp);
12066 effect(USE labl);
12067
12068 ins_cost(300);
12069 format %{ "J$cop,us $labl\t# Loop end" %}
12070 size(2);
12071 ins_encode %{
12072 Label* L = $labl$$label;
12073 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12074 %}
12075 ins_pipe( pipe_jcc );
12076 ins_short_branch(1);
12077 %}
12078
12079 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12080 match(CountedLoopEnd cop cmp);
12081 effect(USE labl);
12082
12083 ins_cost(300);
12084 format %{ "J$cop,us $labl\t# Loop end" %}
12085 size(2);
12086 ins_encode %{
12087 Label* L = $labl$$label;
12088 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12089 %}
12090 ins_pipe( pipe_jcc );
12091 ins_short_branch(1);
12092 %}
12093
12094 // Jump Direct Conditional - using unsigned comparison
12095 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12096 match(If cop cmp);
12097 effect(USE labl);
12098
12099 ins_cost(300);
12100 format %{ "J$cop,us $labl" %}
12101 size(2);
12102 ins_encode %{
12103 Label* L = $labl$$label;
12104 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12105 %}
12106 ins_pipe( pipe_jcc );
12107 ins_short_branch(1);
12108 %}
12109
12110 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12111 match(If cop cmp);
12112 effect(USE labl);
12113
12114 ins_cost(300);
12115 format %{ "J$cop,us $labl" %}
12116 size(2);
12117 ins_encode %{
12118 Label* L = $labl$$label;
12119 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12120 %}
12121 ins_pipe( pipe_jcc );
12122 ins_short_branch(1);
12123 %}
12124
12125 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12126 match(If cop cmp);
12127 effect(USE labl);
12128
12129 ins_cost(300);
12130 format %{ $$template
12131 if ($cop$$cmpcode == Assembler::notEqual) {
12132 $$emit$$"JP,u,s $labl\n\t"
12133 $$emit$$"J$cop,u,s $labl"
12134 } else {
12135 $$emit$$"JP,u,s done\n\t"
12136 $$emit$$"J$cop,u,s $labl\n\t"
12137 $$emit$$"done:"
12138 }
12139 %}
12140 size(4);
12141 ins_encode %{
12142 Label* l = $labl$$label;
12143 if ($cop$$cmpcode == Assembler::notEqual) {
12144 __ jccb(Assembler::parity, *l);
12145 __ jccb(Assembler::notEqual, *l);
12146 } else if ($cop$$cmpcode == Assembler::equal) {
12147 Label done;
12148 __ jccb(Assembler::parity, done);
12149 __ jccb(Assembler::equal, *l);
12150 __ bind(done);
12151 } else {
12152 ShouldNotReachHere();
12153 }
12154 %}
12155 ins_pipe(pipe_jcc);
12156 ins_short_branch(1);
12157 %}
12158
12159 // ============================================================================
12160 // Long Compare
12161 //
12162 // Currently we hold longs in 2 registers. Comparing such values efficiently
12163 // is tricky. The flavor of compare used depends on whether we are testing
12164 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12165 // The GE test is the negated LT test. The LE test can be had by commuting
12166 // the operands (yielding a GE test) and then negating; negate again for the
12167 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12168 // NE test is negated from that.
12169
12170 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12171 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12172 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12173 // are collapsed internally in the ADLC's dfa-gen code. The match for
12174 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12175 // foo match ends up with the wrong leaf. One fix is to not match both
12176 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12177 // both forms beat the trinary form of long-compare and both are very useful
12178 // on Intel which has so few registers.
12179
12180 // Manifest a CmpL result in an integer register. Very painful.
12181 // This is the test to avoid.
12182 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12183 match(Set dst (CmpL3 src1 src2));
12184 effect( KILL flags );
12185 ins_cost(1000);
12186 format %{ "XOR $dst,$dst\n\t"
12187 "CMP $src1.hi,$src2.hi\n\t"
12188 "JLT,s m_one\n\t"
12189 "JGT,s p_one\n\t"
12190 "CMP $src1.lo,$src2.lo\n\t"
12191 "JB,s m_one\n\t"
12192 "JEQ,s done\n"
12193 "p_one:\tINC $dst\n\t"
12194 "JMP,s done\n"
12195 "m_one:\tDEC $dst\n"
12196 "done:" %}
12197 ins_encode %{
12198 Label p_one, m_one, done;
12199 __ xorptr($dst$$Register, $dst$$Register);
12200 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12201 __ jccb(Assembler::less, m_one);
12202 __ jccb(Assembler::greater, p_one);
12203 __ cmpl($src1$$Register, $src2$$Register);
12204 __ jccb(Assembler::below, m_one);
12205 __ jccb(Assembler::equal, done);
12206 __ bind(p_one);
12207 __ incrementl($dst$$Register);
12208 __ jmpb(done);
12209 __ bind(m_one);
12210 __ decrementl($dst$$Register);
12211 __ bind(done);
12212 %}
12213 ins_pipe( pipe_slow );
12214 %}
12215
12216 //======
12217 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12218 // compares. Can be used for LE or GT compares by reversing arguments.
12219 // NOT GOOD FOR EQ/NE tests.
12220 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12221 match( Set flags (CmpL src zero ));
12222 ins_cost(100);
12223 format %{ "TEST $src.hi,$src.hi" %}
12224 opcode(0x85);
12225 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12226 ins_pipe( ialu_cr_reg_reg );
12227 %}
12228
12229 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12230 // compares. Can be used for LE or GT compares by reversing arguments.
12231 // NOT GOOD FOR EQ/NE tests.
12232 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12233 match( Set flags (CmpL src1 src2 ));
12234 effect( TEMP tmp );
12235 ins_cost(300);
12236 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12237 "MOV $tmp,$src1.hi\n\t"
12238 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12239 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12240 ins_pipe( ialu_cr_reg_reg );
12241 %}
12242
12243 // Long compares reg < zero/req OR reg >= zero/req.
12244 // Just a wrapper for a normal branch, plus the predicate test.
12245 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12246 match(If cmp flags);
12247 effect(USE labl);
12248 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12249 expand %{
12250 jmpCon(cmp,flags,labl); // JLT or JGE...
12251 %}
12252 %}
12253
12254 // Compare 2 longs and CMOVE longs.
12255 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12256 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12257 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12258 ins_cost(400);
12259 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12260 "CMOV$cmp $dst.hi,$src.hi" %}
12261 opcode(0x0F,0x40);
12262 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12263 ins_pipe( pipe_cmov_reg_long );
12264 %}
12265
12266 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12267 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12268 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12269 ins_cost(500);
12270 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12271 "CMOV$cmp $dst.hi,$src.hi" %}
12272 opcode(0x0F,0x40);
12273 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12274 ins_pipe( pipe_cmov_reg_long );
12275 %}
12276
12277 // Compare 2 longs and CMOVE ints.
12278 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12279 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12280 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12281 ins_cost(200);
12282 format %{ "CMOV$cmp $dst,$src" %}
12283 opcode(0x0F,0x40);
12284 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12285 ins_pipe( pipe_cmov_reg );
12286 %}
12287
12288 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12289 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12290 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12291 ins_cost(250);
12292 format %{ "CMOV$cmp $dst,$src" %}
12293 opcode(0x0F,0x40);
12294 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12295 ins_pipe( pipe_cmov_mem );
12296 %}
12297
12298 // Compare 2 longs and CMOVE ints.
12299 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12300 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12301 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12302 ins_cost(200);
12303 format %{ "CMOV$cmp $dst,$src" %}
12304 opcode(0x0F,0x40);
12305 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12306 ins_pipe( pipe_cmov_reg );
12307 %}
12308
12309 // Compare 2 longs and CMOVE doubles
12310 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12311 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12312 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12313 ins_cost(200);
12314 expand %{
12315 fcmovDPR_regS(cmp,flags,dst,src);
12316 %}
12317 %}
12318
12319 // Compare 2 longs and CMOVE doubles
12320 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12321 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12322 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12323 ins_cost(200);
12324 expand %{
12325 fcmovD_regS(cmp,flags,dst,src);
12326 %}
12327 %}
12328
12329 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12330 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12331 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12332 ins_cost(200);
12333 expand %{
12334 fcmovFPR_regS(cmp,flags,dst,src);
12335 %}
12336 %}
12337
12338 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12339 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12340 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12341 ins_cost(200);
12342 expand %{
12343 fcmovF_regS(cmp,flags,dst,src);
12344 %}
12345 %}
12346
12347 //======
12348 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12349 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12350 match( Set flags (CmpL src zero ));
12351 effect(TEMP tmp);
12352 ins_cost(200);
12353 format %{ "MOV $tmp,$src.lo\n\t"
12354 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12355 ins_encode( long_cmp_flags0( src, tmp ) );
12356 ins_pipe( ialu_reg_reg_long );
12357 %}
12358
12359 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12360 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12361 match( Set flags (CmpL src1 src2 ));
12362 ins_cost(200+300);
12363 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12364 "JNE,s skip\n\t"
12365 "CMP $src1.hi,$src2.hi\n\t"
12366 "skip:\t" %}
12367 ins_encode( long_cmp_flags1( src1, src2 ) );
12368 ins_pipe( ialu_cr_reg_reg );
12369 %}
12370
12371 // Long compare reg == zero/reg OR reg != zero/reg
12372 // Just a wrapper for a normal branch, plus the predicate test.
12373 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12374 match(If cmp flags);
12375 effect(USE labl);
12376 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12377 expand %{
12378 jmpCon(cmp,flags,labl); // JEQ or JNE...
12379 %}
12380 %}
12381
12382 // Compare 2 longs and CMOVE longs.
12383 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12384 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12385 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12386 ins_cost(400);
12387 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12388 "CMOV$cmp $dst.hi,$src.hi" %}
12389 opcode(0x0F,0x40);
12390 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12391 ins_pipe( pipe_cmov_reg_long );
12392 %}
12393
12394 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12395 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12396 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12397 ins_cost(500);
12398 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12399 "CMOV$cmp $dst.hi,$src.hi" %}
12400 opcode(0x0F,0x40);
12401 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12402 ins_pipe( pipe_cmov_reg_long );
12403 %}
12404
12405 // Compare 2 longs and CMOVE ints.
12406 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12407 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12408 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12409 ins_cost(200);
12410 format %{ "CMOV$cmp $dst,$src" %}
12411 opcode(0x0F,0x40);
12412 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12413 ins_pipe( pipe_cmov_reg );
12414 %}
12415
12416 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12417 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12418 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12419 ins_cost(250);
12420 format %{ "CMOV$cmp $dst,$src" %}
12421 opcode(0x0F,0x40);
12422 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12423 ins_pipe( pipe_cmov_mem );
12424 %}
12425
12426 // Compare 2 longs and CMOVE ints.
12427 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12428 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12429 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12430 ins_cost(200);
12431 format %{ "CMOV$cmp $dst,$src" %}
12432 opcode(0x0F,0x40);
12433 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12434 ins_pipe( pipe_cmov_reg );
12435 %}
12436
12437 // Compare 2 longs and CMOVE doubles
12438 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12439 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12440 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12441 ins_cost(200);
12442 expand %{
12443 fcmovDPR_regS(cmp,flags,dst,src);
12444 %}
12445 %}
12446
12447 // Compare 2 longs and CMOVE doubles
12448 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12449 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12450 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12451 ins_cost(200);
12452 expand %{
12453 fcmovD_regS(cmp,flags,dst,src);
12454 %}
12455 %}
12456
12457 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12458 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12459 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12460 ins_cost(200);
12461 expand %{
12462 fcmovFPR_regS(cmp,flags,dst,src);
12463 %}
12464 %}
12465
12466 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12467 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12468 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12469 ins_cost(200);
12470 expand %{
12471 fcmovF_regS(cmp,flags,dst,src);
12472 %}
12473 %}
12474
12475 //======
12476 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12477 // Same as cmpL_reg_flags_LEGT except must negate src
12478 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12479 match( Set flags (CmpL src zero ));
12480 effect( TEMP tmp );
12481 ins_cost(300);
12482 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12483 "CMP $tmp,$src.lo\n\t"
12484 "SBB $tmp,$src.hi\n\t" %}
12485 ins_encode( long_cmp_flags3(src, tmp) );
12486 ins_pipe( ialu_reg_reg_long );
12487 %}
12488
12489 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12490 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12491 // requires a commuted test to get the same result.
12492 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12493 match( Set flags (CmpL src1 src2 ));
12494 effect( TEMP tmp );
12495 ins_cost(300);
12496 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12497 "MOV $tmp,$src2.hi\n\t"
12498 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12499 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12500 ins_pipe( ialu_cr_reg_reg );
12501 %}
12502
12503 // Long compares reg < zero/req OR reg >= zero/req.
12504 // Just a wrapper for a normal branch, plus the predicate test
12505 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12506 match(If cmp flags);
12507 effect(USE labl);
12508 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12509 ins_cost(300);
12510 expand %{
12511 jmpCon(cmp,flags,labl); // JGT or JLE...
12512 %}
12513 %}
12514
12515 // Compare 2 longs and CMOVE longs.
12516 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12517 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12518 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12519 ins_cost(400);
12520 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12521 "CMOV$cmp $dst.hi,$src.hi" %}
12522 opcode(0x0F,0x40);
12523 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12524 ins_pipe( pipe_cmov_reg_long );
12525 %}
12526
12527 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12528 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12529 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12530 ins_cost(500);
12531 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12532 "CMOV$cmp $dst.hi,$src.hi+4" %}
12533 opcode(0x0F,0x40);
12534 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12535 ins_pipe( pipe_cmov_reg_long );
12536 %}
12537
12538 // Compare 2 longs and CMOVE ints.
12539 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12540 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12541 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12542 ins_cost(200);
12543 format %{ "CMOV$cmp $dst,$src" %}
12544 opcode(0x0F,0x40);
12545 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12546 ins_pipe( pipe_cmov_reg );
12547 %}
12548
12549 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12550 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12551 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12552 ins_cost(250);
12553 format %{ "CMOV$cmp $dst,$src" %}
12554 opcode(0x0F,0x40);
12555 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12556 ins_pipe( pipe_cmov_mem );
12557 %}
12558
12559 // Compare 2 longs and CMOVE ptrs.
12560 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12561 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12562 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12563 ins_cost(200);
12564 format %{ "CMOV$cmp $dst,$src" %}
12565 opcode(0x0F,0x40);
12566 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12567 ins_pipe( pipe_cmov_reg );
12568 %}
12569
12570 // Compare 2 longs and CMOVE doubles
12571 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12572 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12573 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12574 ins_cost(200);
12575 expand %{
12576 fcmovDPR_regS(cmp,flags,dst,src);
12577 %}
12578 %}
12579
12580 // Compare 2 longs and CMOVE doubles
12581 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12582 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12583 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12584 ins_cost(200);
12585 expand %{
12586 fcmovD_regS(cmp,flags,dst,src);
12587 %}
12588 %}
12589
12590 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12591 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12592 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12593 ins_cost(200);
12594 expand %{
12595 fcmovFPR_regS(cmp,flags,dst,src);
12596 %}
12597 %}
12598
12599
12600 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12601 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12602 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12603 ins_cost(200);
12604 expand %{
12605 fcmovF_regS(cmp,flags,dst,src);
12606 %}
12607 %}
12608
12609
12610 // ============================================================================
12611 // Procedure Call/Return Instructions
12612 // Call Java Static Instruction
12613 // Note: If this code changes, the corresponding ret_addr_offset() and
12614 // compute_padding() functions will have to be adjusted.
12615 instruct CallStaticJavaDirect(method meth) %{
12616 match(CallStaticJava);
12617 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12618 effect(USE meth);
12619
12620 ins_cost(300);
12621 format %{ "CALL,static " %}
12622 opcode(0xE8); /* E8 cd */
12623 ins_encode( pre_call_resets,
12624 Java_Static_Call( meth ),
12625 call_epilog,
12626 post_call_FPU );
12627 ins_pipe( pipe_slow );
12628 ins_alignment(4);
12629 %}
12630
12631 // Call Java Static Instruction (method handle version)
12632 // Note: If this code changes, the corresponding ret_addr_offset() and
12633 // compute_padding() functions will have to be adjusted.
12634 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12635 match(CallStaticJava);
12636 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12637 effect(USE meth);
12638 // EBP is saved by all callees (for interpreter stack correction).
12639 // We use it here for a similar purpose, in {preserve,restore}_SP.
12640
12641 ins_cost(300);
12642 format %{ "CALL,static/MethodHandle " %}
12643 opcode(0xE8); /* E8 cd */
12644 ins_encode( pre_call_resets,
12645 preserve_SP,
12646 Java_Static_Call( meth ),
12647 restore_SP,
12648 call_epilog,
12649 post_call_FPU );
12650 ins_pipe( pipe_slow );
12651 ins_alignment(4);
12652 %}
12653
12654 // Call Java Dynamic Instruction
12655 // Note: If this code changes, the corresponding ret_addr_offset() and
12656 // compute_padding() functions will have to be adjusted.
12657 instruct CallDynamicJavaDirect(method meth) %{
12658 match(CallDynamicJava);
12659 effect(USE meth);
12660
12661 ins_cost(300);
12662 format %{ "MOV EAX,(oop)-1\n\t"
12663 "CALL,dynamic" %}
12664 opcode(0xE8); /* E8 cd */
12665 ins_encode( pre_call_resets,
12666 Java_Dynamic_Call( meth ),
12667 call_epilog,
12668 post_call_FPU );
12669 ins_pipe( pipe_slow );
12670 ins_alignment(4);
12671 %}
12672
12673 // Call Runtime Instruction
12674 instruct CallRuntimeDirect(method meth) %{
12675 match(CallRuntime );
12676 effect(USE meth);
12677
12678 ins_cost(300);
12679 format %{ "CALL,runtime " %}
12680 opcode(0xE8); /* E8 cd */
12681 // Use FFREEs to clear entries in float stack
12682 ins_encode( pre_call_resets,
12683 FFree_Float_Stack_All,
12684 Java_To_Runtime( meth ),
12685 post_call_FPU );
12686 ins_pipe( pipe_slow );
12687 %}
12688
12689 // Call runtime without safepoint
12690 instruct CallLeafDirect(method meth) %{
12691 match(CallLeaf);
12692 effect(USE meth);
12693
12694 ins_cost(300);
12695 format %{ "CALL_LEAF,runtime " %}
12696 opcode(0xE8); /* E8 cd */
12697 ins_encode( pre_call_resets,
12698 FFree_Float_Stack_All,
12699 Java_To_Runtime( meth ),
12700 Verify_FPU_For_Leaf, post_call_FPU );
12701 ins_pipe( pipe_slow );
12702 %}
12703
12704 instruct CallLeafNoFPDirect(method meth) %{
12705 match(CallLeafNoFP);
12706 effect(USE meth);
12707
12708 ins_cost(300);
12709 format %{ "CALL_LEAF_NOFP,runtime " %}
12710 opcode(0xE8); /* E8 cd */
12711 ins_encode(Java_To_Runtime(meth));
12712 ins_pipe( pipe_slow );
12713 %}
12714
12715
12716 // Return Instruction
12717 // Remove the return address & jump to it.
12718 instruct Ret() %{
12719 match(Return);
12720 format %{ "RET" %}
12721 opcode(0xC3);
12722 ins_encode(OpcP);
12723 ins_pipe( pipe_jmp );
12724 %}
12725
12726 // Tail Call; Jump from runtime stub to Java code.
12727 // Also known as an 'interprocedural jump'.
12728 // Target of jump will eventually return to caller.
12729 // TailJump below removes the return address.
12730 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12731 match(TailCall jump_target method_oop );
12732 ins_cost(300);
12733 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12734 opcode(0xFF, 0x4); /* Opcode FF /4 */
12735 ins_encode( OpcP, RegOpc(jump_target) );
12736 ins_pipe( pipe_jmp );
12737 %}
12738
12739
12740 // Tail Jump; remove the return address; jump to target.
12741 // TailCall above leaves the return address around.
12742 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12743 match( TailJump jump_target ex_oop );
12744 ins_cost(300);
12745 format %{ "POP EDX\t# pop return address into dummy\n\t"
12746 "JMP $jump_target " %}
12747 opcode(0xFF, 0x4); /* Opcode FF /4 */
12748 ins_encode( enc_pop_rdx,
12749 OpcP, RegOpc(jump_target) );
12750 ins_pipe( pipe_jmp );
12751 %}
12752
12753 // Create exception oop: created by stack-crawling runtime code.
12754 // Created exception is now available to this handler, and is setup
12755 // just prior to jumping to this handler. No code emitted.
12756 instruct CreateException( eAXRegP ex_oop )
12757 %{
12758 match(Set ex_oop (CreateEx));
12759
12760 size(0);
12761 // use the following format syntax
12762 format %{ "# exception oop is in EAX; no code emitted" %}
12763 ins_encode();
12764 ins_pipe( empty );
12765 %}
12766
12767
12768 // Rethrow exception:
12769 // The exception oop will come in the first argument position.
12770 // Then JUMP (not call) to the rethrow stub code.
12771 instruct RethrowException()
12772 %{
12773 match(Rethrow);
12774
12775 // use the following format syntax
12776 format %{ "JMP rethrow_stub" %}
12777 ins_encode(enc_rethrow);
12778 ins_pipe( pipe_jmp );
12779 %}
12780
12781 // inlined locking and unlocking
12782
12783 instruct cmpFastLockRTM(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eDXRegI scr, rRegI cx1, rRegI cx2) %{
12784 predicate(Compile::current()->use_rtm());
12785 match(Set cr (FastLock object box));
12786 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12787 ins_cost(300);
12788 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12789 ins_encode %{
12790 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12791 $scr$$Register, $cx1$$Register, $cx2$$Register,
12792 _counters, _rtm_counters, _stack_rtm_counters,
12793 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12794 true, ra_->C->profile_rtm());
12795 %}
12796 ins_pipe(pipe_slow);
12797 %}
12798
12799 instruct cmpFastLock(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12800 predicate(!Compile::current()->use_rtm());
12801 match(Set cr (FastLock object box));
12802 effect(TEMP tmp, TEMP scr, USE_KILL box);
12803 ins_cost(300);
12804 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12805 ins_encode %{
12806 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12807 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12808 %}
12809 ins_pipe(pipe_slow);
12810 %}
12811
12812 instruct cmpFastUnlock(eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12813 match(Set cr (FastUnlock object box));
12814 effect(TEMP tmp, USE_KILL box);
12815 ins_cost(300);
12816 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
12817 ins_encode %{
12818 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12819 %}
12820 ins_pipe(pipe_slow);
12821 %}
12822
12823
12824
12825 // ============================================================================
12826 // Safepoint Instruction
12827 instruct safePoint_poll(eFlagsReg cr) %{
12828 match(SafePoint);
12829 effect(KILL cr);
12830
12831 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12832 // On SPARC that might be acceptable as we can generate the address with
12833 // just a sethi, saving an or. By polling at offset 0 we can end up
12834 // putting additional pressure on the index-0 in the D$. Because of
12835 // alignment (just like the situation at hand) the lower indices tend
12836 // to see more traffic. It'd be better to change the polling address
12837 // to offset 0 of the last $line in the polling page.
12838
12839 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
12840 ins_cost(125);
12841 size(6) ;
12842 ins_encode( Safepoint_Poll() );
12843 ins_pipe( ialu_reg_mem );
12844 %}
12845
12846
12847 // ============================================================================
12848 // This name is KNOWN by the ADLC and cannot be changed.
12849 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12850 // for this guy.
12851 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
12852 match(Set dst (ThreadLocal));
12853 effect(DEF dst, KILL cr);
12854
12855 format %{ "MOV $dst, Thread::current()" %}
12856 ins_encode %{
12857 Register dstReg = as_Register($dst$$reg);
12858 __ get_thread(dstReg);
12859 %}
12860 ins_pipe( ialu_reg_fat );
12861 %}
12862
12863
12864
12865 //----------PEEPHOLE RULES-----------------------------------------------------
12866 // These must follow all instruction definitions as they use the names
12867 // defined in the instructions definitions.
12868 //
12869 // peepmatch ( root_instr_name [preceding_instruction]* );
12870 //
12871 // peepconstraint %{
12872 // (instruction_number.operand_name relational_op instruction_number.operand_name
12873 // [, ...] );
12874 // // instruction numbers are zero-based using left to right order in peepmatch
12875 //
12876 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12877 // // provide an instruction_number.operand_name for each operand that appears
12878 // // in the replacement instruction's match rule
12879 //
12880 // ---------VM FLAGS---------------------------------------------------------
12881 //
12882 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12883 //
12884 // Each peephole rule is given an identifying number starting with zero and
12885 // increasing by one in the order seen by the parser. An individual peephole
12886 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12887 // on the command-line.
12888 //
12889 // ---------CURRENT LIMITATIONS----------------------------------------------
12890 //
12891 // Only match adjacent instructions in same basic block
12892 // Only equality constraints
12893 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12894 // Only one replacement instruction
12895 //
12896 // ---------EXAMPLE----------------------------------------------------------
12897 //
12898 // // pertinent parts of existing instructions in architecture description
12899 // instruct movI(rRegI dst, rRegI src) %{
12900 // match(Set dst (CopyI src));
12901 // %}
12902 //
12903 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
12904 // match(Set dst (AddI dst src));
12905 // effect(KILL cr);
12906 // %}
12907 //
12908 // // Change (inc mov) to lea
12909 // peephole %{
12910 // // increment preceeded by register-register move
12911 // peepmatch ( incI_eReg movI );
12912 // // require that the destination register of the increment
12913 // // match the destination register of the move
12914 // peepconstraint ( 0.dst == 1.dst );
12915 // // construct a replacement instruction that sets
12916 // // the destination to ( move's source register + one )
12917 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12918 // %}
12919 //
12920 // Implementation no longer uses movX instructions since
12921 // machine-independent system no longer uses CopyX nodes.
12922 //
12923 // peephole %{
12924 // peepmatch ( incI_eReg movI );
12925 // peepconstraint ( 0.dst == 1.dst );
12926 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12927 // %}
12928 //
12929 // peephole %{
12930 // peepmatch ( decI_eReg movI );
12931 // peepconstraint ( 0.dst == 1.dst );
12932 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12933 // %}
12934 //
12935 // peephole %{
12936 // peepmatch ( addI_eReg_imm movI );
12937 // peepconstraint ( 0.dst == 1.dst );
12938 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12939 // %}
12940 //
12941 // peephole %{
12942 // peepmatch ( addP_eReg_imm movP );
12943 // peepconstraint ( 0.dst == 1.dst );
12944 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12945 // %}
12946
12947 // // Change load of spilled value to only a spill
12948 // instruct storeI(memory mem, rRegI src) %{
12949 // match(Set mem (StoreI mem src));
12950 // %}
12951 //
12952 // instruct loadI(rRegI dst, memory mem) %{
12953 // match(Set dst (LoadI mem));
12954 // %}
12955 //
12956 peephole %{
12957 peepmatch ( loadI storeI );
12958 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12959 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12960 %}
12961
12962 //----------SMARTSPILL RULES---------------------------------------------------
12963 // These must follow all instruction definitions as they use the names
12964 // defined in the instructions definitions.