1 /*
   2  * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2012, 2017, SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/assembler.inline.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "compiler/disassembler.hpp"
  30 #include "memory/resourceArea.hpp"
  31 #include "prims/jvm.h"
  32 #include "runtime/java.hpp"
  33 #include "runtime/os.hpp"
  34 #include "runtime/stubCodeGenerator.hpp"
  35 #include "utilities/defaultStream.hpp"
  36 #include "utilities/globalDefinitions.hpp"
  37 #include "vm_version_ppc.hpp"
  38 
  39 # include <sys/sysinfo.h>
  40 
  41 bool VM_Version::_is_determine_features_test_running = false;
  42 uint64_t VM_Version::_dscr_val = 0;
  43 
  44 #define MSG(flag)   \
  45   if (flag && !FLAG_IS_DEFAULT(flag))                                  \
  46       jio_fprintf(defaultStream::error_stream(),                       \
  47                   "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
  48                   "         -XX:+" #flag " will be disabled!\n");
  49 
  50 void VM_Version::initialize() {
  51 
  52   // Test which instructions are supported and measure cache line size.
  53   determine_features();
  54 
  55   // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
  56   if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
  57     if (VM_Version::has_lqarx()) {
  58       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
  59     } else if (VM_Version::has_popcntw()) {
  60       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
  61     } else if (VM_Version::has_cmpb()) {
  62       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
  63     } else if (VM_Version::has_popcntb()) {
  64       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
  65     } else {
  66       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
  67     }
  68   }
  69 
  70   bool PowerArchitecturePPC64_ok = false;
  71   switch (PowerArchitecturePPC64) {
  72     case 8: if (!VM_Version::has_lqarx()  ) break;
  73     case 7: if (!VM_Version::has_popcntw()) break;
  74     case 6: if (!VM_Version::has_cmpb()   ) break;
  75     case 5: if (!VM_Version::has_popcntb()) break;
  76     case 0: PowerArchitecturePPC64_ok = true; break;
  77     default: break;
  78   }
  79   guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
  80             UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
  81 
  82   // Power 8: Configure Data Stream Control Register.
  83   if (has_mfdscr()) {
  84     config_dscr();
  85   }
  86 
  87   if (!UseSIGTRAP) {
  88     MSG(TrapBasedICMissChecks);
  89     MSG(TrapBasedNotEntrantChecks);
  90     MSG(TrapBasedNullChecks);
  91     FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
  92     FLAG_SET_ERGO(bool, TrapBasedNullChecks,       false);
  93     FLAG_SET_ERGO(bool, TrapBasedICMissChecks,     false);
  94   }
  95 
  96 #ifdef COMPILER2
  97   if (!UseSIGTRAP) {
  98     MSG(TrapBasedRangeChecks);
  99     FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
 100   }
 101 
 102   // On Power6 test for section size.
 103   if (PowerArchitecturePPC64 == 6) {
 104     determine_section_size();
 105   // TODO: PPC port } else {
 106   // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
 107   }
 108 
 109   MaxVectorSize = 8;
 110 #endif
 111 
 112   // Create and print feature-string.
 113   char buf[(num_features+1) * 16]; // Max 16 chars per feature.
 114   jio_snprintf(buf, sizeof(buf),
 115                "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 116                (has_fsqrt()   ? " fsqrt"   : ""),
 117                (has_isel()    ? " isel"    : ""),
 118                (has_lxarxeh() ? " lxarxeh" : ""),
 119                (has_cmpb()    ? " cmpb"    : ""),
 120                //(has_mftgpr()? " mftgpr"  : ""),
 121                (has_popcntb() ? " popcntb" : ""),
 122                (has_popcntw() ? " popcntw" : ""),
 123                (has_fcfids()  ? " fcfids"  : ""),
 124                (has_vand()    ? " vand"    : ""),
 125                (has_lqarx()   ? " lqarx"   : ""),
 126                (has_vcipher() ? " aes"     : ""),
 127                (has_vpmsumb() ? " vpmsumb" : ""),
 128                (has_tcheck()  ? " tcheck"  : ""),
 129                (has_mfdscr()  ? " mfdscr"  : ""),
 130                (has_vsx()     ? " vsx"     : ""),
 131                (has_ldbrx()   ? " ldbrx"   : ""),
 132                (has_stdbrx()  ? " stdbrx"  : "")
 133                // Make sure number of %s matches num_features!
 134               );
 135   _features_string = os::strdup(buf);
 136   if (Verbose) {
 137     print_features();
 138   }
 139 
 140   // PPC64 supports 8-byte compare-exchange operations (see
 141   // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
 142   // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
 143   _supports_cx8 = true;
 144 
 145   // Used by C1.
 146   _supports_atomic_getset4 = true;
 147   _supports_atomic_getadd4 = true;
 148   _supports_atomic_getset8 = true;
 149   _supports_atomic_getadd8 = true;
 150 
 151   UseSSE = 0; // Only on x86 and x64
 152 
 153   intx cache_line_size = L1_data_cache_line_size();
 154 
 155   if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
 156 
 157   if (AllocatePrefetchStyle == 4) {
 158     AllocatePrefetchStepSize = cache_line_size; // Need exact value.
 159     if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
 160     if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
 161   } else {
 162     if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
 163     if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
 164     if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
 165   }
 166 
 167   assert(AllocatePrefetchLines > 0, "invalid value");
 168   if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
 169     AllocatePrefetchLines = 1; // Conservative value.
 170   }
 171 
 172   if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
 173     AllocatePrefetchStyle = 1; // Fall back if inappropriate.
 174   }
 175 
 176   assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
 177 
 178   // If defined(VM_LITTLE_ENDIAN) and running on Power8 or newer hardware,
 179   // the implementation uses the vector instructions available with Power8.
 180   // In all other cases, the implementation uses only generally available instructions.
 181   if (!UseCRC32Intrinsics) {
 182     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 183       FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
 184     }
 185   }
 186 
 187   // Implementation does not use any of the vector instructions available with Power8.
 188   // Their exploitation is still pending (aka "work in progress").
 189   if (!UseCRC32CIntrinsics) {
 190     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 191       FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
 192     }
 193   }
 194 
 195   // TODO: Provide implementation.
 196   if (UseAdler32Intrinsics) {
 197     warning("Adler32Intrinsics not available on this CPU.");
 198     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
 199   }
 200 
 201   // The AES intrinsic stubs require AES instruction support.
 202 #if defined(VM_LITTLE_ENDIAN)
 203   if (has_vcipher()) {
 204     if (FLAG_IS_DEFAULT(UseAES)) {
 205       UseAES = true;
 206     }
 207   } else if (UseAES) {
 208     if (!FLAG_IS_DEFAULT(UseAES))
 209       warning("AES instructions are not available on this CPU");
 210     FLAG_SET_DEFAULT(UseAES, false);
 211   }
 212 
 213   if (UseAES && has_vcipher()) {
 214     if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 215       UseAESIntrinsics = true;
 216     }
 217   } else if (UseAESIntrinsics) {
 218     if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
 219       warning("AES intrinsics are not available on this CPU");
 220     FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 221   }
 222 
 223 #else
 224   if (UseAES) {
 225     warning("AES instructions are not available on this CPU");
 226     FLAG_SET_DEFAULT(UseAES, false);
 227   }
 228   if (UseAESIntrinsics) {
 229     if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
 230       warning("AES intrinsics are not available on this CPU");
 231     FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 232   }
 233 #endif
 234 
 235   if (UseAESCTRIntrinsics) {
 236     warning("AES/CTR intrinsics are not available on this CPU");
 237     FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 238   }
 239 
 240   if (UseGHASHIntrinsics) {
 241     warning("GHASH intrinsics are not available on this CPU");
 242     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 243   }
 244 
 245   if (FLAG_IS_DEFAULT(UseFMA)) {
 246     FLAG_SET_DEFAULT(UseFMA, true);
 247   }
 248 
 249   if (UseSHA) {
 250     warning("SHA instructions are not available on this CPU");
 251     FLAG_SET_DEFAULT(UseSHA, false);
 252   }
 253   if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
 254     warning("SHA intrinsics are not available on this CPU");
 255     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 256     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 257     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 258   }
 259 
 260   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
 261     UseMultiplyToLenIntrinsic = true;
 262   }
 263   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
 264     UseMontgomeryMultiplyIntrinsic = true;
 265   }
 266   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
 267     UseMontgomerySquareIntrinsic = true;
 268   }
 269 
 270   if (UseVectorizedMismatchIntrinsic) {
 271     warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
 272     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
 273   }
 274 
 275 
 276   // Adjust RTM (Restricted Transactional Memory) flags.
 277   if (UseRTMLocking) {
 278     // If CPU or OS are too old:
 279     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 280     // setting during arguments processing. See use_biased_locking().
 281     // VM_Version_init() is executed after UseBiasedLocking is used
 282     // in Thread::allocate().
 283     if (!has_tcheck()) {
 284       vm_exit_during_initialization("RTM instructions are not available on this CPU");
 285     }
 286     bool os_too_old = true;
 287 #ifdef AIX
 288     // Actually, this is supported since AIX 7.1.. Unfortunately, this first
 289     // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
 290     // The Java property os.version, which is used in RTM tests to decide
 291     // whether the feature is available, only knows major and minor versions.
 292     // We don't want to change this property, as user code might depend on it.
 293     // So the tests can not check on subversion 3.30, and we only enable RTM
 294     // with AIX 7.2.
 295     if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
 296       os_too_old = false;
 297     }
 298 #endif
 299 #ifdef LINUX
 300     // At least Linux kernel 4.2, as the problematic behavior of syscalls
 301     // being called in the middle of a transaction has been addressed.
 302     // Please, refer to commit b4b56f9ecab40f3b4ef53e130c9f6663be491894
 303     // in Linux kernel source tree: https://goo.gl/Kc5i7A
 304     if (os::Linux::os_version_is_known()) {
 305       if (os::Linux::os_version() >= 0x040200)
 306         os_too_old = false;
 307     } else {
 308       vm_exit_during_initialization("RTM can not be enabled: kernel version is unknown.");
 309     }
 310 #endif
 311     if (os_too_old) {
 312       vm_exit_during_initialization("RTM is not supported on this OS version.");
 313     }
 314   }
 315 
 316   if (UseRTMLocking) {
 317 #if INCLUDE_RTM_OPT
 318     if (!UnlockExperimentalVMOptions) {
 319       vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
 320                                     "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
 321     } else {
 322       warning("UseRTMLocking is only available as experimental option on this platform.");
 323     }
 324     if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
 325       // RTM locking should be used only for applications with
 326       // high lock contention. For now we do not use it by default.
 327       vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
 328     }
 329     if (!is_power_of_2(RTMTotalCountIncrRate)) {
 330       warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
 331       FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
 332     }
 333     if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
 334       warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
 335       FLAG_SET_DEFAULT(RTMAbortRatio, 50);
 336     }
 337     if (RTMSpinLoopCount < 0) {
 338       warning("RTMSpinLoopCount must not be a negative value, resetting it to 0");
 339       FLAG_SET_DEFAULT(RTMSpinLoopCount, 0);
 340     }
 341 #else
 342     // Only C2 does RTM locking optimization.
 343     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 344     // setting during arguments processing. See use_biased_locking().
 345     vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
 346 #endif
 347   } else { // !UseRTMLocking
 348     if (UseRTMForStackLocks) {
 349       if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
 350         warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
 351       }
 352       FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
 353     }
 354     if (UseRTMDeopt) {
 355       FLAG_SET_DEFAULT(UseRTMDeopt, false);
 356     }
 357     if (PrintPreciseRTMLockingStatistics) {
 358       FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
 359     }
 360   }
 361 
 362   // This machine allows unaligned memory accesses
 363   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
 364     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
 365   }
 366 }
 367 
 368 bool VM_Version::use_biased_locking() {
 369 #if INCLUDE_RTM_OPT
 370   // RTM locking is most useful when there is high lock contention and
 371   // low data contention. With high lock contention the lock is usually
 372   // inflated and biased locking is not suitable for that case.
 373   // RTM locking code requires that biased locking is off.
 374   // Note: we can't switch off UseBiasedLocking in get_processor_features()
 375   // because it is used by Thread::allocate() which is called before
 376   // VM_Version::initialize().
 377   if (UseRTMLocking && UseBiasedLocking) {
 378     if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
 379       FLAG_SET_DEFAULT(UseBiasedLocking, false);
 380     } else {
 381       warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
 382       UseBiasedLocking = false;
 383     }
 384   }
 385 #endif
 386   return UseBiasedLocking;
 387 }
 388 
 389 void VM_Version::print_features() {
 390   tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
 391 }
 392 
 393 #ifdef COMPILER2
 394 // Determine section size on power6: If section size is 8 instructions,
 395 // there should be a difference between the two testloops of ~15 %. If
 396 // no difference is detected the section is assumed to be 32 instructions.
 397 void VM_Version::determine_section_size() {
 398 
 399   int unroll = 80;
 400 
 401   const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
 402 
 403   // Allocate space for the code.
 404   ResourceMark rm;
 405   CodeBuffer cb("detect_section_size", code_size, 0);
 406   MacroAssembler* a = new MacroAssembler(&cb);
 407 
 408   uint32_t *code = (uint32_t *)a->pc();
 409   // Emit code.
 410   void (*test1)() = (void(*)())(void *)a->function_entry();
 411 
 412   Label l1;
 413 
 414   a->li(R4, 1);
 415   a->sldi(R4, R4, 28);
 416   a->b(l1);
 417   a->align(CodeEntryAlignment);
 418 
 419   a->bind(l1);
 420 
 421   for (int i = 0; i < unroll; i++) {
 422     // Schleife 1
 423     // ------- sector 0 ------------
 424     // ;; 0
 425     a->nop();                   // 1
 426     a->fpnop0();                // 2
 427     a->fpnop1();                // 3
 428     a->addi(R4,R4, -1); // 4
 429 
 430     // ;;  1
 431     a->nop();                   // 5
 432     a->fmr(F6, F6);             // 6
 433     a->fmr(F7, F7);             // 7
 434     a->endgroup();              // 8
 435     // ------- sector 8 ------------
 436 
 437     // ;;  2
 438     a->nop();                   // 9
 439     a->nop();                   // 10
 440     a->fmr(F8, F8);             // 11
 441     a->fmr(F9, F9);             // 12
 442 
 443     // ;;  3
 444     a->nop();                   // 13
 445     a->fmr(F10, F10);           // 14
 446     a->fmr(F11, F11);           // 15
 447     a->endgroup();              // 16
 448     // -------- sector 16 -------------
 449 
 450     // ;;  4
 451     a->nop();                   // 17
 452     a->nop();                   // 18
 453     a->fmr(F15, F15);           // 19
 454     a->fmr(F16, F16);           // 20
 455 
 456     // ;;  5
 457     a->nop();                   // 21
 458     a->fmr(F17, F17);           // 22
 459     a->fmr(F18, F18);           // 23
 460     a->endgroup();              // 24
 461     // ------- sector 24  ------------
 462 
 463     // ;;  6
 464     a->nop();                   // 25
 465     a->nop();                   // 26
 466     a->fmr(F19, F19);           // 27
 467     a->fmr(F20, F20);           // 28
 468 
 469     // ;;  7
 470     a->nop();                   // 29
 471     a->fmr(F21, F21);           // 30
 472     a->fmr(F22, F22);           // 31
 473     a->brnop0();                // 32
 474 
 475     // ------- sector 32 ------------
 476   }
 477 
 478   // ;; 8
 479   a->cmpdi(CCR0, R4, unroll);   // 33
 480   a->bge(CCR0, l1);             // 34
 481   a->blr();
 482 
 483   // Emit code.
 484   void (*test2)() = (void(*)())(void *)a->function_entry();
 485   // uint32_t *code = (uint32_t *)a->pc();
 486 
 487   Label l2;
 488 
 489   a->li(R4, 1);
 490   a->sldi(R4, R4, 28);
 491   a->b(l2);
 492   a->align(CodeEntryAlignment);
 493 
 494   a->bind(l2);
 495 
 496   for (int i = 0; i < unroll; i++) {
 497     // Schleife 2
 498     // ------- sector 0 ------------
 499     // ;; 0
 500     a->brnop0();                  // 1
 501     a->nop();                     // 2
 502     //a->cmpdi(CCR0, R4, unroll);
 503     a->fpnop0();                  // 3
 504     a->fpnop1();                  // 4
 505     a->addi(R4,R4, -1);           // 5
 506 
 507     // ;; 1
 508 
 509     a->nop();                     // 6
 510     a->fmr(F6, F6);               // 7
 511     a->fmr(F7, F7);               // 8
 512     // ------- sector 8 ---------------
 513 
 514     // ;; 2
 515     a->endgroup();                // 9
 516 
 517     // ;; 3
 518     a->nop();                     // 10
 519     a->nop();                     // 11
 520     a->fmr(F8, F8);               // 12
 521 
 522     // ;; 4
 523     a->fmr(F9, F9);               // 13
 524     a->nop();                     // 14
 525     a->fmr(F10, F10);             // 15
 526 
 527     // ;; 5
 528     a->fmr(F11, F11);             // 16
 529     // -------- sector 16 -------------
 530 
 531     // ;; 6
 532     a->endgroup();                // 17
 533 
 534     // ;; 7
 535     a->nop();                     // 18
 536     a->nop();                     // 19
 537     a->fmr(F15, F15);             // 20
 538 
 539     // ;; 8
 540     a->fmr(F16, F16);             // 21
 541     a->nop();                     // 22
 542     a->fmr(F17, F17);             // 23
 543 
 544     // ;; 9
 545     a->fmr(F18, F18);             // 24
 546     // -------- sector 24 -------------
 547 
 548     // ;; 10
 549     a->endgroup();                // 25
 550 
 551     // ;; 11
 552     a->nop();                     // 26
 553     a->nop();                     // 27
 554     a->fmr(F19, F19);             // 28
 555 
 556     // ;; 12
 557     a->fmr(F20, F20);             // 29
 558     a->nop();                     // 30
 559     a->fmr(F21, F21);             // 31
 560 
 561     // ;; 13
 562     a->fmr(F22, F22);             // 32
 563   }
 564 
 565   // -------- sector 32 -------------
 566   // ;; 14
 567   a->cmpdi(CCR0, R4, unroll); // 33
 568   a->bge(CCR0, l2);           // 34
 569 
 570   a->blr();
 571   uint32_t *code_end = (uint32_t *)a->pc();
 572   a->flush();
 573 
 574   double loop1_seconds,loop2_seconds, rel_diff;
 575   uint64_t start1, stop1;
 576 
 577   start1 = os::current_thread_cpu_time(false);
 578   (*test1)();
 579   stop1 = os::current_thread_cpu_time(false);
 580   loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
 581 
 582 
 583   start1 = os::current_thread_cpu_time(false);
 584   (*test2)();
 585   stop1 = os::current_thread_cpu_time(false);
 586 
 587   loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
 588 
 589   rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
 590 
 591   if (PrintAssembly) {
 592     ttyLocker ttyl;
 593     tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
 594     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 595     tty->print_cr("Time loop1 :%f", loop1_seconds);
 596     tty->print_cr("Time loop2 :%f", loop2_seconds);
 597     tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
 598 
 599     if (rel_diff > 12.0) {
 600       tty->print_cr("Section Size 8 Instructions");
 601     } else{
 602       tty->print_cr("Section Size 32 Instructions or Power5");
 603     }
 604   }
 605 
 606 #if 0 // TODO: PPC port
 607   // Set sector size (if not set explicitly).
 608   if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
 609     if (rel_diff > 12.0) {
 610       PdScheduling::power6SectorSize = 0x20;
 611     } else {
 612       PdScheduling::power6SectorSize = 0x80;
 613     }
 614   } else if (Power6SectorSize128PPC64) {
 615     PdScheduling::power6SectorSize = 0x80;
 616   } else {
 617     PdScheduling::power6SectorSize = 0x20;
 618   }
 619 #endif
 620   if (UsePower6SchedulerPPC64) Unimplemented();
 621 }
 622 #endif // COMPILER2
 623 
 624 void VM_Version::determine_features() {
 625 #if defined(ABI_ELFv2)
 626   // 1 InstWord per call for the blr instruction.
 627   const int code_size = (num_features+1+2*1)*BytesPerInstWord;
 628 #else
 629   // 7 InstWords for each call (function descriptor + blr instruction).
 630   const int code_size = (num_features+1+2*7)*BytesPerInstWord;
 631 #endif
 632   int features = 0;
 633 
 634   // create test area
 635   enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
 636   char test_area[BUFFER_SIZE];
 637   char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
 638 
 639   // Allocate space for the code.
 640   ResourceMark rm;
 641   CodeBuffer cb("detect_cpu_features", code_size, 0);
 642   MacroAssembler* a = new MacroAssembler(&cb);
 643 
 644   // Must be set to true so we can generate the test code.
 645   _features = VM_Version::all_features_m;
 646 
 647   // Emit code.
 648   void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
 649   uint32_t *code = (uint32_t *)a->pc();
 650   // Don't use R0 in ldarx.
 651   // Keep R3_ARG1 unmodified, it contains &field (see below).
 652   // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
 653   a->fsqrt(F3, F4);                            // code[0]  -> fsqrt_m
 654   a->fsqrts(F3, F4);                           // code[1]  -> fsqrts_m
 655   a->isel(R7, R5, R6, 0);                      // code[2]  -> isel_m
 656   a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3]  -> lxarx_m
 657   a->cmpb(R7, R5, R6);                         // code[4]  -> cmpb
 658   a->popcntb(R7, R5);                          // code[5]  -> popcntb
 659   a->popcntw(R7, R5);                          // code[6]  -> popcntw
 660   a->fcfids(F3, F4);                           // code[7]  -> fcfids
 661   a->vand(VR0, VR0, VR0);                      // code[8]  -> vand
 662   // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
 663   a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9]  -> lqarx_m
 664   a->vcipher(VR0, VR1, VR2);                   // code[10] -> vcipher
 665   a->vpmsumb(VR0, VR1, VR2);                   // code[11] -> vpmsumb
 666   a->tcheck(0);                                // code[12] -> tcheck
 667   a->mfdscr(R0);                               // code[13] -> mfdscr
 668   a->lxvd2x(VSR0, R3_ARG1);                    // code[14] -> vsx
 669   a->ldbrx(R7, R3_ARG1, R4_ARG2);              // code[15] -> ldbrx
 670   a->stdbrx(R7, R3_ARG1, R4_ARG2);             // code[16] -> stdbrx
 671   a->blr();
 672 
 673   // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
 674   void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
 675   a->dcbz(R3_ARG1); // R3_ARG1 = addr
 676   a->blr();
 677 
 678   uint32_t *code_end = (uint32_t *)a->pc();
 679   a->flush();
 680   _features = VM_Version::unknown_m;
 681 
 682   // Print the detection code.
 683   if (PrintAssembly) {
 684     ttyLocker ttyl;
 685     tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
 686     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 687   }
 688 
 689   // Measure cache line size.
 690   memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
 691   (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
 692   int count = 0; // count zeroed bytes
 693   for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
 694   guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
 695   _L1_data_cache_line_size = count;
 696 
 697   // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
 698   VM_Version::_is_determine_features_test_running = true;
 699   // We must align the first argument to 16 bytes because of the lqarx check.
 700   (*test)(align_up(mid_of_test_area, 16), (uint64_t)0);
 701   VM_Version::_is_determine_features_test_running = false;
 702 
 703   // determine which instructions are legal.
 704   int feature_cntr = 0;
 705   if (code[feature_cntr++]) features |= fsqrt_m;
 706   if (code[feature_cntr++]) features |= fsqrts_m;
 707   if (code[feature_cntr++]) features |= isel_m;
 708   if (code[feature_cntr++]) features |= lxarxeh_m;
 709   if (code[feature_cntr++]) features |= cmpb_m;
 710   if (code[feature_cntr++]) features |= popcntb_m;
 711   if (code[feature_cntr++]) features |= popcntw_m;
 712   if (code[feature_cntr++]) features |= fcfids_m;
 713   if (code[feature_cntr++]) features |= vand_m;
 714   if (code[feature_cntr++]) features |= lqarx_m;
 715   if (code[feature_cntr++]) features |= vcipher_m;
 716   if (code[feature_cntr++]) features |= vpmsumb_m;
 717   if (code[feature_cntr++]) features |= tcheck_m;
 718   if (code[feature_cntr++]) features |= mfdscr_m;
 719   if (code[feature_cntr++]) features |= vsx_m;
 720   if (code[feature_cntr++]) features |= ldbrx_m;
 721   if (code[feature_cntr++]) features |= stdbrx_m;
 722 
 723   // Print the detection code.
 724   if (PrintAssembly) {
 725     ttyLocker ttyl;
 726     tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
 727     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 728   }
 729 
 730   _features = features;
 731 }
 732 
 733 // Power 8: Configure Data Stream Control Register.
 734 void VM_Version::config_dscr() {
 735   // 7 InstWords for each call (function descriptor + blr instruction).
 736   const int code_size = (2+2*7)*BytesPerInstWord;
 737 
 738   // Allocate space for the code.
 739   ResourceMark rm;
 740   CodeBuffer cb("config_dscr", code_size, 0);
 741   MacroAssembler* a = new MacroAssembler(&cb);
 742 
 743   // Emit code.
 744   uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
 745   uint32_t *code = (uint32_t *)a->pc();
 746   a->mfdscr(R3);
 747   a->blr();
 748 
 749   void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
 750   a->mtdscr(R3);
 751   a->blr();
 752 
 753   uint32_t *code_end = (uint32_t *)a->pc();
 754   a->flush();
 755 
 756   // Print the detection code.
 757   if (PrintAssembly) {
 758     ttyLocker ttyl;
 759     tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
 760     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 761   }
 762 
 763   // Apply the configuration if needed.
 764   _dscr_val = (*get_dscr)();
 765   if (Verbose) {
 766     tty->print_cr("dscr value was 0x%lx" , _dscr_val);
 767   }
 768   bool change_requested = false;
 769   if (DSCR_PPC64 != (uintx)-1) {
 770     _dscr_val = DSCR_PPC64;
 771     change_requested = true;
 772   }
 773   if (DSCR_DPFD_PPC64 <= 7) {
 774     uint64_t mask = 0x7;
 775     if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
 776       _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
 777       change_requested = true;
 778     }
 779   }
 780   if (DSCR_URG_PPC64 <= 7) {
 781     uint64_t mask = 0x7 << 6;
 782     if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
 783       _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
 784       change_requested = true;
 785     }
 786   }
 787   if (change_requested) {
 788     (*set_dscr)(_dscr_val);
 789     if (Verbose) {
 790       tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
 791     }
 792   }
 793 }
 794 
 795 static uint64_t saved_features = 0;
 796 
 797 void VM_Version::allow_all() {
 798   saved_features = _features;
 799   _features      = all_features_m;
 800 }
 801 
 802 void VM_Version::revert() {
 803   _features = saved_features;
 804 }