1 /*
2 * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #include "precompiled.hpp"
26 #include "compiler/compileLog.hpp"
27 #include "compiler/oopMap.hpp"
28 #include "memory/allocation.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "opto/addnode.hpp"
31 #include "opto/block.hpp"
32 #include "opto/callnode.hpp"
33 #include "opto/cfgnode.hpp"
34 #include "opto/chaitin.hpp"
35 #include "opto/coalesce.hpp"
36 #include "opto/connode.hpp"
37 #include "opto/idealGraphPrinter.hpp"
38 #include "opto/indexSet.hpp"
39 #include "opto/machnode.hpp"
40 #include "opto/memnode.hpp"
41 #include "opto/movenode.hpp"
42 #include "opto/opcodes.hpp"
43 #include "opto/rootnode.hpp"
44
45 #ifndef PRODUCT
46 void LRG::dump() const {
47 ttyLocker ttyl;
48 tty->print("%d ",num_regs());
49 _mask.dump();
50 if( _msize_valid ) {
51 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size);
52 else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size());
53 } else {
54 tty->print(", #?(%d) ",_mask.Size());
55 }
56
57 tty->print("EffDeg: ");
58 if( _degree_valid ) tty->print( "%d ", _eff_degree );
59 else tty->print("? ");
60
61 if( is_multidef() ) {
62 tty->print("MultiDef ");
63 if (_defs != NULL) {
64 tty->print("(");
65 for (int i = 0; i < _defs->length(); i++) {
66 tty->print("N%d ", _defs->at(i)->_idx);
67 }
68 tty->print(") ");
69 }
70 }
71 else if( _def == 0 ) tty->print("Dead ");
72 else tty->print("Def: N%d ",_def->_idx);
73
74 tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score());
75 // Flags
76 if( _is_oop ) tty->print("Oop ");
77 if( _is_float ) tty->print("Float ");
78 if( _is_vector ) tty->print("Vector ");
79 if( _was_spilled1 ) tty->print("Spilled ");
80 if( _was_spilled2 ) tty->print("Spilled2 ");
81 if( _direct_conflict ) tty->print("Direct_conflict ");
82 if( _fat_proj ) tty->print("Fat ");
83 if( _was_lo ) tty->print("Lo ");
84 if( _has_copy ) tty->print("Copy ");
85 if( _at_risk ) tty->print("Risk ");
86
87 if( _must_spill ) tty->print("Must_spill ");
88 if( _is_bound ) tty->print("Bound ");
89 if( _msize_valid ) {
90 if( _degree_valid && lo_degree() ) tty->print("Trivial ");
91 }
92
93 tty->cr();
94 }
95 #endif
96
97 // Compute score from cost and area. Low score is best to spill.
98 static double raw_score( double cost, double area ) {
99 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5;
100 }
101
102 double LRG::score() const {
103 // Scale _area by RegisterCostAreaRatio/64K then subtract from cost.
104 // Bigger area lowers score, encourages spilling this live range.
105 // Bigger cost raise score, prevents spilling this live range.
106 // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer
107 // to turn a divide by a constant into a multiply by the reciprical).
108 double score = raw_score( _cost, _area);
109
110 // Account for area. Basically, LRGs covering large areas are better
111 // to spill because more other LRGs get freed up.
112 if( _area == 0.0 ) // No area? Then no progress to spill
113 return 1e35;
114
115 if( _was_spilled2 ) // If spilled once before, we are unlikely
116 return score + 1e30; // to make progress again.
117
118 if( _cost >= _area*3.0 ) // Tiny area relative to cost
119 return score + 1e17; // Probably no progress to spill
120
121 if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost
122 return score + 1e10; // Likely no progress to spill
123
124 return score;
125 }
126
127 #define NUMBUCKS 3
128
129 // Straight out of Tarjan's union-find algorithm
130 uint LiveRangeMap::find_compress(uint lrg) {
131 uint cur = lrg;
132 uint next = _uf_map.at(cur);
133 while (next != cur) { // Scan chain of equivalences
134 assert( next < cur, "always union smaller");
135 cur = next; // until find a fixed-point
136 next = _uf_map.at(cur);
137 }
138
139 // Core of union-find algorithm: update chain of
140 // equivalences to be equal to the root.
141 while (lrg != next) {
142 uint tmp = _uf_map.at(lrg);
143 _uf_map.at_put(lrg, next);
144 lrg = tmp;
145 }
146 return lrg;
147 }
148
149 // Reset the Union-Find map to identity
150 void LiveRangeMap::reset_uf_map(uint max_lrg_id) {
151 _max_lrg_id= max_lrg_id;
152 // Force the Union-Find mapping to be at least this large
153 _uf_map.at_put_grow(_max_lrg_id, 0);
154 // Initialize it to be the ID mapping.
155 for (uint i = 0; i < _max_lrg_id; ++i) {
156 _uf_map.at_put(i, i);
157 }
158 }
159
160 // Make all Nodes map directly to their final live range; no need for
161 // the Union-Find mapping after this call.
162 void LiveRangeMap::compress_uf_map_for_nodes() {
163 // For all Nodes, compress mapping
164 uint unique = _names.length();
165 for (uint i = 0; i < unique; ++i) {
166 uint lrg = _names.at(i);
167 uint compressed_lrg = find(lrg);
168 if (lrg != compressed_lrg) {
169 _names.at_put(i, compressed_lrg);
170 }
171 }
172 }
173
174 // Like Find above, but no path compress, so bad asymptotic behavior
175 uint LiveRangeMap::find_const(uint lrg) const {
176 if (!lrg) {
177 return lrg; // Ignore the zero LRG
178 }
179
180 // Off the end? This happens during debugging dumps when you got
181 // brand new live ranges but have not told the allocator yet.
182 if (lrg >= _max_lrg_id) {
183 return lrg;
184 }
185
186 uint next = _uf_map.at(lrg);
187 while (next != lrg) { // Scan chain of equivalences
188 assert(next < lrg, "always union smaller");
189 lrg = next; // until find a fixed-point
190 next = _uf_map.at(lrg);
191 }
192 return next;
193 }
194
195 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher, bool scheduling_info_generated)
196 : PhaseRegAlloc(unique, cfg, matcher,
197 #ifndef PRODUCT
198 print_chaitin_statistics
199 #else
200 NULL
201 #endif
202 )
203 , _lrg_map(Thread::current()->resource_area(), unique)
204 , _live(0)
205 , _spilled_once(Thread::current()->resource_area())
206 , _spilled_twice(Thread::current()->resource_area())
207 , _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0)
208 , _oldphi(unique)
209 , _scheduling_info_generated(scheduling_info_generated)
210 , _sched_int_pressure(0, INTPRESSURE)
211 , _sched_float_pressure(0, FLOATPRESSURE)
212 , _scratch_int_pressure(0, INTPRESSURE)
213 , _scratch_float_pressure(0, FLOATPRESSURE)
214 #ifndef PRODUCT
215 , _trace_spilling(C->directive()->TraceSpillingOption)
216 #endif
217 {
218 Compile::TracePhase tp("ctorChaitin", &timers[_t_ctorChaitin]);
219
220 _high_frequency_lrg = MIN2(double(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency());
221
222 // Build a list of basic blocks, sorted by frequency
223 _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
224 // Experiment with sorting strategies to speed compilation
225 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket
226 Block **buckets[NUMBUCKS]; // Array of buckets
227 uint buckcnt[NUMBUCKS]; // Array of bucket counters
228 double buckval[NUMBUCKS]; // Array of bucket value cutoffs
229 for (uint i = 0; i < NUMBUCKS; i++) {
230 buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
231 buckcnt[i] = 0;
232 // Bump by three orders of magnitude each time
233 cutoff *= 0.001;
234 buckval[i] = cutoff;
235 for (uint j = 0; j < _cfg.number_of_blocks(); j++) {
236 buckets[i][j] = NULL;
237 }
238 }
239 // Sort blocks into buckets
240 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
241 for (uint j = 0; j < NUMBUCKS; j++) {
242 if ((j == NUMBUCKS - 1) || (_cfg.get_block(i)->_freq > buckval[j])) {
243 // Assign block to end of list for appropriate bucket
244 buckets[j][buckcnt[j]++] = _cfg.get_block(i);
245 break; // kick out of inner loop
246 }
247 }
248 }
249 // Dump buckets into final block array
250 uint blkcnt = 0;
251 for (uint i = 0; i < NUMBUCKS; i++) {
252 for (uint j = 0; j < buckcnt[i]; j++) {
253 _blks[blkcnt++] = buckets[i][j];
254 }
255 }
256
257 assert(blkcnt == _cfg.number_of_blocks(), "Block array not totally filled");
258 }
259
260 // union 2 sets together.
261 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) {
262 uint src = _lrg_map.find(src_n);
263 uint dst = _lrg_map.find(dst_n);
264 assert(src, "");
265 assert(dst, "");
266 assert(src < _lrg_map.max_lrg_id(), "oob");
267 assert(dst < _lrg_map.max_lrg_id(), "oob");
268 assert(src < dst, "always union smaller");
269 _lrg_map.uf_map(dst, src);
270 }
271
272 void PhaseChaitin::new_lrg(const Node *x, uint lrg) {
273 // Make the Node->LRG mapping
274 _lrg_map.extend(x->_idx,lrg);
275 // Make the Union-Find mapping an identity function
276 _lrg_map.uf_extend(lrg, lrg);
277 }
278
279
280 int PhaseChaitin::clone_projs(Block* b, uint idx, Node* orig, Node* copy, uint& max_lrg_id) {
281 assert(b->find_node(copy) == (idx - 1), "incorrect insert index for copy kill projections");
282 DEBUG_ONLY( Block* borig = _cfg.get_block_for_node(orig); )
283 int found_projs = 0;
284 uint cnt = orig->outcnt();
285 for (uint i = 0; i < cnt; i++) {
286 Node* proj = orig->raw_out(i);
287 if (proj->is_MachProj()) {
288 assert(proj->outcnt() == 0, "only kill projections are expected here");
289 assert(_cfg.get_block_for_node(proj) == borig, "incorrect block for kill projections");
290 found_projs++;
291 // Copy kill projections after the cloned node
292 Node* kills = proj->clone();
293 kills->set_req(0, copy);
294 b->insert_node(kills, idx++);
295 _cfg.map_node_to_block(kills, b);
296 new_lrg(kills, max_lrg_id++);
297 }
298 }
299 return found_projs;
300 }
301
302 // Renumber the live ranges to compact them. Makes the IFG smaller.
303 void PhaseChaitin::compact() {
304 Compile::TracePhase tp("chaitinCompact", &timers[_t_chaitinCompact]);
305
306 // Current the _uf_map contains a series of short chains which are headed
307 // by a self-cycle. All the chains run from big numbers to little numbers.
308 // The Find() call chases the chains & shortens them for the next Find call.
309 // We are going to change this structure slightly. Numbers above a moving
310 // wave 'i' are unchanged. Numbers below 'j' point directly to their
311 // compacted live range with no further chaining. There are no chains or
312 // cycles below 'i', so the Find call no longer works.
313 uint j=1;
314 uint i;
315 for (i = 1; i < _lrg_map.max_lrg_id(); i++) {
316 uint lr = _lrg_map.uf_live_range_id(i);
317 // Ignore unallocated live ranges
318 if (!lr) {
319 continue;
320 }
321 assert(lr <= i, "");
322 _lrg_map.uf_map(i, ( lr == i ) ? j++ : _lrg_map.uf_live_range_id(lr));
323 }
324 // Now change the Node->LR mapping to reflect the compacted names
325 uint unique = _lrg_map.size();
326 for (i = 0; i < unique; i++) {
327 uint lrg_id = _lrg_map.live_range_id(i);
328 _lrg_map.map(i, _lrg_map.uf_live_range_id(lrg_id));
329 }
330
331 // Reset the Union-Find mapping
332 _lrg_map.reset_uf_map(j);
333 }
334
335 void PhaseChaitin::Register_Allocate() {
336
337 // Above the OLD FP (and in registers) are the incoming arguments. Stack
338 // slots in this area are called "arg_slots". Above the NEW FP (and in
339 // registers) is the outgoing argument area; above that is the spill/temp
340 // area. These are all "frame_slots". Arg_slots start at the zero
341 // stack_slots and count up to the known arg_size. Frame_slots start at
342 // the stack_slot #arg_size and go up. After allocation I map stack
343 // slots to actual offsets. Stack-slots in the arg_slot area are biased
344 // by the frame_size; stack-slots in the frame_slot area are biased by 0.
345
346 _trip_cnt = 0;
347 _alternate = 0;
348 _matcher._allocation_started = true;
349
350 ResourceArea split_arena; // Arena for Split local resources
351 ResourceArea live_arena; // Arena for liveness & IFG info
352 ResourceMark rm(&live_arena);
353
354 // Need live-ness for the IFG; need the IFG for coalescing. If the
355 // liveness is JUST for coalescing, then I can get some mileage by renaming
356 // all copy-related live ranges low and then using the max copy-related
357 // live range as a cut-off for LIVE and the IFG. In other words, I can
358 // build a subset of LIVE and IFG just for copies.
359 PhaseLive live(_cfg, _lrg_map.names(), &live_arena, false);
360
361 // Need IFG for coalescing and coloring
362 PhaseIFG ifg(&live_arena);
363 _ifg = &ifg;
364
365 // Come out of SSA world to the Named world. Assign (virtual) registers to
366 // Nodes. Use the same register for all inputs and the output of PhiNodes
367 // - effectively ending SSA form. This requires either coalescing live
368 // ranges or inserting copies. For the moment, we insert "virtual copies"
369 // - we pretend there is a copy prior to each Phi in predecessor blocks.
370 // We will attempt to coalesce such "virtual copies" before we manifest
371 // them for real.
372 de_ssa();
373
374 #ifdef ASSERT
375 // Veify the graph before RA.
376 verify(&live_arena);
377 #endif
378
379 {
380 Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
381 _live = NULL; // Mark live as being not available
382 rm.reset_to_mark(); // Reclaim working storage
383 IndexSet::reset_memory(C, &live_arena);
384 ifg.init(_lrg_map.max_lrg_id()); // Empty IFG
385 gather_lrg_masks( false ); // Collect LRG masks
386 live.compute(_lrg_map.max_lrg_id()); // Compute liveness
387 _live = &live; // Mark LIVE as being available
388 }
389
390 // Base pointers are currently "used" by instructions which define new
391 // derived pointers. This makes base pointers live up to the where the
392 // derived pointer is made, but not beyond. Really, they need to be live
393 // across any GC point where the derived value is live. So this code looks
394 // at all the GC points, and "stretches" the live range of any base pointer
395 // to the GC point.
396 if (stretch_base_pointer_live_ranges(&live_arena)) {
397 Compile::TracePhase tp("computeLive (sbplr)", &timers[_t_computeLive]);
398 // Since some live range stretched, I need to recompute live
399 _live = NULL;
400 rm.reset_to_mark(); // Reclaim working storage
401 IndexSet::reset_memory(C, &live_arena);
402 ifg.init(_lrg_map.max_lrg_id());
403 gather_lrg_masks(false);
404 live.compute(_lrg_map.max_lrg_id());
405 _live = &live;
406 }
407 // Create the interference graph using virtual copies
408 build_ifg_virtual(); // Include stack slots this time
409
410 // The IFG is/was triangular. I am 'squaring it up' so Union can run
411 // faster. Union requires a 'for all' operation which is slow on the
412 // triangular adjacency matrix (quick reminder: the IFG is 'sparse' -
413 // meaning I can visit all the Nodes neighbors less than a Node in time
414 // O(# of neighbors), but I have to visit all the Nodes greater than a
415 // given Node and search them for an instance, i.e., time O(#MaxLRG)).
416 _ifg->SquareUp();
417
418 // Aggressive (but pessimistic) copy coalescing.
419 // This pass works on virtual copies. Any virtual copies which are not
420 // coalesced get manifested as actual copies
421 {
422 Compile::TracePhase tp("chaitinCoalesce1", &timers[_t_chaitinCoalesce1]);
423
424 PhaseAggressiveCoalesce coalesce(*this);
425 coalesce.coalesce_driver();
426 // Insert un-coalesced copies. Visit all Phis. Where inputs to a Phi do
427 // not match the Phi itself, insert a copy.
428 coalesce.insert_copies(_matcher);
429 if (C->failing()) {
430 return;
431 }
432 }
433
434 // After aggressive coalesce, attempt a first cut at coloring.
435 // To color, we need the IFG and for that we need LIVE.
436 {
437 Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
438 _live = NULL;
439 rm.reset_to_mark(); // Reclaim working storage
440 IndexSet::reset_memory(C, &live_arena);
441 ifg.init(_lrg_map.max_lrg_id());
442 gather_lrg_masks( true );
443 live.compute(_lrg_map.max_lrg_id());
444 _live = &live;
445 }
446
447 // Build physical interference graph
448 uint must_spill = 0;
449 must_spill = build_ifg_physical(&live_arena);
450 // If we have a guaranteed spill, might as well spill now
451 if (must_spill) {
452 if(!_lrg_map.max_lrg_id()) {
453 return;
454 }
455 // Bail out if unique gets too large (ie - unique > MaxNodeLimit)
456 C->check_node_count(10*must_spill, "out of nodes before split");
457 if (C->failing()) {
458 return;
459 }
460
461 uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena); // Split spilling LRG everywhere
462 _lrg_map.set_max_lrg_id(new_max_lrg_id);
463 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
464 // or we failed to split
465 C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split");
466 if (C->failing()) {
467 return;
468 }
469
470 NOT_PRODUCT(C->verify_graph_edges();)
471
472 compact(); // Compact LRGs; return new lower max lrg
473
474 {
475 Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
476 _live = NULL;
477 rm.reset_to_mark(); // Reclaim working storage
478 IndexSet::reset_memory(C, &live_arena);
479 ifg.init(_lrg_map.max_lrg_id()); // Build a new interference graph
480 gather_lrg_masks( true ); // Collect intersect mask
481 live.compute(_lrg_map.max_lrg_id()); // Compute LIVE
482 _live = &live;
483 }
484 build_ifg_physical(&live_arena);
485 _ifg->SquareUp();
486 _ifg->Compute_Effective_Degree();
487 // Only do conservative coalescing if requested
488 if (OptoCoalesce) {
489 Compile::TracePhase tp("chaitinCoalesce2", &timers[_t_chaitinCoalesce2]);
490 // Conservative (and pessimistic) copy coalescing of those spills
491 PhaseConservativeCoalesce coalesce(*this);
492 // If max live ranges greater than cutoff, don't color the stack.
493 // This cutoff can be larger than below since it is only done once.
494 coalesce.coalesce_driver();
495 }
496 _lrg_map.compress_uf_map_for_nodes();
497
498 #ifdef ASSERT
499 verify(&live_arena, true);
500 #endif
501 } else {
502 ifg.SquareUp();
503 ifg.Compute_Effective_Degree();
504 #ifdef ASSERT
505 set_was_low();
506 #endif
507 }
508
509 // Prepare for Simplify & Select
510 cache_lrg_info(); // Count degree of LRGs
511
512 // Simplify the InterFerence Graph by removing LRGs of low degree.
513 // LRGs of low degree are trivially colorable.
514 Simplify();
515
516 // Select colors by re-inserting LRGs back into the IFG in reverse order.
517 // Return whether or not something spills.
518 uint spills = Select( );
519
520 // If we spill, split and recycle the entire thing
521 while( spills ) {
522 if( _trip_cnt++ > 24 ) {
523 DEBUG_ONLY( dump_for_spill_split_recycle(); )
524 if( _trip_cnt > 27 ) {
525 C->record_method_not_compilable("failed spill-split-recycle sanity check");
526 return;
527 }
528 }
529
530 if (!_lrg_map.max_lrg_id()) {
531 return;
532 }
533 uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena); // Split spilling LRG everywhere
534 _lrg_map.set_max_lrg_id(new_max_lrg_id);
535 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
536 C->check_node_count(2 * NodeLimitFudgeFactor, "out of nodes after split");
537 if (C->failing()) {
538 return;
539 }
540
541 compact(); // Compact LRGs; return new lower max lrg
542
543 // Nuke the live-ness and interference graph and LiveRanGe info
544 {
545 Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
546 _live = NULL;
547 rm.reset_to_mark(); // Reclaim working storage
548 IndexSet::reset_memory(C, &live_arena);
549 ifg.init(_lrg_map.max_lrg_id());
550
551 // Create LiveRanGe array.
552 // Intersect register masks for all USEs and DEFs
553 gather_lrg_masks(true);
554 live.compute(_lrg_map.max_lrg_id());
555 _live = &live;
556 }
557 must_spill = build_ifg_physical(&live_arena);
558 _ifg->SquareUp();
559 _ifg->Compute_Effective_Degree();
560
561 // Only do conservative coalescing if requested
562 if (OptoCoalesce) {
563 Compile::TracePhase tp("chaitinCoalesce3", &timers[_t_chaitinCoalesce3]);
564 // Conservative (and pessimistic) copy coalescing
565 PhaseConservativeCoalesce coalesce(*this);
566 // Check for few live ranges determines how aggressive coalesce is.
567 coalesce.coalesce_driver();
568 }
569 _lrg_map.compress_uf_map_for_nodes();
570 #ifdef ASSERT
571 verify(&live_arena, true);
572 #endif
573 cache_lrg_info(); // Count degree of LRGs
574
575 // Simplify the InterFerence Graph by removing LRGs of low degree.
576 // LRGs of low degree are trivially colorable.
577 Simplify();
578
579 // Select colors by re-inserting LRGs back into the IFG in reverse order.
580 // Return whether or not something spills.
581 spills = Select();
582 }
583
584 // Count number of Simplify-Select trips per coloring success.
585 _allocator_attempts += _trip_cnt + 1;
586 _allocator_successes += 1;
587
588 // Peephole remove copies
589 post_allocate_copy_removal();
590
591 // Merge multidefs if multiple defs representing the same value are used in a single block.
592 merge_multidefs();
593
594 #ifdef ASSERT
595 // Veify the graph after RA.
596 verify(&live_arena);
597 #endif
598
599 // max_reg is past the largest *register* used.
600 // Convert that to a frame_slot number.
601 if (_max_reg <= _matcher._new_SP) {
602 _framesize = C->out_preserve_stack_slots();
603 }
604 else {
605 _framesize = _max_reg -_matcher._new_SP;
606 }
607 assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough");
608
609 // This frame must preserve the required fp alignment
610 _framesize = align_up(_framesize, Matcher::stack_alignment_in_slots());
611 assert(_framesize <= 1000000, "sanity check");
612 #ifndef PRODUCT
613 _total_framesize += _framesize;
614 if ((int)_framesize > _max_framesize) {
615 _max_framesize = _framesize;
616 }
617 #endif
618
619 // Convert CISC spills
620 fixup_spills();
621
622 // Log regalloc results
623 CompileLog* log = Compile::current()->log();
624 if (log != NULL) {
625 log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());
626 }
627
628 if (C->failing()) {
629 return;
630 }
631
632 NOT_PRODUCT(C->verify_graph_edges();)
633
634 // Move important info out of the live_arena to longer lasting storage.
635 alloc_node_regs(_lrg_map.size());
636 for (uint i=0; i < _lrg_map.size(); i++) {
637 if (_lrg_map.live_range_id(i)) { // Live range associated with Node?
638 LRG &lrg = lrgs(_lrg_map.live_range_id(i));
639 if (!lrg.alive()) {
640 set_bad(i);
641 } else if (lrg.num_regs() == 1) {
642 set1(i, lrg.reg());
643 } else { // Must be a register-set
644 if (!lrg._fat_proj) { // Must be aligned adjacent register set
645 // Live ranges record the highest register in their mask.
646 // We want the low register for the AD file writer's convenience.
647 OptoReg::Name hi = lrg.reg(); // Get hi register
648 OptoReg::Name lo = OptoReg::add(hi, (1-lrg.num_regs())); // Find lo
649 // We have to use pair [lo,lo+1] even for wide vectors because
650 // the rest of code generation works only with pairs. It is safe
651 // since for registers encoding only 'lo' is used.
652 // Second reg from pair is used in ScheduleAndBundle on SPARC where
653 // vector max size is 8 which corresponds to registers pair.
654 // It is also used in BuildOopMaps but oop operations are not
655 // vectorized.
656 set2(i, lo);
657 } else { // Misaligned; extract 2 bits
658 OptoReg::Name hi = lrg.reg(); // Get hi register
659 lrg.Remove(hi); // Yank from mask
660 int lo = lrg.mask().find_first_elem(); // Find lo
661 set_pair(i, hi, lo);
662 }
663 }
664 if( lrg._is_oop ) _node_oops.set(i);
665 } else {
666 set_bad(i);
667 }
668 }
669
670 // Done!
671 _live = NULL;
672 _ifg = NULL;
673 C->set_indexSet_arena(NULL); // ResourceArea is at end of scope
674 }
675
676 void PhaseChaitin::de_ssa() {
677 // Set initial Names for all Nodes. Most Nodes get the virtual register
678 // number. A few get the ZERO live range number. These do not
679 // get allocated, but instead rely on correct scheduling to ensure that
680 // only one instance is simultaneously live at a time.
681 uint lr_counter = 1;
682 for( uint i = 0; i < _cfg.number_of_blocks(); i++ ) {
683 Block* block = _cfg.get_block(i);
684 uint cnt = block->number_of_nodes();
685
686 // Handle all the normal Nodes in the block
687 for( uint j = 0; j < cnt; j++ ) {
688 Node *n = block->get_node(j);
689 // Pre-color to the zero live range, or pick virtual register
690 const RegMask &rm = n->out_RegMask();
691 _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0);
692 }
693 }
694
695 // Reset the Union-Find mapping to be identity
696 _lrg_map.reset_uf_map(lr_counter);
697 }
698
699 void PhaseChaitin::mark_ssa() {
700 // Use ssa names to populate the live range maps or if no mask
701 // is available, use the 0 entry.
702 uint max_idx = 0;
703 for ( uint i = 0; i < _cfg.number_of_blocks(); i++ ) {
704 Block* block = _cfg.get_block(i);
705 uint cnt = block->number_of_nodes();
706
707 // Handle all the normal Nodes in the block
708 for ( uint j = 0; j < cnt; j++ ) {
709 Node *n = block->get_node(j);
710 // Pre-color to the zero live range, or pick virtual register
711 const RegMask &rm = n->out_RegMask();
712 _lrg_map.map(n->_idx, rm.is_NotEmpty() ? n->_idx : 0);
713 max_idx = (n->_idx > max_idx) ? n->_idx : max_idx;
714 }
715 }
716 _lrg_map.set_max_lrg_id(max_idx+1);
717
718 // Reset the Union-Find mapping to be identity
719 _lrg_map.reset_uf_map(max_idx+1);
720 }
721
722
723 // Gather LiveRanGe information, including register masks. Modification of
724 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce.
725 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
726
727 // Nail down the frame pointer live range
728 uint fp_lrg = _lrg_map.live_range_id(_cfg.get_root_node()->in(1)->in(TypeFunc::FramePtr));
729 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite
730
731 // For all blocks
732 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
733 Block* block = _cfg.get_block(i);
734
735 // For all instructions
736 for (uint j = 1; j < block->number_of_nodes(); j++) {
737 Node* n = block->get_node(j);
738 uint input_edge_start =1; // Skip control most nodes
739 bool is_machine_node = false;
740 if (n->is_Mach()) {
741 is_machine_node = true;
742 input_edge_start = n->as_Mach()->oper_input_base();
743 }
744 uint idx = n->is_Copy();
745
746 // Get virtual register number, same as LiveRanGe index
747 uint vreg = _lrg_map.live_range_id(n);
748 LRG& lrg = lrgs(vreg);
749 if (vreg) { // No vreg means un-allocable (e.g. memory)
750
751 // Collect has-copy bit
752 if (idx) {
753 lrg._has_copy = 1;
754 uint clidx = _lrg_map.live_range_id(n->in(idx));
755 LRG& copy_src = lrgs(clidx);
756 copy_src._has_copy = 1;
757 }
758
759 // Check for float-vs-int live range (used in register-pressure
760 // calculations)
761 const Type *n_type = n->bottom_type();
762 if (n_type->is_floatingpoint()) {
763 lrg._is_float = 1;
764 }
765
766 // Check for twice prior spilling. Once prior spilling might have
767 // spilled 'soft', 2nd prior spill should have spilled 'hard' and
768 // further spilling is unlikely to make progress.
769 if (_spilled_once.test(n->_idx)) {
770 lrg._was_spilled1 = 1;
771 if (_spilled_twice.test(n->_idx)) {
772 lrg._was_spilled2 = 1;
773 }
774 }
775
776 #ifndef PRODUCT
777 if (trace_spilling() && lrg._def != NULL) {
778 // collect defs for MultiDef printing
779 if (lrg._defs == NULL) {
780 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL);
781 lrg._defs->append(lrg._def);
782 }
783 lrg._defs->append(n);
784 }
785 #endif
786
787 // Check for a single def LRG; these can spill nicely
788 // via rematerialization. Flag as NULL for no def found
789 // yet, or 'n' for single def or -1 for many defs.
790 lrg._def = lrg._def ? NodeSentinel : n;
791
792 // Limit result register mask to acceptable registers
793 const RegMask &rm = n->out_RegMask();
794 lrg.AND( rm );
795
796 uint ireg = n->ideal_reg();
797 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
798 "oops must be in Op_RegP's" );
799
800 // Check for vector live range (only if vector register is used).
801 // On SPARC vector uses RegD which could be misaligned so it is not
802 // processes as vector in RA.
803 if (RegMask::is_vector(ireg))
804 lrg._is_vector = 1;
805 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD || ireg == Op_RegL,
806 "vector must be in vector registers");
807
808 // Check for bound register masks
809 const RegMask &lrgmask = lrg.mask();
810 if (lrgmask.is_bound(ireg)) {
811 lrg._is_bound = 1;
812 }
813
814 // Check for maximum frequency value
815 if (lrg._maxfreq < block->_freq) {
816 lrg._maxfreq = block->_freq;
817 }
818
819 // Check for oop-iness, or long/double
820 // Check for multi-kill projection
821 switch (ireg) {
822 case MachProjNode::fat_proj:
823 // Fat projections have size equal to number of registers killed
824 lrg.set_num_regs(rm.Size());
825 lrg.set_reg_pressure(lrg.num_regs());
826 lrg._fat_proj = 1;
827 lrg._is_bound = 1;
828 break;
829 case Op_RegP:
830 #ifdef _LP64
831 lrg.set_num_regs(2); // Size is 2 stack words
832 #else
833 lrg.set_num_regs(1); // Size is 1 stack word
834 #endif
835 // Register pressure is tracked relative to the maximum values
836 // suggested for that platform, INTPRESSURE and FLOATPRESSURE,
837 // and relative to other types which compete for the same regs.
838 //
839 // The following table contains suggested values based on the
840 // architectures as defined in each .ad file.
841 // INTPRESSURE and FLOATPRESSURE may be tuned differently for
842 // compile-speed or performance.
843 // Note1:
844 // SPARC and SPARCV9 reg_pressures are at 2 instead of 1
845 // since .ad registers are defined as high and low halves.
846 // These reg_pressure values remain compatible with the code
847 // in is_high_pressure() which relates get_invalid_mask_size(),
848 // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE.
849 // Note2:
850 // SPARC -d32 has 24 registers available for integral values,
851 // but only 10 of these are safe for 64-bit longs.
852 // Using set_reg_pressure(2) for both int and long means
853 // the allocator will believe it can fit 26 longs into
854 // registers. Using 2 for longs and 1 for ints means the
855 // allocator will attempt to put 52 integers into registers.
856 // The settings below limit this problem to methods with
857 // many long values which are being run on 32-bit SPARC.
858 //
859 // ------------------- reg_pressure --------------------
860 // Each entry is reg_pressure_per_value,number_of_regs
861 // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE
862 // IA32 2 1 1 1 1 6 6
863 // IA64 1 1 1 1 1 50 41
864 // SPARC 2 2 2 2 2 48 (24) 52 (26)
865 // SPARCV9 2 2 2 2 2 48 (24) 52 (26)
866 // AMD64 1 1 1 1 1 14 15
867 // -----------------------------------------------------
868 #if defined(SPARC)
869 lrg.set_reg_pressure(2); // use for v9 as well
870 #else
871 lrg.set_reg_pressure(1); // normally one value per register
872 #endif
873 if( n_type->isa_oop_ptr() ) {
874 lrg._is_oop = 1;
875 }
876 break;
877 case Op_RegL: // Check for long or double
878 case Op_RegD:
879 lrg.set_num_regs(2);
880 // Define platform specific register pressure
881 #if defined(SPARC) || defined(ARM32)
882 lrg.set_reg_pressure(2);
883 #elif defined(IA32)
884 if( ireg == Op_RegL ) {
885 lrg.set_reg_pressure(2);
886 } else {
887 lrg.set_reg_pressure(1);
888 }
889 #else
890 lrg.set_reg_pressure(1); // normally one value per register
891 #endif
892 // If this def of a double forces a mis-aligned double,
893 // flag as '_fat_proj' - really flag as allowing misalignment
894 // AND changes how we count interferences. A mis-aligned
895 // double can interfere with TWO aligned pairs, or effectively
896 // FOUR registers!
897 if (rm.is_misaligned_pair()) {
898 lrg._fat_proj = 1;
899 lrg._is_bound = 1;
900 }
901 break;
902 case Op_RegF:
903 case Op_RegI:
904 case Op_RegN:
905 case Op_RegFlags:
906 case 0: // not an ideal register
907 lrg.set_num_regs(1);
908 #ifdef SPARC
909 lrg.set_reg_pressure(2);
910 #else
911 lrg.set_reg_pressure(1);
912 #endif
913 break;
914 case Op_VecS:
915 assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");
916 assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity");
917 lrg.set_num_regs(RegMask::SlotsPerVecS);
918 lrg.set_reg_pressure(1);
919 break;
920 case Op_VecD:
921 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
922 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
923 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
924 lrg.set_num_regs(RegMask::SlotsPerVecD);
925 lrg.set_reg_pressure(1);
926 break;
927 case Op_VecX:
928 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
929 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
930 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
931 lrg.set_num_regs(RegMask::SlotsPerVecX);
932 lrg.set_reg_pressure(1);
933 break;
934 case Op_VecY:
935 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity");
936 assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity");
937 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
938 lrg.set_num_regs(RegMask::SlotsPerVecY);
939 lrg.set_reg_pressure(1);
940 break;
941 case Op_VecZ:
942 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecZ), "sanity");
943 assert(RegMask::num_registers(Op_VecZ) == RegMask::SlotsPerVecZ, "sanity");
944 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecZ), "vector should be aligned");
945 lrg.set_num_regs(RegMask::SlotsPerVecZ);
946 lrg.set_reg_pressure(1);
947 break;
948 default:
949 ShouldNotReachHere();
950 }
951 }
952
953 // Now do the same for inputs
954 uint cnt = n->req();
955 // Setup for CISC SPILLING
956 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
957 if( UseCISCSpill && after_aggressive ) {
958 inp = n->cisc_operand();
959 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
960 // Convert operand number to edge index number
961 inp = n->as_Mach()->operand_index(inp);
962 }
963
964 // Prepare register mask for each input
965 for( uint k = input_edge_start; k < cnt; k++ ) {
966 uint vreg = _lrg_map.live_range_id(n->in(k));
967 if (!vreg) {
968 continue;
969 }
970
971 // If this instruction is CISC Spillable, add the flags
972 // bit to its appropriate input
973 if( UseCISCSpill && after_aggressive && inp == k ) {
974 #ifndef PRODUCT
975 if( TraceCISCSpill ) {
976 tty->print(" use_cisc_RegMask: ");
977 n->dump();
978 }
979 #endif
980 n->as_Mach()->use_cisc_RegMask();
981 }
982
983 if (is_machine_node && _scheduling_info_generated) {
984 MachNode* cur_node = n->as_Mach();
985 // this is cleaned up by register allocation
986 if (k >= cur_node->num_opnds()) continue;
987 }
988
989 LRG &lrg = lrgs(vreg);
990 // // Testing for floating point code shape
991 // Node *test = n->in(k);
992 // if( test->is_Mach() ) {
993 // MachNode *m = test->as_Mach();
994 // int op = m->ideal_Opcode();
995 // if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) {
996 // int zzz = 1;
997 // }
998 // }
999
1000 // Limit result register mask to acceptable registers.
1001 // Do not limit registers from uncommon uses before
1002 // AggressiveCoalesce. This effectively pre-virtual-splits
1003 // around uncommon uses of common defs.
1004 const RegMask &rm = n->in_RegMask(k);
1005 if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) {
1006 // Since we are BEFORE aggressive coalesce, leave the register
1007 // mask untrimmed by the call. This encourages more coalescing.
1008 // Later, AFTER aggressive, this live range will have to spill
1009 // but the spiller handles slow-path calls very nicely.
1010 } else {
1011 lrg.AND( rm );
1012 }
1013
1014 // Check for bound register masks
1015 const RegMask &lrgmask = lrg.mask();
1016 uint kreg = n->in(k)->ideal_reg();
1017 bool is_vect = RegMask::is_vector(kreg);
1018 assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
1019 is_vect || kreg == Op_RegD || kreg == Op_RegL,
1020 "vector must be in vector registers");
1021 if (lrgmask.is_bound(kreg))
1022 lrg._is_bound = 1;
1023
1024 // If this use of a double forces a mis-aligned double,
1025 // flag as '_fat_proj' - really flag as allowing misalignment
1026 // AND changes how we count interferences. A mis-aligned
1027 // double can interfere with TWO aligned pairs, or effectively
1028 // FOUR registers!
1029 #ifdef ASSERT
1030 if (is_vect && !_scheduling_info_generated) {
1031 if (lrg.num_regs() != 0) {
1032 assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned");
1033 assert(!lrg._fat_proj, "sanity");
1034 assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity");
1035 } else {
1036 assert(n->is_Phi(), "not all inputs processed only if Phi");
1037 }
1038 }
1039 #endif
1040 if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) {
1041 lrg._fat_proj = 1;
1042 lrg._is_bound = 1;
1043 }
1044 // if the LRG is an unaligned pair, we will have to spill
1045 // so clear the LRG's register mask if it is not already spilled
1046 if (!is_vect && !n->is_SpillCopy() &&
1047 (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) &&
1048 lrgmask.is_misaligned_pair()) {
1049 lrg.Clear();
1050 }
1051
1052 // Check for maximum frequency value
1053 if (lrg._maxfreq < block->_freq) {
1054 lrg._maxfreq = block->_freq;
1055 }
1056
1057 } // End for all allocated inputs
1058 } // end for all instructions
1059 } // end for all blocks
1060
1061 // Final per-liverange setup
1062 for (uint i2 = 0; i2 < _lrg_map.max_lrg_id(); i2++) {
1063 LRG &lrg = lrgs(i2);
1064 assert(!lrg._is_vector || !lrg._fat_proj, "sanity");
1065 if (lrg.num_regs() > 1 && !lrg._fat_proj) {
1066 lrg.clear_to_sets();
1067 }
1068 lrg.compute_set_mask_size();
1069 if (lrg.not_free()) { // Handle case where we lose from the start
1070 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG));
1071 lrg._direct_conflict = 1;
1072 }
1073 lrg.set_degree(0); // no neighbors in IFG yet
1074 }
1075 }
1076
1077 // Set the was-lo-degree bit. Conservative coalescing should not change the
1078 // colorability of the graph. If any live range was of low-degree before
1079 // coalescing, it should Simplify. This call sets the was-lo-degree bit.
1080 // The bit is checked in Simplify.
1081 void PhaseChaitin::set_was_low() {
1082 #ifdef ASSERT
1083 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1084 int size = lrgs(i).num_regs();
1085 uint old_was_lo = lrgs(i)._was_lo;
1086 lrgs(i)._was_lo = 0;
1087 if( lrgs(i).lo_degree() ) {
1088 lrgs(i)._was_lo = 1; // Trivially of low degree
1089 } else { // Else check the Brigg's assertion
1090 // Brigg's observation is that the lo-degree neighbors of a
1091 // hi-degree live range will not interfere with the color choices
1092 // of said hi-degree live range. The Simplify reverse-stack-coloring
1093 // order takes care of the details. Hence you do not have to count
1094 // low-degree neighbors when determining if this guy colors.
1095 int briggs_degree = 0;
1096 IndexSet *s = _ifg->neighbors(i);
1097 IndexSetIterator elements(s);
1098 uint lidx;
1099 while((lidx = elements.next()) != 0) {
1100 if( !lrgs(lidx).lo_degree() )
1101 briggs_degree += MAX2(size,lrgs(lidx).num_regs());
1102 }
1103 if( briggs_degree < lrgs(i).degrees_of_freedom() )
1104 lrgs(i)._was_lo = 1; // Low degree via the briggs assertion
1105 }
1106 assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease");
1107 }
1108 #endif
1109 }
1110
1111 #define REGISTER_CONSTRAINED 16
1112
1113 // Compute cost/area ratio, in case we spill. Build the lo-degree list.
1114 void PhaseChaitin::cache_lrg_info( ) {
1115 Compile::TracePhase tp("chaitinCacheLRG", &timers[_t_chaitinCacheLRG]);
1116
1117 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1118 LRG &lrg = lrgs(i);
1119
1120 // Check for being of low degree: means we can be trivially colored.
1121 // Low degree, dead or must-spill guys just get to simplify right away
1122 if( lrg.lo_degree() ||
1123 !lrg.alive() ||
1124 lrg._must_spill ) {
1125 // Split low degree list into those guys that must get a
1126 // register and those that can go to register or stack.
1127 // The idea is LRGs that can go register or stack color first when
1128 // they have a good chance of getting a register. The register-only
1129 // lo-degree live ranges always get a register.
1130 OptoReg::Name hi_reg = lrg.mask().find_last_elem();
1131 if( OptoReg::is_stack(hi_reg)) { // Can go to stack?
1132 lrg._next = _lo_stk_degree;
1133 _lo_stk_degree = i;
1134 } else {
1135 lrg._next = _lo_degree;
1136 _lo_degree = i;
1137 }
1138 } else { // Else high degree
1139 lrgs(_hi_degree)._prev = i;
1140 lrg._next = _hi_degree;
1141 lrg._prev = 0;
1142 _hi_degree = i;
1143 }
1144 }
1145 }
1146
1147 // Simplify the IFG by removing LRGs of low degree that have NO copies
1148 void PhaseChaitin::Pre_Simplify( ) {
1149
1150 // Warm up the lo-degree no-copy list
1151 int lo_no_copy = 0;
1152 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1153 if ((lrgs(i).lo_degree() && !lrgs(i)._has_copy) ||
1154 !lrgs(i).alive() ||
1155 lrgs(i)._must_spill) {
1156 lrgs(i)._next = lo_no_copy;
1157 lo_no_copy = i;
1158 }
1159 }
1160
1161 while( lo_no_copy ) {
1162 uint lo = lo_no_copy;
1163 lo_no_copy = lrgs(lo)._next;
1164 int size = lrgs(lo).num_regs();
1165
1166 // Put the simplified guy on the simplified list.
1167 lrgs(lo)._next = _simplified;
1168 _simplified = lo;
1169
1170 // Yank this guy from the IFG.
1171 IndexSet *adj = _ifg->remove_node( lo );
1172
1173 // If any neighbors' degrees fall below their number of
1174 // allowed registers, then put that neighbor on the low degree
1175 // list. Note that 'degree' can only fall and 'numregs' is
1176 // unchanged by this action. Thus the two are equal at most once,
1177 // so LRGs hit the lo-degree worklists at most once.
1178 IndexSetIterator elements(adj);
1179 uint neighbor;
1180 while ((neighbor = elements.next()) != 0) {
1181 LRG *n = &lrgs(neighbor);
1182 assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
1183
1184 // Check for just becoming of-low-degree
1185 if( n->just_lo_degree() && !n->_has_copy ) {
1186 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
1187 // Put on lo-degree list
1188 n->_next = lo_no_copy;
1189 lo_no_copy = neighbor;
1190 }
1191 }
1192 } // End of while lo-degree no_copy worklist not empty
1193
1194 // No more lo-degree no-copy live ranges to simplify
1195 }
1196
1197 // Simplify the IFG by removing LRGs of low degree.
1198 void PhaseChaitin::Simplify( ) {
1199 Compile::TracePhase tp("chaitinSimplify", &timers[_t_chaitinSimplify]);
1200
1201 while( 1 ) { // Repeat till simplified it all
1202 // May want to explore simplifying lo_degree before _lo_stk_degree.
1203 // This might result in more spills coloring into registers during
1204 // Select().
1205 while( _lo_degree || _lo_stk_degree ) {
1206 // If possible, pull from lo_stk first
1207 uint lo;
1208 if( _lo_degree ) {
1209 lo = _lo_degree;
1210 _lo_degree = lrgs(lo)._next;
1211 } else {
1212 lo = _lo_stk_degree;
1213 _lo_stk_degree = lrgs(lo)._next;
1214 }
1215
1216 // Put the simplified guy on the simplified list.
1217 lrgs(lo)._next = _simplified;
1218 _simplified = lo;
1219 // If this guy is "at risk" then mark his current neighbors
1220 if( lrgs(lo)._at_risk ) {
1221 IndexSetIterator elements(_ifg->neighbors(lo));
1222 uint datum;
1223 while ((datum = elements.next()) != 0) {
1224 lrgs(datum)._risk_bias = lo;
1225 }
1226 }
1227
1228 // Yank this guy from the IFG.
1229 IndexSet *adj = _ifg->remove_node( lo );
1230
1231 // If any neighbors' degrees fall below their number of
1232 // allowed registers, then put that neighbor on the low degree
1233 // list. Note that 'degree' can only fall and 'numregs' is
1234 // unchanged by this action. Thus the two are equal at most once,
1235 // so LRGs hit the lo-degree worklist at most once.
1236 IndexSetIterator elements(adj);
1237 uint neighbor;
1238 while ((neighbor = elements.next()) != 0) {
1239 LRG *n = &lrgs(neighbor);
1240 #ifdef ASSERT
1241 if( VerifyOpto || VerifyRegisterAllocator ) {
1242 assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
1243 }
1244 #endif
1245
1246 // Check for just becoming of-low-degree just counting registers.
1247 // _must_spill live ranges are already on the low degree list.
1248 if( n->just_lo_degree() && !n->_must_spill ) {
1249 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
1250 // Pull from hi-degree list
1251 uint prev = n->_prev;
1252 uint next = n->_next;
1253 if( prev ) lrgs(prev)._next = next;
1254 else _hi_degree = next;
1255 lrgs(next)._prev = prev;
1256 n->_next = _lo_degree;
1257 _lo_degree = neighbor;
1258 }
1259 }
1260 } // End of while lo-degree/lo_stk_degree worklist not empty
1261
1262 // Check for got everything: is hi-degree list empty?
1263 if( !_hi_degree ) break;
1264
1265 // Time to pick a potential spill guy
1266 uint lo_score = _hi_degree;
1267 double score = lrgs(lo_score).score();
1268 double area = lrgs(lo_score)._area;
1269 double cost = lrgs(lo_score)._cost;
1270 bool bound = lrgs(lo_score)._is_bound;
1271
1272 // Find cheapest guy
1273 debug_only( int lo_no_simplify=0; );
1274 for( uint i = _hi_degree; i; i = lrgs(i)._next ) {
1275 assert( !(*_ifg->_yanked)[i], "" );
1276 // It's just vaguely possible to move hi-degree to lo-degree without
1277 // going through a just-lo-degree stage: If you remove a double from
1278 // a float live range it's degree will drop by 2 and you can skip the
1279 // just-lo-degree stage. It's very rare (shows up after 5000+ methods
1280 // in -Xcomp of Java2Demo). So just choose this guy to simplify next.
1281 if( lrgs(i).lo_degree() ) {
1282 lo_score = i;
1283 break;
1284 }
1285 debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; );
1286 double iscore = lrgs(i).score();
1287 double iarea = lrgs(i)._area;
1288 double icost = lrgs(i)._cost;
1289 bool ibound = lrgs(i)._is_bound;
1290
1291 // Compare cost/area of i vs cost/area of lo_score. Smaller cost/area
1292 // wins. Ties happen because all live ranges in question have spilled
1293 // a few times before and the spill-score adds a huge number which
1294 // washes out the low order bits. We are choosing the lesser of 2
1295 // evils; in this case pick largest area to spill.
1296 // Ties also happen when live ranges are defined and used only inside
1297 // one block. In which case their area is 0 and score set to max.
1298 // In such case choose bound live range over unbound to free registers
1299 // or with smaller cost to spill.
1300 if( iscore < score ||
1301 (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) ||
1302 (iscore == score && iarea == area &&
1303 ( (ibound && !bound) || ibound == bound && (icost < cost) )) ) {
1304 lo_score = i;
1305 score = iscore;
1306 area = iarea;
1307 cost = icost;
1308 bound = ibound;
1309 }
1310 }
1311 LRG *lo_lrg = &lrgs(lo_score);
1312 // The live range we choose for spilling is either hi-degree, or very
1313 // rarely it can be low-degree. If we choose a hi-degree live range
1314 // there better not be any lo-degree choices.
1315 assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" );
1316
1317 // Pull from hi-degree list
1318 uint prev = lo_lrg->_prev;
1319 uint next = lo_lrg->_next;
1320 if( prev ) lrgs(prev)._next = next;
1321 else _hi_degree = next;
1322 lrgs(next)._prev = prev;
1323 // Jam him on the lo-degree list, despite his high degree.
1324 // Maybe he'll get a color, and maybe he'll spill.
1325 // Only Select() will know.
1326 lrgs(lo_score)._at_risk = true;
1327 _lo_degree = lo_score;
1328 lo_lrg->_next = 0;
1329
1330 } // End of while not simplified everything
1331
1332 }
1333
1334 // Is 'reg' register legal for 'lrg'?
1335 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) {
1336 if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) &&
1337 lrg.mask().Member(OptoReg::add(reg,-chunk))) {
1338 // RA uses OptoReg which represent the highest element of a registers set.
1339 // For example, vectorX (128bit) on x86 uses [XMM,XMMb,XMMc,XMMd] set
1340 // in which XMMd is used by RA to represent such vectors. A double value
1341 // uses [XMM,XMMb] pairs and XMMb is used by RA for it.
1342 // The register mask uses largest bits set of overlapping register sets.
1343 // On x86 with AVX it uses 8 bits for each XMM registers set.
1344 //
1345 // The 'lrg' already has cleared-to-set register mask (done in Select()
1346 // before calling choose_color()). Passing mask.Member(reg) check above
1347 // indicates that the size (num_regs) of 'reg' set is less or equal to
1348 // 'lrg' set size.
1349 // For set size 1 any register which is member of 'lrg' mask is legal.
1350 if (lrg.num_regs()==1)
1351 return true;
1352 // For larger sets only an aligned register with the same set size is legal.
1353 int mask = lrg.num_regs()-1;
1354 if ((reg&mask) == mask)
1355 return true;
1356 }
1357 return false;
1358 }
1359
1360 // Choose a color using the biasing heuristic
1361 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
1362
1363 // Check for "at_risk" LRG's
1364 uint risk_lrg = _lrg_map.find(lrg._risk_bias);
1365 if( risk_lrg != 0 ) {
1366 // Walk the colored neighbors of the "at_risk" candidate
1367 // Choose a color which is both legal and already taken by a neighbor
1368 // of the "at_risk" candidate in order to improve the chances of the
1369 // "at_risk" candidate of coloring
1370 IndexSetIterator elements(_ifg->neighbors(risk_lrg));
1371 uint datum;
1372 while ((datum = elements.next()) != 0) {
1373 OptoReg::Name reg = lrgs(datum).reg();
1374 // If this LRG's register is legal for us, choose it
1375 if (is_legal_reg(lrg, reg, chunk))
1376 return reg;
1377 }
1378 }
1379
1380 uint copy_lrg = _lrg_map.find(lrg._copy_bias);
1381 if( copy_lrg != 0 ) {
1382 // If he has a color,
1383 if( !(*(_ifg->_yanked))[copy_lrg] ) {
1384 OptoReg::Name reg = lrgs(copy_lrg).reg();
1385 // And it is legal for you,
1386 if (is_legal_reg(lrg, reg, chunk))
1387 return reg;
1388 } else if( chunk == 0 ) {
1389 // Choose a color which is legal for him
1390 RegMask tempmask = lrg.mask();
1391 tempmask.AND(lrgs(copy_lrg).mask());
1392 tempmask.clear_to_sets(lrg.num_regs());
1393 OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs());
1394 if (OptoReg::is_valid(reg))
1395 return reg;
1396 }
1397 }
1398
1399 // If no bias info exists, just go with the register selection ordering
1400 if (lrg._is_vector || lrg.num_regs() == 2) {
1401 // Find an aligned set
1402 return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk);
1403 }
1404
1405 // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate
1406 // copy removal to remove many more copies, by preventing a just-assigned
1407 // register from being repeatedly assigned.
1408 OptoReg::Name reg = lrg.mask().find_first_elem();
1409 if( (++_alternate & 1) && OptoReg::is_valid(reg) ) {
1410 // This 'Remove; find; Insert' idiom is an expensive way to find the
1411 // SECOND element in the mask.
1412 lrg.Remove(reg);
1413 OptoReg::Name reg2 = lrg.mask().find_first_elem();
1414 lrg.Insert(reg);
1415 if( OptoReg::is_reg(reg2))
1416 reg = reg2;
1417 }
1418 return OptoReg::add( reg, chunk );
1419 }
1420
1421 // Choose a color in the current chunk
1422 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) {
1423 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)");
1424 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)");
1425
1426 if( lrg.num_regs() == 1 || // Common Case
1427 !lrg._fat_proj ) // Aligned+adjacent pairs ok
1428 // Use a heuristic to "bias" the color choice
1429 return bias_color(lrg, chunk);
1430
1431 assert(!lrg._is_vector, "should be not vector here" );
1432 assert( lrg.num_regs() >= 2, "dead live ranges do not color" );
1433
1434 // Fat-proj case or misaligned double argument.
1435 assert(lrg.compute_mask_size() == lrg.num_regs() ||
1436 lrg.num_regs() == 2,"fat projs exactly color" );
1437 assert( !chunk, "always color in 1st chunk" );
1438 // Return the highest element in the set.
1439 return lrg.mask().find_last_elem();
1440 }
1441
1442 // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted
1443 // in reverse order of removal. As long as nothing of hi-degree was yanked,
1444 // everything going back is guaranteed a color. Select that color. If some
1445 // hi-degree LRG cannot get a color then we record that we must spill.
1446 uint PhaseChaitin::Select( ) {
1447 Compile::TracePhase tp("chaitinSelect", &timers[_t_chaitinSelect]);
1448
1449 uint spill_reg = LRG::SPILL_REG;
1450 _max_reg = OptoReg::Name(0); // Past max register used
1451 while( _simplified ) {
1452 // Pull next LRG from the simplified list - in reverse order of removal
1453 uint lidx = _simplified;
1454 LRG *lrg = &lrgs(lidx);
1455 _simplified = lrg->_next;
1456
1457
1458 #ifndef PRODUCT
1459 if (trace_spilling()) {
1460 ttyLocker ttyl;
1461 tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(),
1462 lrg->degrees_of_freedom());
1463 lrg->dump();
1464 }
1465 #endif
1466
1467 // Re-insert into the IFG
1468 _ifg->re_insert(lidx);
1469 if( !lrg->alive() ) continue;
1470 // capture allstackedness flag before mask is hacked
1471 const int is_allstack = lrg->mask().is_AllStack();
1472
1473 // Yeah, yeah, yeah, I know, I know. I can refactor this
1474 // to avoid the GOTO, although the refactored code will not
1475 // be much clearer. We arrive here IFF we have a stack-based
1476 // live range that cannot color in the current chunk, and it
1477 // has to move into the next free stack chunk.
1478 int chunk = 0; // Current chunk is first chunk
1479 retry_next_chunk:
1480
1481 // Remove neighbor colors
1482 IndexSet *s = _ifg->neighbors(lidx);
1483
1484 debug_only(RegMask orig_mask = lrg->mask();)
1485 IndexSetIterator elements(s);
1486 uint neighbor;
1487 while ((neighbor = elements.next()) != 0) {
1488 // Note that neighbor might be a spill_reg. In this case, exclusion
1489 // of its color will be a no-op, since the spill_reg chunk is in outer
1490 // space. Also, if neighbor is in a different chunk, this exclusion
1491 // will be a no-op. (Later on, if lrg runs out of possible colors in
1492 // its chunk, a new chunk of color may be tried, in which case
1493 // examination of neighbors is started again, at retry_next_chunk.)
1494 LRG &nlrg = lrgs(neighbor);
1495 OptoReg::Name nreg = nlrg.reg();
1496 // Only subtract masks in the same chunk
1497 if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) {
1498 #ifndef PRODUCT
1499 uint size = lrg->mask().Size();
1500 RegMask rm = lrg->mask();
1501 #endif
1502 lrg->SUBTRACT(nlrg.mask());
1503 #ifndef PRODUCT
1504 if (trace_spilling() && lrg->mask().Size() != size) {
1505 ttyLocker ttyl;
1506 tty->print("L%d ", lidx);
1507 rm.dump();
1508 tty->print(" intersected L%d ", neighbor);
1509 nlrg.mask().dump();
1510 tty->print(" removed ");
1511 rm.SUBTRACT(lrg->mask());
1512 rm.dump();
1513 tty->print(" leaving ");
1514 lrg->mask().dump();
1515 tty->cr();
1516 }
1517 #endif
1518 }
1519 }
1520 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
1521 // Aligned pairs need aligned masks
1522 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1523 if (lrg->num_regs() > 1 && !lrg->_fat_proj) {
1524 lrg->clear_to_sets();
1525 }
1526
1527 // Check if a color is available and if so pick the color
1528 OptoReg::Name reg = choose_color( *lrg, chunk );
1529 #ifdef SPARC
1530 debug_only(lrg->compute_set_mask_size());
1531 assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned");
1532 #endif
1533
1534 //---------------
1535 // If we fail to color and the AllStack flag is set, trigger
1536 // a chunk-rollover event
1537 if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) {
1538 // Bump register mask up to next stack chunk
1539 chunk += RegMask::CHUNK_SIZE;
1540 lrg->Set_All();
1541
1542 goto retry_next_chunk;
1543 }
1544
1545 //---------------
1546 // Did we get a color?
1547 else if( OptoReg::is_valid(reg)) {
1548 #ifndef PRODUCT
1549 RegMask avail_rm = lrg->mask();
1550 #endif
1551
1552 // Record selected register
1553 lrg->set_reg(reg);
1554
1555 if( reg >= _max_reg ) // Compute max register limit
1556 _max_reg = OptoReg::add(reg,1);
1557 // Fold reg back into normal space
1558 reg = OptoReg::add(reg,-chunk);
1559
1560 // If the live range is not bound, then we actually had some choices
1561 // to make. In this case, the mask has more bits in it than the colors
1562 // chosen. Restrict the mask to just what was picked.
1563 int n_regs = lrg->num_regs();
1564 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1565 if (n_regs == 1 || !lrg->_fat_proj) {
1566 assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecZ, "sanity");
1567 lrg->Clear(); // Clear the mask
1568 lrg->Insert(reg); // Set regmask to match selected reg
1569 // For vectors and pairs, also insert the low bit of the pair
1570 for (int i = 1; i < n_regs; i++)
1571 lrg->Insert(OptoReg::add(reg,-i));
1572 lrg->set_mask_size(n_regs);
1573 } else { // Else fatproj
1574 // mask must be equal to fatproj bits, by definition
1575 }
1576 #ifndef PRODUCT
1577 if (trace_spilling()) {
1578 ttyLocker ttyl;
1579 tty->print("L%d selected ", lidx);
1580 lrg->mask().dump();
1581 tty->print(" from ");
1582 avail_rm.dump();
1583 tty->cr();
1584 }
1585 #endif
1586 // Note that reg is the highest-numbered register in the newly-bound mask.
1587 } // end color available case
1588
1589 //---------------
1590 // Live range is live and no colors available
1591 else {
1592 assert( lrg->alive(), "" );
1593 assert( !lrg->_fat_proj || lrg->is_multidef() ||
1594 lrg->_def->outcnt() > 0, "fat_proj cannot spill");
1595 assert( !orig_mask.is_AllStack(), "All Stack does not spill" );
1596
1597 // Assign the special spillreg register
1598 lrg->set_reg(OptoReg::Name(spill_reg++));
1599 // Do not empty the regmask; leave mask_size lying around
1600 // for use during Spilling
1601 #ifndef PRODUCT
1602 if( trace_spilling() ) {
1603 ttyLocker ttyl;
1604 tty->print("L%d spilling with neighbors: ", lidx);
1605 s->dump();
1606 debug_only(tty->print(" original mask: "));
1607 debug_only(orig_mask.dump());
1608 dump_lrg(lidx);
1609 }
1610 #endif
1611 } // end spill case
1612
1613 }
1614
1615 return spill_reg-LRG::SPILL_REG; // Return number of spills
1616 }
1617
1618 // Copy 'was_spilled'-edness from the source Node to the dst Node.
1619 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) {
1620 if( _spilled_once.test(src->_idx) ) {
1621 _spilled_once.set(dst->_idx);
1622 lrgs(_lrg_map.find(dst))._was_spilled1 = 1;
1623 if( _spilled_twice.test(src->_idx) ) {
1624 _spilled_twice.set(dst->_idx);
1625 lrgs(_lrg_map.find(dst))._was_spilled2 = 1;
1626 }
1627 }
1628 }
1629
1630 // Set the 'spilled_once' or 'spilled_twice' flag on a node.
1631 void PhaseChaitin::set_was_spilled( Node *n ) {
1632 if( _spilled_once.test_set(n->_idx) )
1633 _spilled_twice.set(n->_idx);
1634 }
1635
1636 // Convert Ideal spill instructions into proper FramePtr + offset Loads and
1637 // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are.
1638 void PhaseChaitin::fixup_spills() {
1639 // This function does only cisc spill work.
1640 if( !UseCISCSpill ) return;
1641
1642 Compile::TracePhase tp("fixupSpills", &timers[_t_fixupSpills]);
1643
1644 // Grab the Frame Pointer
1645 Node *fp = _cfg.get_root_block()->head()->in(1)->in(TypeFunc::FramePtr);
1646
1647 // For all blocks
1648 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1649 Block* block = _cfg.get_block(i);
1650
1651 // For all instructions in block
1652 uint last_inst = block->end_idx();
1653 for (uint j = 1; j <= last_inst; j++) {
1654 Node* n = block->get_node(j);
1655
1656 // Dead instruction???
1657 assert( n->outcnt() != 0 ||// Nothing dead after post alloc
1658 C->top() == n || // Or the random TOP node
1659 n->is_Proj(), // Or a fat-proj kill node
1660 "No dead instructions after post-alloc" );
1661
1662 int inp = n->cisc_operand();
1663 if( inp != AdlcVMDeps::Not_cisc_spillable ) {
1664 // Convert operand number to edge index number
1665 MachNode *mach = n->as_Mach();
1666 inp = mach->operand_index(inp);
1667 Node *src = n->in(inp); // Value to load or store
1668 LRG &lrg_cisc = lrgs(_lrg_map.find_const(src));
1669 OptoReg::Name src_reg = lrg_cisc.reg();
1670 // Doubles record the HIGH register of an adjacent pair.
1671 src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs());
1672 if( OptoReg::is_stack(src_reg) ) { // If input is on stack
1673 // This is a CISC Spill, get stack offset and construct new node
1674 #ifndef PRODUCT
1675 if( TraceCISCSpill ) {
1676 tty->print(" reg-instr: ");
1677 n->dump();
1678 }
1679 #endif
1680 int stk_offset = reg2offset(src_reg);
1681 // Bailout if we might exceed node limit when spilling this instruction
1682 C->check_node_count(0, "out of nodes fixing spills");
1683 if (C->failing()) return;
1684 // Transform node
1685 MachNode *cisc = mach->cisc_version(stk_offset)->as_Mach();
1686 cisc->set_req(inp,fp); // Base register is frame pointer
1687 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) {
1688 assert( cisc->oper_input_base() == 2, "Only adding one edge");
1689 cisc->ins_req(1,src); // Requires a memory edge
1690 }
1691 block->map_node(cisc, j); // Insert into basic block
1692 n->subsume_by(cisc, C); // Correct graph
1693 //
1694 ++_used_cisc_instructions;
1695 #ifndef PRODUCT
1696 if( TraceCISCSpill ) {
1697 tty->print(" cisc-instr: ");
1698 cisc->dump();
1699 }
1700 #endif
1701 } else {
1702 #ifndef PRODUCT
1703 if( TraceCISCSpill ) {
1704 tty->print(" using reg-instr: ");
1705 n->dump();
1706 }
1707 #endif
1708 ++_unused_cisc_instructions; // input can be on stack
1709 }
1710 }
1711
1712 } // End of for all instructions
1713
1714 } // End of for all blocks
1715 }
1716
1717 // Helper to stretch above; recursively discover the base Node for a
1718 // given derived Node. Easy for AddP-related machine nodes, but needs
1719 // to be recursive for derived Phis.
1720 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) {
1721 // See if already computed; if so return it
1722 if( derived_base_map[derived->_idx] )
1723 return derived_base_map[derived->_idx];
1724
1725 // See if this happens to be a base.
1726 // NOTE: we use TypePtr instead of TypeOopPtr because we can have
1727 // pointers derived from NULL! These are always along paths that
1728 // can't happen at run-time but the optimizer cannot deduce it so
1729 // we have to handle it gracefully.
1730 assert(!derived->bottom_type()->isa_narrowoop() ||
1731 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1732 const TypePtr *tj = derived->bottom_type()->isa_ptr();
1733 // If its an OOP with a non-zero offset, then it is derived.
1734 if( tj == NULL || tj->_offset == 0 ) {
1735 derived_base_map[derived->_idx] = derived;
1736 return derived;
1737 }
1738 // Derived is NULL+offset? Base is NULL!
1739 if( derived->is_Con() ) {
1740 Node *base = _matcher.mach_null();
1741 assert(base != NULL, "sanity");
1742 if (base->in(0) == NULL) {
1743 // Initialize it once and make it shared:
1744 // set control to _root and place it into Start block
1745 // (where top() node is placed).
1746 base->init_req(0, _cfg.get_root_node());
1747 Block *startb = _cfg.get_block_for_node(C->top());
1748 uint node_pos = startb->find_node(C->top());
1749 startb->insert_node(base, node_pos);
1750 _cfg.map_node_to_block(base, startb);
1751 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet");
1752
1753 // The loadConP0 might have projection nodes depending on architecture
1754 // Add the projection nodes to the CFG
1755 for (DUIterator_Fast imax, i = base->fast_outs(imax); i < imax; i++) {
1756 Node* use = base->fast_out(i);
1757 if (use->is_MachProj()) {
1758 startb->insert_node(use, ++node_pos);
1759 _cfg.map_node_to_block(use, startb);
1760 new_lrg(use, maxlrg++);
1761 }
1762 }
1763 }
1764 if (_lrg_map.live_range_id(base) == 0) {
1765 new_lrg(base, maxlrg++);
1766 }
1767 assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared");
1768 derived_base_map[derived->_idx] = base;
1769 return base;
1770 }
1771
1772 // Check for AddP-related opcodes
1773 if (!derived->is_Phi()) {
1774 assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, "but is: %s", derived->Name());
1775 Node *base = derived->in(AddPNode::Base);
1776 derived_base_map[derived->_idx] = base;
1777 return base;
1778 }
1779
1780 // Recursively find bases for Phis.
1781 // First check to see if we can avoid a base Phi here.
1782 Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg);
1783 uint i;
1784 for( i = 2; i < derived->req(); i++ )
1785 if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg))
1786 break;
1787 // Went to the end without finding any different bases?
1788 if( i == derived->req() ) { // No need for a base Phi here
1789 derived_base_map[derived->_idx] = base;
1790 return base;
1791 }
1792
1793 // Now we see we need a base-Phi here to merge the bases
1794 const Type *t = base->bottom_type();
1795 base = new PhiNode( derived->in(0), t );
1796 for( i = 1; i < derived->req(); i++ ) {
1797 base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg));
1798 t = t->meet(base->in(i)->bottom_type());
1799 }
1800 base->as_Phi()->set_type(t);
1801
1802 // Search the current block for an existing base-Phi
1803 Block *b = _cfg.get_block_for_node(derived);
1804 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi
1805 Node *phi = b->get_node(i);
1806 if( !phi->is_Phi() ) { // Found end of Phis with no match?
1807 b->insert_node(base, i); // Must insert created Phi here as base
1808 _cfg.map_node_to_block(base, b);
1809 new_lrg(base,maxlrg++);
1810 break;
1811 }
1812 // See if Phi matches.
1813 uint j;
1814 for( j = 1; j < base->req(); j++ )
1815 if( phi->in(j) != base->in(j) &&
1816 !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs
1817 break;
1818 if( j == base->req() ) { // All inputs match?
1819 base = phi; // Then use existing 'phi' and drop 'base'
1820 break;
1821 }
1822 }
1823
1824
1825 // Cache info for later passes
1826 derived_base_map[derived->_idx] = base;
1827 return base;
1828 }
1829
1830 // At each Safepoint, insert extra debug edges for each pair of derived value/
1831 // base pointer that is live across the Safepoint for oopmap building. The
1832 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the
1833 // required edge set.
1834 bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) {
1835 int must_recompute_live = false;
1836 uint maxlrg = _lrg_map.max_lrg_id();
1837 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique());
1838 memset( derived_base_map, 0, sizeof(Node*)*C->unique() );
1839
1840 // For all blocks in RPO do...
1841 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1842 Block* block = _cfg.get_block(i);
1843 // Note use of deep-copy constructor. I cannot hammer the original
1844 // liveout bits, because they are needed by the following coalesce pass.
1845 IndexSet liveout(_live->live(block));
1846
1847 for (uint j = block->end_idx() + 1; j > 1; j--) {
1848 Node* n = block->get_node(j - 1);
1849
1850 // Pre-split compares of loop-phis. Loop-phis form a cycle we would
1851 // like to see in the same register. Compare uses the loop-phi and so
1852 // extends its live range BUT cannot be part of the cycle. If this
1853 // extended live range overlaps with the update of the loop-phi value
1854 // we need both alive at the same time -- which requires at least 1
1855 // copy. But because Intel has only 2-address registers we end up with
1856 // at least 2 copies, one before the loop-phi update instruction and
1857 // one after. Instead we split the input to the compare just after the
1858 // phi.
1859 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
1860 Node *phi = n->in(1);
1861 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
1862 Block *phi_block = _cfg.get_block_for_node(phi);
1863 if (_cfg.get_block_for_node(phi_block->pred(2)) == block) {
1864 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
1865 Node *spill = new MachSpillCopyNode(MachSpillCopyNode::LoopPhiInput, phi, *mask, *mask);
1866 insert_proj( phi_block, 1, spill, maxlrg++ );
1867 n->set_req(1,spill);
1868 must_recompute_live = true;
1869 }
1870 }
1871 }
1872
1873 // Get value being defined
1874 uint lidx = _lrg_map.live_range_id(n);
1875 // Ignore the occasional brand-new live range
1876 if (lidx && lidx < _lrg_map.max_lrg_id()) {
1877 // Remove from live-out set
1878 liveout.remove(lidx);
1879
1880 // Copies do not define a new value and so do not interfere.
1881 // Remove the copies source from the liveout set before interfering.
1882 uint idx = n->is_Copy();
1883 if (idx) {
1884 liveout.remove(_lrg_map.live_range_id(n->in(idx)));
1885 }
1886 }
1887
1888 // Found a safepoint?
1889 JVMState *jvms = n->jvms();
1890 if( jvms ) {
1891 // Now scan for a live derived pointer
1892 IndexSetIterator elements(&liveout);
1893 uint neighbor;
1894 while ((neighbor = elements.next()) != 0) {
1895 // Find reaching DEF for base and derived values
1896 // This works because we are still in SSA during this call.
1897 Node *derived = lrgs(neighbor)._def;
1898 const TypePtr *tj = derived->bottom_type()->isa_ptr();
1899 assert(!derived->bottom_type()->isa_narrowoop() ||
1900 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1901 // If its an OOP with a non-zero offset, then it is derived.
1902 if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) {
1903 Node *base = find_base_for_derived(derived_base_map, derived, maxlrg);
1904 assert(base->_idx < _lrg_map.size(), "");
1905 // Add reaching DEFs of derived pointer and base pointer as a
1906 // pair of inputs
1907 n->add_req(derived);
1908 n->add_req(base);
1909
1910 // See if the base pointer is already live to this point.
1911 // Since I'm working on the SSA form, live-ness amounts to
1912 // reaching def's. So if I find the base's live range then
1913 // I know the base's def reaches here.
1914 if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or
1915 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND
1916 (_lrg_map.live_range_id(base) > 0) && // not a constant
1917 _cfg.get_block_for_node(base) != block) { // base not def'd in blk)
1918 // Base pointer is not currently live. Since I stretched
1919 // the base pointer to here and it crosses basic-block
1920 // boundaries, the global live info is now incorrect.
1921 // Recompute live.
1922 must_recompute_live = true;
1923 } // End of if base pointer is not live to debug info
1924 }
1925 } // End of scan all live data for derived ptrs crossing GC point
1926 } // End of if found a GC point
1927
1928 // Make all inputs live
1929 if (!n->is_Phi()) { // Phi function uses come from prior block
1930 for (uint k = 1; k < n->req(); k++) {
1931 uint lidx = _lrg_map.live_range_id(n->in(k));
1932 if (lidx < _lrg_map.max_lrg_id()) {
1933 liveout.insert(lidx);
1934 }
1935 }
1936 }
1937
1938 } // End of forall instructions in block
1939 liveout.clear(); // Free the memory used by liveout.
1940
1941 } // End of forall blocks
1942 _lrg_map.set_max_lrg_id(maxlrg);
1943
1944 // If I created a new live range I need to recompute live
1945 if (maxlrg != _ifg->_maxlrg) {
1946 must_recompute_live = true;
1947 }
1948
1949 return must_recompute_live != 0;
1950 }
1951
1952 // Extend the node to LRG mapping
1953
1954 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) {
1955 _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node));
1956 }
1957
1958 #ifndef PRODUCT
1959 void PhaseChaitin::dump(const Node *n) const {
1960 uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0;
1961 tty->print("L%d",r);
1962 if (r && n->Opcode() != Op_Phi) {
1963 if( _node_regs ) { // Got a post-allocation copy of allocation?
1964 tty->print("[");
1965 OptoReg::Name second = get_reg_second(n);
1966 if( OptoReg::is_valid(second) ) {
1967 if( OptoReg::is_reg(second) )
1968 tty->print("%s:",Matcher::regName[second]);
1969 else
1970 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second));
1971 }
1972 OptoReg::Name first = get_reg_first(n);
1973 if( OptoReg::is_reg(first) )
1974 tty->print("%s]",Matcher::regName[first]);
1975 else
1976 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first));
1977 } else
1978 n->out_RegMask().dump();
1979 }
1980 tty->print("/N%d\t",n->_idx);
1981 tty->print("%s === ", n->Name());
1982 uint k;
1983 for (k = 0; k < n->req(); k++) {
1984 Node *m = n->in(k);
1985 if (!m) {
1986 tty->print("_ ");
1987 }
1988 else {
1989 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1990 tty->print("L%d",r);
1991 // Data MultiNode's can have projections with no real registers.
1992 // Don't die while dumping them.
1993 int op = n->Opcode();
1994 if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) {
1995 if( _node_regs ) {
1996 tty->print("[");
1997 OptoReg::Name second = get_reg_second(n->in(k));
1998 if( OptoReg::is_valid(second) ) {
1999 if( OptoReg::is_reg(second) )
2000 tty->print("%s:",Matcher::regName[second]);
2001 else
2002 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer),
2003 reg2offset_unchecked(second));
2004 }
2005 OptoReg::Name first = get_reg_first(n->in(k));
2006 if( OptoReg::is_reg(first) )
2007 tty->print("%s]",Matcher::regName[first]);
2008 else
2009 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer),
2010 reg2offset_unchecked(first));
2011 } else
2012 n->in_RegMask(k).dump();
2013 }
2014 tty->print("/N%d ",m->_idx);
2015 }
2016 }
2017 if( k < n->len() && n->in(k) ) tty->print("| ");
2018 for( ; k < n->len(); k++ ) {
2019 Node *m = n->in(k);
2020 if(!m) {
2021 break;
2022 }
2023 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
2024 tty->print("L%d",r);
2025 tty->print("/N%d ",m->_idx);
2026 }
2027 if( n->is_Mach() ) n->as_Mach()->dump_spec(tty);
2028 else n->dump_spec(tty);
2029 if( _spilled_once.test(n->_idx ) ) {
2030 tty->print(" Spill_1");
2031 if( _spilled_twice.test(n->_idx ) )
2032 tty->print(" Spill_2");
2033 }
2034 tty->print("\n");
2035 }
2036
2037 void PhaseChaitin::dump(const Block *b) const {
2038 b->dump_head(&_cfg);
2039
2040 // For all instructions
2041 for( uint j = 0; j < b->number_of_nodes(); j++ )
2042 dump(b->get_node(j));
2043 // Print live-out info at end of block
2044 if( _live ) {
2045 tty->print("Liveout: ");
2046 IndexSet *live = _live->live(b);
2047 IndexSetIterator elements(live);
2048 tty->print("{");
2049 uint i;
2050 while ((i = elements.next()) != 0) {
2051 tty->print("L%d ", _lrg_map.find_const(i));
2052 }
2053 tty->print_cr("}");
2054 }
2055 tty->print("\n");
2056 }
2057
2058 void PhaseChaitin::dump() const {
2059 tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n",
2060 _matcher._new_SP, _framesize );
2061
2062 // For all blocks
2063 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2064 dump(_cfg.get_block(i));
2065 }
2066 // End of per-block dump
2067 tty->print("\n");
2068
2069 if (!_ifg) {
2070 tty->print("(No IFG.)\n");
2071 return;
2072 }
2073
2074 // Dump LRG array
2075 tty->print("--- Live RanGe Array ---\n");
2076 for (uint i2 = 1; i2 < _lrg_map.max_lrg_id(); i2++) {
2077 tty->print("L%d: ",i2);
2078 if (i2 < _ifg->_maxlrg) {
2079 lrgs(i2).dump();
2080 }
2081 else {
2082 tty->print_cr("new LRG");
2083 }
2084 }
2085 tty->cr();
2086
2087 // Dump lo-degree list
2088 tty->print("Lo degree: ");
2089 for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next )
2090 tty->print("L%d ",i3);
2091 tty->cr();
2092
2093 // Dump lo-stk-degree list
2094 tty->print("Lo stk degree: ");
2095 for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next )
2096 tty->print("L%d ",i4);
2097 tty->cr();
2098
2099 // Dump lo-degree list
2100 tty->print("Hi degree: ");
2101 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next )
2102 tty->print("L%d ",i5);
2103 tty->cr();
2104 }
2105
2106 void PhaseChaitin::dump_degree_lists() const {
2107 // Dump lo-degree list
2108 tty->print("Lo degree: ");
2109 for( uint i = _lo_degree; i; i = lrgs(i)._next )
2110 tty->print("L%d ",i);
2111 tty->cr();
2112
2113 // Dump lo-stk-degree list
2114 tty->print("Lo stk degree: ");
2115 for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next )
2116 tty->print("L%d ",i2);
2117 tty->cr();
2118
2119 // Dump lo-degree list
2120 tty->print("Hi degree: ");
2121 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next )
2122 tty->print("L%d ",i3);
2123 tty->cr();
2124 }
2125
2126 void PhaseChaitin::dump_simplified() const {
2127 tty->print("Simplified: ");
2128 for( uint i = _simplified; i; i = lrgs(i)._next )
2129 tty->print("L%d ",i);
2130 tty->cr();
2131 }
2132
2133 static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) {
2134 if ((int)reg < 0)
2135 sprintf(buf, "<OptoReg::%d>", (int)reg);
2136 else if (OptoReg::is_reg(reg))
2137 strcpy(buf, Matcher::regName[reg]);
2138 else
2139 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer),
2140 pc->reg2offset(reg));
2141 return buf+strlen(buf);
2142 }
2143
2144 // Dump a register name into a buffer. Be intelligent if we get called
2145 // before allocation is complete.
2146 char *PhaseChaitin::dump_register( const Node *n, char *buf ) const {
2147 if( this == NULL ) { // Not got anything?
2148 sprintf(buf,"N%d",n->_idx); // Then use Node index
2149 } else if( _node_regs ) {
2150 // Post allocation, use direct mappings, no LRG info available
2151 print_reg( get_reg_first(n), this, buf );
2152 } else {
2153 uint lidx = _lrg_map.find_const(n); // Grab LRG number
2154 if( !_ifg ) {
2155 sprintf(buf,"L%d",lidx); // No register binding yet
2156 } else if( !lidx ) { // Special, not allocated value
2157 strcpy(buf,"Special");
2158 } else {
2159 if (lrgs(lidx)._is_vector) {
2160 if (lrgs(lidx).mask().is_bound_set(lrgs(lidx).num_regs()))
2161 print_reg( lrgs(lidx).reg(), this, buf ); // a bound machine register
2162 else
2163 sprintf(buf,"L%d",lidx); // No register binding yet
2164 } else if( (lrgs(lidx).num_regs() == 1)
2165 ? lrgs(lidx).mask().is_bound1()
2166 : lrgs(lidx).mask().is_bound_pair() ) {
2167 // Hah! We have a bound machine register
2168 print_reg( lrgs(lidx).reg(), this, buf );
2169 } else {
2170 sprintf(buf,"L%d",lidx); // No register binding yet
2171 }
2172 }
2173 }
2174 return buf+strlen(buf);
2175 }
2176
2177 void PhaseChaitin::dump_for_spill_split_recycle() const {
2178 if( WizardMode && (PrintCompilation || PrintOpto) ) {
2179 // Display which live ranges need to be split and the allocator's state
2180 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt);
2181 for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) {
2182 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) {
2183 tty->print("L%d: ", bidx);
2184 lrgs(bidx).dump();
2185 }
2186 }
2187 tty->cr();
2188 dump();
2189 }
2190 }
2191
2192 void PhaseChaitin::dump_frame() const {
2193 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer);
2194 const TypeTuple *domain = C->tf()->domain();
2195 const int argcnt = domain->cnt() - TypeFunc::Parms;
2196
2197 // Incoming arguments in registers dump
2198 for( int k = 0; k < argcnt; k++ ) {
2199 OptoReg::Name parmreg = _matcher._parm_regs[k].first();
2200 if( OptoReg::is_reg(parmreg)) {
2201 const char *reg_name = OptoReg::regname(parmreg);
2202 tty->print("#r%3.3d %s", parmreg, reg_name);
2203 parmreg = _matcher._parm_regs[k].second();
2204 if( OptoReg::is_reg(parmreg)) {
2205 tty->print(":%s", OptoReg::regname(parmreg));
2206 }
2207 tty->print(" : parm %d: ", k);
2208 domain->field_at(k + TypeFunc::Parms)->dump();
2209 tty->cr();
2210 }
2211 }
2212
2213 // Check for un-owned padding above incoming args
2214 OptoReg::Name reg = _matcher._new_SP;
2215 if( reg > _matcher._in_arg_limit ) {
2216 reg = OptoReg::add(reg, -1);
2217 tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg));
2218 }
2219
2220 // Incoming argument area dump
2221 OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots());
2222 while( reg > begin_in_arg ) {
2223 reg = OptoReg::add(reg, -1);
2224 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
2225 int j;
2226 for( j = 0; j < argcnt; j++) {
2227 if( _matcher._parm_regs[j].first() == reg ||
2228 _matcher._parm_regs[j].second() == reg ) {
2229 tty->print("parm %d: ",j);
2230 domain->field_at(j + TypeFunc::Parms)->dump();
2231 tty->cr();
2232 break;
2233 }
2234 }
2235 if( j >= argcnt )
2236 tty->print_cr("HOLE, owned by SELF");
2237 }
2238
2239 // Old outgoing preserve area
2240 while( reg > _matcher._old_SP ) {
2241 reg = OptoReg::add(reg, -1);
2242 tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg));
2243 }
2244
2245 // Old SP
2246 tty->print_cr("# -- Old %s -- Framesize: %d --",fp,
2247 reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize);
2248
2249 // Preserve area dump
2250 int fixed_slots = C->fixed_slots();
2251 OptoReg::Name begin_in_preserve = OptoReg::add(_matcher._old_SP, -(int)C->in_preserve_stack_slots());
2252 OptoReg::Name return_addr = _matcher.return_addr();
2253
2254 reg = OptoReg::add(reg, -1);
2255 while (OptoReg::is_stack(reg)) {
2256 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
2257 if (return_addr == reg) {
2258 tty->print_cr("return address");
2259 } else if (reg >= begin_in_preserve) {
2260 // Preserved slots are present on x86
2261 if (return_addr == OptoReg::add(reg, VMRegImpl::slots_per_word))
2262 tty->print_cr("saved fp register");
2263 else if (return_addr == OptoReg::add(reg, 2*VMRegImpl::slots_per_word) &&
2264 VerifyStackAtCalls)
2265 tty->print_cr("0xBADB100D +VerifyStackAtCalls");
2266 else
2267 tty->print_cr("in_preserve");
2268 } else if ((int)OptoReg::reg2stack(reg) < fixed_slots) {
2269 tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg));
2270 } else {
2271 tty->print_cr("pad2, stack alignment");
2272 }
2273 reg = OptoReg::add(reg, -1);
2274 }
2275
2276 // Spill area dump
2277 reg = OptoReg::add(_matcher._new_SP, _framesize );
2278 while( reg > _matcher._out_arg_limit ) {
2279 reg = OptoReg::add(reg, -1);
2280 tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg));
2281 }
2282
2283 // Outgoing argument area dump
2284 while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) {
2285 reg = OptoReg::add(reg, -1);
2286 tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg));
2287 }
2288
2289 // Outgoing new preserve area
2290 while( reg > _matcher._new_SP ) {
2291 reg = OptoReg::add(reg, -1);
2292 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg));
2293 }
2294 tty->print_cr("#");
2295 }
2296
2297 void PhaseChaitin::dump_bb( uint pre_order ) const {
2298 tty->print_cr("---dump of B%d---",pre_order);
2299 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2300 Block* block = _cfg.get_block(i);
2301 if (block->_pre_order == pre_order) {
2302 dump(block);
2303 }
2304 }
2305 }
2306
2307 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const {
2308 tty->print_cr("---dump of L%d---",lidx);
2309
2310 if (_ifg) {
2311 if (lidx >= _lrg_map.max_lrg_id()) {
2312 tty->print("Attempt to print live range index beyond max live range.\n");
2313 return;
2314 }
2315 tty->print("L%d: ",lidx);
2316 if (lidx < _ifg->_maxlrg) {
2317 lrgs(lidx).dump();
2318 } else {
2319 tty->print_cr("new LRG");
2320 }
2321 }
2322 if( _ifg && lidx < _ifg->_maxlrg) {
2323 tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx));
2324 _ifg->neighbors(lidx)->dump();
2325 tty->cr();
2326 }
2327 // For all blocks
2328 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2329 Block* block = _cfg.get_block(i);
2330 int dump_once = 0;
2331
2332 // For all instructions
2333 for( uint j = 0; j < block->number_of_nodes(); j++ ) {
2334 Node *n = block->get_node(j);
2335 if (_lrg_map.find_const(n) == lidx) {
2336 if (!dump_once++) {
2337 tty->cr();
2338 block->dump_head(&_cfg);
2339 }
2340 dump(n);
2341 continue;
2342 }
2343 if (!defs_only) {
2344 uint cnt = n->req();
2345 for( uint k = 1; k < cnt; k++ ) {
2346 Node *m = n->in(k);
2347 if (!m) {
2348 continue; // be robust in the dumper
2349 }
2350 if (_lrg_map.find_const(m) == lidx) {
2351 if (!dump_once++) {
2352 tty->cr();
2353 block->dump_head(&_cfg);
2354 }
2355 dump(n);
2356 }
2357 }
2358 }
2359 }
2360 } // End of per-block dump
2361 tty->cr();
2362 }
2363 #endif // not PRODUCT
2364
2365 int PhaseChaitin::_final_loads = 0;
2366 int PhaseChaitin::_final_stores = 0;
2367 int PhaseChaitin::_final_memoves= 0;
2368 int PhaseChaitin::_final_copies = 0;
2369 double PhaseChaitin::_final_load_cost = 0;
2370 double PhaseChaitin::_final_store_cost = 0;
2371 double PhaseChaitin::_final_memove_cost= 0;
2372 double PhaseChaitin::_final_copy_cost = 0;
2373 int PhaseChaitin::_conserv_coalesce = 0;
2374 int PhaseChaitin::_conserv_coalesce_pair = 0;
2375 int PhaseChaitin::_conserv_coalesce_trie = 0;
2376 int PhaseChaitin::_conserv_coalesce_quad = 0;
2377 int PhaseChaitin::_post_alloc = 0;
2378 int PhaseChaitin::_lost_opp_pp_coalesce = 0;
2379 int PhaseChaitin::_lost_opp_cflow_coalesce = 0;
2380 int PhaseChaitin::_used_cisc_instructions = 0;
2381 int PhaseChaitin::_unused_cisc_instructions = 0;
2382 int PhaseChaitin::_allocator_attempts = 0;
2383 int PhaseChaitin::_allocator_successes = 0;
2384
2385 #ifndef PRODUCT
2386 uint PhaseChaitin::_high_pressure = 0;
2387 uint PhaseChaitin::_low_pressure = 0;
2388
2389 void PhaseChaitin::print_chaitin_statistics() {
2390 tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies);
2391 tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost);
2392 tty->print_cr("Adjusted spill cost = %7.0f.",
2393 _final_load_cost*4.0 + _final_store_cost * 2.0 +
2394 _final_copy_cost*1.0 + _final_memove_cost*12.0);
2395 tty->print("Conservatively coalesced %d copies, %d pairs",
2396 _conserv_coalesce, _conserv_coalesce_pair);
2397 if( _conserv_coalesce_trie || _conserv_coalesce_quad )
2398 tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad);
2399 tty->print_cr(", %d post alloc.", _post_alloc);
2400 if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce )
2401 tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.",
2402 _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce );
2403 if( _used_cisc_instructions || _unused_cisc_instructions )
2404 tty->print_cr("Used cisc instruction %d, remained in register %d",
2405 _used_cisc_instructions, _unused_cisc_instructions);
2406 if( _allocator_successes != 0 )
2407 tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes);
2408 tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure);
2409 }
2410 #endif // not PRODUCT