1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/ad.hpp"
28 #include "opto/addnode.hpp"
29 #include "opto/callnode.hpp"
30 #include "opto/idealGraphPrinter.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/memnode.hpp"
33 #include "opto/movenode.hpp"
34 #include "opto/opcodes.hpp"
35 #include "opto/regmask.hpp"
36 #include "opto/rootnode.hpp"
37 #include "opto/runtime.hpp"
38 #include "opto/type.hpp"
39 #include "opto/vectornode.hpp"
40 #include "runtime/os.hpp"
41 #include "runtime/sharedRuntime.hpp"
42
43 OptoReg::Name OptoReg::c_frame_pointer;
44
45 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
46 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
47 RegMask Matcher::STACK_ONLY_mask;
48 RegMask Matcher::c_frame_ptr_mask;
49 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
50 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
51
52 //---------------------------Matcher-------------------------------------------
53 Matcher::Matcher()
54 : PhaseTransform( Phase::Ins_Select ),
55 #ifdef ASSERT
56 _old2new_map(C->comp_arena()),
57 _new2old_map(C->comp_arena()),
58 #endif
59 _shared_nodes(C->comp_arena()),
60 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
61 _swallowed(swallowed),
62 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
63 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
64 _must_clone(must_clone),
65 _register_save_policy(register_save_policy),
66 _c_reg_save_policy(c_reg_save_policy),
67 _register_save_type(register_save_type),
68 _ruleName(ruleName),
69 _allocation_started(false),
70 _states_arena(Chunk::medium_size),
71 _visited(&_states_arena),
72 _shared(&_states_arena),
73 _dontcare(&_states_arena) {
74 C->set_matcher(this);
75
76 idealreg2spillmask [Op_RegI] = NULL;
77 idealreg2spillmask [Op_RegN] = NULL;
78 idealreg2spillmask [Op_RegL] = NULL;
79 idealreg2spillmask [Op_RegF] = NULL;
80 idealreg2spillmask [Op_RegD] = NULL;
81 idealreg2spillmask [Op_RegP] = NULL;
82 idealreg2spillmask [Op_VecS] = NULL;
83 idealreg2spillmask [Op_VecD] = NULL;
84 idealreg2spillmask [Op_VecX] = NULL;
85 idealreg2spillmask [Op_VecY] = NULL;
86
87 idealreg2debugmask [Op_RegI] = NULL;
88 idealreg2debugmask [Op_RegN] = NULL;
89 idealreg2debugmask [Op_RegL] = NULL;
90 idealreg2debugmask [Op_RegF] = NULL;
91 idealreg2debugmask [Op_RegD] = NULL;
92 idealreg2debugmask [Op_RegP] = NULL;
93 idealreg2debugmask [Op_VecS] = NULL;
94 idealreg2debugmask [Op_VecD] = NULL;
95 idealreg2debugmask [Op_VecX] = NULL;
96 idealreg2debugmask [Op_VecY] = NULL;
97
98 idealreg2mhdebugmask[Op_RegI] = NULL;
99 idealreg2mhdebugmask[Op_RegN] = NULL;
100 idealreg2mhdebugmask[Op_RegL] = NULL;
101 idealreg2mhdebugmask[Op_RegF] = NULL;
102 idealreg2mhdebugmask[Op_RegD] = NULL;
103 idealreg2mhdebugmask[Op_RegP] = NULL;
104 idealreg2mhdebugmask[Op_VecS] = NULL;
105 idealreg2mhdebugmask[Op_VecD] = NULL;
106 idealreg2mhdebugmask[Op_VecX] = NULL;
107 idealreg2mhdebugmask[Op_VecY] = NULL;
108
109 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
110 }
111
112 //------------------------------warp_incoming_stk_arg------------------------
113 // This warps a VMReg into an OptoReg::Name
114 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
115 OptoReg::Name warped;
116 if( reg->is_stack() ) { // Stack slot argument?
117 warped = OptoReg::add(_old_SP, reg->reg2stack() );
118 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
119 if( warped >= _in_arg_limit )
120 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
121 if (!RegMask::can_represent_arg(warped)) {
122 // the compiler cannot represent this method's calling sequence
123 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
124 return OptoReg::Bad;
125 }
126 return warped;
127 }
128 return OptoReg::as_OptoReg(reg);
129 }
130
131 //---------------------------compute_old_SP------------------------------------
132 OptoReg::Name Compile::compute_old_SP() {
133 int fixed = fixed_slots();
134 int preserve = in_preserve_stack_slots();
135 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
136 }
137
138
139
140 #ifdef ASSERT
141 void Matcher::verify_new_nodes_only(Node* xroot) {
142 // Make sure that the new graph only references new nodes
143 ResourceMark rm;
144 Unique_Node_List worklist;
145 VectorSet visited(Thread::current()->resource_area());
146 worklist.push(xroot);
147 while (worklist.size() > 0) {
148 Node* n = worklist.pop();
149 visited <<= n->_idx;
150 assert(C->node_arena()->contains(n), "dead node");
151 for (uint j = 0; j < n->req(); j++) {
152 Node* in = n->in(j);
153 if (in != NULL) {
154 assert(C->node_arena()->contains(in), "dead node");
155 if (!visited.test(in->_idx)) {
156 worklist.push(in);
157 }
158 }
159 }
160 }
161 }
162 #endif
163
164
165 //---------------------------match---------------------------------------------
166 void Matcher::match( ) {
167 if( MaxLabelRootDepth < 100 ) { // Too small?
168 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
169 MaxLabelRootDepth = 100;
170 }
171 // One-time initialization of some register masks.
172 init_spill_mask( C->root()->in(1) );
173 _return_addr_mask = return_addr();
174 #ifdef _LP64
175 // Pointers take 2 slots in 64-bit land
176 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
177 #endif
178
179 // Map a Java-signature return type into return register-value
180 // machine registers for 0, 1 and 2 returned values.
181 const TypeTuple *range = C->tf()->range();
182 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
183 // Get ideal-register return type
184 int ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
185 // Get machine return register
186 uint sop = C->start()->Opcode();
187 OptoRegPair regs = return_value(ireg, false);
188
189 // And mask for same
190 _return_value_mask = RegMask(regs.first());
191 if( OptoReg::is_valid(regs.second()) )
192 _return_value_mask.Insert(regs.second());
193 }
194
195 // ---------------
196 // Frame Layout
197
198 // Need the method signature to determine the incoming argument types,
199 // because the types determine which registers the incoming arguments are
200 // in, and this affects the matched code.
201 const TypeTuple *domain = C->tf()->domain();
202 uint argcnt = domain->cnt() - TypeFunc::Parms;
203 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
204 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
205 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
206 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
207 uint i;
208 for( i = 0; i<argcnt; i++ ) {
209 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
210 }
211
212 // Pass array of ideal registers and length to USER code (from the AD file)
213 // that will convert this to an array of register numbers.
214 const StartNode *start = C->start();
215 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
216 #ifdef ASSERT
217 // Sanity check users' calling convention. Real handy while trying to
218 // get the initial port correct.
219 { for (uint i = 0; i<argcnt; i++) {
220 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
221 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
222 _parm_regs[i].set_bad();
223 continue;
224 }
225 VMReg parm_reg = vm_parm_regs[i].first();
226 assert(parm_reg->is_valid(), "invalid arg?");
227 if (parm_reg->is_reg()) {
228 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
229 assert(can_be_java_arg(opto_parm_reg) ||
230 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
231 opto_parm_reg == inline_cache_reg(),
232 "parameters in register must be preserved by runtime stubs");
233 }
234 for (uint j = 0; j < i; j++) {
235 assert(parm_reg != vm_parm_regs[j].first(),
236 "calling conv. must produce distinct regs");
237 }
238 }
239 }
240 #endif
241
242 // Do some initial frame layout.
243
244 // Compute the old incoming SP (may be called FP) as
245 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
246 _old_SP = C->compute_old_SP();
247 assert( is_even(_old_SP), "must be even" );
248
249 // Compute highest incoming stack argument as
250 // _old_SP + out_preserve_stack_slots + incoming argument size.
251 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
252 assert( is_even(_in_arg_limit), "out_preserve must be even" );
253 for( i = 0; i < argcnt; i++ ) {
254 // Permit args to have no register
255 _calling_convention_mask[i].Clear();
256 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
257 continue;
258 }
259 // calling_convention returns stack arguments as a count of
260 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
261 // the allocators point of view, taking into account all the
262 // preserve area, locks & pad2.
263
264 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
265 if( OptoReg::is_valid(reg1))
266 _calling_convention_mask[i].Insert(reg1);
267
268 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
269 if( OptoReg::is_valid(reg2))
270 _calling_convention_mask[i].Insert(reg2);
271
272 // Saved biased stack-slot register number
273 _parm_regs[i].set_pair(reg2, reg1);
274 }
275
276 // Finally, make sure the incoming arguments take up an even number of
277 // words, in case the arguments or locals need to contain doubleword stack
278 // slots. The rest of the system assumes that stack slot pairs (in
279 // particular, in the spill area) which look aligned will in fact be
280 // aligned relative to the stack pointer in the target machine. Double
281 // stack slots will always be allocated aligned.
282 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
283
284 // Compute highest outgoing stack argument as
285 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
286 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
287 assert( is_even(_out_arg_limit), "out_preserve must be even" );
288
289 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
290 // the compiler cannot represent this method's calling sequence
291 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
292 }
293
294 if (C->failing()) return; // bailed out on incoming arg failure
295
296 // ---------------
297 // Collect roots of matcher trees. Every node for which
298 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
299 // can be a valid interior of some tree.
300 find_shared( C->root() );
301 find_shared( C->top() );
302
303 C->print_method(PHASE_BEFORE_MATCHING);
304
305 // Create new ideal node ConP #NULL even if it does exist in old space
306 // to avoid false sharing if the corresponding mach node is not used.
307 // The corresponding mach node is only used in rare cases for derived
308 // pointers.
309 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR);
310
311 // Swap out to old-space; emptying new-space
312 Arena *old = C->node_arena()->move_contents(C->old_arena());
313
314 // Save debug and profile information for nodes in old space:
315 _old_node_note_array = C->node_note_array();
316 if (_old_node_note_array != NULL) {
317 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
318 (C->comp_arena(), _old_node_note_array->length(),
319 0, NULL));
320 }
321
322 // Pre-size the new_node table to avoid the need for range checks.
323 grow_new_node_array(C->unique());
324
325 // Reset node counter so MachNodes start with _idx at 0
326 int nodes = C->unique(); // save value
327 C->set_unique(0);
328 C->reset_dead_node_list();
329
330 // Recursively match trees from old space into new space.
331 // Correct leaves of new-space Nodes; they point to old-space.
332 _visited.Clear(); // Clear visit bits for xform call
333 C->set_cached_top_node(xform( C->top(), nodes ));
334 if (!C->failing()) {
335 Node* xroot = xform( C->root(), 1 );
336 if (xroot == NULL) {
337 Matcher::soft_match_failure(); // recursive matching process failed
338 C->record_method_not_compilable("instruction match failed");
339 } else {
340 // During matching shared constants were attached to C->root()
341 // because xroot wasn't available yet, so transfer the uses to
342 // the xroot.
343 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
344 Node* n = C->root()->fast_out(j);
345 if (C->node_arena()->contains(n)) {
346 assert(n->in(0) == C->root(), "should be control user");
347 n->set_req(0, xroot);
348 --j;
349 --jmax;
350 }
351 }
352
353 // Generate new mach node for ConP #NULL
354 assert(new_ideal_null != NULL, "sanity");
355 _mach_null = match_tree(new_ideal_null);
356 // Don't set control, it will confuse GCM since there are no uses.
357 // The control will be set when this node is used first time
358 // in find_base_for_derived().
359 assert(_mach_null != NULL, "");
360
361 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
362
363 #ifdef ASSERT
364 verify_new_nodes_only(xroot);
365 #endif
366 }
367 }
368 if (C->top() == NULL || C->root() == NULL) {
369 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
370 }
371 if (C->failing()) {
372 // delete old;
373 old->destruct_contents();
374 return;
375 }
376 assert( C->top(), "" );
377 assert( C->root(), "" );
378 validate_null_checks();
379
380 // Now smoke old-space
381 NOT_DEBUG( old->destruct_contents() );
382
383 // ------------------------
384 // Set up save-on-entry registers
385 Fixup_Save_On_Entry( );
386 }
387
388
389 //------------------------------Fixup_Save_On_Entry----------------------------
390 // The stated purpose of this routine is to take care of save-on-entry
391 // registers. However, the overall goal of the Match phase is to convert into
392 // machine-specific instructions which have RegMasks to guide allocation.
393 // So what this procedure really does is put a valid RegMask on each input
394 // to the machine-specific variations of all Return, TailCall and Halt
395 // instructions. It also adds edgs to define the save-on-entry values (and of
396 // course gives them a mask).
397
398 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
399 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
400 // Do all the pre-defined register masks
401 rms[TypeFunc::Control ] = RegMask::Empty;
402 rms[TypeFunc::I_O ] = RegMask::Empty;
403 rms[TypeFunc::Memory ] = RegMask::Empty;
404 rms[TypeFunc::ReturnAdr] = ret_adr;
405 rms[TypeFunc::FramePtr ] = fp;
406 return rms;
407 }
408
409 //---------------------------init_first_stack_mask-----------------------------
410 // Create the initial stack mask used by values spilling to the stack.
411 // Disallow any debug info in outgoing argument areas by setting the
412 // initial mask accordingly.
413 void Matcher::init_first_stack_mask() {
414
415 // Allocate storage for spill masks as masks for the appropriate load type.
416 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+4));
417
418 idealreg2spillmask [Op_RegN] = &rms[0];
419 idealreg2spillmask [Op_RegI] = &rms[1];
420 idealreg2spillmask [Op_RegL] = &rms[2];
421 idealreg2spillmask [Op_RegF] = &rms[3];
422 idealreg2spillmask [Op_RegD] = &rms[4];
423 idealreg2spillmask [Op_RegP] = &rms[5];
424
425 idealreg2debugmask [Op_RegN] = &rms[6];
426 idealreg2debugmask [Op_RegI] = &rms[7];
427 idealreg2debugmask [Op_RegL] = &rms[8];
428 idealreg2debugmask [Op_RegF] = &rms[9];
429 idealreg2debugmask [Op_RegD] = &rms[10];
430 idealreg2debugmask [Op_RegP] = &rms[11];
431
432 idealreg2mhdebugmask[Op_RegN] = &rms[12];
433 idealreg2mhdebugmask[Op_RegI] = &rms[13];
434 idealreg2mhdebugmask[Op_RegL] = &rms[14];
435 idealreg2mhdebugmask[Op_RegF] = &rms[15];
436 idealreg2mhdebugmask[Op_RegD] = &rms[16];
437 idealreg2mhdebugmask[Op_RegP] = &rms[17];
438
439 idealreg2spillmask [Op_VecS] = &rms[18];
440 idealreg2spillmask [Op_VecD] = &rms[19];
441 idealreg2spillmask [Op_VecX] = &rms[20];
442 idealreg2spillmask [Op_VecY] = &rms[21];
443
444 OptoReg::Name i;
445
446 // At first, start with the empty mask
447 C->FIRST_STACK_mask().Clear();
448
449 // Add in the incoming argument area
450 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
451 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
452 C->FIRST_STACK_mask().Insert(i);
453 }
454 // Add in all bits past the outgoing argument area
455 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
456 "must be able to represent all call arguments in reg mask");
457 OptoReg::Name init = _out_arg_limit;
458 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
459 C->FIRST_STACK_mask().Insert(i);
460 }
461 // Finally, set the "infinite stack" bit.
462 C->FIRST_STACK_mask().set_AllStack();
463
464 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
465 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
466 // Keep spill masks aligned.
467 aligned_stack_mask.clear_to_pairs();
468 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
469
470 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
471 #ifdef _LP64
472 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
473 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
474 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
475 #else
476 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
477 #endif
478 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
479 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
480 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
481 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
482 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
483 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
484 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
485 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
486
487 if (Matcher::vector_size_supported(T_BYTE,4)) {
488 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
489 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
490 }
491 if (Matcher::vector_size_supported(T_FLOAT,2)) {
492 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
493 // RA guarantees such alignment since it is needed for Double and Long values.
494 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
495 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
496 }
497 if (Matcher::vector_size_supported(T_FLOAT,4)) {
498 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
499 //
500 // RA can use input arguments stack slots for spills but until RA
501 // we don't know frame size and offset of input arg stack slots.
502 //
503 // Exclude last input arg stack slots to avoid spilling vectors there
504 // otherwise vector spills could stomp over stack slots in caller frame.
505 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
506 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
507 aligned_stack_mask.Remove(in);
508 in = OptoReg::add(in, -1);
509 }
510 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
511 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
512 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
513 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
514 }
515 if (Matcher::vector_size_supported(T_FLOAT,8)) {
516 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
517 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
518 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
519 aligned_stack_mask.Remove(in);
520 in = OptoReg::add(in, -1);
521 }
522 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
523 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
524 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
525 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
526 }
527 if (UseFPUForSpilling) {
528 // This mask logic assumes that the spill operations are
529 // symmetric and that the registers involved are the same size.
530 // On sparc for instance we may have to use 64 bit moves will
531 // kill 2 registers when used with F0-F31.
532 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
533 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
534 #ifdef _LP64
535 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
536 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
537 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
538 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
539 #else
540 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
541 #ifdef ARM
542 // ARM has support for moving 64bit values between a pair of
543 // integer registers and a double register
544 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
545 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
546 #endif
547 #endif
548 }
549
550 // Make up debug masks. Any spill slot plus callee-save registers.
551 // Caller-save registers are assumed to be trashable by the various
552 // inline-cache fixup routines.
553 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
554 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
555 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
556 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
557 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
558 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
559
560 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
561 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
562 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
563 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
564 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
565 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
566
567 // Prevent stub compilations from attempting to reference
568 // callee-saved registers from debug info
569 bool exclude_soe = !Compile::current()->is_method_compilation();
570
571 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
572 // registers the caller has to save do not work
573 if( _register_save_policy[i] == 'C' ||
574 _register_save_policy[i] == 'A' ||
575 (_register_save_policy[i] == 'E' && exclude_soe) ) {
576 idealreg2debugmask [Op_RegN]->Remove(i);
577 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
578 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
579 idealreg2debugmask [Op_RegF]->Remove(i); // masks
580 idealreg2debugmask [Op_RegD]->Remove(i);
581 idealreg2debugmask [Op_RegP]->Remove(i);
582
583 idealreg2mhdebugmask[Op_RegN]->Remove(i);
584 idealreg2mhdebugmask[Op_RegI]->Remove(i);
585 idealreg2mhdebugmask[Op_RegL]->Remove(i);
586 idealreg2mhdebugmask[Op_RegF]->Remove(i);
587 idealreg2mhdebugmask[Op_RegD]->Remove(i);
588 idealreg2mhdebugmask[Op_RegP]->Remove(i);
589 }
590 }
591
592 // Subtract the register we use to save the SP for MethodHandle
593 // invokes to from the debug mask.
594 const RegMask save_mask = method_handle_invoke_SP_save_mask();
595 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
596 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
597 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
598 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
599 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
600 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
601 }
602
603 //---------------------------is_save_on_entry----------------------------------
604 bool Matcher::is_save_on_entry( int reg ) {
605 return
606 _register_save_policy[reg] == 'E' ||
607 _register_save_policy[reg] == 'A' || // Save-on-entry register?
608 // Also save argument registers in the trampolining stubs
609 (C->save_argument_registers() && is_spillable_arg(reg));
610 }
611
612 //---------------------------Fixup_Save_On_Entry-------------------------------
613 void Matcher::Fixup_Save_On_Entry( ) {
614 init_first_stack_mask();
615
616 Node *root = C->root(); // Short name for root
617 // Count number of save-on-entry registers.
618 uint soe_cnt = number_of_saved_registers();
619 uint i;
620
621 // Find the procedure Start Node
622 StartNode *start = C->start();
623 assert( start, "Expect a start node" );
624
625 // Save argument registers in the trampolining stubs
626 if( C->save_argument_registers() )
627 for( i = 0; i < _last_Mach_Reg; i++ )
628 if( is_spillable_arg(i) )
629 soe_cnt++;
630
631 // Input RegMask array shared by all Returns.
632 // The type for doubles and longs has a count of 2, but
633 // there is only 1 returned value
634 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
635 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
636 // Returns have 0 or 1 returned values depending on call signature.
637 // Return register is specified by return_value in the AD file.
638 if (ret_edge_cnt > TypeFunc::Parms)
639 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
640
641 // Input RegMask array shared by all Rethrows.
642 uint reth_edge_cnt = TypeFunc::Parms+1;
643 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
644 // Rethrow takes exception oop only, but in the argument 0 slot.
645 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
646 #ifdef _LP64
647 // Need two slots for ptrs in 64-bit land
648 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
649 #endif
650
651 // Input RegMask array shared by all TailCalls
652 uint tail_call_edge_cnt = TypeFunc::Parms+2;
653 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
654
655 // Input RegMask array shared by all TailJumps
656 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
657 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
658
659 // TailCalls have 2 returned values (target & moop), whose masks come
660 // from the usual MachNode/MachOper mechanism. Find a sample
661 // TailCall to extract these masks and put the correct masks into
662 // the tail_call_rms array.
663 for( i=1; i < root->req(); i++ ) {
664 MachReturnNode *m = root->in(i)->as_MachReturn();
665 if( m->ideal_Opcode() == Op_TailCall ) {
666 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
667 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
668 break;
669 }
670 }
671
672 // TailJumps have 2 returned values (target & ex_oop), whose masks come
673 // from the usual MachNode/MachOper mechanism. Find a sample
674 // TailJump to extract these masks and put the correct masks into
675 // the tail_jump_rms array.
676 for( i=1; i < root->req(); i++ ) {
677 MachReturnNode *m = root->in(i)->as_MachReturn();
678 if( m->ideal_Opcode() == Op_TailJump ) {
679 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
680 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
681 break;
682 }
683 }
684
685 // Input RegMask array shared by all Halts
686 uint halt_edge_cnt = TypeFunc::Parms;
687 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
688
689 // Capture the return input masks into each exit flavor
690 for( i=1; i < root->req(); i++ ) {
691 MachReturnNode *exit = root->in(i)->as_MachReturn();
692 switch( exit->ideal_Opcode() ) {
693 case Op_Return : exit->_in_rms = ret_rms; break;
694 case Op_Rethrow : exit->_in_rms = reth_rms; break;
695 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
696 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
697 case Op_Halt : exit->_in_rms = halt_rms; break;
698 default : ShouldNotReachHere();
699 }
700 }
701
702 // Next unused projection number from Start.
703 int proj_cnt = C->tf()->domain()->cnt();
704
705 // Do all the save-on-entry registers. Make projections from Start for
706 // them, and give them a use at the exit points. To the allocator, they
707 // look like incoming register arguments.
708 for( i = 0; i < _last_Mach_Reg; i++ ) {
709 if( is_save_on_entry(i) ) {
710
711 // Add the save-on-entry to the mask array
712 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
713 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
714 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
715 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
716 // Halts need the SOE registers, but only in the stack as debug info.
717 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
718 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
719
720 Node *mproj;
721
722 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
723 // into a single RegD.
724 if( (i&1) == 0 &&
725 _register_save_type[i ] == Op_RegF &&
726 _register_save_type[i+1] == Op_RegF &&
727 is_save_on_entry(i+1) ) {
728 // Add other bit for double
729 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
730 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
731 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
732 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
733 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
734 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
735 proj_cnt += 2; // Skip 2 for doubles
736 }
737 else if( (i&1) == 1 && // Else check for high half of double
738 _register_save_type[i-1] == Op_RegF &&
739 _register_save_type[i ] == Op_RegF &&
740 is_save_on_entry(i-1) ) {
741 ret_rms [ ret_edge_cnt] = RegMask::Empty;
742 reth_rms [ reth_edge_cnt] = RegMask::Empty;
743 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
744 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
745 halt_rms [ halt_edge_cnt] = RegMask::Empty;
746 mproj = C->top();
747 }
748 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
749 // into a single RegL.
750 else if( (i&1) == 0 &&
751 _register_save_type[i ] == Op_RegI &&
752 _register_save_type[i+1] == Op_RegI &&
753 is_save_on_entry(i+1) ) {
754 // Add other bit for long
755 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
756 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
757 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
758 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
759 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
760 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
761 proj_cnt += 2; // Skip 2 for longs
762 }
763 else if( (i&1) == 1 && // Else check for high half of long
764 _register_save_type[i-1] == Op_RegI &&
765 _register_save_type[i ] == Op_RegI &&
766 is_save_on_entry(i-1) ) {
767 ret_rms [ ret_edge_cnt] = RegMask::Empty;
768 reth_rms [ reth_edge_cnt] = RegMask::Empty;
769 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
770 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
771 halt_rms [ halt_edge_cnt] = RegMask::Empty;
772 mproj = C->top();
773 } else {
774 // Make a projection for it off the Start
775 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
776 }
777
778 ret_edge_cnt ++;
779 reth_edge_cnt ++;
780 tail_call_edge_cnt ++;
781 tail_jump_edge_cnt ++;
782 halt_edge_cnt ++;
783
784 // Add a use of the SOE register to all exit paths
785 for( uint j=1; j < root->req(); j++ )
786 root->in(j)->add_req(mproj);
787 } // End of if a save-on-entry register
788 } // End of for all machine registers
789 }
790
791 //------------------------------init_spill_mask--------------------------------
792 void Matcher::init_spill_mask( Node *ret ) {
793 if( idealreg2regmask[Op_RegI] ) return; // One time only init
794
795 OptoReg::c_frame_pointer = c_frame_pointer();
796 c_frame_ptr_mask = c_frame_pointer();
797 #ifdef _LP64
798 // pointers are twice as big
799 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
800 #endif
801
802 // Start at OptoReg::stack0()
803 STACK_ONLY_mask.Clear();
804 OptoReg::Name init = OptoReg::stack2reg(0);
805 // STACK_ONLY_mask is all stack bits
806 OptoReg::Name i;
807 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
808 STACK_ONLY_mask.Insert(i);
809 // Also set the "infinite stack" bit.
810 STACK_ONLY_mask.set_AllStack();
811
812 // Copy the register names over into the shared world
813 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
814 // SharedInfo::regName[i] = regName[i];
815 // Handy RegMasks per machine register
816 mreg2regmask[i].Insert(i);
817 }
818
819 // Grab the Frame Pointer
820 Node *fp = ret->in(TypeFunc::FramePtr);
821 Node *mem = ret->in(TypeFunc::Memory);
822 const TypePtr* atp = TypePtr::BOTTOM;
823 // Share frame pointer while making spill ops
824 set_shared(fp);
825
826 // Compute generic short-offset Loads
827 #ifdef _LP64
828 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
829 #endif
830 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
831 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered,false));
832 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
833 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
834 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
835 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
836 spillD != NULL && spillP != NULL, "");
837 // Get the ADLC notion of the right regmask, for each basic type.
838 #ifdef _LP64
839 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
840 #endif
841 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
842 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
843 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
844 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
845 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
846
847 // Vector regmasks.
848 if (Matcher::vector_size_supported(T_BYTE,4)) {
849 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
850 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
851 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
852 }
853 if (Matcher::vector_size_supported(T_FLOAT,2)) {
854 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
855 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
856 }
857 if (Matcher::vector_size_supported(T_FLOAT,4)) {
858 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
859 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
860 }
861 if (Matcher::vector_size_supported(T_FLOAT,8)) {
862 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
863 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
864 }
865 }
866
867 #ifdef ASSERT
868 static void match_alias_type(Compile* C, Node* n, Node* m) {
869 if (!VerifyAliases) return; // do not go looking for trouble by default
870 const TypePtr* nat = n->adr_type();
871 const TypePtr* mat = m->adr_type();
872 int nidx = C->get_alias_index(nat);
873 int midx = C->get_alias_index(mat);
874 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
875 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
876 for (uint i = 1; i < n->req(); i++) {
877 Node* n1 = n->in(i);
878 const TypePtr* n1at = n1->adr_type();
879 if (n1at != NULL) {
880 nat = n1at;
881 nidx = C->get_alias_index(n1at);
882 }
883 }
884 }
885 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
886 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
887 switch (n->Opcode()) {
888 case Op_PrefetchRead:
889 case Op_PrefetchWrite:
890 case Op_PrefetchAllocation:
891 nidx = Compile::AliasIdxRaw;
892 nat = TypeRawPtr::BOTTOM;
893 break;
894 }
895 }
896 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
897 switch (n->Opcode()) {
898 case Op_ClearArray:
899 midx = Compile::AliasIdxRaw;
900 mat = TypeRawPtr::BOTTOM;
901 break;
902 }
903 }
904 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
905 switch (n->Opcode()) {
906 case Op_Return:
907 case Op_Rethrow:
908 case Op_Halt:
909 case Op_TailCall:
910 case Op_TailJump:
911 nidx = Compile::AliasIdxBot;
912 nat = TypePtr::BOTTOM;
913 break;
914 }
915 }
916 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
917 switch (n->Opcode()) {
918 case Op_StrComp:
919 case Op_StrEquals:
920 case Op_StrIndexOf:
921 case Op_AryEq:
922 case Op_MemBarVolatile:
923 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
924 case Op_EncodeISOArray:
925 nidx = Compile::AliasIdxTop;
926 nat = NULL;
927 break;
928 }
929 }
930 if (nidx != midx) {
931 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
932 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
933 n->dump();
934 m->dump();
935 }
936 assert(C->subsume_loads() && C->must_alias(nat, midx),
937 "must not lose alias info when matching");
938 }
939 }
940 #endif
941
942
943 //------------------------------MStack-----------------------------------------
944 // State and MStack class used in xform() and find_shared() iterative methods.
945 enum Node_State { Pre_Visit, // node has to be pre-visited
946 Visit, // visit node
947 Post_Visit, // post-visit node
948 Alt_Post_Visit // alternative post-visit path
949 };
950
951 class MStack: public Node_Stack {
952 public:
953 MStack(int size) : Node_Stack(size) { }
954
955 void push(Node *n, Node_State ns) {
956 Node_Stack::push(n, (uint)ns);
957 }
958 void push(Node *n, Node_State ns, Node *parent, int indx) {
959 ++_inode_top;
960 if ((_inode_top + 1) >= _inode_max) grow();
961 _inode_top->node = parent;
962 _inode_top->indx = (uint)indx;
963 ++_inode_top;
964 _inode_top->node = n;
965 _inode_top->indx = (uint)ns;
966 }
967 Node *parent() {
968 pop();
969 return node();
970 }
971 Node_State state() const {
972 return (Node_State)index();
973 }
974 void set_state(Node_State ns) {
975 set_index((uint)ns);
976 }
977 };
978
979
980 //------------------------------xform------------------------------------------
981 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
982 // Node in new-space. Given a new-space Node, recursively walk his children.
983 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
984 Node *Matcher::xform( Node *n, int max_stack ) {
985 // Use one stack to keep both: child's node/state and parent's node/index
986 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2
987 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
988
989 while (mstack.is_nonempty()) {
990 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
991 if (C->failing()) return NULL;
992 n = mstack.node(); // Leave node on stack
993 Node_State nstate = mstack.state();
994 if (nstate == Visit) {
995 mstack.set_state(Post_Visit);
996 Node *oldn = n;
997 // Old-space or new-space check
998 if (!C->node_arena()->contains(n)) {
999 // Old space!
1000 Node* m;
1001 if (has_new_node(n)) { // Not yet Label/Reduced
1002 m = new_node(n);
1003 } else {
1004 if (!is_dontcare(n)) { // Matcher can match this guy
1005 // Calls match special. They match alone with no children.
1006 // Their children, the incoming arguments, match normally.
1007 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1008 if (C->failing()) return NULL;
1009 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1010 } else { // Nothing the matcher cares about
1011 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
1012 // Convert to machine-dependent projection
1013 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1014 #ifdef ASSERT
1015 _new2old_map.map(m->_idx, n);
1016 #endif
1017 if (m->in(0) != NULL) // m might be top
1018 collect_null_checks(m, n);
1019 } else { // Else just a regular 'ol guy
1020 m = n->clone(); // So just clone into new-space
1021 #ifdef ASSERT
1022 _new2old_map.map(m->_idx, n);
1023 #endif
1024 // Def-Use edges will be added incrementally as Uses
1025 // of this node are matched.
1026 assert(m->outcnt() == 0, "no Uses of this clone yet");
1027 }
1028 }
1029
1030 set_new_node(n, m); // Map old to new
1031 if (_old_node_note_array != NULL) {
1032 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1033 n->_idx);
1034 C->set_node_notes_at(m->_idx, nn);
1035 }
1036 debug_only(match_alias_type(C, n, m));
1037 }
1038 n = m; // n is now a new-space node
1039 mstack.set_node(n);
1040 }
1041
1042 // New space!
1043 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1044
1045 int i;
1046 // Put precedence edges on stack first (match them last).
1047 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1048 Node *m = oldn->in(i);
1049 if (m == NULL) break;
1050 // set -1 to call add_prec() instead of set_req() during Step1
1051 mstack.push(m, Visit, n, -1);
1052 }
1053
1054 // For constant debug info, I'd rather have unmatched constants.
1055 int cnt = n->req();
1056 JVMState* jvms = n->jvms();
1057 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1058
1059 // Now do only debug info. Clone constants rather than matching.
1060 // Constants are represented directly in the debug info without
1061 // the need for executable machine instructions.
1062 // Monitor boxes are also represented directly.
1063 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1064 Node *m = n->in(i); // Get input
1065 int op = m->Opcode();
1066 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1067 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1068 op == Op_ConF || op == Op_ConD || op == Op_ConL
1069 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1070 ) {
1071 m = m->clone();
1072 #ifdef ASSERT
1073 _new2old_map.map(m->_idx, n);
1074 #endif
1075 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1076 mstack.push(m->in(0), Visit, m, 0);
1077 } else {
1078 mstack.push(m, Visit, n, i);
1079 }
1080 }
1081
1082 // And now walk his children, and convert his inputs to new-space.
1083 for( ; i >= 0; --i ) { // For all normal inputs do
1084 Node *m = n->in(i); // Get input
1085 if(m != NULL)
1086 mstack.push(m, Visit, n, i);
1087 }
1088
1089 }
1090 else if (nstate == Post_Visit) {
1091 // Set xformed input
1092 Node *p = mstack.parent();
1093 if (p != NULL) { // root doesn't have parent
1094 int i = (int)mstack.index();
1095 if (i >= 0)
1096 p->set_req(i, n); // required input
1097 else if (i == -1)
1098 p->add_prec(n); // precedence input
1099 else
1100 ShouldNotReachHere();
1101 }
1102 mstack.pop(); // remove processed node from stack
1103 }
1104 else {
1105 ShouldNotReachHere();
1106 }
1107 } // while (mstack.is_nonempty())
1108 return n; // Return new-space Node
1109 }
1110
1111 //------------------------------warp_outgoing_stk_arg------------------------
1112 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1113 // Convert outgoing argument location to a pre-biased stack offset
1114 if (reg->is_stack()) {
1115 OptoReg::Name warped = reg->reg2stack();
1116 // Adjust the stack slot offset to be the register number used
1117 // by the allocator.
1118 warped = OptoReg::add(begin_out_arg_area, warped);
1119 // Keep track of the largest numbered stack slot used for an arg.
1120 // Largest used slot per call-site indicates the amount of stack
1121 // that is killed by the call.
1122 if( warped >= out_arg_limit_per_call )
1123 out_arg_limit_per_call = OptoReg::add(warped,1);
1124 if (!RegMask::can_represent_arg(warped)) {
1125 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1126 return OptoReg::Bad;
1127 }
1128 return warped;
1129 }
1130 return OptoReg::as_OptoReg(reg);
1131 }
1132
1133
1134 //------------------------------match_sfpt-------------------------------------
1135 // Helper function to match call instructions. Calls match special.
1136 // They match alone with no children. Their children, the incoming
1137 // arguments, match normally.
1138 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1139 MachSafePointNode *msfpt = NULL;
1140 MachCallNode *mcall = NULL;
1141 uint cnt;
1142 // Split out case for SafePoint vs Call
1143 CallNode *call;
1144 const TypeTuple *domain;
1145 ciMethod* method = NULL;
1146 bool is_method_handle_invoke = false; // for special kill effects
1147 if( sfpt->is_Call() ) {
1148 call = sfpt->as_Call();
1149 domain = call->tf()->domain();
1150 cnt = domain->cnt();
1151
1152 // Match just the call, nothing else
1153 MachNode *m = match_tree(call);
1154 if (C->failing()) return NULL;
1155 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1156
1157 // Copy data from the Ideal SafePoint to the machine version
1158 mcall = m->as_MachCall();
1159
1160 mcall->set_tf( call->tf());
1161 mcall->set_entry_point(call->entry_point());
1162 mcall->set_cnt( call->cnt());
1163
1164 if( mcall->is_MachCallJava() ) {
1165 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1166 const CallJavaNode *call_java = call->as_CallJava();
1167 method = call_java->method();
1168 mcall_java->_method = method;
1169 mcall_java->_bci = call_java->_bci;
1170 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1171 is_method_handle_invoke = call_java->is_method_handle_invoke();
1172 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1173 if (is_method_handle_invoke) {
1174 C->set_has_method_handle_invokes(true);
1175 }
1176 if( mcall_java->is_MachCallStaticJava() )
1177 mcall_java->as_MachCallStaticJava()->_name =
1178 call_java->as_CallStaticJava()->_name;
1179 if( mcall_java->is_MachCallDynamicJava() )
1180 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1181 call_java->as_CallDynamicJava()->_vtable_index;
1182 }
1183 else if( mcall->is_MachCallRuntime() ) {
1184 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1185 }
1186 msfpt = mcall;
1187 }
1188 // This is a non-call safepoint
1189 else {
1190 call = NULL;
1191 domain = NULL;
1192 MachNode *mn = match_tree(sfpt);
1193 if (C->failing()) return NULL;
1194 msfpt = mn->as_MachSafePoint();
1195 cnt = TypeFunc::Parms;
1196 }
1197
1198 // Advertise the correct memory effects (for anti-dependence computation).
1199 msfpt->set_adr_type(sfpt->adr_type());
1200
1201 // Allocate a private array of RegMasks. These RegMasks are not shared.
1202 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1203 // Empty them all.
1204 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1205
1206 // Do all the pre-defined non-Empty register masks
1207 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1208 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1209
1210 // Place first outgoing argument can possibly be put.
1211 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1212 assert( is_even(begin_out_arg_area), "" );
1213 // Compute max outgoing register number per call site.
1214 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1215 // Calls to C may hammer extra stack slots above and beyond any arguments.
1216 // These are usually backing store for register arguments for varargs.
1217 if( call != NULL && call->is_CallRuntime() )
1218 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1219
1220
1221 // Do the normal argument list (parameters) register masks
1222 int argcnt = cnt - TypeFunc::Parms;
1223 if( argcnt > 0 ) { // Skip it all if we have no args
1224 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1225 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1226 int i;
1227 for( i = 0; i < argcnt; i++ ) {
1228 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1229 }
1230 // V-call to pick proper calling convention
1231 call->calling_convention( sig_bt, parm_regs, argcnt );
1232
1233 #ifdef ASSERT
1234 // Sanity check users' calling convention. Really handy during
1235 // the initial porting effort. Fairly expensive otherwise.
1236 { for (int i = 0; i<argcnt; i++) {
1237 if( !parm_regs[i].first()->is_valid() &&
1238 !parm_regs[i].second()->is_valid() ) continue;
1239 VMReg reg1 = parm_regs[i].first();
1240 VMReg reg2 = parm_regs[i].second();
1241 for (int j = 0; j < i; j++) {
1242 if( !parm_regs[j].first()->is_valid() &&
1243 !parm_regs[j].second()->is_valid() ) continue;
1244 VMReg reg3 = parm_regs[j].first();
1245 VMReg reg4 = parm_regs[j].second();
1246 if( !reg1->is_valid() ) {
1247 assert( !reg2->is_valid(), "valid halvsies" );
1248 } else if( !reg3->is_valid() ) {
1249 assert( !reg4->is_valid(), "valid halvsies" );
1250 } else {
1251 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1252 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1253 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1254 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1255 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1256 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1257 }
1258 }
1259 }
1260 }
1261 #endif
1262
1263 // Visit each argument. Compute its outgoing register mask.
1264 // Return results now can have 2 bits returned.
1265 // Compute max over all outgoing arguments both per call-site
1266 // and over the entire method.
1267 for( i = 0; i < argcnt; i++ ) {
1268 // Address of incoming argument mask to fill in
1269 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1270 if( !parm_regs[i].first()->is_valid() &&
1271 !parm_regs[i].second()->is_valid() ) {
1272 continue; // Avoid Halves
1273 }
1274 // Grab first register, adjust stack slots and insert in mask.
1275 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1276 if (OptoReg::is_valid(reg1))
1277 rm->Insert( reg1 );
1278 // Grab second register (if any), adjust stack slots and insert in mask.
1279 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1280 if (OptoReg::is_valid(reg2))
1281 rm->Insert( reg2 );
1282 } // End of for all arguments
1283
1284 // Compute number of stack slots needed to restore stack in case of
1285 // Pascal-style argument popping.
1286 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1287 }
1288
1289 // Compute the max stack slot killed by any call. These will not be
1290 // available for debug info, and will be used to adjust FIRST_STACK_mask
1291 // after all call sites have been visited.
1292 if( _out_arg_limit < out_arg_limit_per_call)
1293 _out_arg_limit = out_arg_limit_per_call;
1294
1295 if (mcall) {
1296 // Kill the outgoing argument area, including any non-argument holes and
1297 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1298 // Since the max-per-method covers the max-per-call-site and debug info
1299 // is excluded on the max-per-method basis, debug info cannot land in
1300 // this killed area.
1301 uint r_cnt = mcall->tf()->range()->cnt();
1302 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1303 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1304 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1305 } else {
1306 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1307 proj->_rout.Insert(OptoReg::Name(i));
1308 }
1309 if (proj->_rout.is_NotEmpty()) {
1310 push_projection(proj);
1311 }
1312 }
1313 // Transfer the safepoint information from the call to the mcall
1314 // Move the JVMState list
1315 msfpt->set_jvms(sfpt->jvms());
1316 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1317 jvms->set_map(sfpt);
1318 }
1319
1320 // Debug inputs begin just after the last incoming parameter
1321 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1322 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1323
1324 // Move the OopMap
1325 msfpt->_oop_map = sfpt->_oop_map;
1326
1327 // Add additional edges.
1328 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1329 // For these calls we can not add MachConstantBase in expand(), as the
1330 // ins are not complete then.
1331 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1332 if (msfpt->jvms() &&
1333 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1334 // We added an edge before jvms, so we must adapt the position of the ins.
1335 msfpt->jvms()->adapt_position(+1);
1336 }
1337 }
1338
1339 // Registers killed by the call are set in the local scheduling pass
1340 // of Global Code Motion.
1341 return msfpt;
1342 }
1343
1344 //---------------------------match_tree----------------------------------------
1345 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1346 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1347 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1348 // a Load's result RegMask for memoization in idealreg2regmask[]
1349 MachNode *Matcher::match_tree( const Node *n ) {
1350 assert( n->Opcode() != Op_Phi, "cannot match" );
1351 assert( !n->is_block_start(), "cannot match" );
1352 // Set the mark for all locally allocated State objects.
1353 // When this call returns, the _states_arena arena will be reset
1354 // freeing all State objects.
1355 ResourceMark rm( &_states_arena );
1356
1357 LabelRootDepth = 0;
1358
1359 // StoreNodes require their Memory input to match any LoadNodes
1360 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1361 #ifdef ASSERT
1362 Node* save_mem_node = _mem_node;
1363 _mem_node = n->is_Store() ? (Node*)n : NULL;
1364 #endif
1365 // State object for root node of match tree
1366 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1367 State *s = new (&_states_arena) State;
1368 s->_kids[0] = NULL;
1369 s->_kids[1] = NULL;
1370 s->_leaf = (Node*)n;
1371 // Label the input tree, allocating labels from top-level arena
1372 Label_Root( n, s, n->in(0), mem );
1373 if (C->failing()) return NULL;
1374
1375 // The minimum cost match for the whole tree is found at the root State
1376 uint mincost = max_juint;
1377 uint cost = max_juint;
1378 uint i;
1379 for( i = 0; i < NUM_OPERANDS; i++ ) {
1380 if( s->valid(i) && // valid entry and
1381 s->_cost[i] < cost && // low cost and
1382 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1383 cost = s->_cost[mincost=i];
1384 }
1385 if (mincost == max_juint) {
1386 #ifndef PRODUCT
1387 tty->print("No matching rule for:");
1388 s->dump();
1389 #endif
1390 Matcher::soft_match_failure();
1391 return NULL;
1392 }
1393 // Reduce input tree based upon the state labels to machine Nodes
1394 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1395 #ifdef ASSERT
1396 _old2new_map.map(n->_idx, m);
1397 _new2old_map.map(m->_idx, (Node*)n);
1398 #endif
1399
1400 // Add any Matcher-ignored edges
1401 uint cnt = n->req();
1402 uint start = 1;
1403 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1404 if( n->is_AddP() ) {
1405 assert( mem == (Node*)1, "" );
1406 start = AddPNode::Base+1;
1407 }
1408 for( i = start; i < cnt; i++ ) {
1409 if( !n->match_edge(i) ) {
1410 if( i < m->req() )
1411 m->ins_req( i, n->in(i) );
1412 else
1413 m->add_req( n->in(i) );
1414 }
1415 }
1416
1417 debug_only( _mem_node = save_mem_node; )
1418 return m;
1419 }
1420
1421
1422 //------------------------------match_into_reg---------------------------------
1423 // Choose to either match this Node in a register or part of the current
1424 // match tree. Return true for requiring a register and false for matching
1425 // as part of the current match tree.
1426 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1427
1428 const Type *t = m->bottom_type();
1429
1430 if (t->singleton()) {
1431 // Never force constants into registers. Allow them to match as
1432 // constants or registers. Copies of the same value will share
1433 // the same register. See find_shared_node.
1434 return false;
1435 } else { // Not a constant
1436 // Stop recursion if they have different Controls.
1437 Node* m_control = m->in(0);
1438 // Control of load's memory can post-dominates load's control.
1439 // So use it since load can't float above its memory.
1440 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1441 if (control && m_control && control != m_control && control != mem_control) {
1442
1443 // Actually, we can live with the most conservative control we
1444 // find, if it post-dominates the others. This allows us to
1445 // pick up load/op/store trees where the load can float a little
1446 // above the store.
1447 Node *x = control;
1448 const uint max_scan = 6; // Arbitrary scan cutoff
1449 uint j;
1450 for (j=0; j<max_scan; j++) {
1451 if (x->is_Region()) // Bail out at merge points
1452 return true;
1453 x = x->in(0);
1454 if (x == m_control) // Does 'control' post-dominate
1455 break; // m->in(0)? If so, we can use it
1456 if (x == mem_control) // Does 'control' post-dominate
1457 break; // mem_control? If so, we can use it
1458 }
1459 if (j == max_scan) // No post-domination before scan end?
1460 return true; // Then break the match tree up
1461 }
1462 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1463 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1464 // These are commonly used in address expressions and can
1465 // efficiently fold into them on X64 in some cases.
1466 return false;
1467 }
1468 }
1469
1470 // Not forceable cloning. If shared, put it into a register.
1471 return shared;
1472 }
1473
1474
1475 //------------------------------Instruction Selection--------------------------
1476 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1477 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1478 // things the Matcher does not match (e.g., Memory), and things with different
1479 // Controls (hence forced into different blocks). We pass in the Control
1480 // selected for this entire State tree.
1481
1482 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1483 // Store and the Load must have identical Memories (as well as identical
1484 // pointers). Since the Matcher does not have anything for Memory (and
1485 // does not handle DAGs), I have to match the Memory input myself. If the
1486 // Tree root is a Store, I require all Loads to have the identical memory.
1487 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1488 // Since Label_Root is a recursive function, its possible that we might run
1489 // out of stack space. See bugs 6272980 & 6227033 for more info.
1490 LabelRootDepth++;
1491 if (LabelRootDepth > MaxLabelRootDepth) {
1492 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1493 return NULL;
1494 }
1495 uint care = 0; // Edges matcher cares about
1496 uint cnt = n->req();
1497 uint i = 0;
1498
1499 // Examine children for memory state
1500 // Can only subsume a child into your match-tree if that child's memory state
1501 // is not modified along the path to another input.
1502 // It is unsafe even if the other inputs are separate roots.
1503 Node *input_mem = NULL;
1504 for( i = 1; i < cnt; i++ ) {
1505 if( !n->match_edge(i) ) continue;
1506 Node *m = n->in(i); // Get ith input
1507 assert( m, "expect non-null children" );
1508 if( m->is_Load() ) {
1509 if( input_mem == NULL ) {
1510 input_mem = m->in(MemNode::Memory);
1511 } else if( input_mem != m->in(MemNode::Memory) ) {
1512 input_mem = NodeSentinel;
1513 }
1514 }
1515 }
1516
1517 for( i = 1; i < cnt; i++ ){// For my children
1518 if( !n->match_edge(i) ) continue;
1519 Node *m = n->in(i); // Get ith input
1520 // Allocate states out of a private arena
1521 State *s = new (&_states_arena) State;
1522 svec->_kids[care++] = s;
1523 assert( care <= 2, "binary only for now" );
1524
1525 // Recursively label the State tree.
1526 s->_kids[0] = NULL;
1527 s->_kids[1] = NULL;
1528 s->_leaf = m;
1529
1530 // Check for leaves of the State Tree; things that cannot be a part of
1531 // the current tree. If it finds any, that value is matched as a
1532 // register operand. If not, then the normal matching is used.
1533 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1534 //
1535 // Stop recursion if this is LoadNode and the root of this tree is a
1536 // StoreNode and the load & store have different memories.
1537 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1538 // Can NOT include the match of a subtree when its memory state
1539 // is used by any of the other subtrees
1540 (input_mem == NodeSentinel) ) {
1541 #ifndef PRODUCT
1542 // Print when we exclude matching due to different memory states at input-loads
1543 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1544 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1545 tty->print_cr("invalid input_mem");
1546 }
1547 #endif
1548 // Switch to a register-only opcode; this value must be in a register
1549 // and cannot be subsumed as part of a larger instruction.
1550 s->DFA( m->ideal_reg(), m );
1551
1552 } else {
1553 // If match tree has no control and we do, adopt it for entire tree
1554 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1555 control = m->in(0); // Pick up control
1556 // Else match as a normal part of the match tree.
1557 control = Label_Root(m,s,control,mem);
1558 if (C->failing()) return NULL;
1559 }
1560 }
1561
1562
1563 // Call DFA to match this node, and return
1564 svec->DFA( n->Opcode(), n );
1565
1566 #ifdef ASSERT
1567 uint x;
1568 for( x = 0; x < _LAST_MACH_OPER; x++ )
1569 if( svec->valid(x) )
1570 break;
1571
1572 if (x >= _LAST_MACH_OPER) {
1573 n->dump();
1574 svec->dump();
1575 assert( false, "bad AD file" );
1576 }
1577 #endif
1578 return control;
1579 }
1580
1581
1582 // Con nodes reduced using the same rule can share their MachNode
1583 // which reduces the number of copies of a constant in the final
1584 // program. The register allocator is free to split uses later to
1585 // split live ranges.
1586 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1587 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1588
1589 // See if this Con has already been reduced using this rule.
1590 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1591 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1592 if (last != NULL && rule == last->rule()) {
1593 // Don't expect control change for DecodeN
1594 if (leaf->is_DecodeNarrowPtr())
1595 return last;
1596 // Get the new space root.
1597 Node* xroot = new_node(C->root());
1598 if (xroot == NULL) {
1599 // This shouldn't happen give the order of matching.
1600 return NULL;
1601 }
1602
1603 // Shared constants need to have their control be root so they
1604 // can be scheduled properly.
1605 Node* control = last->in(0);
1606 if (control != xroot) {
1607 if (control == NULL || control == C->root()) {
1608 last->set_req(0, xroot);
1609 } else {
1610 assert(false, "unexpected control");
1611 return NULL;
1612 }
1613 }
1614 return last;
1615 }
1616 return NULL;
1617 }
1618
1619
1620 //------------------------------ReduceInst-------------------------------------
1621 // Reduce a State tree (with given Control) into a tree of MachNodes.
1622 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1623 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1624 // Each MachNode has a number of complicated MachOper operands; each
1625 // MachOper also covers a further tree of Ideal Nodes.
1626
1627 // The root of the Ideal match tree is always an instruction, so we enter
1628 // the recursion here. After building the MachNode, we need to recurse
1629 // the tree checking for these cases:
1630 // (1) Child is an instruction -
1631 // Build the instruction (recursively), add it as an edge.
1632 // Build a simple operand (register) to hold the result of the instruction.
1633 // (2) Child is an interior part of an instruction -
1634 // Skip over it (do nothing)
1635 // (3) Child is the start of a operand -
1636 // Build the operand, place it inside the instruction
1637 // Call ReduceOper.
1638 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1639 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1640
1641 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1642 if (shared_node != NULL) {
1643 return shared_node;
1644 }
1645
1646 // Build the object to represent this state & prepare for recursive calls
1647 MachNode *mach = s->MachNodeGenerator( rule, C );
1648 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1649 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1650 Node *leaf = s->_leaf;
1651 // Check for instruction or instruction chain rule
1652 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1653 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1654 "duplicating node that's already been matched");
1655 // Instruction
1656 mach->add_req( leaf->in(0) ); // Set initial control
1657 // Reduce interior of complex instruction
1658 ReduceInst_Interior( s, rule, mem, mach, 1 );
1659 } else {
1660 // Instruction chain rules are data-dependent on their inputs
1661 mach->add_req(0); // Set initial control to none
1662 ReduceInst_Chain_Rule( s, rule, mem, mach );
1663 }
1664
1665 // If a Memory was used, insert a Memory edge
1666 if( mem != (Node*)1 ) {
1667 mach->ins_req(MemNode::Memory,mem);
1668 #ifdef ASSERT
1669 // Verify adr type after matching memory operation
1670 const MachOper* oper = mach->memory_operand();
1671 if (oper != NULL && oper != (MachOper*)-1) {
1672 // It has a unique memory operand. Find corresponding ideal mem node.
1673 Node* m = NULL;
1674 if (leaf->is_Mem()) {
1675 m = leaf;
1676 } else {
1677 m = _mem_node;
1678 assert(m != NULL && m->is_Mem(), "expecting memory node");
1679 }
1680 const Type* mach_at = mach->adr_type();
1681 // DecodeN node consumed by an address may have different type
1682 // then its input. Don't compare types for such case.
1683 if (m->adr_type() != mach_at &&
1684 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1685 m->in(MemNode::Address)->is_AddP() &&
1686 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1687 m->in(MemNode::Address)->is_AddP() &&
1688 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1689 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1690 mach_at = m->adr_type();
1691 }
1692 if (m->adr_type() != mach_at) {
1693 m->dump();
1694 tty->print_cr("mach:");
1695 mach->dump(1);
1696 }
1697 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1698 }
1699 #endif
1700 }
1701
1702 // If the _leaf is an AddP, insert the base edge
1703 if (leaf->is_AddP()) {
1704 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1705 }
1706
1707 uint number_of_projections_prior = number_of_projections();
1708
1709 // Perform any 1-to-many expansions required
1710 MachNode *ex = mach->Expand(s, _projection_list, mem);
1711 if (ex != mach) {
1712 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1713 if( ex->in(1)->is_Con() )
1714 ex->in(1)->set_req(0, C->root());
1715 // Remove old node from the graph
1716 for( uint i=0; i<mach->req(); i++ ) {
1717 mach->set_req(i,NULL);
1718 }
1719 #ifdef ASSERT
1720 _new2old_map.map(ex->_idx, s->_leaf);
1721 #endif
1722 }
1723
1724 // PhaseChaitin::fixup_spills will sometimes generate spill code
1725 // via the matcher. By the time, nodes have been wired into the CFG,
1726 // and any further nodes generated by expand rules will be left hanging
1727 // in space, and will not get emitted as output code. Catch this.
1728 // Also, catch any new register allocation constraints ("projections")
1729 // generated belatedly during spill code generation.
1730 if (_allocation_started) {
1731 guarantee(ex == mach, "no expand rules during spill generation");
1732 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1733 }
1734
1735 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1736 // Record the con for sharing
1737 _shared_nodes.map(leaf->_idx, ex);
1738 }
1739
1740 return ex;
1741 }
1742
1743 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1744 // 'op' is what I am expecting to receive
1745 int op = _leftOp[rule];
1746 // Operand type to catch childs result
1747 // This is what my child will give me.
1748 int opnd_class_instance = s->_rule[op];
1749 // Choose between operand class or not.
1750 // This is what I will receive.
1751 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1752 // New rule for child. Chase operand classes to get the actual rule.
1753 int newrule = s->_rule[catch_op];
1754
1755 if( newrule < NUM_OPERANDS ) {
1756 // Chain from operand or operand class, may be output of shared node
1757 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1758 "Bad AD file: Instruction chain rule must chain from operand");
1759 // Insert operand into array of operands for this instruction
1760 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1761
1762 ReduceOper( s, newrule, mem, mach );
1763 } else {
1764 // Chain from the result of an instruction
1765 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1766 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1767 Node *mem1 = (Node*)1;
1768 debug_only(Node *save_mem_node = _mem_node;)
1769 mach->add_req( ReduceInst(s, newrule, mem1) );
1770 debug_only(_mem_node = save_mem_node;)
1771 }
1772 return;
1773 }
1774
1775
1776 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1777 if( s->_leaf->is_Load() ) {
1778 Node *mem2 = s->_leaf->in(MemNode::Memory);
1779 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1780 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1781 mem = mem2;
1782 }
1783 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1784 if( mach->in(0) == NULL )
1785 mach->set_req(0, s->_leaf->in(0));
1786 }
1787
1788 // Now recursively walk the state tree & add operand list.
1789 for( uint i=0; i<2; i++ ) { // binary tree
1790 State *newstate = s->_kids[i];
1791 if( newstate == NULL ) break; // Might only have 1 child
1792 // 'op' is what I am expecting to receive
1793 int op;
1794 if( i == 0 ) {
1795 op = _leftOp[rule];
1796 } else {
1797 op = _rightOp[rule];
1798 }
1799 // Operand type to catch childs result
1800 // This is what my child will give me.
1801 int opnd_class_instance = newstate->_rule[op];
1802 // Choose between operand class or not.
1803 // This is what I will receive.
1804 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1805 // New rule for child. Chase operand classes to get the actual rule.
1806 int newrule = newstate->_rule[catch_op];
1807
1808 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1809 // Operand/operandClass
1810 // Insert operand into array of operands for this instruction
1811 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1812 ReduceOper( newstate, newrule, mem, mach );
1813
1814 } else { // Child is internal operand or new instruction
1815 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1816 // internal operand --> call ReduceInst_Interior
1817 // Interior of complex instruction. Do nothing but recurse.
1818 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1819 } else {
1820 // instruction --> call build operand( ) to catch result
1821 // --> ReduceInst( newrule )
1822 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1823 Node *mem1 = (Node*)1;
1824 debug_only(Node *save_mem_node = _mem_node;)
1825 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1826 debug_only(_mem_node = save_mem_node;)
1827 }
1828 }
1829 assert( mach->_opnds[num_opnds-1], "" );
1830 }
1831 return num_opnds;
1832 }
1833
1834 // This routine walks the interior of possible complex operands.
1835 // At each point we check our children in the match tree:
1836 // (1) No children -
1837 // We are a leaf; add _leaf field as an input to the MachNode
1838 // (2) Child is an internal operand -
1839 // Skip over it ( do nothing )
1840 // (3) Child is an instruction -
1841 // Call ReduceInst recursively and
1842 // and instruction as an input to the MachNode
1843 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1844 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1845 State *kid = s->_kids[0];
1846 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1847
1848 // Leaf? And not subsumed?
1849 if( kid == NULL && !_swallowed[rule] ) {
1850 mach->add_req( s->_leaf ); // Add leaf pointer
1851 return; // Bail out
1852 }
1853
1854 if( s->_leaf->is_Load() ) {
1855 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1856 mem = s->_leaf->in(MemNode::Memory);
1857 debug_only(_mem_node = s->_leaf;)
1858 }
1859 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1860 if( !mach->in(0) )
1861 mach->set_req(0,s->_leaf->in(0));
1862 else {
1863 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1864 }
1865 }
1866
1867 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1868 int newrule;
1869 if( i == 0)
1870 newrule = kid->_rule[_leftOp[rule]];
1871 else
1872 newrule = kid->_rule[_rightOp[rule]];
1873
1874 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1875 // Internal operand; recurse but do nothing else
1876 ReduceOper( kid, newrule, mem, mach );
1877
1878 } else { // Child is a new instruction
1879 // Reduce the instruction, and add a direct pointer from this
1880 // machine instruction to the newly reduced one.
1881 Node *mem1 = (Node*)1;
1882 debug_only(Node *save_mem_node = _mem_node;)
1883 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1884 debug_only(_mem_node = save_mem_node;)
1885 }
1886 }
1887 }
1888
1889
1890 // -------------------------------------------------------------------------
1891 // Java-Java calling convention
1892 // (what you use when Java calls Java)
1893
1894 //------------------------------find_receiver----------------------------------
1895 // For a given signature, return the OptoReg for parameter 0.
1896 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1897 VMRegPair regs;
1898 BasicType sig_bt = T_OBJECT;
1899 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1900 // Return argument 0 register. In the LP64 build pointers
1901 // take 2 registers, but the VM wants only the 'main' name.
1902 return OptoReg::as_OptoReg(regs.first());
1903 }
1904
1905 // This function identifies sub-graphs in which a 'load' node is
1906 // input to two different nodes, and such that it can be matched
1907 // with BMI instructions like blsi, blsr, etc.
1908 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1909 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1910 // refers to the same node.
1911 #ifdef X86
1912 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1913 // This is a temporary solution until we make DAGs expressible in ADL.
1914 template<typename ConType>
1915 class FusedPatternMatcher {
1916 Node* _op1_node;
1917 Node* _mop_node;
1918 int _con_op;
1919
1920 static int match_next(Node* n, int next_op, int next_op_idx) {
1921 if (n->in(1) == NULL || n->in(2) == NULL) {
1922 return -1;
1923 }
1924
1925 if (next_op_idx == -1) { // n is commutative, try rotations
1926 if (n->in(1)->Opcode() == next_op) {
1927 return 1;
1928 } else if (n->in(2)->Opcode() == next_op) {
1929 return 2;
1930 }
1931 } else {
1932 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1933 if (n->in(next_op_idx)->Opcode() == next_op) {
1934 return next_op_idx;
1935 }
1936 }
1937 return -1;
1938 }
1939 public:
1940 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1941 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1942
1943 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1944 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
1945 typename ConType::NativeType con_value) {
1946 if (_op1_node->Opcode() != op1) {
1947 return false;
1948 }
1949 if (_mop_node->outcnt() > 2) {
1950 return false;
1951 }
1952 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1953 if (op1_op2_idx == -1) {
1954 return false;
1955 }
1956 // Memory operation must be the other edge
1957 int op1_mop_idx = (op1_op2_idx & 1) + 1;
1958
1959 // Check that the mop node is really what we want
1960 if (_op1_node->in(op1_mop_idx) == _mop_node) {
1961 Node *op2_node = _op1_node->in(op1_op2_idx);
1962 if (op2_node->outcnt() > 1) {
1963 return false;
1964 }
1965 assert(op2_node->Opcode() == op2, "Should be");
1966 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
1967 if (op2_con_idx == -1) {
1968 return false;
1969 }
1970 // Memory operation must be the other edge
1971 int op2_mop_idx = (op2_con_idx & 1) + 1;
1972 // Check that the memory operation is the same node
1973 if (op2_node->in(op2_mop_idx) == _mop_node) {
1974 // Now check the constant
1975 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
1976 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
1977 return true;
1978 }
1979 }
1980 }
1981 return false;
1982 }
1983 };
1984
1985
1986 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
1987 if (n != NULL && m != NULL) {
1988 if (m->Opcode() == Op_LoadI) {
1989 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
1990 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
1991 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
1992 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
1993 } else if (m->Opcode() == Op_LoadL) {
1994 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
1995 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
1996 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
1997 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
1998 }
1999 }
2000 return false;
2001 }
2002 #endif // X86
2003
2004 // A method-klass-holder may be passed in the inline_cache_reg
2005 // and then expanded into the inline_cache_reg and a method_oop register
2006 // defined in ad_<arch>.cpp
2007
2008
2009 //------------------------------find_shared------------------------------------
2010 // Set bits if Node is shared or otherwise a root
2011 void Matcher::find_shared( Node *n ) {
2012 // Allocate stack of size C->unique() * 2 to avoid frequent realloc
2013 MStack mstack(C->unique() * 2);
2014 // Mark nodes as address_visited if they are inputs to an address expression
2015 VectorSet address_visited(Thread::current()->resource_area());
2016 mstack.push(n, Visit); // Don't need to pre-visit root node
2017 while (mstack.is_nonempty()) {
2018 n = mstack.node(); // Leave node on stack
2019 Node_State nstate = mstack.state();
2020 uint nop = n->Opcode();
2021 if (nstate == Pre_Visit) {
2022 if (address_visited.test(n->_idx)) { // Visited in address already?
2023 // Flag as visited and shared now.
2024 set_visited(n);
2025 }
2026 if (is_visited(n)) { // Visited already?
2027 // Node is shared and has no reason to clone. Flag it as shared.
2028 // This causes it to match into a register for the sharing.
2029 set_shared(n); // Flag as shared and
2030 mstack.pop(); // remove node from stack
2031 continue;
2032 }
2033 nstate = Visit; // Not already visited; so visit now
2034 }
2035 if (nstate == Visit) {
2036 mstack.set_state(Post_Visit);
2037 set_visited(n); // Flag as visited now
2038 bool mem_op = false;
2039
2040 switch( nop ) { // Handle some opcodes special
2041 case Op_Phi: // Treat Phis as shared roots
2042 case Op_Parm:
2043 case Op_Proj: // All handled specially during matching
2044 case Op_SafePointScalarObject:
2045 set_shared(n);
2046 set_dontcare(n);
2047 break;
2048 case Op_If:
2049 case Op_CountedLoopEnd:
2050 mstack.set_state(Alt_Post_Visit); // Alternative way
2051 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2052 // with matching cmp/branch in 1 instruction. The Matcher needs the
2053 // Bool and CmpX side-by-side, because it can only get at constants
2054 // that are at the leaves of Match trees, and the Bool's condition acts
2055 // as a constant here.
2056 mstack.push(n->in(1), Visit); // Clone the Bool
2057 mstack.push(n->in(0), Pre_Visit); // Visit control input
2058 continue; // while (mstack.is_nonempty())
2059 case Op_ConvI2D: // These forms efficiently match with a prior
2060 case Op_ConvI2F: // Load but not a following Store
2061 if( n->in(1)->is_Load() && // Prior load
2062 n->outcnt() == 1 && // Not already shared
2063 n->unique_out()->is_Store() ) // Following store
2064 set_shared(n); // Force it to be a root
2065 break;
2066 case Op_ReverseBytesI:
2067 case Op_ReverseBytesL:
2068 if( n->in(1)->is_Load() && // Prior load
2069 n->outcnt() == 1 ) // Not already shared
2070 set_shared(n); // Force it to be a root
2071 break;
2072 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
2073 case Op_IfFalse:
2074 case Op_IfTrue:
2075 case Op_MachProj:
2076 case Op_MergeMem:
2077 case Op_Catch:
2078 case Op_CatchProj:
2079 case Op_CProj:
2080 case Op_JumpProj:
2081 case Op_JProj:
2082 case Op_NeverBranch:
2083 set_dontcare(n);
2084 break;
2085 case Op_Jump:
2086 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2087 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2088 continue; // while (mstack.is_nonempty())
2089 case Op_StrComp:
2090 case Op_StrEquals:
2091 case Op_StrIndexOf:
2092 case Op_AryEq:
2093 case Op_EncodeISOArray:
2094 set_shared(n); // Force result into register (it will be anyways)
2095 break;
2096 case Op_ConP: { // Convert pointers above the centerline to NUL
2097 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2098 const TypePtr* tp = tn->type()->is_ptr();
2099 if (tp->_ptr == TypePtr::AnyNull) {
2100 tn->set_type(TypePtr::NULL_PTR);
2101 }
2102 break;
2103 }
2104 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2105 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2106 const TypePtr* tp = tn->type()->make_ptr();
2107 if (tp && tp->_ptr == TypePtr::AnyNull) {
2108 tn->set_type(TypeNarrowOop::NULL_PTR);
2109 }
2110 break;
2111 }
2112 case Op_Binary: // These are introduced in the Post_Visit state.
2113 ShouldNotReachHere();
2114 break;
2115 case Op_ClearArray:
2116 case Op_SafePoint:
2117 mem_op = true;
2118 break;
2119 default:
2120 if( n->is_Store() ) {
2121 // Do match stores, despite no ideal reg
2122 mem_op = true;
2123 break;
2124 }
2125 if( n->is_Mem() ) { // Loads and LoadStores
2126 mem_op = true;
2127 // Loads must be root of match tree due to prior load conflict
2128 if( C->subsume_loads() == false )
2129 set_shared(n);
2130 }
2131 // Fall into default case
2132 if( !n->ideal_reg() )
2133 set_dontcare(n); // Unmatchable Nodes
2134 } // end_switch
2135
2136 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2137 Node *m = n->in(i); // Get ith input
2138 if (m == NULL) continue; // Ignore NULLs
2139 uint mop = m->Opcode();
2140
2141 // Must clone all producers of flags, or we will not match correctly.
2142 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2143 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2144 // are also there, so we may match a float-branch to int-flags and
2145 // expect the allocator to haul the flags from the int-side to the
2146 // fp-side. No can do.
2147 if( _must_clone[mop] ) {
2148 mstack.push(m, Visit);
2149 continue; // for(int i = ...)
2150 }
2151
2152 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2153 // Bases used in addresses must be shared but since
2154 // they are shared through a DecodeN they may appear
2155 // to have a single use so force sharing here.
2156 set_shared(m->in(AddPNode::Base)->in(1));
2157 }
2158
2159 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2160 #ifdef X86
2161 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2162 mstack.push(m, Visit);
2163 continue;
2164 }
2165 #endif
2166
2167 // Clone addressing expressions as they are "free" in memory access instructions
2168 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
2169 // Some inputs for address expression are not put on stack
2170 // to avoid marking them as shared and forcing them into register
2171 // if they are used only in address expressions.
2172 // But they should be marked as shared if there are other uses
2173 // besides address expressions.
2174
2175 Node *off = m->in(AddPNode::Offset);
2176 if( off->is_Con() &&
2177 // When there are other uses besides address expressions
2178 // put it on stack and mark as shared.
2179 !is_visited(m) ) {
2180 address_visited.test_set(m->_idx); // Flag as address_visited
2181 Node *adr = m->in(AddPNode::Address);
2182
2183 // Intel, ARM and friends can handle 2 adds in addressing mode
2184 if( clone_shift_expressions && adr->is_AddP() &&
2185 // AtomicAdd is not an addressing expression.
2186 // Cheap to find it by looking for screwy base.
2187 !adr->in(AddPNode::Base)->is_top() &&
2188 // Are there other uses besides address expressions?
2189 !is_visited(adr) ) {
2190 address_visited.set(adr->_idx); // Flag as address_visited
2191 Node *shift = adr->in(AddPNode::Offset);
2192 // Check for shift by small constant as well
2193 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2194 shift->in(2)->get_int() <= 3 &&
2195 // Are there other uses besides address expressions?
2196 !is_visited(shift) ) {
2197 address_visited.set(shift->_idx); // Flag as address_visited
2198 mstack.push(shift->in(2), Visit);
2199 Node *conv = shift->in(1);
2200 #ifdef _LP64
2201 // Allow Matcher to match the rule which bypass
2202 // ConvI2L operation for an array index on LP64
2203 // if the index value is positive.
2204 if( conv->Opcode() == Op_ConvI2L &&
2205 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2206 // Are there other uses besides address expressions?
2207 !is_visited(conv) ) {
2208 address_visited.set(conv->_idx); // Flag as address_visited
2209 mstack.push(conv->in(1), Pre_Visit);
2210 } else
2211 #endif
2212 mstack.push(conv, Pre_Visit);
2213 } else {
2214 mstack.push(shift, Pre_Visit);
2215 }
2216 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2217 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2218 } else { // Sparc, Alpha, PPC and friends
2219 mstack.push(adr, Pre_Visit);
2220 }
2221
2222 // Clone X+offset as it also folds into most addressing expressions
2223 mstack.push(off, Visit);
2224 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2225 continue; // for(int i = ...)
2226 } // if( off->is_Con() )
2227 } // if( mem_op &&
2228 mstack.push(m, Pre_Visit);
2229 } // for(int i = ...)
2230 }
2231 else if (nstate == Alt_Post_Visit) {
2232 mstack.pop(); // Remove node from stack
2233 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2234 // shared and all users of the Bool need to move the Cmp in parallel.
2235 // This leaves both the Bool and the If pointing at the Cmp. To
2236 // prevent the Matcher from trying to Match the Cmp along both paths
2237 // BoolNode::match_edge always returns a zero.
2238
2239 // We reorder the Op_If in a pre-order manner, so we can visit without
2240 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2241 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2242 }
2243 else if (nstate == Post_Visit) {
2244 mstack.pop(); // Remove node from stack
2245
2246 // Now hack a few special opcodes
2247 switch( n->Opcode() ) { // Handle some opcodes special
2248 case Op_StorePConditional:
2249 case Op_StoreIConditional:
2250 case Op_StoreLConditional:
2251 case Op_CompareAndSwapI:
2252 case Op_CompareAndSwapL:
2253 case Op_CompareAndSwapP:
2254 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2255 Node *newval = n->in(MemNode::ValueIn );
2256 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2257 Node *pair = new BinaryNode( oldval, newval );
2258 n->set_req(MemNode::ValueIn,pair);
2259 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2260 break;
2261 }
2262 case Op_CMoveD: // Convert trinary to binary-tree
2263 case Op_CMoveF:
2264 case Op_CMoveI:
2265 case Op_CMoveL:
2266 case Op_CMoveN:
2267 case Op_CMoveP: {
2268 // Restructure into a binary tree for Matching. It's possible that
2269 // we could move this code up next to the graph reshaping for IfNodes
2270 // or vice-versa, but I do not want to debug this for Ladybird.
2271 // 10/2/2000 CNC.
2272 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2273 n->set_req(1,pair1);
2274 Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2275 n->set_req(2,pair2);
2276 n->del_req(3);
2277 break;
2278 }
2279 case Op_LoopLimit: {
2280 Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2281 n->set_req(1,pair1);
2282 n->set_req(2,n->in(3));
2283 n->del_req(3);
2284 break;
2285 }
2286 case Op_StrEquals: {
2287 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2288 n->set_req(2,pair1);
2289 n->set_req(3,n->in(4));
2290 n->del_req(4);
2291 break;
2292 }
2293 case Op_StrComp:
2294 case Op_StrIndexOf: {
2295 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2296 n->set_req(2,pair1);
2297 Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2298 n->set_req(3,pair2);
2299 n->del_req(5);
2300 n->del_req(4);
2301 break;
2302 }
2303 case Op_EncodeISOArray: {
2304 // Restructure into a binary tree for Matching.
2305 Node* pair = new BinaryNode(n->in(3), n->in(4));
2306 n->set_req(3, pair);
2307 n->del_req(4);
2308 break;
2309 }
2310 default:
2311 break;
2312 }
2313 }
2314 else {
2315 ShouldNotReachHere();
2316 }
2317 } // end of while (mstack.is_nonempty())
2318 }
2319
2320 #ifdef ASSERT
2321 // machine-independent root to machine-dependent root
2322 void Matcher::dump_old2new_map() {
2323 _old2new_map.dump();
2324 }
2325 #endif
2326
2327 //---------------------------collect_null_checks-------------------------------
2328 // Find null checks in the ideal graph; write a machine-specific node for
2329 // it. Used by later implicit-null-check handling. Actually collects
2330 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2331 // value being tested.
2332 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2333 Node *iff = proj->in(0);
2334 if( iff->Opcode() == Op_If ) {
2335 // During matching If's have Bool & Cmp side-by-side
2336 BoolNode *b = iff->in(1)->as_Bool();
2337 Node *cmp = iff->in(2);
2338 int opc = cmp->Opcode();
2339 if (opc != Op_CmpP && opc != Op_CmpN) return;
2340
2341 const Type* ct = cmp->in(2)->bottom_type();
2342 if (ct == TypePtr::NULL_PTR ||
2343 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2344
2345 bool push_it = false;
2346 if( proj->Opcode() == Op_IfTrue ) {
2347 extern int all_null_checks_found;
2348 all_null_checks_found++;
2349 if( b->_test._test == BoolTest::ne ) {
2350 push_it = true;
2351 }
2352 } else {
2353 assert( proj->Opcode() == Op_IfFalse, "" );
2354 if( b->_test._test == BoolTest::eq ) {
2355 push_it = true;
2356 }
2357 }
2358 if( push_it ) {
2359 _null_check_tests.push(proj);
2360 Node* val = cmp->in(1);
2361 #ifdef _LP64
2362 if (val->bottom_type()->isa_narrowoop() &&
2363 !Matcher::narrow_oop_use_complex_address()) {
2364 //
2365 // Look for DecodeN node which should be pinned to orig_proj.
2366 // On platforms (Sparc) which can not handle 2 adds
2367 // in addressing mode we have to keep a DecodeN node and
2368 // use it to do implicit NULL check in address.
2369 //
2370 // DecodeN node was pinned to non-null path (orig_proj) during
2371 // CastPP transformation in final_graph_reshaping_impl().
2372 //
2373 uint cnt = orig_proj->outcnt();
2374 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2375 Node* d = orig_proj->raw_out(i);
2376 if (d->is_DecodeN() && d->in(1) == val) {
2377 val = d;
2378 val->set_req(0, NULL); // Unpin now.
2379 // Mark this as special case to distinguish from
2380 // a regular case: CmpP(DecodeN, NULL).
2381 val = (Node*)(((intptr_t)val) | 1);
2382 break;
2383 }
2384 }
2385 }
2386 #endif
2387 _null_check_tests.push(val);
2388 }
2389 }
2390 }
2391 }
2392
2393 //---------------------------validate_null_checks------------------------------
2394 // Its possible that the value being NULL checked is not the root of a match
2395 // tree. If so, I cannot use the value in an implicit null check.
2396 void Matcher::validate_null_checks( ) {
2397 uint cnt = _null_check_tests.size();
2398 for( uint i=0; i < cnt; i+=2 ) {
2399 Node *test = _null_check_tests[i];
2400 Node *val = _null_check_tests[i+1];
2401 bool is_decoden = ((intptr_t)val) & 1;
2402 val = (Node*)(((intptr_t)val) & ~1);
2403 if (has_new_node(val)) {
2404 Node* new_val = new_node(val);
2405 if (is_decoden) {
2406 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2407 // Note: new_val may have a control edge if
2408 // the original ideal node DecodeN was matched before
2409 // it was unpinned in Matcher::collect_null_checks().
2410 // Unpin the mach node and mark it.
2411 new_val->set_req(0, NULL);
2412 new_val = (Node*)(((intptr_t)new_val) | 1);
2413 }
2414 // Is a match-tree root, so replace with the matched value
2415 _null_check_tests.map(i+1, new_val);
2416 } else {
2417 // Yank from candidate list
2418 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2419 _null_check_tests.map(i,_null_check_tests[--cnt]);
2420 _null_check_tests.pop();
2421 _null_check_tests.pop();
2422 i-=2;
2423 }
2424 }
2425 }
2426
2427 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2428 // atomic instruction acting as a store_load barrier without any
2429 // intervening volatile load, and thus we don't need a barrier here.
2430 // We retain the Node to act as a compiler ordering barrier.
2431 bool Matcher::post_store_load_barrier(const Node* vmb) {
2432 Compile* C = Compile::current();
2433 assert(vmb->is_MemBar(), "");
2434 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2435 const MemBarNode* membar = vmb->as_MemBar();
2436
2437 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2438 Node* ctrl = NULL;
2439 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2440 Node* p = membar->fast_out(i);
2441 assert(p->is_Proj(), "only projections here");
2442 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2443 !C->node_arena()->contains(p)) { // Unmatched old-space only
2444 ctrl = p;
2445 break;
2446 }
2447 }
2448 assert((ctrl != NULL), "missing control projection");
2449
2450 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2451 Node *x = ctrl->fast_out(j);
2452 int xop = x->Opcode();
2453
2454 // We don't need current barrier if we see another or a lock
2455 // before seeing volatile load.
2456 //
2457 // Op_Fastunlock previously appeared in the Op_* list below.
2458 // With the advent of 1-0 lock operations we're no longer guaranteed
2459 // that a monitor exit operation contains a serializing instruction.
2460
2461 if (xop == Op_MemBarVolatile ||
2462 xop == Op_CompareAndSwapL ||
2463 xop == Op_CompareAndSwapP ||
2464 xop == Op_CompareAndSwapN ||
2465 xop == Op_CompareAndSwapI) {
2466 return true;
2467 }
2468
2469 // Op_FastLock previously appeared in the Op_* list above.
2470 // With biased locking we're no longer guaranteed that a monitor
2471 // enter operation contains a serializing instruction.
2472 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2473 return true;
2474 }
2475
2476 if (x->is_MemBar()) {
2477 // We must retain this membar if there is an upcoming volatile
2478 // load, which will be followed by acquire membar.
2479 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2480 return false;
2481 } else {
2482 // For other kinds of barriers, check by pretending we
2483 // are them, and seeing if we can be removed.
2484 return post_store_load_barrier(x->as_MemBar());
2485 }
2486 }
2487
2488 // probably not necessary to check for these
2489 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2490 return false;
2491 }
2492 }
2493 return false;
2494 }
2495
2496 // Check whether node n is a branch to an uncommon trap that we could
2497 // optimize as test with very high branch costs in case of going to
2498 // the uncommon trap. The code must be able to be recompiled to use
2499 // a cheaper test.
2500 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2501 // Don't do it for natives, adapters, or runtime stubs
2502 Compile *C = Compile::current();
2503 if (!C->is_method_compilation()) return false;
2504
2505 assert(n->is_If(), "You should only call this on if nodes.");
2506 IfNode *ifn = n->as_If();
2507
2508 Node *ifFalse = NULL;
2509 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2510 if (ifn->fast_out(i)->is_IfFalse()) {
2511 ifFalse = ifn->fast_out(i);
2512 break;
2513 }
2514 }
2515 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2516
2517 Node *reg = ifFalse;
2518 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2519 // Alternatively use visited set? Seems too expensive.
2520 while (reg != NULL && cnt > 0) {
2521 CallNode *call = NULL;
2522 RegionNode *nxt_reg = NULL;
2523 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2524 Node *o = reg->fast_out(i);
2525 if (o->is_Call()) {
2526 call = o->as_Call();
2527 }
2528 if (o->is_Region()) {
2529 nxt_reg = o->as_Region();
2530 }
2531 }
2532
2533 if (call &&
2534 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2535 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2536 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2537 jint tr_con = trtype->is_int()->get_con();
2538 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2539 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2540 assert((int)reason < (int)BitsPerInt, "recode bit map");
2541
2542 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2543 && action != Deoptimization::Action_none) {
2544 // This uncommon trap is sure to recompile, eventually.
2545 // When that happens, C->too_many_traps will prevent
2546 // this transformation from happening again.
2547 return true;
2548 }
2549 }
2550 }
2551
2552 reg = nxt_reg;
2553 cnt--;
2554 }
2555
2556 return false;
2557 }
2558
2559 //=============================================================================
2560 //---------------------------State---------------------------------------------
2561 State::State(void) {
2562 #ifdef ASSERT
2563 _id = 0;
2564 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2565 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2566 //memset(_cost, -1, sizeof(_cost));
2567 //memset(_rule, -1, sizeof(_rule));
2568 #endif
2569 memset(_valid, 0, sizeof(_valid));
2570 }
2571
2572 #ifdef ASSERT
2573 State::~State() {
2574 _id = 99;
2575 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2576 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2577 memset(_cost, -3, sizeof(_cost));
2578 memset(_rule, -3, sizeof(_rule));
2579 }
2580 #endif
2581
2582 #ifndef PRODUCT
2583 //---------------------------dump----------------------------------------------
2584 void State::dump() {
2585 tty->print("\n");
2586 dump(0);
2587 }
2588
2589 void State::dump(int depth) {
2590 for( int j = 0; j < depth; j++ )
2591 tty->print(" ");
2592 tty->print("--N: ");
2593 _leaf->dump();
2594 uint i;
2595 for( i = 0; i < _LAST_MACH_OPER; i++ )
2596 // Check for valid entry
2597 if( valid(i) ) {
2598 for( int j = 0; j < depth; j++ )
2599 tty->print(" ");
2600 assert(_cost[i] != max_juint, "cost must be a valid value");
2601 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2602 tty->print_cr("%s %d %s",
2603 ruleName[i], _cost[i], ruleName[_rule[i]] );
2604 }
2605 tty->cr();
2606
2607 for( i=0; i<2; i++ )
2608 if( _kids[i] )
2609 _kids[i]->dump(depth+1);
2610 }
2611 #endif