9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "logging/log.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/os.hpp"
32 #include "runtime/stubCodeGenerator.hpp"
33 #include "vm_version_x86.hpp"
34
35
36 int VM_Version::_cpu;
37 int VM_Version::_model;
38 int VM_Version::_stepping;
39 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
40
41 // Address of instruction which causes SEGV
42 address VM_Version::_cpuinfo_segv_addr = 0;
43 // Address of instruction after the one which causes SEGV
44 address VM_Version::_cpuinfo_cont_addr = 0;
45
46 static BufferBlob* stub_blob;
47 static const int stub_size = 1000;
48
1346 }
1347 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1348 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1349 }
1350 if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
1351 FLAG_SET_DEFAULT(PrefetchFieldsAhead, 1);
1352 }
1353 #endif
1354
1355 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1356 (cache_line_size > ContendedPaddingWidth))
1357 ContendedPaddingWidth = cache_line_size;
1358
1359 // This machine allows unaligned memory accesses
1360 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1361 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1362 }
1363
1364 #ifndef PRODUCT
1365 if (log_is_enabled(Info, os, cpu)) {
1366 outputStream* log = Log(os, cpu)::info_stream();
1367 log->print_cr("Logical CPUs per core: %u",
1368 logical_processors_per_package());
1369 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1370 log->print("UseSSE=%d", (int) UseSSE);
1371 if (UseAVX > 0) {
1372 log->print(" UseAVX=%d", (int) UseAVX);
1373 }
1374 if (UseAES) {
1375 log->print(" UseAES=1");
1376 }
1377 #ifdef COMPILER2
1378 if (MaxVectorSize > 0) {
1379 log->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1380 }
1381 #endif
1382 log->cr();
1383 log->print("Allocation");
1384 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
1385 log->print_cr(": no prefetching");
1386 } else {
|
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "logging/log.hpp"
29 #include "logging/logStream.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "vm_version_x86.hpp"
35
36
37 int VM_Version::_cpu;
38 int VM_Version::_model;
39 int VM_Version::_stepping;
40 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
41
42 // Address of instruction which causes SEGV
43 address VM_Version::_cpuinfo_segv_addr = 0;
44 // Address of instruction after the one which causes SEGV
45 address VM_Version::_cpuinfo_cont_addr = 0;
46
47 static BufferBlob* stub_blob;
48 static const int stub_size = 1000;
49
1347 }
1348 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1349 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1350 }
1351 if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
1352 FLAG_SET_DEFAULT(PrefetchFieldsAhead, 1);
1353 }
1354 #endif
1355
1356 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1357 (cache_line_size > ContendedPaddingWidth))
1358 ContendedPaddingWidth = cache_line_size;
1359
1360 // This machine allows unaligned memory accesses
1361 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1362 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1363 }
1364
1365 #ifndef PRODUCT
1366 if (log_is_enabled(Info, os, cpu)) {
1367 LogStream ls(Log(os, cpu)::info());
1368 outputStream* log = &ls;
1369 log->print_cr("Logical CPUs per core: %u",
1370 logical_processors_per_package());
1371 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1372 log->print("UseSSE=%d", (int) UseSSE);
1373 if (UseAVX > 0) {
1374 log->print(" UseAVX=%d", (int) UseAVX);
1375 }
1376 if (UseAES) {
1377 log->print(" UseAES=1");
1378 }
1379 #ifdef COMPILER2
1380 if (MaxVectorSize > 0) {
1381 log->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1382 }
1383 #endif
1384 log->cr();
1385 log->print("Allocation");
1386 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
1387 log->print_cr(": no prefetching");
1388 } else {
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