1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "logging/log.hpp"
28 #include "logging/logStream.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "prims/jvm.h"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "vm_version_sparc.hpp"
35
36 #include <sys/mman.h>
37
38 uint VM_Version::_L2_data_cache_line_size = 0;
39
40 void VM_Version::initialize() {
41 assert(_features != 0, "System pre-initialization is not complete.");
42 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
43
44 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
45 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
46 PrefetchFieldsAhead = prefetch_fields_ahead();
47
48 // Allocation prefetch settings
49
50 AllocatePrefetchDistance = allocate_prefetch_distance();
51 AllocatePrefetchStyle = allocate_prefetch_style();
52
53 intx cache_line_size = prefetch_data_size();
54
55 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize)) {
56 AllocatePrefetchStepSize = MAX2(AllocatePrefetchStepSize, cache_line_size);
57 }
58
59 if (AllocatePrefetchInstr == 1) {
60 if (!has_blk_init()) {
61 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
62 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
63 }
64 if (cache_line_size <= 0) {
65 warning("Cache-line size must be known for AllocatePrefetchInstr 1 to work");
66 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
67 }
68 }
69
70 UseSSE = false; // Only used on x86 and x64.
71
72 _supports_cx8 = true; // All SPARC V9 implementations.
73 _supports_atomic_getset4 = true; // Using the 'swap' instruction.
74
75 if (has_fast_ind_br() && FLAG_IS_DEFAULT(UseInlineCaches)) {
76 // Indirect and direct branches are cost equivalent.
77 FLAG_SET_DEFAULT(UseInlineCaches, false);
78 }
79 // Align loops on the proper instruction boundary to fill the instruction
80 // fetch buffer.
81 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
82 FLAG_SET_DEFAULT(OptoLoopAlignment, VM_Version::insn_fetch_alignment);
83 }
84
85 // 32-bit oops don't make sense for the 64-bit VM on SPARC since the 32-bit
86 // VM has the same registers and smaller objects.
87 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
88 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
89
90 #ifdef COMPILER2
91 if (has_fast_ind_br() && FLAG_IS_DEFAULT(UseJumpTables)) {
92 // Indirect and direct branches are cost equivalent.
93 FLAG_SET_DEFAULT(UseJumpTables, true);
94 }
95 // Entry and loop tops are aligned to fill the instruction fetch buffer.
96 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
97 FLAG_SET_DEFAULT(InteriorEntryAlignment, VM_Version::insn_fetch_alignment);
98 }
99 if (UseTLAB && cache_line_size > 0 &&
100 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
101 if (has_fast_bis()) {
102 // Use BIS instruction for TLAB allocation prefetch.
103 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
104 }
105 else if (has_sparc5()) {
106 // Use prefetch instruction to avoid partial RAW issue on Core S4 processors,
107 // also use prefetch style 3.
108 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
109 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
110 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
111 }
112 }
113 }
114 if (AllocatePrefetchInstr == 1) {
115 // Use allocation prefetch style 3 because BIS instructions require
116 // aligned memory addresses.
117 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
118 }
119 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
120 if (AllocatePrefetchInstr == 0) {
121 // Use different prefetch distance without BIS
122 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
123 } else {
124 // Use smaller prefetch distance with BIS
125 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
126 }
127 }
128
129 // We increase the number of prefetched cache lines, to use just a bit more
130 // aggressive approach, when the L2-cache line size is small (32 bytes), or
131 // when running on newer processor implementations, such as the Core S4.
132 bool inc_prefetch = cache_line_size > 0 && (cache_line_size < 64 || has_sparc5());
133
134 if (inc_prefetch) {
135 // We use a factor two for small cache line sizes (as before) but a slightly
136 // more conservative increase when running on more recent hardware that will
137 // benefit from just a bit more aggressive prefetching.
138 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
139 const int ap_lns = AllocatePrefetchLines;
140 const int ap_inc = cache_line_size < 64 ? ap_lns : (ap_lns + 1) / 2;
141 FLAG_SET_ERGO(intx, AllocatePrefetchLines, ap_lns + ap_inc);
142 }
143 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
144 const int ip_lns = AllocateInstancePrefetchLines;
145 const int ip_inc = cache_line_size < 64 ? ip_lns : (ip_lns + 1) / 2;
146 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, ip_lns + ip_inc);
147 }
148 }
149 #endif /* COMPILER2 */
150
151 // Use hardware population count instruction if available.
152 if (has_popc()) {
153 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
154 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
155 }
156 } else if (UsePopCountInstruction) {
157 warning("POPC instruction is not available on this CPU");
158 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
159 }
160
161 // Use compare and branch instructions if available.
162 if (has_cbcond()) {
163 if (FLAG_IS_DEFAULT(UseCBCond)) {
164 FLAG_SET_DEFAULT(UseCBCond, true);
165 }
166 } else if (UseCBCond) {
167 warning("CBCOND instruction is not available on this CPU");
168 FLAG_SET_DEFAULT(UseCBCond, false);
169 }
170
171 assert(BlockZeroingLowLimit > 0, "invalid value");
172
173 if (has_blk_zeroing() && cache_line_size > 0) {
174 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
175 FLAG_SET_DEFAULT(UseBlockZeroing, true);
176 }
177 } else if (UseBlockZeroing) {
178 warning("BIS zeroing instructions are not available on this CPU");
179 FLAG_SET_DEFAULT(UseBlockZeroing, false);
180 }
181
182 assert(BlockCopyLowLimit > 0, "invalid value");
183
184 if (has_blk_zeroing() && cache_line_size > 0) {
185 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
186 FLAG_SET_DEFAULT(UseBlockCopy, true);
187 }
188 } else if (UseBlockCopy) {
189 warning("BIS instructions are not available or expensive on this CPU");
190 FLAG_SET_DEFAULT(UseBlockCopy, false);
191 }
192
193 #ifdef COMPILER2
194 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
195 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
196 }
197
198 // Currently not supported anywhere.
199 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
200
201 MaxVectorSize = 8;
202
203 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
204 #endif
205
206 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
207 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
208
209 char buf[512];
210 jio_snprintf(buf, sizeof(buf),
211 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
212 (has_v9() ? "v9" : ""),
213 (has_popc() ? ", popc" : ""),
214 (has_vis1() ? ", vis1" : ""),
215 (has_vis2() ? ", vis2" : ""),
216 (has_blk_init() ? ", blk_init" : ""),
217 (has_fmaf() ? ", fmaf" : ""),
218 (has_hpc() ? ", hpc" : ""),
219 (has_ima() ? ", ima" : ""),
220 (has_aes() ? ", aes" : ""),
221 (has_des() ? ", des" : ""),
222 (has_kasumi() ? ", kas" : ""),
223 (has_camellia() ? ", cam" : ""),
224 (has_md5() ? ", md5" : ""),
225 (has_sha1() ? ", sha1" : ""),
226 (has_sha256() ? ", sha256" : ""),
227 (has_sha512() ? ", sha512" : ""),
228 (has_mpmul() ? ", mpmul" : ""),
229 (has_mont() ? ", mont" : ""),
230 (has_pause() ? ", pause" : ""),
231 (has_cbcond() ? ", cbcond" : ""),
232 (has_crc32c() ? ", crc32c" : ""),
233
234 (has_athena_plus() ? ", athena_plus" : ""),
235 (has_vis3b() ? ", vis3b" : ""),
236 (has_adi() ? ", adi" : ""),
237 (has_sparc5() ? ", sparc5" : ""),
238 (has_mwait() ? ", mwait" : ""),
239 (has_xmpmul() ? ", xmpmul" : ""),
240 (has_xmont() ? ", xmont" : ""),
241 (has_pause_nsec() ? ", pause_nsec" : ""),
242 (has_vamask() ? ", vamask" : ""),
243
244 (has_fast_idiv() ? ", *idiv" : ""),
245 (has_fast_rdpc() ? ", *rdpc" : ""),
246 (has_fast_bis() ? ", *bis" : ""),
247 (has_fast_ld() ? ", *ld" : ""),
248 (has_fast_cmove() ? ", *cmove" : ""),
249 (has_fast_ind_br() ? ", *ind_br" : ""),
250 (has_blk_zeroing() ? ", *blk_zeroing" : ""));
251
252 assert(strlen(buf) >= 2, "must be");
253
254 _features_string = os::strdup(buf);
255
256 log_info(os, cpu)("SPARC features detected: %s", _features_string);
257
258 // UseVIS is set to the smallest of what hardware supports and what the command
259 // line requires, i.e. you cannot set UseVIS to 3 on older UltraSparc which do
260 // not support it.
261
262 if (UseVIS > 3) UseVIS = 3;
263 if (UseVIS < 0) UseVIS = 0;
264 if (!has_vis3()) // Drop to 2 if no VIS3 support
265 UseVIS = MIN2((intx)2, UseVIS);
266 if (!has_vis2()) // Drop to 1 if no VIS2 support
267 UseVIS = MIN2((intx)1, UseVIS);
268 if (!has_vis1()) // Drop to 0 if no VIS1 support
269 UseVIS = 0;
270
271 if (has_aes()) {
272 if (FLAG_IS_DEFAULT(UseAES)) {
273 FLAG_SET_DEFAULT(UseAES, true);
274 }
275 if (!UseAES) {
276 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
277 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
278 }
279 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
280 } else {
281 // The AES intrinsic stubs require AES instruction support (of course)
282 // but also require VIS3 mode or higher for instructions it use.
283 if (UseVIS > 2) {
284 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
285 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
286 }
287 } else {
288 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
289 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
290 }
291 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
292 }
293 }
294 } else if (UseAES || UseAESIntrinsics) {
295 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
296 warning("AES instructions are not available on this CPU");
297 FLAG_SET_DEFAULT(UseAES, false);
298 }
299 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
300 warning("AES intrinsics are not available on this CPU");
301 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
302 }
303 }
304
305 if (UseAESCTRIntrinsics) {
306 warning("AES/CTR intrinsics are not available on this CPU");
307 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
308 }
309
310 // GHASH/GCM intrinsics
311 if (has_vis3() && (UseVIS > 2)) {
312 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
313 UseGHASHIntrinsics = true;
314 }
315 } else if (UseGHASHIntrinsics) {
316 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
317 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
318 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
319 }
320
321 if (has_fmaf()) {
322 if (FLAG_IS_DEFAULT(UseFMA)) {
323 UseFMA = true;
324 }
325 } else if (UseFMA) {
326 warning("FMA instructions are not available on this CPU");
327 FLAG_SET_DEFAULT(UseFMA, false);
328 }
329
330 // SHA1, SHA256, and SHA512 instructions were added to SPARC at different times
331 if (has_sha1() || has_sha256() || has_sha512()) {
332 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
333 if (FLAG_IS_DEFAULT(UseSHA)) {
334 FLAG_SET_DEFAULT(UseSHA, true);
335 }
336 } else {
337 if (UseSHA) {
338 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
339 FLAG_SET_DEFAULT(UseSHA, false);
340 }
341 }
342 } else if (UseSHA) {
343 warning("SHA instructions are not available on this CPU");
344 FLAG_SET_DEFAULT(UseSHA, false);
345 }
346
347 if (UseSHA && has_sha1()) {
348 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
349 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
350 }
351 } else if (UseSHA1Intrinsics) {
352 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
353 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
354 }
355
356 if (UseSHA && has_sha256()) {
357 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
358 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
359 }
360 } else if (UseSHA256Intrinsics) {
361 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
362 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
363 }
364
365 if (UseSHA && has_sha512()) {
366 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
367 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
368 }
369 } else if (UseSHA512Intrinsics) {
370 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
371 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
372 }
373
374 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
375 FLAG_SET_DEFAULT(UseSHA, false);
376 }
377
378 if (has_crc32c()) {
379 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
380 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
381 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
382 }
383 } else {
384 if (UseCRC32CIntrinsics) {
385 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
386 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
387 }
388 }
389 } else if (UseCRC32CIntrinsics) {
390 warning("CRC32C instruction is not available on this CPU");
391 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
392 }
393
394 if (UseVIS > 2) {
395 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
396 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
397 }
398 } else if (UseAdler32Intrinsics) {
399 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
400 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
401 }
402
403 if (UseVIS > 2) {
404 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
405 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
406 }
407 } else if (UseCRC32Intrinsics) {
408 warning("SPARC CRC32 intrinsics require VIS3 instructions support. Intrinsics will be disabled");
409 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
410 }
411
412 if (UseVectorizedMismatchIntrinsic) {
413 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
414 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
415 }
416
417 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
418 (cache_line_size > ContendedPaddingWidth))
419 ContendedPaddingWidth = cache_line_size;
420
421 // This machine does not allow unaligned memory accesses
422 if (UseUnalignedAccesses) {
423 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
424 warning("Unaligned memory access is not available on this CPU");
425 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
426 }
427
428 if (log_is_enabled(Info, os, cpu)) {
429 ResourceMark rm;
430 LogStream ls(Log(os, cpu)::info());
431 outputStream* log = &ls;
432 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
433 log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
434 log->print("Allocation");
435 if (AllocatePrefetchStyle <= 0) {
436 log->print(": no prefetching");
437 } else {
438 log->print(" prefetching: ");
439 if (AllocatePrefetchInstr == 0) {
440 log->print("PREFETCH");
441 } else if (AllocatePrefetchInstr == 1) {
442 log->print("BIS");
443 }
444 if (AllocatePrefetchLines > 1) {
445 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
446 } else {
447 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
448 }
449 }
450 if (PrefetchCopyIntervalInBytes > 0) {
451 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
452 }
453 if (PrefetchScanIntervalInBytes > 0) {
454 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
455 }
456 if (PrefetchFieldsAhead > 0) {
457 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
458 }
459 if (ContendedPaddingWidth > 0) {
460 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
461 }
462 }
463 }
464
465 void VM_Version::print_features() {
466 tty->print("ISA features [0x%0" PRIx64 "]:", _features);
467 if (_features_string != NULL) {
468 tty->print(" %s", _features_string);
469 }
470 tty->cr();
471 }
472
473 void VM_Version::determine_features() {
474 platform_features(); // platform_features() is os_arch specific.
475
476 assert(has_v9(), "must be");
477
478 if (UseNiagaraInstrs) { // Limit code generation to Niagara.
479 _features &= niagara1_msk;
480 }
481 }
482
483 static uint64_t saved_features = 0;
484
485 void VM_Version::allow_all() {
486 saved_features = _features;
487 _features = full_feature_msk;
488 }
489
490 void VM_Version::revert() {
491 _features = saved_features;
492 }
493
494 /* Determine a suitable number of threads on this particular machine.
495 *
496 * FIXME: Simply checking the processor family is insufficient.
497 */
498 unsigned int VM_Version::calc_parallel_worker_threads() {
499 const int num = 5;
500 const int den = is_post_niagara() ? 16 : 8;
501 const int threshold = 8;
502
503 return nof_parallel_worker_threads(num, den, threshold);
504 }