9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "logging/log.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "prims/jvm.h"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "vm_version_x86.hpp"
35
36
37 int VM_Version::_cpu;
38 int VM_Version::_model;
39 int VM_Version::_stepping;
40 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
41
42 // Address of instruction which causes SEGV
43 address VM_Version::_cpuinfo_segv_addr = 0;
44 // Address of instruction after the one which causes SEGV
45 address VM_Version::_cpuinfo_cont_addr = 0;
46
47 static BufferBlob* stub_blob;
48 static const int stub_size = 1000;
1345 }
1346 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1347 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1348 }
1349 if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
1350 FLAG_SET_DEFAULT(PrefetchFieldsAhead, 1);
1351 }
1352 #endif
1353
1354 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1355 (cache_line_size > ContendedPaddingWidth))
1356 ContendedPaddingWidth = cache_line_size;
1357
1358 // This machine allows unaligned memory accesses
1359 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1360 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1361 }
1362
1363 #ifndef PRODUCT
1364 if (log_is_enabled(Info, os, cpu)) {
1365 outputStream* log = Log(os, cpu)::info_stream();
1366 log->print_cr("Logical CPUs per core: %u",
1367 logical_processors_per_package());
1368 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1369 log->print("UseSSE=%d", (int) UseSSE);
1370 if (UseAVX > 0) {
1371 log->print(" UseAVX=%d", (int) UseAVX);
1372 }
1373 if (UseAES) {
1374 log->print(" UseAES=1");
1375 }
1376 #ifdef COMPILER2
1377 if (MaxVectorSize > 0) {
1378 log->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1379 }
1380 #endif
1381 log->cr();
1382 log->print("Allocation");
1383 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
1384 log->print_cr(": no prefetching");
1385 } else {
|
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "logging/log.hpp"
29 #include "logging/logStream.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "prims/jvm.h"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "vm_version_x86.hpp"
36
37
38 int VM_Version::_cpu;
39 int VM_Version::_model;
40 int VM_Version::_stepping;
41 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
42
43 // Address of instruction which causes SEGV
44 address VM_Version::_cpuinfo_segv_addr = 0;
45 // Address of instruction after the one which causes SEGV
46 address VM_Version::_cpuinfo_cont_addr = 0;
47
48 static BufferBlob* stub_blob;
49 static const int stub_size = 1000;
1346 }
1347 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1348 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1349 }
1350 if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
1351 FLAG_SET_DEFAULT(PrefetchFieldsAhead, 1);
1352 }
1353 #endif
1354
1355 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1356 (cache_line_size > ContendedPaddingWidth))
1357 ContendedPaddingWidth = cache_line_size;
1358
1359 // This machine allows unaligned memory accesses
1360 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1361 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1362 }
1363
1364 #ifndef PRODUCT
1365 if (log_is_enabled(Info, os, cpu)) {
1366 LogStream ls(Log(os, cpu)::info());
1367 outputStream* log = &ls;
1368 log->print_cr("Logical CPUs per core: %u",
1369 logical_processors_per_package());
1370 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1371 log->print("UseSSE=%d", (int) UseSSE);
1372 if (UseAVX > 0) {
1373 log->print(" UseAVX=%d", (int) UseAVX);
1374 }
1375 if (UseAES) {
1376 log->print(" UseAES=1");
1377 }
1378 #ifdef COMPILER2
1379 if (MaxVectorSize > 0) {
1380 log->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1381 }
1382 #endif
1383 log->cr();
1384 log->print("Allocation");
1385 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
1386 log->print_cr(": no prefetching");
1387 } else {
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