1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "logging/log.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "runtime/java.hpp"
30 #include "runtime/os.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_sparc.hpp"
33
34 unsigned int VM_Version::_L2_data_cache_line_size = 0;
35
36 void VM_Version::initialize() {
37 assert(_features != 0, "System pre-initialization is not complete.");
38 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
39
40 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
41 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
42 PrefetchFieldsAhead = prefetch_fields_ahead();
43
44 // Allocation prefetch settings
45 intx cache_line_size = prefetch_data_size();
46 if( cache_line_size > AllocatePrefetchStepSize )
47 AllocatePrefetchStepSize = cache_line_size;
48
49 AllocatePrefetchDistance = allocate_prefetch_distance();
50 AllocatePrefetchStyle = allocate_prefetch_style();
51
52 if (!has_blk_init() || cache_line_size <= 0) {
53 if (AllocatePrefetchInstr == 1) {
54 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
55 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
56 }
57 }
58
59 UseSSE = 0; // Only on x86 and x64
60
61 _supports_cx8 = has_v9();
62 _supports_atomic_getset4 = true; // swap instruction
63
64 if (is_niagara()) {
65 // Indirect branch is the same cost as direct
66 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
67 FLAG_SET_DEFAULT(UseInlineCaches, false);
68 }
69 // Align loops on a single instruction boundary.
70 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
71 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
72 }
73 // 32-bit oops don't make sense for the 64-bit VM on sparc
74 // since the 32-bit VM has the same registers and smaller objects.
75 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
76 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
77 #ifdef COMPILER2
78 // Indirect branch is the same cost as direct
79 if (FLAG_IS_DEFAULT(UseJumpTables)) {
80 FLAG_SET_DEFAULT(UseJumpTables, true);
81 }
82 // Single-issue, so entry and loop tops are
83 // aligned on a single instruction boundary
84 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
85 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
86 }
87 if (is_niagara_plus()) {
88 if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
89 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
90 if (!has_sparc5_instr()) {
91 // Use BIS instruction for TLAB allocation prefetch
92 // on Niagara plus processors other than those based on CoreS4
93 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
94 } else {
95 // On CoreS4 processors use prefetch instruction
96 // to avoid partial RAW issue, also use prefetch style 3
97 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
98 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
99 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
100 }
101 }
102 }
103 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
104 if (AllocatePrefetchInstr == 0) {
105 // Use different prefetch distance without BIS
106 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
107 } else {
108 // Use smaller prefetch distance with BIS
109 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
110 }
111 }
112 if (is_T4()) {
113 // Double number of prefetched cache lines on T4
114 // since L2 cache line size is smaller (32 bytes).
115 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
116 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
117 }
118 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
119 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
120 }
121 }
122 }
123
124 if (AllocatePrefetchInstr == 1) {
125 // Use allocation prefetch style 3 because BIS instructions
126 // require aligned memory addresses.
127 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
128 }
129 #endif /* COMPILER2 */
130 }
131
132 // Use hardware population count instruction if available.
133 if (has_hardware_popc()) {
134 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
135 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
136 }
137 } else if (UsePopCountInstruction) {
138 warning("POPC instruction is not available on this CPU");
139 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
140 }
141
142 // T4 and newer Sparc cpus have new compare and branch instruction.
143 if (has_cbcond()) {
144 if (FLAG_IS_DEFAULT(UseCBCond)) {
145 FLAG_SET_DEFAULT(UseCBCond, true);
146 }
147 } else if (UseCBCond) {
148 warning("CBCOND instruction is not available on this CPU");
149 FLAG_SET_DEFAULT(UseCBCond, false);
150 }
151
152 assert(BlockZeroingLowLimit > 0, "invalid value");
153 if (has_block_zeroing() && cache_line_size > 0) {
154 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
155 FLAG_SET_DEFAULT(UseBlockZeroing, true);
156 }
157 } else if (UseBlockZeroing) {
158 warning("BIS zeroing instructions are not available on this CPU");
159 FLAG_SET_DEFAULT(UseBlockZeroing, false);
160 }
161
162 assert(BlockCopyLowLimit > 0, "invalid value");
163 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
164 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
165 FLAG_SET_DEFAULT(UseBlockCopy, true);
166 }
167 } else if (UseBlockCopy) {
168 warning("BIS instructions are not available or expensive on this CPU");
169 FLAG_SET_DEFAULT(UseBlockCopy, false);
170 }
171
172 #ifdef COMPILER2
173 // T4 and newer Sparc cpus have fast RDPC.
174 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
175 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
176 }
177
178 // Currently not supported anywhere.
179 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
180
181 MaxVectorSize = 8;
182
183 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
184 #endif
185
186 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
187 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
188
189 char buf[512];
190 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
191 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
192 (has_hardware_popc() ? ", popc" : ""),
193 (has_vis1() ? ", vis1" : ""),
194 (has_vis2() ? ", vis2" : ""),
195 (has_vis3() ? ", vis3" : ""),
196 (has_blk_init() ? ", blk_init" : ""),
197 (has_cbcond() ? ", cbcond" : ""),
198 (has_aes() ? ", aes" : ""),
199 (has_sha1() ? ", sha1" : ""),
200 (has_sha256() ? ", sha256" : ""),
201 (has_sha512() ? ", sha512" : ""),
202 (has_crc32c() ? ", crc32c" : ""),
203 (is_ultra3() ? ", ultra3" : ""),
204 (has_sparc5_instr() ? ", sparc5" : ""),
205 (is_sun4v() ? ", sun4v" : ""),
206 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
207 (is_sparc64() ? ", sparc64" : ""),
208 (!has_hardware_mul32() ? ", no-mul32" : ""),
209 (!has_hardware_div32() ? ", no-div32" : ""),
210 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
211
212 // buf is started with ", " or is empty
213 _features_string = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
214
215 // UseVIS is set to the smallest of what hardware supports and what
216 // the command line requires. I.e., you cannot set UseVIS to 3 on
217 // older UltraSparc which do not support it.
218 if (UseVIS > 3) UseVIS=3;
219 if (UseVIS < 0) UseVIS=0;
220 if (!has_vis3()) // Drop to 2 if no VIS3 support
221 UseVIS = MIN2((intx)2,UseVIS);
222 if (!has_vis2()) // Drop to 1 if no VIS2 support
223 UseVIS = MIN2((intx)1,UseVIS);
224 if (!has_vis1()) // Drop to 0 if no VIS1 support
225 UseVIS = 0;
226
227 // SPARC T4 and above should have support for AES instructions
228 if (has_aes()) {
229 if (FLAG_IS_DEFAULT(UseAES)) {
230 FLAG_SET_DEFAULT(UseAES, true);
231 }
232 if (!UseAES) {
233 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
234 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
235 }
236 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
237 } else {
238 // The AES intrinsic stubs require AES instruction support (of course)
239 // but also require VIS3 mode or higher for instructions it use.
240 if (UseVIS > 2) {
241 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
242 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
243 }
244 } else {
245 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
246 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
247 }
248 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
249 }
250 }
251 } else if (UseAES || UseAESIntrinsics) {
252 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
253 warning("AES instructions are not available on this CPU");
254 FLAG_SET_DEFAULT(UseAES, false);
255 }
256 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
257 warning("AES intrinsics are not available on this CPU");
258 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
259 }
260 }
261
262 if (UseAESCTRIntrinsics) {
263 warning("AES/CTR intrinsics are not available on this CPU");
264 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
265 }
266
267 // GHASH/GCM intrinsics
268 if (has_vis3() && (UseVIS > 2)) {
269 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
270 UseGHASHIntrinsics = true;
271 }
272 } else if (UseGHASHIntrinsics) {
273 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
274 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
275 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
276 }
277
278 if (UseFMA) {
279 warning("FMA instructions are not available on this CPU");
280 FLAG_SET_DEFAULT(UseFMA, false);
281 }
282
283 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
284 if (has_sha1() || has_sha256() || has_sha512()) {
285 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
286 if (FLAG_IS_DEFAULT(UseSHA)) {
287 FLAG_SET_DEFAULT(UseSHA, true);
288 }
289 } else {
290 if (UseSHA) {
291 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
292 FLAG_SET_DEFAULT(UseSHA, false);
293 }
294 }
295 } else if (UseSHA) {
296 warning("SHA instructions are not available on this CPU");
297 FLAG_SET_DEFAULT(UseSHA, false);
298 }
299
300 if (UseSHA && has_sha1()) {
301 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
302 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
303 }
304 } else if (UseSHA1Intrinsics) {
305 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
306 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
307 }
308
309 if (UseSHA && has_sha256()) {
310 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
311 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
312 }
313 } else if (UseSHA256Intrinsics) {
314 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
315 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
316 }
317
318 if (UseSHA && has_sha512()) {
319 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
320 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
321 }
322 } else if (UseSHA512Intrinsics) {
323 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
324 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
325 }
326
327 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
328 FLAG_SET_DEFAULT(UseSHA, false);
329 }
330
331 // SPARC T4 and above should have support for CRC32C instruction
332 if (has_crc32c()) {
333 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
334 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
335 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
336 }
337 } else {
338 if (UseCRC32CIntrinsics) {
339 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
340 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
341 }
342 }
343 } else if (UseCRC32CIntrinsics) {
344 warning("CRC32C instruction is not available on this CPU");
345 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
346 }
347
348 if (UseVIS > 2) {
349 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
350 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
351 }
352 } else if (UseAdler32Intrinsics) {
353 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
354 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
355 }
356
357 if (UseVIS > 2) {
358 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
359 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
360 }
361 } else if (UseCRC32Intrinsics) {
362 warning("SPARC CRC32 intrinsics require VIS3 instructions support. Intrinsics will be disabled");
363 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
364 }
365
366 if (UseVectorizedMismatchIntrinsic) {
367 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
368 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
369 }
370
371 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
372 (cache_line_size > ContendedPaddingWidth))
373 ContendedPaddingWidth = cache_line_size;
374
375 // This machine does not allow unaligned memory accesses
376 if (UseUnalignedAccesses) {
377 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
378 warning("Unaligned memory access is not available on this CPU");
379 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
380 }
381
382 if (log_is_enabled(Info, os, cpu)) {
383 ResourceMark rm;
384 outputStream* log = Log(os, cpu)::info_stream();
385 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
386 log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
387 log->print("Allocation");
388 if (AllocatePrefetchStyle <= 0) {
389 log->print(": no prefetching");
390 } else {
391 log->print(" prefetching: ");
392 if (AllocatePrefetchInstr == 0) {
393 log->print("PREFETCH");
394 } else if (AllocatePrefetchInstr == 1) {
395 log->print("BIS");
396 }
397 if (AllocatePrefetchLines > 1) {
398 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
399 } else {
400 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
401 }
402 }
403 if (PrefetchCopyIntervalInBytes > 0) {
404 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
405 }
406 if (PrefetchScanIntervalInBytes > 0) {
407 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
408 }
409 if (PrefetchFieldsAhead > 0) {
410 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
411 }
412 if (ContendedPaddingWidth > 0) {
413 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
414 }
415 }
416 }
417
418 void VM_Version::print_features() {
419 tty->print_cr("Version:%s", _features);
420 }
421
422 int VM_Version::determine_features() {
423 if (UseV8InstrsOnly) {
424 log_info(os, cpu)("Version is Forced-V8");
425 return generic_v8_m;
426 }
427
428 int features = platform_features(unknown_m); // platform_features() is os_arch specific
429
430 if (features == unknown_m) {
431 features = generic_v9_m;
432 log_info(os)("Cannot recognize SPARC version. Default to V9");
433 }
434
435 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
436 if (UseNiagaraInstrs) { // Force code generation for Niagara
437 if (is_T_family(features)) {
438 // Happy to accomodate...
439 } else {
440 log_info(os, cpu)("Version is Forced-Niagara");
441 features |= T_family_m;
442 }
443 } else {
444 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
445 log_info(os, cpu)("Version is Forced-Not-Niagara");
446 features &= ~(T_family_m | T1_model_m);
447 } else {
448 // Happy to accomodate...
449 }
450 }
451
452 return features;
453 }
454
455 static uint64_t saved_features = 0;
456
457 void VM_Version::allow_all() {
458 saved_features = _features;
459 _features = all_features_m;
460 }
461
462 void VM_Version::revert() {
463 _features = saved_features;
464 }
465
466 unsigned int VM_Version::calc_parallel_worker_threads() {
467 unsigned int result;
468 if (is_M_series() || is_S_series()) {
469 // for now, use same gc thread calculation for M-series and S-series as for
470 // niagara-plus. In future, we may want to tweak parameters for
471 // nof_parallel_worker_thread
472 result = nof_parallel_worker_threads(5, 16, 8);
473 } else if (is_niagara_plus()) {
474 result = nof_parallel_worker_threads(5, 16, 8);
475 } else {
476 result = nof_parallel_worker_threads(5, 8, 8);
477 }
478 return result;
479 }
480
481
482 int VM_Version::parse_features(const char* implementation) {
483 int features = unknown_m;
484 // Convert to UPPER case before compare.
485 char* impl = os::strdup_check_oom(implementation);
486
487 for (int i = 0; impl[i] != 0; i++)
488 impl[i] = (char)toupper((uint)impl[i]);
489
490 if (strstr(impl, "SPARC64") != NULL) {
491 features |= sparc64_family_m;
492 } else if (strstr(impl, "SPARC-M") != NULL) {
493 // M-series SPARC is based on T-series.
494 features |= (M_family_m | T_family_m);
495 } else if (strstr(impl, "SPARC-S") != NULL) {
496 // S-series SPARC is based on T-series.
497 features |= (S_family_m | T_family_m);
498 } else if (strstr(impl, "SPARC-T") != NULL) {
499 features |= T_family_m;
500 if (strstr(impl, "SPARC-T1") != NULL) {
501 features |= T1_model_m;
502 }
503 } else if (strstr(impl, "SUN4V-CPU") != NULL) {
504 // Generic or migration class LDOM
505 features |= T_family_m;
506 } else {
507 log_info(os, cpu)("Failed to parse CPU implementation = '%s'", impl);
508 }
509 os::free((void*)impl);
510 return features;
511 }