319 CPU_BMI1 = (1 << 22),
320 CPU_BMI2 = (1 << 23),
321 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
322 CPU_ADX = (1 << 25),
323 CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
324 CPU_AVX512DQ = (1 << 27),
325 CPU_AVX512PF = (1 << 28),
326 CPU_AVX512ER = (1 << 29),
327 CPU_AVX512CD = (1 << 30)
328 // Keeping sign bit 31 unassigned.
329 };
330
331 #define CPU_AVX512BW ((uint64_t)UCONST64(0x100000000)) // enums are limited to 31 bit
332 #define CPU_AVX512VL ((uint64_t)UCONST64(0x200000000)) // EVEX instructions with smaller vector length
333 #define CPU_SHA ((uint64_t)UCONST64(0x400000000)) // SHA instructions
334 #define CPU_FMA ((uint64_t)UCONST64(0x800000000)) // FMA instructions
335 #define CPU_VZEROUPPER ((uint64_t)UCONST64(0x1000000000)) // Vzeroupper instruction
336 #define CPU_AVX512_VPOPCNTDQ ((uint64_t)UCONST64(0x2000000000)) // Vector popcount
337 #define CPU_VPCLMULQDQ ((uint64_t)UCONST64(0x4000000000)) //Vector carryless multiplication
338 #define CPU_VAES ((uint64_t)UCONST64(0x8000000000)) // Vector AES instructions
339 #define CPU_VNNI ((uint64_t)UCONST64(0x16000000000)) // Vector Neural Network Instructions
340
341 enum Extended_Family {
342 // AMD
343 CPU_FAMILY_AMD_11H = 0x11,
344 // ZX
345 CPU_FAMILY_ZX_CORE_F6 = 6,
346 CPU_FAMILY_ZX_CORE_F7 = 7,
347 // Intel
348 CPU_FAMILY_INTEL_CORE = 6,
349 CPU_MODEL_NEHALEM = 0x1e,
350 CPU_MODEL_NEHALEM_EP = 0x1a,
351 CPU_MODEL_NEHALEM_EX = 0x2e,
352 CPU_MODEL_WESTMERE = 0x25,
353 CPU_MODEL_WESTMERE_EP = 0x2c,
354 CPU_MODEL_WESTMERE_EX = 0x2f,
355 CPU_MODEL_SANDYBRIDGE = 0x2a,
356 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
357 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
358 CPU_MODEL_HASWELL_E3 = 0x3c,
359 CPU_MODEL_HASWELL_E7 = 0x3f,
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319 CPU_BMI1 = (1 << 22),
320 CPU_BMI2 = (1 << 23),
321 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
322 CPU_ADX = (1 << 25),
323 CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
324 CPU_AVX512DQ = (1 << 27),
325 CPU_AVX512PF = (1 << 28),
326 CPU_AVX512ER = (1 << 29),
327 CPU_AVX512CD = (1 << 30)
328 // Keeping sign bit 31 unassigned.
329 };
330
331 #define CPU_AVX512BW ((uint64_t)UCONST64(0x100000000)) // enums are limited to 31 bit
332 #define CPU_AVX512VL ((uint64_t)UCONST64(0x200000000)) // EVEX instructions with smaller vector length
333 #define CPU_SHA ((uint64_t)UCONST64(0x400000000)) // SHA instructions
334 #define CPU_FMA ((uint64_t)UCONST64(0x800000000)) // FMA instructions
335 #define CPU_VZEROUPPER ((uint64_t)UCONST64(0x1000000000)) // Vzeroupper instruction
336 #define CPU_AVX512_VPOPCNTDQ ((uint64_t)UCONST64(0x2000000000)) // Vector popcount
337 #define CPU_VPCLMULQDQ ((uint64_t)UCONST64(0x4000000000)) //Vector carryless multiplication
338 #define CPU_VAES ((uint64_t)UCONST64(0x8000000000)) // Vector AES instructions
339 #define CPU_VNNI ((uint64_t)UCONST64(0x10000000000)) // Vector Neural Network Instructions
340
341 enum Extended_Family {
342 // AMD
343 CPU_FAMILY_AMD_11H = 0x11,
344 // ZX
345 CPU_FAMILY_ZX_CORE_F6 = 6,
346 CPU_FAMILY_ZX_CORE_F7 = 7,
347 // Intel
348 CPU_FAMILY_INTEL_CORE = 6,
349 CPU_MODEL_NEHALEM = 0x1e,
350 CPU_MODEL_NEHALEM_EP = 0x1a,
351 CPU_MODEL_NEHALEM_EX = 0x2e,
352 CPU_MODEL_WESTMERE = 0x25,
353 CPU_MODEL_WESTMERE_EP = 0x2c,
354 CPU_MODEL_WESTMERE_EX = 0x2f,
355 CPU_MODEL_SANDYBRIDGE = 0x2a,
356 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
357 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
358 CPU_MODEL_HASWELL_E3 = 0x3c,
359 CPU_MODEL_HASWELL_E7 = 0x3f,
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