1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableBarrierSet.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/objectMonitor.hpp"
35 #include "runtime/os.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #include "utilities/macros.hpp"
39
40 #ifdef PRODUCT
41 #define BLOCK_COMMENT(str) /* nothing */
42 #define STOP(error) stop(error)
43 #else
44 #define BLOCK_COMMENT(str) block_comment(str)
45 #define STOP(error) block_comment(error); stop(error)
46 #endif
47
48 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
49 // Implementation of AddressLiteral
50
51 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
52 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
53 // -----------------Table 4.5 -------------------- //
54 16, 32, 64, // EVEX_FV(0)
55 4, 4, 4, // EVEX_FV(1) - with Evex.b
56 16, 32, 64, // EVEX_FV(2) - with Evex.w
57 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
58 8, 16, 32, // EVEX_HV(0)
59 4, 4, 4, // EVEX_HV(1) - with Evex.b
60 // -----------------Table 4.6 -------------------- //
61 16, 32, 64, // EVEX_FVM(0)
62 1, 1, 1, // EVEX_T1S(0)
63 2, 2, 2, // EVEX_T1S(1)
64 4, 4, 4, // EVEX_T1S(2)
65 8, 8, 8, // EVEX_T1S(3)
66 4, 4, 4, // EVEX_T1F(0)
67 8, 8, 8, // EVEX_T1F(1)
68 8, 8, 8, // EVEX_T2(0)
69 0, 16, 16, // EVEX_T2(1)
70 0, 16, 16, // EVEX_T4(0)
71 0, 0, 32, // EVEX_T4(1)
72 0, 0, 32, // EVEX_T8(0)
73 8, 16, 32, // EVEX_HVM(0)
74 4, 8, 16, // EVEX_QVM(0)
75 2, 4, 8, // EVEX_OVM(0)
76 16, 16, 16, // EVEX_M128(0)
77 8, 32, 64, // EVEX_DUP(0)
78 0, 0, 0 // EVEX_NTUP
79 };
80
81 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
82 _is_lval = false;
83 _target = target;
84 switch (rtype) {
85 case relocInfo::oop_type:
86 case relocInfo::metadata_type:
87 // Oops are a special case. Normally they would be their own section
88 // but in cases like icBuffer they are literals in the code stream that
89 // we don't have a section for. We use none so that we get a literal address
90 // which is always patchable.
91 break;
92 case relocInfo::external_word_type:
93 _rspec = external_word_Relocation::spec(target);
94 break;
95 case relocInfo::internal_word_type:
96 _rspec = internal_word_Relocation::spec(target);
97 break;
98 case relocInfo::opt_virtual_call_type:
99 _rspec = opt_virtual_call_Relocation::spec();
100 break;
101 case relocInfo::static_call_type:
102 _rspec = static_call_Relocation::spec();
103 break;
104 case relocInfo::runtime_call_type:
105 _rspec = runtime_call_Relocation::spec();
106 break;
107 case relocInfo::poll_type:
108 case relocInfo::poll_return_type:
109 _rspec = Relocation::spec_simple(rtype);
110 break;
111 case relocInfo::none:
112 break;
113 default:
114 ShouldNotReachHere();
115 break;
116 }
117 }
118
119 // Implementation of Address
120
121 #ifdef _LP64
122
123 Address Address::make_array(ArrayAddress adr) {
124 // Not implementable on 64bit machines
125 // Should have been handled higher up the call chain.
126 ShouldNotReachHere();
127 return Address();
128 }
129
130 // exceedingly dangerous constructor
131 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
132 _base = noreg;
133 _index = noreg;
134 _scale = no_scale;
135 _disp = disp;
136 _xmmindex = xnoreg;
137 _isxmmindex = false;
138 switch (rtype) {
139 case relocInfo::external_word_type:
140 _rspec = external_word_Relocation::spec(loc);
141 break;
142 case relocInfo::internal_word_type:
143 _rspec = internal_word_Relocation::spec(loc);
144 break;
145 case relocInfo::runtime_call_type:
146 // HMM
147 _rspec = runtime_call_Relocation::spec();
148 break;
149 case relocInfo::poll_type:
150 case relocInfo::poll_return_type:
151 _rspec = Relocation::spec_simple(rtype);
152 break;
153 case relocInfo::none:
154 break;
155 default:
156 ShouldNotReachHere();
157 }
158 }
159 #else // LP64
160
161 Address Address::make_array(ArrayAddress adr) {
162 AddressLiteral base = adr.base();
163 Address index = adr.index();
164 assert(index._disp == 0, "must not have disp"); // maybe it can?
165 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
166 array._rspec = base._rspec;
167 return array;
168 }
169
170 // exceedingly dangerous constructor
171 Address::Address(address loc, RelocationHolder spec) {
172 _base = noreg;
173 _index = noreg;
174 _scale = no_scale;
175 _disp = (intptr_t) loc;
176 _rspec = spec;
177 _xmmindex = xnoreg;
178 _isxmmindex = false;
179 }
180
181 #endif // _LP64
182
183
184
185 // Convert the raw encoding form into the form expected by the constructor for
186 // Address. An index of 4 (rsp) corresponds to having no index, so convert
187 // that to noreg for the Address constructor.
188 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
189 RelocationHolder rspec;
190 if (disp_reloc != relocInfo::none) {
191 rspec = Relocation::spec_simple(disp_reloc);
192 }
193 bool valid_index = index != rsp->encoding();
194 if (valid_index) {
195 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
196 madr._rspec = rspec;
197 return madr;
198 } else {
199 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
200 madr._rspec = rspec;
201 return madr;
202 }
203 }
204
205 // Implementation of Assembler
206
207 int AbstractAssembler::code_fill_byte() {
208 return (u_char)'\xF4'; // hlt
209 }
210
211 // make this go away someday
212 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
213 if (rtype == relocInfo::none)
214 emit_int32(data);
215 else
216 emit_data(data, Relocation::spec_simple(rtype), format);
217 }
218
219 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
220 assert(imm_operand == 0, "default format must be immediate in this file");
221 assert(inst_mark() != NULL, "must be inside InstructionMark");
222 if (rspec.type() != relocInfo::none) {
223 #ifdef ASSERT
224 check_relocation(rspec, format);
225 #endif
226 // Do not use AbstractAssembler::relocate, which is not intended for
227 // embedded words. Instead, relocate to the enclosing instruction.
228
229 // hack. call32 is too wide for mask so use disp32
230 if (format == call32_operand)
231 code_section()->relocate(inst_mark(), rspec, disp32_operand);
232 else
233 code_section()->relocate(inst_mark(), rspec, format);
234 }
235 emit_int32(data);
236 }
237
238 static int encode(Register r) {
239 int enc = r->encoding();
240 if (enc >= 8) {
241 enc -= 8;
242 }
243 return enc;
244 }
245
246 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
247 assert(dst->has_byte_register(), "must have byte register");
248 assert(isByte(op1) && isByte(op2), "wrong opcode");
249 assert(isByte(imm8), "not a byte");
250 assert((op1 & 0x01) == 0, "should be 8bit operation");
251 emit_int8(op1);
252 emit_int8(op2 | encode(dst));
253 emit_int8(imm8);
254 }
255
256
257 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
258 assert(isByte(op1) && isByte(op2), "wrong opcode");
259 assert((op1 & 0x01) == 1, "should be 32bit operation");
260 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
261 if (is8bit(imm32)) {
262 emit_int8(op1 | 0x02); // set sign bit
263 emit_int8(op2 | encode(dst));
264 emit_int8(imm32 & 0xFF);
265 } else {
266 emit_int8(op1);
267 emit_int8(op2 | encode(dst));
268 emit_int32(imm32);
269 }
270 }
271
272 // Force generation of a 4 byte immediate value even if it fits into 8bit
273 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
274 assert(isByte(op1) && isByte(op2), "wrong opcode");
275 assert((op1 & 0x01) == 1, "should be 32bit operation");
276 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
277 emit_int8(op1);
278 emit_int8(op2 | encode(dst));
279 emit_int32(imm32);
280 }
281
282 // immediate-to-memory forms
283 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
284 assert((op1 & 0x01) == 1, "should be 32bit operation");
285 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
286 if (is8bit(imm32)) {
287 emit_int8(op1 | 0x02); // set sign bit
288 emit_operand(rm, adr, 1);
289 emit_int8(imm32 & 0xFF);
290 } else {
291 emit_int8(op1);
292 emit_operand(rm, adr, 4);
293 emit_int32(imm32);
294 }
295 }
296
297
298 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
299 assert(isByte(op1) && isByte(op2), "wrong opcode");
300 emit_int8(op1);
301 emit_int8(op2 | encode(dst) << 3 | encode(src));
302 }
303
304
305 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
306 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
307 int mod_idx = 0;
308 // We will test if the displacement fits the compressed format and if so
309 // apply the compression to the displacment iff the result is8bit.
310 if (VM_Version::supports_evex() && is_evex_inst) {
311 switch (cur_tuple_type) {
312 case EVEX_FV:
313 if ((cur_encoding & VEX_W) == VEX_W) {
314 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
315 } else {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 }
318 break;
319
320 case EVEX_HV:
321 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
322 break;
323
324 case EVEX_FVM:
325 break;
326
327 case EVEX_T1S:
328 switch (in_size_in_bits) {
329 case EVEX_8bit:
330 break;
331
332 case EVEX_16bit:
333 mod_idx = 1;
334 break;
335
336 case EVEX_32bit:
337 mod_idx = 2;
338 break;
339
340 case EVEX_64bit:
341 mod_idx = 3;
342 break;
343 }
344 break;
345
346 case EVEX_T1F:
347 case EVEX_T2:
348 case EVEX_T4:
349 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
350 break;
351
352 case EVEX_T8:
353 break;
354
355 case EVEX_HVM:
356 break;
357
358 case EVEX_QVM:
359 break;
360
361 case EVEX_OVM:
362 break;
363
364 case EVEX_M128:
365 break;
366
367 case EVEX_DUP:
368 break;
369
370 default:
371 assert(0, "no valid evex tuple_table entry");
372 break;
373 }
374
375 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
376 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
377 if ((disp % disp_factor) == 0) {
378 int new_disp = disp / disp_factor;
379 if ((-0x80 <= new_disp && new_disp < 0x80)) {
380 disp = new_disp;
381 }
382 } else {
383 return false;
384 }
385 }
386 }
387 return (-0x80 <= disp && disp < 0x80);
388 }
389
390
391 bool Assembler::emit_compressed_disp_byte(int &disp) {
392 int mod_idx = 0;
393 // We will test if the displacement fits the compressed format and if so
394 // apply the compression to the displacment iff the result is8bit.
395 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
396 int evex_encoding = _attributes->get_evex_encoding();
397 int tuple_type = _attributes->get_tuple_type();
398 switch (tuple_type) {
399 case EVEX_FV:
400 if ((evex_encoding & VEX_W) == VEX_W) {
401 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
402 } else {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (_attributes->get_input_size()) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 int vector_len = _attributes->get_vector_len();
463 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
464 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
465 if ((disp % disp_factor) == 0) {
466 int new_disp = disp / disp_factor;
467 if (is8bit(new_disp)) {
468 disp = new_disp;
469 }
470 } else {
471 return false;
472 }
473 }
474 }
475 return is8bit(disp);
476 }
477
478
479 void Assembler::emit_operand(Register reg, Register base, Register index,
480 Address::ScaleFactor scale, int disp,
481 RelocationHolder const& rspec,
482 int rip_relative_correction) {
483 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
484
485 // Encode the registers as needed in the fields they are used in
486
487 int regenc = encode(reg) << 3;
488 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
489 int baseenc = base->is_valid() ? encode(base) : 0;
490
491 if (base->is_valid()) {
492 if (index->is_valid()) {
493 assert(scale != Address::no_scale, "inconsistent address");
494 // [base + index*scale + disp]
495 if (disp == 0 && rtype == relocInfo::none &&
496 base != rbp LP64_ONLY(&& base != r13)) {
497 // [base + index*scale]
498 // [00 reg 100][ss index base]
499 assert(index != rsp, "illegal addressing mode");
500 emit_int8(0x04 | regenc);
501 emit_int8(scale << 6 | indexenc | baseenc);
502 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
503 // [base + index*scale + imm8]
504 // [01 reg 100][ss index base] imm8
505 assert(index != rsp, "illegal addressing mode");
506 emit_int8(0x44 | regenc);
507 emit_int8(scale << 6 | indexenc | baseenc);
508 emit_int8(disp & 0xFF);
509 } else {
510 // [base + index*scale + disp32]
511 // [10 reg 100][ss index base] disp32
512 assert(index != rsp, "illegal addressing mode");
513 emit_int8(0x84 | regenc);
514 emit_int8(scale << 6 | indexenc | baseenc);
515 emit_data(disp, rspec, disp32_operand);
516 }
517 } else if (base == rsp LP64_ONLY(|| base == r12)) {
518 // [rsp + disp]
519 if (disp == 0 && rtype == relocInfo::none) {
520 // [rsp]
521 // [00 reg 100][00 100 100]
522 emit_int8(0x04 | regenc);
523 emit_int8(0x24);
524 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
525 // [rsp + imm8]
526 // [01 reg 100][00 100 100] disp8
527 emit_int8(0x44 | regenc);
528 emit_int8(0x24);
529 emit_int8(disp & 0xFF);
530 } else {
531 // [rsp + imm32]
532 // [10 reg 100][00 100 100] disp32
533 emit_int8(0x84 | regenc);
534 emit_int8(0x24);
535 emit_data(disp, rspec, disp32_operand);
536 }
537 } else {
538 // [base + disp]
539 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
540 if (disp == 0 && rtype == relocInfo::none &&
541 base != rbp LP64_ONLY(&& base != r13)) {
542 // [base]
543 // [00 reg base]
544 emit_int8(0x00 | regenc | baseenc);
545 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
546 // [base + disp8]
547 // [01 reg base] disp8
548 emit_int8(0x40 | regenc | baseenc);
549 emit_int8(disp & 0xFF);
550 } else {
551 // [base + disp32]
552 // [10 reg base] disp32
553 emit_int8(0x80 | regenc | baseenc);
554 emit_data(disp, rspec, disp32_operand);
555 }
556 }
557 } else {
558 if (index->is_valid()) {
559 assert(scale != Address::no_scale, "inconsistent address");
560 // [index*scale + disp]
561 // [00 reg 100][ss index 101] disp32
562 assert(index != rsp, "illegal addressing mode");
563 emit_int8(0x04 | regenc);
564 emit_int8(scale << 6 | indexenc | 0x05);
565 emit_data(disp, rspec, disp32_operand);
566 } else if (rtype != relocInfo::none ) {
567 // [disp] (64bit) RIP-RELATIVE (32bit) abs
568 // [00 000 101] disp32
569
570 emit_int8(0x05 | regenc);
571 // Note that the RIP-rel. correction applies to the generated
572 // disp field, but _not_ to the target address in the rspec.
573
574 // disp was created by converting the target address minus the pc
575 // at the start of the instruction. That needs more correction here.
576 // intptr_t disp = target - next_ip;
577 assert(inst_mark() != NULL, "must be inside InstructionMark");
578 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
579 int64_t adjusted = disp;
580 // Do rip-rel adjustment for 64bit
581 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
582 assert(is_simm32(adjusted),
583 "must be 32bit offset (RIP relative address)");
584 emit_data((int32_t) adjusted, rspec, disp32_operand);
585
586 } else {
587 // 32bit never did this, did everything as the rip-rel/disp code above
588 // [disp] ABSOLUTE
589 // [00 reg 100][00 100 101] disp32
590 emit_int8(0x04 | regenc);
591 emit_int8(0x25);
592 emit_data(disp, rspec, disp32_operand);
593 }
594 }
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 void Assembler::emit_operand(XMMRegister reg, Register base, XMMRegister index,
612 Address::ScaleFactor scale, int disp,
613 RelocationHolder const& rspec) {
614 if (UseAVX > 2) {
615 int xreg_enc = reg->encoding();
616 int xmmindex_enc = index->encoding();
617 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
618 XMMRegister new_index = as_XMMRegister(xmmindex_enc & 0xf);
619 emit_operand((Register)new_reg, base, (Register)new_index, scale, disp, rspec);
620 } else {
621 emit_operand((Register)reg, base, (Register)index, scale, disp, rspec);
622 }
623 }
624
625
626 // Secret local extension to Assembler::WhichOperand:
627 #define end_pc_operand (_WhichOperand_limit)
628
629 address Assembler::locate_operand(address inst, WhichOperand which) {
630 // Decode the given instruction, and return the address of
631 // an embedded 32-bit operand word.
632
633 // If "which" is disp32_operand, selects the displacement portion
634 // of an effective address specifier.
635 // If "which" is imm64_operand, selects the trailing immediate constant.
636 // If "which" is call32_operand, selects the displacement of a call or jump.
637 // Caller is responsible for ensuring that there is such an operand,
638 // and that it is 32/64 bits wide.
639
640 // If "which" is end_pc_operand, find the end of the instruction.
641
642 address ip = inst;
643 bool is_64bit = false;
644
645 debug_only(bool has_disp32 = false);
646 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
647
648 again_after_prefix:
649 switch (0xFF & *ip++) {
650
651 // These convenience macros generate groups of "case" labels for the switch.
652 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
653 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
654 case (x)+4: case (x)+5: case (x)+6: case (x)+7
655 #define REP16(x) REP8((x)+0): \
656 case REP8((x)+8)
657
658 case CS_segment:
659 case SS_segment:
660 case DS_segment:
661 case ES_segment:
662 case FS_segment:
663 case GS_segment:
664 // Seems dubious
665 LP64_ONLY(assert(false, "shouldn't have that prefix"));
666 assert(ip == inst+1, "only one prefix allowed");
667 goto again_after_prefix;
668
669 case 0x67:
670 case REX:
671 case REX_B:
672 case REX_X:
673 case REX_XB:
674 case REX_R:
675 case REX_RB:
676 case REX_RX:
677 case REX_RXB:
678 NOT_LP64(assert(false, "64bit prefixes"));
679 goto again_after_prefix;
680
681 case REX_W:
682 case REX_WB:
683 case REX_WX:
684 case REX_WXB:
685 case REX_WR:
686 case REX_WRB:
687 case REX_WRX:
688 case REX_WRXB:
689 NOT_LP64(assert(false, "64bit prefixes"));
690 is_64bit = true;
691 goto again_after_prefix;
692
693 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
694 case 0x88: // movb a, r
695 case 0x89: // movl a, r
696 case 0x8A: // movb r, a
697 case 0x8B: // movl r, a
698 case 0x8F: // popl a
699 debug_only(has_disp32 = true);
700 break;
701
702 case 0x68: // pushq #32
703 if (which == end_pc_operand) {
704 return ip + 4;
705 }
706 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
707 return ip; // not produced by emit_operand
708
709 case 0x66: // movw ... (size prefix)
710 again_after_size_prefix2:
711 switch (0xFF & *ip++) {
712 case REX:
713 case REX_B:
714 case REX_X:
715 case REX_XB:
716 case REX_R:
717 case REX_RB:
718 case REX_RX:
719 case REX_RXB:
720 case REX_W:
721 case REX_WB:
722 case REX_WX:
723 case REX_WXB:
724 case REX_WR:
725 case REX_WRB:
726 case REX_WRX:
727 case REX_WRXB:
728 NOT_LP64(assert(false, "64bit prefix found"));
729 goto again_after_size_prefix2;
730 case 0x8B: // movw r, a
731 case 0x89: // movw a, r
732 debug_only(has_disp32 = true);
733 break;
734 case 0xC7: // movw a, #16
735 debug_only(has_disp32 = true);
736 tail_size = 2; // the imm16
737 break;
738 case 0x0F: // several SSE/SSE2 variants
739 ip--; // reparse the 0x0F
740 goto again_after_prefix;
741 default:
742 ShouldNotReachHere();
743 }
744 break;
745
746 case REP8(0xB8): // movl/q r, #32/#64(oop?)
747 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
748 // these asserts are somewhat nonsensical
749 #ifndef _LP64
750 assert(which == imm_operand || which == disp32_operand,
751 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
752 #else
753 assert((which == call32_operand || which == imm_operand) && is_64bit ||
754 which == narrow_oop_operand && !is_64bit,
755 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
756 #endif // _LP64
757 return ip;
758
759 case 0x69: // imul r, a, #32
760 case 0xC7: // movl a, #32(oop?)
761 tail_size = 4;
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 break;
764
765 case 0x0F: // movx..., etc.
766 switch (0xFF & *ip++) {
767 case 0x3A: // pcmpestri
768 tail_size = 1;
769 case 0x38: // ptest, pmovzxbw
770 ip++; // skip opcode
771 debug_only(has_disp32 = true); // has both kinds of operands!
772 break;
773
774 case 0x70: // pshufd r, r/a, #8
775 debug_only(has_disp32 = true); // has both kinds of operands!
776 case 0x73: // psrldq r, #8
777 tail_size = 1;
778 break;
779
780 case 0x12: // movlps
781 case 0x28: // movaps
782 case 0x2E: // ucomiss
783 case 0x2F: // comiss
784 case 0x54: // andps
785 case 0x55: // andnps
786 case 0x56: // orps
787 case 0x57: // xorps
788 case 0x58: // addpd
789 case 0x59: // mulpd
790 case 0x6E: // movd
791 case 0x7E: // movd
792 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
793 case 0xFE: // paddd
794 debug_only(has_disp32 = true);
795 break;
796
797 case 0xAD: // shrd r, a, %cl
798 case 0xAF: // imul r, a
799 case 0xBE: // movsbl r, a (movsxb)
800 case 0xBF: // movswl r, a (movsxw)
801 case 0xB6: // movzbl r, a (movzxb)
802 case 0xB7: // movzwl r, a (movzxw)
803 case REP16(0x40): // cmovl cc, r, a
804 case 0xB0: // cmpxchgb
805 case 0xB1: // cmpxchg
806 case 0xC1: // xaddl
807 case 0xC7: // cmpxchg8
808 case REP16(0x90): // setcc a
809 debug_only(has_disp32 = true);
810 // fall out of the switch to decode the address
811 break;
812
813 case 0xC4: // pinsrw r, a, #8
814 debug_only(has_disp32 = true);
815 case 0xC5: // pextrw r, r, #8
816 tail_size = 1; // the imm8
817 break;
818
819 case 0xAC: // shrd r, a, #8
820 debug_only(has_disp32 = true);
821 tail_size = 1; // the imm8
822 break;
823
824 case REP16(0x80): // jcc rdisp32
825 if (which == end_pc_operand) return ip + 4;
826 assert(which == call32_operand, "jcc has no disp32 or imm");
827 return ip;
828 default:
829 ShouldNotReachHere();
830 }
831 break;
832
833 case 0x81: // addl a, #32; addl r, #32
834 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
835 // on 32bit in the case of cmpl, the imm might be an oop
836 tail_size = 4;
837 debug_only(has_disp32 = true); // has both kinds of operands!
838 break;
839
840 case 0x83: // addl a, #8; addl r, #8
841 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
842 debug_only(has_disp32 = true); // has both kinds of operands!
843 tail_size = 1;
844 break;
845
846 case 0x9B:
847 switch (0xFF & *ip++) {
848 case 0xD9: // fnstcw a
849 debug_only(has_disp32 = true);
850 break;
851 default:
852 ShouldNotReachHere();
853 }
854 break;
855
856 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
857 case REP4(0x10): // adc...
858 case REP4(0x20): // and...
859 case REP4(0x30): // xor...
860 case REP4(0x08): // or...
861 case REP4(0x18): // sbb...
862 case REP4(0x28): // sub...
863 case 0xF7: // mull a
864 case 0x8D: // lea r, a
865 case 0x87: // xchg r, a
866 case REP4(0x38): // cmp...
867 case 0x85: // test r, a
868 debug_only(has_disp32 = true); // has both kinds of operands!
869 break;
870
871 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
872 case 0xC6: // movb a, #8
873 case 0x80: // cmpb a, #8
874 case 0x6B: // imul r, a, #8
875 debug_only(has_disp32 = true); // has both kinds of operands!
876 tail_size = 1; // the imm8
877 break;
878
879 case 0xC4: // VEX_3bytes
880 case 0xC5: // VEX_2bytes
881 assert((UseAVX > 0), "shouldn't have VEX prefix");
882 assert(ip == inst+1, "no prefixes allowed");
883 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
884 // but they have prefix 0x0F and processed when 0x0F processed above.
885 //
886 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
887 // instructions (these instructions are not supported in 64-bit mode).
888 // To distinguish them bits [7:6] are set in the VEX second byte since
889 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
890 // those VEX bits REX and vvvv bits are inverted.
891 //
892 // Fortunately C2 doesn't generate these instructions so we don't need
893 // to check for them in product version.
894
895 // Check second byte
896 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
897
898 int vex_opcode;
899 // First byte
900 if ((0xFF & *inst) == VEX_3bytes) {
901 vex_opcode = VEX_OPCODE_MASK & *ip;
902 ip++; // third byte
903 is_64bit = ((VEX_W & *ip) == VEX_W);
904 } else {
905 vex_opcode = VEX_OPCODE_0F;
906 }
907 ip++; // opcode
908 // To find the end of instruction (which == end_pc_operand).
909 switch (vex_opcode) {
910 case VEX_OPCODE_0F:
911 switch (0xFF & *ip) {
912 case 0x70: // pshufd r, r/a, #8
913 case 0x71: // ps[rl|ra|ll]w r, #8
914 case 0x72: // ps[rl|ra|ll]d r, #8
915 case 0x73: // ps[rl|ra|ll]q r, #8
916 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
917 case 0xC4: // pinsrw r, r, r/a, #8
918 case 0xC5: // pextrw r/a, r, #8
919 case 0xC6: // shufp[s|d] r, r, r/a, #8
920 tail_size = 1; // the imm8
921 break;
922 }
923 break;
924 case VEX_OPCODE_0F_3A:
925 tail_size = 1;
926 break;
927 }
928 ip++; // skip opcode
929 debug_only(has_disp32 = true); // has both kinds of operands!
930 break;
931
932 case 0x62: // EVEX_4bytes
933 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
934 assert(ip == inst+1, "no prefixes allowed");
935 // no EVEX collisions, all instructions that have 0x62 opcodes
936 // have EVEX versions and are subopcodes of 0x66
937 ip++; // skip P0 and exmaine W in P1
938 is_64bit = ((VEX_W & *ip) == VEX_W);
939 ip++; // move to P2
940 ip++; // skip P2, move to opcode
941 // To find the end of instruction (which == end_pc_operand).
942 switch (0xFF & *ip) {
943 case 0x22: // pinsrd r, r/a, #8
944 case 0x61: // pcmpestri r, r/a, #8
945 case 0x70: // pshufd r, r/a, #8
946 case 0x73: // psrldq r, #8
947 tail_size = 1; // the imm8
948 break;
949 default:
950 break;
951 }
952 ip++; // skip opcode
953 debug_only(has_disp32 = true); // has both kinds of operands!
954 break;
955
956 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
957 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
958 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
959 case 0xDD: // fld_d a; fst_d a; fstp_d a
960 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
961 case 0xDF: // fild_d a; fistp_d a
962 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
963 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
964 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
965 debug_only(has_disp32 = true);
966 break;
967
968 case 0xE8: // call rdisp32
969 case 0xE9: // jmp rdisp32
970 if (which == end_pc_operand) return ip + 4;
971 assert(which == call32_operand, "call has no disp32 or imm");
972 return ip;
973
974 case 0xF0: // Lock
975 goto again_after_prefix;
976
977 case 0xF3: // For SSE
978 case 0xF2: // For SSE2
979 switch (0xFF & *ip++) {
980 case REX:
981 case REX_B:
982 case REX_X:
983 case REX_XB:
984 case REX_R:
985 case REX_RB:
986 case REX_RX:
987 case REX_RXB:
988 case REX_W:
989 case REX_WB:
990 case REX_WX:
991 case REX_WXB:
992 case REX_WR:
993 case REX_WRB:
994 case REX_WRX:
995 case REX_WRXB:
996 NOT_LP64(assert(false, "found 64bit prefix"));
997 ip++;
998 default:
999 ip++;
1000 }
1001 debug_only(has_disp32 = true); // has both kinds of operands!
1002 break;
1003
1004 default:
1005 ShouldNotReachHere();
1006
1007 #undef REP8
1008 #undef REP16
1009 }
1010
1011 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1012 #ifdef _LP64
1013 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1014 #else
1015 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1016 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1017 #endif // LP64
1018 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1019
1020 // parse the output of emit_operand
1021 int op2 = 0xFF & *ip++;
1022 int base = op2 & 0x07;
1023 int op3 = -1;
1024 const int b100 = 4;
1025 const int b101 = 5;
1026 if (base == b100 && (op2 >> 6) != 3) {
1027 op3 = 0xFF & *ip++;
1028 base = op3 & 0x07; // refetch the base
1029 }
1030 // now ip points at the disp (if any)
1031
1032 switch (op2 >> 6) {
1033 case 0:
1034 // [00 reg 100][ss index base]
1035 // [00 reg 100][00 100 esp]
1036 // [00 reg base]
1037 // [00 reg 100][ss index 101][disp32]
1038 // [00 reg 101] [disp32]
1039
1040 if (base == b101) {
1041 if (which == disp32_operand)
1042 return ip; // caller wants the disp32
1043 ip += 4; // skip the disp32
1044 }
1045 break;
1046
1047 case 1:
1048 // [01 reg 100][ss index base][disp8]
1049 // [01 reg 100][00 100 esp][disp8]
1050 // [01 reg base] [disp8]
1051 ip += 1; // skip the disp8
1052 break;
1053
1054 case 2:
1055 // [10 reg 100][ss index base][disp32]
1056 // [10 reg 100][00 100 esp][disp32]
1057 // [10 reg base] [disp32]
1058 if (which == disp32_operand)
1059 return ip; // caller wants the disp32
1060 ip += 4; // skip the disp32
1061 break;
1062
1063 case 3:
1064 // [11 reg base] (not a memory addressing mode)
1065 break;
1066 }
1067
1068 if (which == end_pc_operand) {
1069 return ip + tail_size;
1070 }
1071
1072 #ifdef _LP64
1073 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1074 #else
1075 assert(which == imm_operand, "instruction has only an imm field");
1076 #endif // LP64
1077 return ip;
1078 }
1079
1080 address Assembler::locate_next_instruction(address inst) {
1081 // Secretly share code with locate_operand:
1082 return locate_operand(inst, end_pc_operand);
1083 }
1084
1085
1086 #ifdef ASSERT
1087 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1088 address inst = inst_mark();
1089 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1090 address opnd;
1091
1092 Relocation* r = rspec.reloc();
1093 if (r->type() == relocInfo::none) {
1094 return;
1095 } else if (r->is_call() || format == call32_operand) {
1096 // assert(format == imm32_operand, "cannot specify a nonzero format");
1097 opnd = locate_operand(inst, call32_operand);
1098 } else if (r->is_data()) {
1099 assert(format == imm_operand || format == disp32_operand
1100 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1101 opnd = locate_operand(inst, (WhichOperand)format);
1102 } else {
1103 assert(format == imm_operand, "cannot specify a format");
1104 return;
1105 }
1106 assert(opnd == pc(), "must put operand where relocs can find it");
1107 }
1108 #endif // ASSERT
1109
1110 void Assembler::emit_operand32(Register reg, Address adr) {
1111 assert(reg->encoding() < 8, "no extended registers");
1112 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1114 adr._rspec);
1115 }
1116
1117 void Assembler::emit_operand(Register reg, Address adr,
1118 int rip_relative_correction) {
1119 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1120 adr._rspec,
1121 rip_relative_correction);
1122 }
1123
1124 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1125 if (adr.isxmmindex()) {
1126 emit_operand(reg, adr._base, adr._xmmindex, adr._scale, adr._disp, adr._rspec);
1127 } else {
1128 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1129 adr._rspec);
1130 }
1131 }
1132
1133 // MMX operations
1134 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1135 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1136 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1137 }
1138
1139 // work around gcc (3.2.1-7a) bug
1140 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1141 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1142 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1143 }
1144
1145
1146 void Assembler::emit_farith(int b1, int b2, int i) {
1147 assert(isByte(b1) && isByte(b2), "wrong opcode");
1148 assert(0 <= i && i < 8, "illegal stack offset");
1149 emit_int8(b1);
1150 emit_int8(b2 + i);
1151 }
1152
1153
1154 // Now the Assembler instructions (identical for 32/64 bits)
1155
1156 void Assembler::adcl(Address dst, int32_t imm32) {
1157 InstructionMark im(this);
1158 prefix(dst);
1159 emit_arith_operand(0x81, rdx, dst, imm32);
1160 }
1161
1162 void Assembler::adcl(Address dst, Register src) {
1163 InstructionMark im(this);
1164 prefix(dst, src);
1165 emit_int8(0x11);
1166 emit_operand(src, dst);
1167 }
1168
1169 void Assembler::adcl(Register dst, int32_t imm32) {
1170 prefix(dst);
1171 emit_arith(0x81, 0xD0, dst, imm32);
1172 }
1173
1174 void Assembler::adcl(Register dst, Address src) {
1175 InstructionMark im(this);
1176 prefix(src, dst);
1177 emit_int8(0x13);
1178 emit_operand(dst, src);
1179 }
1180
1181 void Assembler::adcl(Register dst, Register src) {
1182 (void) prefix_and_encode(dst->encoding(), src->encoding());
1183 emit_arith(0x13, 0xC0, dst, src);
1184 }
1185
1186 void Assembler::addl(Address dst, int32_t imm32) {
1187 InstructionMark im(this);
1188 prefix(dst);
1189 emit_arith_operand(0x81, rax, dst, imm32);
1190 }
1191
1192 void Assembler::addb(Address dst, int imm8) {
1193 InstructionMark im(this);
1194 prefix(dst);
1195 emit_int8((unsigned char)0x80);
1196 emit_operand(rax, dst, 1);
1197 emit_int8(imm8);
1198 }
1199
1200 void Assembler::addw(Address dst, int imm16) {
1201 InstructionMark im(this);
1202 emit_int8(0x66);
1203 prefix(dst);
1204 emit_int8((unsigned char)0x81);
1205 emit_operand(rax, dst, 2);
1206 emit_int16(imm16);
1207 }
1208
1209 void Assembler::addl(Address dst, Register src) {
1210 InstructionMark im(this);
1211 prefix(dst, src);
1212 emit_int8(0x01);
1213 emit_operand(src, dst);
1214 }
1215
1216 void Assembler::addl(Register dst, int32_t imm32) {
1217 prefix(dst);
1218 emit_arith(0x81, 0xC0, dst, imm32);
1219 }
1220
1221 void Assembler::addl(Register dst, Address src) {
1222 InstructionMark im(this);
1223 prefix(src, dst);
1224 emit_int8(0x03);
1225 emit_operand(dst, src);
1226 }
1227
1228 void Assembler::addl(Register dst, Register src) {
1229 (void) prefix_and_encode(dst->encoding(), src->encoding());
1230 emit_arith(0x03, 0xC0, dst, src);
1231 }
1232
1233 void Assembler::addr_nop_4() {
1234 assert(UseAddressNop, "no CPU support");
1235 // 4 bytes: NOP DWORD PTR [EAX+0]
1236 emit_int8(0x0F);
1237 emit_int8(0x1F);
1238 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1239 emit_int8(0); // 8-bits offset (1 byte)
1240 }
1241
1242 void Assembler::addr_nop_5() {
1243 assert(UseAddressNop, "no CPU support");
1244 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1245 emit_int8(0x0F);
1246 emit_int8(0x1F);
1247 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1248 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1249 emit_int8(0); // 8-bits offset (1 byte)
1250 }
1251
1252 void Assembler::addr_nop_7() {
1253 assert(UseAddressNop, "no CPU support");
1254 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1255 emit_int8(0x0F);
1256 emit_int8(0x1F);
1257 emit_int8((unsigned char)0x80);
1258 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1259 emit_int32(0); // 32-bits offset (4 bytes)
1260 }
1261
1262 void Assembler::addr_nop_8() {
1263 assert(UseAddressNop, "no CPU support");
1264 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1265 emit_int8(0x0F);
1266 emit_int8(0x1F);
1267 emit_int8((unsigned char)0x84);
1268 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1269 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1270 emit_int32(0); // 32-bits offset (4 bytes)
1271 }
1272
1273 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1274 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1275 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1276 attributes.set_rex_vex_w_reverted();
1277 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1278 emit_int8(0x58);
1279 emit_int8((unsigned char)(0xC0 | encode));
1280 }
1281
1282 void Assembler::addsd(XMMRegister dst, Address src) {
1283 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1284 InstructionMark im(this);
1285 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1286 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1287 attributes.set_rex_vex_w_reverted();
1288 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1289 emit_int8(0x58);
1290 emit_operand(dst, src);
1291 }
1292
1293 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1294 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1295 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1296 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1297 emit_int8(0x58);
1298 emit_int8((unsigned char)(0xC0 | encode));
1299 }
1300
1301 void Assembler::addss(XMMRegister dst, Address src) {
1302 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1303 InstructionMark im(this);
1304 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1305 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1306 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1307 emit_int8(0x58);
1308 emit_operand(dst, src);
1309 }
1310
1311 void Assembler::aesdec(XMMRegister dst, Address src) {
1312 assert(VM_Version::supports_aes(), "");
1313 InstructionMark im(this);
1314 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1315 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1316 emit_int8((unsigned char)0xDE);
1317 emit_operand(dst, src);
1318 }
1319
1320 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1321 assert(VM_Version::supports_aes(), "");
1322 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1323 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1324 emit_int8((unsigned char)0xDE);
1325 emit_int8(0xC0 | encode);
1326 }
1327
1328 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1329 assert(VM_Version::supports_vaes(), "");
1330 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1331 attributes.set_is_evex_instruction();
1332 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1333 emit_int8((unsigned char)0xDE);
1334 emit_int8((unsigned char)(0xC0 | encode));
1335 }
1336
1337
1338 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1339 assert(VM_Version::supports_aes(), "");
1340 InstructionMark im(this);
1341 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1342 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1343 emit_int8((unsigned char)0xDF);
1344 emit_operand(dst, src);
1345 }
1346
1347 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1348 assert(VM_Version::supports_aes(), "");
1349 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1350 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1351 emit_int8((unsigned char)0xDF);
1352 emit_int8((unsigned char)(0xC0 | encode));
1353 }
1354
1355 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1356 assert(VM_Version::supports_vaes(), "");
1357 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1358 attributes.set_is_evex_instruction();
1359 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1360 emit_int8((unsigned char)0xDF);
1361 emit_int8((unsigned char)(0xC0 | encode));
1362 }
1363
1364 void Assembler::aesenc(XMMRegister dst, Address src) {
1365 assert(VM_Version::supports_aes(), "");
1366 InstructionMark im(this);
1367 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1368 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1369 emit_int8((unsigned char)0xDC);
1370 emit_operand(dst, src);
1371 }
1372
1373 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1374 assert(VM_Version::supports_aes(), "");
1375 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1376 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1377 emit_int8((unsigned char)0xDC);
1378 emit_int8(0xC0 | encode);
1379 }
1380
1381 void Assembler::aesenclast(XMMRegister dst, Address src) {
1382 assert(VM_Version::supports_aes(), "");
1383 InstructionMark im(this);
1384 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1385 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1386 emit_int8((unsigned char)0xDD);
1387 emit_operand(dst, src);
1388 }
1389
1390 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1391 assert(VM_Version::supports_aes(), "");
1392 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1393 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1394 emit_int8((unsigned char)0xDD);
1395 emit_int8((unsigned char)(0xC0 | encode));
1396 }
1397
1398 void Assembler::andl(Address dst, int32_t imm32) {
1399 InstructionMark im(this);
1400 prefix(dst);
1401 emit_int8((unsigned char)0x81);
1402 emit_operand(rsp, dst, 4);
1403 emit_int32(imm32);
1404 }
1405
1406 void Assembler::andl(Register dst, int32_t imm32) {
1407 prefix(dst);
1408 emit_arith(0x81, 0xE0, dst, imm32);
1409 }
1410
1411 void Assembler::andl(Register dst, Address src) {
1412 InstructionMark im(this);
1413 prefix(src, dst);
1414 emit_int8(0x23);
1415 emit_operand(dst, src);
1416 }
1417
1418 void Assembler::andl(Register dst, Register src) {
1419 (void) prefix_and_encode(dst->encoding(), src->encoding());
1420 emit_arith(0x23, 0xC0, dst, src);
1421 }
1422
1423 void Assembler::andnl(Register dst, Register src1, Register src2) {
1424 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1425 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1426 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1427 emit_int8((unsigned char)0xF2);
1428 emit_int8((unsigned char)(0xC0 | encode));
1429 }
1430
1431 void Assembler::andnl(Register dst, Register src1, Address src2) {
1432 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1433 InstructionMark im(this);
1434 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1435 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1436 emit_int8((unsigned char)0xF2);
1437 emit_operand(dst, src2);
1438 }
1439
1440 void Assembler::bsfl(Register dst, Register src) {
1441 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1442 emit_int8(0x0F);
1443 emit_int8((unsigned char)0xBC);
1444 emit_int8((unsigned char)(0xC0 | encode));
1445 }
1446
1447 void Assembler::bsrl(Register dst, Register src) {
1448 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1449 emit_int8(0x0F);
1450 emit_int8((unsigned char)0xBD);
1451 emit_int8((unsigned char)(0xC0 | encode));
1452 }
1453
1454 void Assembler::bswapl(Register reg) { // bswap
1455 int encode = prefix_and_encode(reg->encoding());
1456 emit_int8(0x0F);
1457 emit_int8((unsigned char)(0xC8 | encode));
1458 }
1459
1460 void Assembler::blsil(Register dst, Register src) {
1461 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1462 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1463 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1464 emit_int8((unsigned char)0xF3);
1465 emit_int8((unsigned char)(0xC0 | encode));
1466 }
1467
1468 void Assembler::blsil(Register dst, Address src) {
1469 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1470 InstructionMark im(this);
1471 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1472 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1473 emit_int8((unsigned char)0xF3);
1474 emit_operand(rbx, src);
1475 }
1476
1477 void Assembler::blsmskl(Register dst, Register src) {
1478 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1479 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1480 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1481 emit_int8((unsigned char)0xF3);
1482 emit_int8((unsigned char)(0xC0 | encode));
1483 }
1484
1485 void Assembler::blsmskl(Register dst, Address src) {
1486 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1487 InstructionMark im(this);
1488 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1489 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1490 emit_int8((unsigned char)0xF3);
1491 emit_operand(rdx, src);
1492 }
1493
1494 void Assembler::blsrl(Register dst, Register src) {
1495 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1496 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1497 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1498 emit_int8((unsigned char)0xF3);
1499 emit_int8((unsigned char)(0xC0 | encode));
1500 }
1501
1502 void Assembler::blsrl(Register dst, Address src) {
1503 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1504 InstructionMark im(this);
1505 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1506 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1507 emit_int8((unsigned char)0xF3);
1508 emit_operand(rcx, src);
1509 }
1510
1511 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1512 // suspect disp32 is always good
1513 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1514
1515 if (L.is_bound()) {
1516 const int long_size = 5;
1517 int offs = (int)( target(L) - pc() );
1518 assert(offs <= 0, "assembler error");
1519 InstructionMark im(this);
1520 // 1110 1000 #32-bit disp
1521 emit_int8((unsigned char)0xE8);
1522 emit_data(offs - long_size, rtype, operand);
1523 } else {
1524 InstructionMark im(this);
1525 // 1110 1000 #32-bit disp
1526 L.add_patch_at(code(), locator());
1527
1528 emit_int8((unsigned char)0xE8);
1529 emit_data(int(0), rtype, operand);
1530 }
1531 }
1532
1533 void Assembler::call(Register dst) {
1534 int encode = prefix_and_encode(dst->encoding());
1535 emit_int8((unsigned char)0xFF);
1536 emit_int8((unsigned char)(0xD0 | encode));
1537 }
1538
1539
1540 void Assembler::call(Address adr) {
1541 InstructionMark im(this);
1542 prefix(adr);
1543 emit_int8((unsigned char)0xFF);
1544 emit_operand(rdx, adr);
1545 }
1546
1547 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1548 InstructionMark im(this);
1549 emit_int8((unsigned char)0xE8);
1550 intptr_t disp = entry - (pc() + sizeof(int32_t));
1551 // Entry is NULL in case of a scratch emit.
1552 assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
1553 // Technically, should use call32_operand, but this format is
1554 // implied by the fact that we're emitting a call instruction.
1555
1556 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1557 emit_data((int) disp, rspec, operand);
1558 }
1559
1560 void Assembler::cdql() {
1561 emit_int8((unsigned char)0x99);
1562 }
1563
1564 void Assembler::cld() {
1565 emit_int8((unsigned char)0xFC);
1566 }
1567
1568 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1569 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1570 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1571 emit_int8(0x0F);
1572 emit_int8(0x40 | cc);
1573 emit_int8((unsigned char)(0xC0 | encode));
1574 }
1575
1576
1577 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1578 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1579 prefix(src, dst);
1580 emit_int8(0x0F);
1581 emit_int8(0x40 | cc);
1582 emit_operand(dst, src);
1583 }
1584
1585 void Assembler::cmpb(Address dst, int imm8) {
1586 InstructionMark im(this);
1587 prefix(dst);
1588 emit_int8((unsigned char)0x80);
1589 emit_operand(rdi, dst, 1);
1590 emit_int8(imm8);
1591 }
1592
1593 void Assembler::cmpl(Address dst, int32_t imm32) {
1594 InstructionMark im(this);
1595 prefix(dst);
1596 emit_int8((unsigned char)0x81);
1597 emit_operand(rdi, dst, 4);
1598 emit_int32(imm32);
1599 }
1600
1601 void Assembler::cmpl(Register dst, int32_t imm32) {
1602 prefix(dst);
1603 emit_arith(0x81, 0xF8, dst, imm32);
1604 }
1605
1606 void Assembler::cmpl(Register dst, Register src) {
1607 (void) prefix_and_encode(dst->encoding(), src->encoding());
1608 emit_arith(0x3B, 0xC0, dst, src);
1609 }
1610
1611 void Assembler::cmpl(Register dst, Address src) {
1612 InstructionMark im(this);
1613 prefix(src, dst);
1614 emit_int8((unsigned char)0x3B);
1615 emit_operand(dst, src);
1616 }
1617
1618 void Assembler::cmpw(Address dst, int imm16) {
1619 InstructionMark im(this);
1620 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1621 emit_int8(0x66);
1622 emit_int8((unsigned char)0x81);
1623 emit_operand(rdi, dst, 2);
1624 emit_int16(imm16);
1625 }
1626
1627 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1628 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1629 // The ZF is set if the compared values were equal, and cleared otherwise.
1630 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1631 InstructionMark im(this);
1632 prefix(adr, reg);
1633 emit_int8(0x0F);
1634 emit_int8((unsigned char)0xB1);
1635 emit_operand(reg, adr);
1636 }
1637
1638 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1639 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1640 // The ZF is set if the compared values were equal, and cleared otherwise.
1641 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1642 InstructionMark im(this);
1643 prefix(adr, reg, true);
1644 emit_int8(0x0F);
1645 emit_int8((unsigned char)0xB0);
1646 emit_operand(reg, adr);
1647 }
1648
1649 void Assembler::comisd(XMMRegister dst, Address src) {
1650 // NOTE: dbx seems to decode this as comiss even though the
1651 // 0x66 is there. Strangly ucomisd comes out correct
1652 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1653 InstructionMark im(this);
1654 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1655 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1656 attributes.set_rex_vex_w_reverted();
1657 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1658 emit_int8(0x2F);
1659 emit_operand(dst, src);
1660 }
1661
1662 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1663 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1664 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1665 attributes.set_rex_vex_w_reverted();
1666 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1667 emit_int8(0x2F);
1668 emit_int8((unsigned char)(0xC0 | encode));
1669 }
1670
1671 void Assembler::comiss(XMMRegister dst, Address src) {
1672 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1673 InstructionMark im(this);
1674 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1675 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1676 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1677 emit_int8(0x2F);
1678 emit_operand(dst, src);
1679 }
1680
1681 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1682 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1683 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1684 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1685 emit_int8(0x2F);
1686 emit_int8((unsigned char)(0xC0 | encode));
1687 }
1688
1689 void Assembler::cpuid() {
1690 emit_int8(0x0F);
1691 emit_int8((unsigned char)0xA2);
1692 }
1693
1694 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1695 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1696 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1697 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1698 //
1699 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1700 //
1701 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1702 //
1703 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1704 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1705 assert(VM_Version::supports_sse4_2(), "");
1706 int8_t w = 0x01;
1707 Prefix p = Prefix_EMPTY;
1708
1709 emit_int8((int8_t)0xF2);
1710 switch (sizeInBytes) {
1711 case 1:
1712 w = 0;
1713 break;
1714 case 2:
1715 case 4:
1716 break;
1717 LP64_ONLY(case 8:)
1718 // This instruction is not valid in 32 bits
1719 // Note:
1720 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1721 //
1722 // Page B - 72 Vol. 2C says
1723 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1724 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1725 // F0!!!
1726 // while 3 - 208 Vol. 2A
1727 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1728 //
1729 // the 0 on a last bit is reserved for a different flavor of this instruction :
1730 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1731 p = REX_W;
1732 break;
1733 default:
1734 assert(0, "Unsupported value for a sizeInBytes argument");
1735 break;
1736 }
1737 LP64_ONLY(prefix(crc, v, p);)
1738 emit_int8((int8_t)0x0F);
1739 emit_int8(0x38);
1740 emit_int8((int8_t)(0xF0 | w));
1741 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1742 }
1743
1744 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1745 assert(VM_Version::supports_sse4_2(), "");
1746 InstructionMark im(this);
1747 int8_t w = 0x01;
1748 Prefix p = Prefix_EMPTY;
1749
1750 emit_int8((int8_t)0xF2);
1751 switch (sizeInBytes) {
1752 case 1:
1753 w = 0;
1754 break;
1755 case 2:
1756 case 4:
1757 break;
1758 LP64_ONLY(case 8:)
1759 // This instruction is not valid in 32 bits
1760 p = REX_W;
1761 break;
1762 default:
1763 assert(0, "Unsupported value for a sizeInBytes argument");
1764 break;
1765 }
1766 LP64_ONLY(prefix(crc, adr, p);)
1767 emit_int8((int8_t)0x0F);
1768 emit_int8(0x38);
1769 emit_int8((int8_t)(0xF0 | w));
1770 emit_operand(crc, adr);
1771 }
1772
1773 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1774 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1775 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1776 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1777 emit_int8((unsigned char)0xE6);
1778 emit_int8((unsigned char)(0xC0 | encode));
1779 }
1780
1781 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1782 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1783 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1784 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1785 emit_int8(0x5B);
1786 emit_int8((unsigned char)(0xC0 | encode));
1787 }
1788
1789 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1790 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1791 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1792 attributes.set_rex_vex_w_reverted();
1793 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1794 emit_int8(0x5A);
1795 emit_int8((unsigned char)(0xC0 | encode));
1796 }
1797
1798 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1799 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1800 InstructionMark im(this);
1801 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1802 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1803 attributes.set_rex_vex_w_reverted();
1804 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1805 emit_int8(0x5A);
1806 emit_operand(dst, src);
1807 }
1808
1809 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1810 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1811 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1812 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1813 emit_int8(0x2A);
1814 emit_int8((unsigned char)(0xC0 | encode));
1815 }
1816
1817 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1818 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1819 InstructionMark im(this);
1820 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1821 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1822 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1823 emit_int8(0x2A);
1824 emit_operand(dst, src);
1825 }
1826
1827 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1828 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1829 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1830 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1831 emit_int8(0x2A);
1832 emit_int8((unsigned char)(0xC0 | encode));
1833 }
1834
1835 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1836 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1837 InstructionMark im(this);
1838 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1839 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1840 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1841 emit_int8(0x2A);
1842 emit_operand(dst, src);
1843 }
1844
1845 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1846 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1847 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1848 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1849 emit_int8(0x2A);
1850 emit_int8((unsigned char)(0xC0 | encode));
1851 }
1852
1853 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1854 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1855 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1856 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1857 emit_int8(0x5A);
1858 emit_int8((unsigned char)(0xC0 | encode));
1859 }
1860
1861 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1862 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1863 InstructionMark im(this);
1864 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1865 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1866 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1867 emit_int8(0x5A);
1868 emit_operand(dst, src);
1869 }
1870
1871
1872 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1873 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1874 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1875 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1876 emit_int8(0x2C);
1877 emit_int8((unsigned char)(0xC0 | encode));
1878 }
1879
1880 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1881 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1882 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1883 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1884 emit_int8(0x2C);
1885 emit_int8((unsigned char)(0xC0 | encode));
1886 }
1887
1888 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1889 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1890 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1891 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1892 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1893 emit_int8((unsigned char)0xE6);
1894 emit_int8((unsigned char)(0xC0 | encode));
1895 }
1896
1897 void Assembler::pabsb(XMMRegister dst, XMMRegister src) {
1898 assert(VM_Version::supports_ssse3(), "");
1899 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
1900 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1901 emit_int8(0x1C);
1902 emit_int8((unsigned char)(0xC0 | encode));
1903 }
1904
1905 void Assembler::pabsw(XMMRegister dst, XMMRegister src) {
1906 assert(VM_Version::supports_ssse3(), "");
1907 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
1908 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1909 emit_int8(0x1D);
1910 emit_int8((unsigned char)(0xC0 | encode));
1911 }
1912
1913 void Assembler::pabsd(XMMRegister dst, XMMRegister src) {
1914 assert(VM_Version::supports_ssse3(), "");
1915 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1916 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1917 emit_int8(0x1E);
1918 emit_int8((unsigned char)(0xC0 | encode));
1919 }
1920
1921 void Assembler::vpabsb(XMMRegister dst, XMMRegister src, int vector_len) {
1922 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
1923 vector_len == AVX_256bit? VM_Version::supports_avx2() :
1924 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
1925 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
1926 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1927 emit_int8((unsigned char)0x1C);
1928 emit_int8((unsigned char)(0xC0 | encode));
1929 }
1930
1931 void Assembler::vpabsw(XMMRegister dst, XMMRegister src, int vector_len) {
1932 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
1933 vector_len == AVX_256bit? VM_Version::supports_avx2() :
1934 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
1935 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
1936 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1937 emit_int8((unsigned char)0x1D);
1938 emit_int8((unsigned char)(0xC0 | encode));
1939 }
1940
1941 void Assembler::vpabsd(XMMRegister dst, XMMRegister src, int vector_len) {
1942 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
1943 vector_len == AVX_256bit? VM_Version::supports_avx2() :
1944 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, "");
1945 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1946 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1947 emit_int8((unsigned char)0x1E);
1948 emit_int8((unsigned char)(0xC0 | encode));
1949 }
1950
1951 void Assembler::evpabsq(XMMRegister dst, XMMRegister src, int vector_len) {
1952 assert(UseAVX > 2, "");
1953 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1954 attributes.set_is_evex_instruction();
1955 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1956 emit_int8((unsigned char)0x1F);
1957 emit_int8((unsigned char)(0xC0 | encode));
1958 }
1959
1960 void Assembler::decl(Address dst) {
1961 // Don't use it directly. Use MacroAssembler::decrement() instead.
1962 InstructionMark im(this);
1963 prefix(dst);
1964 emit_int8((unsigned char)0xFF);
1965 emit_operand(rcx, dst);
1966 }
1967
1968 void Assembler::divsd(XMMRegister dst, Address src) {
1969 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1970 InstructionMark im(this);
1971 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1972 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1973 attributes.set_rex_vex_w_reverted();
1974 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1975 emit_int8(0x5E);
1976 emit_operand(dst, src);
1977 }
1978
1979 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1980 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1981 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1982 attributes.set_rex_vex_w_reverted();
1983 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1984 emit_int8(0x5E);
1985 emit_int8((unsigned char)(0xC0 | encode));
1986 }
1987
1988 void Assembler::divss(XMMRegister dst, Address src) {
1989 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1990 InstructionMark im(this);
1991 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1992 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1993 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1994 emit_int8(0x5E);
1995 emit_operand(dst, src);
1996 }
1997
1998 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1999 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2000 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2001 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2002 emit_int8(0x5E);
2003 emit_int8((unsigned char)(0xC0 | encode));
2004 }
2005
2006 void Assembler::emms() {
2007 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
2008 emit_int8(0x0F);
2009 emit_int8(0x77);
2010 }
2011
2012 void Assembler::hlt() {
2013 emit_int8((unsigned char)0xF4);
2014 }
2015
2016 void Assembler::idivl(Register src) {
2017 int encode = prefix_and_encode(src->encoding());
2018 emit_int8((unsigned char)0xF7);
2019 emit_int8((unsigned char)(0xF8 | encode));
2020 }
2021
2022 void Assembler::divl(Register src) { // Unsigned
2023 int encode = prefix_and_encode(src->encoding());
2024 emit_int8((unsigned char)0xF7);
2025 emit_int8((unsigned char)(0xF0 | encode));
2026 }
2027
2028 void Assembler::imull(Register src) {
2029 int encode = prefix_and_encode(src->encoding());
2030 emit_int8((unsigned char)0xF7);
2031 emit_int8((unsigned char)(0xE8 | encode));
2032 }
2033
2034 void Assembler::imull(Register dst, Register src) {
2035 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2036 emit_int8(0x0F);
2037 emit_int8((unsigned char)0xAF);
2038 emit_int8((unsigned char)(0xC0 | encode));
2039 }
2040
2041
2042 void Assembler::imull(Register dst, Register src, int value) {
2043 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2044 if (is8bit(value)) {
2045 emit_int8(0x6B);
2046 emit_int8((unsigned char)(0xC0 | encode));
2047 emit_int8(value & 0xFF);
2048 } else {
2049 emit_int8(0x69);
2050 emit_int8((unsigned char)(0xC0 | encode));
2051 emit_int32(value);
2052 }
2053 }
2054
2055 void Assembler::imull(Register dst, Address src) {
2056 InstructionMark im(this);
2057 prefix(src, dst);
2058 emit_int8(0x0F);
2059 emit_int8((unsigned char) 0xAF);
2060 emit_operand(dst, src);
2061 }
2062
2063
2064 void Assembler::incl(Address dst) {
2065 // Don't use it directly. Use MacroAssembler::increment() instead.
2066 InstructionMark im(this);
2067 prefix(dst);
2068 emit_int8((unsigned char)0xFF);
2069 emit_operand(rax, dst);
2070 }
2071
2072 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
2073 InstructionMark im(this);
2074 assert((0 <= cc) && (cc < 16), "illegal cc");
2075 if (L.is_bound()) {
2076 address dst = target(L);
2077 assert(dst != NULL, "jcc most probably wrong");
2078
2079 const int short_size = 2;
2080 const int long_size = 6;
2081 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
2082 if (maybe_short && is8bit(offs - short_size)) {
2083 // 0111 tttn #8-bit disp
2084 emit_int8(0x70 | cc);
2085 emit_int8((offs - short_size) & 0xFF);
2086 } else {
2087 // 0000 1111 1000 tttn #32-bit disp
2088 assert(is_simm32(offs - long_size),
2089 "must be 32bit offset (call4)");
2090 emit_int8(0x0F);
2091 emit_int8((unsigned char)(0x80 | cc));
2092 emit_int32(offs - long_size);
2093 }
2094 } else {
2095 // Note: could eliminate cond. jumps to this jump if condition
2096 // is the same however, seems to be rather unlikely case.
2097 // Note: use jccb() if label to be bound is very close to get
2098 // an 8-bit displacement
2099 L.add_patch_at(code(), locator());
2100 emit_int8(0x0F);
2101 emit_int8((unsigned char)(0x80 | cc));
2102 emit_int32(0);
2103 }
2104 }
2105
2106 void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) {
2107 if (L.is_bound()) {
2108 const int short_size = 2;
2109 address entry = target(L);
2110 #ifdef ASSERT
2111 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2112 intptr_t delta = short_branch_delta();
2113 if (delta != 0) {
2114 dist += (dist < 0 ? (-delta) :delta);
2115 }
2116 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2117 #endif
2118 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2119 // 0111 tttn #8-bit disp
2120 emit_int8(0x70 | cc);
2121 emit_int8((offs - short_size) & 0xFF);
2122 } else {
2123 InstructionMark im(this);
2124 L.add_patch_at(code(), locator(), file, line);
2125 emit_int8(0x70 | cc);
2126 emit_int8(0);
2127 }
2128 }
2129
2130 void Assembler::jmp(Address adr) {
2131 InstructionMark im(this);
2132 prefix(adr);
2133 emit_int8((unsigned char)0xFF);
2134 emit_operand(rsp, adr);
2135 }
2136
2137 void Assembler::jmp(Label& L, bool maybe_short) {
2138 if (L.is_bound()) {
2139 address entry = target(L);
2140 assert(entry != NULL, "jmp most probably wrong");
2141 InstructionMark im(this);
2142 const int short_size = 2;
2143 const int long_size = 5;
2144 intptr_t offs = entry - pc();
2145 if (maybe_short && is8bit(offs - short_size)) {
2146 emit_int8((unsigned char)0xEB);
2147 emit_int8((offs - short_size) & 0xFF);
2148 } else {
2149 emit_int8((unsigned char)0xE9);
2150 emit_int32(offs - long_size);
2151 }
2152 } else {
2153 // By default, forward jumps are always 32-bit displacements, since
2154 // we can't yet know where the label will be bound. If you're sure that
2155 // the forward jump will not run beyond 256 bytes, use jmpb to
2156 // force an 8-bit displacement.
2157 InstructionMark im(this);
2158 L.add_patch_at(code(), locator());
2159 emit_int8((unsigned char)0xE9);
2160 emit_int32(0);
2161 }
2162 }
2163
2164 void Assembler::jmp(Register entry) {
2165 int encode = prefix_and_encode(entry->encoding());
2166 emit_int8((unsigned char)0xFF);
2167 emit_int8((unsigned char)(0xE0 | encode));
2168 }
2169
2170 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2171 InstructionMark im(this);
2172 emit_int8((unsigned char)0xE9);
2173 assert(dest != NULL, "must have a target");
2174 intptr_t disp = dest - (pc() + sizeof(int32_t));
2175 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2176 emit_data(disp, rspec.reloc(), call32_operand);
2177 }
2178
2179 void Assembler::jmpb_0(Label& L, const char* file, int line) {
2180 if (L.is_bound()) {
2181 const int short_size = 2;
2182 address entry = target(L);
2183 assert(entry != NULL, "jmp most probably wrong");
2184 #ifdef ASSERT
2185 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2186 intptr_t delta = short_branch_delta();
2187 if (delta != 0) {
2188 dist += (dist < 0 ? (-delta) :delta);
2189 }
2190 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2191 #endif
2192 intptr_t offs = entry - pc();
2193 emit_int8((unsigned char)0xEB);
2194 emit_int8((offs - short_size) & 0xFF);
2195 } else {
2196 InstructionMark im(this);
2197 L.add_patch_at(code(), locator(), file, line);
2198 emit_int8((unsigned char)0xEB);
2199 emit_int8(0);
2200 }
2201 }
2202
2203 void Assembler::ldmxcsr( Address src) {
2204 if (UseAVX > 0 ) {
2205 InstructionMark im(this);
2206 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2207 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2208 emit_int8((unsigned char)0xAE);
2209 emit_operand(as_Register(2), src);
2210 } else {
2211 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2212 InstructionMark im(this);
2213 prefix(src);
2214 emit_int8(0x0F);
2215 emit_int8((unsigned char)0xAE);
2216 emit_operand(as_Register(2), src);
2217 }
2218 }
2219
2220 void Assembler::leal(Register dst, Address src) {
2221 InstructionMark im(this);
2222 #ifdef _LP64
2223 emit_int8(0x67); // addr32
2224 prefix(src, dst);
2225 #endif // LP64
2226 emit_int8((unsigned char)0x8D);
2227 emit_operand(dst, src);
2228 }
2229
2230 void Assembler::lfence() {
2231 emit_int8(0x0F);
2232 emit_int8((unsigned char)0xAE);
2233 emit_int8((unsigned char)0xE8);
2234 }
2235
2236 void Assembler::lock() {
2237 emit_int8((unsigned char)0xF0);
2238 }
2239
2240 void Assembler::lzcntl(Register dst, Register src) {
2241 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2242 emit_int8((unsigned char)0xF3);
2243 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2244 emit_int8(0x0F);
2245 emit_int8((unsigned char)0xBD);
2246 emit_int8((unsigned char)(0xC0 | encode));
2247 }
2248
2249 // Emit mfence instruction
2250 void Assembler::mfence() {
2251 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2252 emit_int8(0x0F);
2253 emit_int8((unsigned char)0xAE);
2254 emit_int8((unsigned char)0xF0);
2255 }
2256
2257 void Assembler::mov(Register dst, Register src) {
2258 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2259 }
2260
2261 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2262 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2263 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2264 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2265 attributes.set_rex_vex_w_reverted();
2266 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2267 emit_int8(0x28);
2268 emit_int8((unsigned char)(0xC0 | encode));
2269 }
2270
2271 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2272 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2273 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2274 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2275 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2276 emit_int8(0x28);
2277 emit_int8((unsigned char)(0xC0 | encode));
2278 }
2279
2280 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2281 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2282 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2283 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2284 emit_int8(0x16);
2285 emit_int8((unsigned char)(0xC0 | encode));
2286 }
2287
2288 void Assembler::movb(Register dst, Address src) {
2289 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2290 InstructionMark im(this);
2291 prefix(src, dst, true);
2292 emit_int8((unsigned char)0x8A);
2293 emit_operand(dst, src);
2294 }
2295
2296 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2297 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2298 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2299 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2300 attributes.set_rex_vex_w_reverted();
2301 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2302 emit_int8(0x12);
2303 emit_int8(0xC0 | encode);
2304 }
2305
2306 void Assembler::kmovbl(KRegister dst, Register src) {
2307 assert(VM_Version::supports_avx512dq(), "");
2308 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2309 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2310 emit_int8((unsigned char)0x92);
2311 emit_int8((unsigned char)(0xC0 | encode));
2312 }
2313
2314 void Assembler::kmovbl(Register dst, KRegister src) {
2315 assert(VM_Version::supports_avx512dq(), "");
2316 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2317 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2318 emit_int8((unsigned char)0x93);
2319 emit_int8((unsigned char)(0xC0 | encode));
2320 }
2321
2322 void Assembler::kmovwl(KRegister dst, Register src) {
2323 assert(VM_Version::supports_evex(), "");
2324 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2325 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2326 emit_int8((unsigned char)0x92);
2327 emit_int8((unsigned char)(0xC0 | encode));
2328 }
2329
2330 void Assembler::kmovwl(Register dst, KRegister src) {
2331 assert(VM_Version::supports_evex(), "");
2332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2333 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2334 emit_int8((unsigned char)0x93);
2335 emit_int8((unsigned char)(0xC0 | encode));
2336 }
2337
2338 void Assembler::kmovwl(KRegister dst, Address src) {
2339 assert(VM_Version::supports_evex(), "");
2340 InstructionMark im(this);
2341 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2342 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2343 emit_int8((unsigned char)0x90);
2344 emit_operand((Register)dst, src);
2345 }
2346
2347 void Assembler::kmovdl(KRegister dst, Register src) {
2348 assert(VM_Version::supports_avx512bw(), "");
2349 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2350 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2351 emit_int8((unsigned char)0x92);
2352 emit_int8((unsigned char)(0xC0 | encode));
2353 }
2354
2355 void Assembler::kmovdl(Register dst, KRegister src) {
2356 assert(VM_Version::supports_avx512bw(), "");
2357 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2358 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2359 emit_int8((unsigned char)0x93);
2360 emit_int8((unsigned char)(0xC0 | encode));
2361 }
2362
2363 void Assembler::kmovql(KRegister dst, KRegister src) {
2364 assert(VM_Version::supports_avx512bw(), "");
2365 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2366 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2367 emit_int8((unsigned char)0x90);
2368 emit_int8((unsigned char)(0xC0 | encode));
2369 }
2370
2371 void Assembler::kmovql(KRegister dst, Address src) {
2372 assert(VM_Version::supports_avx512bw(), "");
2373 InstructionMark im(this);
2374 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2375 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2376 emit_int8((unsigned char)0x90);
2377 emit_operand((Register)dst, src);
2378 }
2379
2380 void Assembler::kmovql(Address dst, KRegister src) {
2381 assert(VM_Version::supports_avx512bw(), "");
2382 InstructionMark im(this);
2383 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2384 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2385 emit_int8((unsigned char)0x90);
2386 emit_operand((Register)src, dst);
2387 }
2388
2389 void Assembler::kmovql(KRegister dst, Register src) {
2390 assert(VM_Version::supports_avx512bw(), "");
2391 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2392 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2393 emit_int8((unsigned char)0x92);
2394 emit_int8((unsigned char)(0xC0 | encode));
2395 }
2396
2397 void Assembler::kmovql(Register dst, KRegister src) {
2398 assert(VM_Version::supports_avx512bw(), "");
2399 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2400 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2401 emit_int8((unsigned char)0x93);
2402 emit_int8((unsigned char)(0xC0 | encode));
2403 }
2404
2405 void Assembler::knotwl(KRegister dst, KRegister src) {
2406 assert(VM_Version::supports_evex(), "");
2407 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2408 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2409 emit_int8((unsigned char)0x44);
2410 emit_int8((unsigned char)(0xC0 | encode));
2411 }
2412
2413 // This instruction produces ZF or CF flags
2414 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2415 assert(VM_Version::supports_avx512dq(), "");
2416 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2417 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2418 emit_int8((unsigned char)0x98);
2419 emit_int8((unsigned char)(0xC0 | encode));
2420 }
2421
2422 // This instruction produces ZF or CF flags
2423 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2424 assert(VM_Version::supports_evex(), "");
2425 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2426 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2427 emit_int8((unsigned char)0x98);
2428 emit_int8((unsigned char)(0xC0 | encode));
2429 }
2430
2431 // This instruction produces ZF or CF flags
2432 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2433 assert(VM_Version::supports_avx512bw(), "");
2434 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2435 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2436 emit_int8((unsigned char)0x98);
2437 emit_int8((unsigned char)(0xC0 | encode));
2438 }
2439
2440 // This instruction produces ZF or CF flags
2441 void Assembler::kortestql(KRegister src1, KRegister src2) {
2442 assert(VM_Version::supports_avx512bw(), "");
2443 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2444 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2445 emit_int8((unsigned char)0x98);
2446 emit_int8((unsigned char)(0xC0 | encode));
2447 }
2448
2449 // This instruction produces ZF or CF flags
2450 void Assembler::ktestql(KRegister src1, KRegister src2) {
2451 assert(VM_Version::supports_avx512bw(), "");
2452 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2453 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2454 emit_int8((unsigned char)0x99);
2455 emit_int8((unsigned char)(0xC0 | encode));
2456 }
2457
2458 void Assembler::ktestq(KRegister src1, KRegister src2) {
2459 assert(VM_Version::supports_avx512bw(), "");
2460 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2461 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2462 emit_int8((unsigned char)0x99);
2463 emit_int8((unsigned char)(0xC0 | encode));
2464 }
2465
2466 void Assembler::ktestd(KRegister src1, KRegister src2) {
2467 assert(VM_Version::supports_avx512bw(), "");
2468 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2469 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2470 emit_int8((unsigned char)0x99);
2471 emit_int8((unsigned char)(0xC0 | encode));
2472 }
2473
2474 void Assembler::movb(Address dst, int imm8) {
2475 InstructionMark im(this);
2476 prefix(dst);
2477 emit_int8((unsigned char)0xC6);
2478 emit_operand(rax, dst, 1);
2479 emit_int8(imm8);
2480 }
2481
2482
2483 void Assembler::movb(Address dst, Register src) {
2484 assert(src->has_byte_register(), "must have byte register");
2485 InstructionMark im(this);
2486 prefix(dst, src, true);
2487 emit_int8((unsigned char)0x88);
2488 emit_operand(src, dst);
2489 }
2490
2491 void Assembler::movdl(XMMRegister dst, Register src) {
2492 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2493 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2494 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2495 emit_int8(0x6E);
2496 emit_int8((unsigned char)(0xC0 | encode));
2497 }
2498
2499 void Assembler::movdl(Register dst, XMMRegister src) {
2500 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2501 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2502 // swap src/dst to get correct prefix
2503 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2504 emit_int8(0x7E);
2505 emit_int8((unsigned char)(0xC0 | encode));
2506 }
2507
2508 void Assembler::movdl(XMMRegister dst, Address src) {
2509 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2510 InstructionMark im(this);
2511 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2512 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2513 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2514 emit_int8(0x6E);
2515 emit_operand(dst, src);
2516 }
2517
2518 void Assembler::movdl(Address dst, XMMRegister src) {
2519 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2520 InstructionMark im(this);
2521 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2522 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2523 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2524 emit_int8(0x7E);
2525 emit_operand(src, dst);
2526 }
2527
2528 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2529 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2530 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2531 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2532 emit_int8(0x6F);
2533 emit_int8((unsigned char)(0xC0 | encode));
2534 }
2535
2536 void Assembler::movdqa(XMMRegister dst, Address src) {
2537 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2538 InstructionMark im(this);
2539 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2540 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2541 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2542 emit_int8(0x6F);
2543 emit_operand(dst, src);
2544 }
2545
2546 void Assembler::movdqu(XMMRegister dst, Address src) {
2547 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2548 InstructionMark im(this);
2549 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2550 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2551 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2552 emit_int8(0x6F);
2553 emit_operand(dst, src);
2554 }
2555
2556 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2557 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2558 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2559 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2560 emit_int8(0x6F);
2561 emit_int8((unsigned char)(0xC0 | encode));
2562 }
2563
2564 void Assembler::movdqu(Address dst, XMMRegister src) {
2565 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2566 InstructionMark im(this);
2567 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2568 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2569 attributes.reset_is_clear_context();
2570 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2571 emit_int8(0x7F);
2572 emit_operand(src, dst);
2573 }
2574
2575 // Move Unaligned 256bit Vector
2576 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2577 assert(UseAVX > 0, "");
2578 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2579 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2580 emit_int8(0x6F);
2581 emit_int8((unsigned char)(0xC0 | encode));
2582 }
2583
2584 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2585 assert(UseAVX > 0, "");
2586 InstructionMark im(this);
2587 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2588 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2589 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2590 emit_int8(0x6F);
2591 emit_operand(dst, src);
2592 }
2593
2594 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2595 assert(UseAVX > 0, "");
2596 InstructionMark im(this);
2597 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2598 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2599 attributes.reset_is_clear_context();
2600 // swap src<->dst for encoding
2601 assert(src != xnoreg, "sanity");
2602 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2603 emit_int8(0x7F);
2604 emit_operand(src, dst);
2605 }
2606
2607 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2608 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2609 assert(VM_Version::supports_evex(), "");
2610 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2611 attributes.set_is_evex_instruction();
2612 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2613 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2614 emit_int8(0x6F);
2615 emit_int8((unsigned char)(0xC0 | encode));
2616 }
2617
2618 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2619 assert(VM_Version::supports_evex(), "");
2620 InstructionMark im(this);
2621 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2622 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2623 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2624 attributes.set_is_evex_instruction();
2625 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2626 emit_int8(0x6F);
2627 emit_operand(dst, src);
2628 }
2629
2630 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2631 assert(VM_Version::supports_evex(), "");
2632 assert(src != xnoreg, "sanity");
2633 InstructionMark im(this);
2634 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2635 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2636 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2637 attributes.set_is_evex_instruction();
2638 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2639 emit_int8(0x7F);
2640 emit_operand(src, dst);
2641 }
2642
2643 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2644 assert(VM_Version::supports_avx512vlbw(), "");
2645 InstructionMark im(this);
2646 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2647 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2648 attributes.set_embedded_opmask_register_specifier(mask);
2649 attributes.set_is_evex_instruction();
2650 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2651 emit_int8(0x6F);
2652 emit_operand(dst, src);
2653 }
2654
2655 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2656 assert(VM_Version::supports_evex(), "");
2657 InstructionMark im(this);
2658 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2659 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2660 attributes.set_is_evex_instruction();
2661 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2662 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2663 emit_int8(0x6F);
2664 emit_operand(dst, src);
2665 }
2666
2667 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2668 assert(VM_Version::supports_avx512vlbw(), "");
2669 InstructionMark im(this);
2670 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2671 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2672 attributes.set_embedded_opmask_register_specifier(mask);
2673 attributes.set_is_evex_instruction();
2674 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2675 emit_int8(0x6F);
2676 emit_operand(dst, src);
2677 }
2678
2679 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2680 assert(VM_Version::supports_evex(), "");
2681 assert(src != xnoreg, "sanity");
2682 InstructionMark im(this);
2683 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2684 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2685 attributes.set_is_evex_instruction();
2686 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2687 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2688 emit_int8(0x7F);
2689 emit_operand(src, dst);
2690 }
2691
2692 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) {
2693 assert(VM_Version::supports_avx512vlbw(), "");
2694 assert(src != xnoreg, "sanity");
2695 InstructionMark im(this);
2696 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2697 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2698 attributes.reset_is_clear_context();
2699 attributes.set_embedded_opmask_register_specifier(mask);
2700 attributes.set_is_evex_instruction();
2701 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2702 emit_int8(0x7F);
2703 emit_operand(src, dst);
2704 }
2705
2706 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2707 assert(VM_Version::supports_evex(), "");
2708 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2709 attributes.set_is_evex_instruction();
2710 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2711 emit_int8(0x6F);
2712 emit_int8((unsigned char)(0xC0 | encode));
2713 }
2714
2715 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2716 assert(VM_Version::supports_evex(), "");
2717 InstructionMark im(this);
2718 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ true);
2719 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2720 attributes.set_is_evex_instruction();
2721 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2722 emit_int8(0x6F);
2723 emit_operand(dst, src);
2724 }
2725
2726 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2727 assert(VM_Version::supports_evex(), "");
2728 assert(src != xnoreg, "sanity");
2729 InstructionMark im(this);
2730 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2731 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2732 attributes.reset_is_clear_context();
2733 attributes.set_is_evex_instruction();
2734 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2735 emit_int8(0x7F);
2736 emit_operand(src, dst);
2737 }
2738
2739 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2740 assert(VM_Version::supports_evex(), "");
2741 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2742 attributes.set_is_evex_instruction();
2743 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2744 emit_int8(0x6F);
2745 emit_int8((unsigned char)(0xC0 | encode));
2746 }
2747
2748 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2749 assert(VM_Version::supports_evex(), "");
2750 InstructionMark im(this);
2751 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2752 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2753 attributes.set_is_evex_instruction();
2754 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2755 emit_int8(0x6F);
2756 emit_operand(dst, src);
2757 }
2758
2759 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2760 assert(VM_Version::supports_evex(), "");
2761 assert(src != xnoreg, "sanity");
2762 InstructionMark im(this);
2763 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2764 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2765 attributes.reset_is_clear_context();
2766 attributes.set_is_evex_instruction();
2767 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2768 emit_int8(0x7F);
2769 emit_operand(src, dst);
2770 }
2771
2772 // Uses zero extension on 64bit
2773
2774 void Assembler::movl(Register dst, int32_t imm32) {
2775 int encode = prefix_and_encode(dst->encoding());
2776 emit_int8((unsigned char)(0xB8 | encode));
2777 emit_int32(imm32);
2778 }
2779
2780 void Assembler::movl(Register dst, Register src) {
2781 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2782 emit_int8((unsigned char)0x8B);
2783 emit_int8((unsigned char)(0xC0 | encode));
2784 }
2785
2786 void Assembler::movl(Register dst, Address src) {
2787 InstructionMark im(this);
2788 prefix(src, dst);
2789 emit_int8((unsigned char)0x8B);
2790 emit_operand(dst, src);
2791 }
2792
2793 void Assembler::movl(Address dst, int32_t imm32) {
2794 InstructionMark im(this);
2795 prefix(dst);
2796 emit_int8((unsigned char)0xC7);
2797 emit_operand(rax, dst, 4);
2798 emit_int32(imm32);
2799 }
2800
2801 void Assembler::movl(Address dst, Register src) {
2802 InstructionMark im(this);
2803 prefix(dst, src);
2804 emit_int8((unsigned char)0x89);
2805 emit_operand(src, dst);
2806 }
2807
2808 // New cpus require to use movsd and movss to avoid partial register stall
2809 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2810 // The selection is done in MacroAssembler::movdbl() and movflt().
2811 void Assembler::movlpd(XMMRegister dst, Address src) {
2812 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2813 InstructionMark im(this);
2814 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2815 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2816 attributes.set_rex_vex_w_reverted();
2817 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2818 emit_int8(0x12);
2819 emit_operand(dst, src);
2820 }
2821
2822 void Assembler::movq( MMXRegister dst, Address src ) {
2823 assert( VM_Version::supports_mmx(), "" );
2824 emit_int8(0x0F);
2825 emit_int8(0x6F);
2826 emit_operand(dst, src);
2827 }
2828
2829 void Assembler::movq( Address dst, MMXRegister src ) {
2830 assert( VM_Version::supports_mmx(), "" );
2831 emit_int8(0x0F);
2832 emit_int8(0x7F);
2833 // workaround gcc (3.2.1-7a) bug
2834 // In that version of gcc with only an emit_operand(MMX, Address)
2835 // gcc will tail jump and try and reverse the parameters completely
2836 // obliterating dst in the process. By having a version available
2837 // that doesn't need to swap the args at the tail jump the bug is
2838 // avoided.
2839 emit_operand(dst, src);
2840 }
2841
2842 void Assembler::movq(XMMRegister dst, Address src) {
2843 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2844 InstructionMark im(this);
2845 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2846 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2847 attributes.set_rex_vex_w_reverted();
2848 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2849 emit_int8(0x7E);
2850 emit_operand(dst, src);
2851 }
2852
2853 void Assembler::movq(Address dst, XMMRegister src) {
2854 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2855 InstructionMark im(this);
2856 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2857 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2858 attributes.set_rex_vex_w_reverted();
2859 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2860 emit_int8((unsigned char)0xD6);
2861 emit_operand(src, dst);
2862 }
2863
2864 void Assembler::movsbl(Register dst, Address src) { // movsxb
2865 InstructionMark im(this);
2866 prefix(src, dst);
2867 emit_int8(0x0F);
2868 emit_int8((unsigned char)0xBE);
2869 emit_operand(dst, src);
2870 }
2871
2872 void Assembler::movsbl(Register dst, Register src) { // movsxb
2873 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2874 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2875 emit_int8(0x0F);
2876 emit_int8((unsigned char)0xBE);
2877 emit_int8((unsigned char)(0xC0 | encode));
2878 }
2879
2880 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2881 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2882 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2883 attributes.set_rex_vex_w_reverted();
2884 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2885 emit_int8(0x10);
2886 emit_int8((unsigned char)(0xC0 | encode));
2887 }
2888
2889 void Assembler::movsd(XMMRegister dst, Address src) {
2890 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2891 InstructionMark im(this);
2892 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2893 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2894 attributes.set_rex_vex_w_reverted();
2895 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2896 emit_int8(0x10);
2897 emit_operand(dst, src);
2898 }
2899
2900 void Assembler::movsd(Address dst, XMMRegister src) {
2901 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2902 InstructionMark im(this);
2903 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2904 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2905 attributes.reset_is_clear_context();
2906 attributes.set_rex_vex_w_reverted();
2907 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2908 emit_int8(0x11);
2909 emit_operand(src, dst);
2910 }
2911
2912 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2913 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2914 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2915 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2916 emit_int8(0x10);
2917 emit_int8((unsigned char)(0xC0 | encode));
2918 }
2919
2920 void Assembler::movss(XMMRegister dst, Address src) {
2921 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2922 InstructionMark im(this);
2923 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2924 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2925 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2926 emit_int8(0x10);
2927 emit_operand(dst, src);
2928 }
2929
2930 void Assembler::movss(Address dst, XMMRegister src) {
2931 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2932 InstructionMark im(this);
2933 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2934 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2935 attributes.reset_is_clear_context();
2936 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2937 emit_int8(0x11);
2938 emit_operand(src, dst);
2939 }
2940
2941 void Assembler::movswl(Register dst, Address src) { // movsxw
2942 InstructionMark im(this);
2943 prefix(src, dst);
2944 emit_int8(0x0F);
2945 emit_int8((unsigned char)0xBF);
2946 emit_operand(dst, src);
2947 }
2948
2949 void Assembler::movswl(Register dst, Register src) { // movsxw
2950 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2951 emit_int8(0x0F);
2952 emit_int8((unsigned char)0xBF);
2953 emit_int8((unsigned char)(0xC0 | encode));
2954 }
2955
2956 void Assembler::movw(Address dst, int imm16) {
2957 InstructionMark im(this);
2958
2959 emit_int8(0x66); // switch to 16-bit mode
2960 prefix(dst);
2961 emit_int8((unsigned char)0xC7);
2962 emit_operand(rax, dst, 2);
2963 emit_int16(imm16);
2964 }
2965
2966 void Assembler::movw(Register dst, Address src) {
2967 InstructionMark im(this);
2968 emit_int8(0x66);
2969 prefix(src, dst);
2970 emit_int8((unsigned char)0x8B);
2971 emit_operand(dst, src);
2972 }
2973
2974 void Assembler::movw(Address dst, Register src) {
2975 InstructionMark im(this);
2976 emit_int8(0x66);
2977 prefix(dst, src);
2978 emit_int8((unsigned char)0x89);
2979 emit_operand(src, dst);
2980 }
2981
2982 void Assembler::movzbl(Register dst, Address src) { // movzxb
2983 InstructionMark im(this);
2984 prefix(src, dst);
2985 emit_int8(0x0F);
2986 emit_int8((unsigned char)0xB6);
2987 emit_operand(dst, src);
2988 }
2989
2990 void Assembler::movzbl(Register dst, Register src) { // movzxb
2991 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2992 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2993 emit_int8(0x0F);
2994 emit_int8((unsigned char)0xB6);
2995 emit_int8(0xC0 | encode);
2996 }
2997
2998 void Assembler::movzwl(Register dst, Address src) { // movzxw
2999 InstructionMark im(this);
3000 prefix(src, dst);
3001 emit_int8(0x0F);
3002 emit_int8((unsigned char)0xB7);
3003 emit_operand(dst, src);
3004 }
3005
3006 void Assembler::movzwl(Register dst, Register src) { // movzxw
3007 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3008 emit_int8(0x0F);
3009 emit_int8((unsigned char)0xB7);
3010 emit_int8(0xC0 | encode);
3011 }
3012
3013 void Assembler::mull(Address src) {
3014 InstructionMark im(this);
3015 prefix(src);
3016 emit_int8((unsigned char)0xF7);
3017 emit_operand(rsp, src);
3018 }
3019
3020 void Assembler::mull(Register src) {
3021 int encode = prefix_and_encode(src->encoding());
3022 emit_int8((unsigned char)0xF7);
3023 emit_int8((unsigned char)(0xE0 | encode));
3024 }
3025
3026 void Assembler::mulsd(XMMRegister dst, Address src) {
3027 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3028 InstructionMark im(this);
3029 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3030 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3031 attributes.set_rex_vex_w_reverted();
3032 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3033 emit_int8(0x59);
3034 emit_operand(dst, src);
3035 }
3036
3037 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
3038 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3039 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3040 attributes.set_rex_vex_w_reverted();
3041 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3042 emit_int8(0x59);
3043 emit_int8((unsigned char)(0xC0 | encode));
3044 }
3045
3046 void Assembler::mulss(XMMRegister dst, Address src) {
3047 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3048 InstructionMark im(this);
3049 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3050 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3051 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3052 emit_int8(0x59);
3053 emit_operand(dst, src);
3054 }
3055
3056 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
3057 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3058 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3059 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3060 emit_int8(0x59);
3061 emit_int8((unsigned char)(0xC0 | encode));
3062 }
3063
3064 void Assembler::negl(Register dst) {
3065 int encode = prefix_and_encode(dst->encoding());
3066 emit_int8((unsigned char)0xF7);
3067 emit_int8((unsigned char)(0xD8 | encode));
3068 }
3069
3070 void Assembler::nop(int i) {
3071 #ifdef ASSERT
3072 assert(i > 0, " ");
3073 // The fancy nops aren't currently recognized by debuggers making it a
3074 // pain to disassemble code while debugging. If asserts are on clearly
3075 // speed is not an issue so simply use the single byte traditional nop
3076 // to do alignment.
3077
3078 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
3079 return;
3080
3081 #endif // ASSERT
3082
3083 if (UseAddressNop && VM_Version::is_intel()) {
3084 //
3085 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
3086 // 1: 0x90
3087 // 2: 0x66 0x90
3088 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3089 // 4: 0x0F 0x1F 0x40 0x00
3090 // 5: 0x0F 0x1F 0x44 0x00 0x00
3091 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3092 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3093 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3094 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3095 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3096 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3097
3098 // The rest coding is Intel specific - don't use consecutive address nops
3099
3100 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3101 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3102 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3103 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3104
3105 while(i >= 15) {
3106 // For Intel don't generate consecutive addess nops (mix with regular nops)
3107 i -= 15;
3108 emit_int8(0x66); // size prefix
3109 emit_int8(0x66); // size prefix
3110 emit_int8(0x66); // size prefix
3111 addr_nop_8();
3112 emit_int8(0x66); // size prefix
3113 emit_int8(0x66); // size prefix
3114 emit_int8(0x66); // size prefix
3115 emit_int8((unsigned char)0x90);
3116 // nop
3117 }
3118 switch (i) {
3119 case 14:
3120 emit_int8(0x66); // size prefix
3121 case 13:
3122 emit_int8(0x66); // size prefix
3123 case 12:
3124 addr_nop_8();
3125 emit_int8(0x66); // size prefix
3126 emit_int8(0x66); // size prefix
3127 emit_int8(0x66); // size prefix
3128 emit_int8((unsigned char)0x90);
3129 // nop
3130 break;
3131 case 11:
3132 emit_int8(0x66); // size prefix
3133 case 10:
3134 emit_int8(0x66); // size prefix
3135 case 9:
3136 emit_int8(0x66); // size prefix
3137 case 8:
3138 addr_nop_8();
3139 break;
3140 case 7:
3141 addr_nop_7();
3142 break;
3143 case 6:
3144 emit_int8(0x66); // size prefix
3145 case 5:
3146 addr_nop_5();
3147 break;
3148 case 4:
3149 addr_nop_4();
3150 break;
3151 case 3:
3152 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3153 emit_int8(0x66); // size prefix
3154 case 2:
3155 emit_int8(0x66); // size prefix
3156 case 1:
3157 emit_int8((unsigned char)0x90);
3158 // nop
3159 break;
3160 default:
3161 assert(i == 0, " ");
3162 }
3163 return;
3164 }
3165 if (UseAddressNop && VM_Version::is_amd_family()) {
3166 //
3167 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3168 // 1: 0x90
3169 // 2: 0x66 0x90
3170 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3171 // 4: 0x0F 0x1F 0x40 0x00
3172 // 5: 0x0F 0x1F 0x44 0x00 0x00
3173 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3174 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3175 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3176 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3177 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3178 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3179
3180 // The rest coding is AMD specific - use consecutive address nops
3181
3182 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3183 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3184 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3185 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3186 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3187 // Size prefixes (0x66) are added for larger sizes
3188
3189 while(i >= 22) {
3190 i -= 11;
3191 emit_int8(0x66); // size prefix
3192 emit_int8(0x66); // size prefix
3193 emit_int8(0x66); // size prefix
3194 addr_nop_8();
3195 }
3196 // Generate first nop for size between 21-12
3197 switch (i) {
3198 case 21:
3199 i -= 1;
3200 emit_int8(0x66); // size prefix
3201 case 20:
3202 case 19:
3203 i -= 1;
3204 emit_int8(0x66); // size prefix
3205 case 18:
3206 case 17:
3207 i -= 1;
3208 emit_int8(0x66); // size prefix
3209 case 16:
3210 case 15:
3211 i -= 8;
3212 addr_nop_8();
3213 break;
3214 case 14:
3215 case 13:
3216 i -= 7;
3217 addr_nop_7();
3218 break;
3219 case 12:
3220 i -= 6;
3221 emit_int8(0x66); // size prefix
3222 addr_nop_5();
3223 break;
3224 default:
3225 assert(i < 12, " ");
3226 }
3227
3228 // Generate second nop for size between 11-1
3229 switch (i) {
3230 case 11:
3231 emit_int8(0x66); // size prefix
3232 case 10:
3233 emit_int8(0x66); // size prefix
3234 case 9:
3235 emit_int8(0x66); // size prefix
3236 case 8:
3237 addr_nop_8();
3238 break;
3239 case 7:
3240 addr_nop_7();
3241 break;
3242 case 6:
3243 emit_int8(0x66); // size prefix
3244 case 5:
3245 addr_nop_5();
3246 break;
3247 case 4:
3248 addr_nop_4();
3249 break;
3250 case 3:
3251 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3252 emit_int8(0x66); // size prefix
3253 case 2:
3254 emit_int8(0x66); // size prefix
3255 case 1:
3256 emit_int8((unsigned char)0x90);
3257 // nop
3258 break;
3259 default:
3260 assert(i == 0, " ");
3261 }
3262 return;
3263 }
3264
3265 if (UseAddressNop && VM_Version::is_zx()) {
3266 //
3267 // Using multi-bytes nops "0x0F 0x1F [address]" for ZX
3268 // 1: 0x90
3269 // 2: 0x66 0x90
3270 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3271 // 4: 0x0F 0x1F 0x40 0x00
3272 // 5: 0x0F 0x1F 0x44 0x00 0x00
3273 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3274 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3275 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3276 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3277 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3278 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3279
3280 // The rest coding is ZX specific - don't use consecutive address nops
3281
3282 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3283 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3284 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3285 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3286
3287 while (i >= 15) {
3288 // For ZX don't generate consecutive addess nops (mix with regular nops)
3289 i -= 15;
3290 emit_int8(0x66); // size prefix
3291 emit_int8(0x66); // size prefix
3292 emit_int8(0x66); // size prefix
3293 addr_nop_8();
3294 emit_int8(0x66); // size prefix
3295 emit_int8(0x66); // size prefix
3296 emit_int8(0x66); // size prefix
3297 emit_int8((unsigned char)0x90);
3298 // nop
3299 }
3300 switch (i) {
3301 case 14:
3302 emit_int8(0x66); // size prefix
3303 case 13:
3304 emit_int8(0x66); // size prefix
3305 case 12:
3306 addr_nop_8();
3307 emit_int8(0x66); // size prefix
3308 emit_int8(0x66); // size prefix
3309 emit_int8(0x66); // size prefix
3310 emit_int8((unsigned char)0x90);
3311 // nop
3312 break;
3313 case 11:
3314 emit_int8(0x66); // size prefix
3315 case 10:
3316 emit_int8(0x66); // size prefix
3317 case 9:
3318 emit_int8(0x66); // size prefix
3319 case 8:
3320 addr_nop_8();
3321 break;
3322 case 7:
3323 addr_nop_7();
3324 break;
3325 case 6:
3326 emit_int8(0x66); // size prefix
3327 case 5:
3328 addr_nop_5();
3329 break;
3330 case 4:
3331 addr_nop_4();
3332 break;
3333 case 3:
3334 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3335 emit_int8(0x66); // size prefix
3336 case 2:
3337 emit_int8(0x66); // size prefix
3338 case 1:
3339 emit_int8((unsigned char)0x90);
3340 // nop
3341 break;
3342 default:
3343 assert(i == 0, " ");
3344 }
3345 return;
3346 }
3347
3348 // Using nops with size prefixes "0x66 0x90".
3349 // From AMD Optimization Guide:
3350 // 1: 0x90
3351 // 2: 0x66 0x90
3352 // 3: 0x66 0x66 0x90
3353 // 4: 0x66 0x66 0x66 0x90
3354 // 5: 0x66 0x66 0x90 0x66 0x90
3355 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3356 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3357 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3358 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3359 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3360 //
3361 while(i > 12) {
3362 i -= 4;
3363 emit_int8(0x66); // size prefix
3364 emit_int8(0x66);
3365 emit_int8(0x66);
3366 emit_int8((unsigned char)0x90);
3367 // nop
3368 }
3369 // 1 - 12 nops
3370 if(i > 8) {
3371 if(i > 9) {
3372 i -= 1;
3373 emit_int8(0x66);
3374 }
3375 i -= 3;
3376 emit_int8(0x66);
3377 emit_int8(0x66);
3378 emit_int8((unsigned char)0x90);
3379 }
3380 // 1 - 8 nops
3381 if(i > 4) {
3382 if(i > 6) {
3383 i -= 1;
3384 emit_int8(0x66);
3385 }
3386 i -= 3;
3387 emit_int8(0x66);
3388 emit_int8(0x66);
3389 emit_int8((unsigned char)0x90);
3390 }
3391 switch (i) {
3392 case 4:
3393 emit_int8(0x66);
3394 case 3:
3395 emit_int8(0x66);
3396 case 2:
3397 emit_int8(0x66);
3398 case 1:
3399 emit_int8((unsigned char)0x90);
3400 break;
3401 default:
3402 assert(i == 0, " ");
3403 }
3404 }
3405
3406 void Assembler::notl(Register dst) {
3407 int encode = prefix_and_encode(dst->encoding());
3408 emit_int8((unsigned char)0xF7);
3409 emit_int8((unsigned char)(0xD0 | encode));
3410 }
3411
3412 void Assembler::orl(Address dst, int32_t imm32) {
3413 InstructionMark im(this);
3414 prefix(dst);
3415 emit_arith_operand(0x81, rcx, dst, imm32);
3416 }
3417
3418 void Assembler::orl(Register dst, int32_t imm32) {
3419 prefix(dst);
3420 emit_arith(0x81, 0xC8, dst, imm32);
3421 }
3422
3423 void Assembler::orl(Register dst, Address src) {
3424 InstructionMark im(this);
3425 prefix(src, dst);
3426 emit_int8(0x0B);
3427 emit_operand(dst, src);
3428 }
3429
3430 void Assembler::orl(Register dst, Register src) {
3431 (void) prefix_and_encode(dst->encoding(), src->encoding());
3432 emit_arith(0x0B, 0xC0, dst, src);
3433 }
3434
3435 void Assembler::orl(Address dst, Register src) {
3436 InstructionMark im(this);
3437 prefix(dst, src);
3438 emit_int8(0x09);
3439 emit_operand(src, dst);
3440 }
3441
3442 void Assembler::orb(Address dst, int imm8) {
3443 InstructionMark im(this);
3444 prefix(dst);
3445 emit_int8((unsigned char)0x80);
3446 emit_operand(rcx, dst, 1);
3447 emit_int8(imm8);
3448 }
3449
3450 void Assembler::packuswb(XMMRegister dst, Address src) {
3451 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3452 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3453 InstructionMark im(this);
3454 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3455 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3456 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3457 emit_int8(0x67);
3458 emit_operand(dst, src);
3459 }
3460
3461 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3462 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3463 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3464 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3465 emit_int8(0x67);
3466 emit_int8((unsigned char)(0xC0 | encode));
3467 }
3468
3469 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3470 assert(UseAVX > 0, "some form of AVX must be enabled");
3471 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3472 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3473 emit_int8(0x67);
3474 emit_int8((unsigned char)(0xC0 | encode));
3475 }
3476
3477 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3478 assert(VM_Version::supports_avx2(), "");
3479 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3480 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3481 emit_int8(0x00);
3482 emit_int8((unsigned char)(0xC0 | encode));
3483 emit_int8(imm8);
3484 }
3485
3486 void Assembler::vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3487 assert(UseAVX > 2, "requires AVX512F");
3488 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3489 attributes.set_is_evex_instruction();
3490 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3491 emit_int8((unsigned char)0x36);
3492 emit_int8((unsigned char)(0xC0 | encode));
3493 }
3494
3495 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3496 assert(VM_Version::supports_avx2(), "");
3497 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3498 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3499 emit_int8(0x46);
3500 emit_int8(0xC0 | encode);
3501 emit_int8(imm8);
3502 }
3503
3504 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3505 assert(VM_Version::supports_avx(), "");
3506 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3507 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3508 emit_int8(0x06);
3509 emit_int8(0xC0 | encode);
3510 emit_int8(imm8);
3511 }
3512
3513 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3514 assert(VM_Version::supports_evex(), "");
3515 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3516 attributes.set_is_evex_instruction();
3517 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3518 emit_int8(0x76);
3519 emit_int8((unsigned char)(0xC0 | encode));
3520 }
3521
3522
3523 void Assembler::pause() {
3524 emit_int8((unsigned char)0xF3);
3525 emit_int8((unsigned char)0x90);
3526 }
3527
3528 void Assembler::ud2() {
3529 emit_int8(0x0F);
3530 emit_int8(0x0B);
3531 }
3532
3533 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3534 assert(VM_Version::supports_sse4_2(), "");
3535 InstructionMark im(this);
3536 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3537 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3538 emit_int8(0x61);
3539 emit_operand(dst, src);
3540 emit_int8(imm8);
3541 }
3542
3543 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3544 assert(VM_Version::supports_sse4_2(), "");
3545 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3546 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3547 emit_int8(0x61);
3548 emit_int8((unsigned char)(0xC0 | encode));
3549 emit_int8(imm8);
3550 }
3551
3552 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3553 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3554 assert(VM_Version::supports_sse2(), "");
3555 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3556 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3557 emit_int8(0x74);
3558 emit_int8((unsigned char)(0xC0 | encode));
3559 }
3560
3561 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3562 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3563 assert(VM_Version::supports_avx(), "");
3564 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3565 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3566 emit_int8(0x74);
3567 emit_int8((unsigned char)(0xC0 | encode));
3568 }
3569
3570 // In this context, kdst is written the mask used to process the equal components
3571 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3572 assert(VM_Version::supports_avx512bw(), "");
3573 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3574 attributes.set_is_evex_instruction();
3575 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3576 emit_int8(0x74);
3577 emit_int8((unsigned char)(0xC0 | encode));
3578 }
3579
3580 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3581 assert(VM_Version::supports_avx512vlbw(), "");
3582 InstructionMark im(this);
3583 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3584 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3585 attributes.set_is_evex_instruction();
3586 int dst_enc = kdst->encoding();
3587 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3588 emit_int8(0x64);
3589 emit_operand(as_Register(dst_enc), src);
3590 }
3591
3592 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3593 assert(VM_Version::supports_avx512vlbw(), "");
3594 InstructionMark im(this);
3595 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3596 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3597 attributes.reset_is_clear_context();
3598 attributes.set_embedded_opmask_register_specifier(mask);
3599 attributes.set_is_evex_instruction();
3600 int dst_enc = kdst->encoding();
3601 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3602 emit_int8(0x64);
3603 emit_operand(as_Register(dst_enc), src);
3604 }
3605
3606 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3607 assert(VM_Version::supports_avx512vlbw(), "");
3608 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3609 attributes.set_is_evex_instruction();
3610 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3611 emit_int8(0x3E);
3612 emit_int8((unsigned char)(0xC0 | encode));
3613 emit_int8(vcc);
3614 }
3615
3616 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3617 assert(VM_Version::supports_avx512vlbw(), "");
3618 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3619 attributes.reset_is_clear_context();
3620 attributes.set_embedded_opmask_register_specifier(mask);
3621 attributes.set_is_evex_instruction();
3622 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3623 emit_int8(0x3E);
3624 emit_int8((unsigned char)(0xC0 | encode));
3625 emit_int8(vcc);
3626 }
3627
3628 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
3629 assert(VM_Version::supports_avx512vlbw(), "");
3630 InstructionMark im(this);
3631 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3632 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3633 attributes.set_is_evex_instruction();
3634 int dst_enc = kdst->encoding();
3635 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3636 emit_int8(0x3E);
3637 emit_operand(as_Register(dst_enc), src);
3638 emit_int8(vcc);
3639 }
3640
3641 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3642 assert(VM_Version::supports_avx512bw(), "");
3643 InstructionMark im(this);
3644 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3645 attributes.set_is_evex_instruction();
3646 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3647 int dst_enc = kdst->encoding();
3648 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3649 emit_int8(0x74);
3650 emit_operand(as_Register(dst_enc), src);
3651 }
3652
3653 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3654 assert(VM_Version::supports_avx512vlbw(), "");
3655 InstructionMark im(this);
3656 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ true);
3657 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3658 attributes.reset_is_clear_context();
3659 attributes.set_embedded_opmask_register_specifier(mask);
3660 attributes.set_is_evex_instruction();
3661 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3662 emit_int8(0x74);
3663 emit_operand(as_Register(kdst->encoding()), src);
3664 }
3665
3666 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3667 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3668 assert(VM_Version::supports_sse2(), "");
3669 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3670 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3671 emit_int8(0x75);
3672 emit_int8((unsigned char)(0xC0 | encode));
3673 }
3674
3675 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3676 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3677 assert(VM_Version::supports_avx(), "");
3678 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3679 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3680 emit_int8(0x75);
3681 emit_int8((unsigned char)(0xC0 | encode));
3682 }
3683
3684 // In this context, kdst is written the mask used to process the equal components
3685 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3686 assert(VM_Version::supports_avx512bw(), "");
3687 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3688 attributes.set_is_evex_instruction();
3689 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3690 emit_int8(0x75);
3691 emit_int8((unsigned char)(0xC0 | encode));
3692 }
3693
3694 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3695 assert(VM_Version::supports_avx512bw(), "");
3696 InstructionMark im(this);
3697 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3698 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3699 attributes.set_is_evex_instruction();
3700 int dst_enc = kdst->encoding();
3701 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3702 emit_int8(0x75);
3703 emit_operand(as_Register(dst_enc), src);
3704 }
3705
3706 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3707 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3708 assert(VM_Version::supports_sse2(), "");
3709 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3710 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3711 emit_int8(0x76);
3712 emit_int8((unsigned char)(0xC0 | encode));
3713 }
3714
3715 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3716 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3717 assert(VM_Version::supports_avx(), "");
3718 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3719 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3720 emit_int8(0x76);
3721 emit_int8((unsigned char)(0xC0 | encode));
3722 }
3723
3724 // In this context, kdst is written the mask used to process the equal components
3725 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3726 assert(VM_Version::supports_evex(), "");
3727 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3728 attributes.set_is_evex_instruction();
3729 attributes.reset_is_clear_context();
3730 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3731 emit_int8(0x76);
3732 emit_int8((unsigned char)(0xC0 | encode));
3733 }
3734
3735 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3736 assert(VM_Version::supports_evex(), "");
3737 InstructionMark im(this);
3738 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3739 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3740 attributes.reset_is_clear_context();
3741 attributes.set_is_evex_instruction();
3742 int dst_enc = kdst->encoding();
3743 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3744 emit_int8(0x76);
3745 emit_operand(as_Register(dst_enc), src);
3746 }
3747
3748 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3749 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3750 assert(VM_Version::supports_sse4_1(), "");
3751 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3752 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3753 emit_int8(0x29);
3754 emit_int8((unsigned char)(0xC0 | encode));
3755 }
3756
3757 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3758 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3759 assert(VM_Version::supports_avx(), "");
3760 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3761 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3762 emit_int8(0x29);
3763 emit_int8((unsigned char)(0xC0 | encode));
3764 }
3765
3766 // In this context, kdst is written the mask used to process the equal components
3767 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3768 assert(VM_Version::supports_evex(), "");
3769 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3770 attributes.reset_is_clear_context();
3771 attributes.set_is_evex_instruction();
3772 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3773 emit_int8(0x29);
3774 emit_int8((unsigned char)(0xC0 | encode));
3775 }
3776
3777 // In this context, kdst is written the mask used to process the equal components
3778 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3779 assert(VM_Version::supports_evex(), "");
3780 InstructionMark im(this);
3781 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3782 attributes.reset_is_clear_context();
3783 attributes.set_is_evex_instruction();
3784 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3785 int dst_enc = kdst->encoding();
3786 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3787 emit_int8(0x29);
3788 emit_operand(as_Register(dst_enc), src);
3789 }
3790
3791 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3792 assert(VM_Version::supports_sse2(), "");
3793 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3794 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3795 emit_int8((unsigned char)0xD7);
3796 emit_int8((unsigned char)(0xC0 | encode));
3797 }
3798
3799 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3800 assert(VM_Version::supports_avx2(), "");
3801 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3802 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3803 emit_int8((unsigned char)0xD7);
3804 emit_int8((unsigned char)(0xC0 | encode));
3805 }
3806
3807 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3808 assert(VM_Version::supports_sse4_1(), "");
3809 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3810 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3811 emit_int8(0x16);
3812 emit_int8((unsigned char)(0xC0 | encode));
3813 emit_int8(imm8);
3814 }
3815
3816 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3817 assert(VM_Version::supports_sse4_1(), "");
3818 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3819 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3820 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3821 emit_int8(0x16);
3822 emit_operand(src, dst);
3823 emit_int8(imm8);
3824 }
3825
3826 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3827 assert(VM_Version::supports_sse4_1(), "");
3828 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3829 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3830 emit_int8(0x16);
3831 emit_int8((unsigned char)(0xC0 | encode));
3832 emit_int8(imm8);
3833 }
3834
3835 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3836 assert(VM_Version::supports_sse4_1(), "");
3837 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3838 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3839 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3840 emit_int8(0x16);
3841 emit_operand(src, dst);
3842 emit_int8(imm8);
3843 }
3844
3845 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3846 assert(VM_Version::supports_sse2(), "");
3847 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3848 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3849 emit_int8((unsigned char)0xC5);
3850 emit_int8((unsigned char)(0xC0 | encode));
3851 emit_int8(imm8);
3852 }
3853
3854 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3855 assert(VM_Version::supports_sse4_1(), "");
3856 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3857 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3858 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3859 emit_int8((unsigned char)0x15);
3860 emit_operand(src, dst);
3861 emit_int8(imm8);
3862 }
3863
3864 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3865 assert(VM_Version::supports_sse4_1(), "");
3866 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3867 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3868 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3869 emit_int8(0x14);
3870 emit_operand(src, dst);
3871 emit_int8(imm8);
3872 }
3873
3874 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3875 assert(VM_Version::supports_sse4_1(), "");
3876 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3877 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3878 emit_int8(0x22);
3879 emit_int8((unsigned char)(0xC0 | encode));
3880 emit_int8(imm8);
3881 }
3882
3883 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3884 assert(VM_Version::supports_sse4_1(), "");
3885 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3886 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3887 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3888 emit_int8(0x22);
3889 emit_operand(dst,src);
3890 emit_int8(imm8);
3891 }
3892
3893 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3894 assert(VM_Version::supports_sse4_1(), "");
3895 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3896 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3897 emit_int8(0x22);
3898 emit_int8((unsigned char)(0xC0 | encode));
3899 emit_int8(imm8);
3900 }
3901
3902 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3903 assert(VM_Version::supports_sse4_1(), "");
3904 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3905 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3906 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3907 emit_int8(0x22);
3908 emit_operand(dst, src);
3909 emit_int8(imm8);
3910 }
3911
3912 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3913 assert(VM_Version::supports_sse2(), "");
3914 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3915 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3916 emit_int8((unsigned char)0xC4);
3917 emit_int8((unsigned char)(0xC0 | encode));
3918 emit_int8(imm8);
3919 }
3920
3921 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3922 assert(VM_Version::supports_sse2(), "");
3923 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3924 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3925 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3926 emit_int8((unsigned char)0xC4);
3927 emit_operand(dst, src);
3928 emit_int8(imm8);
3929 }
3930
3931 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3932 assert(VM_Version::supports_sse4_1(), "");
3933 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3934 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3935 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3936 emit_int8(0x20);
3937 emit_operand(dst, src);
3938 emit_int8(imm8);
3939 }
3940
3941 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3942 assert(VM_Version::supports_sse4_1(), "");
3943 InstructionMark im(this);
3944 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3945 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3946 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3947 emit_int8(0x30);
3948 emit_operand(dst, src);
3949 }
3950
3951 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3952 assert(VM_Version::supports_sse4_1(), "");
3953 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3954 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3955 emit_int8(0x30);
3956 emit_int8((unsigned char)(0xC0 | encode));
3957 }
3958
3959 void Assembler::pmovsxbw(XMMRegister dst, XMMRegister src) {
3960 assert(VM_Version::supports_sse4_1(), "");
3961 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3962 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3963 emit_int8(0x20);
3964 emit_int8((unsigned char)(0xC0 | encode));
3965 }
3966
3967 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3968 assert(VM_Version::supports_avx(), "");
3969 InstructionMark im(this);
3970 assert(dst != xnoreg, "sanity");
3971 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3972 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3973 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3974 emit_int8(0x30);
3975 emit_operand(dst, src);
3976 }
3977
3978 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) {
3979 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3980 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3981 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
3982 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3983 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3984 emit_int8(0x30);
3985 emit_int8((unsigned char) (0xC0 | encode));
3986 }
3987
3988 void Assembler::vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len) {
3989 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3990 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3991 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
3992 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3993 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3994 emit_int8(0x20);
3995 emit_int8((unsigned char)(0xC0 | encode));
3996 }
3997
3998 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
3999 assert(VM_Version::supports_avx512vlbw(), "");
4000 assert(dst != xnoreg, "sanity");
4001 InstructionMark im(this);
4002 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4003 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4004 attributes.set_embedded_opmask_register_specifier(mask);
4005 attributes.set_is_evex_instruction();
4006 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4007 emit_int8(0x30);
4008 emit_operand(dst, src);
4009 }
4010 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
4011 assert(VM_Version::supports_avx512vlbw(), "");
4012 assert(src != xnoreg, "sanity");
4013 InstructionMark im(this);
4014 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4015 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4016 attributes.set_is_evex_instruction();
4017 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
4018 emit_int8(0x30);
4019 emit_operand(src, dst);
4020 }
4021
4022 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
4023 assert(VM_Version::supports_avx512vlbw(), "");
4024 assert(src != xnoreg, "sanity");
4025 InstructionMark im(this);
4026 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4027 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4028 attributes.reset_is_clear_context();
4029 attributes.set_embedded_opmask_register_specifier(mask);
4030 attributes.set_is_evex_instruction();
4031 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
4032 emit_int8(0x30);
4033 emit_operand(src, dst);
4034 }
4035
4036 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) {
4037 assert(VM_Version::supports_evex(), "");
4038 assert(src != xnoreg, "sanity");
4039 InstructionMark im(this);
4040 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4041 attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit);
4042 attributes.set_is_evex_instruction();
4043 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
4044 emit_int8(0x31);
4045 emit_operand(src, dst);
4046 }
4047
4048 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) {
4049 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4050 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4051 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
4052 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4053 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4054 emit_int8(0x33);
4055 emit_int8((unsigned char)(0xC0 | encode));
4056 }
4057
4058 void Assembler::pmaddwd(XMMRegister dst, XMMRegister src) {
4059 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4060 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4061 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4062 emit_int8((unsigned char)0xF5);
4063 emit_int8((unsigned char)(0xC0 | encode));
4064 }
4065
4066 void Assembler::vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4067 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4068 (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4069 (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0)), "");
4070 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4071 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4072 emit_int8((unsigned char)0xF5);
4073 emit_int8((unsigned char)(0xC0 | encode));
4074 }
4075
4076 void Assembler::evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4077 assert(VM_Version::supports_evex(), "");
4078 assert(VM_Version::supports_vnni(), "must support vnni");
4079 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4080 attributes.set_is_evex_instruction();
4081 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4082 emit_int8(0x52);
4083 emit_int8((unsigned char)(0xC0 | encode));
4084 }
4085
4086 // generic
4087 void Assembler::pop(Register dst) {
4088 int encode = prefix_and_encode(dst->encoding());
4089 emit_int8(0x58 | encode);
4090 }
4091
4092 void Assembler::popcntl(Register dst, Address src) {
4093 assert(VM_Version::supports_popcnt(), "must support");
4094 InstructionMark im(this);
4095 emit_int8((unsigned char)0xF3);
4096 prefix(src, dst);
4097 emit_int8(0x0F);
4098 emit_int8((unsigned char)0xB8);
4099 emit_operand(dst, src);
4100 }
4101
4102 void Assembler::popcntl(Register dst, Register src) {
4103 assert(VM_Version::supports_popcnt(), "must support");
4104 emit_int8((unsigned char)0xF3);
4105 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4106 emit_int8(0x0F);
4107 emit_int8((unsigned char)0xB8);
4108 emit_int8((unsigned char)(0xC0 | encode));
4109 }
4110
4111 void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) {
4112 assert(VM_Version::supports_vpopcntdq(), "must support vpopcntdq feature");
4113 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4114 attributes.set_is_evex_instruction();
4115 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4116 emit_int8(0x55);
4117 emit_int8((unsigned char)(0xC0 | encode));
4118 }
4119
4120 void Assembler::popf() {
4121 emit_int8((unsigned char)0x9D);
4122 }
4123
4124 #ifndef _LP64 // no 32bit push/pop on amd64
4125 void Assembler::popl(Address dst) {
4126 // NOTE: this will adjust stack by 8byte on 64bits
4127 InstructionMark im(this);
4128 prefix(dst);
4129 emit_int8((unsigned char)0x8F);
4130 emit_operand(rax, dst);
4131 }
4132 #endif
4133
4134 void Assembler::prefetch_prefix(Address src) {
4135 prefix(src);
4136 emit_int8(0x0F);
4137 }
4138
4139 void Assembler::prefetchnta(Address src) {
4140 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4141 InstructionMark im(this);
4142 prefetch_prefix(src);
4143 emit_int8(0x18);
4144 emit_operand(rax, src); // 0, src
4145 }
4146
4147 void Assembler::prefetchr(Address src) {
4148 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4149 InstructionMark im(this);
4150 prefetch_prefix(src);
4151 emit_int8(0x0D);
4152 emit_operand(rax, src); // 0, src
4153 }
4154
4155 void Assembler::prefetcht0(Address src) {
4156 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4157 InstructionMark im(this);
4158 prefetch_prefix(src);
4159 emit_int8(0x18);
4160 emit_operand(rcx, src); // 1, src
4161 }
4162
4163 void Assembler::prefetcht1(Address src) {
4164 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4165 InstructionMark im(this);
4166 prefetch_prefix(src);
4167 emit_int8(0x18);
4168 emit_operand(rdx, src); // 2, src
4169 }
4170
4171 void Assembler::prefetcht2(Address src) {
4172 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4173 InstructionMark im(this);
4174 prefetch_prefix(src);
4175 emit_int8(0x18);
4176 emit_operand(rbx, src); // 3, src
4177 }
4178
4179 void Assembler::prefetchw(Address src) {
4180 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4181 InstructionMark im(this);
4182 prefetch_prefix(src);
4183 emit_int8(0x0D);
4184 emit_operand(rcx, src); // 1, src
4185 }
4186
4187 void Assembler::prefix(Prefix p) {
4188 emit_int8(p);
4189 }
4190
4191 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
4192 assert(VM_Version::supports_ssse3(), "");
4193 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4194 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4195 emit_int8(0x00);
4196 emit_int8((unsigned char)(0xC0 | encode));
4197 }
4198
4199 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4200 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4201 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4202 0, "");
4203 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4204 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4205 emit_int8(0x00);
4206 emit_int8((unsigned char)(0xC0 | encode));
4207 }
4208
4209 void Assembler::pshufb(XMMRegister dst, Address src) {
4210 assert(VM_Version::supports_ssse3(), "");
4211 InstructionMark im(this);
4212 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4213 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4214 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4215 emit_int8(0x00);
4216 emit_operand(dst, src);
4217 }
4218
4219 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
4220 assert(isByte(mode), "invalid value");
4221 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4222 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
4223 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4224 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4225 emit_int8(0x70);
4226 emit_int8((unsigned char)(0xC0 | encode));
4227 emit_int8(mode & 0xFF);
4228 }
4229
4230 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
4231 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4232 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4233 0, "");
4234 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4235 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4236 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4237 emit_int8(0x70);
4238 emit_int8((unsigned char)(0xC0 | encode));
4239 emit_int8(mode & 0xFF);
4240 }
4241
4242 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
4243 assert(isByte(mode), "invalid value");
4244 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4245 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4246 InstructionMark im(this);
4247 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4248 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4249 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4250 emit_int8(0x70);
4251 emit_operand(dst, src);
4252 emit_int8(mode & 0xFF);
4253 }
4254
4255 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4256 assert(isByte(mode), "invalid value");
4257 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4258 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4259 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4260 emit_int8(0x70);
4261 emit_int8((unsigned char)(0xC0 | encode));
4262 emit_int8(mode & 0xFF);
4263 }
4264
4265 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
4266 assert(isByte(mode), "invalid value");
4267 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4268 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4269 InstructionMark im(this);
4270 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4271 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4272 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4273 emit_int8(0x70);
4274 emit_operand(dst, src);
4275 emit_int8(mode & 0xFF);
4276 }
4277 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4278 assert(VM_Version::supports_evex(), "requires EVEX support");
4279 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
4280 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4281 attributes.set_is_evex_instruction();
4282 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4283 emit_int8(0x43);
4284 emit_int8((unsigned char)(0xC0 | encode));
4285 emit_int8(imm8 & 0xFF);
4286 }
4287
4288 void Assembler::psrldq(XMMRegister dst, int shift) {
4289 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4290 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4291 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4292 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4293 emit_int8(0x73);
4294 emit_int8((unsigned char)(0xC0 | encode));
4295 emit_int8(shift);
4296 }
4297
4298 void Assembler::vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4299 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4300 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4301 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
4302 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4303 int encode = vex_prefix_and_encode(xmm3->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4304 emit_int8(0x73);
4305 emit_int8((unsigned char)(0xC0 | encode));
4306 emit_int8(shift & 0xFF);
4307 }
4308
4309 void Assembler::pslldq(XMMRegister dst, int shift) {
4310 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4311 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4312 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4313 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
4314 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4315 emit_int8(0x73);
4316 emit_int8((unsigned char)(0xC0 | encode));
4317 emit_int8(shift);
4318 }
4319
4320 void Assembler::vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4321 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4322 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4323 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
4324 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4325 int encode = vex_prefix_and_encode(xmm7->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4326 emit_int8(0x73);
4327 emit_int8((unsigned char)(0xC0 | encode));
4328 emit_int8(shift & 0xFF);
4329 }
4330
4331 void Assembler::ptest(XMMRegister dst, Address src) {
4332 assert(VM_Version::supports_sse4_1(), "");
4333 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4334 InstructionMark im(this);
4335 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4336 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4337 emit_int8(0x17);
4338 emit_operand(dst, src);
4339 }
4340
4341 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
4342 assert(VM_Version::supports_sse4_1() || VM_Version::supports_avx(), "");
4343 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4344 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4345 emit_int8(0x17);
4346 emit_int8((unsigned char)(0xC0 | encode));
4347 }
4348
4349 void Assembler::vptest(XMMRegister dst, Address src) {
4350 assert(VM_Version::supports_avx(), "");
4351 InstructionMark im(this);
4352 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4353 assert(dst != xnoreg, "sanity");
4354 // swap src<->dst for encoding
4355 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4356 emit_int8(0x17);
4357 emit_operand(dst, src);
4358 }
4359
4360 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
4361 assert(VM_Version::supports_avx(), "");
4362 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4363 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4364 emit_int8(0x17);
4365 emit_int8((unsigned char)(0xC0 | encode));
4366 }
4367
4368 void Assembler::punpcklbw(XMMRegister dst, Address src) {
4369 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4370 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4371 InstructionMark im(this);
4372 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
4373 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4374 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4375 emit_int8(0x60);
4376 emit_operand(dst, src);
4377 }
4378
4379 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4380 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4381 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
4382 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4383 emit_int8(0x60);
4384 emit_int8((unsigned char)(0xC0 | encode));
4385 }
4386
4387 void Assembler::punpckldq(XMMRegister dst, Address src) {
4388 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4389 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4390 InstructionMark im(this);
4391 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4392 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4393 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4394 emit_int8(0x62);
4395 emit_operand(dst, src);
4396 }
4397
4398 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
4399 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4400 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4401 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4402 emit_int8(0x62);
4403 emit_int8((unsigned char)(0xC0 | encode));
4404 }
4405
4406 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
4407 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4408 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4409 attributes.set_rex_vex_w_reverted();
4410 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4411 emit_int8(0x6C);
4412 emit_int8((unsigned char)(0xC0 | encode));
4413 }
4414
4415 void Assembler::push(int32_t imm32) {
4416 // in 64bits we push 64bits onto the stack but only
4417 // take a 32bit immediate
4418 emit_int8(0x68);
4419 emit_int32(imm32);
4420 }
4421
4422 void Assembler::push(Register src) {
4423 int encode = prefix_and_encode(src->encoding());
4424
4425 emit_int8(0x50 | encode);
4426 }
4427
4428 void Assembler::pushf() {
4429 emit_int8((unsigned char)0x9C);
4430 }
4431
4432 #ifndef _LP64 // no 32bit push/pop on amd64
4433 void Assembler::pushl(Address src) {
4434 // Note this will push 64bit on 64bit
4435 InstructionMark im(this);
4436 prefix(src);
4437 emit_int8((unsigned char)0xFF);
4438 emit_operand(rsi, src);
4439 }
4440 #endif
4441
4442 void Assembler::rcll(Register dst, int imm8) {
4443 assert(isShiftCount(imm8), "illegal shift count");
4444 int encode = prefix_and_encode(dst->encoding());
4445 if (imm8 == 1) {
4446 emit_int8((unsigned char)0xD1);
4447 emit_int8((unsigned char)(0xD0 | encode));
4448 } else {
4449 emit_int8((unsigned char)0xC1);
4450 emit_int8((unsigned char)0xD0 | encode);
4451 emit_int8(imm8);
4452 }
4453 }
4454
4455 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
4456 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4457 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4458 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4459 emit_int8(0x53);
4460 emit_int8((unsigned char)(0xC0 | encode));
4461 }
4462
4463 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
4464 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4465 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4466 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4467 emit_int8(0x53);
4468 emit_int8((unsigned char)(0xC0 | encode));
4469 }
4470
4471 void Assembler::rdtsc() {
4472 emit_int8((unsigned char)0x0F);
4473 emit_int8((unsigned char)0x31);
4474 }
4475
4476 // copies data from [esi] to [edi] using rcx pointer sized words
4477 // generic
4478 void Assembler::rep_mov() {
4479 emit_int8((unsigned char)0xF3);
4480 // MOVSQ
4481 LP64_ONLY(prefix(REX_W));
4482 emit_int8((unsigned char)0xA5);
4483 }
4484
4485 // sets rcx bytes with rax, value at [edi]
4486 void Assembler::rep_stosb() {
4487 emit_int8((unsigned char)0xF3); // REP
4488 LP64_ONLY(prefix(REX_W));
4489 emit_int8((unsigned char)0xAA); // STOSB
4490 }
4491
4492 // sets rcx pointer sized words with rax, value at [edi]
4493 // generic
4494 void Assembler::rep_stos() {
4495 emit_int8((unsigned char)0xF3); // REP
4496 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
4497 emit_int8((unsigned char)0xAB);
4498 }
4499
4500 // scans rcx pointer sized words at [edi] for occurance of rax,
4501 // generic
4502 void Assembler::repne_scan() { // repne_scan
4503 emit_int8((unsigned char)0xF2);
4504 // SCASQ
4505 LP64_ONLY(prefix(REX_W));
4506 emit_int8((unsigned char)0xAF);
4507 }
4508
4509 #ifdef _LP64
4510 // scans rcx 4 byte words at [edi] for occurance of rax,
4511 // generic
4512 void Assembler::repne_scanl() { // repne_scan
4513 emit_int8((unsigned char)0xF2);
4514 // SCASL
4515 emit_int8((unsigned char)0xAF);
4516 }
4517 #endif
4518
4519 void Assembler::ret(int imm16) {
4520 if (imm16 == 0) {
4521 emit_int8((unsigned char)0xC3);
4522 } else {
4523 emit_int8((unsigned char)0xC2);
4524 emit_int16(imm16);
4525 }
4526 }
4527
4528 void Assembler::sahf() {
4529 #ifdef _LP64
4530 // Not supported in 64bit mode
4531 ShouldNotReachHere();
4532 #endif
4533 emit_int8((unsigned char)0x9E);
4534 }
4535
4536 void Assembler::sarl(Register dst, int imm8) {
4537 int encode = prefix_and_encode(dst->encoding());
4538 assert(isShiftCount(imm8), "illegal shift count");
4539 if (imm8 == 1) {
4540 emit_int8((unsigned char)0xD1);
4541 emit_int8((unsigned char)(0xF8 | encode));
4542 } else {
4543 emit_int8((unsigned char)0xC1);
4544 emit_int8((unsigned char)(0xF8 | encode));
4545 emit_int8(imm8);
4546 }
4547 }
4548
4549 void Assembler::sarl(Register dst) {
4550 int encode = prefix_and_encode(dst->encoding());
4551 emit_int8((unsigned char)0xD3);
4552 emit_int8((unsigned char)(0xF8 | encode));
4553 }
4554
4555 void Assembler::sbbl(Address dst, int32_t imm32) {
4556 InstructionMark im(this);
4557 prefix(dst);
4558 emit_arith_operand(0x81, rbx, dst, imm32);
4559 }
4560
4561 void Assembler::sbbl(Register dst, int32_t imm32) {
4562 prefix(dst);
4563 emit_arith(0x81, 0xD8, dst, imm32);
4564 }
4565
4566
4567 void Assembler::sbbl(Register dst, Address src) {
4568 InstructionMark im(this);
4569 prefix(src, dst);
4570 emit_int8(0x1B);
4571 emit_operand(dst, src);
4572 }
4573
4574 void Assembler::sbbl(Register dst, Register src) {
4575 (void) prefix_and_encode(dst->encoding(), src->encoding());
4576 emit_arith(0x1B, 0xC0, dst, src);
4577 }
4578
4579 void Assembler::setb(Condition cc, Register dst) {
4580 assert(0 <= cc && cc < 16, "illegal cc");
4581 int encode = prefix_and_encode(dst->encoding(), true);
4582 emit_int8(0x0F);
4583 emit_int8((unsigned char)0x90 | cc);
4584 emit_int8((unsigned char)(0xC0 | encode));
4585 }
4586
4587 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4588 assert(VM_Version::supports_ssse3(), "");
4589 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4590 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4591 emit_int8((unsigned char)0x0F);
4592 emit_int8((unsigned char)(0xC0 | encode));
4593 emit_int8(imm8);
4594 }
4595
4596 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4597 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4598 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4599 0, "");
4600 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4601 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4602 emit_int8((unsigned char)0x0F);
4603 emit_int8((unsigned char)(0xC0 | encode));
4604 emit_int8(imm8);
4605 }
4606
4607 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
4608 assert(VM_Version::supports_evex(), "");
4609 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4610 attributes.set_is_evex_instruction();
4611 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4612 emit_int8(0x3);
4613 emit_int8((unsigned char)(0xC0 | encode));
4614 emit_int8(imm8);
4615 }
4616
4617 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4618 assert(VM_Version::supports_sse4_1(), "");
4619 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4620 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4621 emit_int8((unsigned char)0x0E);
4622 emit_int8((unsigned char)(0xC0 | encode));
4623 emit_int8(imm8);
4624 }
4625
4626 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4627 assert(VM_Version::supports_sha(), "");
4628 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
4629 emit_int8((unsigned char)0xCC);
4630 emit_int8((unsigned char)(0xC0 | encode));
4631 emit_int8((unsigned char)imm8);
4632 }
4633
4634 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4635 assert(VM_Version::supports_sha(), "");
4636 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4637 emit_int8((unsigned char)0xC8);
4638 emit_int8((unsigned char)(0xC0 | encode));
4639 }
4640
4641 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4642 assert(VM_Version::supports_sha(), "");
4643 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4644 emit_int8((unsigned char)0xC9);
4645 emit_int8((unsigned char)(0xC0 | encode));
4646 }
4647
4648 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4649 assert(VM_Version::supports_sha(), "");
4650 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4651 emit_int8((unsigned char)0xCA);
4652 emit_int8((unsigned char)(0xC0 | encode));
4653 }
4654
4655 // xmm0 is implicit additional source to this instruction.
4656 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4657 assert(VM_Version::supports_sha(), "");
4658 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4659 emit_int8((unsigned char)0xCB);
4660 emit_int8((unsigned char)(0xC0 | encode));
4661 }
4662
4663 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4664 assert(VM_Version::supports_sha(), "");
4665 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4666 emit_int8((unsigned char)0xCC);
4667 emit_int8((unsigned char)(0xC0 | encode));
4668 }
4669
4670 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4671 assert(VM_Version::supports_sha(), "");
4672 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4673 emit_int8((unsigned char)0xCD);
4674 emit_int8((unsigned char)(0xC0 | encode));
4675 }
4676
4677
4678 void Assembler::shll(Register dst, int imm8) {
4679 assert(isShiftCount(imm8), "illegal shift count");
4680 int encode = prefix_and_encode(dst->encoding());
4681 if (imm8 == 1 ) {
4682 emit_int8((unsigned char)0xD1);
4683 emit_int8((unsigned char)(0xE0 | encode));
4684 } else {
4685 emit_int8((unsigned char)0xC1);
4686 emit_int8((unsigned char)(0xE0 | encode));
4687 emit_int8(imm8);
4688 }
4689 }
4690
4691 void Assembler::shll(Register dst) {
4692 int encode = prefix_and_encode(dst->encoding());
4693 emit_int8((unsigned char)0xD3);
4694 emit_int8((unsigned char)(0xE0 | encode));
4695 }
4696
4697 void Assembler::shrl(Register dst, int imm8) {
4698 assert(isShiftCount(imm8), "illegal shift count");
4699 int encode = prefix_and_encode(dst->encoding());
4700 emit_int8((unsigned char)0xC1);
4701 emit_int8((unsigned char)(0xE8 | encode));
4702 emit_int8(imm8);
4703 }
4704
4705 void Assembler::shrl(Register dst) {
4706 int encode = prefix_and_encode(dst->encoding());
4707 emit_int8((unsigned char)0xD3);
4708 emit_int8((unsigned char)(0xE8 | encode));
4709 }
4710
4711 // copies a single word from [esi] to [edi]
4712 void Assembler::smovl() {
4713 emit_int8((unsigned char)0xA5);
4714 }
4715
4716 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4717 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4718 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4719 attributes.set_rex_vex_w_reverted();
4720 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4721 emit_int8(0x51);
4722 emit_int8((unsigned char)(0xC0 | encode));
4723 }
4724
4725 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4726 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4727 InstructionMark im(this);
4728 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4729 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4730 attributes.set_rex_vex_w_reverted();
4731 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4732 emit_int8(0x51);
4733 emit_operand(dst, src);
4734 }
4735
4736 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4737 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4738 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4739 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4740 emit_int8(0x51);
4741 emit_int8((unsigned char)(0xC0 | encode));
4742 }
4743
4744 void Assembler::std() {
4745 emit_int8((unsigned char)0xFD);
4746 }
4747
4748 void Assembler::sqrtss(XMMRegister dst, Address src) {
4749 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4750 InstructionMark im(this);
4751 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4752 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4753 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4754 emit_int8(0x51);
4755 emit_operand(dst, src);
4756 }
4757
4758 void Assembler::stmxcsr( Address dst) {
4759 if (UseAVX > 0 ) {
4760 assert(VM_Version::supports_avx(), "");
4761 InstructionMark im(this);
4762 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4763 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4764 emit_int8((unsigned char)0xAE);
4765 emit_operand(as_Register(3), dst);
4766 } else {
4767 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4768 InstructionMark im(this);
4769 prefix(dst);
4770 emit_int8(0x0F);
4771 emit_int8((unsigned char)0xAE);
4772 emit_operand(as_Register(3), dst);
4773 }
4774 }
4775
4776 void Assembler::subl(Address dst, int32_t imm32) {
4777 InstructionMark im(this);
4778 prefix(dst);
4779 emit_arith_operand(0x81, rbp, dst, imm32);
4780 }
4781
4782 void Assembler::subl(Address dst, Register src) {
4783 InstructionMark im(this);
4784 prefix(dst, src);
4785 emit_int8(0x29);
4786 emit_operand(src, dst);
4787 }
4788
4789 void Assembler::subl(Register dst, int32_t imm32) {
4790 prefix(dst);
4791 emit_arith(0x81, 0xE8, dst, imm32);
4792 }
4793
4794 // Force generation of a 4 byte immediate value even if it fits into 8bit
4795 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4796 prefix(dst);
4797 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4798 }
4799
4800 void Assembler::subl(Register dst, Address src) {
4801 InstructionMark im(this);
4802 prefix(src, dst);
4803 emit_int8(0x2B);
4804 emit_operand(dst, src);
4805 }
4806
4807 void Assembler::subl(Register dst, Register src) {
4808 (void) prefix_and_encode(dst->encoding(), src->encoding());
4809 emit_arith(0x2B, 0xC0, dst, src);
4810 }
4811
4812 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4813 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4814 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4815 attributes.set_rex_vex_w_reverted();
4816 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4817 emit_int8(0x5C);
4818 emit_int8((unsigned char)(0xC0 | encode));
4819 }
4820
4821 void Assembler::subsd(XMMRegister dst, Address src) {
4822 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4823 InstructionMark im(this);
4824 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4825 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4826 attributes.set_rex_vex_w_reverted();
4827 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4828 emit_int8(0x5C);
4829 emit_operand(dst, src);
4830 }
4831
4832 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4833 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4834 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
4835 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4836 emit_int8(0x5C);
4837 emit_int8((unsigned char)(0xC0 | encode));
4838 }
4839
4840 void Assembler::subss(XMMRegister dst, Address src) {
4841 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4842 InstructionMark im(this);
4843 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4844 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4845 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4846 emit_int8(0x5C);
4847 emit_operand(dst, src);
4848 }
4849
4850 void Assembler::testb(Register dst, int imm8) {
4851 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4852 (void) prefix_and_encode(dst->encoding(), true);
4853 emit_arith_b(0xF6, 0xC0, dst, imm8);
4854 }
4855
4856 void Assembler::testb(Address dst, int imm8) {
4857 InstructionMark im(this);
4858 prefix(dst);
4859 emit_int8((unsigned char)0xF6);
4860 emit_operand(rax, dst, 1);
4861 emit_int8(imm8);
4862 }
4863
4864 void Assembler::testl(Register dst, int32_t imm32) {
4865 // not using emit_arith because test
4866 // doesn't support sign-extension of
4867 // 8bit operands
4868 int encode = dst->encoding();
4869 if (encode == 0) {
4870 emit_int8((unsigned char)0xA9);
4871 } else {
4872 encode = prefix_and_encode(encode);
4873 emit_int8((unsigned char)0xF7);
4874 emit_int8((unsigned char)(0xC0 | encode));
4875 }
4876 emit_int32(imm32);
4877 }
4878
4879 void Assembler::testl(Register dst, Register src) {
4880 (void) prefix_and_encode(dst->encoding(), src->encoding());
4881 emit_arith(0x85, 0xC0, dst, src);
4882 }
4883
4884 void Assembler::testl(Register dst, Address src) {
4885 InstructionMark im(this);
4886 prefix(src, dst);
4887 emit_int8((unsigned char)0x85);
4888 emit_operand(dst, src);
4889 }
4890
4891 void Assembler::tzcntl(Register dst, Register src) {
4892 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4893 emit_int8((unsigned char)0xF3);
4894 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4895 emit_int8(0x0F);
4896 emit_int8((unsigned char)0xBC);
4897 emit_int8((unsigned char)0xC0 | encode);
4898 }
4899
4900 void Assembler::tzcntq(Register dst, Register src) {
4901 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4902 emit_int8((unsigned char)0xF3);
4903 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4904 emit_int8(0x0F);
4905 emit_int8((unsigned char)0xBC);
4906 emit_int8((unsigned char)(0xC0 | encode));
4907 }
4908
4909 void Assembler::ucomisd(XMMRegister dst, Address src) {
4910 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4911 InstructionMark im(this);
4912 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4913 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4914 attributes.set_rex_vex_w_reverted();
4915 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4916 emit_int8(0x2E);
4917 emit_operand(dst, src);
4918 }
4919
4920 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4921 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4922 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4923 attributes.set_rex_vex_w_reverted();
4924 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4925 emit_int8(0x2E);
4926 emit_int8((unsigned char)(0xC0 | encode));
4927 }
4928
4929 void Assembler::ucomiss(XMMRegister dst, Address src) {
4930 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4931 InstructionMark im(this);
4932 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4933 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4934 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4935 emit_int8(0x2E);
4936 emit_operand(dst, src);
4937 }
4938
4939 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4940 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4941 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4942 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4943 emit_int8(0x2E);
4944 emit_int8((unsigned char)(0xC0 | encode));
4945 }
4946
4947 void Assembler::xabort(int8_t imm8) {
4948 emit_int8((unsigned char)0xC6);
4949 emit_int8((unsigned char)0xF8);
4950 emit_int8((unsigned char)(imm8 & 0xFF));
4951 }
4952
4953 void Assembler::xaddb(Address dst, Register src) {
4954 InstructionMark im(this);
4955 prefix(dst, src, true);
4956 emit_int8(0x0F);
4957 emit_int8((unsigned char)0xC0);
4958 emit_operand(src, dst);
4959 }
4960
4961 void Assembler::xaddw(Address dst, Register src) {
4962 InstructionMark im(this);
4963 emit_int8(0x66);
4964 prefix(dst, src);
4965 emit_int8(0x0F);
4966 emit_int8((unsigned char)0xC1);
4967 emit_operand(src, dst);
4968 }
4969
4970 void Assembler::xaddl(Address dst, Register src) {
4971 InstructionMark im(this);
4972 prefix(dst, src);
4973 emit_int8(0x0F);
4974 emit_int8((unsigned char)0xC1);
4975 emit_operand(src, dst);
4976 }
4977
4978 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4979 InstructionMark im(this);
4980 relocate(rtype);
4981 if (abort.is_bound()) {
4982 address entry = target(abort);
4983 assert(entry != NULL, "abort entry NULL");
4984 intptr_t offset = entry - pc();
4985 emit_int8((unsigned char)0xC7);
4986 emit_int8((unsigned char)0xF8);
4987 emit_int32(offset - 6); // 2 opcode + 4 address
4988 } else {
4989 abort.add_patch_at(code(), locator());
4990 emit_int8((unsigned char)0xC7);
4991 emit_int8((unsigned char)0xF8);
4992 emit_int32(0);
4993 }
4994 }
4995
4996 void Assembler::xchgb(Register dst, Address src) { // xchg
4997 InstructionMark im(this);
4998 prefix(src, dst, true);
4999 emit_int8((unsigned char)0x86);
5000 emit_operand(dst, src);
5001 }
5002
5003 void Assembler::xchgw(Register dst, Address src) { // xchg
5004 InstructionMark im(this);
5005 emit_int8(0x66);
5006 prefix(src, dst);
5007 emit_int8((unsigned char)0x87);
5008 emit_operand(dst, src);
5009 }
5010
5011 void Assembler::xchgl(Register dst, Address src) { // xchg
5012 InstructionMark im(this);
5013 prefix(src, dst);
5014 emit_int8((unsigned char)0x87);
5015 emit_operand(dst, src);
5016 }
5017
5018 void Assembler::xchgl(Register dst, Register src) {
5019 int encode = prefix_and_encode(dst->encoding(), src->encoding());
5020 emit_int8((unsigned char)0x87);
5021 emit_int8((unsigned char)(0xC0 | encode));
5022 }
5023
5024 void Assembler::xend() {
5025 emit_int8((unsigned char)0x0F);
5026 emit_int8((unsigned char)0x01);
5027 emit_int8((unsigned char)0xD5);
5028 }
5029
5030 void Assembler::xgetbv() {
5031 emit_int8(0x0F);
5032 emit_int8(0x01);
5033 emit_int8((unsigned char)0xD0);
5034 }
5035
5036 void Assembler::xorl(Register dst, int32_t imm32) {
5037 prefix(dst);
5038 emit_arith(0x81, 0xF0, dst, imm32);
5039 }
5040
5041 void Assembler::xorl(Register dst, Address src) {
5042 InstructionMark im(this);
5043 prefix(src, dst);
5044 emit_int8(0x33);
5045 emit_operand(dst, src);
5046 }
5047
5048 void Assembler::xorl(Register dst, Register src) {
5049 (void) prefix_and_encode(dst->encoding(), src->encoding());
5050 emit_arith(0x33, 0xC0, dst, src);
5051 }
5052
5053 void Assembler::xorb(Register dst, Address src) {
5054 InstructionMark im(this);
5055 prefix(src, dst);
5056 emit_int8(0x32);
5057 emit_operand(dst, src);
5058 }
5059
5060 // AVX 3-operands scalar float-point arithmetic instructions
5061
5062 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
5063 assert(VM_Version::supports_avx(), "");
5064 InstructionMark im(this);
5065 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5066 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5067 attributes.set_rex_vex_w_reverted();
5068 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5069 emit_int8(0x58);
5070 emit_operand(dst, src);
5071 }
5072
5073 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5074 assert(VM_Version::supports_avx(), "");
5075 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5076 attributes.set_rex_vex_w_reverted();
5077 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5078 emit_int8(0x58);
5079 emit_int8((unsigned char)(0xC0 | encode));
5080 }
5081
5082 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
5083 assert(VM_Version::supports_avx(), "");
5084 InstructionMark im(this);
5085 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5086 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5087 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5088 emit_int8(0x58);
5089 emit_operand(dst, src);
5090 }
5091
5092 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5093 assert(VM_Version::supports_avx(), "");
5094 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5095 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5096 emit_int8(0x58);
5097 emit_int8((unsigned char)(0xC0 | encode));
5098 }
5099
5100 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
5101 assert(VM_Version::supports_avx(), "");
5102 InstructionMark im(this);
5103 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5104 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5105 attributes.set_rex_vex_w_reverted();
5106 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5107 emit_int8(0x5E);
5108 emit_operand(dst, src);
5109 }
5110
5111 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5112 assert(VM_Version::supports_avx(), "");
5113 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5114 attributes.set_rex_vex_w_reverted();
5115 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5116 emit_int8(0x5E);
5117 emit_int8((unsigned char)(0xC0 | encode));
5118 }
5119
5120 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
5121 assert(VM_Version::supports_avx(), "");
5122 InstructionMark im(this);
5123 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5124 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5125 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5126 emit_int8(0x5E);
5127 emit_operand(dst, src);
5128 }
5129
5130 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5131 assert(VM_Version::supports_avx(), "");
5132 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5133 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5134 emit_int8(0x5E);
5135 emit_int8((unsigned char)(0xC0 | encode));
5136 }
5137
5138 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5139 assert(VM_Version::supports_fma(), "");
5140 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5141 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5142 emit_int8((unsigned char)0xB9);
5143 emit_int8((unsigned char)(0xC0 | encode));
5144 }
5145
5146 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5147 assert(VM_Version::supports_fma(), "");
5148 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5149 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5150 emit_int8((unsigned char)0xB9);
5151 emit_int8((unsigned char)(0xC0 | encode));
5152 }
5153
5154 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
5155 assert(VM_Version::supports_avx(), "");
5156 InstructionMark im(this);
5157 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5158 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5159 attributes.set_rex_vex_w_reverted();
5160 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5161 emit_int8(0x59);
5162 emit_operand(dst, src);
5163 }
5164
5165 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5166 assert(VM_Version::supports_avx(), "");
5167 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5168 attributes.set_rex_vex_w_reverted();
5169 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5170 emit_int8(0x59);
5171 emit_int8((unsigned char)(0xC0 | encode));
5172 }
5173
5174 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
5175 assert(VM_Version::supports_avx(), "");
5176 InstructionMark im(this);
5177 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5178 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5179 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5180 emit_int8(0x59);
5181 emit_operand(dst, src);
5182 }
5183
5184 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5185 assert(VM_Version::supports_avx(), "");
5186 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5187 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5188 emit_int8(0x59);
5189 emit_int8((unsigned char)(0xC0 | encode));
5190 }
5191
5192 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
5193 assert(VM_Version::supports_avx(), "");
5194 InstructionMark im(this);
5195 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5196 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5197 attributes.set_rex_vex_w_reverted();
5198 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5199 emit_int8(0x5C);
5200 emit_operand(dst, src);
5201 }
5202
5203 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5204 assert(VM_Version::supports_avx(), "");
5205 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5206 attributes.set_rex_vex_w_reverted();
5207 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5208 emit_int8(0x5C);
5209 emit_int8((unsigned char)(0xC0 | encode));
5210 }
5211
5212 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
5213 assert(VM_Version::supports_avx(), "");
5214 InstructionMark im(this);
5215 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5216 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5217 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5218 emit_int8(0x5C);
5219 emit_operand(dst, src);
5220 }
5221
5222 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5223 assert(VM_Version::supports_avx(), "");
5224 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5225 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5226 emit_int8(0x5C);
5227 emit_int8((unsigned char)(0xC0 | encode));
5228 }
5229
5230 //====================VECTOR ARITHMETIC=====================================
5231
5232 // Float-point vector arithmetic
5233
5234 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
5235 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5236 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5237 attributes.set_rex_vex_w_reverted();
5238 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5239 emit_int8(0x58);
5240 emit_int8((unsigned char)(0xC0 | encode));
5241 }
5242
5243 void Assembler::addpd(XMMRegister dst, Address src) {
5244 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5245 InstructionMark im(this);
5246 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5247 attributes.set_rex_vex_w_reverted();
5248 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5249 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5250 emit_int8(0x58);
5251 emit_operand(dst, src);
5252 }
5253
5254
5255 void Assembler::addps(XMMRegister dst, XMMRegister src) {
5256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5257 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5258 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5259 emit_int8(0x58);
5260 emit_int8((unsigned char)(0xC0 | encode));
5261 }
5262
5263 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5264 assert(VM_Version::supports_avx(), "");
5265 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5266 attributes.set_rex_vex_w_reverted();
5267 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5268 emit_int8(0x58);
5269 emit_int8((unsigned char)(0xC0 | encode));
5270 }
5271
5272 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5273 assert(VM_Version::supports_avx(), "");
5274 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5275 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5276 emit_int8(0x58);
5277 emit_int8((unsigned char)(0xC0 | encode));
5278 }
5279
5280 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5281 assert(VM_Version::supports_avx(), "");
5282 InstructionMark im(this);
5283 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5284 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5285 attributes.set_rex_vex_w_reverted();
5286 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5287 emit_int8(0x58);
5288 emit_operand(dst, src);
5289 }
5290
5291 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5292 assert(VM_Version::supports_avx(), "");
5293 InstructionMark im(this);
5294 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5295 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5296 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5297 emit_int8(0x58);
5298 emit_operand(dst, src);
5299 }
5300
5301 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
5302 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5303 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5304 attributes.set_rex_vex_w_reverted();
5305 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5306 emit_int8(0x5C);
5307 emit_int8((unsigned char)(0xC0 | encode));
5308 }
5309
5310 void Assembler::subps(XMMRegister dst, XMMRegister src) {
5311 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5312 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5313 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5314 emit_int8(0x5C);
5315 emit_int8((unsigned char)(0xC0 | encode));
5316 }
5317
5318 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5319 assert(VM_Version::supports_avx(), "");
5320 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5321 attributes.set_rex_vex_w_reverted();
5322 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5323 emit_int8(0x5C);
5324 emit_int8((unsigned char)(0xC0 | encode));
5325 }
5326
5327 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5328 assert(VM_Version::supports_avx(), "");
5329 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5330 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5331 emit_int8(0x5C);
5332 emit_int8((unsigned char)(0xC0 | encode));
5333 }
5334
5335 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5336 assert(VM_Version::supports_avx(), "");
5337 InstructionMark im(this);
5338 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5339 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5340 attributes.set_rex_vex_w_reverted();
5341 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5342 emit_int8(0x5C);
5343 emit_operand(dst, src);
5344 }
5345
5346 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5347 assert(VM_Version::supports_avx(), "");
5348 InstructionMark im(this);
5349 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5350 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5351 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5352 emit_int8(0x5C);
5353 emit_operand(dst, src);
5354 }
5355
5356 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
5357 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5358 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5359 attributes.set_rex_vex_w_reverted();
5360 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5361 emit_int8(0x59);
5362 emit_int8((unsigned char)(0xC0 | encode));
5363 }
5364
5365 void Assembler::mulpd(XMMRegister dst, Address src) {
5366 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5367 InstructionMark im(this);
5368 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5369 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5370 attributes.set_rex_vex_w_reverted();
5371 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5372 emit_int8(0x59);
5373 emit_operand(dst, src);
5374 }
5375
5376 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
5377 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5378 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5379 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5380 emit_int8(0x59);
5381 emit_int8((unsigned char)(0xC0 | encode));
5382 }
5383
5384 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5385 assert(VM_Version::supports_avx(), "");
5386 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5387 attributes.set_rex_vex_w_reverted();
5388 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5389 emit_int8(0x59);
5390 emit_int8((unsigned char)(0xC0 | encode));
5391 }
5392
5393 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5394 assert(VM_Version::supports_avx(), "");
5395 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5396 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5397 emit_int8(0x59);
5398 emit_int8((unsigned char)(0xC0 | encode));
5399 }
5400
5401 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5402 assert(VM_Version::supports_avx(), "");
5403 InstructionMark im(this);
5404 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5405 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5406 attributes.set_rex_vex_w_reverted();
5407 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5408 emit_int8(0x59);
5409 emit_operand(dst, src);
5410 }
5411
5412 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5413 assert(VM_Version::supports_avx(), "");
5414 InstructionMark im(this);
5415 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5416 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5417 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5418 emit_int8(0x59);
5419 emit_operand(dst, src);
5420 }
5421
5422 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5423 assert(VM_Version::supports_fma(), "");
5424 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5425 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5426 emit_int8((unsigned char)0xB8);
5427 emit_int8((unsigned char)(0xC0 | encode));
5428 }
5429
5430 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5431 assert(VM_Version::supports_fma(), "");
5432 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5433 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5434 emit_int8((unsigned char)0xB8);
5435 emit_int8((unsigned char)(0xC0 | encode));
5436 }
5437
5438 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5439 assert(VM_Version::supports_fma(), "");
5440 InstructionMark im(this);
5441 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5442 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5443 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5444 emit_int8((unsigned char)0xB8);
5445 emit_operand(dst, src2);
5446 }
5447
5448 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5449 assert(VM_Version::supports_fma(), "");
5450 InstructionMark im(this);
5451 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5452 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5453 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5454 emit_int8((unsigned char)0xB8);
5455 emit_operand(dst, src2);
5456 }
5457
5458 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5459 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5460 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5461 attributes.set_rex_vex_w_reverted();
5462 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5463 emit_int8(0x5E);
5464 emit_int8((unsigned char)(0xC0 | encode));
5465 }
5466
5467 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5468 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5469 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5470 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5471 emit_int8(0x5E);
5472 emit_int8((unsigned char)(0xC0 | encode));
5473 }
5474
5475 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5476 assert(VM_Version::supports_avx(), "");
5477 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5478 attributes.set_rex_vex_w_reverted();
5479 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5480 emit_int8(0x5E);
5481 emit_int8((unsigned char)(0xC0 | encode));
5482 }
5483
5484 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5485 assert(VM_Version::supports_avx(), "");
5486 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5487 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5488 emit_int8(0x5E);
5489 emit_int8((unsigned char)(0xC0 | encode));
5490 }
5491
5492 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5493 assert(VM_Version::supports_avx(), "");
5494 InstructionMark im(this);
5495 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5496 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5497 attributes.set_rex_vex_w_reverted();
5498 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5499 emit_int8(0x5E);
5500 emit_operand(dst, src);
5501 }
5502
5503 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5504 assert(VM_Version::supports_avx(), "");
5505 InstructionMark im(this);
5506 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5507 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5508 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5509 emit_int8(0x5E);
5510 emit_operand(dst, src);
5511 }
5512
5513 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
5514 assert(VM_Version::supports_avx(), "");
5515 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5516 attributes.set_rex_vex_w_reverted();
5517 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5518 emit_int8(0x51);
5519 emit_int8((unsigned char)(0xC0 | encode));
5520 }
5521
5522 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
5523 assert(VM_Version::supports_avx(), "");
5524 InstructionMark im(this);
5525 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5526 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5527 attributes.set_rex_vex_w_reverted();
5528 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5529 emit_int8(0x51);
5530 emit_operand(dst, src);
5531 }
5532
5533 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
5534 assert(VM_Version::supports_avx(), "");
5535 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5536 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5537 emit_int8(0x51);
5538 emit_int8((unsigned char)(0xC0 | encode));
5539 }
5540
5541 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
5542 assert(VM_Version::supports_avx(), "");
5543 InstructionMark im(this);
5544 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5545 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5546 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5547 emit_int8(0x51);
5548 emit_operand(dst, src);
5549 }
5550
5551 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
5552 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5553 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5554 attributes.set_rex_vex_w_reverted();
5555 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5556 emit_int8(0x54);
5557 emit_int8((unsigned char)(0xC0 | encode));
5558 }
5559
5560 void Assembler::andps(XMMRegister dst, XMMRegister src) {
5561 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5562 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5563 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5564 emit_int8(0x54);
5565 emit_int8((unsigned char)(0xC0 | encode));
5566 }
5567
5568 void Assembler::andps(XMMRegister dst, Address src) {
5569 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5570 InstructionMark im(this);
5571 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5572 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5573 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5574 emit_int8(0x54);
5575 emit_operand(dst, src);
5576 }
5577
5578 void Assembler::andpd(XMMRegister dst, Address src) {
5579 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5580 InstructionMark im(this);
5581 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5582 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5583 attributes.set_rex_vex_w_reverted();
5584 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5585 emit_int8(0x54);
5586 emit_operand(dst, src);
5587 }
5588
5589 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5590 assert(VM_Version::supports_avx(), "");
5591 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5592 attributes.set_rex_vex_w_reverted();
5593 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5594 emit_int8(0x54);
5595 emit_int8((unsigned char)(0xC0 | encode));
5596 }
5597
5598 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5599 assert(VM_Version::supports_avx(), "");
5600 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5601 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5602 emit_int8(0x54);
5603 emit_int8((unsigned char)(0xC0 | encode));
5604 }
5605
5606 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5607 assert(VM_Version::supports_avx(), "");
5608 InstructionMark im(this);
5609 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5610 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5611 attributes.set_rex_vex_w_reverted();
5612 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5613 emit_int8(0x54);
5614 emit_operand(dst, src);
5615 }
5616
5617 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5618 assert(VM_Version::supports_avx(), "");
5619 InstructionMark im(this);
5620 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5621 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5622 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5623 emit_int8(0x54);
5624 emit_operand(dst, src);
5625 }
5626
5627 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
5628 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5629 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5630 attributes.set_rex_vex_w_reverted();
5631 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5632 emit_int8(0x15);
5633 emit_int8((unsigned char)(0xC0 | encode));
5634 }
5635
5636 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
5637 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5638 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5639 attributes.set_rex_vex_w_reverted();
5640 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5641 emit_int8(0x14);
5642 emit_int8((unsigned char)(0xC0 | encode));
5643 }
5644
5645 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
5646 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5647 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5648 attributes.set_rex_vex_w_reverted();
5649 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5650 emit_int8(0x57);
5651 emit_int8((unsigned char)(0xC0 | encode));
5652 }
5653
5654 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
5655 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5656 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5657 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5658 emit_int8(0x57);
5659 emit_int8((unsigned char)(0xC0 | encode));
5660 }
5661
5662 void Assembler::xorpd(XMMRegister dst, Address src) {
5663 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5664 InstructionMark im(this);
5665 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5666 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5667 attributes.set_rex_vex_w_reverted();
5668 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5669 emit_int8(0x57);
5670 emit_operand(dst, src);
5671 }
5672
5673 void Assembler::xorps(XMMRegister dst, Address src) {
5674 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5675 InstructionMark im(this);
5676 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5677 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5678 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5679 emit_int8(0x57);
5680 emit_operand(dst, src);
5681 }
5682
5683 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5684 assert(VM_Version::supports_avx(), "");
5685 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5686 attributes.set_rex_vex_w_reverted();
5687 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5688 emit_int8(0x57);
5689 emit_int8((unsigned char)(0xC0 | encode));
5690 }
5691
5692 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5693 assert(VM_Version::supports_avx(), "");
5694 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5695 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5696 emit_int8(0x57);
5697 emit_int8((unsigned char)(0xC0 | encode));
5698 }
5699
5700 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5701 assert(VM_Version::supports_avx(), "");
5702 InstructionMark im(this);
5703 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5704 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5705 attributes.set_rex_vex_w_reverted();
5706 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5707 emit_int8(0x57);
5708 emit_operand(dst, src);
5709 }
5710
5711 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5712 assert(VM_Version::supports_avx(), "");
5713 InstructionMark im(this);
5714 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5715 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5716 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5717 emit_int8(0x57);
5718 emit_operand(dst, src);
5719 }
5720
5721 // Integer vector arithmetic
5722 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5723 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5724 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5725 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5726 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5727 emit_int8(0x01);
5728 emit_int8((unsigned char)(0xC0 | encode));
5729 }
5730
5731 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5732 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5733 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5734 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5735 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5736 emit_int8(0x02);
5737 emit_int8((unsigned char)(0xC0 | encode));
5738 }
5739
5740 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5741 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5742 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5743 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5744 emit_int8((unsigned char)0xFC);
5745 emit_int8((unsigned char)(0xC0 | encode));
5746 }
5747
5748 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5749 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5750 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5751 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5752 emit_int8((unsigned char)0xFD);
5753 emit_int8((unsigned char)(0xC0 | encode));
5754 }
5755
5756 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5757 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5758 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5759 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5760 emit_int8((unsigned char)0xFE);
5761 emit_int8((unsigned char)(0xC0 | encode));
5762 }
5763
5764 void Assembler::paddd(XMMRegister dst, Address src) {
5765 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5766 InstructionMark im(this);
5767 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5768 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5769 emit_int8((unsigned char)0xFE);
5770 emit_operand(dst, src);
5771 }
5772
5773 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5774 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5775 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5776 attributes.set_rex_vex_w_reverted();
5777 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5778 emit_int8((unsigned char)0xD4);
5779 emit_int8((unsigned char)(0xC0 | encode));
5780 }
5781
5782 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5783 assert(VM_Version::supports_sse3(), "");
5784 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5785 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5786 emit_int8(0x01);
5787 emit_int8((unsigned char)(0xC0 | encode));
5788 }
5789
5790 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5791 assert(VM_Version::supports_sse3(), "");
5792 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5793 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5794 emit_int8(0x02);
5795 emit_int8((unsigned char)(0xC0 | encode));
5796 }
5797
5798 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5799 assert(UseAVX > 0, "requires some form of AVX");
5800 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5801 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5802 emit_int8((unsigned char)0xFC);
5803 emit_int8((unsigned char)(0xC0 | encode));
5804 }
5805
5806 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5807 assert(UseAVX > 0, "requires some form of AVX");
5808 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5809 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5810 emit_int8((unsigned char)0xFD);
5811 emit_int8((unsigned char)(0xC0 | encode));
5812 }
5813
5814 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5815 assert(UseAVX > 0, "requires some form of AVX");
5816 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5817 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5818 emit_int8((unsigned char)0xFE);
5819 emit_int8((unsigned char)(0xC0 | encode));
5820 }
5821
5822 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5823 assert(UseAVX > 0, "requires some form of AVX");
5824 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5825 attributes.set_rex_vex_w_reverted();
5826 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5827 emit_int8((unsigned char)0xD4);
5828 emit_int8((unsigned char)(0xC0 | encode));
5829 }
5830
5831 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5832 assert(UseAVX > 0, "requires some form of AVX");
5833 InstructionMark im(this);
5834 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5835 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5836 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5837 emit_int8((unsigned char)0xFC);
5838 emit_operand(dst, src);
5839 }
5840
5841 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5842 assert(UseAVX > 0, "requires some form of AVX");
5843 InstructionMark im(this);
5844 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5845 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5846 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5847 emit_int8((unsigned char)0xFD);
5848 emit_operand(dst, src);
5849 }
5850
5851 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5852 assert(UseAVX > 0, "requires some form of AVX");
5853 InstructionMark im(this);
5854 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5855 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5856 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5857 emit_int8((unsigned char)0xFE);
5858 emit_operand(dst, src);
5859 }
5860
5861 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5862 assert(UseAVX > 0, "requires some form of AVX");
5863 InstructionMark im(this);
5864 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5865 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5866 attributes.set_rex_vex_w_reverted();
5867 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5868 emit_int8((unsigned char)0xD4);
5869 emit_operand(dst, src);
5870 }
5871
5872 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5873 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5874 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5875 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5876 emit_int8((unsigned char)0xF8);
5877 emit_int8((unsigned char)(0xC0 | encode));
5878 }
5879
5880 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5881 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5882 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5883 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5884 emit_int8((unsigned char)0xF9);
5885 emit_int8((unsigned char)(0xC0 | encode));
5886 }
5887
5888 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5889 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5890 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5891 emit_int8((unsigned char)0xFA);
5892 emit_int8((unsigned char)(0xC0 | encode));
5893 }
5894
5895 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5896 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5897 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5898 attributes.set_rex_vex_w_reverted();
5899 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5900 emit_int8((unsigned char)0xFB);
5901 emit_int8((unsigned char)(0xC0 | encode));
5902 }
5903
5904 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5905 assert(UseAVX > 0, "requires some form of AVX");
5906 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5907 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5908 emit_int8((unsigned char)0xF8);
5909 emit_int8((unsigned char)(0xC0 | encode));
5910 }
5911
5912 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5913 assert(UseAVX > 0, "requires some form of AVX");
5914 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5915 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5916 emit_int8((unsigned char)0xF9);
5917 emit_int8((unsigned char)(0xC0 | encode));
5918 }
5919
5920 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5921 assert(UseAVX > 0, "requires some form of AVX");
5922 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5923 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5924 emit_int8((unsigned char)0xFA);
5925 emit_int8((unsigned char)(0xC0 | encode));
5926 }
5927
5928 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5929 assert(UseAVX > 0, "requires some form of AVX");
5930 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5931 attributes.set_rex_vex_w_reverted();
5932 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5933 emit_int8((unsigned char)0xFB);
5934 emit_int8((unsigned char)(0xC0 | encode));
5935 }
5936
5937 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5938 assert(UseAVX > 0, "requires some form of AVX");
5939 InstructionMark im(this);
5940 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5941 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5942 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5943 emit_int8((unsigned char)0xF8);
5944 emit_operand(dst, src);
5945 }
5946
5947 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5948 assert(UseAVX > 0, "requires some form of AVX");
5949 InstructionMark im(this);
5950 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5951 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5952 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5953 emit_int8((unsigned char)0xF9);
5954 emit_operand(dst, src);
5955 }
5956
5957 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5958 assert(UseAVX > 0, "requires some form of AVX");
5959 InstructionMark im(this);
5960 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5961 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5962 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5963 emit_int8((unsigned char)0xFA);
5964 emit_operand(dst, src);
5965 }
5966
5967 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5968 assert(UseAVX > 0, "requires some form of AVX");
5969 InstructionMark im(this);
5970 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5971 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5972 attributes.set_rex_vex_w_reverted();
5973 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5974 emit_int8((unsigned char)0xFB);
5975 emit_operand(dst, src);
5976 }
5977
5978 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5979 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5980 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5981 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5982 emit_int8((unsigned char)0xD5);
5983 emit_int8((unsigned char)(0xC0 | encode));
5984 }
5985
5986 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5987 assert(VM_Version::supports_sse4_1(), "");
5988 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5989 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5990 emit_int8(0x40);
5991 emit_int8((unsigned char)(0xC0 | encode));
5992 }
5993
5994 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5995 assert(UseAVX > 0, "requires some form of AVX");
5996 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5997 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5998 emit_int8((unsigned char)0xD5);
5999 emit_int8((unsigned char)(0xC0 | encode));
6000 }
6001
6002 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6003 assert(UseAVX > 0, "requires some form of AVX");
6004 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6005 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6006 emit_int8(0x40);
6007 emit_int8((unsigned char)(0xC0 | encode));
6008 }
6009
6010 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6011 assert(UseAVX > 2, "requires some form of EVEX");
6012 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
6013 attributes.set_is_evex_instruction();
6014 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6015 emit_int8(0x40);
6016 emit_int8((unsigned char)(0xC0 | encode));
6017 }
6018
6019 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6020 assert(UseAVX > 0, "requires some form of AVX");
6021 InstructionMark im(this);
6022 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6023 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
6024 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6025 emit_int8((unsigned char)0xD5);
6026 emit_operand(dst, src);
6027 }
6028
6029 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6030 assert(UseAVX > 0, "requires some form of AVX");
6031 InstructionMark im(this);
6032 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6033 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6034 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6035 emit_int8(0x40);
6036 emit_operand(dst, src);
6037 }
6038
6039 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6040 assert(UseAVX > 2, "requires some form of EVEX");
6041 InstructionMark im(this);
6042 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
6043 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6044 attributes.set_is_evex_instruction();
6045 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6046 emit_int8(0x40);
6047 emit_operand(dst, src);
6048 }
6049
6050 // Shift packed integers left by specified number of bits.
6051 void Assembler::psllw(XMMRegister dst, int shift) {
6052 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6053 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6054 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
6055 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6056 emit_int8(0x71);
6057 emit_int8((unsigned char)(0xC0 | encode));
6058 emit_int8(shift & 0xFF);
6059 }
6060
6061 void Assembler::pslld(XMMRegister dst, int shift) {
6062 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6063 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6064 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
6065 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6066 emit_int8(0x72);
6067 emit_int8((unsigned char)(0xC0 | encode));
6068 emit_int8(shift & 0xFF);
6069 }
6070
6071 void Assembler::psllq(XMMRegister dst, int shift) {
6072 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6073 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6074 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
6075 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6076 emit_int8(0x73);
6077 emit_int8((unsigned char)(0xC0 | encode));
6078 emit_int8(shift & 0xFF);
6079 }
6080
6081 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
6082 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6083 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6084 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6085 emit_int8((unsigned char)0xF1);
6086 emit_int8((unsigned char)(0xC0 | encode));
6087 }
6088
6089 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
6090 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6091 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6092 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6093 emit_int8((unsigned char)0xF2);
6094 emit_int8((unsigned char)(0xC0 | encode));
6095 }
6096
6097 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
6098 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6099 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6100 attributes.set_rex_vex_w_reverted();
6101 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6102 emit_int8((unsigned char)0xF3);
6103 emit_int8((unsigned char)(0xC0 | encode));
6104 }
6105
6106 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6107 assert(UseAVX > 0, "requires some form of AVX");
6108 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6109 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
6110 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6111 emit_int8(0x71);
6112 emit_int8((unsigned char)(0xC0 | encode));
6113 emit_int8(shift & 0xFF);
6114 }
6115
6116 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6117 assert(UseAVX > 0, "requires some form of AVX");
6118 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6119 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6120 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
6121 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6122 emit_int8(0x72);
6123 emit_int8((unsigned char)(0xC0 | encode));
6124 emit_int8(shift & 0xFF);
6125 }
6126
6127 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6128 assert(UseAVX > 0, "requires some form of AVX");
6129 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6130 attributes.set_rex_vex_w_reverted();
6131 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
6132 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6133 emit_int8(0x73);
6134 emit_int8((unsigned char)(0xC0 | encode));
6135 emit_int8(shift & 0xFF);
6136 }
6137
6138 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6139 assert(UseAVX > 0, "requires some form of AVX");
6140 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6141 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6142 emit_int8((unsigned char)0xF1);
6143 emit_int8((unsigned char)(0xC0 | encode));
6144 }
6145
6146 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6147 assert(UseAVX > 0, "requires some form of AVX");
6148 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6149 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6150 emit_int8((unsigned char)0xF2);
6151 emit_int8((unsigned char)(0xC0 | encode));
6152 }
6153
6154 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6155 assert(UseAVX > 0, "requires some form of AVX");
6156 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6157 attributes.set_rex_vex_w_reverted();
6158 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6159 emit_int8((unsigned char)0xF3);
6160 emit_int8((unsigned char)(0xC0 | encode));
6161 }
6162
6163 // Shift packed integers logically right by specified number of bits.
6164 void Assembler::psrlw(XMMRegister dst, int shift) {
6165 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6166 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6167 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6168 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6169 emit_int8(0x71);
6170 emit_int8((unsigned char)(0xC0 | encode));
6171 emit_int8(shift & 0xFF);
6172 }
6173
6174 void Assembler::psrld(XMMRegister dst, int shift) {
6175 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6176 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6177 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6178 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6179 emit_int8(0x72);
6180 emit_int8((unsigned char)(0xC0 | encode));
6181 emit_int8(shift & 0xFF);
6182 }
6183
6184 void Assembler::psrlq(XMMRegister dst, int shift) {
6185 // Do not confuse it with psrldq SSE2 instruction which
6186 // shifts 128 bit value in xmm register by number of bytes.
6187 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6188 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6189 attributes.set_rex_vex_w_reverted();
6190 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6191 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6192 emit_int8(0x73);
6193 emit_int8((unsigned char)(0xC0 | encode));
6194 emit_int8(shift & 0xFF);
6195 }
6196
6197 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
6198 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6199 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6200 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6201 emit_int8((unsigned char)0xD1);
6202 emit_int8((unsigned char)(0xC0 | encode));
6203 }
6204
6205 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
6206 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6207 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6208 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6209 emit_int8((unsigned char)0xD2);
6210 emit_int8((unsigned char)(0xC0 | encode));
6211 }
6212
6213 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
6214 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6215 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6216 attributes.set_rex_vex_w_reverted();
6217 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6218 emit_int8((unsigned char)0xD3);
6219 emit_int8((unsigned char)(0xC0 | encode));
6220 }
6221
6222 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6223 assert(UseAVX > 0, "requires some form of AVX");
6224 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6225 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6226 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6227 emit_int8(0x71);
6228 emit_int8((unsigned char)(0xC0 | encode));
6229 emit_int8(shift & 0xFF);
6230 }
6231
6232 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6233 assert(UseAVX > 0, "requires some form of AVX");
6234 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6235 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6236 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6237 emit_int8(0x72);
6238 emit_int8((unsigned char)(0xC0 | encode));
6239 emit_int8(shift & 0xFF);
6240 }
6241
6242 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6243 assert(UseAVX > 0, "requires some form of AVX");
6244 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6245 attributes.set_rex_vex_w_reverted();
6246 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6247 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6248 emit_int8(0x73);
6249 emit_int8((unsigned char)(0xC0 | encode));
6250 emit_int8(shift & 0xFF);
6251 }
6252
6253 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6254 assert(UseAVX > 0, "requires some form of AVX");
6255 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6256 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6257 emit_int8((unsigned char)0xD1);
6258 emit_int8((unsigned char)(0xC0 | encode));
6259 }
6260
6261 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6262 assert(UseAVX > 0, "requires some form of AVX");
6263 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6264 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6265 emit_int8((unsigned char)0xD2);
6266 emit_int8((unsigned char)(0xC0 | encode));
6267 }
6268
6269 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6270 assert(UseAVX > 0, "requires some form of AVX");
6271 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6272 attributes.set_rex_vex_w_reverted();
6273 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6274 emit_int8((unsigned char)0xD3);
6275 emit_int8((unsigned char)(0xC0 | encode));
6276 }
6277
6278 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6279 assert(VM_Version::supports_avx512bw(), "");
6280 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6281 attributes.set_is_evex_instruction();
6282 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6283 emit_int8(0x10);
6284 emit_int8((unsigned char)(0xC0 | encode));
6285 }
6286
6287 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6288 assert(VM_Version::supports_avx512bw(), "");
6289 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6290 attributes.set_is_evex_instruction();
6291 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6292 emit_int8(0x12);
6293 emit_int8((unsigned char)(0xC0 | encode));
6294 }
6295
6296 // Shift packed integers arithmetically right by specified number of bits.
6297 void Assembler::psraw(XMMRegister dst, int shift) {
6298 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6299 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6300 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6301 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6302 emit_int8(0x71);
6303 emit_int8((unsigned char)(0xC0 | encode));
6304 emit_int8(shift & 0xFF);
6305 }
6306
6307 void Assembler::psrad(XMMRegister dst, int shift) {
6308 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6309 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6310 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
6311 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6312 emit_int8(0x72);
6313 emit_int8((unsigned char)(0xC0 | encode));
6314 emit_int8(shift & 0xFF);
6315 }
6316
6317 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
6318 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6319 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6320 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6321 emit_int8((unsigned char)0xE1);
6322 emit_int8((unsigned char)(0xC0 | encode));
6323 }
6324
6325 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
6326 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6327 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6328 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6329 emit_int8((unsigned char)0xE2);
6330 emit_int8((unsigned char)(0xC0 | encode));
6331 }
6332
6333 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6334 assert(UseAVX > 0, "requires some form of AVX");
6335 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6336 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6337 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6338 emit_int8(0x71);
6339 emit_int8((unsigned char)(0xC0 | encode));
6340 emit_int8(shift & 0xFF);
6341 }
6342
6343 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6344 assert(UseAVX > 0, "requires some form of AVX");
6345 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6346 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6347 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6348 emit_int8(0x72);
6349 emit_int8((unsigned char)(0xC0 | encode));
6350 emit_int8(shift & 0xFF);
6351 }
6352
6353 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6354 assert(UseAVX > 0, "requires some form of AVX");
6355 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6356 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6357 emit_int8((unsigned char)0xE1);
6358 emit_int8((unsigned char)(0xC0 | encode));
6359 }
6360
6361 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6362 assert(UseAVX > 0, "requires some form of AVX");
6363 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6364 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6365 emit_int8((unsigned char)0xE2);
6366 emit_int8((unsigned char)(0xC0 | encode));
6367 }
6368
6369 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6370 assert(UseAVX > 2, "requires AVX512");
6371 assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl");
6372 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6373 attributes.set_is_evex_instruction();
6374 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6375 emit_int8((unsigned char)0x72);
6376 emit_int8((unsigned char)(0xC0 | encode));
6377 emit_int8(shift & 0xFF);
6378 }
6379
6380 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6381 assert(UseAVX > 2, "requires AVX512");
6382 assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl");
6383 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6384 attributes.set_is_evex_instruction();
6385 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6386 emit_int8((unsigned char)0xE2);
6387 emit_int8((unsigned char)(0xC0 | encode));
6388 }
6389
6390 // logical operations packed integers
6391 void Assembler::pand(XMMRegister dst, XMMRegister src) {
6392 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6393 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6394 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6395 emit_int8((unsigned char)0xDB);
6396 emit_int8((unsigned char)(0xC0 | encode));
6397 }
6398
6399 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6400 assert(UseAVX > 0, "requires some form of AVX");
6401 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6402 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6403 emit_int8((unsigned char)0xDB);
6404 emit_int8((unsigned char)(0xC0 | encode));
6405 }
6406
6407 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6408 assert(UseAVX > 0, "requires some form of AVX");
6409 InstructionMark im(this);
6410 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6411 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6412 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6413 emit_int8((unsigned char)0xDB);
6414 emit_operand(dst, src);
6415 }
6416
6417 void Assembler::vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6418 assert(VM_Version::supports_evex(), "");
6419 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6420 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6421 emit_int8((unsigned char)0xDB);
6422 emit_int8((unsigned char)(0xC0 | encode));
6423 }
6424
6425
6426 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
6427 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6428 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6429 attributes.set_rex_vex_w_reverted();
6430 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6431 emit_int8((unsigned char)0xDF);
6432 emit_int8((unsigned char)(0xC0 | encode));
6433 }
6434
6435 void Assembler::vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6436 assert(UseAVX > 0, "requires some form of AVX");
6437 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6438 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6439 emit_int8((unsigned char)0xDF);
6440 emit_int8((unsigned char)(0xC0 | encode));
6441 }
6442
6443
6444 void Assembler::por(XMMRegister dst, XMMRegister src) {
6445 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6446 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6447 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6448 emit_int8((unsigned char)0xEB);
6449 emit_int8((unsigned char)(0xC0 | encode));
6450 }
6451
6452 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6453 assert(UseAVX > 0, "requires some form of AVX");
6454 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6455 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6456 emit_int8((unsigned char)0xEB);
6457 emit_int8((unsigned char)(0xC0 | encode));
6458 }
6459
6460 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6461 assert(UseAVX > 0, "requires some form of AVX");
6462 InstructionMark im(this);
6463 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6464 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6465 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6466 emit_int8((unsigned char)0xEB);
6467 emit_operand(dst, src);
6468 }
6469
6470 void Assembler::vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6471 assert(VM_Version::supports_evex(), "");
6472 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6473 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6474 emit_int8((unsigned char)0xEB);
6475 emit_int8((unsigned char)(0xC0 | encode));
6476 }
6477
6478
6479 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
6480 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6481 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6482 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6483 emit_int8((unsigned char)0xEF);
6484 emit_int8((unsigned char)(0xC0 | encode));
6485 }
6486
6487 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6488 assert(UseAVX > 0, "requires some form of AVX");
6489 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6490 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6491 emit_int8((unsigned char)0xEF);
6492 emit_int8((unsigned char)(0xC0 | encode));
6493 }
6494
6495 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6496 assert(UseAVX > 0, "requires some form of AVX");
6497 InstructionMark im(this);
6498 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6499 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6500 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6501 emit_int8((unsigned char)0xEF);
6502 emit_operand(dst, src);
6503 }
6504
6505 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6506 assert(VM_Version::supports_evex(), "requires EVEX support");
6507 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6508 attributes.set_is_evex_instruction();
6509 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6510 emit_int8((unsigned char)0xEF);
6511 emit_int8((unsigned char)(0xC0 | encode));
6512 }
6513
6514 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6515 assert(VM_Version::supports_evex(), "requires EVEX support");
6516 assert(dst != xnoreg, "sanity");
6517 InstructionMark im(this);
6518 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6519 attributes.set_is_evex_instruction();
6520 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6521 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6522 emit_int8((unsigned char)0xEF);
6523 emit_operand(dst, src);
6524 }
6525
6526
6527 // vinserti forms
6528
6529 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6530 assert(VM_Version::supports_avx2(), "");
6531 assert(imm8 <= 0x01, "imm8: %u", imm8);
6532 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6533 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6534 emit_int8(0x38);
6535 emit_int8((unsigned char)(0xC0 | encode));
6536 // 0x00 - insert into lower 128 bits
6537 // 0x01 - insert into upper 128 bits
6538 emit_int8(imm8 & 0x01);
6539 }
6540
6541 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6542 assert(VM_Version::supports_avx2(), "");
6543 assert(dst != xnoreg, "sanity");
6544 assert(imm8 <= 0x01, "imm8: %u", imm8);
6545 InstructionMark im(this);
6546 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6547 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6548 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6549 emit_int8(0x38);
6550 emit_operand(dst, src);
6551 // 0x00 - insert into lower 128 bits
6552 // 0x01 - insert into upper 128 bits
6553 emit_int8(imm8 & 0x01);
6554 }
6555
6556 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6557 assert(VM_Version::supports_evex(), "");
6558 assert(imm8 <= 0x03, "imm8: %u", imm8);
6559 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6560 attributes.set_is_evex_instruction();
6561 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6562 emit_int8(0x38);
6563 emit_int8((unsigned char)(0xC0 | encode));
6564 // 0x00 - insert into q0 128 bits (0..127)
6565 // 0x01 - insert into q1 128 bits (128..255)
6566 // 0x02 - insert into q2 128 bits (256..383)
6567 // 0x03 - insert into q3 128 bits (384..511)
6568 emit_int8(imm8 & 0x03);
6569 }
6570
6571 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6572 assert(VM_Version::supports_avx(), "");
6573 assert(dst != xnoreg, "sanity");
6574 assert(imm8 <= 0x03, "imm8: %u", imm8);
6575 InstructionMark im(this);
6576 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6577 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6578 attributes.set_is_evex_instruction();
6579 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6580 emit_int8(0x18);
6581 emit_operand(dst, src);
6582 // 0x00 - insert into q0 128 bits (0..127)
6583 // 0x01 - insert into q1 128 bits (128..255)
6584 // 0x02 - insert into q2 128 bits (256..383)
6585 // 0x03 - insert into q3 128 bits (384..511)
6586 emit_int8(imm8 & 0x03);
6587 }
6588
6589 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6590 assert(VM_Version::supports_evex(), "");
6591 assert(imm8 <= 0x01, "imm8: %u", imm8);
6592 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6593 attributes.set_is_evex_instruction();
6594 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6595 emit_int8(0x3A);
6596 emit_int8((unsigned char)(0xC0 | encode));
6597 // 0x00 - insert into lower 256 bits
6598 // 0x01 - insert into upper 256 bits
6599 emit_int8(imm8 & 0x01);
6600 }
6601
6602
6603 // vinsertf forms
6604
6605 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6606 assert(VM_Version::supports_avx(), "");
6607 assert(imm8 <= 0x01, "imm8: %u", imm8);
6608 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6609 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6610 emit_int8(0x18);
6611 emit_int8((unsigned char)(0xC0 | encode));
6612 // 0x00 - insert into lower 128 bits
6613 // 0x01 - insert into upper 128 bits
6614 emit_int8(imm8 & 0x01);
6615 }
6616
6617 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6618 assert(VM_Version::supports_avx(), "");
6619 assert(dst != xnoreg, "sanity");
6620 assert(imm8 <= 0x01, "imm8: %u", imm8);
6621 InstructionMark im(this);
6622 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6623 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6624 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6625 emit_int8(0x18);
6626 emit_operand(dst, src);
6627 // 0x00 - insert into lower 128 bits
6628 // 0x01 - insert into upper 128 bits
6629 emit_int8(imm8 & 0x01);
6630 }
6631
6632 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6633 assert(VM_Version::supports_avx2(), "");
6634 assert(imm8 <= 0x03, "imm8: %u", imm8);
6635 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6636 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6637 emit_int8(0x18);
6638 emit_int8((unsigned char)(0xC0 | encode));
6639 // 0x00 - insert into q0 128 bits (0..127)
6640 // 0x01 - insert into q1 128 bits (128..255)
6641 // 0x02 - insert into q0 128 bits (256..383)
6642 // 0x03 - insert into q1 128 bits (384..512)
6643 emit_int8(imm8 & 0x03);
6644 }
6645
6646 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6647 assert(VM_Version::supports_avx(), "");
6648 assert(dst != xnoreg, "sanity");
6649 assert(imm8 <= 0x03, "imm8: %u", imm8);
6650 InstructionMark im(this);
6651 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6652 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6653 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6654 emit_int8(0x18);
6655 emit_operand(dst, src);
6656 // 0x00 - insert into q0 128 bits (0..127)
6657 // 0x01 - insert into q1 128 bits (128..255)
6658 // 0x02 - insert into q0 128 bits (256..383)
6659 // 0x03 - insert into q1 128 bits (384..512)
6660 emit_int8(imm8 & 0x03);
6661 }
6662
6663 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6664 assert(VM_Version::supports_evex(), "");
6665 assert(imm8 <= 0x01, "imm8: %u", imm8);
6666 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6667 attributes.set_is_evex_instruction();
6668 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6669 emit_int8(0x1A);
6670 emit_int8((unsigned char)(0xC0 | encode));
6671 // 0x00 - insert into lower 256 bits
6672 // 0x01 - insert into upper 256 bits
6673 emit_int8(imm8 & 0x01);
6674 }
6675
6676 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6677 assert(VM_Version::supports_evex(), "");
6678 assert(dst != xnoreg, "sanity");
6679 assert(imm8 <= 0x01, "imm8: %u", imm8);
6680 InstructionMark im(this);
6681 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6682 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6683 attributes.set_is_evex_instruction();
6684 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6685 emit_int8(0x1A);
6686 emit_operand(dst, src);
6687 // 0x00 - insert into lower 256 bits
6688 // 0x01 - insert into upper 256 bits
6689 emit_int8(imm8 & 0x01);
6690 }
6691
6692
6693 // vextracti forms
6694
6695 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6696 assert(VM_Version::supports_avx2(), "");
6697 assert(imm8 <= 0x01, "imm8: %u", imm8);
6698 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6699 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6700 emit_int8(0x39);
6701 emit_int8((unsigned char)(0xC0 | encode));
6702 // 0x00 - extract from lower 128 bits
6703 // 0x01 - extract from upper 128 bits
6704 emit_int8(imm8 & 0x01);
6705 }
6706
6707 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
6708 assert(VM_Version::supports_avx2(), "");
6709 assert(src != xnoreg, "sanity");
6710 assert(imm8 <= 0x01, "imm8: %u", imm8);
6711 InstructionMark im(this);
6712 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6713 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6714 attributes.reset_is_clear_context();
6715 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6716 emit_int8(0x39);
6717 emit_operand(src, dst);
6718 // 0x00 - extract from lower 128 bits
6719 // 0x01 - extract from upper 128 bits
6720 emit_int8(imm8 & 0x01);
6721 }
6722
6723 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6724 assert(VM_Version::supports_evex(), "");
6725 assert(imm8 <= 0x03, "imm8: %u", imm8);
6726 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6727 attributes.set_is_evex_instruction();
6728 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6729 emit_int8(0x39);
6730 emit_int8((unsigned char)(0xC0 | encode));
6731 // 0x00 - extract from bits 127:0
6732 // 0x01 - extract from bits 255:128
6733 // 0x02 - extract from bits 383:256
6734 // 0x03 - extract from bits 511:384
6735 emit_int8(imm8 & 0x03);
6736 }
6737
6738 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
6739 assert(VM_Version::supports_evex(), "");
6740 assert(src != xnoreg, "sanity");
6741 assert(imm8 <= 0x03, "imm8: %u", imm8);
6742 InstructionMark im(this);
6743 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6744 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6745 attributes.reset_is_clear_context();
6746 attributes.set_is_evex_instruction();
6747 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6748 emit_int8(0x39);
6749 emit_operand(src, dst);
6750 // 0x00 - extract from bits 127:0
6751 // 0x01 - extract from bits 255:128
6752 // 0x02 - extract from bits 383:256
6753 // 0x03 - extract from bits 511:384
6754 emit_int8(imm8 & 0x03);
6755 }
6756
6757 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6758 assert(VM_Version::supports_avx512dq(), "");
6759 assert(imm8 <= 0x03, "imm8: %u", imm8);
6760 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6761 attributes.set_is_evex_instruction();
6762 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6763 emit_int8(0x39);
6764 emit_int8((unsigned char)(0xC0 | encode));
6765 // 0x00 - extract from bits 127:0
6766 // 0x01 - extract from bits 255:128
6767 // 0x02 - extract from bits 383:256
6768 // 0x03 - extract from bits 511:384
6769 emit_int8(imm8 & 0x03);
6770 }
6771
6772 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6773 assert(VM_Version::supports_evex(), "");
6774 assert(imm8 <= 0x01, "imm8: %u", imm8);
6775 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6776 attributes.set_is_evex_instruction();
6777 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6778 emit_int8(0x3B);
6779 emit_int8((unsigned char)(0xC0 | encode));
6780 // 0x00 - extract from lower 256 bits
6781 // 0x01 - extract from upper 256 bits
6782 emit_int8(imm8 & 0x01);
6783 }
6784
6785 void Assembler::vextracti64x4(Address dst, XMMRegister src, uint8_t imm8) {
6786 assert(VM_Version::supports_evex(), "");
6787 assert(src != xnoreg, "sanity");
6788 assert(imm8 <= 0x01, "imm8: %u", imm8);
6789 InstructionMark im(this);
6790 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6791 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6792 attributes.reset_is_clear_context();
6793 attributes.set_is_evex_instruction();
6794 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6795 emit_int8(0x38);
6796 emit_operand(src, dst);
6797 // 0x00 - extract from lower 256 bits
6798 // 0x01 - extract from upper 256 bits
6799 emit_int8(imm8 & 0x01);
6800 }
6801 // vextractf forms
6802
6803 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6804 assert(VM_Version::supports_avx(), "");
6805 assert(imm8 <= 0x01, "imm8: %u", imm8);
6806 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6807 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6808 emit_int8(0x19);
6809 emit_int8((unsigned char)(0xC0 | encode));
6810 // 0x00 - extract from lower 128 bits
6811 // 0x01 - extract from upper 128 bits
6812 emit_int8(imm8 & 0x01);
6813 }
6814
6815 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6816 assert(VM_Version::supports_avx(), "");
6817 assert(src != xnoreg, "sanity");
6818 assert(imm8 <= 0x01, "imm8: %u", imm8);
6819 InstructionMark im(this);
6820 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6821 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6822 attributes.reset_is_clear_context();
6823 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6824 emit_int8(0x19);
6825 emit_operand(src, dst);
6826 // 0x00 - extract from lower 128 bits
6827 // 0x01 - extract from upper 128 bits
6828 emit_int8(imm8 & 0x01);
6829 }
6830
6831 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6832 assert(VM_Version::supports_evex(), "");
6833 assert(imm8 <= 0x03, "imm8: %u", imm8);
6834 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6835 attributes.set_is_evex_instruction();
6836 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6837 emit_int8(0x19);
6838 emit_int8((unsigned char)(0xC0 | encode));
6839 // 0x00 - extract from bits 127:0
6840 // 0x01 - extract from bits 255:128
6841 // 0x02 - extract from bits 383:256
6842 // 0x03 - extract from bits 511:384
6843 emit_int8(imm8 & 0x03);
6844 }
6845
6846 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6847 assert(VM_Version::supports_evex(), "");
6848 assert(src != xnoreg, "sanity");
6849 assert(imm8 <= 0x03, "imm8: %u", imm8);
6850 InstructionMark im(this);
6851 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6852 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6853 attributes.reset_is_clear_context();
6854 attributes.set_is_evex_instruction();
6855 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6856 emit_int8(0x19);
6857 emit_operand(src, dst);
6858 // 0x00 - extract from bits 127:0
6859 // 0x01 - extract from bits 255:128
6860 // 0x02 - extract from bits 383:256
6861 // 0x03 - extract from bits 511:384
6862 emit_int8(imm8 & 0x03);
6863 }
6864
6865 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6866 assert(VM_Version::supports_avx512dq(), "");
6867 assert(imm8 <= 0x03, "imm8: %u", imm8);
6868 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6869 attributes.set_is_evex_instruction();
6870 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6871 emit_int8(0x19);
6872 emit_int8((unsigned char)(0xC0 | encode));
6873 // 0x00 - extract from bits 127:0
6874 // 0x01 - extract from bits 255:128
6875 // 0x02 - extract from bits 383:256
6876 // 0x03 - extract from bits 511:384
6877 emit_int8(imm8 & 0x03);
6878 }
6879
6880 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6881 assert(VM_Version::supports_evex(), "");
6882 assert(imm8 <= 0x01, "imm8: %u", imm8);
6883 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6884 attributes.set_is_evex_instruction();
6885 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6886 emit_int8(0x1B);
6887 emit_int8((unsigned char)(0xC0 | encode));
6888 // 0x00 - extract from lower 256 bits
6889 // 0x01 - extract from upper 256 bits
6890 emit_int8(imm8 & 0x01);
6891 }
6892
6893 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
6894 assert(VM_Version::supports_evex(), "");
6895 assert(src != xnoreg, "sanity");
6896 assert(imm8 <= 0x01, "imm8: %u", imm8);
6897 InstructionMark im(this);
6898 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6899 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
6900 attributes.reset_is_clear_context();
6901 attributes.set_is_evex_instruction();
6902 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6903 emit_int8(0x1B);
6904 emit_operand(src, dst);
6905 // 0x00 - extract from lower 256 bits
6906 // 0x01 - extract from upper 256 bits
6907 emit_int8(imm8 & 0x01);
6908 }
6909
6910 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6911 void Assembler::vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6912 assert(VM_Version::supports_avx2(), "");
6913 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6914 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6915 emit_int8(0x78);
6916 emit_int8((unsigned char)(0xC0 | encode));
6917 }
6918
6919 void Assembler::vpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6920 assert(VM_Version::supports_avx2(), "");
6921 assert(dst != xnoreg, "sanity");
6922 InstructionMark im(this);
6923 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6924 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6925 // swap src<->dst for encoding
6926 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6927 emit_int8(0x78);
6928 emit_operand(dst, src);
6929 }
6930
6931 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6932 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6933 assert(VM_Version::supports_avx2(), "");
6934 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6935 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6936 emit_int8(0x79);
6937 emit_int8((unsigned char)(0xC0 | encode));
6938 }
6939
6940 void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6941 assert(VM_Version::supports_avx2(), "");
6942 assert(dst != xnoreg, "sanity");
6943 InstructionMark im(this);
6944 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6945 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6946 // swap src<->dst for encoding
6947 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6948 emit_int8(0x79);
6949 emit_operand(dst, src);
6950 }
6951
6952 // xmm/mem sourced byte/word/dword/qword replicate
6953
6954 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6955 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6956 assert(UseAVX >= 2, "");
6957 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6958 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6959 emit_int8(0x58);
6960 emit_int8((unsigned char)(0xC0 | encode));
6961 }
6962
6963 void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6964 assert(VM_Version::supports_avx2(), "");
6965 assert(dst != xnoreg, "sanity");
6966 InstructionMark im(this);
6967 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6968 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6969 // swap src<->dst for encoding
6970 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6971 emit_int8(0x58);
6972 emit_operand(dst, src);
6973 }
6974
6975 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6976 void Assembler::vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6977 assert(VM_Version::supports_avx2(), "");
6978 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6979 attributes.set_rex_vex_w_reverted();
6980 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6981 emit_int8(0x59);
6982 emit_int8((unsigned char)(0xC0 | encode));
6983 }
6984
6985 void Assembler::vpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6986 assert(VM_Version::supports_avx2(), "");
6987 assert(dst != xnoreg, "sanity");
6988 InstructionMark im(this);
6989 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6990 attributes.set_rex_vex_w_reverted();
6991 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6992 // swap src<->dst for encoding
6993 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6994 emit_int8(0x59);
6995 emit_operand(dst, src);
6996 }
6997 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) {
6998 assert(vector_len != Assembler::AVX_128bit, "");
6999 assert(VM_Version::supports_avx512dq(), "");
7000 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7001 attributes.set_rex_vex_w_reverted();
7002 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7003 emit_int8(0x5A);
7004 emit_int8((unsigned char)(0xC0 | encode));
7005 }
7006
7007 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) {
7008 assert(vector_len != Assembler::AVX_128bit, "");
7009 assert(VM_Version::supports_avx512dq(), "");
7010 assert(dst != xnoreg, "sanity");
7011 InstructionMark im(this);
7012 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7013 attributes.set_rex_vex_w_reverted();
7014 attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit);
7015 // swap src<->dst for encoding
7016 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7017 emit_int8(0x5A);
7018 emit_operand(dst, src);
7019 }
7020
7021 // scalar single/double precision replicate
7022
7023 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
7024 void Assembler::vpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
7025 assert(VM_Version::supports_avx(), "");
7026 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7027 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7028 emit_int8(0x18);
7029 emit_int8((unsigned char)(0xC0 | encode));
7030 }
7031
7032 void Assembler::vpbroadcastss(XMMRegister dst, Address src, int vector_len) {
7033 assert(VM_Version::supports_avx(), "");
7034 assert(dst != xnoreg, "sanity");
7035 InstructionMark im(this);
7036 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7037 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
7038 // swap src<->dst for encoding
7039 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7040 emit_int8(0x18);
7041 emit_operand(dst, src);
7042 }
7043
7044 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
7045 void Assembler::vpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
7046 assert(VM_Version::supports_avx(), "");
7047 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7048 attributes.set_rex_vex_w_reverted();
7049 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7050 emit_int8(0x19);
7051 emit_int8((unsigned char)(0xC0 | encode));
7052 }
7053
7054 void Assembler::vpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
7055 assert(VM_Version::supports_avx(), "");
7056 assert(dst != xnoreg, "sanity");
7057 InstructionMark im(this);
7058 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7059 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7060 attributes.set_rex_vex_w_reverted();
7061 // swap src<->dst for encoding
7062 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7063 emit_int8(0x19);
7064 emit_operand(dst, src);
7065 }
7066
7067
7068 // gpr source broadcast forms
7069
7070 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
7071 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
7072 assert(VM_Version::supports_avx512bw(), "");
7073 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7074 attributes.set_is_evex_instruction();
7075 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7076 emit_int8(0x7A);
7077 emit_int8((unsigned char)(0xC0 | encode));
7078 }
7079
7080 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
7081 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
7082 assert(VM_Version::supports_avx512bw(), "");
7083 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7084 attributes.set_is_evex_instruction();
7085 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7086 emit_int8(0x7B);
7087 emit_int8((unsigned char)(0xC0 | encode));
7088 }
7089
7090 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
7091 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
7092 assert(VM_Version::supports_evex(), "");
7093 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7094 attributes.set_is_evex_instruction();
7095 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7096 emit_int8(0x7C);
7097 emit_int8((unsigned char)(0xC0 | encode));
7098 }
7099
7100 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
7101 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
7102 assert(VM_Version::supports_evex(), "");
7103 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7104 attributes.set_is_evex_instruction();
7105 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7106 emit_int8(0x7C);
7107 emit_int8((unsigned char)(0xC0 | encode));
7108 }
7109
7110 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
7111 assert(VM_Version::supports_evex(), "");
7112 assert(dst != xnoreg, "sanity");
7113 InstructionMark im(this);
7114 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7115 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7116 attributes.reset_is_clear_context();
7117 attributes.set_embedded_opmask_register_specifier(mask);
7118 attributes.set_is_evex_instruction();
7119 // swap src<->dst for encoding
7120 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7121 emit_int8((unsigned char)0x90);
7122 emit_operand(dst, src);
7123 }
7124
7125 // Carry-Less Multiplication Quadword
7126 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
7127 assert(VM_Version::supports_clmul(), "");
7128 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7129 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7130 emit_int8(0x44);
7131 emit_int8((unsigned char)(0xC0 | encode));
7132 emit_int8((unsigned char)mask);
7133 }
7134
7135 // Carry-Less Multiplication Quadword
7136 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
7137 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
7138 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7139 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7140 emit_int8(0x44);
7141 emit_int8((unsigned char)(0xC0 | encode));
7142 emit_int8((unsigned char)mask);
7143 }
7144
7145 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) {
7146 assert(VM_Version::supports_vpclmulqdq(), "Requires vector carryless multiplication support");
7147 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7148 attributes.set_is_evex_instruction();
7149 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7150 emit_int8(0x44);
7151 emit_int8((unsigned char)(0xC0 | encode));
7152 emit_int8((unsigned char)mask);
7153 }
7154
7155 void Assembler::vzeroupper() {
7156 if (VM_Version::supports_vzeroupper()) {
7157 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
7158 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7159 emit_int8(0x77);
7160 }
7161 }
7162
7163 #ifndef _LP64
7164 // 32bit only pieces of the assembler
7165
7166 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7167 // NO PREFIX AS NEVER 64BIT
7168 InstructionMark im(this);
7169 emit_int8((unsigned char)0x81);
7170 emit_int8((unsigned char)(0xF8 | src1->encoding()));
7171 emit_data(imm32, rspec, 0);
7172 }
7173
7174 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7175 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
7176 InstructionMark im(this);
7177 emit_int8((unsigned char)0x81);
7178 emit_operand(rdi, src1);
7179 emit_data(imm32, rspec, 0);
7180 }
7181
7182 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
7183 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
7184 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
7185 void Assembler::cmpxchg8(Address adr) {
7186 InstructionMark im(this);
7187 emit_int8(0x0F);
7188 emit_int8((unsigned char)0xC7);
7189 emit_operand(rcx, adr);
7190 }
7191
7192 void Assembler::decl(Register dst) {
7193 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7194 emit_int8(0x48 | dst->encoding());
7195 }
7196
7197 #endif // _LP64
7198
7199 // 64bit typically doesn't use the x87 but needs to for the trig funcs
7200
7201 void Assembler::fabs() {
7202 emit_int8((unsigned char)0xD9);
7203 emit_int8((unsigned char)0xE1);
7204 }
7205
7206 void Assembler::fadd(int i) {
7207 emit_farith(0xD8, 0xC0, i);
7208 }
7209
7210 void Assembler::fadd_d(Address src) {
7211 InstructionMark im(this);
7212 emit_int8((unsigned char)0xDC);
7213 emit_operand32(rax, src);
7214 }
7215
7216 void Assembler::fadd_s(Address src) {
7217 InstructionMark im(this);
7218 emit_int8((unsigned char)0xD8);
7219 emit_operand32(rax, src);
7220 }
7221
7222 void Assembler::fadda(int i) {
7223 emit_farith(0xDC, 0xC0, i);
7224 }
7225
7226 void Assembler::faddp(int i) {
7227 emit_farith(0xDE, 0xC0, i);
7228 }
7229
7230 void Assembler::fchs() {
7231 emit_int8((unsigned char)0xD9);
7232 emit_int8((unsigned char)0xE0);
7233 }
7234
7235 void Assembler::fcom(int i) {
7236 emit_farith(0xD8, 0xD0, i);
7237 }
7238
7239 void Assembler::fcomp(int i) {
7240 emit_farith(0xD8, 0xD8, i);
7241 }
7242
7243 void Assembler::fcomp_d(Address src) {
7244 InstructionMark im(this);
7245 emit_int8((unsigned char)0xDC);
7246 emit_operand32(rbx, src);
7247 }
7248
7249 void Assembler::fcomp_s(Address src) {
7250 InstructionMark im(this);
7251 emit_int8((unsigned char)0xD8);
7252 emit_operand32(rbx, src);
7253 }
7254
7255 void Assembler::fcompp() {
7256 emit_int8((unsigned char)0xDE);
7257 emit_int8((unsigned char)0xD9);
7258 }
7259
7260 void Assembler::fcos() {
7261 emit_int8((unsigned char)0xD9);
7262 emit_int8((unsigned char)0xFF);
7263 }
7264
7265 void Assembler::fdecstp() {
7266 emit_int8((unsigned char)0xD9);
7267 emit_int8((unsigned char)0xF6);
7268 }
7269
7270 void Assembler::fdiv(int i) {
7271 emit_farith(0xD8, 0xF0, i);
7272 }
7273
7274 void Assembler::fdiv_d(Address src) {
7275 InstructionMark im(this);
7276 emit_int8((unsigned char)0xDC);
7277 emit_operand32(rsi, src);
7278 }
7279
7280 void Assembler::fdiv_s(Address src) {
7281 InstructionMark im(this);
7282 emit_int8((unsigned char)0xD8);
7283 emit_operand32(rsi, src);
7284 }
7285
7286 void Assembler::fdiva(int i) {
7287 emit_farith(0xDC, 0xF8, i);
7288 }
7289
7290 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
7291 // is erroneous for some of the floating-point instructions below.
7292
7293 void Assembler::fdivp(int i) {
7294 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
7295 }
7296
7297 void Assembler::fdivr(int i) {
7298 emit_farith(0xD8, 0xF8, i);
7299 }
7300
7301 void Assembler::fdivr_d(Address src) {
7302 InstructionMark im(this);
7303 emit_int8((unsigned char)0xDC);
7304 emit_operand32(rdi, src);
7305 }
7306
7307 void Assembler::fdivr_s(Address src) {
7308 InstructionMark im(this);
7309 emit_int8((unsigned char)0xD8);
7310 emit_operand32(rdi, src);
7311 }
7312
7313 void Assembler::fdivra(int i) {
7314 emit_farith(0xDC, 0xF0, i);
7315 }
7316
7317 void Assembler::fdivrp(int i) {
7318 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
7319 }
7320
7321 void Assembler::ffree(int i) {
7322 emit_farith(0xDD, 0xC0, i);
7323 }
7324
7325 void Assembler::fild_d(Address adr) {
7326 InstructionMark im(this);
7327 emit_int8((unsigned char)0xDF);
7328 emit_operand32(rbp, adr);
7329 }
7330
7331 void Assembler::fild_s(Address adr) {
7332 InstructionMark im(this);
7333 emit_int8((unsigned char)0xDB);
7334 emit_operand32(rax, adr);
7335 }
7336
7337 void Assembler::fincstp() {
7338 emit_int8((unsigned char)0xD9);
7339 emit_int8((unsigned char)0xF7);
7340 }
7341
7342 void Assembler::finit() {
7343 emit_int8((unsigned char)0x9B);
7344 emit_int8((unsigned char)0xDB);
7345 emit_int8((unsigned char)0xE3);
7346 }
7347
7348 void Assembler::fist_s(Address adr) {
7349 InstructionMark im(this);
7350 emit_int8((unsigned char)0xDB);
7351 emit_operand32(rdx, adr);
7352 }
7353
7354 void Assembler::fistp_d(Address adr) {
7355 InstructionMark im(this);
7356 emit_int8((unsigned char)0xDF);
7357 emit_operand32(rdi, adr);
7358 }
7359
7360 void Assembler::fistp_s(Address adr) {
7361 InstructionMark im(this);
7362 emit_int8((unsigned char)0xDB);
7363 emit_operand32(rbx, adr);
7364 }
7365
7366 void Assembler::fld1() {
7367 emit_int8((unsigned char)0xD9);
7368 emit_int8((unsigned char)0xE8);
7369 }
7370
7371 void Assembler::fld_d(Address adr) {
7372 InstructionMark im(this);
7373 emit_int8((unsigned char)0xDD);
7374 emit_operand32(rax, adr);
7375 }
7376
7377 void Assembler::fld_s(Address adr) {
7378 InstructionMark im(this);
7379 emit_int8((unsigned char)0xD9);
7380 emit_operand32(rax, adr);
7381 }
7382
7383
7384 void Assembler::fld_s(int index) {
7385 emit_farith(0xD9, 0xC0, index);
7386 }
7387
7388 void Assembler::fld_x(Address adr) {
7389 InstructionMark im(this);
7390 emit_int8((unsigned char)0xDB);
7391 emit_operand32(rbp, adr);
7392 }
7393
7394 void Assembler::fldcw(Address src) {
7395 InstructionMark im(this);
7396 emit_int8((unsigned char)0xD9);
7397 emit_operand32(rbp, src);
7398 }
7399
7400 void Assembler::fldenv(Address src) {
7401 InstructionMark im(this);
7402 emit_int8((unsigned char)0xD9);
7403 emit_operand32(rsp, src);
7404 }
7405
7406 void Assembler::fldlg2() {
7407 emit_int8((unsigned char)0xD9);
7408 emit_int8((unsigned char)0xEC);
7409 }
7410
7411 void Assembler::fldln2() {
7412 emit_int8((unsigned char)0xD9);
7413 emit_int8((unsigned char)0xED);
7414 }
7415
7416 void Assembler::fldz() {
7417 emit_int8((unsigned char)0xD9);
7418 emit_int8((unsigned char)0xEE);
7419 }
7420
7421 void Assembler::flog() {
7422 fldln2();
7423 fxch();
7424 fyl2x();
7425 }
7426
7427 void Assembler::flog10() {
7428 fldlg2();
7429 fxch();
7430 fyl2x();
7431 }
7432
7433 void Assembler::fmul(int i) {
7434 emit_farith(0xD8, 0xC8, i);
7435 }
7436
7437 void Assembler::fmul_d(Address src) {
7438 InstructionMark im(this);
7439 emit_int8((unsigned char)0xDC);
7440 emit_operand32(rcx, src);
7441 }
7442
7443 void Assembler::fmul_s(Address src) {
7444 InstructionMark im(this);
7445 emit_int8((unsigned char)0xD8);
7446 emit_operand32(rcx, src);
7447 }
7448
7449 void Assembler::fmula(int i) {
7450 emit_farith(0xDC, 0xC8, i);
7451 }
7452
7453 void Assembler::fmulp(int i) {
7454 emit_farith(0xDE, 0xC8, i);
7455 }
7456
7457 void Assembler::fnsave(Address dst) {
7458 InstructionMark im(this);
7459 emit_int8((unsigned char)0xDD);
7460 emit_operand32(rsi, dst);
7461 }
7462
7463 void Assembler::fnstcw(Address src) {
7464 InstructionMark im(this);
7465 emit_int8((unsigned char)0x9B);
7466 emit_int8((unsigned char)0xD9);
7467 emit_operand32(rdi, src);
7468 }
7469
7470 void Assembler::fnstsw_ax() {
7471 emit_int8((unsigned char)0xDF);
7472 emit_int8((unsigned char)0xE0);
7473 }
7474
7475 void Assembler::fprem() {
7476 emit_int8((unsigned char)0xD9);
7477 emit_int8((unsigned char)0xF8);
7478 }
7479
7480 void Assembler::fprem1() {
7481 emit_int8((unsigned char)0xD9);
7482 emit_int8((unsigned char)0xF5);
7483 }
7484
7485 void Assembler::frstor(Address src) {
7486 InstructionMark im(this);
7487 emit_int8((unsigned char)0xDD);
7488 emit_operand32(rsp, src);
7489 }
7490
7491 void Assembler::fsin() {
7492 emit_int8((unsigned char)0xD9);
7493 emit_int8((unsigned char)0xFE);
7494 }
7495
7496 void Assembler::fsqrt() {
7497 emit_int8((unsigned char)0xD9);
7498 emit_int8((unsigned char)0xFA);
7499 }
7500
7501 void Assembler::fst_d(Address adr) {
7502 InstructionMark im(this);
7503 emit_int8((unsigned char)0xDD);
7504 emit_operand32(rdx, adr);
7505 }
7506
7507 void Assembler::fst_s(Address adr) {
7508 InstructionMark im(this);
7509 emit_int8((unsigned char)0xD9);
7510 emit_operand32(rdx, adr);
7511 }
7512
7513 void Assembler::fstp_d(Address adr) {
7514 InstructionMark im(this);
7515 emit_int8((unsigned char)0xDD);
7516 emit_operand32(rbx, adr);
7517 }
7518
7519 void Assembler::fstp_d(int index) {
7520 emit_farith(0xDD, 0xD8, index);
7521 }
7522
7523 void Assembler::fstp_s(Address adr) {
7524 InstructionMark im(this);
7525 emit_int8((unsigned char)0xD9);
7526 emit_operand32(rbx, adr);
7527 }
7528
7529 void Assembler::fstp_x(Address adr) {
7530 InstructionMark im(this);
7531 emit_int8((unsigned char)0xDB);
7532 emit_operand32(rdi, adr);
7533 }
7534
7535 void Assembler::fsub(int i) {
7536 emit_farith(0xD8, 0xE0, i);
7537 }
7538
7539 void Assembler::fsub_d(Address src) {
7540 InstructionMark im(this);
7541 emit_int8((unsigned char)0xDC);
7542 emit_operand32(rsp, src);
7543 }
7544
7545 void Assembler::fsub_s(Address src) {
7546 InstructionMark im(this);
7547 emit_int8((unsigned char)0xD8);
7548 emit_operand32(rsp, src);
7549 }
7550
7551 void Assembler::fsuba(int i) {
7552 emit_farith(0xDC, 0xE8, i);
7553 }
7554
7555 void Assembler::fsubp(int i) {
7556 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
7557 }
7558
7559 void Assembler::fsubr(int i) {
7560 emit_farith(0xD8, 0xE8, i);
7561 }
7562
7563 void Assembler::fsubr_d(Address src) {
7564 InstructionMark im(this);
7565 emit_int8((unsigned char)0xDC);
7566 emit_operand32(rbp, src);
7567 }
7568
7569 void Assembler::fsubr_s(Address src) {
7570 InstructionMark im(this);
7571 emit_int8((unsigned char)0xD8);
7572 emit_operand32(rbp, src);
7573 }
7574
7575 void Assembler::fsubra(int i) {
7576 emit_farith(0xDC, 0xE0, i);
7577 }
7578
7579 void Assembler::fsubrp(int i) {
7580 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
7581 }
7582
7583 void Assembler::ftan() {
7584 emit_int8((unsigned char)0xD9);
7585 emit_int8((unsigned char)0xF2);
7586 emit_int8((unsigned char)0xDD);
7587 emit_int8((unsigned char)0xD8);
7588 }
7589
7590 void Assembler::ftst() {
7591 emit_int8((unsigned char)0xD9);
7592 emit_int8((unsigned char)0xE4);
7593 }
7594
7595 void Assembler::fucomi(int i) {
7596 // make sure the instruction is supported (introduced for P6, together with cmov)
7597 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7598 emit_farith(0xDB, 0xE8, i);
7599 }
7600
7601 void Assembler::fucomip(int i) {
7602 // make sure the instruction is supported (introduced for P6, together with cmov)
7603 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7604 emit_farith(0xDF, 0xE8, i);
7605 }
7606
7607 void Assembler::fwait() {
7608 emit_int8((unsigned char)0x9B);
7609 }
7610
7611 void Assembler::fxch(int i) {
7612 emit_farith(0xD9, 0xC8, i);
7613 }
7614
7615 void Assembler::fyl2x() {
7616 emit_int8((unsigned char)0xD9);
7617 emit_int8((unsigned char)0xF1);
7618 }
7619
7620 void Assembler::frndint() {
7621 emit_int8((unsigned char)0xD9);
7622 emit_int8((unsigned char)0xFC);
7623 }
7624
7625 void Assembler::f2xm1() {
7626 emit_int8((unsigned char)0xD9);
7627 emit_int8((unsigned char)0xF0);
7628 }
7629
7630 void Assembler::fldl2e() {
7631 emit_int8((unsigned char)0xD9);
7632 emit_int8((unsigned char)0xEA);
7633 }
7634
7635 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
7636 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
7637 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
7638 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
7639
7640 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
7641 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7642 if (pre > 0) {
7643 emit_int8(simd_pre[pre]);
7644 }
7645 if (rex_w) {
7646 prefixq(adr, xreg);
7647 } else {
7648 prefix(adr, xreg);
7649 }
7650 if (opc > 0) {
7651 emit_int8(0x0F);
7652 int opc2 = simd_opc[opc];
7653 if (opc2 > 0) {
7654 emit_int8(opc2);
7655 }
7656 }
7657 }
7658
7659 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7660 if (pre > 0) {
7661 emit_int8(simd_pre[pre]);
7662 }
7663 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
7664 if (opc > 0) {
7665 emit_int8(0x0F);
7666 int opc2 = simd_opc[opc];
7667 if (opc2 > 0) {
7668 emit_int8(opc2);
7669 }
7670 }
7671 return encode;
7672 }
7673
7674
7675 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
7676 int vector_len = _attributes->get_vector_len();
7677 bool vex_w = _attributes->is_rex_vex_w();
7678 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
7679 prefix(VEX_3bytes);
7680
7681 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
7682 byte1 = (~byte1) & 0xE0;
7683 byte1 |= opc;
7684 emit_int8(byte1);
7685
7686 int byte2 = ((~nds_enc) & 0xf) << 3;
7687 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
7688 emit_int8(byte2);
7689 } else {
7690 prefix(VEX_2bytes);
7691
7692 int byte1 = vex_r ? VEX_R : 0;
7693 byte1 = (~byte1) & 0x80;
7694 byte1 |= ((~nds_enc) & 0xf) << 3;
7695 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
7696 emit_int8(byte1);
7697 }
7698 }
7699
7700 // This is a 4 byte encoding
7701 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
7702 // EVEX 0x62 prefix
7703 prefix(EVEX_4bytes);
7704 bool vex_w = _attributes->is_rex_vex_w();
7705 int evex_encoding = (vex_w ? VEX_W : 0);
7706 // EVEX.b is not currently used for broadcast of single element or data rounding modes
7707 _attributes->set_evex_encoding(evex_encoding);
7708
7709 // P0: byte 2, initialized to RXBR`00mm
7710 // instead of not'd
7711 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
7712 byte2 = (~byte2) & 0xF0;
7713 // confine opc opcode extensions in mm bits to lower two bits
7714 // of form {0F, 0F_38, 0F_3A}
7715 byte2 |= opc;
7716 emit_int8(byte2);
7717
7718 // P1: byte 3 as Wvvvv1pp
7719 int byte3 = ((~nds_enc) & 0xf) << 3;
7720 // p[10] is always 1
7721 byte3 |= EVEX_F;
7722 byte3 |= (vex_w & 1) << 7;
7723 // confine pre opcode extensions in pp bits to lower two bits
7724 // of form {66, F3, F2}
7725 byte3 |= pre;
7726 emit_int8(byte3);
7727
7728 // P2: byte 4 as zL'Lbv'aaa
7729 // kregs are implemented in the low 3 bits as aaa
7730 int byte4 = (_attributes->is_no_reg_mask()) ?
7731 0 :
7732 _attributes->get_embedded_opmask_register_specifier();
7733 // EVEX.v` for extending EVEX.vvvv or VIDX
7734 byte4 |= (evex_v ? 0: EVEX_V);
7735 // third EXEC.b for broadcast actions
7736 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
7737 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
7738 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
7739 // last is EVEX.z for zero/merge actions
7740 if (_attributes->is_no_reg_mask() == false) {
7741 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
7742 }
7743 emit_int8(byte4);
7744 }
7745
7746 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7747 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
7748 bool vex_b = adr.base_needs_rex();
7749 bool vex_x;
7750 if (adr.isxmmindex()) {
7751 vex_x = adr.xmmindex_needs_rex();
7752 } else {
7753 vex_x = adr.index_needs_rex();
7754 }
7755 set_attributes(attributes);
7756 attributes->set_current_assembler(this);
7757
7758 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
7759 // is allowed in legacy mode and has resources which will fit in it.
7760 // Pure EVEX instructions will have is_evex_instruction set in their definition.
7761 if (!attributes->is_legacy_mode()) {
7762 if (UseAVX > 2 && !attributes->is_evex_instruction() && !_is_managed) {
7763 if ((attributes->get_vector_len() != AVX_512bit) && (nds_enc < 16) && (xreg_enc < 16)) {
7764 attributes->set_is_legacy_mode();
7765 }
7766 }
7767 }
7768
7769 if (UseAVX > 2) {
7770 assert(((!attributes->uses_vl()) ||
7771 (attributes->get_vector_len() == AVX_512bit) ||
7772 (!_legacy_mode_vl) ||
7773 (attributes->is_legacy_mode())),"XMM register should be 0-15");
7774 assert(((nds_enc < 16 && xreg_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
7775 }
7776
7777 _is_managed = false;
7778 if (UseAVX > 2 && !attributes->is_legacy_mode())
7779 {
7780 bool evex_r = (xreg_enc >= 16);
7781 bool evex_v;
7782 // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31)
7783 if (adr.isxmmindex()) {
7784 evex_v = ((adr._xmmindex->encoding() > 15) ? true : false);
7785 } else {
7786 evex_v = (nds_enc >= 16);
7787 }
7788 attributes->set_is_evex_instruction();
7789 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7790 } else {
7791 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7792 attributes->set_rex_vex_w(false);
7793 }
7794 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7795 }
7796 }
7797
7798 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7799 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
7800 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
7801 bool vex_x = false;
7802 set_attributes(attributes);
7803 attributes->set_current_assembler(this);
7804
7805 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
7806 // is allowed in legacy mode and has resources which will fit in it.
7807 // Pure EVEX instructions will have is_evex_instruction set in their definition.
7808 if (!attributes->is_legacy_mode()) {
7809 if (UseAVX > 2 && !attributes->is_evex_instruction() && !_is_managed) {
7810 if ((!attributes->uses_vl() || (attributes->get_vector_len() != AVX_512bit)) &&
7811 (dst_enc < 16) && (nds_enc < 16) && (src_enc < 16)) {
7812 attributes->set_is_legacy_mode();
7813 }
7814 }
7815 }
7816
7817 if (UseAVX > 2) {
7818 // All the scalar fp instructions (with uses_vl as false) can have legacy_mode as false
7819 // Instruction with uses_vl true are vector instructions
7820 // All the vector instructions with AVX_512bit length can have legacy_mode as false
7821 // All the vector instructions with < AVX_512bit length can have legacy_mode as false if AVX512vl() is supported
7822 // Rest all should have legacy_mode set as true
7823 assert(((!attributes->uses_vl()) ||
7824 (attributes->get_vector_len() == AVX_512bit) ||
7825 (!_legacy_mode_vl) ||
7826 (attributes->is_legacy_mode())),"XMM register should be 0-15");
7827 // Instruction with legacy_mode true should have dst, nds and src < 15
7828 assert(((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
7829 }
7830
7831 _is_managed = false;
7832 if (UseAVX > 2 && !attributes->is_legacy_mode())
7833 {
7834 bool evex_r = (dst_enc >= 16);
7835 bool evex_v = (nds_enc >= 16);
7836 // can use vex_x as bank extender on rm encoding
7837 vex_x = (src_enc >= 16);
7838 attributes->set_is_evex_instruction();
7839 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7840 } else {
7841 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7842 attributes->set_rex_vex_w(false);
7843 }
7844 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7845 }
7846
7847 // return modrm byte components for operands
7848 return (((dst_enc & 7) << 3) | (src_enc & 7));
7849 }
7850
7851
7852 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
7853 VexOpcode opc, InstructionAttr *attributes) {
7854 if (UseAVX > 0) {
7855 int xreg_enc = xreg->encoding();
7856 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7857 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
7858 } else {
7859 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
7860 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
7861 }
7862 }
7863
7864 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
7865 VexOpcode opc, InstructionAttr *attributes) {
7866 int dst_enc = dst->encoding();
7867 int src_enc = src->encoding();
7868 if (UseAVX > 0) {
7869 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7870 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7871 } else {
7872 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7873 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7874 }
7875 }
7876
7877 void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
7878 assert(VM_Version::supports_avx(), "");
7879 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7880 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7881 emit_int8(0x5F);
7882 emit_int8((unsigned char)(0xC0 | encode));
7883 }
7884
7885 void Assembler::vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
7886 assert(VM_Version::supports_avx(), "");
7887 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7888 attributes.set_rex_vex_w_reverted();
7889 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7890 emit_int8(0x5F);
7891 emit_int8((unsigned char)(0xC0 | encode));
7892 }
7893
7894 void Assembler::vminss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
7895 assert(VM_Version::supports_avx(), "");
7896 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7897 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7898 emit_int8(0x5D);
7899 emit_int8((unsigned char)(0xC0 | encode));
7900 }
7901
7902 void Assembler::vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
7903 assert(VM_Version::supports_avx(), "");
7904 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7905 attributes.set_rex_vex_w_reverted();
7906 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7907 emit_int8(0x5D);
7908 emit_int8((unsigned char)(0xC0 | encode));
7909 }
7910
7911 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7912 assert(VM_Version::supports_avx(), "");
7913 assert(vector_len <= AVX_256bit, "");
7914 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7915 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7916 emit_int8((unsigned char)0xC2);
7917 emit_int8((unsigned char)(0xC0 | encode));
7918 emit_int8((unsigned char)(0xF & cop));
7919 }
7920
7921 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7922 assert(VM_Version::supports_avx(), "");
7923 assert(vector_len <= AVX_256bit, "");
7924 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7925 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7926 emit_int8((unsigned char)0x4B);
7927 emit_int8((unsigned char)(0xC0 | encode));
7928 int src2_enc = src2->encoding();
7929 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7930 }
7931
7932 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7933 assert(VM_Version::supports_avx(), "");
7934 assert(vector_len <= AVX_256bit, "");
7935 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7936 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7937 emit_int8((unsigned char)0xC2);
7938 emit_int8((unsigned char)(0xC0 | encode));
7939 emit_int8((unsigned char)(0xF & cop));
7940 }
7941
7942 void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7943 assert(VM_Version::supports_avx(), "");
7944 assert(vector_len <= AVX_256bit, "");
7945 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7946 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7947 emit_int8((unsigned char)0x4A);
7948 emit_int8((unsigned char)(0xC0 | encode));
7949 int src2_enc = src2->encoding();
7950 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7951 }
7952
7953 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
7954 assert(VM_Version::supports_avx2(), "");
7955 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7956 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7957 emit_int8((unsigned char)0x02);
7958 emit_int8((unsigned char)(0xC0 | encode));
7959 emit_int8((unsigned char)imm8);
7960 }
7961
7962 void Assembler::shlxl(Register dst, Register src1, Register src2) {
7963 assert(VM_Version::supports_bmi2(), "");
7964 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7965 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7966 emit_int8((unsigned char)0xF7);
7967 emit_int8((unsigned char)(0xC0 | encode));
7968 }
7969
7970 void Assembler::shlxq(Register dst, Register src1, Register src2) {
7971 assert(VM_Version::supports_bmi2(), "");
7972 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7973 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7974 emit_int8((unsigned char)0xF7);
7975 emit_int8((unsigned char)(0xC0 | encode));
7976 }
7977
7978 #ifndef _LP64
7979
7980 void Assembler::incl(Register dst) {
7981 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7982 emit_int8(0x40 | dst->encoding());
7983 }
7984
7985 void Assembler::lea(Register dst, Address src) {
7986 leal(dst, src);
7987 }
7988
7989 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7990 InstructionMark im(this);
7991 emit_int8((unsigned char)0xC7);
7992 emit_operand(rax, dst);
7993 emit_data((int)imm32, rspec, 0);
7994 }
7995
7996 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7997 InstructionMark im(this);
7998 int encode = prefix_and_encode(dst->encoding());
7999 emit_int8((unsigned char)(0xB8 | encode));
8000 emit_data((int)imm32, rspec, 0);
8001 }
8002
8003 void Assembler::popa() { // 32bit
8004 emit_int8(0x61);
8005 }
8006
8007 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
8008 InstructionMark im(this);
8009 emit_int8(0x68);
8010 emit_data(imm32, rspec, 0);
8011 }
8012
8013 void Assembler::pusha() { // 32bit
8014 emit_int8(0x60);
8015 }
8016
8017 void Assembler::set_byte_if_not_zero(Register dst) {
8018 emit_int8(0x0F);
8019 emit_int8((unsigned char)0x95);
8020 emit_int8((unsigned char)(0xE0 | dst->encoding()));
8021 }
8022
8023 void Assembler::shldl(Register dst, Register src) {
8024 emit_int8(0x0F);
8025 emit_int8((unsigned char)0xA5);
8026 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
8027 }
8028
8029 // 0F A4 / r ib
8030 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
8031 emit_int8(0x0F);
8032 emit_int8((unsigned char)0xA4);
8033 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
8034 emit_int8(imm8);
8035 }
8036
8037 void Assembler::shrdl(Register dst, Register src) {
8038 emit_int8(0x0F);
8039 emit_int8((unsigned char)0xAD);
8040 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
8041 }
8042
8043 #else // LP64
8044
8045 void Assembler::set_byte_if_not_zero(Register dst) {
8046 int enc = prefix_and_encode(dst->encoding(), true);
8047 emit_int8(0x0F);
8048 emit_int8((unsigned char)0x95);
8049 emit_int8((unsigned char)(0xE0 | enc));
8050 }
8051
8052 // 64bit only pieces of the assembler
8053 // This should only be used by 64bit instructions that can use rip-relative
8054 // it cannot be used by instructions that want an immediate value.
8055
8056 bool Assembler::reachable(AddressLiteral adr) {
8057 int64_t disp;
8058 // None will force a 64bit literal to the code stream. Likely a placeholder
8059 // for something that will be patched later and we need to certain it will
8060 // always be reachable.
8061 if (adr.reloc() == relocInfo::none) {
8062 return false;
8063 }
8064 if (adr.reloc() == relocInfo::internal_word_type) {
8065 // This should be rip relative and easily reachable.
8066 return true;
8067 }
8068 if (adr.reloc() == relocInfo::virtual_call_type ||
8069 adr.reloc() == relocInfo::opt_virtual_call_type ||
8070 adr.reloc() == relocInfo::static_call_type ||
8071 adr.reloc() == relocInfo::static_stub_type ) {
8072 // This should be rip relative within the code cache and easily
8073 // reachable until we get huge code caches. (At which point
8074 // ic code is going to have issues).
8075 return true;
8076 }
8077 if (adr.reloc() != relocInfo::external_word_type &&
8078 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
8079 adr.reloc() != relocInfo::poll_type && // relocs to identify them
8080 adr.reloc() != relocInfo::runtime_call_type ) {
8081 return false;
8082 }
8083
8084 // Stress the correction code
8085 if (ForceUnreachable) {
8086 // Must be runtimecall reloc, see if it is in the codecache
8087 // Flipping stuff in the codecache to be unreachable causes issues
8088 // with things like inline caches where the additional instructions
8089 // are not handled.
8090 if (CodeCache::find_blob(adr._target) == NULL) {
8091 return false;
8092 }
8093 }
8094 // For external_word_type/runtime_call_type if it is reachable from where we
8095 // are now (possibly a temp buffer) and where we might end up
8096 // anywhere in the codeCache then we are always reachable.
8097 // This would have to change if we ever save/restore shared code
8098 // to be more pessimistic.
8099 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
8100 if (!is_simm32(disp)) return false;
8101 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
8102 if (!is_simm32(disp)) return false;
8103
8104 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
8105
8106 // Because rip relative is a disp + address_of_next_instruction and we
8107 // don't know the value of address_of_next_instruction we apply a fudge factor
8108 // to make sure we will be ok no matter the size of the instruction we get placed into.
8109 // We don't have to fudge the checks above here because they are already worst case.
8110
8111 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
8112 // + 4 because better safe than sorry.
8113 const int fudge = 12 + 4;
8114 if (disp < 0) {
8115 disp -= fudge;
8116 } else {
8117 disp += fudge;
8118 }
8119 return is_simm32(disp);
8120 }
8121
8122 // Check if the polling page is not reachable from the code cache using rip-relative
8123 // addressing.
8124 bool Assembler::is_polling_page_far() {
8125 intptr_t addr = (intptr_t)os::get_polling_page();
8126 return ForceUnreachable ||
8127 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
8128 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
8129 }
8130
8131 void Assembler::emit_data64(jlong data,
8132 relocInfo::relocType rtype,
8133 int format) {
8134 if (rtype == relocInfo::none) {
8135 emit_int64(data);
8136 } else {
8137 emit_data64(data, Relocation::spec_simple(rtype), format);
8138 }
8139 }
8140
8141 void Assembler::emit_data64(jlong data,
8142 RelocationHolder const& rspec,
8143 int format) {
8144 assert(imm_operand == 0, "default format must be immediate in this file");
8145 assert(imm_operand == format, "must be immediate");
8146 assert(inst_mark() != NULL, "must be inside InstructionMark");
8147 // Do not use AbstractAssembler::relocate, which is not intended for
8148 // embedded words. Instead, relocate to the enclosing instruction.
8149 code_section()->relocate(inst_mark(), rspec, format);
8150 #ifdef ASSERT
8151 check_relocation(rspec, format);
8152 #endif
8153 emit_int64(data);
8154 }
8155
8156 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
8157 if (reg_enc >= 8) {
8158 prefix(REX_B);
8159 reg_enc -= 8;
8160 } else if (byteinst && reg_enc >= 4) {
8161 prefix(REX);
8162 }
8163 return reg_enc;
8164 }
8165
8166 int Assembler::prefixq_and_encode(int reg_enc) {
8167 if (reg_enc < 8) {
8168 prefix(REX_W);
8169 } else {
8170 prefix(REX_WB);
8171 reg_enc -= 8;
8172 }
8173 return reg_enc;
8174 }
8175
8176 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
8177 if (dst_enc < 8) {
8178 if (src_enc >= 8) {
8179 prefix(REX_B);
8180 src_enc -= 8;
8181 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
8182 prefix(REX);
8183 }
8184 } else {
8185 if (src_enc < 8) {
8186 prefix(REX_R);
8187 } else {
8188 prefix(REX_RB);
8189 src_enc -= 8;
8190 }
8191 dst_enc -= 8;
8192 }
8193 return dst_enc << 3 | src_enc;
8194 }
8195
8196 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
8197 if (dst_enc < 8) {
8198 if (src_enc < 8) {
8199 prefix(REX_W);
8200 } else {
8201 prefix(REX_WB);
8202 src_enc -= 8;
8203 }
8204 } else {
8205 if (src_enc < 8) {
8206 prefix(REX_WR);
8207 } else {
8208 prefix(REX_WRB);
8209 src_enc -= 8;
8210 }
8211 dst_enc -= 8;
8212 }
8213 return dst_enc << 3 | src_enc;
8214 }
8215
8216 void Assembler::prefix(Register reg) {
8217 if (reg->encoding() >= 8) {
8218 prefix(REX_B);
8219 }
8220 }
8221
8222 void Assembler::prefix(Register dst, Register src, Prefix p) {
8223 if (src->encoding() >= 8) {
8224 p = (Prefix)(p | REX_B);
8225 }
8226 if (dst->encoding() >= 8) {
8227 p = (Prefix)( p | REX_R);
8228 }
8229 if (p != Prefix_EMPTY) {
8230 // do not generate an empty prefix
8231 prefix(p);
8232 }
8233 }
8234
8235 void Assembler::prefix(Register dst, Address adr, Prefix p) {
8236 if (adr.base_needs_rex()) {
8237 if (adr.index_needs_rex()) {
8238 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
8239 } else {
8240 prefix(REX_B);
8241 }
8242 } else {
8243 if (adr.index_needs_rex()) {
8244 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
8245 }
8246 }
8247 if (dst->encoding() >= 8) {
8248 p = (Prefix)(p | REX_R);
8249 }
8250 if (p != Prefix_EMPTY) {
8251 // do not generate an empty prefix
8252 prefix(p);
8253 }
8254 }
8255
8256 void Assembler::prefix(Address adr) {
8257 if (adr.base_needs_rex()) {
8258 if (adr.index_needs_rex()) {
8259 prefix(REX_XB);
8260 } else {
8261 prefix(REX_B);
8262 }
8263 } else {
8264 if (adr.index_needs_rex()) {
8265 prefix(REX_X);
8266 }
8267 }
8268 }
8269
8270 void Assembler::prefixq(Address adr) {
8271 if (adr.base_needs_rex()) {
8272 if (adr.index_needs_rex()) {
8273 prefix(REX_WXB);
8274 } else {
8275 prefix(REX_WB);
8276 }
8277 } else {
8278 if (adr.index_needs_rex()) {
8279 prefix(REX_WX);
8280 } else {
8281 prefix(REX_W);
8282 }
8283 }
8284 }
8285
8286
8287 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
8288 if (reg->encoding() < 8) {
8289 if (adr.base_needs_rex()) {
8290 if (adr.index_needs_rex()) {
8291 prefix(REX_XB);
8292 } else {
8293 prefix(REX_B);
8294 }
8295 } else {
8296 if (adr.index_needs_rex()) {
8297 prefix(REX_X);
8298 } else if (byteinst && reg->encoding() >= 4 ) {
8299 prefix(REX);
8300 }
8301 }
8302 } else {
8303 if (adr.base_needs_rex()) {
8304 if (adr.index_needs_rex()) {
8305 prefix(REX_RXB);
8306 } else {
8307 prefix(REX_RB);
8308 }
8309 } else {
8310 if (adr.index_needs_rex()) {
8311 prefix(REX_RX);
8312 } else {
8313 prefix(REX_R);
8314 }
8315 }
8316 }
8317 }
8318
8319 void Assembler::prefixq(Address adr, Register src) {
8320 if (src->encoding() < 8) {
8321 if (adr.base_needs_rex()) {
8322 if (adr.index_needs_rex()) {
8323 prefix(REX_WXB);
8324 } else {
8325 prefix(REX_WB);
8326 }
8327 } else {
8328 if (adr.index_needs_rex()) {
8329 prefix(REX_WX);
8330 } else {
8331 prefix(REX_W);
8332 }
8333 }
8334 } else {
8335 if (adr.base_needs_rex()) {
8336 if (adr.index_needs_rex()) {
8337 prefix(REX_WRXB);
8338 } else {
8339 prefix(REX_WRB);
8340 }
8341 } else {
8342 if (adr.index_needs_rex()) {
8343 prefix(REX_WRX);
8344 } else {
8345 prefix(REX_WR);
8346 }
8347 }
8348 }
8349 }
8350
8351 void Assembler::prefix(Address adr, XMMRegister reg) {
8352 if (reg->encoding() < 8) {
8353 if (adr.base_needs_rex()) {
8354 if (adr.index_needs_rex()) {
8355 prefix(REX_XB);
8356 } else {
8357 prefix(REX_B);
8358 }
8359 } else {
8360 if (adr.index_needs_rex()) {
8361 prefix(REX_X);
8362 }
8363 }
8364 } else {
8365 if (adr.base_needs_rex()) {
8366 if (adr.index_needs_rex()) {
8367 prefix(REX_RXB);
8368 } else {
8369 prefix(REX_RB);
8370 }
8371 } else {
8372 if (adr.index_needs_rex()) {
8373 prefix(REX_RX);
8374 } else {
8375 prefix(REX_R);
8376 }
8377 }
8378 }
8379 }
8380
8381 void Assembler::prefixq(Address adr, XMMRegister src) {
8382 if (src->encoding() < 8) {
8383 if (adr.base_needs_rex()) {
8384 if (adr.index_needs_rex()) {
8385 prefix(REX_WXB);
8386 } else {
8387 prefix(REX_WB);
8388 }
8389 } else {
8390 if (adr.index_needs_rex()) {
8391 prefix(REX_WX);
8392 } else {
8393 prefix(REX_W);
8394 }
8395 }
8396 } else {
8397 if (adr.base_needs_rex()) {
8398 if (adr.index_needs_rex()) {
8399 prefix(REX_WRXB);
8400 } else {
8401 prefix(REX_WRB);
8402 }
8403 } else {
8404 if (adr.index_needs_rex()) {
8405 prefix(REX_WRX);
8406 } else {
8407 prefix(REX_WR);
8408 }
8409 }
8410 }
8411 }
8412
8413 void Assembler::adcq(Register dst, int32_t imm32) {
8414 (void) prefixq_and_encode(dst->encoding());
8415 emit_arith(0x81, 0xD0, dst, imm32);
8416 }
8417
8418 void Assembler::adcq(Register dst, Address src) {
8419 InstructionMark im(this);
8420 prefixq(src, dst);
8421 emit_int8(0x13);
8422 emit_operand(dst, src);
8423 }
8424
8425 void Assembler::adcq(Register dst, Register src) {
8426 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8427 emit_arith(0x13, 0xC0, dst, src);
8428 }
8429
8430 void Assembler::addq(Address dst, int32_t imm32) {
8431 InstructionMark im(this);
8432 prefixq(dst);
8433 emit_arith_operand(0x81, rax, dst,imm32);
8434 }
8435
8436 void Assembler::addq(Address dst, Register src) {
8437 InstructionMark im(this);
8438 prefixq(dst, src);
8439 emit_int8(0x01);
8440 emit_operand(src, dst);
8441 }
8442
8443 void Assembler::addq(Register dst, int32_t imm32) {
8444 (void) prefixq_and_encode(dst->encoding());
8445 emit_arith(0x81, 0xC0, dst, imm32);
8446 }
8447
8448 void Assembler::addq(Register dst, Address src) {
8449 InstructionMark im(this);
8450 prefixq(src, dst);
8451 emit_int8(0x03);
8452 emit_operand(dst, src);
8453 }
8454
8455 void Assembler::addq(Register dst, Register src) {
8456 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8457 emit_arith(0x03, 0xC0, dst, src);
8458 }
8459
8460 void Assembler::adcxq(Register dst, Register src) {
8461 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8462 emit_int8((unsigned char)0x66);
8463 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8464 emit_int8(0x0F);
8465 emit_int8(0x38);
8466 emit_int8((unsigned char)0xF6);
8467 emit_int8((unsigned char)(0xC0 | encode));
8468 }
8469
8470 void Assembler::adoxq(Register dst, Register src) {
8471 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8472 emit_int8((unsigned char)0xF3);
8473 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8474 emit_int8(0x0F);
8475 emit_int8(0x38);
8476 emit_int8((unsigned char)0xF6);
8477 emit_int8((unsigned char)(0xC0 | encode));
8478 }
8479
8480 void Assembler::andq(Address dst, int32_t imm32) {
8481 InstructionMark im(this);
8482 prefixq(dst);
8483 emit_int8((unsigned char)0x81);
8484 emit_operand(rsp, dst, 4);
8485 emit_int32(imm32);
8486 }
8487
8488 void Assembler::andq(Register dst, int32_t imm32) {
8489 (void) prefixq_and_encode(dst->encoding());
8490 emit_arith(0x81, 0xE0, dst, imm32);
8491 }
8492
8493 void Assembler::andq(Register dst, Address src) {
8494 InstructionMark im(this);
8495 prefixq(src, dst);
8496 emit_int8(0x23);
8497 emit_operand(dst, src);
8498 }
8499
8500 void Assembler::andq(Register dst, Register src) {
8501 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8502 emit_arith(0x23, 0xC0, dst, src);
8503 }
8504
8505 void Assembler::andnq(Register dst, Register src1, Register src2) {
8506 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8507 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8508 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8509 emit_int8((unsigned char)0xF2);
8510 emit_int8((unsigned char)(0xC0 | encode));
8511 }
8512
8513 void Assembler::andnq(Register dst, Register src1, Address src2) {
8514 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8515 InstructionMark im(this);
8516 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8517 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8518 emit_int8((unsigned char)0xF2);
8519 emit_operand(dst, src2);
8520 }
8521
8522 void Assembler::bsfq(Register dst, Register src) {
8523 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8524 emit_int8(0x0F);
8525 emit_int8((unsigned char)0xBC);
8526 emit_int8((unsigned char)(0xC0 | encode));
8527 }
8528
8529 void Assembler::bsrq(Register dst, Register src) {
8530 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8531 emit_int8(0x0F);
8532 emit_int8((unsigned char)0xBD);
8533 emit_int8((unsigned char)(0xC0 | encode));
8534 }
8535
8536 void Assembler::bswapq(Register reg) {
8537 int encode = prefixq_and_encode(reg->encoding());
8538 emit_int8(0x0F);
8539 emit_int8((unsigned char)(0xC8 | encode));
8540 }
8541
8542 void Assembler::blsiq(Register dst, Register src) {
8543 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8544 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8545 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8546 emit_int8((unsigned char)0xF3);
8547 emit_int8((unsigned char)(0xC0 | encode));
8548 }
8549
8550 void Assembler::blsiq(Register dst, Address src) {
8551 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8552 InstructionMark im(this);
8553 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8554 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8555 emit_int8((unsigned char)0xF3);
8556 emit_operand(rbx, src);
8557 }
8558
8559 void Assembler::blsmskq(Register dst, Register src) {
8560 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8561 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8562 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8563 emit_int8((unsigned char)0xF3);
8564 emit_int8((unsigned char)(0xC0 | encode));
8565 }
8566
8567 void Assembler::blsmskq(Register dst, Address src) {
8568 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8569 InstructionMark im(this);
8570 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8571 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8572 emit_int8((unsigned char)0xF3);
8573 emit_operand(rdx, src);
8574 }
8575
8576 void Assembler::blsrq(Register dst, Register src) {
8577 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8578 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8579 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8580 emit_int8((unsigned char)0xF3);
8581 emit_int8((unsigned char)(0xC0 | encode));
8582 }
8583
8584 void Assembler::blsrq(Register dst, Address src) {
8585 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8586 InstructionMark im(this);
8587 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8588 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8589 emit_int8((unsigned char)0xF3);
8590 emit_operand(rcx, src);
8591 }
8592
8593 void Assembler::cdqq() {
8594 prefix(REX_W);
8595 emit_int8((unsigned char)0x99);
8596 }
8597
8598 void Assembler::clflush(Address adr) {
8599 prefix(adr);
8600 emit_int8(0x0F);
8601 emit_int8((unsigned char)0xAE);
8602 emit_operand(rdi, adr);
8603 }
8604
8605 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8606 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8607 emit_int8(0x0F);
8608 emit_int8(0x40 | cc);
8609 emit_int8((unsigned char)(0xC0 | encode));
8610 }
8611
8612 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8613 InstructionMark im(this);
8614 prefixq(src, dst);
8615 emit_int8(0x0F);
8616 emit_int8(0x40 | cc);
8617 emit_operand(dst, src);
8618 }
8619
8620 void Assembler::cmpq(Address dst, int32_t imm32) {
8621 InstructionMark im(this);
8622 prefixq(dst);
8623 emit_int8((unsigned char)0x81);
8624 emit_operand(rdi, dst, 4);
8625 emit_int32(imm32);
8626 }
8627
8628 void Assembler::cmpq(Register dst, int32_t imm32) {
8629 (void) prefixq_and_encode(dst->encoding());
8630 emit_arith(0x81, 0xF8, dst, imm32);
8631 }
8632
8633 void Assembler::cmpq(Address dst, Register src) {
8634 InstructionMark im(this);
8635 prefixq(dst, src);
8636 emit_int8(0x3B);
8637 emit_operand(src, dst);
8638 }
8639
8640 void Assembler::cmpq(Register dst, Register src) {
8641 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8642 emit_arith(0x3B, 0xC0, dst, src);
8643 }
8644
8645 void Assembler::cmpq(Register dst, Address src) {
8646 InstructionMark im(this);
8647 prefixq(src, dst);
8648 emit_int8(0x3B);
8649 emit_operand(dst, src);
8650 }
8651
8652 void Assembler::cmpxchgq(Register reg, Address adr) {
8653 InstructionMark im(this);
8654 prefixq(adr, reg);
8655 emit_int8(0x0F);
8656 emit_int8((unsigned char)0xB1);
8657 emit_operand(reg, adr);
8658 }
8659
8660 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
8661 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8662 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8663 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8664 emit_int8(0x2A);
8665 emit_int8((unsigned char)(0xC0 | encode));
8666 }
8667
8668 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
8669 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8670 InstructionMark im(this);
8671 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8672 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8673 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8674 emit_int8(0x2A);
8675 emit_operand(dst, src);
8676 }
8677
8678 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
8679 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8680 InstructionMark im(this);
8681 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8682 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8683 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8684 emit_int8(0x2A);
8685 emit_operand(dst, src);
8686 }
8687
8688 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
8689 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8690 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8691 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8692 emit_int8(0x2C);
8693 emit_int8((unsigned char)(0xC0 | encode));
8694 }
8695
8696 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
8697 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8698 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8699 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8700 emit_int8(0x2C);
8701 emit_int8((unsigned char)(0xC0 | encode));
8702 }
8703
8704 void Assembler::decl(Register dst) {
8705 // Don't use it directly. Use MacroAssembler::decrementl() instead.
8706 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
8707 int encode = prefix_and_encode(dst->encoding());
8708 emit_int8((unsigned char)0xFF);
8709 emit_int8((unsigned char)(0xC8 | encode));
8710 }
8711
8712 void Assembler::decq(Register dst) {
8713 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8714 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8715 int encode = prefixq_and_encode(dst->encoding());
8716 emit_int8((unsigned char)0xFF);
8717 emit_int8(0xC8 | encode);
8718 }
8719
8720 void Assembler::decq(Address dst) {
8721 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8722 InstructionMark im(this);
8723 prefixq(dst);
8724 emit_int8((unsigned char)0xFF);
8725 emit_operand(rcx, dst);
8726 }
8727
8728 void Assembler::fxrstor(Address src) {
8729 prefixq(src);
8730 emit_int8(0x0F);
8731 emit_int8((unsigned char)0xAE);
8732 emit_operand(as_Register(1), src);
8733 }
8734
8735 void Assembler::xrstor(Address src) {
8736 prefixq(src);
8737 emit_int8(0x0F);
8738 emit_int8((unsigned char)0xAE);
8739 emit_operand(as_Register(5), src);
8740 }
8741
8742 void Assembler::fxsave(Address dst) {
8743 prefixq(dst);
8744 emit_int8(0x0F);
8745 emit_int8((unsigned char)0xAE);
8746 emit_operand(as_Register(0), dst);
8747 }
8748
8749 void Assembler::xsave(Address dst) {
8750 prefixq(dst);
8751 emit_int8(0x0F);
8752 emit_int8((unsigned char)0xAE);
8753 emit_operand(as_Register(4), dst);
8754 }
8755
8756 void Assembler::idivq(Register src) {
8757 int encode = prefixq_and_encode(src->encoding());
8758 emit_int8((unsigned char)0xF7);
8759 emit_int8((unsigned char)(0xF8 | encode));
8760 }
8761
8762 void Assembler::imulq(Register dst, Register src) {
8763 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8764 emit_int8(0x0F);
8765 emit_int8((unsigned char)0xAF);
8766 emit_int8((unsigned char)(0xC0 | encode));
8767 }
8768
8769 void Assembler::imulq(Register dst, Register src, int value) {
8770 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8771 if (is8bit(value)) {
8772 emit_int8(0x6B);
8773 emit_int8((unsigned char)(0xC0 | encode));
8774 emit_int8(value & 0xFF);
8775 } else {
8776 emit_int8(0x69);
8777 emit_int8((unsigned char)(0xC0 | encode));
8778 emit_int32(value);
8779 }
8780 }
8781
8782 void Assembler::imulq(Register dst, Address src) {
8783 InstructionMark im(this);
8784 prefixq(src, dst);
8785 emit_int8(0x0F);
8786 emit_int8((unsigned char) 0xAF);
8787 emit_operand(dst, src);
8788 }
8789
8790 void Assembler::incl(Register dst) {
8791 // Don't use it directly. Use MacroAssembler::incrementl() instead.
8792 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8793 int encode = prefix_and_encode(dst->encoding());
8794 emit_int8((unsigned char)0xFF);
8795 emit_int8((unsigned char)(0xC0 | encode));
8796 }
8797
8798 void Assembler::incq(Register dst) {
8799 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8800 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8801 int encode = prefixq_and_encode(dst->encoding());
8802 emit_int8((unsigned char)0xFF);
8803 emit_int8((unsigned char)(0xC0 | encode));
8804 }
8805
8806 void Assembler::incq(Address dst) {
8807 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8808 InstructionMark im(this);
8809 prefixq(dst);
8810 emit_int8((unsigned char)0xFF);
8811 emit_operand(rax, dst);
8812 }
8813
8814 void Assembler::lea(Register dst, Address src) {
8815 leaq(dst, src);
8816 }
8817
8818 void Assembler::leaq(Register dst, Address src) {
8819 InstructionMark im(this);
8820 prefixq(src, dst);
8821 emit_int8((unsigned char)0x8D);
8822 emit_operand(dst, src);
8823 }
8824
8825 void Assembler::mov64(Register dst, int64_t imm64) {
8826 InstructionMark im(this);
8827 int encode = prefixq_and_encode(dst->encoding());
8828 emit_int8((unsigned char)(0xB8 | encode));
8829 emit_int64(imm64);
8830 }
8831
8832 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
8833 InstructionMark im(this);
8834 int encode = prefixq_and_encode(dst->encoding());
8835 emit_int8(0xB8 | encode);
8836 emit_data64(imm64, rspec);
8837 }
8838
8839 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
8840 InstructionMark im(this);
8841 int encode = prefix_and_encode(dst->encoding());
8842 emit_int8((unsigned char)(0xB8 | encode));
8843 emit_data((int)imm32, rspec, narrow_oop_operand);
8844 }
8845
8846 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
8847 InstructionMark im(this);
8848 prefix(dst);
8849 emit_int8((unsigned char)0xC7);
8850 emit_operand(rax, dst, 4);
8851 emit_data((int)imm32, rspec, narrow_oop_operand);
8852 }
8853
8854 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
8855 InstructionMark im(this);
8856 int encode = prefix_and_encode(src1->encoding());
8857 emit_int8((unsigned char)0x81);
8858 emit_int8((unsigned char)(0xF8 | encode));
8859 emit_data((int)imm32, rspec, narrow_oop_operand);
8860 }
8861
8862 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
8863 InstructionMark im(this);
8864 prefix(src1);
8865 emit_int8((unsigned char)0x81);
8866 emit_operand(rax, src1, 4);
8867 emit_data((int)imm32, rspec, narrow_oop_operand);
8868 }
8869
8870 void Assembler::lzcntq(Register dst, Register src) {
8871 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
8872 emit_int8((unsigned char)0xF3);
8873 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8874 emit_int8(0x0F);
8875 emit_int8((unsigned char)0xBD);
8876 emit_int8((unsigned char)(0xC0 | encode));
8877 }
8878
8879 void Assembler::movdq(XMMRegister dst, Register src) {
8880 // table D-1 says MMX/SSE2
8881 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8882 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8883 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8884 emit_int8(0x6E);
8885 emit_int8((unsigned char)(0xC0 | encode));
8886 }
8887
8888 void Assembler::movdq(Register dst, XMMRegister src) {
8889 // table D-1 says MMX/SSE2
8890 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8891 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8892 // swap src/dst to get correct prefix
8893 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8894 emit_int8(0x7E);
8895 emit_int8((unsigned char)(0xC0 | encode));
8896 }
8897
8898 void Assembler::movq(Register dst, Register src) {
8899 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8900 emit_int8((unsigned char)0x8B);
8901 emit_int8((unsigned char)(0xC0 | encode));
8902 }
8903
8904 void Assembler::movq(Register dst, Address src) {
8905 InstructionMark im(this);
8906 prefixq(src, dst);
8907 emit_int8((unsigned char)0x8B);
8908 emit_operand(dst, src);
8909 }
8910
8911 void Assembler::movq(Address dst, Register src) {
8912 InstructionMark im(this);
8913 prefixq(dst, src);
8914 emit_int8((unsigned char)0x89);
8915 emit_operand(src, dst);
8916 }
8917
8918 void Assembler::movsbq(Register dst, Address src) {
8919 InstructionMark im(this);
8920 prefixq(src, dst);
8921 emit_int8(0x0F);
8922 emit_int8((unsigned char)0xBE);
8923 emit_operand(dst, src);
8924 }
8925
8926 void Assembler::movsbq(Register dst, Register src) {
8927 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8928 emit_int8(0x0F);
8929 emit_int8((unsigned char)0xBE);
8930 emit_int8((unsigned char)(0xC0 | encode));
8931 }
8932
8933 void Assembler::movslq(Register dst, int32_t imm32) {
8934 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
8935 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
8936 // as a result we shouldn't use until tested at runtime...
8937 ShouldNotReachHere();
8938 InstructionMark im(this);
8939 int encode = prefixq_and_encode(dst->encoding());
8940 emit_int8((unsigned char)(0xC7 | encode));
8941 emit_int32(imm32);
8942 }
8943
8944 void Assembler::movslq(Address dst, int32_t imm32) {
8945 assert(is_simm32(imm32), "lost bits");
8946 InstructionMark im(this);
8947 prefixq(dst);
8948 emit_int8((unsigned char)0xC7);
8949 emit_operand(rax, dst, 4);
8950 emit_int32(imm32);
8951 }
8952
8953 void Assembler::movslq(Register dst, Address src) {
8954 InstructionMark im(this);
8955 prefixq(src, dst);
8956 emit_int8(0x63);
8957 emit_operand(dst, src);
8958 }
8959
8960 void Assembler::movslq(Register dst, Register src) {
8961 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8962 emit_int8(0x63);
8963 emit_int8((unsigned char)(0xC0 | encode));
8964 }
8965
8966 void Assembler::movswq(Register dst, Address src) {
8967 InstructionMark im(this);
8968 prefixq(src, dst);
8969 emit_int8(0x0F);
8970 emit_int8((unsigned char)0xBF);
8971 emit_operand(dst, src);
8972 }
8973
8974 void Assembler::movswq(Register dst, Register src) {
8975 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8976 emit_int8((unsigned char)0x0F);
8977 emit_int8((unsigned char)0xBF);
8978 emit_int8((unsigned char)(0xC0 | encode));
8979 }
8980
8981 void Assembler::movzbq(Register dst, Address src) {
8982 InstructionMark im(this);
8983 prefixq(src, dst);
8984 emit_int8((unsigned char)0x0F);
8985 emit_int8((unsigned char)0xB6);
8986 emit_operand(dst, src);
8987 }
8988
8989 void Assembler::movzbq(Register dst, Register src) {
8990 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8991 emit_int8(0x0F);
8992 emit_int8((unsigned char)0xB6);
8993 emit_int8(0xC0 | encode);
8994 }
8995
8996 void Assembler::movzwq(Register dst, Address src) {
8997 InstructionMark im(this);
8998 prefixq(src, dst);
8999 emit_int8((unsigned char)0x0F);
9000 emit_int8((unsigned char)0xB7);
9001 emit_operand(dst, src);
9002 }
9003
9004 void Assembler::movzwq(Register dst, Register src) {
9005 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9006 emit_int8((unsigned char)0x0F);
9007 emit_int8((unsigned char)0xB7);
9008 emit_int8((unsigned char)(0xC0 | encode));
9009 }
9010
9011 void Assembler::mulq(Address src) {
9012 InstructionMark im(this);
9013 prefixq(src);
9014 emit_int8((unsigned char)0xF7);
9015 emit_operand(rsp, src);
9016 }
9017
9018 void Assembler::mulq(Register src) {
9019 int encode = prefixq_and_encode(src->encoding());
9020 emit_int8((unsigned char)0xF7);
9021 emit_int8((unsigned char)(0xE0 | encode));
9022 }
9023
9024 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
9025 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9026 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9027 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
9028 emit_int8((unsigned char)0xF6);
9029 emit_int8((unsigned char)(0xC0 | encode));
9030 }
9031
9032 void Assembler::negq(Register dst) {
9033 int encode = prefixq_and_encode(dst->encoding());
9034 emit_int8((unsigned char)0xF7);
9035 emit_int8((unsigned char)(0xD8 | encode));
9036 }
9037
9038 void Assembler::notq(Register dst) {
9039 int encode = prefixq_and_encode(dst->encoding());
9040 emit_int8((unsigned char)0xF7);
9041 emit_int8((unsigned char)(0xD0 | encode));
9042 }
9043
9044 void Assembler::orq(Address dst, int32_t imm32) {
9045 InstructionMark im(this);
9046 prefixq(dst);
9047 emit_int8((unsigned char)0x81);
9048 emit_operand(rcx, dst, 4);
9049 emit_int32(imm32);
9050 }
9051
9052 void Assembler::orq(Register dst, int32_t imm32) {
9053 (void) prefixq_and_encode(dst->encoding());
9054 emit_arith(0x81, 0xC8, dst, imm32);
9055 }
9056
9057 void Assembler::orq(Register dst, Address src) {
9058 InstructionMark im(this);
9059 prefixq(src, dst);
9060 emit_int8(0x0B);
9061 emit_operand(dst, src);
9062 }
9063
9064 void Assembler::orq(Register dst, Register src) {
9065 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9066 emit_arith(0x0B, 0xC0, dst, src);
9067 }
9068
9069 void Assembler::popa() { // 64bit
9070 movq(r15, Address(rsp, 0));
9071 movq(r14, Address(rsp, wordSize));
9072 movq(r13, Address(rsp, 2 * wordSize));
9073 movq(r12, Address(rsp, 3 * wordSize));
9074 movq(r11, Address(rsp, 4 * wordSize));
9075 movq(r10, Address(rsp, 5 * wordSize));
9076 movq(r9, Address(rsp, 6 * wordSize));
9077 movq(r8, Address(rsp, 7 * wordSize));
9078 movq(rdi, Address(rsp, 8 * wordSize));
9079 movq(rsi, Address(rsp, 9 * wordSize));
9080 movq(rbp, Address(rsp, 10 * wordSize));
9081 // skip rsp
9082 movq(rbx, Address(rsp, 12 * wordSize));
9083 movq(rdx, Address(rsp, 13 * wordSize));
9084 movq(rcx, Address(rsp, 14 * wordSize));
9085 movq(rax, Address(rsp, 15 * wordSize));
9086
9087 addq(rsp, 16 * wordSize);
9088 }
9089
9090 void Assembler::popcntq(Register dst, Address src) {
9091 assert(VM_Version::supports_popcnt(), "must support");
9092 InstructionMark im(this);
9093 emit_int8((unsigned char)0xF3);
9094 prefixq(src, dst);
9095 emit_int8((unsigned char)0x0F);
9096 emit_int8((unsigned char)0xB8);
9097 emit_operand(dst, src);
9098 }
9099
9100 void Assembler::popcntq(Register dst, Register src) {
9101 assert(VM_Version::supports_popcnt(), "must support");
9102 emit_int8((unsigned char)0xF3);
9103 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9104 emit_int8((unsigned char)0x0F);
9105 emit_int8((unsigned char)0xB8);
9106 emit_int8((unsigned char)(0xC0 | encode));
9107 }
9108
9109 void Assembler::popq(Address dst) {
9110 InstructionMark im(this);
9111 prefixq(dst);
9112 emit_int8((unsigned char)0x8F);
9113 emit_operand(rax, dst);
9114 }
9115
9116 void Assembler::pusha() { // 64bit
9117 // we have to store original rsp. ABI says that 128 bytes
9118 // below rsp are local scratch.
9119 movq(Address(rsp, -5 * wordSize), rsp);
9120
9121 subq(rsp, 16 * wordSize);
9122
9123 movq(Address(rsp, 15 * wordSize), rax);
9124 movq(Address(rsp, 14 * wordSize), rcx);
9125 movq(Address(rsp, 13 * wordSize), rdx);
9126 movq(Address(rsp, 12 * wordSize), rbx);
9127 // skip rsp
9128 movq(Address(rsp, 10 * wordSize), rbp);
9129 movq(Address(rsp, 9 * wordSize), rsi);
9130 movq(Address(rsp, 8 * wordSize), rdi);
9131 movq(Address(rsp, 7 * wordSize), r8);
9132 movq(Address(rsp, 6 * wordSize), r9);
9133 movq(Address(rsp, 5 * wordSize), r10);
9134 movq(Address(rsp, 4 * wordSize), r11);
9135 movq(Address(rsp, 3 * wordSize), r12);
9136 movq(Address(rsp, 2 * wordSize), r13);
9137 movq(Address(rsp, wordSize), r14);
9138 movq(Address(rsp, 0), r15);
9139 }
9140
9141 void Assembler::pushq(Address src) {
9142 InstructionMark im(this);
9143 prefixq(src);
9144 emit_int8((unsigned char)0xFF);
9145 emit_operand(rsi, src);
9146 }
9147
9148 void Assembler::rclq(Register dst, int imm8) {
9149 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9150 int encode = prefixq_and_encode(dst->encoding());
9151 if (imm8 == 1) {
9152 emit_int8((unsigned char)0xD1);
9153 emit_int8((unsigned char)(0xD0 | encode));
9154 } else {
9155 emit_int8((unsigned char)0xC1);
9156 emit_int8((unsigned char)(0xD0 | encode));
9157 emit_int8(imm8);
9158 }
9159 }
9160
9161 void Assembler::rcrq(Register dst, int imm8) {
9162 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9163 int encode = prefixq_and_encode(dst->encoding());
9164 if (imm8 == 1) {
9165 emit_int8((unsigned char)0xD1);
9166 emit_int8((unsigned char)(0xD8 | encode));
9167 } else {
9168 emit_int8((unsigned char)0xC1);
9169 emit_int8((unsigned char)(0xD8 | encode));
9170 emit_int8(imm8);
9171 }
9172 }
9173
9174 void Assembler::rorq(Register dst, int imm8) {
9175 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9176 int encode = prefixq_and_encode(dst->encoding());
9177 if (imm8 == 1) {
9178 emit_int8((unsigned char)0xD1);
9179 emit_int8((unsigned char)(0xC8 | encode));
9180 } else {
9181 emit_int8((unsigned char)0xC1);
9182 emit_int8((unsigned char)(0xc8 | encode));
9183 emit_int8(imm8);
9184 }
9185 }
9186
9187 void Assembler::rorxq(Register dst, Register src, int imm8) {
9188 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9189 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9190 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9191 emit_int8((unsigned char)0xF0);
9192 emit_int8((unsigned char)(0xC0 | encode));
9193 emit_int8(imm8);
9194 }
9195
9196 void Assembler::rorxd(Register dst, Register src, int imm8) {
9197 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9198 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9199 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9200 emit_int8((unsigned char)0xF0);
9201 emit_int8((unsigned char)(0xC0 | encode));
9202 emit_int8(imm8);
9203 }
9204
9205 void Assembler::sarq(Register dst, int imm8) {
9206 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9207 int encode = prefixq_and_encode(dst->encoding());
9208 if (imm8 == 1) {
9209 emit_int8((unsigned char)0xD1);
9210 emit_int8((unsigned char)(0xF8 | encode));
9211 } else {
9212 emit_int8((unsigned char)0xC1);
9213 emit_int8((unsigned char)(0xF8 | encode));
9214 emit_int8(imm8);
9215 }
9216 }
9217
9218 void Assembler::sarq(Register dst) {
9219 int encode = prefixq_and_encode(dst->encoding());
9220 emit_int8((unsigned char)0xD3);
9221 emit_int8((unsigned char)(0xF8 | encode));
9222 }
9223
9224 void Assembler::sbbq(Address dst, int32_t imm32) {
9225 InstructionMark im(this);
9226 prefixq(dst);
9227 emit_arith_operand(0x81, rbx, dst, imm32);
9228 }
9229
9230 void Assembler::sbbq(Register dst, int32_t imm32) {
9231 (void) prefixq_and_encode(dst->encoding());
9232 emit_arith(0x81, 0xD8, dst, imm32);
9233 }
9234
9235 void Assembler::sbbq(Register dst, Address src) {
9236 InstructionMark im(this);
9237 prefixq(src, dst);
9238 emit_int8(0x1B);
9239 emit_operand(dst, src);
9240 }
9241
9242 void Assembler::sbbq(Register dst, Register src) {
9243 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9244 emit_arith(0x1B, 0xC0, dst, src);
9245 }
9246
9247 void Assembler::shlq(Register dst, int imm8) {
9248 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9249 int encode = prefixq_and_encode(dst->encoding());
9250 if (imm8 == 1) {
9251 emit_int8((unsigned char)0xD1);
9252 emit_int8((unsigned char)(0xE0 | encode));
9253 } else {
9254 emit_int8((unsigned char)0xC1);
9255 emit_int8((unsigned char)(0xE0 | encode));
9256 emit_int8(imm8);
9257 }
9258 }
9259
9260 void Assembler::shlq(Register dst) {
9261 int encode = prefixq_and_encode(dst->encoding());
9262 emit_int8((unsigned char)0xD3);
9263 emit_int8((unsigned char)(0xE0 | encode));
9264 }
9265
9266 void Assembler::shrq(Register dst, int imm8) {
9267 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9268 int encode = prefixq_and_encode(dst->encoding());
9269 emit_int8((unsigned char)0xC1);
9270 emit_int8((unsigned char)(0xE8 | encode));
9271 emit_int8(imm8);
9272 }
9273
9274 void Assembler::shrq(Register dst) {
9275 int encode = prefixq_and_encode(dst->encoding());
9276 emit_int8((unsigned char)0xD3);
9277 emit_int8(0xE8 | encode);
9278 }
9279
9280 void Assembler::subq(Address dst, int32_t imm32) {
9281 InstructionMark im(this);
9282 prefixq(dst);
9283 emit_arith_operand(0x81, rbp, dst, imm32);
9284 }
9285
9286 void Assembler::subq(Address dst, Register src) {
9287 InstructionMark im(this);
9288 prefixq(dst, src);
9289 emit_int8(0x29);
9290 emit_operand(src, dst);
9291 }
9292
9293 void Assembler::subq(Register dst, int32_t imm32) {
9294 (void) prefixq_and_encode(dst->encoding());
9295 emit_arith(0x81, 0xE8, dst, imm32);
9296 }
9297
9298 // Force generation of a 4 byte immediate value even if it fits into 8bit
9299 void Assembler::subq_imm32(Register dst, int32_t imm32) {
9300 (void) prefixq_and_encode(dst->encoding());
9301 emit_arith_imm32(0x81, 0xE8, dst, imm32);
9302 }
9303
9304 void Assembler::subq(Register dst, Address src) {
9305 InstructionMark im(this);
9306 prefixq(src, dst);
9307 emit_int8(0x2B);
9308 emit_operand(dst, src);
9309 }
9310
9311 void Assembler::subq(Register dst, Register src) {
9312 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9313 emit_arith(0x2B, 0xC0, dst, src);
9314 }
9315
9316 void Assembler::testq(Register dst, int32_t imm32) {
9317 // not using emit_arith because test
9318 // doesn't support sign-extension of
9319 // 8bit operands
9320 int encode = dst->encoding();
9321 if (encode == 0) {
9322 prefix(REX_W);
9323 emit_int8((unsigned char)0xA9);
9324 } else {
9325 encode = prefixq_and_encode(encode);
9326 emit_int8((unsigned char)0xF7);
9327 emit_int8((unsigned char)(0xC0 | encode));
9328 }
9329 emit_int32(imm32);
9330 }
9331
9332 void Assembler::testq(Register dst, Register src) {
9333 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9334 emit_arith(0x85, 0xC0, dst, src);
9335 }
9336
9337 void Assembler::testq(Register dst, Address src) {
9338 InstructionMark im(this);
9339 prefixq(src, dst);
9340 emit_int8((unsigned char)0x85);
9341 emit_operand(dst, src);
9342 }
9343
9344 void Assembler::xaddq(Address dst, Register src) {
9345 InstructionMark im(this);
9346 prefixq(dst, src);
9347 emit_int8(0x0F);
9348 emit_int8((unsigned char)0xC1);
9349 emit_operand(src, dst);
9350 }
9351
9352 void Assembler::xchgq(Register dst, Address src) {
9353 InstructionMark im(this);
9354 prefixq(src, dst);
9355 emit_int8((unsigned char)0x87);
9356 emit_operand(dst, src);
9357 }
9358
9359 void Assembler::xchgq(Register dst, Register src) {
9360 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9361 emit_int8((unsigned char)0x87);
9362 emit_int8((unsigned char)(0xc0 | encode));
9363 }
9364
9365 void Assembler::xorq(Register dst, Register src) {
9366 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9367 emit_arith(0x33, 0xC0, dst, src);
9368 }
9369
9370 void Assembler::xorq(Register dst, Address src) {
9371 InstructionMark im(this);
9372 prefixq(src, dst);
9373 emit_int8(0x33);
9374 emit_operand(dst, src);
9375 }
9376
9377 #endif // !LP64