1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
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  24 
  25 #ifndef CPU_X86_ASSEMBLER_X86_HPP
  26 #define CPU_X86_ASSEMBLER_X86_HPP
  27 
  28 #include "asm/register.hpp"
  29 #include "vm_version_x86.hpp"
  30 
  31 class BiasedLockingCounters;
  32 
  33 // Contains all the definitions needed for x86 assembly code generation.
  34 
  35 // Calling convention
  36 class Argument {
  37  public:
  38   enum {
  39 #ifdef _LP64
  40 #ifdef _WIN64
  41     n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
  42     n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
  43 #else
  44     n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
  45     n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
  46 #endif // _WIN64
  47     n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
  48     n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
  49 #else
  50     n_register_parameters = 0   // 0 registers used to pass arguments
  51 #endif // _LP64
  52   };
  53 };
  54 
  55 
  56 #ifdef _LP64
  57 // Symbolically name the register arguments used by the c calling convention.
  58 // Windows is different from linux/solaris. So much for standards...
  59 
  60 #ifdef _WIN64
  61 
  62 REGISTER_DECLARATION(Register, c_rarg0, rcx);
  63 REGISTER_DECLARATION(Register, c_rarg1, rdx);
  64 REGISTER_DECLARATION(Register, c_rarg2, r8);
  65 REGISTER_DECLARATION(Register, c_rarg3, r9);
  66 
  67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  71 
  72 #else
  73 
  74 REGISTER_DECLARATION(Register, c_rarg0, rdi);
  75 REGISTER_DECLARATION(Register, c_rarg1, rsi);
  76 REGISTER_DECLARATION(Register, c_rarg2, rdx);
  77 REGISTER_DECLARATION(Register, c_rarg3, rcx);
  78 REGISTER_DECLARATION(Register, c_rarg4, r8);
  79 REGISTER_DECLARATION(Register, c_rarg5, r9);
  80 
  81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
  86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
  87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
  88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
  89 
  90 #endif // _WIN64
  91 
  92 // Symbolically name the register arguments used by the Java calling convention.
  93 // We have control over the convention for java so we can do what we please.
  94 // What pleases us is to offset the java calling convention so that when
  95 // we call a suitable jni method the arguments are lined up and we don't
  96 // have to do little shuffling. A suitable jni method is non-static and a
  97 // small number of arguments (two fewer args on windows)
  98 //
  99 //        |-------------------------------------------------------|
 100 //        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
 101 //        |-------------------------------------------------------|
 102 //        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
 103 //        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
 104 //        |-------------------------------------------------------|
 105 //        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
 106 //        |-------------------------------------------------------|
 107 
 108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
 109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
 110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
 111 // Windows runs out of register args here
 112 #ifdef _WIN64
 113 REGISTER_DECLARATION(Register, j_rarg3, rdi);
 114 REGISTER_DECLARATION(Register, j_rarg4, rsi);
 115 #else
 116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
 117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
 118 #endif /* _WIN64 */
 119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
 120 
 121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
 122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
 123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
 124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
 125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
 126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
 127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
 128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
 129 
 130 REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
 131 REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
 132 
 133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
 134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
 135 
 136 #else
 137 // rscratch1 will apear in 32bit code that is dead but of course must compile
 138 // Using noreg ensures if the dead code is incorrectly live and executed it
 139 // will cause an assertion failure
 140 #define rscratch1 noreg
 141 #define rscratch2 noreg
 142 
 143 #endif // _LP64
 144 
 145 // JSR 292
 146 // On x86, the SP does not have to be saved when invoking method handle intrinsics
 147 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
 148 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
 149 
 150 // Address is an abstraction used to represent a memory location
 151 // using any of the amd64 addressing modes with one object.
 152 //
 153 // Note: A register location is represented via a Register, not
 154 //       via an address for efficiency & simplicity reasons.
 155 
 156 class ArrayAddress;
 157 
 158 class Address {
 159  public:
 160   enum ScaleFactor {
 161     no_scale = -1,
 162     times_1  =  0,
 163     times_2  =  1,
 164     times_4  =  2,
 165     times_8  =  3,
 166     times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 167   };
 168   static ScaleFactor times(int size) {
 169     assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
 170     if (size == 8)  return times_8;
 171     if (size == 4)  return times_4;
 172     if (size == 2)  return times_2;
 173     return times_1;
 174   }
 175   static int scale_size(ScaleFactor scale) {
 176     assert(scale != no_scale, "");
 177     assert(((1 << (int)times_1) == 1 &&
 178             (1 << (int)times_2) == 2 &&
 179             (1 << (int)times_4) == 4 &&
 180             (1 << (int)times_8) == 8), "");
 181     return (1 << (int)scale);
 182   }
 183 
 184  private:
 185   Register         _base;
 186   Register         _index;
 187   XMMRegister      _xmmindex;
 188   ScaleFactor      _scale;
 189   int              _disp;
 190   bool             _isxmmindex;
 191   RelocationHolder _rspec;
 192 
 193   // Easily misused constructors make them private
 194   // %%% can we make these go away?
 195   NOT_LP64(Address(address loc, RelocationHolder spec);)
 196   Address(int disp, address loc, relocInfo::relocType rtype);
 197   Address(int disp, address loc, RelocationHolder spec);
 198 
 199  public:
 200 
 201  int disp() { return _disp; }
 202   // creation
 203   Address()
 204     : _base(noreg),
 205       _index(noreg),
 206       _xmmindex(xnoreg),
 207       _scale(no_scale),
 208       _disp(0),
 209       _isxmmindex(false){
 210   }
 211 
 212   // No default displacement otherwise Register can be implicitly
 213   // converted to 0(Register) which is quite a different animal.
 214 
 215   Address(Register base, int disp)
 216     : _base(base),
 217       _index(noreg),
 218       _xmmindex(xnoreg),
 219       _scale(no_scale),
 220       _disp(disp),
 221       _isxmmindex(false){
 222   }
 223 
 224   Address(Register base, Register index, ScaleFactor scale, int disp = 0)
 225     : _base (base),
 226       _index(index),
 227       _xmmindex(xnoreg),
 228       _scale(scale),
 229       _disp (disp),
 230       _isxmmindex(false) {
 231     assert(!index->is_valid() == (scale == Address::no_scale),
 232            "inconsistent address");
 233   }
 234 
 235   Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
 236     : _base (base),
 237       _index(index.register_or_noreg()),
 238       _xmmindex(xnoreg),
 239       _scale(scale),
 240       _disp (disp + (index.constant_or_zero() * scale_size(scale))),
 241       _isxmmindex(false){
 242     if (!index.is_register())  scale = Address::no_scale;
 243     assert(!_index->is_valid() == (scale == Address::no_scale),
 244            "inconsistent address");
 245   }
 246 
 247   Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0)
 248     : _base (base),
 249       _index(noreg),
 250       _xmmindex(index),
 251       _scale(scale),
 252       _disp(disp),
 253       _isxmmindex(true) {
 254       assert(!index->is_valid() == (scale == Address::no_scale),
 255              "inconsistent address");
 256   }
 257 
 258   Address plus_disp(int disp) const {
 259     Address a = (*this);
 260     a._disp += disp;
 261     return a;
 262   }
 263   Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
 264     Address a = (*this);
 265     a._disp += disp.constant_or_zero() * scale_size(scale);
 266     if (disp.is_register()) {
 267       assert(!a.index()->is_valid(), "competing indexes");
 268       a._index = disp.as_register();
 269       a._scale = scale;
 270     }
 271     return a;
 272   }
 273   bool is_same_address(Address a) const {
 274     // disregard _rspec
 275     return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
 276   }
 277 
 278   // The following two overloads are used in connection with the
 279   // ByteSize type (see sizes.hpp).  They simplify the use of
 280   // ByteSize'd arguments in assembly code. Note that their equivalent
 281   // for the optimized build are the member functions with int disp
 282   // argument since ByteSize is mapped to an int type in that case.
 283   //
 284   // Note: DO NOT introduce similar overloaded functions for WordSize
 285   // arguments as in the optimized mode, both ByteSize and WordSize
 286   // are mapped to the same type and thus the compiler cannot make a
 287   // distinction anymore (=> compiler errors).
 288 
 289 #ifdef ASSERT
 290   Address(Register base, ByteSize disp)
 291     : _base(base),
 292       _index(noreg),
 293       _xmmindex(xnoreg),
 294       _scale(no_scale),
 295       _disp(in_bytes(disp)),
 296       _isxmmindex(false){
 297   }
 298 
 299   Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
 300     : _base(base),
 301       _index(index),
 302       _xmmindex(xnoreg),
 303       _scale(scale),
 304       _disp(in_bytes(disp)),
 305       _isxmmindex(false){
 306     assert(!index->is_valid() == (scale == Address::no_scale),
 307            "inconsistent address");
 308   }
 309   Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
 310     : _base (base),
 311       _index(index.register_or_noreg()),
 312       _xmmindex(xnoreg),
 313       _scale(scale),
 314       _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))),
 315       _isxmmindex(false) {
 316     if (!index.is_register())  scale = Address::no_scale;
 317     assert(!_index->is_valid() == (scale == Address::no_scale),
 318            "inconsistent address");
 319   }
 320 
 321 #endif // ASSERT
 322 
 323   // accessors
 324   bool        uses(Register reg) const { return _base == reg || _index == reg; }
 325   Register    base()             const { return _base;  }
 326   Register    index()            const { return _index; }
 327   XMMRegister xmmindex()         const { return _xmmindex; }
 328   ScaleFactor scale()            const { return _scale; }
 329   int         disp()             const { return _disp;  }
 330   bool        isxmmindex()       const { return _isxmmindex; }
 331 
 332   // Convert the raw encoding form into the form expected by the constructor for
 333   // Address.  An index of 4 (rsp) corresponds to having no index, so convert
 334   // that to noreg for the Address constructor.
 335   static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
 336 
 337   static Address make_array(ArrayAddress);
 338 
 339  private:
 340   bool base_needs_rex() const {
 341     return _base != noreg && _base->encoding() >= 8;
 342   }
 343 
 344   bool index_needs_rex() const {
 345     return _index != noreg &&_index->encoding() >= 8;
 346   }
 347 
 348   bool xmmindex_needs_rex() const {
 349     return _xmmindex != xnoreg && _xmmindex->encoding() >= 8;
 350   }
 351 
 352   relocInfo::relocType reloc() const { return _rspec.type(); }
 353 
 354   friend class Assembler;
 355   friend class MacroAssembler;
 356   friend class LIR_Assembler; // base/index/scale/disp
 357 };
 358 
 359 //
 360 // AddressLiteral has been split out from Address because operands of this type
 361 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
 362 // the few instructions that need to deal with address literals are unique and the
 363 // MacroAssembler does not have to implement every instruction in the Assembler
 364 // in order to search for address literals that may need special handling depending
 365 // on the instruction and the platform. As small step on the way to merging i486/amd64
 366 // directories.
 367 //
 368 class AddressLiteral {
 369   friend class ArrayAddress;
 370   RelocationHolder _rspec;
 371   // Typically we use AddressLiterals we want to use their rval
 372   // However in some situations we want the lval (effect address) of the item.
 373   // We provide a special factory for making those lvals.
 374   bool _is_lval;
 375 
 376   // If the target is far we'll need to load the ea of this to
 377   // a register to reach it. Otherwise if near we can do rip
 378   // relative addressing.
 379 
 380   address          _target;
 381 
 382  protected:
 383   // creation
 384   AddressLiteral()
 385     : _is_lval(false),
 386       _target(NULL)
 387   {}
 388 
 389   public:
 390 
 391 
 392   AddressLiteral(address target, relocInfo::relocType rtype);
 393 
 394   AddressLiteral(address target, RelocationHolder const& rspec)
 395     : _rspec(rspec),
 396       _is_lval(false),
 397       _target(target)
 398   {}
 399 
 400   AddressLiteral addr() {
 401     AddressLiteral ret = *this;
 402     ret._is_lval = true;
 403     return ret;
 404   }
 405 
 406 
 407  private:
 408 
 409   address target() { return _target; }
 410   bool is_lval() { return _is_lval; }
 411 
 412   relocInfo::relocType reloc() const { return _rspec.type(); }
 413   const RelocationHolder& rspec() const { return _rspec; }
 414 
 415   friend class Assembler;
 416   friend class MacroAssembler;
 417   friend class Address;
 418   friend class LIR_Assembler;
 419 };
 420 
 421 // Convience classes
 422 class RuntimeAddress: public AddressLiteral {
 423 
 424   public:
 425 
 426   RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
 427 
 428 };
 429 
 430 class ExternalAddress: public AddressLiteral {
 431  private:
 432   static relocInfo::relocType reloc_for_target(address target) {
 433     // Sometimes ExternalAddress is used for values which aren't
 434     // exactly addresses, like the card table base.
 435     // external_word_type can't be used for values in the first page
 436     // so just skip the reloc in that case.
 437     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 438   }
 439 
 440  public:
 441 
 442   ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
 443 
 444 };
 445 
 446 class InternalAddress: public AddressLiteral {
 447 
 448   public:
 449 
 450   InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
 451 
 452 };
 453 
 454 // x86 can do array addressing as a single operation since disp can be an absolute
 455 // address amd64 can't. We create a class that expresses the concept but does extra
 456 // magic on amd64 to get the final result
 457 
 458 class ArrayAddress {
 459   private:
 460 
 461   AddressLiteral _base;
 462   Address        _index;
 463 
 464   public:
 465 
 466   ArrayAddress() {};
 467   ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
 468   AddressLiteral base() { return _base; }
 469   Address index() { return _index; }
 470 
 471 };
 472 
 473 class InstructionAttr;
 474 
 475 // 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
 476 // See fxsave and xsave(EVEX enabled) documentation for layout
 477 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
 478 
 479 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
 480 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
 481 // is what you get. The Assembler is generating code into a CodeBuffer.
 482 
 483 class Assembler : public AbstractAssembler  {
 484   friend class AbstractAssembler; // for the non-virtual hack
 485   friend class LIR_Assembler; // as_Address()
 486   friend class StubGenerator;
 487 
 488  public:
 489   enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
 490     zero          = 0x4,
 491     notZero       = 0x5,
 492     equal         = 0x4,
 493     notEqual      = 0x5,
 494     less          = 0xc,
 495     lessEqual     = 0xe,
 496     greater       = 0xf,
 497     greaterEqual  = 0xd,
 498     below         = 0x2,
 499     belowEqual    = 0x6,
 500     above         = 0x7,
 501     aboveEqual    = 0x3,
 502     overflow      = 0x0,
 503     noOverflow    = 0x1,
 504     carrySet      = 0x2,
 505     carryClear    = 0x3,
 506     negative      = 0x8,
 507     positive      = 0x9,
 508     parity        = 0xa,
 509     noParity      = 0xb
 510   };
 511 
 512   enum Prefix {
 513     // segment overrides
 514     CS_segment = 0x2e,
 515     SS_segment = 0x36,
 516     DS_segment = 0x3e,
 517     ES_segment = 0x26,
 518     FS_segment = 0x64,
 519     GS_segment = 0x65,
 520 
 521     REX        = 0x40,
 522 
 523     REX_B      = 0x41,
 524     REX_X      = 0x42,
 525     REX_XB     = 0x43,
 526     REX_R      = 0x44,
 527     REX_RB     = 0x45,
 528     REX_RX     = 0x46,
 529     REX_RXB    = 0x47,
 530 
 531     REX_W      = 0x48,
 532 
 533     REX_WB     = 0x49,
 534     REX_WX     = 0x4A,
 535     REX_WXB    = 0x4B,
 536     REX_WR     = 0x4C,
 537     REX_WRB    = 0x4D,
 538     REX_WRX    = 0x4E,
 539     REX_WRXB   = 0x4F,
 540 
 541     VEX_3bytes = 0xC4,
 542     VEX_2bytes = 0xC5,
 543     EVEX_4bytes = 0x62,
 544     Prefix_EMPTY = 0x0
 545   };
 546 
 547   enum VexPrefix {
 548     VEX_B = 0x20,
 549     VEX_X = 0x40,
 550     VEX_R = 0x80,
 551     VEX_W = 0x80
 552   };
 553 
 554   enum ExexPrefix {
 555     EVEX_F  = 0x04,
 556     EVEX_V  = 0x08,
 557     EVEX_Rb = 0x10,
 558     EVEX_X  = 0x40,
 559     EVEX_Z  = 0x80
 560   };
 561 
 562   enum VexSimdPrefix {
 563     VEX_SIMD_NONE = 0x0,
 564     VEX_SIMD_66   = 0x1,
 565     VEX_SIMD_F3   = 0x2,
 566     VEX_SIMD_F2   = 0x3
 567   };
 568 
 569   enum VexOpcode {
 570     VEX_OPCODE_NONE  = 0x0,
 571     VEX_OPCODE_0F    = 0x1,
 572     VEX_OPCODE_0F_38 = 0x2,
 573     VEX_OPCODE_0F_3A = 0x3,
 574     VEX_OPCODE_MASK  = 0x1F
 575   };
 576 
 577   enum AvxVectorLen {
 578     AVX_128bit = 0x0,
 579     AVX_256bit = 0x1,
 580     AVX_512bit = 0x2,
 581     AVX_NoVec  = 0x4
 582   };
 583 
 584   enum EvexTupleType {
 585     EVEX_FV   = 0,
 586     EVEX_HV   = 4,
 587     EVEX_FVM  = 6,
 588     EVEX_T1S  = 7,
 589     EVEX_T1F  = 11,
 590     EVEX_T2   = 13,
 591     EVEX_T4   = 15,
 592     EVEX_T8   = 17,
 593     EVEX_HVM  = 18,
 594     EVEX_QVM  = 19,
 595     EVEX_OVM  = 20,
 596     EVEX_M128 = 21,
 597     EVEX_DUP  = 22,
 598     EVEX_ETUP = 23
 599   };
 600 
 601   enum EvexInputSizeInBits {
 602     EVEX_8bit  = 0,
 603     EVEX_16bit = 1,
 604     EVEX_32bit = 2,
 605     EVEX_64bit = 3,
 606     EVEX_NObit = 4
 607   };
 608 
 609   enum WhichOperand {
 610     // input to locate_operand, and format code for relocations
 611     imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
 612     disp32_operand = 1,          // embedded 32-bit displacement or address
 613     call32_operand = 2,          // embedded 32-bit self-relative displacement
 614 #ifndef _LP64
 615     _WhichOperand_limit = 3
 616 #else
 617      narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
 618     _WhichOperand_limit = 4
 619 #endif
 620   };
 621 
 622   enum ComparisonPredicate {
 623     eq = 0,
 624     lt = 1,
 625     le = 2,
 626     _false = 3,
 627     neq = 4,
 628     nlt = 5,
 629     nle = 6,
 630     _true = 7
 631   };
 632 
 633 
 634   // NOTE: The general philopsophy of the declarations here is that 64bit versions
 635   // of instructions are freely declared without the need for wrapping them an ifdef.
 636   // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
 637   // In the .cpp file the implementations are wrapped so that they are dropped out
 638   // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
 639   // to the size it was prior to merging up the 32bit and 64bit assemblers.
 640   //
 641   // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
 642   // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
 643 
 644 private:
 645 
 646   bool _legacy_mode_bw;
 647   bool _legacy_mode_dq;
 648   bool _legacy_mode_vl;
 649   bool _legacy_mode_vlbw;
 650   bool _is_managed;
 651   bool _vector_masking;    // For stub code use only
 652 
 653   class InstructionAttr *_attributes;
 654 
 655   // 64bit prefixes
 656   int prefix_and_encode(int reg_enc, bool byteinst = false);
 657   int prefixq_and_encode(int reg_enc);
 658 
 659   int prefix_and_encode(int dst_enc, int src_enc) {
 660     return prefix_and_encode(dst_enc, false, src_enc, false);
 661   }
 662   int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
 663   int prefixq_and_encode(int dst_enc, int src_enc);
 664 
 665   void prefix(Register reg);
 666   void prefix(Register dst, Register src, Prefix p);
 667   void prefix(Register dst, Address adr, Prefix p);
 668   void prefix(Address adr);
 669   void prefixq(Address adr);
 670 
 671   void prefix(Address adr, Register reg,  bool byteinst = false);
 672   void prefix(Address adr, XMMRegister reg);
 673   void prefixq(Address adr, Register reg);
 674   void prefixq(Address adr, XMMRegister reg);
 675 
 676   void prefetch_prefix(Address src);
 677 
 678   void rex_prefix(Address adr, XMMRegister xreg,
 679                   VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 680   int  rex_prefix_and_encode(int dst_enc, int src_enc,
 681                              VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 682 
 683   void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
 684 
 685   void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
 686                    int nds_enc, VexSimdPrefix pre, VexOpcode opc);
 687 
 688   void vex_prefix(Address adr, int nds_enc, int xreg_enc,
 689                   VexSimdPrefix pre, VexOpcode opc,
 690                   InstructionAttr *attributes);
 691 
 692   int  vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
 693                              VexSimdPrefix pre, VexOpcode opc,
 694                              InstructionAttr *attributes);
 695 
 696   void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
 697                    VexOpcode opc, InstructionAttr *attributes);
 698 
 699   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
 700                              VexOpcode opc, InstructionAttr *attributes);
 701 
 702   // Helper functions for groups of instructions
 703   void emit_arith_b(int op1, int op2, Register dst, int imm8);
 704 
 705   void emit_arith(int op1, int op2, Register dst, int32_t imm32);
 706   // Force generation of a 4 byte immediate value even if it fits into 8bit
 707   void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
 708   void emit_arith(int op1, int op2, Register dst, Register src);
 709 
 710   bool emit_compressed_disp_byte(int &disp);
 711 
 712   void emit_operand(Register reg,
 713                     Register base, Register index, Address::ScaleFactor scale,
 714                     int disp,
 715                     RelocationHolder const& rspec,
 716                     int rip_relative_correction = 0);
 717 
 718   void emit_operand(XMMRegister reg, Register base, XMMRegister index,
 719                     Address::ScaleFactor scale,
 720                     int disp, RelocationHolder const& rspec);
 721 
 722   void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
 723 
 724   // operands that only take the original 32bit registers
 725   void emit_operand32(Register reg, Address adr);
 726 
 727   void emit_operand(XMMRegister reg,
 728                     Register base, Register index, Address::ScaleFactor scale,
 729                     int disp,
 730                     RelocationHolder const& rspec);
 731 
 732   void emit_operand(XMMRegister reg, Address adr);
 733 
 734   void emit_operand(MMXRegister reg, Address adr);
 735 
 736   // workaround gcc (3.2.1-7) bug
 737   void emit_operand(Address adr, MMXRegister reg);
 738 
 739 
 740   // Immediate-to-memory forms
 741   void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
 742 
 743   void emit_farith(int b1, int b2, int i);
 744 
 745 
 746  protected:
 747   #ifdef ASSERT
 748   void check_relocation(RelocationHolder const& rspec, int format);
 749   #endif
 750 
 751   void emit_data(jint data, relocInfo::relocType    rtype, int format);
 752   void emit_data(jint data, RelocationHolder const& rspec, int format);
 753   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
 754   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
 755 
 756   bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
 757 
 758   // These are all easily abused and hence protected
 759 
 760   // 32BIT ONLY SECTION
 761 #ifndef _LP64
 762   // Make these disappear in 64bit mode since they would never be correct
 763   void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);   // 32BIT ONLY
 764   void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 765 
 766   void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 767   void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);     // 32BIT ONLY
 768 
 769   void push_literal32(int32_t imm32, RelocationHolder const& rspec);                 // 32BIT ONLY
 770 #else
 771   // 64BIT ONLY SECTION
 772   void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);   // 64BIT ONLY
 773 
 774   void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
 775   void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
 776 
 777   void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
 778   void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
 779 #endif // _LP64
 780 
 781   // These are unique in that we are ensured by the caller that the 32bit
 782   // relative in these instructions will always be able to reach the potentially
 783   // 64bit address described by entry. Since they can take a 64bit address they
 784   // don't have the 32 suffix like the other instructions in this class.
 785 
 786   void call_literal(address entry, RelocationHolder const& rspec);
 787   void jmp_literal(address entry, RelocationHolder const& rspec);
 788 
 789   // Avoid using directly section
 790   // Instructions in this section are actually usable by anyone without danger
 791   // of failure but have performance issues that are addressed my enhanced
 792   // instructions which will do the proper thing base on the particular cpu.
 793   // We protect them because we don't trust you...
 794 
 795   // Don't use next inc() and dec() methods directly. INC & DEC instructions
 796   // could cause a partial flag stall since they don't set CF flag.
 797   // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
 798   // which call inc() & dec() or add() & sub() in accordance with
 799   // the product flag UseIncDec value.
 800 
 801   void decl(Register dst);
 802   void decl(Address dst);
 803   void decq(Register dst);
 804   void decq(Address dst);
 805 
 806   void incl(Register dst);
 807   void incl(Address dst);
 808   void incq(Register dst);
 809   void incq(Address dst);
 810 
 811   // New cpus require use of movsd and movss to avoid partial register stall
 812   // when loading from memory. But for old Opteron use movlpd instead of movsd.
 813   // The selection is done in MacroAssembler::movdbl() and movflt().
 814 
 815   // Move Scalar Single-Precision Floating-Point Values
 816   void movss(XMMRegister dst, Address src);
 817   void movss(XMMRegister dst, XMMRegister src);
 818   void movss(Address dst, XMMRegister src);
 819 
 820   // Move Scalar Double-Precision Floating-Point Values
 821   void movsd(XMMRegister dst, Address src);
 822   void movsd(XMMRegister dst, XMMRegister src);
 823   void movsd(Address dst, XMMRegister src);
 824   void movlpd(XMMRegister dst, Address src);
 825 
 826   // New cpus require use of movaps and movapd to avoid partial register stall
 827   // when moving between registers.
 828   void movaps(XMMRegister dst, XMMRegister src);
 829   void movapd(XMMRegister dst, XMMRegister src);
 830 
 831   // End avoid using directly
 832 
 833 
 834   // Instruction prefixes
 835   void prefix(Prefix p);
 836 
 837   public:
 838 
 839   // Creation
 840   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
 841     init_attributes();
 842   }
 843 
 844   // Decoding
 845   static address locate_operand(address inst, WhichOperand which);
 846   static address locate_next_instruction(address inst);
 847 
 848   // Utilities
 849   static bool is_polling_page_far() NOT_LP64({ return false;});
 850   static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
 851                                          int cur_tuple_type, int in_size_in_bits, int cur_encoding);
 852 
 853   // Generic instructions
 854   // Does 32bit or 64bit as needed for the platform. In some sense these
 855   // belong in macro assembler but there is no need for both varieties to exist
 856 
 857   void init_attributes(void) {
 858     _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
 859     _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
 860     _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
 861     _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
 862     _is_managed = false;
 863     _vector_masking = false;
 864     _attributes = NULL;
 865   }
 866 
 867   void set_attributes(InstructionAttr *attributes) { _attributes = attributes; }
 868   void clear_attributes(void) { _attributes = NULL; }
 869 
 870   void set_managed(void) { _is_managed = true; }
 871   void clear_managed(void) { _is_managed = false; }
 872   bool is_managed(void) { return _is_managed; }
 873 
 874   void lea(Register dst, Address src);
 875 
 876   void mov(Register dst, Register src);
 877 
 878   void pusha();
 879   void popa();
 880 
 881   void pushf();
 882   void popf();
 883 
 884   void push(int32_t imm32);
 885 
 886   void push(Register src);
 887 
 888   void pop(Register dst);
 889 
 890   // These are dummies to prevent surprise implicit conversions to Register
 891   void push(void* v);
 892   void pop(void* v);
 893 
 894   // These do register sized moves/scans
 895   void rep_mov();
 896   void rep_stos();
 897   void rep_stosb();
 898   void repne_scan();
 899 #ifdef _LP64
 900   void repne_scanl();
 901 #endif
 902 
 903   // Vanilla instructions in lexical order
 904 
 905   void adcl(Address dst, int32_t imm32);
 906   void adcl(Address dst, Register src);
 907   void adcl(Register dst, int32_t imm32);
 908   void adcl(Register dst, Address src);
 909   void adcl(Register dst, Register src);
 910 
 911   void adcq(Register dst, int32_t imm32);
 912   void adcq(Register dst, Address src);
 913   void adcq(Register dst, Register src);
 914 
 915   void addb(Address dst, int imm8);
 916   void addw(Address dst, int imm16);
 917 
 918   void addl(Address dst, int32_t imm32);
 919   void addl(Address dst, Register src);
 920   void addl(Register dst, int32_t imm32);
 921   void addl(Register dst, Address src);
 922   void addl(Register dst, Register src);
 923 
 924   void addq(Address dst, int32_t imm32);
 925   void addq(Address dst, Register src);
 926   void addq(Register dst, int32_t imm32);
 927   void addq(Register dst, Address src);
 928   void addq(Register dst, Register src);
 929 
 930 #ifdef _LP64
 931  //Add Unsigned Integers with Carry Flag
 932   void adcxq(Register dst, Register src);
 933 
 934  //Add Unsigned Integers with Overflow Flag
 935   void adoxq(Register dst, Register src);
 936 #endif
 937 
 938   void addr_nop_4();
 939   void addr_nop_5();
 940   void addr_nop_7();
 941   void addr_nop_8();
 942 
 943   // Add Scalar Double-Precision Floating-Point Values
 944   void addsd(XMMRegister dst, Address src);
 945   void addsd(XMMRegister dst, XMMRegister src);
 946 
 947   // Add Scalar Single-Precision Floating-Point Values
 948   void addss(XMMRegister dst, Address src);
 949   void addss(XMMRegister dst, XMMRegister src);
 950 
 951   // AES instructions
 952   void aesdec(XMMRegister dst, Address src);
 953   void aesdec(XMMRegister dst, XMMRegister src);
 954   void aesdeclast(XMMRegister dst, Address src);
 955   void aesdeclast(XMMRegister dst, XMMRegister src);
 956   void aesenc(XMMRegister dst, Address src);
 957   void aesenc(XMMRegister dst, XMMRegister src);
 958   void aesenclast(XMMRegister dst, Address src);
 959   void aesenclast(XMMRegister dst, XMMRegister src);
 960   void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 961   void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 962 
 963   void andl(Address  dst, int32_t imm32);
 964   void andl(Register dst, int32_t imm32);
 965   void andl(Register dst, Address src);
 966   void andl(Register dst, Register src);
 967 
 968   void andq(Address  dst, int32_t imm32);
 969   void andq(Register dst, int32_t imm32);
 970   void andq(Register dst, Address src);
 971   void andq(Register dst, Register src);
 972 
 973   // BMI instructions
 974   void andnl(Register dst, Register src1, Register src2);
 975   void andnl(Register dst, Register src1, Address src2);
 976   void andnq(Register dst, Register src1, Register src2);
 977   void andnq(Register dst, Register src1, Address src2);
 978 
 979   void blsil(Register dst, Register src);
 980   void blsil(Register dst, Address src);
 981   void blsiq(Register dst, Register src);
 982   void blsiq(Register dst, Address src);
 983 
 984   void blsmskl(Register dst, Register src);
 985   void blsmskl(Register dst, Address src);
 986   void blsmskq(Register dst, Register src);
 987   void blsmskq(Register dst, Address src);
 988 
 989   void blsrl(Register dst, Register src);
 990   void blsrl(Register dst, Address src);
 991   void blsrq(Register dst, Register src);
 992   void blsrq(Register dst, Address src);
 993 
 994   void bsfl(Register dst, Register src);
 995   void bsrl(Register dst, Register src);
 996 
 997 #ifdef _LP64
 998   void bsfq(Register dst, Register src);
 999   void bsrq(Register dst, Register src);
1000 #endif
1001 
1002   void bswapl(Register reg);
1003 
1004   void bswapq(Register reg);
1005 
1006   void call(Label& L, relocInfo::relocType rtype);
1007   void call(Register reg);  // push pc; pc <- reg
1008   void call(Address adr);   // push pc; pc <- adr
1009 
1010   void cdql();
1011 
1012   void cdqq();
1013 
1014   void cld();
1015 
1016   void clflush(Address adr);
1017 
1018   void cmovl(Condition cc, Register dst, Register src);
1019   void cmovl(Condition cc, Register dst, Address src);
1020 
1021   void cmovq(Condition cc, Register dst, Register src);
1022   void cmovq(Condition cc, Register dst, Address src);
1023 
1024 
1025   void cmpb(Address dst, int imm8);
1026 
1027   void cmpl(Address dst, int32_t imm32);
1028 
1029   void cmpl(Register dst, int32_t imm32);
1030   void cmpl(Register dst, Register src);
1031   void cmpl(Register dst, Address src);
1032 
1033   void cmpq(Address dst, int32_t imm32);
1034   void cmpq(Address dst, Register src);
1035 
1036   void cmpq(Register dst, int32_t imm32);
1037   void cmpq(Register dst, Register src);
1038   void cmpq(Register dst, Address src);
1039 
1040   // these are dummies used to catch attempting to convert NULL to Register
1041   void cmpl(Register dst, void* junk); // dummy
1042   void cmpq(Register dst, void* junk); // dummy
1043 
1044   void cmpw(Address dst, int imm16);
1045 
1046   void cmpxchg8 (Address adr);
1047 
1048   void cmpxchgb(Register reg, Address adr);
1049   void cmpxchgl(Register reg, Address adr);
1050 
1051   void cmpxchgq(Register reg, Address adr);
1052 
1053   // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1054   void comisd(XMMRegister dst, Address src);
1055   void comisd(XMMRegister dst, XMMRegister src);
1056 
1057   // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1058   void comiss(XMMRegister dst, Address src);
1059   void comiss(XMMRegister dst, XMMRegister src);
1060 
1061   // Identify processor type and features
1062   void cpuid();
1063 
1064   // CRC32C
1065   void crc32(Register crc, Register v, int8_t sizeInBytes);
1066   void crc32(Register crc, Address adr, int8_t sizeInBytes);
1067 
1068   // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1069   void cvtsd2ss(XMMRegister dst, XMMRegister src);
1070   void cvtsd2ss(XMMRegister dst, Address src);
1071 
1072   // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1073   void cvtsi2sdl(XMMRegister dst, Register src);
1074   void cvtsi2sdl(XMMRegister dst, Address src);
1075   void cvtsi2sdq(XMMRegister dst, Register src);
1076   void cvtsi2sdq(XMMRegister dst, Address src);
1077 
1078   // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1079   void cvtsi2ssl(XMMRegister dst, Register src);
1080   void cvtsi2ssl(XMMRegister dst, Address src);
1081   void cvtsi2ssq(XMMRegister dst, Register src);
1082   void cvtsi2ssq(XMMRegister dst, Address src);
1083 
1084   // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1085   void cvtdq2pd(XMMRegister dst, XMMRegister src);
1086 
1087   // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1088   void cvtdq2ps(XMMRegister dst, XMMRegister src);
1089 
1090   // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1091   void cvtss2sd(XMMRegister dst, XMMRegister src);
1092   void cvtss2sd(XMMRegister dst, Address src);
1093 
1094   // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1095   void cvttsd2sil(Register dst, Address src);
1096   void cvttsd2sil(Register dst, XMMRegister src);
1097   void cvttsd2siq(Register dst, XMMRegister src);
1098 
1099   // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1100   void cvttss2sil(Register dst, XMMRegister src);
1101   void cvttss2siq(Register dst, XMMRegister src);
1102 
1103   void cvttpd2dq(XMMRegister dst, XMMRegister src);
1104 
1105   //Abs of packed Integer values
1106   void pabsb(XMMRegister dst, XMMRegister src);
1107   void pabsw(XMMRegister dst, XMMRegister src);
1108   void pabsd(XMMRegister dst, XMMRegister src);
1109   void vpabsb(XMMRegister dst, XMMRegister src, int vector_len);
1110   void vpabsw(XMMRegister dst, XMMRegister src, int vector_len);
1111   void vpabsd(XMMRegister dst, XMMRegister src, int vector_len);
1112   void evpabsq(XMMRegister dst, XMMRegister src, int vector_len);
1113 
1114   // Divide Scalar Double-Precision Floating-Point Values
1115   void divsd(XMMRegister dst, Address src);
1116   void divsd(XMMRegister dst, XMMRegister src);
1117 
1118   // Divide Scalar Single-Precision Floating-Point Values
1119   void divss(XMMRegister dst, Address src);
1120   void divss(XMMRegister dst, XMMRegister src);
1121 
1122   void emms();
1123 
1124   void fabs();
1125 
1126   void fadd(int i);
1127 
1128   void fadd_d(Address src);
1129   void fadd_s(Address src);
1130 
1131   // "Alternate" versions of x87 instructions place result down in FPU
1132   // stack instead of on TOS
1133 
1134   void fadda(int i); // "alternate" fadd
1135   void faddp(int i = 1);
1136 
1137   void fchs();
1138 
1139   void fcom(int i);
1140 
1141   void fcomp(int i = 1);
1142   void fcomp_d(Address src);
1143   void fcomp_s(Address src);
1144 
1145   void fcompp();
1146 
1147   void fcos();
1148 
1149   void fdecstp();
1150 
1151   void fdiv(int i);
1152   void fdiv_d(Address src);
1153   void fdivr_s(Address src);
1154   void fdiva(int i);  // "alternate" fdiv
1155   void fdivp(int i = 1);
1156 
1157   void fdivr(int i);
1158   void fdivr_d(Address src);
1159   void fdiv_s(Address src);
1160 
1161   void fdivra(int i); // "alternate" reversed fdiv
1162 
1163   void fdivrp(int i = 1);
1164 
1165   void ffree(int i = 0);
1166 
1167   void fild_d(Address adr);
1168   void fild_s(Address adr);
1169 
1170   void fincstp();
1171 
1172   void finit();
1173 
1174   void fist_s (Address adr);
1175   void fistp_d(Address adr);
1176   void fistp_s(Address adr);
1177 
1178   void fld1();
1179 
1180   void fld_d(Address adr);
1181   void fld_s(Address adr);
1182   void fld_s(int index);
1183   void fld_x(Address adr);  // extended-precision (80-bit) format
1184 
1185   void fldcw(Address src);
1186 
1187   void fldenv(Address src);
1188 
1189   void fldlg2();
1190 
1191   void fldln2();
1192 
1193   void fldz();
1194 
1195   void flog();
1196   void flog10();
1197 
1198   void fmul(int i);
1199 
1200   void fmul_d(Address src);
1201   void fmul_s(Address src);
1202 
1203   void fmula(int i);  // "alternate" fmul
1204 
1205   void fmulp(int i = 1);
1206 
1207   void fnsave(Address dst);
1208 
1209   void fnstcw(Address src);
1210 
1211   void fnstsw_ax();
1212 
1213   void fprem();
1214   void fprem1();
1215 
1216   void frstor(Address src);
1217 
1218   void fsin();
1219 
1220   void fsqrt();
1221 
1222   void fst_d(Address adr);
1223   void fst_s(Address adr);
1224 
1225   void fstp_d(Address adr);
1226   void fstp_d(int index);
1227   void fstp_s(Address adr);
1228   void fstp_x(Address adr); // extended-precision (80-bit) format
1229 
1230   void fsub(int i);
1231   void fsub_d(Address src);
1232   void fsub_s(Address src);
1233 
1234   void fsuba(int i);  // "alternate" fsub
1235 
1236   void fsubp(int i = 1);
1237 
1238   void fsubr(int i);
1239   void fsubr_d(Address src);
1240   void fsubr_s(Address src);
1241 
1242   void fsubra(int i); // "alternate" reversed fsub
1243 
1244   void fsubrp(int i = 1);
1245 
1246   void ftan();
1247 
1248   void ftst();
1249 
1250   void fucomi(int i = 1);
1251   void fucomip(int i = 1);
1252 
1253   void fwait();
1254 
1255   void fxch(int i = 1);
1256 
1257   void fxrstor(Address src);
1258   void xrstor(Address src);
1259 
1260   void fxsave(Address dst);
1261   void xsave(Address dst);
1262 
1263   void fyl2x();
1264   void frndint();
1265   void f2xm1();
1266   void fldl2e();
1267 
1268   void hlt();
1269 
1270   void idivl(Register src);
1271   void divl(Register src); // Unsigned division
1272 
1273 #ifdef _LP64
1274   void idivq(Register src);
1275 #endif
1276 
1277   void imull(Register src);
1278   void imull(Register dst, Register src);
1279   void imull(Register dst, Register src, int value);
1280   void imull(Register dst, Address src);
1281 
1282 #ifdef _LP64
1283   void imulq(Register dst, Register src);
1284   void imulq(Register dst, Register src, int value);
1285   void imulq(Register dst, Address src);
1286 #endif
1287 
1288   // jcc is the generic conditional branch generator to run-
1289   // time routines, jcc is used for branches to labels. jcc
1290   // takes a branch opcode (cc) and a label (L) and generates
1291   // either a backward branch or a forward branch and links it
1292   // to the label fixup chain. Usage:
1293   //
1294   // Label L;      // unbound label
1295   // jcc(cc, L);   // forward branch to unbound label
1296   // bind(L);      // bind label to the current pc
1297   // jcc(cc, L);   // backward branch to bound label
1298   // bind(L);      // illegal: a label may be bound only once
1299   //
1300   // Note: The same Label can be used for forward and backward branches
1301   // but it may be bound only once.
1302 
1303   void jcc(Condition cc, Label& L, bool maybe_short = true);
1304 
1305   // Conditional jump to a 8-bit offset to L.
1306   // WARNING: be very careful using this for forward jumps.  If the label is
1307   // not bound within an 8-bit offset of this instruction, a run-time error
1308   // will occur.
1309 
1310   // Use macro to record file and line number.
1311   #define jccb(cc, L) jccb_0(cc, L, __FILE__, __LINE__)
1312 
1313   void jccb_0(Condition cc, Label& L, const char* file, int line);
1314 
1315   void jmp(Address entry);    // pc <- entry
1316 
1317   // Label operations & relative jumps (PPUM Appendix D)
1318   void jmp(Label& L, bool maybe_short = true);   // unconditional jump to L
1319 
1320   void jmp(Register entry); // pc <- entry
1321 
1322   // Unconditional 8-bit offset jump to L.
1323   // WARNING: be very careful using this for forward jumps.  If the label is
1324   // not bound within an 8-bit offset of this instruction, a run-time error
1325   // will occur.
1326 
1327   // Use macro to record file and line number.
1328   #define jmpb(L) jmpb_0(L, __FILE__, __LINE__)
1329 
1330   void jmpb_0(Label& L, const char* file, int line);
1331 
1332   void ldmxcsr( Address src );
1333 
1334   void leal(Register dst, Address src);
1335 
1336   void leaq(Register dst, Address src);
1337 
1338   void lfence();
1339 
1340   void lock();
1341 
1342   void lzcntl(Register dst, Register src);
1343 
1344 #ifdef _LP64
1345   void lzcntq(Register dst, Register src);
1346 #endif
1347 
1348   enum Membar_mask_bits {
1349     StoreStore = 1 << 3,
1350     LoadStore  = 1 << 2,
1351     StoreLoad  = 1 << 1,
1352     LoadLoad   = 1 << 0
1353   };
1354 
1355   // Serializes memory and blows flags
1356   void membar(Membar_mask_bits order_constraint) {
1357     // We only have to handle StoreLoad
1358     if (order_constraint & StoreLoad) {
1359       // All usable chips support "locked" instructions which suffice
1360       // as barriers, and are much faster than the alternative of
1361       // using cpuid instruction. We use here a locked add [esp-C],0.
1362       // This is conveniently otherwise a no-op except for blowing
1363       // flags, and introducing a false dependency on target memory
1364       // location. We can't do anything with flags, but we can avoid
1365       // memory dependencies in the current method by locked-adding
1366       // somewhere else on the stack. Doing [esp+C] will collide with
1367       // something on stack in current method, hence we go for [esp-C].
1368       // It is convenient since it is almost always in data cache, for
1369       // any small C.  We need to step back from SP to avoid data
1370       // dependencies with other things on below SP (callee-saves, for
1371       // example). Without a clear way to figure out the minimal safe
1372       // distance from SP, it makes sense to step back the complete
1373       // cache line, as this will also avoid possible second-order effects
1374       // with locked ops against the cache line. Our choice of offset
1375       // is bounded by x86 operand encoding, which should stay within
1376       // [-128; +127] to have the 8-byte displacement encoding.
1377       //
1378       // Any change to this code may need to revisit other places in
1379       // the code where this idiom is used, in particular the
1380       // orderAccess code.
1381 
1382       int offset = -VM_Version::L1_line_size();
1383       if (offset < -128) {
1384         offset = -128;
1385       }
1386 
1387       lock();
1388       addl(Address(rsp, offset), 0);// Assert the lock# signal here
1389     }
1390   }
1391 
1392   void mfence();
1393 
1394   // Moves
1395 
1396   void mov64(Register dst, int64_t imm64);
1397 
1398   void movb(Address dst, Register src);
1399   void movb(Address dst, int imm8);
1400   void movb(Register dst, Address src);
1401 
1402   void movddup(XMMRegister dst, XMMRegister src);
1403 
1404   void kmovbl(KRegister dst, Register src);
1405   void kmovbl(Register dst, KRegister src);
1406   void kmovwl(KRegister dst, Register src);
1407   void kmovwl(KRegister dst, Address src);
1408   void kmovwl(Register dst, KRegister src);
1409   void kmovdl(KRegister dst, Register src);
1410   void kmovdl(Register dst, KRegister src);
1411   void kmovql(KRegister dst, KRegister src);
1412   void kmovql(Address dst, KRegister src);
1413   void kmovql(KRegister dst, Address src);
1414   void kmovql(KRegister dst, Register src);
1415   void kmovql(Register dst, KRegister src);
1416 
1417   void knotwl(KRegister dst, KRegister src);
1418 
1419   void kortestbl(KRegister dst, KRegister src);
1420   void kortestwl(KRegister dst, KRegister src);
1421   void kortestdl(KRegister dst, KRegister src);
1422   void kortestql(KRegister dst, KRegister src);
1423 
1424   void ktestq(KRegister src1, KRegister src2);
1425   void ktestd(KRegister src1, KRegister src2);
1426 
1427   void ktestql(KRegister dst, KRegister src);
1428 
1429   void movdl(XMMRegister dst, Register src);
1430   void movdl(Register dst, XMMRegister src);
1431   void movdl(XMMRegister dst, Address src);
1432   void movdl(Address dst, XMMRegister src);
1433 
1434   // Move Double Quadword
1435   void movdq(XMMRegister dst, Register src);
1436   void movdq(Register dst, XMMRegister src);
1437 
1438   // Move Aligned Double Quadword
1439   void movdqa(XMMRegister dst, XMMRegister src);
1440   void movdqa(XMMRegister dst, Address src);
1441 
1442   // Move Unaligned Double Quadword
1443   void movdqu(Address     dst, XMMRegister src);
1444   void movdqu(XMMRegister dst, Address src);
1445   void movdqu(XMMRegister dst, XMMRegister src);
1446 
1447   // Move Unaligned 256bit Vector
1448   void vmovdqu(Address dst, XMMRegister src);
1449   void vmovdqu(XMMRegister dst, Address src);
1450   void vmovdqu(XMMRegister dst, XMMRegister src);
1451 
1452    // Move Unaligned 512bit Vector
1453   void evmovdqub(Address dst, XMMRegister src, int vector_len);
1454   void evmovdqub(XMMRegister dst, Address src, int vector_len);
1455   void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len);
1456   void evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len);
1457   void evmovdquw(Address dst, XMMRegister src, int vector_len);
1458   void evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len);
1459   void evmovdquw(XMMRegister dst, Address src, int vector_len);
1460   void evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1461   void evmovdqul(Address dst, XMMRegister src, int vector_len);
1462   void evmovdqul(XMMRegister dst, Address src, int vector_len);
1463   void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1464   void evmovdquq(Address dst, XMMRegister src, int vector_len);
1465   void evmovdquq(XMMRegister dst, Address src, int vector_len);
1466   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1467 
1468   // Move lower 64bit to high 64bit in 128bit register
1469   void movlhps(XMMRegister dst, XMMRegister src);
1470 
1471   void movl(Register dst, int32_t imm32);
1472   void movl(Address dst, int32_t imm32);
1473   void movl(Register dst, Register src);
1474   void movl(Register dst, Address src);
1475   void movl(Address dst, Register src);
1476 
1477   // These dummies prevent using movl from converting a zero (like NULL) into Register
1478   // by giving the compiler two choices it can't resolve
1479 
1480   void movl(Address  dst, void* junk);
1481   void movl(Register dst, void* junk);
1482 
1483 #ifdef _LP64
1484   void movq(Register dst, Register src);
1485   void movq(Register dst, Address src);
1486   void movq(Address  dst, Register src);
1487 #endif
1488 
1489   void movq(Address     dst, MMXRegister src );
1490   void movq(MMXRegister dst, Address src );
1491 
1492 #ifdef _LP64
1493   // These dummies prevent using movq from converting a zero (like NULL) into Register
1494   // by giving the compiler two choices it can't resolve
1495 
1496   void movq(Address  dst, void* dummy);
1497   void movq(Register dst, void* dummy);
1498 #endif
1499 
1500   // Move Quadword
1501   void movq(Address     dst, XMMRegister src);
1502   void movq(XMMRegister dst, Address src);
1503 
1504   void movsbl(Register dst, Address src);
1505   void movsbl(Register dst, Register src);
1506 
1507 #ifdef _LP64
1508   void movsbq(Register dst, Address src);
1509   void movsbq(Register dst, Register src);
1510 
1511   // Move signed 32bit immediate to 64bit extending sign
1512   void movslq(Address  dst, int32_t imm64);
1513   void movslq(Register dst, int32_t imm64);
1514 
1515   void movslq(Register dst, Address src);
1516   void movslq(Register dst, Register src);
1517   void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1518 #endif
1519 
1520   void movswl(Register dst, Address src);
1521   void movswl(Register dst, Register src);
1522 
1523 #ifdef _LP64
1524   void movswq(Register dst, Address src);
1525   void movswq(Register dst, Register src);
1526 #endif
1527 
1528   void movw(Address dst, int imm16);
1529   void movw(Register dst, Address src);
1530   void movw(Address dst, Register src);
1531 
1532   void movzbl(Register dst, Address src);
1533   void movzbl(Register dst, Register src);
1534 
1535 #ifdef _LP64
1536   void movzbq(Register dst, Address src);
1537   void movzbq(Register dst, Register src);
1538 #endif
1539 
1540   void movzwl(Register dst, Address src);
1541   void movzwl(Register dst, Register src);
1542 
1543 #ifdef _LP64
1544   void movzwq(Register dst, Address src);
1545   void movzwq(Register dst, Register src);
1546 #endif
1547 
1548   // Unsigned multiply with RAX destination register
1549   void mull(Address src);
1550   void mull(Register src);
1551 
1552 #ifdef _LP64
1553   void mulq(Address src);
1554   void mulq(Register src);
1555   void mulxq(Register dst1, Register dst2, Register src);
1556 #endif
1557 
1558   // Multiply Scalar Double-Precision Floating-Point Values
1559   void mulsd(XMMRegister dst, Address src);
1560   void mulsd(XMMRegister dst, XMMRegister src);
1561 
1562   // Multiply Scalar Single-Precision Floating-Point Values
1563   void mulss(XMMRegister dst, Address src);
1564   void mulss(XMMRegister dst, XMMRegister src);
1565 
1566   void negl(Register dst);
1567 
1568 #ifdef _LP64
1569   void negq(Register dst);
1570 #endif
1571 
1572   void nop(int i = 1);
1573 
1574   void notl(Register dst);
1575 
1576 #ifdef _LP64
1577   void notq(Register dst);
1578 #endif
1579 
1580   void orl(Address dst, int32_t imm32);
1581   void orl(Register dst, int32_t imm32);
1582   void orl(Register dst, Address src);
1583   void orl(Register dst, Register src);
1584   void orl(Address dst, Register src);
1585 
1586   void orb(Address dst, int imm8);
1587 
1588   void orq(Address dst, int32_t imm32);
1589   void orq(Register dst, int32_t imm32);
1590   void orq(Register dst, Address src);
1591   void orq(Register dst, Register src);
1592 
1593   // Pack with unsigned saturation
1594   void packuswb(XMMRegister dst, XMMRegister src);
1595   void packuswb(XMMRegister dst, Address src);
1596   void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1597 
1598   // Pemutation of 64bit words
1599   void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1600   void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1601   void vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1602   void vperm2i128(XMMRegister dst,  XMMRegister nds, XMMRegister src, int imm8);
1603   void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1604   void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1605 
1606   void pause();
1607 
1608   // Undefined Instruction
1609   void ud2();
1610 
1611   // SSE4.2 string instructions
1612   void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1613   void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1614 
1615   void pcmpeqb(XMMRegister dst, XMMRegister src);
1616   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1617   void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1618   void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1619   void evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1620 
1621   void evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1622   void evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1623 
1624   void evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len);
1625   void evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate of, int vector_len);
1626   void evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len);
1627 
1628   void pcmpeqw(XMMRegister dst, XMMRegister src);
1629   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1630   void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1631   void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1632 
1633   void pcmpeqd(XMMRegister dst, XMMRegister src);
1634   void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1635   void evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1636   void evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1637 
1638   void pcmpeqq(XMMRegister dst, XMMRegister src);
1639   void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1640   void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1641   void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1642 
1643   void pmovmskb(Register dst, XMMRegister src);
1644   void vpmovmskb(Register dst, XMMRegister src);
1645 
1646   // SSE 4.1 extract
1647   void pextrd(Register dst, XMMRegister src, int imm8);
1648   void pextrq(Register dst, XMMRegister src, int imm8);
1649   void pextrd(Address dst, XMMRegister src, int imm8);
1650   void pextrq(Address dst, XMMRegister src, int imm8);
1651   void pextrb(Address dst, XMMRegister src, int imm8);
1652   // SSE 2 extract
1653   void pextrw(Register dst, XMMRegister src, int imm8);
1654   void pextrw(Address dst, XMMRegister src, int imm8);
1655 
1656   // SSE 4.1 insert
1657   void pinsrd(XMMRegister dst, Register src, int imm8);
1658   void pinsrq(XMMRegister dst, Register src, int imm8);
1659   void pinsrd(XMMRegister dst, Address src, int imm8);
1660   void pinsrq(XMMRegister dst, Address src, int imm8);
1661   void pinsrb(XMMRegister dst, Address src, int imm8);
1662   // SSE 2 insert
1663   void pinsrw(XMMRegister dst, Register src, int imm8);
1664   void pinsrw(XMMRegister dst, Address src, int imm8);
1665 
1666   // SSE4.1 packed move
1667   void pmovzxbw(XMMRegister dst, XMMRegister src);
1668   void pmovzxbw(XMMRegister dst, Address src);
1669 
1670   void vpmovzxbw( XMMRegister dst, Address src, int vector_len);
1671   void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len);
1672   void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1673 
1674   void evpmovwb(Address dst, XMMRegister src, int vector_len);
1675   void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len);
1676 
1677   void vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len);
1678 
1679   void evpmovdb(Address dst, XMMRegister src, int vector_len);
1680 
1681   // Sign extend moves
1682   void pmovsxbw(XMMRegister dst, XMMRegister src);
1683   void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len);
1684 
1685   // Multiply add
1686   void pmaddwd(XMMRegister dst, XMMRegister src);
1687   void vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1688   // Multiply add accumulate
1689   void evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1690 
1691 #ifndef _LP64 // no 32bit push/pop on amd64
1692   void popl(Address dst);
1693 #endif
1694 
1695 #ifdef _LP64
1696   void popq(Address dst);
1697 #endif
1698 
1699   void popcntl(Register dst, Address src);
1700   void popcntl(Register dst, Register src);
1701 
1702   void vpopcntd(XMMRegister dst, XMMRegister src, int vector_len);
1703 
1704 #ifdef _LP64
1705   void popcntq(Register dst, Address src);
1706   void popcntq(Register dst, Register src);
1707 #endif
1708 
1709   // Prefetches (SSE, SSE2, 3DNOW only)
1710 
1711   void prefetchnta(Address src);
1712   void prefetchr(Address src);
1713   void prefetcht0(Address src);
1714   void prefetcht1(Address src);
1715   void prefetcht2(Address src);
1716   void prefetchw(Address src);
1717 
1718   // Shuffle Bytes
1719   void pshufb(XMMRegister dst, XMMRegister src);
1720   void pshufb(XMMRegister dst, Address src);
1721   void vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1722 
1723   // Shuffle Packed Doublewords
1724   void pshufd(XMMRegister dst, XMMRegister src, int mode);
1725   void pshufd(XMMRegister dst, Address src,     int mode);
1726   void vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len);
1727 
1728   // Shuffle Packed Low Words
1729   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1730   void pshuflw(XMMRegister dst, Address src,     int mode);
1731 
1732   // Shuffle packed values at 128 bit granularity
1733   void evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
1734 
1735   // Shift Right by bytes Logical DoubleQuadword Immediate
1736   void psrldq(XMMRegister dst, int shift);
1737   // Shift Left by bytes Logical DoubleQuadword Immediate
1738   void pslldq(XMMRegister dst, int shift);
1739 
1740   // Logical Compare 128bit
1741   void ptest(XMMRegister dst, XMMRegister src);
1742   void ptest(XMMRegister dst, Address src);
1743   // Logical Compare 256bit
1744   void vptest(XMMRegister dst, XMMRegister src);
1745   void vptest(XMMRegister dst, Address src);
1746 
1747   // Interleave Low Bytes
1748   void punpcklbw(XMMRegister dst, XMMRegister src);
1749   void punpcklbw(XMMRegister dst, Address src);
1750 
1751   // Interleave Low Doublewords
1752   void punpckldq(XMMRegister dst, XMMRegister src);
1753   void punpckldq(XMMRegister dst, Address src);
1754 
1755   // Interleave Low Quadwords
1756   void punpcklqdq(XMMRegister dst, XMMRegister src);
1757 
1758 #ifndef _LP64 // no 32bit push/pop on amd64
1759   void pushl(Address src);
1760 #endif
1761 
1762   void pushq(Address src);
1763 
1764   void rcll(Register dst, int imm8);
1765 
1766   void rclq(Register dst, int imm8);
1767 
1768   void rcrq(Register dst, int imm8);
1769 
1770   void rcpps(XMMRegister dst, XMMRegister src);
1771 
1772   void rcpss(XMMRegister dst, XMMRegister src);
1773 
1774   void rdtsc();
1775 
1776   void ret(int imm16);
1777 
1778 #ifdef _LP64
1779   void rorq(Register dst, int imm8);
1780   void rorxq(Register dst, Register src, int imm8);
1781   void rorxd(Register dst, Register src, int imm8);
1782 #endif
1783 
1784   void sahf();
1785 
1786   void sarl(Register dst, int imm8);
1787   void sarl(Register dst);
1788 
1789   void sarq(Register dst, int imm8);
1790   void sarq(Register dst);
1791 
1792   void sbbl(Address dst, int32_t imm32);
1793   void sbbl(Register dst, int32_t imm32);
1794   void sbbl(Register dst, Address src);
1795   void sbbl(Register dst, Register src);
1796 
1797   void sbbq(Address dst, int32_t imm32);
1798   void sbbq(Register dst, int32_t imm32);
1799   void sbbq(Register dst, Address src);
1800   void sbbq(Register dst, Register src);
1801 
1802   void setb(Condition cc, Register dst);
1803 
1804   void palignr(XMMRegister dst, XMMRegister src, int imm8);
1805   void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
1806   void evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
1807 
1808   void pblendw(XMMRegister dst, XMMRegister src, int imm8);
1809 
1810   void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8);
1811   void sha1nexte(XMMRegister dst, XMMRegister src);
1812   void sha1msg1(XMMRegister dst, XMMRegister src);
1813   void sha1msg2(XMMRegister dst, XMMRegister src);
1814   // xmm0 is implicit additional source to the following instruction.
1815   void sha256rnds2(XMMRegister dst, XMMRegister src);
1816   void sha256msg1(XMMRegister dst, XMMRegister src);
1817   void sha256msg2(XMMRegister dst, XMMRegister src);
1818 
1819   void shldl(Register dst, Register src);
1820   void shldl(Register dst, Register src, int8_t imm8);
1821 
1822   void shll(Register dst, int imm8);
1823   void shll(Register dst);
1824 
1825   void shlq(Register dst, int imm8);
1826   void shlq(Register dst);
1827 
1828   void shrdl(Register dst, Register src);
1829 
1830   void shrl(Register dst, int imm8);
1831   void shrl(Register dst);
1832 
1833   void shrq(Register dst, int imm8);
1834   void shrq(Register dst);
1835 
1836   void smovl(); // QQQ generic?
1837 
1838   // Compute Square Root of Scalar Double-Precision Floating-Point Value
1839   void sqrtsd(XMMRegister dst, Address src);
1840   void sqrtsd(XMMRegister dst, XMMRegister src);
1841 
1842   // Compute Square Root of Scalar Single-Precision Floating-Point Value
1843   void sqrtss(XMMRegister dst, Address src);
1844   void sqrtss(XMMRegister dst, XMMRegister src);
1845 
1846   void std();
1847 
1848   void stmxcsr( Address dst );
1849 
1850   void subl(Address dst, int32_t imm32);
1851   void subl(Address dst, Register src);
1852   void subl(Register dst, int32_t imm32);
1853   void subl(Register dst, Address src);
1854   void subl(Register dst, Register src);
1855 
1856   void subq(Address dst, int32_t imm32);
1857   void subq(Address dst, Register src);
1858   void subq(Register dst, int32_t imm32);
1859   void subq(Register dst, Address src);
1860   void subq(Register dst, Register src);
1861 
1862   // Force generation of a 4 byte immediate value even if it fits into 8bit
1863   void subl_imm32(Register dst, int32_t imm32);
1864   void subq_imm32(Register dst, int32_t imm32);
1865 
1866   // Subtract Scalar Double-Precision Floating-Point Values
1867   void subsd(XMMRegister dst, Address src);
1868   void subsd(XMMRegister dst, XMMRegister src);
1869 
1870   // Subtract Scalar Single-Precision Floating-Point Values
1871   void subss(XMMRegister dst, Address src);
1872   void subss(XMMRegister dst, XMMRegister src);
1873 
1874   void testb(Register dst, int imm8);
1875   void testb(Address dst, int imm8);
1876 
1877   void testl(Register dst, int32_t imm32);
1878   void testl(Register dst, Register src);
1879   void testl(Register dst, Address src);
1880 
1881   void testq(Register dst, int32_t imm32);
1882   void testq(Register dst, Register src);
1883   void testq(Register dst, Address src);
1884 
1885   // BMI - count trailing zeros
1886   void tzcntl(Register dst, Register src);
1887   void tzcntq(Register dst, Register src);
1888 
1889   // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1890   void ucomisd(XMMRegister dst, Address src);
1891   void ucomisd(XMMRegister dst, XMMRegister src);
1892 
1893   // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1894   void ucomiss(XMMRegister dst, Address src);
1895   void ucomiss(XMMRegister dst, XMMRegister src);
1896 
1897   void xabort(int8_t imm8);
1898 
1899   void xaddb(Address dst, Register src);
1900   void xaddw(Address dst, Register src);
1901   void xaddl(Address dst, Register src);
1902   void xaddq(Address dst, Register src);
1903 
1904   void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1905 
1906   void xchgb(Register reg, Address adr);
1907   void xchgw(Register reg, Address adr);
1908   void xchgl(Register reg, Address adr);
1909   void xchgl(Register dst, Register src);
1910 
1911   void xchgq(Register reg, Address adr);
1912   void xchgq(Register dst, Register src);
1913 
1914   void xend();
1915 
1916   // Get Value of Extended Control Register
1917   void xgetbv();
1918 
1919   void xorl(Register dst, int32_t imm32);
1920   void xorl(Register dst, Address src);
1921   void xorl(Register dst, Register src);
1922 
1923   void xorb(Register dst, Address src);
1924 
1925   void xorq(Register dst, Address src);
1926   void xorq(Register dst, Register src);
1927 
1928   void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1929 
1930   // AVX 3-operands scalar instructions (encoded with VEX prefix)
1931 
1932   void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1933   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1934   void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1935   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1936   void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1937   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1938   void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1939   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1940   void vfmadd231sd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1941   void vfmadd231ss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1942   void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1943   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1944   void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1945   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1946   void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1947   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1948   void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1949   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1950 
1951   void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1952   void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1953   void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1954   void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1955 
1956   void shlxl(Register dst, Register src1, Register src2);
1957   void shlxq(Register dst, Register src1, Register src2);
1958 
1959   //====================VECTOR ARITHMETIC=====================================
1960 
1961   // Add Packed Floating-Point Values
1962   void addpd(XMMRegister dst, XMMRegister src);
1963   void addpd(XMMRegister dst, Address src);
1964   void addps(XMMRegister dst, XMMRegister src);
1965   void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1966   void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1967   void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1968   void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1969 
1970   // Subtract Packed Floating-Point Values
1971   void subpd(XMMRegister dst, XMMRegister src);
1972   void subps(XMMRegister dst, XMMRegister src);
1973   void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1974   void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1975   void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1976   void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1977 
1978   // Multiply Packed Floating-Point Values
1979   void mulpd(XMMRegister dst, XMMRegister src);
1980   void mulpd(XMMRegister dst, Address src);
1981   void mulps(XMMRegister dst, XMMRegister src);
1982   void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1983   void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1984   void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1985   void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1986 
1987   void vfmadd231pd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1988   void vfmadd231ps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1989   void vfmadd231pd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1990   void vfmadd231ps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1991 
1992   // Divide Packed Floating-Point Values
1993   void divpd(XMMRegister dst, XMMRegister src);
1994   void divps(XMMRegister dst, XMMRegister src);
1995   void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1996   void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1997   void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1998   void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1999 
2000   // Sqrt Packed Floating-Point Values
2001   void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
2002   void vsqrtpd(XMMRegister dst, Address src, int vector_len);
2003   void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len);
2004   void vsqrtps(XMMRegister dst, Address src, int vector_len);
2005 
2006   // Bitwise Logical AND of Packed Floating-Point Values
2007   void andpd(XMMRegister dst, XMMRegister src);
2008   void andps(XMMRegister dst, XMMRegister src);
2009   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2010   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2011   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2012   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2013 
2014   void unpckhpd(XMMRegister dst, XMMRegister src);
2015   void unpcklpd(XMMRegister dst, XMMRegister src);
2016 
2017   // Bitwise Logical XOR of Packed Floating-Point Values
2018   void xorpd(XMMRegister dst, XMMRegister src);
2019   void xorps(XMMRegister dst, XMMRegister src);
2020   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2021   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2022   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2023   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2024 
2025   // Add horizontal packed integers
2026   void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2027   void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2028   void phaddw(XMMRegister dst, XMMRegister src);
2029   void phaddd(XMMRegister dst, XMMRegister src);
2030 
2031   // Add packed integers
2032   void paddb(XMMRegister dst, XMMRegister src);
2033   void paddw(XMMRegister dst, XMMRegister src);
2034   void paddd(XMMRegister dst, XMMRegister src);
2035   void paddd(XMMRegister dst, Address src);
2036   void paddq(XMMRegister dst, XMMRegister src);
2037   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2038   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2039   void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2040   void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2041   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2042   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2043   void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2044   void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2045 
2046   // Sub packed integers
2047   void psubb(XMMRegister dst, XMMRegister src);
2048   void psubw(XMMRegister dst, XMMRegister src);
2049   void psubd(XMMRegister dst, XMMRegister src);
2050   void psubq(XMMRegister dst, XMMRegister src);
2051   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2052   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2053   void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2054   void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2055   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2056   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2057   void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2058   void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2059 
2060   // Multiply packed integers (only shorts and ints)
2061   void pmullw(XMMRegister dst, XMMRegister src);
2062   void pmulld(XMMRegister dst, XMMRegister src);
2063   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2064   void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2065   void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2066   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2067   void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2068   void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2069 
2070   // Shift left packed integers
2071   void psllw(XMMRegister dst, int shift);
2072   void pslld(XMMRegister dst, int shift);
2073   void psllq(XMMRegister dst, int shift);
2074   void psllw(XMMRegister dst, XMMRegister shift);
2075   void pslld(XMMRegister dst, XMMRegister shift);
2076   void psllq(XMMRegister dst, XMMRegister shift);
2077   void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2078   void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2079   void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2080   void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2081   void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2082   void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2083   void vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2084 
2085   // Logical shift right packed integers
2086   void psrlw(XMMRegister dst, int shift);
2087   void psrld(XMMRegister dst, int shift);
2088   void psrlq(XMMRegister dst, int shift);
2089   void psrlw(XMMRegister dst, XMMRegister shift);
2090   void psrld(XMMRegister dst, XMMRegister shift);
2091   void psrlq(XMMRegister dst, XMMRegister shift);
2092   void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2093   void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2094   void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2095   void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2096   void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2097   void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2098   void vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2099   void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2100   void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2101 
2102   // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
2103   void psraw(XMMRegister dst, int shift);
2104   void psrad(XMMRegister dst, int shift);
2105   void psraw(XMMRegister dst, XMMRegister shift);
2106   void psrad(XMMRegister dst, XMMRegister shift);
2107   void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2108   void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2109   void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2110   void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2111   void evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2112   void evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2113 
2114   // And packed integers
2115   void pand(XMMRegister dst, XMMRegister src);
2116   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2117   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2118   void vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2119 
2120   // Andn packed integers
2121   void pandn(XMMRegister dst, XMMRegister src);
2122   void vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2123 
2124   // Or packed integers
2125   void por(XMMRegister dst, XMMRegister src);
2126   void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2127   void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2128   void vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2129 
2130   // Xor packed integers
2131   void pxor(XMMRegister dst, XMMRegister src);
2132   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2133   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2134   void evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2135   void evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2136 
2137 
2138   // vinserti forms
2139   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2140   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2141   void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2142   void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2143   void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2144 
2145   // vinsertf forms
2146   void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2147   void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2148   void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2149   void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2150   void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2151   void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2152 
2153   // vextracti forms
2154   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2155   void vextracti128(Address dst, XMMRegister src, uint8_t imm8);
2156   void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2157   void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8);
2158   void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2159   void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2160   void vextracti64x4(Address dst, XMMRegister src, uint8_t imm8);
2161 
2162   // vextractf forms
2163   void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2164   void vextractf128(Address dst, XMMRegister src, uint8_t imm8);
2165   void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2166   void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8);
2167   void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2168   void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2169   void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8);
2170 
2171   // xmm/mem sourced byte/word/dword/qword replicate
2172   void vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2173   void vpbroadcastb(XMMRegister dst, Address src, int vector_len);
2174   void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2175   void vpbroadcastw(XMMRegister dst, Address src, int vector_len);
2176   void vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2177   void vpbroadcastd(XMMRegister dst, Address src, int vector_len);
2178   void vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2179   void vpbroadcastq(XMMRegister dst, Address src, int vector_len);
2180 
2181   void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len);
2182   void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len);
2183 
2184   // scalar single/double precision replicate
2185   void vpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2186   void vpbroadcastss(XMMRegister dst, Address src, int vector_len);
2187   void vpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2188   void vpbroadcastsd(XMMRegister dst, Address src, int vector_len);
2189 
2190   // gpr sourced byte/word/dword/qword replicate
2191   void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2192   void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2193   void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2194   void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2195 
2196   void evpgatherdd(XMMRegister dst, KRegister k1, Address src, int vector_len);
2197 
2198   // Carry-Less Multiplication Quadword
2199   void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2200   void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2201   void evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len);
2202   // AVX instruction which is used to clear upper 128 bits of YMM registers and
2203   // to avoid transaction penalty between AVX and SSE states. There is no
2204   // penalty if legacy SSE instructions are encoded using VEX prefix because
2205   // they always clear upper 128 bits. It should be used before calling
2206   // runtime code and native libraries.
2207   void vzeroupper();
2208 
2209   // AVX support for vectorized conditional move (float/double). The following two instructions used only coupled.
2210   void cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2211   void blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2212   void cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2213   void blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2214   void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
2215 
2216  protected:
2217   // Next instructions require address alignment 16 bytes SSE mode.
2218   // They should be called only from corresponding MacroAssembler instructions.
2219   void andpd(XMMRegister dst, Address src);
2220   void andps(XMMRegister dst, Address src);
2221   void xorpd(XMMRegister dst, Address src);
2222   void xorps(XMMRegister dst, Address src);
2223 
2224 };
2225 
2226 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions.
2227 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction
2228 // are applied.
2229 class InstructionAttr {
2230 public:
2231   InstructionAttr(
2232     int vector_len,     // The length of vector to be applied in encoding - for both AVX and EVEX
2233     bool rex_vex_w,     // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true
2234     bool legacy_mode,   // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX
2235     bool no_reg_mask,   // when true, k0 is used when EVEX encoding is chosen, else embedded_opmask_register_specifier is used
2236     bool uses_vl)       // This instruction may have legacy constraints based on vector length for EVEX
2237     :
2238       _avx_vector_len(vector_len),
2239       _rex_vex_w(rex_vex_w),
2240       _rex_vex_w_reverted(false),
2241       _legacy_mode(legacy_mode),
2242       _no_reg_mask(no_reg_mask),
2243       _uses_vl(uses_vl),
2244       _tuple_type(Assembler::EVEX_ETUP),
2245       _input_size_in_bits(Assembler::EVEX_NObit),
2246       _is_evex_instruction(false),
2247       _evex_encoding(0),
2248       _is_clear_context(true),
2249       _is_extended_context(false),
2250       _embedded_opmask_register_specifier(0), // hard code k0
2251       _current_assembler(NULL) {
2252     if (UseAVX < 3) _legacy_mode = true;
2253   }
2254 
2255   ~InstructionAttr() {
2256     if (_current_assembler != NULL) {
2257       _current_assembler->clear_attributes();
2258     }
2259     _current_assembler = NULL;
2260   }
2261 
2262 private:
2263   int  _avx_vector_len;
2264   bool _rex_vex_w;
2265   bool _rex_vex_w_reverted;
2266   bool _legacy_mode;
2267   bool _no_reg_mask;
2268   bool _uses_vl;
2269   int  _tuple_type;
2270   int  _input_size_in_bits;
2271   bool _is_evex_instruction;
2272   int  _evex_encoding;
2273   bool _is_clear_context;
2274   bool _is_extended_context;
2275   int _embedded_opmask_register_specifier;
2276 
2277   Assembler *_current_assembler;
2278 
2279 public:
2280   // query functions for field accessors
2281   int  get_vector_len(void) const { return _avx_vector_len; }
2282   bool is_rex_vex_w(void) const { return _rex_vex_w; }
2283   bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; }
2284   bool is_legacy_mode(void) const { return _legacy_mode; }
2285   bool is_no_reg_mask(void) const { return _no_reg_mask; }
2286   bool uses_vl(void) const { return _uses_vl; }
2287   int  get_tuple_type(void) const { return _tuple_type; }
2288   int  get_input_size(void) const { return _input_size_in_bits; }
2289   int  is_evex_instruction(void) const { return _is_evex_instruction; }
2290   int  get_evex_encoding(void) const { return _evex_encoding; }
2291   bool is_clear_context(void) const { return _is_clear_context; }
2292   bool is_extended_context(void) const { return _is_extended_context; }
2293   int get_embedded_opmask_register_specifier(void) const { return _embedded_opmask_register_specifier; }
2294 
2295   // Set the vector len manually
2296   void set_vector_len(int vector_len) { _avx_vector_len = vector_len; }
2297 
2298   // Set revert rex_vex_w for avx encoding
2299   void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; }
2300 
2301   // Set rex_vex_w based on state
2302   void set_rex_vex_w(bool state) { _rex_vex_w = state; }
2303 
2304   // Set the instruction to be encoded in AVX mode
2305   void set_is_legacy_mode(void) { _legacy_mode = true; }
2306 
2307   // Set the current instuction to be encoded as an EVEX instuction
2308   void set_is_evex_instruction(void) { _is_evex_instruction = true; }
2309 
2310   // Internal encoding data used in compressed immediate offset programming
2311   void set_evex_encoding(int value) { _evex_encoding = value; }
2312 
2313   // Set the Evex.Z field to be used to clear all non directed XMM/YMM/ZMM components
2314   void reset_is_clear_context(void) { _is_clear_context = false; }
2315 
2316   // Map back to current asembler so that we can manage object level assocation
2317   void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
2318 
2319   // Address modifiers used for compressed displacement calculation
2320   void set_address_attributes(int tuple_type, int input_size_in_bits) {
2321     if (VM_Version::supports_evex()) {
2322       _tuple_type = tuple_type;
2323       _input_size_in_bits = input_size_in_bits;
2324     }
2325   }
2326 
2327   // Set embedded opmask register specifier.
2328   void set_embedded_opmask_register_specifier(KRegister mask) {
2329     _embedded_opmask_register_specifier = (*mask).encoding() & 0x7;
2330   }
2331 
2332 };
2333 
2334 #endif // CPU_X86_ASSEMBLER_X86_HPP
--- EOF ---