1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "gc/shared/barrierSet.hpp"
31 #include "gc/shared/barrierSetAssembler.hpp"
32 #include "gc/shared/collectedHeap.inline.hpp"
33 #include "interpreter/interpreter.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "memory/universe.hpp"
36 #include "oops/accessDecorators.hpp"
37 #include "oops/klass.inline.hpp"
38 #include "prims/methodHandles.hpp"
39 #include "runtime/biasedLocking.hpp"
40 #include "runtime/flags/flagSetting.hpp"
41 #include "runtime/interfaceSupport.inline.hpp"
42 #include "runtime/objectMonitor.hpp"
43 #include "runtime/os.hpp"
44 #include "runtime/safepoint.hpp"
45 #include "runtime/safepointMechanism.hpp"
46 #include "runtime/sharedRuntime.hpp"
47 #include "runtime/stubRoutines.hpp"
48 #include "runtime/thread.hpp"
49 #include "utilities/macros.hpp"
50 #include "crc32c.h"
51 #ifdef COMPILER2
52 #include "opto/intrinsicnode.hpp"
53 #endif
54
55 #ifdef PRODUCT
56 #define BLOCK_COMMENT(str) /* nothing */
57 #define STOP(error) stop(error)
58 #else
59 #define BLOCK_COMMENT(str) block_comment(str)
60 #define STOP(error) block_comment(error); stop(error)
61 #endif
62
63 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
64
65 #ifdef ASSERT
66 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
67 #endif
68
69 static Assembler::Condition reverse[] = {
70 Assembler::noOverflow /* overflow = 0x0 */ ,
71 Assembler::overflow /* noOverflow = 0x1 */ ,
72 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
73 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
74 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
75 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
76 Assembler::above /* belowEqual = 0x6 */ ,
77 Assembler::belowEqual /* above = 0x7 */ ,
78 Assembler::positive /* negative = 0x8 */ ,
79 Assembler::negative /* positive = 0x9 */ ,
80 Assembler::noParity /* parity = 0xa */ ,
81 Assembler::parity /* noParity = 0xb */ ,
82 Assembler::greaterEqual /* less = 0xc */ ,
83 Assembler::less /* greaterEqual = 0xd */ ,
84 Assembler::greater /* lessEqual = 0xe */ ,
85 Assembler::lessEqual /* greater = 0xf, */
86
87 };
88
89
90 // Implementation of MacroAssembler
91
92 // First all the versions that have distinct versions depending on 32/64 bit
93 // Unless the difference is trivial (1 line or so).
94
95 #ifndef _LP64
96
97 // 32bit versions
98
99 Address MacroAssembler::as_Address(AddressLiteral adr) {
100 return Address(adr.target(), adr.rspec());
101 }
102
103 Address MacroAssembler::as_Address(ArrayAddress adr) {
104 return Address::make_array(adr);
105 }
106
107 void MacroAssembler::call_VM_leaf_base(address entry_point,
108 int number_of_arguments) {
109 call(RuntimeAddress(entry_point));
110 increment(rsp, number_of_arguments * wordSize);
111 }
112
113 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
114 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
115 }
116
117 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
118 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
119 }
120
121 void MacroAssembler::cmpoop_raw(Address src1, jobject obj) {
122 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
123 }
124
125 void MacroAssembler::cmpoop_raw(Register src1, jobject obj) {
126 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
127 }
128
129 void MacroAssembler::cmpoop(Address src1, jobject obj) {
130 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
131 bs->obj_equals(this, src1, obj);
132 }
133
134 void MacroAssembler::cmpoop(Register src1, jobject obj) {
135 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
136 bs->obj_equals(this, src1, obj);
137 }
138
139 void MacroAssembler::extend_sign(Register hi, Register lo) {
140 // According to Intel Doc. AP-526, "Integer Divide", p.18.
141 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
142 cdql();
143 } else {
144 movl(hi, lo);
145 sarl(hi, 31);
146 }
147 }
148
149 void MacroAssembler::jC2(Register tmp, Label& L) {
150 // set parity bit if FPU flag C2 is set (via rax)
151 save_rax(tmp);
152 fwait(); fnstsw_ax();
153 sahf();
154 restore_rax(tmp);
155 // branch
156 jcc(Assembler::parity, L);
157 }
158
159 void MacroAssembler::jnC2(Register tmp, Label& L) {
160 // set parity bit if FPU flag C2 is set (via rax)
161 save_rax(tmp);
162 fwait(); fnstsw_ax();
163 sahf();
164 restore_rax(tmp);
165 // branch
166 jcc(Assembler::noParity, L);
167 }
168
169 // 32bit can do a case table jump in one instruction but we no longer allow the base
170 // to be installed in the Address class
171 void MacroAssembler::jump(ArrayAddress entry) {
172 jmp(as_Address(entry));
173 }
174
175 // Note: y_lo will be destroyed
176 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
177 // Long compare for Java (semantics as described in JVM spec.)
178 Label high, low, done;
179
180 cmpl(x_hi, y_hi);
181 jcc(Assembler::less, low);
182 jcc(Assembler::greater, high);
183 // x_hi is the return register
184 xorl(x_hi, x_hi);
185 cmpl(x_lo, y_lo);
186 jcc(Assembler::below, low);
187 jcc(Assembler::equal, done);
188
189 bind(high);
190 xorl(x_hi, x_hi);
191 increment(x_hi);
192 jmp(done);
193
194 bind(low);
195 xorl(x_hi, x_hi);
196 decrementl(x_hi);
197
198 bind(done);
199 }
200
201 void MacroAssembler::lea(Register dst, AddressLiteral src) {
202 mov_literal32(dst, (int32_t)src.target(), src.rspec());
203 }
204
205 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
206 // leal(dst, as_Address(adr));
207 // see note in movl as to why we must use a move
208 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
209 }
210
211 void MacroAssembler::leave() {
212 mov(rsp, rbp);
213 pop(rbp);
214 }
215
216 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
217 // Multiplication of two Java long values stored on the stack
218 // as illustrated below. Result is in rdx:rax.
219 //
220 // rsp ---> [ ?? ] \ \
221 // .... | y_rsp_offset |
222 // [ y_lo ] / (in bytes) | x_rsp_offset
223 // [ y_hi ] | (in bytes)
224 // .... |
225 // [ x_lo ] /
226 // [ x_hi ]
227 // ....
228 //
229 // Basic idea: lo(result) = lo(x_lo * y_lo)
230 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
231 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
232 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
233 Label quick;
234 // load x_hi, y_hi and check if quick
235 // multiplication is possible
236 movl(rbx, x_hi);
237 movl(rcx, y_hi);
238 movl(rax, rbx);
239 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
240 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
241 // do full multiplication
242 // 1st step
243 mull(y_lo); // x_hi * y_lo
244 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
245 // 2nd step
246 movl(rax, x_lo);
247 mull(rcx); // x_lo * y_hi
248 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
249 // 3rd step
250 bind(quick); // note: rbx, = 0 if quick multiply!
251 movl(rax, x_lo);
252 mull(y_lo); // x_lo * y_lo
253 addl(rdx, rbx); // correct hi(x_lo * y_lo)
254 }
255
256 void MacroAssembler::lneg(Register hi, Register lo) {
257 negl(lo);
258 adcl(hi, 0);
259 negl(hi);
260 }
261
262 void MacroAssembler::lshl(Register hi, Register lo) {
263 // Java shift left long support (semantics as described in JVM spec., p.305)
264 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
265 // shift value is in rcx !
266 assert(hi != rcx, "must not use rcx");
267 assert(lo != rcx, "must not use rcx");
268 const Register s = rcx; // shift count
269 const int n = BitsPerWord;
270 Label L;
271 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
272 cmpl(s, n); // if (s < n)
273 jcc(Assembler::less, L); // else (s >= n)
274 movl(hi, lo); // x := x << n
275 xorl(lo, lo);
276 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
277 bind(L); // s (mod n) < n
278 shldl(hi, lo); // x := x << s
279 shll(lo);
280 }
281
282
283 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
284 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
285 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
286 assert(hi != rcx, "must not use rcx");
287 assert(lo != rcx, "must not use rcx");
288 const Register s = rcx; // shift count
289 const int n = BitsPerWord;
290 Label L;
291 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
292 cmpl(s, n); // if (s < n)
293 jcc(Assembler::less, L); // else (s >= n)
294 movl(lo, hi); // x := x >> n
295 if (sign_extension) sarl(hi, 31);
296 else xorl(hi, hi);
297 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
298 bind(L); // s (mod n) < n
299 shrdl(lo, hi); // x := x >> s
300 if (sign_extension) sarl(hi);
301 else shrl(hi);
302 }
303
304 void MacroAssembler::movoop(Register dst, jobject obj) {
305 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
306 }
307
308 void MacroAssembler::movoop(Address dst, jobject obj) {
309 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
310 }
311
312 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
313 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
314 }
315
316 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
317 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
318 }
319
320 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
321 // scratch register is not used,
322 // it is defined to match parameters of 64-bit version of this method.
323 if (src.is_lval()) {
324 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
325 } else {
326 movl(dst, as_Address(src));
327 }
328 }
329
330 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
331 movl(as_Address(dst), src);
332 }
333
334 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
335 movl(dst, as_Address(src));
336 }
337
338 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
339 void MacroAssembler::movptr(Address dst, intptr_t src) {
340 movl(dst, src);
341 }
342
343
344 void MacroAssembler::pop_callee_saved_registers() {
345 pop(rcx);
346 pop(rdx);
347 pop(rdi);
348 pop(rsi);
349 }
350
351 void MacroAssembler::pop_fTOS() {
352 fld_d(Address(rsp, 0));
353 addl(rsp, 2 * wordSize);
354 }
355
356 void MacroAssembler::push_callee_saved_registers() {
357 push(rsi);
358 push(rdi);
359 push(rdx);
360 push(rcx);
361 }
362
363 void MacroAssembler::push_fTOS() {
364 subl(rsp, 2 * wordSize);
365 fstp_d(Address(rsp, 0));
366 }
367
368
369 void MacroAssembler::pushoop(jobject obj) {
370 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
371 }
372
373 void MacroAssembler::pushklass(Metadata* obj) {
374 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
375 }
376
377 void MacroAssembler::pushptr(AddressLiteral src) {
378 if (src.is_lval()) {
379 push_literal32((int32_t)src.target(), src.rspec());
380 } else {
381 pushl(as_Address(src));
382 }
383 }
384
385 void MacroAssembler::set_word_if_not_zero(Register dst) {
386 xorl(dst, dst);
387 set_byte_if_not_zero(dst);
388 }
389
390 static void pass_arg0(MacroAssembler* masm, Register arg) {
391 masm->push(arg);
392 }
393
394 static void pass_arg1(MacroAssembler* masm, Register arg) {
395 masm->push(arg);
396 }
397
398 static void pass_arg2(MacroAssembler* masm, Register arg) {
399 masm->push(arg);
400 }
401
402 static void pass_arg3(MacroAssembler* masm, Register arg) {
403 masm->push(arg);
404 }
405
406 #ifndef PRODUCT
407 extern "C" void findpc(intptr_t x);
408 #endif
409
410 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
411 // In order to get locks to work, we need to fake a in_VM state
412 JavaThread* thread = JavaThread::current();
413 JavaThreadState saved_state = thread->thread_state();
414 thread->set_thread_state(_thread_in_vm);
415 if (ShowMessageBoxOnError) {
416 JavaThread* thread = JavaThread::current();
417 JavaThreadState saved_state = thread->thread_state();
418 thread->set_thread_state(_thread_in_vm);
419 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
420 ttyLocker ttyl;
421 BytecodeCounter::print();
422 }
423 // To see where a verify_oop failed, get $ebx+40/X for this frame.
424 // This is the value of eip which points to where verify_oop will return.
425 if (os::message_box(msg, "Execution stopped, print registers?")) {
426 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
427 BREAKPOINT;
428 }
429 } else {
430 ttyLocker ttyl;
431 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
432 }
433 // Don't assert holding the ttyLock
434 assert(false, "DEBUG MESSAGE: %s", msg);
435 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
436 }
437
438 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
439 ttyLocker ttyl;
440 FlagSetting fs(Debugging, true);
441 tty->print_cr("eip = 0x%08x", eip);
442 #ifndef PRODUCT
443 if ((WizardMode || Verbose) && PrintMiscellaneous) {
444 tty->cr();
445 findpc(eip);
446 tty->cr();
447 }
448 #endif
449 #define PRINT_REG(rax) \
450 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
451 PRINT_REG(rax);
452 PRINT_REG(rbx);
453 PRINT_REG(rcx);
454 PRINT_REG(rdx);
455 PRINT_REG(rdi);
456 PRINT_REG(rsi);
457 PRINT_REG(rbp);
458 PRINT_REG(rsp);
459 #undef PRINT_REG
460 // Print some words near top of staack.
461 int* dump_sp = (int*) rsp;
462 for (int col1 = 0; col1 < 8; col1++) {
463 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
464 os::print_location(tty, *dump_sp++);
465 }
466 for (int row = 0; row < 16; row++) {
467 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
468 for (int col = 0; col < 8; col++) {
469 tty->print(" 0x%08x", *dump_sp++);
470 }
471 tty->cr();
472 }
473 // Print some instructions around pc:
474 Disassembler::decode((address)eip-64, (address)eip);
475 tty->print_cr("--------");
476 Disassembler::decode((address)eip, (address)eip+32);
477 }
478
479 void MacroAssembler::stop(const char* msg) {
480 ExternalAddress message((address)msg);
481 // push address of message
482 pushptr(message.addr());
483 { Label L; call(L, relocInfo::none); bind(L); } // push eip
484 pusha(); // push registers
485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
486 hlt();
487 }
488
489 void MacroAssembler::warn(const char* msg) {
490 push_CPU_state();
491
492 ExternalAddress message((address) msg);
493 // push address of message
494 pushptr(message.addr());
495
496 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
497 addl(rsp, wordSize); // discard argument
498 pop_CPU_state();
499 }
500
501 void MacroAssembler::print_state() {
502 { Label L; call(L, relocInfo::none); bind(L); } // push eip
503 pusha(); // push registers
504
505 push_CPU_state();
506 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
507 pop_CPU_state();
508
509 popa();
510 addl(rsp, wordSize);
511 }
512
513 #else // _LP64
514
515 // 64 bit versions
516
517 Address MacroAssembler::as_Address(AddressLiteral adr) {
518 // amd64 always does this as a pc-rel
519 // we can be absolute or disp based on the instruction type
520 // jmp/call are displacements others are absolute
521 assert(!adr.is_lval(), "must be rval");
522 assert(reachable(adr), "must be");
523 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
524
525 }
526
527 Address MacroAssembler::as_Address(ArrayAddress adr) {
528 AddressLiteral base = adr.base();
529 lea(rscratch1, base);
530 Address index = adr.index();
531 assert(index._disp == 0, "must not have disp"); // maybe it can?
532 Address array(rscratch1, index._index, index._scale, index._disp);
533 return array;
534 }
535
536 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
537 Label L, E;
538
539 #ifdef _WIN64
540 // Windows always allocates space for it's register args
541 assert(num_args <= 4, "only register arguments supported");
542 subq(rsp, frame::arg_reg_save_area_bytes);
543 #endif
544
545 // Align stack if necessary
546 testl(rsp, 15);
547 jcc(Assembler::zero, L);
548
549 subq(rsp, 8);
550 {
551 call(RuntimeAddress(entry_point));
552 }
553 addq(rsp, 8);
554 jmp(E);
555
556 bind(L);
557 {
558 call(RuntimeAddress(entry_point));
559 }
560
561 bind(E);
562
563 #ifdef _WIN64
564 // restore stack pointer
565 addq(rsp, frame::arg_reg_save_area_bytes);
566 #endif
567
568 }
569
570 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
571 assert(!src2.is_lval(), "should use cmpptr");
572
573 if (reachable(src2)) {
574 cmpq(src1, as_Address(src2));
575 } else {
576 lea(rscratch1, src2);
577 Assembler::cmpq(src1, Address(rscratch1, 0));
578 }
579 }
580
581 int MacroAssembler::corrected_idivq(Register reg) {
582 // Full implementation of Java ldiv and lrem; checks for special
583 // case as described in JVM spec., p.243 & p.271. The function
584 // returns the (pc) offset of the idivl instruction - may be needed
585 // for implicit exceptions.
586 //
587 // normal case special case
588 //
589 // input : rax: dividend min_long
590 // reg: divisor (may not be eax/edx) -1
591 //
592 // output: rax: quotient (= rax idiv reg) min_long
593 // rdx: remainder (= rax irem reg) 0
594 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
595 static const int64_t min_long = 0x8000000000000000;
596 Label normal_case, special_case;
597
598 // check for special case
599 cmp64(rax, ExternalAddress((address) &min_long));
600 jcc(Assembler::notEqual, normal_case);
601 xorl(rdx, rdx); // prepare rdx for possible special case (where
602 // remainder = 0)
603 cmpq(reg, -1);
604 jcc(Assembler::equal, special_case);
605
606 // handle normal case
607 bind(normal_case);
608 cdqq();
609 int idivq_offset = offset();
610 idivq(reg);
611
612 // normal and special case exit
613 bind(special_case);
614
615 return idivq_offset;
616 }
617
618 void MacroAssembler::decrementq(Register reg, int value) {
619 if (value == min_jint) { subq(reg, value); return; }
620 if (value < 0) { incrementq(reg, -value); return; }
621 if (value == 0) { ; return; }
622 if (value == 1 && UseIncDec) { decq(reg) ; return; }
623 /* else */ { subq(reg, value) ; return; }
624 }
625
626 void MacroAssembler::decrementq(Address dst, int value) {
627 if (value == min_jint) { subq(dst, value); return; }
628 if (value < 0) { incrementq(dst, -value); return; }
629 if (value == 0) { ; return; }
630 if (value == 1 && UseIncDec) { decq(dst) ; return; }
631 /* else */ { subq(dst, value) ; return; }
632 }
633
634 void MacroAssembler::incrementq(AddressLiteral dst) {
635 if (reachable(dst)) {
636 incrementq(as_Address(dst));
637 } else {
638 lea(rscratch1, dst);
639 incrementq(Address(rscratch1, 0));
640 }
641 }
642
643 void MacroAssembler::incrementq(Register reg, int value) {
644 if (value == min_jint) { addq(reg, value); return; }
645 if (value < 0) { decrementq(reg, -value); return; }
646 if (value == 0) { ; return; }
647 if (value == 1 && UseIncDec) { incq(reg) ; return; }
648 /* else */ { addq(reg, value) ; return; }
649 }
650
651 void MacroAssembler::incrementq(Address dst, int value) {
652 if (value == min_jint) { addq(dst, value); return; }
653 if (value < 0) { decrementq(dst, -value); return; }
654 if (value == 0) { ; return; }
655 if (value == 1 && UseIncDec) { incq(dst) ; return; }
656 /* else */ { addq(dst, value) ; return; }
657 }
658
659 // 32bit can do a case table jump in one instruction but we no longer allow the base
660 // to be installed in the Address class
661 void MacroAssembler::jump(ArrayAddress entry) {
662 lea(rscratch1, entry.base());
663 Address dispatch = entry.index();
664 assert(dispatch._base == noreg, "must be");
665 dispatch._base = rscratch1;
666 jmp(dispatch);
667 }
668
669 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
670 ShouldNotReachHere(); // 64bit doesn't use two regs
671 cmpq(x_lo, y_lo);
672 }
673
674 void MacroAssembler::lea(Register dst, AddressLiteral src) {
675 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
676 }
677
678 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
679 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
680 movptr(dst, rscratch1);
681 }
682
683 void MacroAssembler::leave() {
684 // %%% is this really better? Why not on 32bit too?
685 emit_int8((unsigned char)0xC9); // LEAVE
686 }
687
688 void MacroAssembler::lneg(Register hi, Register lo) {
689 ShouldNotReachHere(); // 64bit doesn't use two regs
690 negq(lo);
691 }
692
693 void MacroAssembler::movoop(Register dst, jobject obj) {
694 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
695 }
696
697 void MacroAssembler::movoop(Address dst, jobject obj) {
698 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
699 movq(dst, rscratch1);
700 }
701
702 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
703 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
704 }
705
706 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
707 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
708 movq(dst, rscratch1);
709 }
710
711 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
712 if (src.is_lval()) {
713 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
714 } else {
715 if (reachable(src)) {
716 movq(dst, as_Address(src));
717 } else {
718 lea(scratch, src);
719 movq(dst, Address(scratch, 0));
720 }
721 }
722 }
723
724 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
725 movq(as_Address(dst), src);
726 }
727
728 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
729 movq(dst, as_Address(src));
730 }
731
732 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
733 void MacroAssembler::movptr(Address dst, intptr_t src) {
734 mov64(rscratch1, src);
735 movq(dst, rscratch1);
736 }
737
738 // These are mostly for initializing NULL
739 void MacroAssembler::movptr(Address dst, int32_t src) {
740 movslq(dst, src);
741 }
742
743 void MacroAssembler::movptr(Register dst, int32_t src) {
744 mov64(dst, (intptr_t)src);
745 }
746
747 void MacroAssembler::pushoop(jobject obj) {
748 movoop(rscratch1, obj);
749 push(rscratch1);
750 }
751
752 void MacroAssembler::pushklass(Metadata* obj) {
753 mov_metadata(rscratch1, obj);
754 push(rscratch1);
755 }
756
757 void MacroAssembler::pushptr(AddressLiteral src) {
758 lea(rscratch1, src);
759 if (src.is_lval()) {
760 push(rscratch1);
761 } else {
762 pushq(Address(rscratch1, 0));
763 }
764 }
765
766 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
767 // we must set sp to zero to clear frame
768 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
769 // must clear fp, so that compiled frames are not confused; it is
770 // possible that we need it only for debugging
771 if (clear_fp) {
772 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
773 }
774
775 // Always clear the pc because it could have been set by make_walkable()
776 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
777 vzeroupper();
778 }
779
780 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
781 Register last_java_fp,
782 address last_java_pc) {
783 vzeroupper();
784 // determine last_java_sp register
785 if (!last_java_sp->is_valid()) {
786 last_java_sp = rsp;
787 }
788
789 // last_java_fp is optional
790 if (last_java_fp->is_valid()) {
791 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
792 last_java_fp);
793 }
794
795 // last_java_pc is optional
796 if (last_java_pc != NULL) {
797 Address java_pc(r15_thread,
798 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
799 lea(rscratch1, InternalAddress(last_java_pc));
800 movptr(java_pc, rscratch1);
801 }
802
803 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
804 }
805
806 static void pass_arg0(MacroAssembler* masm, Register arg) {
807 if (c_rarg0 != arg ) {
808 masm->mov(c_rarg0, arg);
809 }
810 }
811
812 static void pass_arg1(MacroAssembler* masm, Register arg) {
813 if (c_rarg1 != arg ) {
814 masm->mov(c_rarg1, arg);
815 }
816 }
817
818 static void pass_arg2(MacroAssembler* masm, Register arg) {
819 if (c_rarg2 != arg ) {
820 masm->mov(c_rarg2, arg);
821 }
822 }
823
824 static void pass_arg3(MacroAssembler* masm, Register arg) {
825 if (c_rarg3 != arg ) {
826 masm->mov(c_rarg3, arg);
827 }
828 }
829
830 void MacroAssembler::stop(const char* msg) {
831 address rip = pc();
832 pusha(); // get regs on stack
833 lea(c_rarg0, ExternalAddress((address) msg));
834 lea(c_rarg1, InternalAddress(rip));
835 movq(c_rarg2, rsp); // pass pointer to regs array
836 andq(rsp, -16); // align stack as required by ABI
837 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
838 hlt();
839 }
840
841 void MacroAssembler::warn(const char* msg) {
842 push(rbp);
843 movq(rbp, rsp);
844 andq(rsp, -16); // align stack as required by push_CPU_state and call
845 push_CPU_state(); // keeps alignment at 16 bytes
846 lea(c_rarg0, ExternalAddress((address) msg));
847 lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
848 call(rax);
849 pop_CPU_state();
850 mov(rsp, rbp);
851 pop(rbp);
852 }
853
854 void MacroAssembler::print_state() {
855 address rip = pc();
856 pusha(); // get regs on stack
857 push(rbp);
858 movq(rbp, rsp);
859 andq(rsp, -16); // align stack as required by push_CPU_state and call
860 push_CPU_state(); // keeps alignment at 16 bytes
861
862 lea(c_rarg0, InternalAddress(rip));
863 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
864 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
865
866 pop_CPU_state();
867 mov(rsp, rbp);
868 pop(rbp);
869 popa();
870 }
871
872 #ifndef PRODUCT
873 extern "C" void findpc(intptr_t x);
874 #endif
875
876 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
877 // In order to get locks to work, we need to fake a in_VM state
878 if (ShowMessageBoxOnError) {
879 JavaThread* thread = JavaThread::current();
880 JavaThreadState saved_state = thread->thread_state();
881 thread->set_thread_state(_thread_in_vm);
882 #ifndef PRODUCT
883 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
884 ttyLocker ttyl;
885 BytecodeCounter::print();
886 }
887 #endif
888 // To see where a verify_oop failed, get $ebx+40/X for this frame.
889 // XXX correct this offset for amd64
890 // This is the value of eip which points to where verify_oop will return.
891 if (os::message_box(msg, "Execution stopped, print registers?")) {
892 print_state64(pc, regs);
893 BREAKPOINT;
894 assert(false, "start up GDB");
895 }
896 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
897 } else {
898 ttyLocker ttyl;
899 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
900 msg);
901 assert(false, "DEBUG MESSAGE: %s", msg);
902 }
903 }
904
905 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
906 ttyLocker ttyl;
907 FlagSetting fs(Debugging, true);
908 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
909 #ifndef PRODUCT
910 tty->cr();
911 findpc(pc);
912 tty->cr();
913 #endif
914 #define PRINT_REG(rax, value) \
915 { tty->print("%s = ", #rax); os::print_location(tty, value); }
916 PRINT_REG(rax, regs[15]);
917 PRINT_REG(rbx, regs[12]);
918 PRINT_REG(rcx, regs[14]);
919 PRINT_REG(rdx, regs[13]);
920 PRINT_REG(rdi, regs[8]);
921 PRINT_REG(rsi, regs[9]);
922 PRINT_REG(rbp, regs[10]);
923 PRINT_REG(rsp, regs[11]);
924 PRINT_REG(r8 , regs[7]);
925 PRINT_REG(r9 , regs[6]);
926 PRINT_REG(r10, regs[5]);
927 PRINT_REG(r11, regs[4]);
928 PRINT_REG(r12, regs[3]);
929 PRINT_REG(r13, regs[2]);
930 PRINT_REG(r14, regs[1]);
931 PRINT_REG(r15, regs[0]);
932 #undef PRINT_REG
933 // Print some words near top of staack.
934 int64_t* rsp = (int64_t*) regs[11];
935 int64_t* dump_sp = rsp;
936 for (int col1 = 0; col1 < 8; col1++) {
937 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
938 os::print_location(tty, *dump_sp++);
939 }
940 for (int row = 0; row < 25; row++) {
941 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
942 for (int col = 0; col < 4; col++) {
943 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
944 }
945 tty->cr();
946 }
947 // Print some instructions around pc:
948 Disassembler::decode((address)pc-64, (address)pc);
949 tty->print_cr("--------");
950 Disassembler::decode((address)pc, (address)pc+32);
951 }
952
953 #endif // _LP64
954
955 // Now versions that are common to 32/64 bit
956
957 void MacroAssembler::addptr(Register dst, int32_t imm32) {
958 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
959 }
960
961 void MacroAssembler::addptr(Register dst, Register src) {
962 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
963 }
964
965 void MacroAssembler::addptr(Address dst, Register src) {
966 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
967 }
968
969 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
970 if (reachable(src)) {
971 Assembler::addsd(dst, as_Address(src));
972 } else {
973 lea(rscratch1, src);
974 Assembler::addsd(dst, Address(rscratch1, 0));
975 }
976 }
977
978 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
979 if (reachable(src)) {
980 addss(dst, as_Address(src));
981 } else {
982 lea(rscratch1, src);
983 addss(dst, Address(rscratch1, 0));
984 }
985 }
986
987 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
988 if (reachable(src)) {
989 Assembler::addpd(dst, as_Address(src));
990 } else {
991 lea(rscratch1, src);
992 Assembler::addpd(dst, Address(rscratch1, 0));
993 }
994 }
995
996 void MacroAssembler::align(int modulus) {
997 align(modulus, offset());
998 }
999
1000 void MacroAssembler::align(int modulus, int target) {
1001 if (target % modulus != 0) {
1002 nop(modulus - (target % modulus));
1003 }
1004 }
1005
1006 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1007 // Used in sign-masking with aligned address.
1008 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1009 if (reachable(src)) {
1010 Assembler::andpd(dst, as_Address(src));
1011 } else {
1012 lea(scratch_reg, src);
1013 Assembler::andpd(dst, Address(scratch_reg, 0));
1014 }
1015 }
1016
1017 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1018 // Used in sign-masking with aligned address.
1019 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1020 if (reachable(src)) {
1021 Assembler::andps(dst, as_Address(src));
1022 } else {
1023 lea(scratch_reg, src);
1024 Assembler::andps(dst, Address(scratch_reg, 0));
1025 }
1026 }
1027
1028 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1029 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1030 }
1031
1032 void MacroAssembler::atomic_incl(Address counter_addr) {
1033 lock();
1034 incrementl(counter_addr);
1035 }
1036
1037 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1038 if (reachable(counter_addr)) {
1039 atomic_incl(as_Address(counter_addr));
1040 } else {
1041 lea(scr, counter_addr);
1042 atomic_incl(Address(scr, 0));
1043 }
1044 }
1045
1046 #ifdef _LP64
1047 void MacroAssembler::atomic_incq(Address counter_addr) {
1048 lock();
1049 incrementq(counter_addr);
1050 }
1051
1052 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1053 if (reachable(counter_addr)) {
1054 atomic_incq(as_Address(counter_addr));
1055 } else {
1056 lea(scr, counter_addr);
1057 atomic_incq(Address(scr, 0));
1058 }
1059 }
1060 #endif
1061
1062 // Writes to stack successive pages until offset reached to check for
1063 // stack overflow + shadow pages. This clobbers tmp.
1064 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1065 movptr(tmp, rsp);
1066 // Bang stack for total size given plus shadow page size.
1067 // Bang one page at a time because large size can bang beyond yellow and
1068 // red zones.
1069 Label loop;
1070 bind(loop);
1071 movl(Address(tmp, (-os::vm_page_size())), size );
1072 subptr(tmp, os::vm_page_size());
1073 subl(size, os::vm_page_size());
1074 jcc(Assembler::greater, loop);
1075
1076 // Bang down shadow pages too.
1077 // At this point, (tmp-0) is the last address touched, so don't
1078 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1079 // was post-decremented.) Skip this address by starting at i=1, and
1080 // touch a few more pages below. N.B. It is important to touch all
1081 // the way down including all pages in the shadow zone.
1082 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1083 // this could be any sized move but this is can be a debugging crumb
1084 // so the bigger the better.
1085 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1086 }
1087 }
1088
1089 void MacroAssembler::reserved_stack_check() {
1090 // testing if reserved zone needs to be enabled
1091 Label no_reserved_zone_enabling;
1092 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1093 NOT_LP64(get_thread(rsi);)
1094
1095 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1096 jcc(Assembler::below, no_reserved_zone_enabling);
1097
1098 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1099 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1100 should_not_reach_here();
1101
1102 bind(no_reserved_zone_enabling);
1103 }
1104
1105 int MacroAssembler::biased_locking_enter(Register lock_reg,
1106 Register obj_reg,
1107 Register swap_reg,
1108 Register tmp_reg,
1109 bool swap_reg_contains_mark,
1110 Label& done,
1111 Label* slow_case,
1112 BiasedLockingCounters* counters) {
1113 assert(UseBiasedLocking, "why call this otherwise?");
1114 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1115 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1116 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1117 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1118 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1119 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1120
1121 if (PrintBiasedLockingStatistics && counters == NULL) {
1122 counters = BiasedLocking::counters();
1123 }
1124 // Biased locking
1125 // See whether the lock is currently biased toward our thread and
1126 // whether the epoch is still valid
1127 // Note that the runtime guarantees sufficient alignment of JavaThread
1128 // pointers to allow age to be placed into low bits
1129 // First check to see whether biasing is even enabled for this object
1130 Label cas_label;
1131 int null_check_offset = -1;
1132 if (!swap_reg_contains_mark) {
1133 null_check_offset = offset();
1134 movptr(swap_reg, mark_addr);
1135 }
1136 movptr(tmp_reg, swap_reg);
1137 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1138 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1139 jcc(Assembler::notEqual, cas_label);
1140 // The bias pattern is present in the object's header. Need to check
1141 // whether the bias owner and the epoch are both still current.
1142 #ifndef _LP64
1143 // Note that because there is no current thread register on x86_32 we
1144 // need to store off the mark word we read out of the object to
1145 // avoid reloading it and needing to recheck invariants below. This
1146 // store is unfortunate but it makes the overall code shorter and
1147 // simpler.
1148 movptr(saved_mark_addr, swap_reg);
1149 #endif
1150 if (swap_reg_contains_mark) {
1151 null_check_offset = offset();
1152 }
1153 load_prototype_header(tmp_reg, obj_reg);
1154 #ifdef _LP64
1155 orptr(tmp_reg, r15_thread);
1156 xorptr(tmp_reg, swap_reg);
1157 Register header_reg = tmp_reg;
1158 #else
1159 xorptr(tmp_reg, swap_reg);
1160 get_thread(swap_reg);
1161 xorptr(swap_reg, tmp_reg);
1162 Register header_reg = swap_reg;
1163 #endif
1164 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1165 if (counters != NULL) {
1166 cond_inc32(Assembler::zero,
1167 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1168 }
1169 jcc(Assembler::equal, done);
1170
1171 Label try_revoke_bias;
1172 Label try_rebias;
1173
1174 // At this point we know that the header has the bias pattern and
1175 // that we are not the bias owner in the current epoch. We need to
1176 // figure out more details about the state of the header in order to
1177 // know what operations can be legally performed on the object's
1178 // header.
1179
1180 // If the low three bits in the xor result aren't clear, that means
1181 // the prototype header is no longer biased and we have to revoke
1182 // the bias on this object.
1183 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1184 jccb(Assembler::notZero, try_revoke_bias);
1185
1186 // Biasing is still enabled for this data type. See whether the
1187 // epoch of the current bias is still valid, meaning that the epoch
1188 // bits of the mark word are equal to the epoch bits of the
1189 // prototype header. (Note that the prototype header's epoch bits
1190 // only change at a safepoint.) If not, attempt to rebias the object
1191 // toward the current thread. Note that we must be absolutely sure
1192 // that the current epoch is invalid in order to do this because
1193 // otherwise the manipulations it performs on the mark word are
1194 // illegal.
1195 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1196 jccb(Assembler::notZero, try_rebias);
1197
1198 // The epoch of the current bias is still valid but we know nothing
1199 // about the owner; it might be set or it might be clear. Try to
1200 // acquire the bias of the object using an atomic operation. If this
1201 // fails we will go in to the runtime to revoke the object's bias.
1202 // Note that we first construct the presumed unbiased header so we
1203 // don't accidentally blow away another thread's valid bias.
1204 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1205 andptr(swap_reg,
1206 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1207 #ifdef _LP64
1208 movptr(tmp_reg, swap_reg);
1209 orptr(tmp_reg, r15_thread);
1210 #else
1211 get_thread(tmp_reg);
1212 orptr(tmp_reg, swap_reg);
1213 #endif
1214 lock();
1215 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1216 // If the biasing toward our thread failed, this means that
1217 // another thread succeeded in biasing it toward itself and we
1218 // need to revoke that bias. The revocation will occur in the
1219 // interpreter runtime in the slow case.
1220 if (counters != NULL) {
1221 cond_inc32(Assembler::zero,
1222 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1223 }
1224 if (slow_case != NULL) {
1225 jcc(Assembler::notZero, *slow_case);
1226 }
1227 jmp(done);
1228
1229 bind(try_rebias);
1230 // At this point we know the epoch has expired, meaning that the
1231 // current "bias owner", if any, is actually invalid. Under these
1232 // circumstances _only_, we are allowed to use the current header's
1233 // value as the comparison value when doing the cas to acquire the
1234 // bias in the current epoch. In other words, we allow transfer of
1235 // the bias from one thread to another directly in this situation.
1236 //
1237 // FIXME: due to a lack of registers we currently blow away the age
1238 // bits in this situation. Should attempt to preserve them.
1239 load_prototype_header(tmp_reg, obj_reg);
1240 #ifdef _LP64
1241 orptr(tmp_reg, r15_thread);
1242 #else
1243 get_thread(swap_reg);
1244 orptr(tmp_reg, swap_reg);
1245 movptr(swap_reg, saved_mark_addr);
1246 #endif
1247 lock();
1248 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1249 // If the biasing toward our thread failed, then another thread
1250 // succeeded in biasing it toward itself and we need to revoke that
1251 // bias. The revocation will occur in the runtime in the slow case.
1252 if (counters != NULL) {
1253 cond_inc32(Assembler::zero,
1254 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1255 }
1256 if (slow_case != NULL) {
1257 jcc(Assembler::notZero, *slow_case);
1258 }
1259 jmp(done);
1260
1261 bind(try_revoke_bias);
1262 // The prototype mark in the klass doesn't have the bias bit set any
1263 // more, indicating that objects of this data type are not supposed
1264 // to be biased any more. We are going to try to reset the mark of
1265 // this object to the prototype value and fall through to the
1266 // CAS-based locking scheme. Note that if our CAS fails, it means
1267 // that another thread raced us for the privilege of revoking the
1268 // bias of this particular object, so it's okay to continue in the
1269 // normal locking code.
1270 //
1271 // FIXME: due to a lack of registers we currently blow away the age
1272 // bits in this situation. Should attempt to preserve them.
1273 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1274 load_prototype_header(tmp_reg, obj_reg);
1275 lock();
1276 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1277 // Fall through to the normal CAS-based lock, because no matter what
1278 // the result of the above CAS, some thread must have succeeded in
1279 // removing the bias bit from the object's header.
1280 if (counters != NULL) {
1281 cond_inc32(Assembler::zero,
1282 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1283 }
1284
1285 bind(cas_label);
1286
1287 return null_check_offset;
1288 }
1289
1290 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1291 assert(UseBiasedLocking, "why call this otherwise?");
1292
1293 // Check for biased locking unlock case, which is a no-op
1294 // Note: we do not have to check the thread ID for two reasons.
1295 // First, the interpreter checks for IllegalMonitorStateException at
1296 // a higher level. Second, if the bias was revoked while we held the
1297 // lock, the object could not be rebiased toward another thread, so
1298 // the bias bit would be clear.
1299 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1300 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1301 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1302 jcc(Assembler::equal, done);
1303 }
1304
1305 #ifdef COMPILER2
1306
1307 #if INCLUDE_RTM_OPT
1308
1309 // Update rtm_counters based on abort status
1310 // input: abort_status
1311 // rtm_counters (RTMLockingCounters*)
1312 // flags are killed
1313 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1314
1315 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1316 if (PrintPreciseRTMLockingStatistics) {
1317 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1318 Label check_abort;
1319 testl(abort_status, (1<<i));
1320 jccb(Assembler::equal, check_abort);
1321 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1322 bind(check_abort);
1323 }
1324 }
1325 }
1326
1327 // Branch if (random & (count-1) != 0), count is 2^n
1328 // tmp, scr and flags are killed
1329 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1330 assert(tmp == rax, "");
1331 assert(scr == rdx, "");
1332 rdtsc(); // modifies EDX:EAX
1333 andptr(tmp, count-1);
1334 jccb(Assembler::notZero, brLabel);
1335 }
1336
1337 // Perform abort ratio calculation, set no_rtm bit if high ratio
1338 // input: rtm_counters_Reg (RTMLockingCounters* address)
1339 // tmpReg, rtm_counters_Reg and flags are killed
1340 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1341 Register rtm_counters_Reg,
1342 RTMLockingCounters* rtm_counters,
1343 Metadata* method_data) {
1344 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1345
1346 if (RTMLockingCalculationDelay > 0) {
1347 // Delay calculation
1348 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1349 testptr(tmpReg, tmpReg);
1350 jccb(Assembler::equal, L_done);
1351 }
1352 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1353 // Aborted transactions = abort_count * 100
1354 // All transactions = total_count * RTMTotalCountIncrRate
1355 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1356
1357 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1358 cmpptr(tmpReg, RTMAbortThreshold);
1359 jccb(Assembler::below, L_check_always_rtm2);
1360 imulptr(tmpReg, tmpReg, 100);
1361
1362 Register scrReg = rtm_counters_Reg;
1363 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1364 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1365 imulptr(scrReg, scrReg, RTMAbortRatio);
1366 cmpptr(tmpReg, scrReg);
1367 jccb(Assembler::below, L_check_always_rtm1);
1368 if (method_data != NULL) {
1369 // set rtm_state to "no rtm" in MDO
1370 mov_metadata(tmpReg, method_data);
1371 lock();
1372 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1373 }
1374 jmpb(L_done);
1375 bind(L_check_always_rtm1);
1376 // Reload RTMLockingCounters* address
1377 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1378 bind(L_check_always_rtm2);
1379 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1380 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1381 jccb(Assembler::below, L_done);
1382 if (method_data != NULL) {
1383 // set rtm_state to "always rtm" in MDO
1384 mov_metadata(tmpReg, method_data);
1385 lock();
1386 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1387 }
1388 bind(L_done);
1389 }
1390
1391 // Update counters and perform abort ratio calculation
1392 // input: abort_status_Reg
1393 // rtm_counters_Reg, flags are killed
1394 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1395 Register rtm_counters_Reg,
1396 RTMLockingCounters* rtm_counters,
1397 Metadata* method_data,
1398 bool profile_rtm) {
1399
1400 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1401 // update rtm counters based on rax value at abort
1402 // reads abort_status_Reg, updates flags
1403 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1404 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1405 if (profile_rtm) {
1406 // Save abort status because abort_status_Reg is used by following code.
1407 if (RTMRetryCount > 0) {
1408 push(abort_status_Reg);
1409 }
1410 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1411 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1412 // restore abort status
1413 if (RTMRetryCount > 0) {
1414 pop(abort_status_Reg);
1415 }
1416 }
1417 }
1418
1419 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1420 // inputs: retry_count_Reg
1421 // : abort_status_Reg
1422 // output: retry_count_Reg decremented by 1
1423 // flags are killed
1424 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1425 Label doneRetry;
1426 assert(abort_status_Reg == rax, "");
1427 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1428 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1429 // if reason is in 0x6 and retry count != 0 then retry
1430 andptr(abort_status_Reg, 0x6);
1431 jccb(Assembler::zero, doneRetry);
1432 testl(retry_count_Reg, retry_count_Reg);
1433 jccb(Assembler::zero, doneRetry);
1434 pause();
1435 decrementl(retry_count_Reg);
1436 jmp(retryLabel);
1437 bind(doneRetry);
1438 }
1439
1440 // Spin and retry if lock is busy,
1441 // inputs: box_Reg (monitor address)
1442 // : retry_count_Reg
1443 // output: retry_count_Reg decremented by 1
1444 // : clear z flag if retry count exceeded
1445 // tmp_Reg, scr_Reg, flags are killed
1446 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1447 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1448 Label SpinLoop, SpinExit, doneRetry;
1449 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1450
1451 testl(retry_count_Reg, retry_count_Reg);
1452 jccb(Assembler::zero, doneRetry);
1453 decrementl(retry_count_Reg);
1454 movptr(scr_Reg, RTMSpinLoopCount);
1455
1456 bind(SpinLoop);
1457 pause();
1458 decrementl(scr_Reg);
1459 jccb(Assembler::lessEqual, SpinExit);
1460 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1461 testptr(tmp_Reg, tmp_Reg);
1462 jccb(Assembler::notZero, SpinLoop);
1463
1464 bind(SpinExit);
1465 jmp(retryLabel);
1466 bind(doneRetry);
1467 incrementl(retry_count_Reg); // clear z flag
1468 }
1469
1470 // Use RTM for normal stack locks
1471 // Input: objReg (object to lock)
1472 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1473 Register retry_on_abort_count_Reg,
1474 RTMLockingCounters* stack_rtm_counters,
1475 Metadata* method_data, bool profile_rtm,
1476 Label& DONE_LABEL, Label& IsInflated) {
1477 assert(UseRTMForStackLocks, "why call this otherwise?");
1478 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1479 assert(tmpReg == rax, "");
1480 assert(scrReg == rdx, "");
1481 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1482
1483 if (RTMRetryCount > 0) {
1484 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1485 bind(L_rtm_retry);
1486 }
1487 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1488 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1489 jcc(Assembler::notZero, IsInflated);
1490
1491 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1492 Label L_noincrement;
1493 if (RTMTotalCountIncrRate > 1) {
1494 // tmpReg, scrReg and flags are killed
1495 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1496 }
1497 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1498 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1499 bind(L_noincrement);
1500 }
1501 xbegin(L_on_abort);
1502 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1503 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1504 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1505 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1506
1507 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1508 if (UseRTMXendForLockBusy) {
1509 xend();
1510 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1511 jmp(L_decrement_retry);
1512 }
1513 else {
1514 xabort(0);
1515 }
1516 bind(L_on_abort);
1517 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1518 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1519 }
1520 bind(L_decrement_retry);
1521 if (RTMRetryCount > 0) {
1522 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1523 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1524 }
1525 }
1526
1527 // Use RTM for inflating locks
1528 // inputs: objReg (object to lock)
1529 // boxReg (on-stack box address (displaced header location) - KILLED)
1530 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1531 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1532 Register scrReg, Register retry_on_busy_count_Reg,
1533 Register retry_on_abort_count_Reg,
1534 RTMLockingCounters* rtm_counters,
1535 Metadata* method_data, bool profile_rtm,
1536 Label& DONE_LABEL) {
1537 assert(UseRTMLocking, "why call this otherwise?");
1538 assert(tmpReg == rax, "");
1539 assert(scrReg == rdx, "");
1540 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1541 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1542
1543 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1544 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1545 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1546
1547 if (RTMRetryCount > 0) {
1548 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1549 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1550 bind(L_rtm_retry);
1551 }
1552 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1553 Label L_noincrement;
1554 if (RTMTotalCountIncrRate > 1) {
1555 // tmpReg, scrReg and flags are killed
1556 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1557 }
1558 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1559 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1560 bind(L_noincrement);
1561 }
1562 xbegin(L_on_abort);
1563 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1564 movptr(tmpReg, Address(tmpReg, owner_offset));
1565 testptr(tmpReg, tmpReg);
1566 jcc(Assembler::zero, DONE_LABEL);
1567 if (UseRTMXendForLockBusy) {
1568 xend();
1569 jmp(L_decrement_retry);
1570 }
1571 else {
1572 xabort(0);
1573 }
1574 bind(L_on_abort);
1575 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1576 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1577 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1578 }
1579 if (RTMRetryCount > 0) {
1580 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1581 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1582 }
1583
1584 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1585 testptr(tmpReg, tmpReg) ;
1586 jccb(Assembler::notZero, L_decrement_retry) ;
1587
1588 // Appears unlocked - try to swing _owner from null to non-null.
1589 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1590 #ifdef _LP64
1591 Register threadReg = r15_thread;
1592 #else
1593 get_thread(scrReg);
1594 Register threadReg = scrReg;
1595 #endif
1596 lock();
1597 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1598
1599 if (RTMRetryCount > 0) {
1600 // success done else retry
1601 jccb(Assembler::equal, DONE_LABEL) ;
1602 bind(L_decrement_retry);
1603 // Spin and retry if lock is busy.
1604 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1605 }
1606 else {
1607 bind(L_decrement_retry);
1608 }
1609 }
1610
1611 #endif // INCLUDE_RTM_OPT
1612
1613 // Fast_Lock and Fast_Unlock used by C2
1614
1615 // Because the transitions from emitted code to the runtime
1616 // monitorenter/exit helper stubs are so slow it's critical that
1617 // we inline both the stack-locking fast-path and the inflated fast path.
1618 //
1619 // See also: cmpFastLock and cmpFastUnlock.
1620 //
1621 // What follows is a specialized inline transliteration of the code
1622 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1623 // another option would be to emit TrySlowEnter and TrySlowExit methods
1624 // at startup-time. These methods would accept arguments as
1625 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1626 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1627 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1628 // In practice, however, the # of lock sites is bounded and is usually small.
1629 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1630 // if the processor uses simple bimodal branch predictors keyed by EIP
1631 // Since the helper routines would be called from multiple synchronization
1632 // sites.
1633 //
1634 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1635 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1636 // to those specialized methods. That'd give us a mostly platform-independent
1637 // implementation that the JITs could optimize and inline at their pleasure.
1638 // Done correctly, the only time we'd need to cross to native could would be
1639 // to park() or unpark() threads. We'd also need a few more unsafe operators
1640 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1641 // (b) explicit barriers or fence operations.
1642 //
1643 // TODO:
1644 //
1645 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1646 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1647 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1648 // the lock operators would typically be faster than reifying Self.
1649 //
1650 // * Ideally I'd define the primitives as:
1651 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1652 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1653 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1654 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1655 // Furthermore the register assignments are overconstrained, possibly resulting in
1656 // sub-optimal code near the synchronization site.
1657 //
1658 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1659 // Alternately, use a better sp-proximity test.
1660 //
1661 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1662 // Either one is sufficient to uniquely identify a thread.
1663 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1664 //
1665 // * Intrinsify notify() and notifyAll() for the common cases where the
1666 // object is locked by the calling thread but the waitlist is empty.
1667 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1668 //
1669 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1670 // But beware of excessive branch density on AMD Opterons.
1671 //
1672 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1673 // or failure of the fast-path. If the fast-path fails then we pass
1674 // control to the slow-path, typically in C. In Fast_Lock and
1675 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1676 // will emit a conditional branch immediately after the node.
1677 // So we have branches to branches and lots of ICC.ZF games.
1678 // Instead, it might be better to have C2 pass a "FailureLabel"
1679 // into Fast_Lock and Fast_Unlock. In the case of success, control
1680 // will drop through the node. ICC.ZF is undefined at exit.
1681 // In the case of failure, the node will branch directly to the
1682 // FailureLabel
1683
1684
1685 // obj: object to lock
1686 // box: on-stack box address (displaced header location) - KILLED
1687 // rax,: tmp -- KILLED
1688 // scr: tmp -- KILLED
1689 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1690 Register scrReg, Register cx1Reg, Register cx2Reg,
1691 BiasedLockingCounters* counters,
1692 RTMLockingCounters* rtm_counters,
1693 RTMLockingCounters* stack_rtm_counters,
1694 Metadata* method_data,
1695 bool use_rtm, bool profile_rtm) {
1696 // Ensure the register assignments are disjoint
1697 assert(tmpReg == rax, "");
1698
1699 if (use_rtm) {
1700 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1701 } else {
1702 assert(cx1Reg == noreg, "");
1703 assert(cx2Reg == noreg, "");
1704 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1705 }
1706
1707 if (counters != NULL) {
1708 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1709 }
1710
1711 // Possible cases that we'll encounter in fast_lock
1712 // ------------------------------------------------
1713 // * Inflated
1714 // -- unlocked
1715 // -- Locked
1716 // = by self
1717 // = by other
1718 // * biased
1719 // -- by Self
1720 // -- by other
1721 // * neutral
1722 // * stack-locked
1723 // -- by self
1724 // = sp-proximity test hits
1725 // = sp-proximity test generates false-negative
1726 // -- by other
1727 //
1728
1729 Label IsInflated, DONE_LABEL;
1730
1731 // it's stack-locked, biased or neutral
1732 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1733 // order to reduce the number of conditional branches in the most common cases.
1734 // Beware -- there's a subtle invariant that fetch of the markword
1735 // at [FETCH], below, will never observe a biased encoding (*101b).
1736 // If this invariant is not held we risk exclusion (safety) failure.
1737 if (UseBiasedLocking && !UseOptoBiasInlining) {
1738 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1739 }
1740
1741 #if INCLUDE_RTM_OPT
1742 if (UseRTMForStackLocks && use_rtm) {
1743 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1744 stack_rtm_counters, method_data, profile_rtm,
1745 DONE_LABEL, IsInflated);
1746 }
1747 #endif // INCLUDE_RTM_OPT
1748
1749 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1750 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1751 jccb(Assembler::notZero, IsInflated);
1752
1753 // Attempt stack-locking ...
1754 orptr (tmpReg, markOopDesc::unlocked_value);
1755 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1756 lock();
1757 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1758 if (counters != NULL) {
1759 cond_inc32(Assembler::equal,
1760 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1761 }
1762 jcc(Assembler::equal, DONE_LABEL); // Success
1763
1764 // Recursive locking.
1765 // The object is stack-locked: markword contains stack pointer to BasicLock.
1766 // Locked by current thread if difference with current SP is less than one page.
1767 subptr(tmpReg, rsp);
1768 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1769 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1770 movptr(Address(boxReg, 0), tmpReg);
1771 if (counters != NULL) {
1772 cond_inc32(Assembler::equal,
1773 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1774 }
1775 jmp(DONE_LABEL);
1776
1777 bind(IsInflated);
1778 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1779
1780 #if INCLUDE_RTM_OPT
1781 // Use the same RTM locking code in 32- and 64-bit VM.
1782 if (use_rtm) {
1783 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1784 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1785 } else {
1786 #endif // INCLUDE_RTM_OPT
1787
1788 #ifndef _LP64
1789 // The object is inflated.
1790
1791 // boxReg refers to the on-stack BasicLock in the current frame.
1792 // We'd like to write:
1793 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1794 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1795 // additional latency as we have another ST in the store buffer that must drain.
1796
1797 // avoid ST-before-CAS
1798 // register juggle because we need tmpReg for cmpxchgptr below
1799 movptr(scrReg, boxReg);
1800 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1801
1802 // Optimistic form: consider XORL tmpReg,tmpReg
1803 movptr(tmpReg, NULL_WORD);
1804
1805 // Appears unlocked - try to swing _owner from null to non-null.
1806 // Ideally, I'd manifest "Self" with get_thread and then attempt
1807 // to CAS the register containing Self into m->Owner.
1808 // But we don't have enough registers, so instead we can either try to CAS
1809 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1810 // we later store "Self" into m->Owner. Transiently storing a stack address
1811 // (rsp or the address of the box) into m->owner is harmless.
1812 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1813 lock();
1814 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1815 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1816 // If we weren't able to swing _owner from NULL to the BasicLock
1817 // then take the slow path.
1818 jccb (Assembler::notZero, DONE_LABEL);
1819 // update _owner from BasicLock to thread
1820 get_thread (scrReg); // beware: clobbers ICCs
1821 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1822 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1823
1824 // If the CAS fails we can either retry or pass control to the slow-path.
1825 // We use the latter tactic.
1826 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1827 // If the CAS was successful ...
1828 // Self has acquired the lock
1829 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1830 // Intentional fall-through into DONE_LABEL ...
1831 #else // _LP64
1832 // It's inflated
1833 movq(scrReg, tmpReg);
1834 xorq(tmpReg, tmpReg);
1835
1836 lock();
1837 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1838 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1839 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1840 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1841 // Intentional fall-through into DONE_LABEL ...
1842 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1843 #endif // _LP64
1844 #if INCLUDE_RTM_OPT
1845 } // use_rtm()
1846 #endif
1847 // DONE_LABEL is a hot target - we'd really like to place it at the
1848 // start of cache line by padding with NOPs.
1849 // See the AMD and Intel software optimization manuals for the
1850 // most efficient "long" NOP encodings.
1851 // Unfortunately none of our alignment mechanisms suffice.
1852 bind(DONE_LABEL);
1853
1854 // At DONE_LABEL the icc ZFlag is set as follows ...
1855 // Fast_Unlock uses the same protocol.
1856 // ZFlag == 1 -> Success
1857 // ZFlag == 0 -> Failure - force control through the slow-path
1858 }
1859
1860 // obj: object to unlock
1861 // box: box address (displaced header location), killed. Must be EAX.
1862 // tmp: killed, cannot be obj nor box.
1863 //
1864 // Some commentary on balanced locking:
1865 //
1866 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1867 // Methods that don't have provably balanced locking are forced to run in the
1868 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1869 // The interpreter provides two properties:
1870 // I1: At return-time the interpreter automatically and quietly unlocks any
1871 // objects acquired the current activation (frame). Recall that the
1872 // interpreter maintains an on-stack list of locks currently held by
1873 // a frame.
1874 // I2: If a method attempts to unlock an object that is not held by the
1875 // the frame the interpreter throws IMSX.
1876 //
1877 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1878 // B() doesn't have provably balanced locking so it runs in the interpreter.
1879 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1880 // is still locked by A().
1881 //
1882 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1883 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1884 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1885 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1886 // Arguably given that the spec legislates the JNI case as undefined our implementation
1887 // could reasonably *avoid* checking owner in Fast_Unlock().
1888 // In the interest of performance we elide m->Owner==Self check in unlock.
1889 // A perfectly viable alternative is to elide the owner check except when
1890 // Xcheck:jni is enabled.
1891
1892 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1893 assert(boxReg == rax, "");
1894 assert_different_registers(objReg, boxReg, tmpReg);
1895
1896 Label DONE_LABEL, Stacked, CheckSucc;
1897
1898 // Critically, the biased locking test must have precedence over
1899 // and appear before the (box->dhw == 0) recursive stack-lock test.
1900 if (UseBiasedLocking && !UseOptoBiasInlining) {
1901 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1902 }
1903
1904 #if INCLUDE_RTM_OPT
1905 if (UseRTMForStackLocks && use_rtm) {
1906 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1907 Label L_regular_unlock;
1908 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1909 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1910 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1911 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1912 xend(); // otherwise end...
1913 jmp(DONE_LABEL); // ... and we're done
1914 bind(L_regular_unlock);
1915 }
1916 #endif
1917
1918 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1919 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
1920 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
1921 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
1922 jccb (Assembler::zero, Stacked);
1923
1924 // It's inflated.
1925 #if INCLUDE_RTM_OPT
1926 if (use_rtm) {
1927 Label L_regular_inflated_unlock;
1928 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1929 movptr(boxReg, Address(tmpReg, owner_offset));
1930 testptr(boxReg, boxReg);
1931 jccb(Assembler::notZero, L_regular_inflated_unlock);
1932 xend();
1933 jmpb(DONE_LABEL);
1934 bind(L_regular_inflated_unlock);
1935 }
1936 #endif
1937
1938 // Despite our balanced locking property we still check that m->_owner == Self
1939 // as java routines or native JNI code called by this thread might
1940 // have released the lock.
1941 // Refer to the comments in synchronizer.cpp for how we might encode extra
1942 // state in _succ so we can avoid fetching EntryList|cxq.
1943 //
1944 // I'd like to add more cases in fast_lock() and fast_unlock() --
1945 // such as recursive enter and exit -- but we have to be wary of
1946 // I$ bloat, T$ effects and BP$ effects.
1947 //
1948 // If there's no contention try a 1-0 exit. That is, exit without
1949 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
1950 // we detect and recover from the race that the 1-0 exit admits.
1951 //
1952 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
1953 // before it STs null into _owner, releasing the lock. Updates
1954 // to data protected by the critical section must be visible before
1955 // we drop the lock (and thus before any other thread could acquire
1956 // the lock and observe the fields protected by the lock).
1957 // IA32's memory-model is SPO, so STs are ordered with respect to
1958 // each other and there's no need for an explicit barrier (fence).
1959 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
1960 #ifndef _LP64
1961 get_thread (boxReg);
1962
1963 // Note that we could employ various encoding schemes to reduce
1964 // the number of loads below (currently 4) to just 2 or 3.
1965 // Refer to the comments in synchronizer.cpp.
1966 // In practice the chain of fetches doesn't seem to impact performance, however.
1967 xorptr(boxReg, boxReg);
1968 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
1969 jccb (Assembler::notZero, DONE_LABEL);
1970 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
1971 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
1972 jccb (Assembler::notZero, CheckSucc);
1973 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
1974 jmpb (DONE_LABEL);
1975
1976 bind (Stacked);
1977 // It's not inflated and it's not recursively stack-locked and it's not biased.
1978 // It must be stack-locked.
1979 // Try to reset the header to displaced header.
1980 // The "box" value on the stack is stable, so we can reload
1981 // and be assured we observe the same value as above.
1982 movptr(tmpReg, Address(boxReg, 0));
1983 lock();
1984 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
1985 // Intention fall-thru into DONE_LABEL
1986
1987 // DONE_LABEL is a hot target - we'd really like to place it at the
1988 // start of cache line by padding with NOPs.
1989 // See the AMD and Intel software optimization manuals for the
1990 // most efficient "long" NOP encodings.
1991 // Unfortunately none of our alignment mechanisms suffice.
1992 bind (CheckSucc);
1993 #else // _LP64
1994 // It's inflated
1995 xorptr(boxReg, boxReg);
1996 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
1997 jccb (Assembler::notZero, DONE_LABEL);
1998 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
1999 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2000 jccb (Assembler::notZero, CheckSucc);
2001 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2002 jmpb (DONE_LABEL);
2003
2004 // Try to avoid passing control into the slow_path ...
2005 Label LSuccess, LGoSlowPath ;
2006 bind (CheckSucc);
2007
2008 // The following optional optimization can be elided if necessary
2009 // Effectively: if (succ == null) goto SlowPath
2010 // The code reduces the window for a race, however,
2011 // and thus benefits performance.
2012 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2013 jccb (Assembler::zero, LGoSlowPath);
2014
2015 xorptr(boxReg, boxReg);
2016 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2017
2018 // Memory barrier/fence
2019 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2020 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2021 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2022 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2023 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2024 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2025 lock(); addl(Address(rsp, 0), 0);
2026
2027 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2028 jccb (Assembler::notZero, LSuccess);
2029
2030 // Rare inopportune interleaving - race.
2031 // The successor vanished in the small window above.
2032 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2033 // We need to ensure progress and succession.
2034 // Try to reacquire the lock.
2035 // If that fails then the new owner is responsible for succession and this
2036 // thread needs to take no further action and can exit via the fast path (success).
2037 // If the re-acquire succeeds then pass control into the slow path.
2038 // As implemented, this latter mode is horrible because we generated more
2039 // coherence traffic on the lock *and* artifically extended the critical section
2040 // length while by virtue of passing control into the slow path.
2041
2042 // box is really RAX -- the following CMPXCHG depends on that binding
2043 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2044 lock();
2045 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2046 // There's no successor so we tried to regrab the lock.
2047 // If that didn't work, then another thread grabbed the
2048 // lock so we're done (and exit was a success).
2049 jccb (Assembler::notEqual, LSuccess);
2050 // Intentional fall-through into slow-path
2051
2052 bind (LGoSlowPath);
2053 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2054 jmpb (DONE_LABEL);
2055
2056 bind (LSuccess);
2057 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2058 jmpb (DONE_LABEL);
2059
2060 bind (Stacked);
2061 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2062 lock();
2063 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2064
2065 #endif
2066 bind(DONE_LABEL);
2067 }
2068 #endif // COMPILER2
2069
2070 void MacroAssembler::c2bool(Register x) {
2071 // implements x == 0 ? 0 : 1
2072 // note: must only look at least-significant byte of x
2073 // since C-style booleans are stored in one byte
2074 // only! (was bug)
2075 andl(x, 0xFF);
2076 setb(Assembler::notZero, x);
2077 }
2078
2079 // Wouldn't need if AddressLiteral version had new name
2080 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2081 Assembler::call(L, rtype);
2082 }
2083
2084 void MacroAssembler::call(Register entry) {
2085 Assembler::call(entry);
2086 }
2087
2088 void MacroAssembler::call(AddressLiteral entry) {
2089 if (reachable(entry)) {
2090 Assembler::call_literal(entry.target(), entry.rspec());
2091 } else {
2092 lea(rscratch1, entry);
2093 Assembler::call(rscratch1);
2094 }
2095 }
2096
2097 void MacroAssembler::ic_call(address entry, jint method_index) {
2098 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2099 movptr(rax, (intptr_t)Universe::non_oop_word());
2100 call(AddressLiteral(entry, rh));
2101 }
2102
2103 // Implementation of call_VM versions
2104
2105 void MacroAssembler::call_VM(Register oop_result,
2106 address entry_point,
2107 bool check_exceptions) {
2108 Label C, E;
2109 call(C, relocInfo::none);
2110 jmp(E);
2111
2112 bind(C);
2113 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2114 ret(0);
2115
2116 bind(E);
2117 }
2118
2119 void MacroAssembler::call_VM(Register oop_result,
2120 address entry_point,
2121 Register arg_1,
2122 bool check_exceptions) {
2123 Label C, E;
2124 call(C, relocInfo::none);
2125 jmp(E);
2126
2127 bind(C);
2128 pass_arg1(this, arg_1);
2129 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2130 ret(0);
2131
2132 bind(E);
2133 }
2134
2135 void MacroAssembler::call_VM(Register oop_result,
2136 address entry_point,
2137 Register arg_1,
2138 Register arg_2,
2139 bool check_exceptions) {
2140 Label C, E;
2141 call(C, relocInfo::none);
2142 jmp(E);
2143
2144 bind(C);
2145
2146 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2147
2148 pass_arg2(this, arg_2);
2149 pass_arg1(this, arg_1);
2150 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2151 ret(0);
2152
2153 bind(E);
2154 }
2155
2156 void MacroAssembler::call_VM(Register oop_result,
2157 address entry_point,
2158 Register arg_1,
2159 Register arg_2,
2160 Register arg_3,
2161 bool check_exceptions) {
2162 Label C, E;
2163 call(C, relocInfo::none);
2164 jmp(E);
2165
2166 bind(C);
2167
2168 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2169 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2170 pass_arg3(this, arg_3);
2171
2172 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2173 pass_arg2(this, arg_2);
2174
2175 pass_arg1(this, arg_1);
2176 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2177 ret(0);
2178
2179 bind(E);
2180 }
2181
2182 void MacroAssembler::call_VM(Register oop_result,
2183 Register last_java_sp,
2184 address entry_point,
2185 int number_of_arguments,
2186 bool check_exceptions) {
2187 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2188 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2189 }
2190
2191 void MacroAssembler::call_VM(Register oop_result,
2192 Register last_java_sp,
2193 address entry_point,
2194 Register arg_1,
2195 bool check_exceptions) {
2196 pass_arg1(this, arg_1);
2197 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2198 }
2199
2200 void MacroAssembler::call_VM(Register oop_result,
2201 Register last_java_sp,
2202 address entry_point,
2203 Register arg_1,
2204 Register arg_2,
2205 bool check_exceptions) {
2206
2207 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2208 pass_arg2(this, arg_2);
2209 pass_arg1(this, arg_1);
2210 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2211 }
2212
2213 void MacroAssembler::call_VM(Register oop_result,
2214 Register last_java_sp,
2215 address entry_point,
2216 Register arg_1,
2217 Register arg_2,
2218 Register arg_3,
2219 bool check_exceptions) {
2220 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2221 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2222 pass_arg3(this, arg_3);
2223 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2224 pass_arg2(this, arg_2);
2225 pass_arg1(this, arg_1);
2226 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2227 }
2228
2229 void MacroAssembler::super_call_VM(Register oop_result,
2230 Register last_java_sp,
2231 address entry_point,
2232 int number_of_arguments,
2233 bool check_exceptions) {
2234 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2235 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2236 }
2237
2238 void MacroAssembler::super_call_VM(Register oop_result,
2239 Register last_java_sp,
2240 address entry_point,
2241 Register arg_1,
2242 bool check_exceptions) {
2243 pass_arg1(this, arg_1);
2244 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2245 }
2246
2247 void MacroAssembler::super_call_VM(Register oop_result,
2248 Register last_java_sp,
2249 address entry_point,
2250 Register arg_1,
2251 Register arg_2,
2252 bool check_exceptions) {
2253
2254 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2255 pass_arg2(this, arg_2);
2256 pass_arg1(this, arg_1);
2257 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2258 }
2259
2260 void MacroAssembler::super_call_VM(Register oop_result,
2261 Register last_java_sp,
2262 address entry_point,
2263 Register arg_1,
2264 Register arg_2,
2265 Register arg_3,
2266 bool check_exceptions) {
2267 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2268 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2269 pass_arg3(this, arg_3);
2270 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2271 pass_arg2(this, arg_2);
2272 pass_arg1(this, arg_1);
2273 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2274 }
2275
2276 void MacroAssembler::call_VM_base(Register oop_result,
2277 Register java_thread,
2278 Register last_java_sp,
2279 address entry_point,
2280 int number_of_arguments,
2281 bool check_exceptions) {
2282 // determine java_thread register
2283 if (!java_thread->is_valid()) {
2284 #ifdef _LP64
2285 java_thread = r15_thread;
2286 #else
2287 java_thread = rdi;
2288 get_thread(java_thread);
2289 #endif // LP64
2290 }
2291 // determine last_java_sp register
2292 if (!last_java_sp->is_valid()) {
2293 last_java_sp = rsp;
2294 }
2295 // debugging support
2296 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2297 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2298 #ifdef ASSERT
2299 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2300 // r12 is the heapbase.
2301 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2302 #endif // ASSERT
2303
2304 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2305 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2306
2307 // push java thread (becomes first argument of C function)
2308
2309 NOT_LP64(push(java_thread); number_of_arguments++);
2310 LP64_ONLY(mov(c_rarg0, r15_thread));
2311
2312 // set last Java frame before call
2313 assert(last_java_sp != rbp, "can't use ebp/rbp");
2314
2315 // Only interpreter should have to set fp
2316 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2317
2318 // do the call, remove parameters
2319 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2320
2321 // restore the thread (cannot use the pushed argument since arguments
2322 // may be overwritten by C code generated by an optimizing compiler);
2323 // however can use the register value directly if it is callee saved.
2324 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2325 // rdi & rsi (also r15) are callee saved -> nothing to do
2326 #ifdef ASSERT
2327 guarantee(java_thread != rax, "change this code");
2328 push(rax);
2329 { Label L;
2330 get_thread(rax);
2331 cmpptr(java_thread, rax);
2332 jcc(Assembler::equal, L);
2333 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2334 bind(L);
2335 }
2336 pop(rax);
2337 #endif
2338 } else {
2339 get_thread(java_thread);
2340 }
2341 // reset last Java frame
2342 // Only interpreter should have to clear fp
2343 reset_last_Java_frame(java_thread, true);
2344
2345 // C++ interp handles this in the interpreter
2346 check_and_handle_popframe(java_thread);
2347 check_and_handle_earlyret(java_thread);
2348
2349 if (check_exceptions) {
2350 // check for pending exceptions (java_thread is set upon return)
2351 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2352 #ifndef _LP64
2353 jump_cc(Assembler::notEqual,
2354 RuntimeAddress(StubRoutines::forward_exception_entry()));
2355 #else
2356 // This used to conditionally jump to forward_exception however it is
2357 // possible if we relocate that the branch will not reach. So we must jump
2358 // around so we can always reach
2359
2360 Label ok;
2361 jcc(Assembler::equal, ok);
2362 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2363 bind(ok);
2364 #endif // LP64
2365 }
2366
2367 // get oop result if there is one and reset the value in the thread
2368 if (oop_result->is_valid()) {
2369 get_vm_result(oop_result, java_thread);
2370 }
2371 }
2372
2373 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2374
2375 // Calculate the value for last_Java_sp
2376 // somewhat subtle. call_VM does an intermediate call
2377 // which places a return address on the stack just under the
2378 // stack pointer as the user finsihed with it. This allows
2379 // use to retrieve last_Java_pc from last_Java_sp[-1].
2380 // On 32bit we then have to push additional args on the stack to accomplish
2381 // the actual requested call. On 64bit call_VM only can use register args
2382 // so the only extra space is the return address that call_VM created.
2383 // This hopefully explains the calculations here.
2384
2385 #ifdef _LP64
2386 // We've pushed one address, correct last_Java_sp
2387 lea(rax, Address(rsp, wordSize));
2388 #else
2389 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2390 #endif // LP64
2391
2392 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2393
2394 }
2395
2396 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2397 void MacroAssembler::call_VM_leaf0(address entry_point) {
2398 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2399 }
2400
2401 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2402 call_VM_leaf_base(entry_point, number_of_arguments);
2403 }
2404
2405 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2406 pass_arg0(this, arg_0);
2407 call_VM_leaf(entry_point, 1);
2408 }
2409
2410 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2411
2412 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2413 pass_arg1(this, arg_1);
2414 pass_arg0(this, arg_0);
2415 call_VM_leaf(entry_point, 2);
2416 }
2417
2418 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2419 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2420 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2421 pass_arg2(this, arg_2);
2422 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2423 pass_arg1(this, arg_1);
2424 pass_arg0(this, arg_0);
2425 call_VM_leaf(entry_point, 3);
2426 }
2427
2428 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2429 pass_arg0(this, arg_0);
2430 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2431 }
2432
2433 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2434
2435 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2436 pass_arg1(this, arg_1);
2437 pass_arg0(this, arg_0);
2438 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2439 }
2440
2441 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2442 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2443 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2444 pass_arg2(this, arg_2);
2445 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2446 pass_arg1(this, arg_1);
2447 pass_arg0(this, arg_0);
2448 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2449 }
2450
2451 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2452 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2453 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2454 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2455 pass_arg3(this, arg_3);
2456 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2457 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2458 pass_arg2(this, arg_2);
2459 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2460 pass_arg1(this, arg_1);
2461 pass_arg0(this, arg_0);
2462 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2463 }
2464
2465 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2466 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2467 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2468 verify_oop(oop_result, "broken oop in call_VM_base");
2469 }
2470
2471 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2472 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2473 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2474 }
2475
2476 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2477 }
2478
2479 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2480 }
2481
2482 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2483 if (reachable(src1)) {
2484 cmpl(as_Address(src1), imm);
2485 } else {
2486 lea(rscratch1, src1);
2487 cmpl(Address(rscratch1, 0), imm);
2488 }
2489 }
2490
2491 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2492 assert(!src2.is_lval(), "use cmpptr");
2493 if (reachable(src2)) {
2494 cmpl(src1, as_Address(src2));
2495 } else {
2496 lea(rscratch1, src2);
2497 cmpl(src1, Address(rscratch1, 0));
2498 }
2499 }
2500
2501 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2502 Assembler::cmpl(src1, imm);
2503 }
2504
2505 void MacroAssembler::cmp32(Register src1, Address src2) {
2506 Assembler::cmpl(src1, src2);
2507 }
2508
2509 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2510 ucomisd(opr1, opr2);
2511
2512 Label L;
2513 if (unordered_is_less) {
2514 movl(dst, -1);
2515 jcc(Assembler::parity, L);
2516 jcc(Assembler::below , L);
2517 movl(dst, 0);
2518 jcc(Assembler::equal , L);
2519 increment(dst);
2520 } else { // unordered is greater
2521 movl(dst, 1);
2522 jcc(Assembler::parity, L);
2523 jcc(Assembler::above , L);
2524 movl(dst, 0);
2525 jcc(Assembler::equal , L);
2526 decrementl(dst);
2527 }
2528 bind(L);
2529 }
2530
2531 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2532 ucomiss(opr1, opr2);
2533
2534 Label L;
2535 if (unordered_is_less) {
2536 movl(dst, -1);
2537 jcc(Assembler::parity, L);
2538 jcc(Assembler::below , L);
2539 movl(dst, 0);
2540 jcc(Assembler::equal , L);
2541 increment(dst);
2542 } else { // unordered is greater
2543 movl(dst, 1);
2544 jcc(Assembler::parity, L);
2545 jcc(Assembler::above , L);
2546 movl(dst, 0);
2547 jcc(Assembler::equal , L);
2548 decrementl(dst);
2549 }
2550 bind(L);
2551 }
2552
2553
2554 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2555 if (reachable(src1)) {
2556 cmpb(as_Address(src1), imm);
2557 } else {
2558 lea(rscratch1, src1);
2559 cmpb(Address(rscratch1, 0), imm);
2560 }
2561 }
2562
2563 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2564 #ifdef _LP64
2565 if (src2.is_lval()) {
2566 movptr(rscratch1, src2);
2567 Assembler::cmpq(src1, rscratch1);
2568 } else if (reachable(src2)) {
2569 cmpq(src1, as_Address(src2));
2570 } else {
2571 lea(rscratch1, src2);
2572 Assembler::cmpq(src1, Address(rscratch1, 0));
2573 }
2574 #else
2575 if (src2.is_lval()) {
2576 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2577 } else {
2578 cmpl(src1, as_Address(src2));
2579 }
2580 #endif // _LP64
2581 }
2582
2583 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2584 assert(src2.is_lval(), "not a mem-mem compare");
2585 #ifdef _LP64
2586 // moves src2's literal address
2587 movptr(rscratch1, src2);
2588 Assembler::cmpq(src1, rscratch1);
2589 #else
2590 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2591 #endif // _LP64
2592 }
2593
2594 void MacroAssembler::cmpoop(Register src1, Register src2) {
2595 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2596 bs->obj_equals(this, src1, src2);
2597 }
2598
2599 void MacroAssembler::cmpoop(Register src1, Address src2) {
2600 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2601 bs->obj_equals(this, src1, src2);
2602 }
2603
2604 #ifdef _LP64
2605 void MacroAssembler::cmpoop(Register src1, jobject src2) {
2606 movoop(rscratch1, src2);
2607 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2608 bs->obj_equals(this, src1, rscratch1);
2609 }
2610 #endif
2611
2612 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2613 if (reachable(adr)) {
2614 lock();
2615 cmpxchgptr(reg, as_Address(adr));
2616 } else {
2617 lea(rscratch1, adr);
2618 lock();
2619 cmpxchgptr(reg, Address(rscratch1, 0));
2620 }
2621 }
2622
2623 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2624 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2625 }
2626
2627 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2628 if (reachable(src)) {
2629 Assembler::comisd(dst, as_Address(src));
2630 } else {
2631 lea(rscratch1, src);
2632 Assembler::comisd(dst, Address(rscratch1, 0));
2633 }
2634 }
2635
2636 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2637 if (reachable(src)) {
2638 Assembler::comiss(dst, as_Address(src));
2639 } else {
2640 lea(rscratch1, src);
2641 Assembler::comiss(dst, Address(rscratch1, 0));
2642 }
2643 }
2644
2645
2646 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2647 Condition negated_cond = negate_condition(cond);
2648 Label L;
2649 jcc(negated_cond, L);
2650 pushf(); // Preserve flags
2651 atomic_incl(counter_addr);
2652 popf();
2653 bind(L);
2654 }
2655
2656 int MacroAssembler::corrected_idivl(Register reg) {
2657 // Full implementation of Java idiv and irem; checks for
2658 // special case as described in JVM spec., p.243 & p.271.
2659 // The function returns the (pc) offset of the idivl
2660 // instruction - may be needed for implicit exceptions.
2661 //
2662 // normal case special case
2663 //
2664 // input : rax,: dividend min_int
2665 // reg: divisor (may not be rax,/rdx) -1
2666 //
2667 // output: rax,: quotient (= rax, idiv reg) min_int
2668 // rdx: remainder (= rax, irem reg) 0
2669 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2670 const int min_int = 0x80000000;
2671 Label normal_case, special_case;
2672
2673 // check for special case
2674 cmpl(rax, min_int);
2675 jcc(Assembler::notEqual, normal_case);
2676 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2677 cmpl(reg, -1);
2678 jcc(Assembler::equal, special_case);
2679
2680 // handle normal case
2681 bind(normal_case);
2682 cdql();
2683 int idivl_offset = offset();
2684 idivl(reg);
2685
2686 // normal and special case exit
2687 bind(special_case);
2688
2689 return idivl_offset;
2690 }
2691
2692
2693
2694 void MacroAssembler::decrementl(Register reg, int value) {
2695 if (value == min_jint) {subl(reg, value) ; return; }
2696 if (value < 0) { incrementl(reg, -value); return; }
2697 if (value == 0) { ; return; }
2698 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2699 /* else */ { subl(reg, value) ; return; }
2700 }
2701
2702 void MacroAssembler::decrementl(Address dst, int value) {
2703 if (value == min_jint) {subl(dst, value) ; return; }
2704 if (value < 0) { incrementl(dst, -value); return; }
2705 if (value == 0) { ; return; }
2706 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2707 /* else */ { subl(dst, value) ; return; }
2708 }
2709
2710 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2711 assert (shift_value > 0, "illegal shift value");
2712 Label _is_positive;
2713 testl (reg, reg);
2714 jcc (Assembler::positive, _is_positive);
2715 int offset = (1 << shift_value) - 1 ;
2716
2717 if (offset == 1) {
2718 incrementl(reg);
2719 } else {
2720 addl(reg, offset);
2721 }
2722
2723 bind (_is_positive);
2724 sarl(reg, shift_value);
2725 }
2726
2727 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2728 if (reachable(src)) {
2729 Assembler::divsd(dst, as_Address(src));
2730 } else {
2731 lea(rscratch1, src);
2732 Assembler::divsd(dst, Address(rscratch1, 0));
2733 }
2734 }
2735
2736 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2737 if (reachable(src)) {
2738 Assembler::divss(dst, as_Address(src));
2739 } else {
2740 lea(rscratch1, src);
2741 Assembler::divss(dst, Address(rscratch1, 0));
2742 }
2743 }
2744
2745 // !defined(COMPILER2) is because of stupid core builds
2746 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2747 void MacroAssembler::empty_FPU_stack() {
2748 if (VM_Version::supports_mmx()) {
2749 emms();
2750 } else {
2751 for (int i = 8; i-- > 0; ) ffree(i);
2752 }
2753 }
2754 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2755
2756
2757 void MacroAssembler::enter() {
2758 push(rbp);
2759 mov(rbp, rsp);
2760 }
2761
2762 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2763 void MacroAssembler::fat_nop() {
2764 if (UseAddressNop) {
2765 addr_nop_5();
2766 } else {
2767 emit_int8(0x26); // es:
2768 emit_int8(0x2e); // cs:
2769 emit_int8(0x64); // fs:
2770 emit_int8(0x65); // gs:
2771 emit_int8((unsigned char)0x90);
2772 }
2773 }
2774
2775 void MacroAssembler::fcmp(Register tmp) {
2776 fcmp(tmp, 1, true, true);
2777 }
2778
2779 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2780 assert(!pop_right || pop_left, "usage error");
2781 if (VM_Version::supports_cmov()) {
2782 assert(tmp == noreg, "unneeded temp");
2783 if (pop_left) {
2784 fucomip(index);
2785 } else {
2786 fucomi(index);
2787 }
2788 if (pop_right) {
2789 fpop();
2790 }
2791 } else {
2792 assert(tmp != noreg, "need temp");
2793 if (pop_left) {
2794 if (pop_right) {
2795 fcompp();
2796 } else {
2797 fcomp(index);
2798 }
2799 } else {
2800 fcom(index);
2801 }
2802 // convert FPU condition into eflags condition via rax,
2803 save_rax(tmp);
2804 fwait(); fnstsw_ax();
2805 sahf();
2806 restore_rax(tmp);
2807 }
2808 // condition codes set as follows:
2809 //
2810 // CF (corresponds to C0) if x < y
2811 // PF (corresponds to C2) if unordered
2812 // ZF (corresponds to C3) if x = y
2813 }
2814
2815 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2816 fcmp2int(dst, unordered_is_less, 1, true, true);
2817 }
2818
2819 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2820 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2821 Label L;
2822 if (unordered_is_less) {
2823 movl(dst, -1);
2824 jcc(Assembler::parity, L);
2825 jcc(Assembler::below , L);
2826 movl(dst, 0);
2827 jcc(Assembler::equal , L);
2828 increment(dst);
2829 } else { // unordered is greater
2830 movl(dst, 1);
2831 jcc(Assembler::parity, L);
2832 jcc(Assembler::above , L);
2833 movl(dst, 0);
2834 jcc(Assembler::equal , L);
2835 decrementl(dst);
2836 }
2837 bind(L);
2838 }
2839
2840 void MacroAssembler::fld_d(AddressLiteral src) {
2841 fld_d(as_Address(src));
2842 }
2843
2844 void MacroAssembler::fld_s(AddressLiteral src) {
2845 fld_s(as_Address(src));
2846 }
2847
2848 void MacroAssembler::fld_x(AddressLiteral src) {
2849 Assembler::fld_x(as_Address(src));
2850 }
2851
2852 void MacroAssembler::fldcw(AddressLiteral src) {
2853 Assembler::fldcw(as_Address(src));
2854 }
2855
2856 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
2857 if (reachable(src)) {
2858 Assembler::mulpd(dst, as_Address(src));
2859 } else {
2860 lea(rscratch1, src);
2861 Assembler::mulpd(dst, Address(rscratch1, 0));
2862 }
2863 }
2864
2865 void MacroAssembler::increase_precision() {
2866 subptr(rsp, BytesPerWord);
2867 fnstcw(Address(rsp, 0));
2868 movl(rax, Address(rsp, 0));
2869 orl(rax, 0x300);
2870 push(rax);
2871 fldcw(Address(rsp, 0));
2872 pop(rax);
2873 }
2874
2875 void MacroAssembler::restore_precision() {
2876 fldcw(Address(rsp, 0));
2877 addptr(rsp, BytesPerWord);
2878 }
2879
2880 void MacroAssembler::fpop() {
2881 ffree();
2882 fincstp();
2883 }
2884
2885 void MacroAssembler::load_float(Address src) {
2886 if (UseSSE >= 1) {
2887 movflt(xmm0, src);
2888 } else {
2889 LP64_ONLY(ShouldNotReachHere());
2890 NOT_LP64(fld_s(src));
2891 }
2892 }
2893
2894 void MacroAssembler::store_float(Address dst) {
2895 if (UseSSE >= 1) {
2896 movflt(dst, xmm0);
2897 } else {
2898 LP64_ONLY(ShouldNotReachHere());
2899 NOT_LP64(fstp_s(dst));
2900 }
2901 }
2902
2903 void MacroAssembler::load_double(Address src) {
2904 if (UseSSE >= 2) {
2905 movdbl(xmm0, src);
2906 } else {
2907 LP64_ONLY(ShouldNotReachHere());
2908 NOT_LP64(fld_d(src));
2909 }
2910 }
2911
2912 void MacroAssembler::store_double(Address dst) {
2913 if (UseSSE >= 2) {
2914 movdbl(dst, xmm0);
2915 } else {
2916 LP64_ONLY(ShouldNotReachHere());
2917 NOT_LP64(fstp_d(dst));
2918 }
2919 }
2920
2921 void MacroAssembler::fremr(Register tmp) {
2922 save_rax(tmp);
2923 { Label L;
2924 bind(L);
2925 fprem();
2926 fwait(); fnstsw_ax();
2927 #ifdef _LP64
2928 testl(rax, 0x400);
2929 jcc(Assembler::notEqual, L);
2930 #else
2931 sahf();
2932 jcc(Assembler::parity, L);
2933 #endif // _LP64
2934 }
2935 restore_rax(tmp);
2936 // Result is in ST0.
2937 // Note: fxch & fpop to get rid of ST1
2938 // (otherwise FPU stack could overflow eventually)
2939 fxch(1);
2940 fpop();
2941 }
2942
2943 // dst = c = a * b + c
2944 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2945 Assembler::vfmadd231sd(c, a, b);
2946 if (dst != c) {
2947 movdbl(dst, c);
2948 }
2949 }
2950
2951 // dst = c = a * b + c
2952 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2953 Assembler::vfmadd231ss(c, a, b);
2954 if (dst != c) {
2955 movflt(dst, c);
2956 }
2957 }
2958
2959 // dst = c = a * b + c
2960 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2961 Assembler::vfmadd231pd(c, a, b, vector_len);
2962 if (dst != c) {
2963 vmovdqu(dst, c);
2964 }
2965 }
2966
2967 // dst = c = a * b + c
2968 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2969 Assembler::vfmadd231ps(c, a, b, vector_len);
2970 if (dst != c) {
2971 vmovdqu(dst, c);
2972 }
2973 }
2974
2975 // dst = c = a * b + c
2976 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2977 Assembler::vfmadd231pd(c, a, b, vector_len);
2978 if (dst != c) {
2979 vmovdqu(dst, c);
2980 }
2981 }
2982
2983 // dst = c = a * b + c
2984 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2985 Assembler::vfmadd231ps(c, a, b, vector_len);
2986 if (dst != c) {
2987 vmovdqu(dst, c);
2988 }
2989 }
2990
2991 void MacroAssembler::incrementl(AddressLiteral dst) {
2992 if (reachable(dst)) {
2993 incrementl(as_Address(dst));
2994 } else {
2995 lea(rscratch1, dst);
2996 incrementl(Address(rscratch1, 0));
2997 }
2998 }
2999
3000 void MacroAssembler::incrementl(ArrayAddress dst) {
3001 incrementl(as_Address(dst));
3002 }
3003
3004 void MacroAssembler::incrementl(Register reg, int value) {
3005 if (value == min_jint) {addl(reg, value) ; return; }
3006 if (value < 0) { decrementl(reg, -value); return; }
3007 if (value == 0) { ; return; }
3008 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3009 /* else */ { addl(reg, value) ; return; }
3010 }
3011
3012 void MacroAssembler::incrementl(Address dst, int value) {
3013 if (value == min_jint) {addl(dst, value) ; return; }
3014 if (value < 0) { decrementl(dst, -value); return; }
3015 if (value == 0) { ; return; }
3016 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3017 /* else */ { addl(dst, value) ; return; }
3018 }
3019
3020 void MacroAssembler::jump(AddressLiteral dst) {
3021 if (reachable(dst)) {
3022 jmp_literal(dst.target(), dst.rspec());
3023 } else {
3024 lea(rscratch1, dst);
3025 jmp(rscratch1);
3026 }
3027 }
3028
3029 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3030 if (reachable(dst)) {
3031 InstructionMark im(this);
3032 relocate(dst.reloc());
3033 const int short_size = 2;
3034 const int long_size = 6;
3035 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3036 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3037 // 0111 tttn #8-bit disp
3038 emit_int8(0x70 | cc);
3039 emit_int8((offs - short_size) & 0xFF);
3040 } else {
3041 // 0000 1111 1000 tttn #32-bit disp
3042 emit_int8(0x0F);
3043 emit_int8((unsigned char)(0x80 | cc));
3044 emit_int32(offs - long_size);
3045 }
3046 } else {
3047 #ifdef ASSERT
3048 warning("reversing conditional branch");
3049 #endif /* ASSERT */
3050 Label skip;
3051 jccb(reverse[cc], skip);
3052 lea(rscratch1, dst);
3053 Assembler::jmp(rscratch1);
3054 bind(skip);
3055 }
3056 }
3057
3058 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3059 if (reachable(src)) {
3060 Assembler::ldmxcsr(as_Address(src));
3061 } else {
3062 lea(rscratch1, src);
3063 Assembler::ldmxcsr(Address(rscratch1, 0));
3064 }
3065 }
3066
3067 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3068 int off;
3069 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3070 off = offset();
3071 movsbl(dst, src); // movsxb
3072 } else {
3073 off = load_unsigned_byte(dst, src);
3074 shll(dst, 24);
3075 sarl(dst, 24);
3076 }
3077 return off;
3078 }
3079
3080 // Note: load_signed_short used to be called load_signed_word.
3081 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3082 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3083 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3084 int MacroAssembler::load_signed_short(Register dst, Address src) {
3085 int off;
3086 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3087 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3088 // version but this is what 64bit has always done. This seems to imply
3089 // that users are only using 32bits worth.
3090 off = offset();
3091 movswl(dst, src); // movsxw
3092 } else {
3093 off = load_unsigned_short(dst, src);
3094 shll(dst, 16);
3095 sarl(dst, 16);
3096 }
3097 return off;
3098 }
3099
3100 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3101 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3102 // and "3.9 Partial Register Penalties", p. 22).
3103 int off;
3104 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3105 off = offset();
3106 movzbl(dst, src); // movzxb
3107 } else {
3108 xorl(dst, dst);
3109 off = offset();
3110 movb(dst, src);
3111 }
3112 return off;
3113 }
3114
3115 // Note: load_unsigned_short used to be called load_unsigned_word.
3116 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3117 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3118 // and "3.9 Partial Register Penalties", p. 22).
3119 int off;
3120 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3121 off = offset();
3122 movzwl(dst, src); // movzxw
3123 } else {
3124 xorl(dst, dst);
3125 off = offset();
3126 movw(dst, src);
3127 }
3128 return off;
3129 }
3130
3131 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3132 switch (size_in_bytes) {
3133 #ifndef _LP64
3134 case 8:
3135 assert(dst2 != noreg, "second dest register required");
3136 movl(dst, src);
3137 movl(dst2, src.plus_disp(BytesPerInt));
3138 break;
3139 #else
3140 case 8: movq(dst, src); break;
3141 #endif
3142 case 4: movl(dst, src); break;
3143 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3144 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3145 default: ShouldNotReachHere();
3146 }
3147 }
3148
3149 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3150 switch (size_in_bytes) {
3151 #ifndef _LP64
3152 case 8:
3153 assert(src2 != noreg, "second source register required");
3154 movl(dst, src);
3155 movl(dst.plus_disp(BytesPerInt), src2);
3156 break;
3157 #else
3158 case 8: movq(dst, src); break;
3159 #endif
3160 case 4: movl(dst, src); break;
3161 case 2: movw(dst, src); break;
3162 case 1: movb(dst, src); break;
3163 default: ShouldNotReachHere();
3164 }
3165 }
3166
3167 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3168 if (reachable(dst)) {
3169 movl(as_Address(dst), src);
3170 } else {
3171 lea(rscratch1, dst);
3172 movl(Address(rscratch1, 0), src);
3173 }
3174 }
3175
3176 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3177 if (reachable(src)) {
3178 movl(dst, as_Address(src));
3179 } else {
3180 lea(rscratch1, src);
3181 movl(dst, Address(rscratch1, 0));
3182 }
3183 }
3184
3185 // C++ bool manipulation
3186
3187 void MacroAssembler::movbool(Register dst, Address src) {
3188 if(sizeof(bool) == 1)
3189 movb(dst, src);
3190 else if(sizeof(bool) == 2)
3191 movw(dst, src);
3192 else if(sizeof(bool) == 4)
3193 movl(dst, src);
3194 else
3195 // unsupported
3196 ShouldNotReachHere();
3197 }
3198
3199 void MacroAssembler::movbool(Address dst, bool boolconst) {
3200 if(sizeof(bool) == 1)
3201 movb(dst, (int) boolconst);
3202 else if(sizeof(bool) == 2)
3203 movw(dst, (int) boolconst);
3204 else if(sizeof(bool) == 4)
3205 movl(dst, (int) boolconst);
3206 else
3207 // unsupported
3208 ShouldNotReachHere();
3209 }
3210
3211 void MacroAssembler::movbool(Address dst, Register src) {
3212 if(sizeof(bool) == 1)
3213 movb(dst, src);
3214 else if(sizeof(bool) == 2)
3215 movw(dst, src);
3216 else if(sizeof(bool) == 4)
3217 movl(dst, src);
3218 else
3219 // unsupported
3220 ShouldNotReachHere();
3221 }
3222
3223 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3224 movb(as_Address(dst), src);
3225 }
3226
3227 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3228 if (reachable(src)) {
3229 movdl(dst, as_Address(src));
3230 } else {
3231 lea(rscratch1, src);
3232 movdl(dst, Address(rscratch1, 0));
3233 }
3234 }
3235
3236 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3237 if (reachable(src)) {
3238 movq(dst, as_Address(src));
3239 } else {
3240 lea(rscratch1, src);
3241 movq(dst, Address(rscratch1, 0));
3242 }
3243 }
3244
3245 #ifdef COMPILER2
3246 void MacroAssembler::setvectmask(Register dst, Register src) {
3247 guarantee(PostLoopMultiversioning, "must be");
3248 Assembler::movl(dst, 1);
3249 Assembler::shlxl(dst, dst, src);
3250 Assembler::decl(dst);
3251 Assembler::kmovdl(k1, dst);
3252 Assembler::movl(dst, src);
3253 }
3254
3255 void MacroAssembler::restorevectmask() {
3256 guarantee(PostLoopMultiversioning, "must be");
3257 Assembler::knotwl(k1, k0);
3258 }
3259 #endif // COMPILER2
3260
3261 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3262 if (reachable(src)) {
3263 if (UseXmmLoadAndClearUpper) {
3264 movsd (dst, as_Address(src));
3265 } else {
3266 movlpd(dst, as_Address(src));
3267 }
3268 } else {
3269 lea(rscratch1, src);
3270 if (UseXmmLoadAndClearUpper) {
3271 movsd (dst, Address(rscratch1, 0));
3272 } else {
3273 movlpd(dst, Address(rscratch1, 0));
3274 }
3275 }
3276 }
3277
3278 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3279 if (reachable(src)) {
3280 movss(dst, as_Address(src));
3281 } else {
3282 lea(rscratch1, src);
3283 movss(dst, Address(rscratch1, 0));
3284 }
3285 }
3286
3287 void MacroAssembler::movptr(Register dst, Register src) {
3288 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3289 }
3290
3291 void MacroAssembler::movptr(Register dst, Address src) {
3292 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3293 }
3294
3295 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3296 void MacroAssembler::movptr(Register dst, intptr_t src) {
3297 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3298 }
3299
3300 void MacroAssembler::movptr(Address dst, Register src) {
3301 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3302 }
3303
3304 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3305 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3306 Assembler::movdqu(dst, src);
3307 }
3308
3309 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3310 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3311 Assembler::movdqu(dst, src);
3312 }
3313
3314 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3315 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3316 Assembler::movdqu(dst, src);
3317 }
3318
3319 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3320 if (reachable(src)) {
3321 movdqu(dst, as_Address(src));
3322 } else {
3323 lea(scratchReg, src);
3324 movdqu(dst, Address(scratchReg, 0));
3325 }
3326 }
3327
3328 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3329 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3330 Assembler::vmovdqu(dst, src);
3331 }
3332
3333 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3334 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3335 Assembler::vmovdqu(dst, src);
3336 }
3337
3338 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3339 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3340 Assembler::vmovdqu(dst, src);
3341 }
3342
3343 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3344 if (reachable(src)) {
3345 vmovdqu(dst, as_Address(src));
3346 }
3347 else {
3348 lea(scratch_reg, src);
3349 vmovdqu(dst, Address(scratch_reg, 0));
3350 }
3351 }
3352
3353 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3354 if (reachable(src)) {
3355 Assembler::evmovdquq(dst, as_Address(src), vector_len);
3356 } else {
3357 lea(rscratch, src);
3358 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
3359 }
3360 }
3361
3362 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3363 if (reachable(src)) {
3364 Assembler::movdqa(dst, as_Address(src));
3365 } else {
3366 lea(rscratch1, src);
3367 Assembler::movdqa(dst, Address(rscratch1, 0));
3368 }
3369 }
3370
3371 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3372 if (reachable(src)) {
3373 Assembler::movsd(dst, as_Address(src));
3374 } else {
3375 lea(rscratch1, src);
3376 Assembler::movsd(dst, Address(rscratch1, 0));
3377 }
3378 }
3379
3380 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3381 if (reachable(src)) {
3382 Assembler::movss(dst, as_Address(src));
3383 } else {
3384 lea(rscratch1, src);
3385 Assembler::movss(dst, Address(rscratch1, 0));
3386 }
3387 }
3388
3389 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3390 if (reachable(src)) {
3391 Assembler::mulsd(dst, as_Address(src));
3392 } else {
3393 lea(rscratch1, src);
3394 Assembler::mulsd(dst, Address(rscratch1, 0));
3395 }
3396 }
3397
3398 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3399 if (reachable(src)) {
3400 Assembler::mulss(dst, as_Address(src));
3401 } else {
3402 lea(rscratch1, src);
3403 Assembler::mulss(dst, Address(rscratch1, 0));
3404 }
3405 }
3406
3407 void MacroAssembler::null_check(Register reg, int offset) {
3408 if (needs_explicit_null_check(offset)) {
3409 // provoke OS NULL exception if reg = NULL by
3410 // accessing M[reg] w/o changing any (non-CC) registers
3411 // NOTE: cmpl is plenty here to provoke a segv
3412 cmpptr(rax, Address(reg, 0));
3413 // Note: should probably use testl(rax, Address(reg, 0));
3414 // may be shorter code (however, this version of
3415 // testl needs to be implemented first)
3416 } else {
3417 // nothing to do, (later) access of M[reg + offset]
3418 // will provoke OS NULL exception if reg = NULL
3419 }
3420 }
3421
3422 void MacroAssembler::os_breakpoint() {
3423 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3424 // (e.g., MSVC can't call ps() otherwise)
3425 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3426 }
3427
3428 void MacroAssembler::unimplemented(const char* what) {
3429 const char* buf = NULL;
3430 {
3431 ResourceMark rm;
3432 stringStream ss;
3433 ss.print("unimplemented: %s", what);
3434 buf = code_string(ss.as_string());
3435 }
3436 stop(buf);
3437 }
3438
3439 #ifdef _LP64
3440 #define XSTATE_BV 0x200
3441 #endif
3442
3443 void MacroAssembler::pop_CPU_state() {
3444 pop_FPU_state();
3445 pop_IU_state();
3446 }
3447
3448 void MacroAssembler::pop_FPU_state() {
3449 #ifndef _LP64
3450 frstor(Address(rsp, 0));
3451 #else
3452 fxrstor(Address(rsp, 0));
3453 #endif
3454 addptr(rsp, FPUStateSizeInWords * wordSize);
3455 }
3456
3457 void MacroAssembler::pop_IU_state() {
3458 popa();
3459 LP64_ONLY(addq(rsp, 8));
3460 popf();
3461 }
3462
3463 // Save Integer and Float state
3464 // Warning: Stack must be 16 byte aligned (64bit)
3465 void MacroAssembler::push_CPU_state() {
3466 push_IU_state();
3467 push_FPU_state();
3468 }
3469
3470 void MacroAssembler::push_FPU_state() {
3471 subptr(rsp, FPUStateSizeInWords * wordSize);
3472 #ifndef _LP64
3473 fnsave(Address(rsp, 0));
3474 fwait();
3475 #else
3476 fxsave(Address(rsp, 0));
3477 #endif // LP64
3478 }
3479
3480 void MacroAssembler::push_IU_state() {
3481 // Push flags first because pusha kills them
3482 pushf();
3483 // Make sure rsp stays 16-byte aligned
3484 LP64_ONLY(subq(rsp, 8));
3485 pusha();
3486 }
3487
3488 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3489 if (!java_thread->is_valid()) {
3490 java_thread = rdi;
3491 get_thread(java_thread);
3492 }
3493 // we must set sp to zero to clear frame
3494 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3495 if (clear_fp) {
3496 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3497 }
3498
3499 // Always clear the pc because it could have been set by make_walkable()
3500 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3501
3502 vzeroupper();
3503 }
3504
3505 void MacroAssembler::restore_rax(Register tmp) {
3506 if (tmp == noreg) pop(rax);
3507 else if (tmp != rax) mov(rax, tmp);
3508 }
3509
3510 void MacroAssembler::round_to(Register reg, int modulus) {
3511 addptr(reg, modulus - 1);
3512 andptr(reg, -modulus);
3513 }
3514
3515 void MacroAssembler::save_rax(Register tmp) {
3516 if (tmp == noreg) push(rax);
3517 else if (tmp != rax) mov(tmp, rax);
3518 }
3519
3520 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
3521 if (SafepointMechanism::uses_thread_local_poll()) {
3522 #ifdef _LP64
3523 assert(thread_reg == r15_thread, "should be");
3524 #else
3525 if (thread_reg == noreg) {
3526 thread_reg = temp_reg;
3527 get_thread(thread_reg);
3528 }
3529 #endif
3530 testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
3531 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3532 } else {
3533 cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
3534 SafepointSynchronize::_not_synchronized);
3535 jcc(Assembler::notEqual, slow_path);
3536 }
3537 }
3538
3539 // Calls to C land
3540 //
3541 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3542 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3543 // has to be reset to 0. This is required to allow proper stack traversal.
3544 void MacroAssembler::set_last_Java_frame(Register java_thread,
3545 Register last_java_sp,
3546 Register last_java_fp,
3547 address last_java_pc) {
3548 vzeroupper();
3549 // determine java_thread register
3550 if (!java_thread->is_valid()) {
3551 java_thread = rdi;
3552 get_thread(java_thread);
3553 }
3554 // determine last_java_sp register
3555 if (!last_java_sp->is_valid()) {
3556 last_java_sp = rsp;
3557 }
3558
3559 // last_java_fp is optional
3560
3561 if (last_java_fp->is_valid()) {
3562 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3563 }
3564
3565 // last_java_pc is optional
3566
3567 if (last_java_pc != NULL) {
3568 lea(Address(java_thread,
3569 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3570 InternalAddress(last_java_pc));
3571
3572 }
3573 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3574 }
3575
3576 void MacroAssembler::shlptr(Register dst, int imm8) {
3577 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3578 }
3579
3580 void MacroAssembler::shrptr(Register dst, int imm8) {
3581 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3582 }
3583
3584 void MacroAssembler::sign_extend_byte(Register reg) {
3585 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3586 movsbl(reg, reg); // movsxb
3587 } else {
3588 shll(reg, 24);
3589 sarl(reg, 24);
3590 }
3591 }
3592
3593 void MacroAssembler::sign_extend_short(Register reg) {
3594 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3595 movswl(reg, reg); // movsxw
3596 } else {
3597 shll(reg, 16);
3598 sarl(reg, 16);
3599 }
3600 }
3601
3602 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3603 assert(reachable(src), "Address should be reachable");
3604 testl(dst, as_Address(src));
3605 }
3606
3607 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3608 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3609 Assembler::pcmpeqb(dst, src);
3610 }
3611
3612 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3613 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3614 Assembler::pcmpeqw(dst, src);
3615 }
3616
3617 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3618 assert((dst->encoding() < 16),"XMM register should be 0-15");
3619 Assembler::pcmpestri(dst, src, imm8);
3620 }
3621
3622 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3623 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3624 Assembler::pcmpestri(dst, src, imm8);
3625 }
3626
3627 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3628 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3629 Assembler::pmovzxbw(dst, src);
3630 }
3631
3632 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3633 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3634 Assembler::pmovzxbw(dst, src);
3635 }
3636
3637 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3638 assert((src->encoding() < 16),"XMM register should be 0-15");
3639 Assembler::pmovmskb(dst, src);
3640 }
3641
3642 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3643 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3644 Assembler::ptest(dst, src);
3645 }
3646
3647 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3648 if (reachable(src)) {
3649 Assembler::sqrtsd(dst, as_Address(src));
3650 } else {
3651 lea(rscratch1, src);
3652 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3653 }
3654 }
3655
3656 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3657 if (reachable(src)) {
3658 Assembler::sqrtss(dst, as_Address(src));
3659 } else {
3660 lea(rscratch1, src);
3661 Assembler::sqrtss(dst, Address(rscratch1, 0));
3662 }
3663 }
3664
3665 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3666 if (reachable(src)) {
3667 Assembler::subsd(dst, as_Address(src));
3668 } else {
3669 lea(rscratch1, src);
3670 Assembler::subsd(dst, Address(rscratch1, 0));
3671 }
3672 }
3673
3674 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3675 if (reachable(src)) {
3676 Assembler::subss(dst, as_Address(src));
3677 } else {
3678 lea(rscratch1, src);
3679 Assembler::subss(dst, Address(rscratch1, 0));
3680 }
3681 }
3682
3683 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3684 if (reachable(src)) {
3685 Assembler::ucomisd(dst, as_Address(src));
3686 } else {
3687 lea(rscratch1, src);
3688 Assembler::ucomisd(dst, Address(rscratch1, 0));
3689 }
3690 }
3691
3692 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3693 if (reachable(src)) {
3694 Assembler::ucomiss(dst, as_Address(src));
3695 } else {
3696 lea(rscratch1, src);
3697 Assembler::ucomiss(dst, Address(rscratch1, 0));
3698 }
3699 }
3700
3701 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3702 // Used in sign-bit flipping with aligned address.
3703 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3704 if (reachable(src)) {
3705 Assembler::xorpd(dst, as_Address(src));
3706 } else {
3707 lea(scratch_reg, src);
3708 Assembler::xorpd(dst, Address(scratch_reg, 0));
3709 }
3710 }
3711
3712 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3713 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3714 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3715 }
3716 else {
3717 Assembler::xorpd(dst, src);
3718 }
3719 }
3720
3721 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3722 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3723 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3724 } else {
3725 Assembler::xorps(dst, src);
3726 }
3727 }
3728
3729 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3730 // Used in sign-bit flipping with aligned address.
3731 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3732 if (reachable(src)) {
3733 Assembler::xorps(dst, as_Address(src));
3734 } else {
3735 lea(scratch_reg, src);
3736 Assembler::xorps(dst, Address(scratch_reg, 0));
3737 }
3738 }
3739
3740 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3741 // Used in sign-bit flipping with aligned address.
3742 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3743 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3744 if (reachable(src)) {
3745 Assembler::pshufb(dst, as_Address(src));
3746 } else {
3747 lea(rscratch1, src);
3748 Assembler::pshufb(dst, Address(rscratch1, 0));
3749 }
3750 }
3751
3752 // AVX 3-operands instructions
3753
3754 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3755 if (reachable(src)) {
3756 vaddsd(dst, nds, as_Address(src));
3757 } else {
3758 lea(rscratch1, src);
3759 vaddsd(dst, nds, Address(rscratch1, 0));
3760 }
3761 }
3762
3763 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3764 if (reachable(src)) {
3765 vaddss(dst, nds, as_Address(src));
3766 } else {
3767 lea(rscratch1, src);
3768 vaddss(dst, nds, Address(rscratch1, 0));
3769 }
3770 }
3771
3772 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3773 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3774 vandps(dst, nds, negate_field, vector_len);
3775 }
3776
3777 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3778 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3779 vandpd(dst, nds, negate_field, vector_len);
3780 }
3781
3782 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3783 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3784 Assembler::vpaddb(dst, nds, src, vector_len);
3785 }
3786
3787 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3788 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3789 Assembler::vpaddb(dst, nds, src, vector_len);
3790 }
3791
3792 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3793 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3794 Assembler::vpaddw(dst, nds, src, vector_len);
3795 }
3796
3797 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3798 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3799 Assembler::vpaddw(dst, nds, src, vector_len);
3800 }
3801
3802 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3803 if (reachable(src)) {
3804 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3805 } else {
3806 lea(scratch_reg, src);
3807 Assembler::vpand(dst, nds, Address(scratch_reg, 0), vector_len);
3808 }
3809 }
3810
3811 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
3812 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3813 Assembler::vpbroadcastw(dst, src, vector_len);
3814 }
3815
3816 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3817 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3818 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3819 }
3820
3821 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3822 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3823 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3824 }
3825
3826 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3827 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3828 Assembler::vpmovzxbw(dst, src, vector_len);
3829 }
3830
3831 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
3832 assert((src->encoding() < 16),"XMM register should be 0-15");
3833 Assembler::vpmovmskb(dst, src);
3834 }
3835
3836 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3837 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3838 Assembler::vpmullw(dst, nds, src, vector_len);
3839 }
3840
3841 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3842 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3843 Assembler::vpmullw(dst, nds, src, vector_len);
3844 }
3845
3846 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3847 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3848 Assembler::vpsubb(dst, nds, src, vector_len);
3849 }
3850
3851 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3852 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3853 Assembler::vpsubb(dst, nds, src, vector_len);
3854 }
3855
3856 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3857 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3858 Assembler::vpsubw(dst, nds, src, vector_len);
3859 }
3860
3861 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3862 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3863 Assembler::vpsubw(dst, nds, src, vector_len);
3864 }
3865
3866 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3867 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3868 Assembler::vpsraw(dst, nds, shift, vector_len);
3869 }
3870
3871 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3872 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3873 Assembler::vpsraw(dst, nds, shift, vector_len);
3874 }
3875
3876 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3877 assert(UseAVX > 2,"");
3878 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3879 vector_len = 2;
3880 }
3881 Assembler::evpsraq(dst, nds, shift, vector_len);
3882 }
3883
3884 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3885 assert(UseAVX > 2,"");
3886 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3887 vector_len = 2;
3888 }
3889 Assembler::evpsraq(dst, nds, shift, vector_len);
3890 }
3891
3892 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3893 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3894 Assembler::vpsrlw(dst, nds, shift, vector_len);
3895 }
3896
3897 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3898 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3899 Assembler::vpsrlw(dst, nds, shift, vector_len);
3900 }
3901
3902 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3903 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3904 Assembler::vpsllw(dst, nds, shift, vector_len);
3905 }
3906
3907 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3908 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3909 Assembler::vpsllw(dst, nds, shift, vector_len);
3910 }
3911
3912 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3913 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3914 Assembler::vptest(dst, src);
3915 }
3916
3917 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3918 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3919 Assembler::punpcklbw(dst, src);
3920 }
3921
3922 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3923 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3924 Assembler::pshufd(dst, src, mode);
3925 }
3926
3927 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3928 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3929 Assembler::pshuflw(dst, src, mode);
3930 }
3931
3932 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3933 if (reachable(src)) {
3934 vandpd(dst, nds, as_Address(src), vector_len);
3935 } else {
3936 lea(scratch_reg, src);
3937 vandpd(dst, nds, Address(scratch_reg, 0), vector_len);
3938 }
3939 }
3940
3941 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3942 if (reachable(src)) {
3943 vandps(dst, nds, as_Address(src), vector_len);
3944 } else {
3945 lea(scratch_reg, src);
3946 vandps(dst, nds, Address(scratch_reg, 0), vector_len);
3947 }
3948 }
3949
3950 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3951 if (reachable(src)) {
3952 vdivsd(dst, nds, as_Address(src));
3953 } else {
3954 lea(rscratch1, src);
3955 vdivsd(dst, nds, Address(rscratch1, 0));
3956 }
3957 }
3958
3959 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3960 if (reachable(src)) {
3961 vdivss(dst, nds, as_Address(src));
3962 } else {
3963 lea(rscratch1, src);
3964 vdivss(dst, nds, Address(rscratch1, 0));
3965 }
3966 }
3967
3968 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3969 if (reachable(src)) {
3970 vmulsd(dst, nds, as_Address(src));
3971 } else {
3972 lea(rscratch1, src);
3973 vmulsd(dst, nds, Address(rscratch1, 0));
3974 }
3975 }
3976
3977 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3978 if (reachable(src)) {
3979 vmulss(dst, nds, as_Address(src));
3980 } else {
3981 lea(rscratch1, src);
3982 vmulss(dst, nds, Address(rscratch1, 0));
3983 }
3984 }
3985
3986 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3987 if (reachable(src)) {
3988 vsubsd(dst, nds, as_Address(src));
3989 } else {
3990 lea(rscratch1, src);
3991 vsubsd(dst, nds, Address(rscratch1, 0));
3992 }
3993 }
3994
3995 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3996 if (reachable(src)) {
3997 vsubss(dst, nds, as_Address(src));
3998 } else {
3999 lea(rscratch1, src);
4000 vsubss(dst, nds, Address(rscratch1, 0));
4001 }
4002 }
4003
4004 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4005 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4006 vxorps(dst, nds, src, Assembler::AVX_128bit);
4007 }
4008
4009 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4010 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4011 vxorpd(dst, nds, src, Assembler::AVX_128bit);
4012 }
4013
4014 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4015 if (reachable(src)) {
4016 vxorpd(dst, nds, as_Address(src), vector_len);
4017 } else {
4018 lea(scratch_reg, src);
4019 vxorpd(dst, nds, Address(scratch_reg, 0), vector_len);
4020 }
4021 }
4022
4023 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4024 if (reachable(src)) {
4025 vxorps(dst, nds, as_Address(src), vector_len);
4026 } else {
4027 lea(scratch_reg, src);
4028 vxorps(dst, nds, Address(scratch_reg, 0), vector_len);
4029 }
4030 }
4031
4032 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4033 if (UseAVX > 1 || (vector_len < 1)) {
4034 if (reachable(src)) {
4035 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
4036 } else {
4037 lea(scratch_reg, src);
4038 Assembler::vpxor(dst, nds, Address(scratch_reg, 0), vector_len);
4039 }
4040 }
4041 else {
4042 MacroAssembler::vxorpd(dst, nds, src, vector_len, scratch_reg);
4043 }
4044 }
4045
4046 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
4047 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
4048 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
4049 // The inverted mask is sign-extended
4050 andptr(possibly_jweak, inverted_jweak_mask);
4051 }
4052
4053 void MacroAssembler::resolve_jobject(Register value,
4054 Register thread,
4055 Register tmp) {
4056 assert_different_registers(value, thread, tmp);
4057 Label done, not_weak;
4058 testptr(value, value);
4059 jcc(Assembler::zero, done); // Use NULL as-is.
4060 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
4061 jcc(Assembler::zero, not_weak);
4062 // Resolve jweak.
4063 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4064 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
4065 verify_oop(value);
4066 jmp(done);
4067 bind(not_weak);
4068 // Resolve (untagged) jobject.
4069 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
4070 verify_oop(value);
4071 bind(done);
4072 }
4073
4074 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4075 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4076 }
4077
4078 // Force generation of a 4 byte immediate value even if it fits into 8bit
4079 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4080 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4081 }
4082
4083 void MacroAssembler::subptr(Register dst, Register src) {
4084 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4085 }
4086
4087 // C++ bool manipulation
4088 void MacroAssembler::testbool(Register dst) {
4089 if(sizeof(bool) == 1)
4090 testb(dst, 0xff);
4091 else if(sizeof(bool) == 2) {
4092 // testw implementation needed for two byte bools
4093 ShouldNotReachHere();
4094 } else if(sizeof(bool) == 4)
4095 testl(dst, dst);
4096 else
4097 // unsupported
4098 ShouldNotReachHere();
4099 }
4100
4101 void MacroAssembler::testptr(Register dst, Register src) {
4102 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4103 }
4104
4105 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4106 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4107 Register var_size_in_bytes,
4108 int con_size_in_bytes,
4109 Register t1,
4110 Register t2,
4111 Label& slow_case) {
4112 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4113 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4114 }
4115
4116 // Defines obj, preserves var_size_in_bytes
4117 void MacroAssembler::eden_allocate(Register thread, Register obj,
4118 Register var_size_in_bytes,
4119 int con_size_in_bytes,
4120 Register t1,
4121 Label& slow_case) {
4122 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4123 bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
4124 }
4125
4126 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4127 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4128 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4129 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4130 Label done;
4131
4132 testptr(length_in_bytes, length_in_bytes);
4133 jcc(Assembler::zero, done);
4134
4135 // initialize topmost word, divide index by 2, check if odd and test if zero
4136 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4137 #ifdef ASSERT
4138 {
4139 Label L;
4140 testptr(length_in_bytes, BytesPerWord - 1);
4141 jcc(Assembler::zero, L);
4142 stop("length must be a multiple of BytesPerWord");
4143 bind(L);
4144 }
4145 #endif
4146 Register index = length_in_bytes;
4147 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4148 if (UseIncDec) {
4149 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4150 } else {
4151 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4152 shrptr(index, 1);
4153 }
4154 #ifndef _LP64
4155 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4156 {
4157 Label even;
4158 // note: if index was a multiple of 8, then it cannot
4159 // be 0 now otherwise it must have been 0 before
4160 // => if it is even, we don't need to check for 0 again
4161 jcc(Assembler::carryClear, even);
4162 // clear topmost word (no jump would be needed if conditional assignment worked here)
4163 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4164 // index could be 0 now, must check again
4165 jcc(Assembler::zero, done);
4166 bind(even);
4167 }
4168 #endif // !_LP64
4169 // initialize remaining object fields: index is a multiple of 2 now
4170 {
4171 Label loop;
4172 bind(loop);
4173 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4174 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4175 decrement(index);
4176 jcc(Assembler::notZero, loop);
4177 }
4178
4179 bind(done);
4180 }
4181
4182 // Look up the method for a megamorphic invokeinterface call.
4183 // The target method is determined by <intf_klass, itable_index>.
4184 // The receiver klass is in recv_klass.
4185 // On success, the result will be in method_result, and execution falls through.
4186 // On failure, execution transfers to the given label.
4187 void MacroAssembler::lookup_interface_method(Register recv_klass,
4188 Register intf_klass,
4189 RegisterOrConstant itable_index,
4190 Register method_result,
4191 Register scan_temp,
4192 Label& L_no_such_interface,
4193 bool return_method) {
4194 assert_different_registers(recv_klass, intf_klass, scan_temp);
4195 assert_different_registers(method_result, intf_klass, scan_temp);
4196 assert(recv_klass != method_result || !return_method,
4197 "recv_klass can be destroyed when method isn't needed");
4198
4199 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4200 "caller must use same register for non-constant itable index as for method");
4201
4202 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4203 int vtable_base = in_bytes(Klass::vtable_start_offset());
4204 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4205 int scan_step = itableOffsetEntry::size() * wordSize;
4206 int vte_size = vtableEntry::size_in_bytes();
4207 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4208 assert(vte_size == wordSize, "else adjust times_vte_scale");
4209
4210 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4211
4212 // %%% Could store the aligned, prescaled offset in the klassoop.
4213 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4214
4215 if (return_method) {
4216 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4217 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4218 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4219 }
4220
4221 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4222 // if (scan->interface() == intf) {
4223 // result = (klass + scan->offset() + itable_index);
4224 // }
4225 // }
4226 Label search, found_method;
4227
4228 for (int peel = 1; peel >= 0; peel--) {
4229 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4230 cmpptr(intf_klass, method_result);
4231
4232 if (peel) {
4233 jccb(Assembler::equal, found_method);
4234 } else {
4235 jccb(Assembler::notEqual, search);
4236 // (invert the test to fall through to found_method...)
4237 }
4238
4239 if (!peel) break;
4240
4241 bind(search);
4242
4243 // Check that the previous entry is non-null. A null entry means that
4244 // the receiver class doesn't implement the interface, and wasn't the
4245 // same as when the caller was compiled.
4246 testptr(method_result, method_result);
4247 jcc(Assembler::zero, L_no_such_interface);
4248 addptr(scan_temp, scan_step);
4249 }
4250
4251 bind(found_method);
4252
4253 if (return_method) {
4254 // Got a hit.
4255 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4256 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4257 }
4258 }
4259
4260
4261 // virtual method calling
4262 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4263 RegisterOrConstant vtable_index,
4264 Register method_result) {
4265 const int base = in_bytes(Klass::vtable_start_offset());
4266 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4267 Address vtable_entry_addr(recv_klass,
4268 vtable_index, Address::times_ptr,
4269 base + vtableEntry::method_offset_in_bytes());
4270 movptr(method_result, vtable_entry_addr);
4271 }
4272
4273
4274 void MacroAssembler::check_klass_subtype(Register sub_klass,
4275 Register super_klass,
4276 Register temp_reg,
4277 Label& L_success) {
4278 Label L_failure;
4279 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
4280 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4281 bind(L_failure);
4282 }
4283
4284
4285 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4286 Register super_klass,
4287 Register temp_reg,
4288 Label* L_success,
4289 Label* L_failure,
4290 Label* L_slow_path,
4291 RegisterOrConstant super_check_offset) {
4292 assert_different_registers(sub_klass, super_klass, temp_reg);
4293 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4294 if (super_check_offset.is_register()) {
4295 assert_different_registers(sub_klass, super_klass,
4296 super_check_offset.as_register());
4297 } else if (must_load_sco) {
4298 assert(temp_reg != noreg, "supply either a temp or a register offset");
4299 }
4300
4301 Label L_fallthrough;
4302 int label_nulls = 0;
4303 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4304 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4305 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4306 assert(label_nulls <= 1, "at most one NULL in the batch");
4307
4308 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4309 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4310 Address super_check_offset_addr(super_klass, sco_offset);
4311
4312 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4313 // range of a jccb. If this routine grows larger, reconsider at
4314 // least some of these.
4315 #define local_jcc(assembler_cond, label) \
4316 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4317 else jcc( assembler_cond, label) /*omit semi*/
4318
4319 // Hacked jmp, which may only be used just before L_fallthrough.
4320 #define final_jmp(label) \
4321 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4322 else jmp(label) /*omit semi*/
4323
4324 // If the pointers are equal, we are done (e.g., String[] elements).
4325 // This self-check enables sharing of secondary supertype arrays among
4326 // non-primary types such as array-of-interface. Otherwise, each such
4327 // type would need its own customized SSA.
4328 // We move this check to the front of the fast path because many
4329 // type checks are in fact trivially successful in this manner,
4330 // so we get a nicely predicted branch right at the start of the check.
4331 cmpptr(sub_klass, super_klass);
4332 local_jcc(Assembler::equal, *L_success);
4333
4334 // Check the supertype display:
4335 if (must_load_sco) {
4336 // Positive movl does right thing on LP64.
4337 movl(temp_reg, super_check_offset_addr);
4338 super_check_offset = RegisterOrConstant(temp_reg);
4339 }
4340 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4341 cmpptr(super_klass, super_check_addr); // load displayed supertype
4342
4343 // This check has worked decisively for primary supers.
4344 // Secondary supers are sought in the super_cache ('super_cache_addr').
4345 // (Secondary supers are interfaces and very deeply nested subtypes.)
4346 // This works in the same check above because of a tricky aliasing
4347 // between the super_cache and the primary super display elements.
4348 // (The 'super_check_addr' can address either, as the case requires.)
4349 // Note that the cache is updated below if it does not help us find
4350 // what we need immediately.
4351 // So if it was a primary super, we can just fail immediately.
4352 // Otherwise, it's the slow path for us (no success at this point).
4353
4354 if (super_check_offset.is_register()) {
4355 local_jcc(Assembler::equal, *L_success);
4356 cmpl(super_check_offset.as_register(), sc_offset);
4357 if (L_failure == &L_fallthrough) {
4358 local_jcc(Assembler::equal, *L_slow_path);
4359 } else {
4360 local_jcc(Assembler::notEqual, *L_failure);
4361 final_jmp(*L_slow_path);
4362 }
4363 } else if (super_check_offset.as_constant() == sc_offset) {
4364 // Need a slow path; fast failure is impossible.
4365 if (L_slow_path == &L_fallthrough) {
4366 local_jcc(Assembler::equal, *L_success);
4367 } else {
4368 local_jcc(Assembler::notEqual, *L_slow_path);
4369 final_jmp(*L_success);
4370 }
4371 } else {
4372 // No slow path; it's a fast decision.
4373 if (L_failure == &L_fallthrough) {
4374 local_jcc(Assembler::equal, *L_success);
4375 } else {
4376 local_jcc(Assembler::notEqual, *L_failure);
4377 final_jmp(*L_success);
4378 }
4379 }
4380
4381 bind(L_fallthrough);
4382
4383 #undef local_jcc
4384 #undef final_jmp
4385 }
4386
4387
4388 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4389 Register super_klass,
4390 Register temp_reg,
4391 Register temp2_reg,
4392 Label* L_success,
4393 Label* L_failure,
4394 bool set_cond_codes) {
4395 assert_different_registers(sub_klass, super_klass, temp_reg);
4396 if (temp2_reg != noreg)
4397 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4398 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4399
4400 Label L_fallthrough;
4401 int label_nulls = 0;
4402 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4403 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4404 assert(label_nulls <= 1, "at most one NULL in the batch");
4405
4406 // a couple of useful fields in sub_klass:
4407 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4408 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4409 Address secondary_supers_addr(sub_klass, ss_offset);
4410 Address super_cache_addr( sub_klass, sc_offset);
4411
4412 // Do a linear scan of the secondary super-klass chain.
4413 // This code is rarely used, so simplicity is a virtue here.
4414 // The repne_scan instruction uses fixed registers, which we must spill.
4415 // Don't worry too much about pre-existing connections with the input regs.
4416
4417 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4418 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4419
4420 // Get super_klass value into rax (even if it was in rdi or rcx).
4421 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4422 if (super_klass != rax || UseCompressedOops) {
4423 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4424 mov(rax, super_klass);
4425 }
4426 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4427 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4428
4429 #ifndef PRODUCT
4430 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4431 ExternalAddress pst_counter_addr((address) pst_counter);
4432 NOT_LP64( incrementl(pst_counter_addr) );
4433 LP64_ONLY( lea(rcx, pst_counter_addr) );
4434 LP64_ONLY( incrementl(Address(rcx, 0)) );
4435 #endif //PRODUCT
4436
4437 // We will consult the secondary-super array.
4438 movptr(rdi, secondary_supers_addr);
4439 // Load the array length. (Positive movl does right thing on LP64.)
4440 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4441 // Skip to start of data.
4442 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4443
4444 // Scan RCX words at [RDI] for an occurrence of RAX.
4445 // Set NZ/Z based on last compare.
4446 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4447 // not change flags (only scas instruction which is repeated sets flags).
4448 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4449
4450 testptr(rax,rax); // Set Z = 0
4451 repne_scan();
4452
4453 // Unspill the temp. registers:
4454 if (pushed_rdi) pop(rdi);
4455 if (pushed_rcx) pop(rcx);
4456 if (pushed_rax) pop(rax);
4457
4458 if (set_cond_codes) {
4459 // Special hack for the AD files: rdi is guaranteed non-zero.
4460 assert(!pushed_rdi, "rdi must be left non-NULL");
4461 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4462 }
4463
4464 if (L_failure == &L_fallthrough)
4465 jccb(Assembler::notEqual, *L_failure);
4466 else jcc(Assembler::notEqual, *L_failure);
4467
4468 // Success. Cache the super we found and proceed in triumph.
4469 movptr(super_cache_addr, super_klass);
4470
4471 if (L_success != &L_fallthrough) {
4472 jmp(*L_success);
4473 }
4474
4475 #undef IS_A_TEMP
4476
4477 bind(L_fallthrough);
4478 }
4479
4480
4481 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4482 if (VM_Version::supports_cmov()) {
4483 cmovl(cc, dst, src);
4484 } else {
4485 Label L;
4486 jccb(negate_condition(cc), L);
4487 movl(dst, src);
4488 bind(L);
4489 }
4490 }
4491
4492 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4493 if (VM_Version::supports_cmov()) {
4494 cmovl(cc, dst, src);
4495 } else {
4496 Label L;
4497 jccb(negate_condition(cc), L);
4498 movl(dst, src);
4499 bind(L);
4500 }
4501 }
4502
4503 void MacroAssembler::verify_oop(Register reg, const char* s) {
4504 if (!VerifyOops) return;
4505
4506 // Pass register number to verify_oop_subroutine
4507 const char* b = NULL;
4508 {
4509 ResourceMark rm;
4510 stringStream ss;
4511 ss.print("verify_oop: %s: %s", reg->name(), s);
4512 b = code_string(ss.as_string());
4513 }
4514 BLOCK_COMMENT("verify_oop {");
4515 #ifdef _LP64
4516 push(rscratch1); // save r10, trashed by movptr()
4517 #endif
4518 push(rax); // save rax,
4519 push(reg); // pass register argument
4520 ExternalAddress buffer((address) b);
4521 // avoid using pushptr, as it modifies scratch registers
4522 // and our contract is not to modify anything
4523 movptr(rax, buffer.addr());
4524 push(rax);
4525 // call indirectly to solve generation ordering problem
4526 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4527 call(rax);
4528 // Caller pops the arguments (oop, message) and restores rax, r10
4529 BLOCK_COMMENT("} verify_oop");
4530 }
4531
4532
4533 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
4534 Register tmp,
4535 int offset) {
4536 intptr_t value = *delayed_value_addr;
4537 if (value != 0)
4538 return RegisterOrConstant(value + offset);
4539
4540 // load indirectly to solve generation ordering problem
4541 movptr(tmp, ExternalAddress((address) delayed_value_addr));
4542
4543 #ifdef ASSERT
4544 { Label L;
4545 testptr(tmp, tmp);
4546 if (WizardMode) {
4547 const char* buf = NULL;
4548 {
4549 ResourceMark rm;
4550 stringStream ss;
4551 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
4552 buf = code_string(ss.as_string());
4553 }
4554 jcc(Assembler::notZero, L);
4555 STOP(buf);
4556 } else {
4557 jccb(Assembler::notZero, L);
4558 hlt();
4559 }
4560 bind(L);
4561 }
4562 #endif
4563
4564 if (offset != 0)
4565 addptr(tmp, offset);
4566
4567 return RegisterOrConstant(tmp);
4568 }
4569
4570
4571 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4572 int extra_slot_offset) {
4573 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4574 int stackElementSize = Interpreter::stackElementSize;
4575 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4576 #ifdef ASSERT
4577 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4578 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4579 #endif
4580 Register scale_reg = noreg;
4581 Address::ScaleFactor scale_factor = Address::no_scale;
4582 if (arg_slot.is_constant()) {
4583 offset += arg_slot.as_constant() * stackElementSize;
4584 } else {
4585 scale_reg = arg_slot.as_register();
4586 scale_factor = Address::times(stackElementSize);
4587 }
4588 offset += wordSize; // return PC is on stack
4589 return Address(rsp, scale_reg, scale_factor, offset);
4590 }
4591
4592
4593 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
4594 if (!VerifyOops) return;
4595
4596 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4597 // Pass register number to verify_oop_subroutine
4598 const char* b = NULL;
4599 {
4600 ResourceMark rm;
4601 stringStream ss;
4602 ss.print("verify_oop_addr: %s", s);
4603 b = code_string(ss.as_string());
4604 }
4605 #ifdef _LP64
4606 push(rscratch1); // save r10, trashed by movptr()
4607 #endif
4608 push(rax); // save rax,
4609 // addr may contain rsp so we will have to adjust it based on the push
4610 // we just did (and on 64 bit we do two pushes)
4611 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4612 // stores rax into addr which is backwards of what was intended.
4613 if (addr.uses(rsp)) {
4614 lea(rax, addr);
4615 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4616 } else {
4617 pushptr(addr);
4618 }
4619
4620 ExternalAddress buffer((address) b);
4621 // pass msg argument
4622 // avoid using pushptr, as it modifies scratch registers
4623 // and our contract is not to modify anything
4624 movptr(rax, buffer.addr());
4625 push(rax);
4626
4627 // call indirectly to solve generation ordering problem
4628 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4629 call(rax);
4630 // Caller pops the arguments (addr, message) and restores rax, r10.
4631 }
4632
4633 void MacroAssembler::verify_tlab() {
4634 #ifdef ASSERT
4635 if (UseTLAB && VerifyOops) {
4636 Label next, ok;
4637 Register t1 = rsi;
4638 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4639
4640 push(t1);
4641 NOT_LP64(push(thread_reg));
4642 NOT_LP64(get_thread(thread_reg));
4643
4644 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4645 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4646 jcc(Assembler::aboveEqual, next);
4647 STOP("assert(top >= start)");
4648 should_not_reach_here();
4649
4650 bind(next);
4651 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4652 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4653 jcc(Assembler::aboveEqual, ok);
4654 STOP("assert(top <= end)");
4655 should_not_reach_here();
4656
4657 bind(ok);
4658 NOT_LP64(pop(thread_reg));
4659 pop(t1);
4660 }
4661 #endif
4662 }
4663
4664 class ControlWord {
4665 public:
4666 int32_t _value;
4667
4668 int rounding_control() const { return (_value >> 10) & 3 ; }
4669 int precision_control() const { return (_value >> 8) & 3 ; }
4670 bool precision() const { return ((_value >> 5) & 1) != 0; }
4671 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4672 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4673 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4674 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4675 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4676
4677 void print() const {
4678 // rounding control
4679 const char* rc;
4680 switch (rounding_control()) {
4681 case 0: rc = "round near"; break;
4682 case 1: rc = "round down"; break;
4683 case 2: rc = "round up "; break;
4684 case 3: rc = "chop "; break;
4685 };
4686 // precision control
4687 const char* pc;
4688 switch (precision_control()) {
4689 case 0: pc = "24 bits "; break;
4690 case 1: pc = "reserved"; break;
4691 case 2: pc = "53 bits "; break;
4692 case 3: pc = "64 bits "; break;
4693 };
4694 // flags
4695 char f[9];
4696 f[0] = ' ';
4697 f[1] = ' ';
4698 f[2] = (precision ()) ? 'P' : 'p';
4699 f[3] = (underflow ()) ? 'U' : 'u';
4700 f[4] = (overflow ()) ? 'O' : 'o';
4701 f[5] = (zero_divide ()) ? 'Z' : 'z';
4702 f[6] = (denormalized()) ? 'D' : 'd';
4703 f[7] = (invalid ()) ? 'I' : 'i';
4704 f[8] = '\x0';
4705 // output
4706 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4707 }
4708
4709 };
4710
4711 class StatusWord {
4712 public:
4713 int32_t _value;
4714
4715 bool busy() const { return ((_value >> 15) & 1) != 0; }
4716 bool C3() const { return ((_value >> 14) & 1) != 0; }
4717 bool C2() const { return ((_value >> 10) & 1) != 0; }
4718 bool C1() const { return ((_value >> 9) & 1) != 0; }
4719 bool C0() const { return ((_value >> 8) & 1) != 0; }
4720 int top() const { return (_value >> 11) & 7 ; }
4721 bool error_status() const { return ((_value >> 7) & 1) != 0; }
4722 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
4723 bool precision() const { return ((_value >> 5) & 1) != 0; }
4724 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4725 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4726 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4727 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4728 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4729
4730 void print() const {
4731 // condition codes
4732 char c[5];
4733 c[0] = (C3()) ? '3' : '-';
4734 c[1] = (C2()) ? '2' : '-';
4735 c[2] = (C1()) ? '1' : '-';
4736 c[3] = (C0()) ? '0' : '-';
4737 c[4] = '\x0';
4738 // flags
4739 char f[9];
4740 f[0] = (error_status()) ? 'E' : '-';
4741 f[1] = (stack_fault ()) ? 'S' : '-';
4742 f[2] = (precision ()) ? 'P' : '-';
4743 f[3] = (underflow ()) ? 'U' : '-';
4744 f[4] = (overflow ()) ? 'O' : '-';
4745 f[5] = (zero_divide ()) ? 'Z' : '-';
4746 f[6] = (denormalized()) ? 'D' : '-';
4747 f[7] = (invalid ()) ? 'I' : '-';
4748 f[8] = '\x0';
4749 // output
4750 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
4751 }
4752
4753 };
4754
4755 class TagWord {
4756 public:
4757 int32_t _value;
4758
4759 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
4760
4761 void print() const {
4762 printf("%04x", _value & 0xFFFF);
4763 }
4764
4765 };
4766
4767 class FPU_Register {
4768 public:
4769 int32_t _m0;
4770 int32_t _m1;
4771 int16_t _ex;
4772
4773 bool is_indefinite() const {
4774 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4775 }
4776
4777 void print() const {
4778 char sign = (_ex < 0) ? '-' : '+';
4779 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
4780 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
4781 };
4782
4783 };
4784
4785 class FPU_State {
4786 public:
4787 enum {
4788 register_size = 10,
4789 number_of_registers = 8,
4790 register_mask = 7
4791 };
4792
4793 ControlWord _control_word;
4794 StatusWord _status_word;
4795 TagWord _tag_word;
4796 int32_t _error_offset;
4797 int32_t _error_selector;
4798 int32_t _data_offset;
4799 int32_t _data_selector;
4800 int8_t _register[register_size * number_of_registers];
4801
4802 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4803 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
4804
4805 const char* tag_as_string(int tag) const {
4806 switch (tag) {
4807 case 0: return "valid";
4808 case 1: return "zero";
4809 case 2: return "special";
4810 case 3: return "empty";
4811 }
4812 ShouldNotReachHere();
4813 return NULL;
4814 }
4815
4816 void print() const {
4817 // print computation registers
4818 { int t = _status_word.top();
4819 for (int i = 0; i < number_of_registers; i++) {
4820 int j = (i - t) & register_mask;
4821 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
4822 st(j)->print();
4823 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
4824 }
4825 }
4826 printf("\n");
4827 // print control registers
4828 printf("ctrl = "); _control_word.print(); printf("\n");
4829 printf("stat = "); _status_word .print(); printf("\n");
4830 printf("tags = "); _tag_word .print(); printf("\n");
4831 }
4832
4833 };
4834
4835 class Flag_Register {
4836 public:
4837 int32_t _value;
4838
4839 bool overflow() const { return ((_value >> 11) & 1) != 0; }
4840 bool direction() const { return ((_value >> 10) & 1) != 0; }
4841 bool sign() const { return ((_value >> 7) & 1) != 0; }
4842 bool zero() const { return ((_value >> 6) & 1) != 0; }
4843 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
4844 bool parity() const { return ((_value >> 2) & 1) != 0; }
4845 bool carry() const { return ((_value >> 0) & 1) != 0; }
4846
4847 void print() const {
4848 // flags
4849 char f[8];
4850 f[0] = (overflow ()) ? 'O' : '-';
4851 f[1] = (direction ()) ? 'D' : '-';
4852 f[2] = (sign ()) ? 'S' : '-';
4853 f[3] = (zero ()) ? 'Z' : '-';
4854 f[4] = (auxiliary_carry()) ? 'A' : '-';
4855 f[5] = (parity ()) ? 'P' : '-';
4856 f[6] = (carry ()) ? 'C' : '-';
4857 f[7] = '\x0';
4858 // output
4859 printf("%08x flags = %s", _value, f);
4860 }
4861
4862 };
4863
4864 class IU_Register {
4865 public:
4866 int32_t _value;
4867
4868 void print() const {
4869 printf("%08x %11d", _value, _value);
4870 }
4871
4872 };
4873
4874 class IU_State {
4875 public:
4876 Flag_Register _eflags;
4877 IU_Register _rdi;
4878 IU_Register _rsi;
4879 IU_Register _rbp;
4880 IU_Register _rsp;
4881 IU_Register _rbx;
4882 IU_Register _rdx;
4883 IU_Register _rcx;
4884 IU_Register _rax;
4885
4886 void print() const {
4887 // computation registers
4888 printf("rax, = "); _rax.print(); printf("\n");
4889 printf("rbx, = "); _rbx.print(); printf("\n");
4890 printf("rcx = "); _rcx.print(); printf("\n");
4891 printf("rdx = "); _rdx.print(); printf("\n");
4892 printf("rdi = "); _rdi.print(); printf("\n");
4893 printf("rsi = "); _rsi.print(); printf("\n");
4894 printf("rbp, = "); _rbp.print(); printf("\n");
4895 printf("rsp = "); _rsp.print(); printf("\n");
4896 printf("\n");
4897 // control registers
4898 printf("flgs = "); _eflags.print(); printf("\n");
4899 }
4900 };
4901
4902
4903 class CPU_State {
4904 public:
4905 FPU_State _fpu_state;
4906 IU_State _iu_state;
4907
4908 void print() const {
4909 printf("--------------------------------------------------\n");
4910 _iu_state .print();
4911 printf("\n");
4912 _fpu_state.print();
4913 printf("--------------------------------------------------\n");
4914 }
4915
4916 };
4917
4918
4919 static void _print_CPU_state(CPU_State* state) {
4920 state->print();
4921 };
4922
4923
4924 void MacroAssembler::print_CPU_state() {
4925 push_CPU_state();
4926 push(rsp); // pass CPU state
4927 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
4928 addptr(rsp, wordSize); // discard argument
4929 pop_CPU_state();
4930 }
4931
4932
4933 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
4934 static int counter = 0;
4935 FPU_State* fs = &state->_fpu_state;
4936 counter++;
4937 // For leaf calls, only verify that the top few elements remain empty.
4938 // We only need 1 empty at the top for C2 code.
4939 if( stack_depth < 0 ) {
4940 if( fs->tag_for_st(7) != 3 ) {
4941 printf("FPR7 not empty\n");
4942 state->print();
4943 assert(false, "error");
4944 return false;
4945 }
4946 return true; // All other stack states do not matter
4947 }
4948
4949 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
4950 "bad FPU control word");
4951
4952 // compute stack depth
4953 int i = 0;
4954 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
4955 int d = i;
4956 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
4957 // verify findings
4958 if (i != FPU_State::number_of_registers) {
4959 // stack not contiguous
4960 printf("%s: stack not contiguous at ST%d\n", s, i);
4961 state->print();
4962 assert(false, "error");
4963 return false;
4964 }
4965 // check if computed stack depth corresponds to expected stack depth
4966 if (stack_depth < 0) {
4967 // expected stack depth is -stack_depth or less
4968 if (d > -stack_depth) {
4969 // too many elements on the stack
4970 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
4971 state->print();
4972 assert(false, "error");
4973 return false;
4974 }
4975 } else {
4976 // expected stack depth is stack_depth
4977 if (d != stack_depth) {
4978 // wrong stack depth
4979 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
4980 state->print();
4981 assert(false, "error");
4982 return false;
4983 }
4984 }
4985 // everything is cool
4986 return true;
4987 }
4988
4989
4990 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
4991 if (!VerifyFPU) return;
4992 push_CPU_state();
4993 push(rsp); // pass CPU state
4994 ExternalAddress msg((address) s);
4995 // pass message string s
4996 pushptr(msg.addr());
4997 push(stack_depth); // pass stack depth
4998 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
4999 addptr(rsp, 3 * wordSize); // discard arguments
5000 // check for error
5001 { Label L;
5002 testl(rax, rax);
5003 jcc(Assembler::notZero, L);
5004 int3(); // break if error condition
5005 bind(L);
5006 }
5007 pop_CPU_state();
5008 }
5009
5010 void MacroAssembler::restore_cpu_control_state_after_jni() {
5011 // Either restore the MXCSR register after returning from the JNI Call
5012 // or verify that it wasn't changed (with -Xcheck:jni flag).
5013 if (VM_Version::supports_sse()) {
5014 if (RestoreMXCSROnJNICalls) {
5015 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5016 } else if (CheckJNICalls) {
5017 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5018 }
5019 }
5020 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5021 vzeroupper();
5022 // Reset k1 to 0xffff.
5023
5024 #ifdef COMPILER2
5025 if (PostLoopMultiversioning && VM_Version::supports_evex()) {
5026 push(rcx);
5027 movl(rcx, 0xffff);
5028 kmovwl(k1, rcx);
5029 pop(rcx);
5030 }
5031 #endif // COMPILER2
5032
5033 #ifndef _LP64
5034 // Either restore the x87 floating pointer control word after returning
5035 // from the JNI call or verify that it wasn't changed.
5036 if (CheckJNICalls) {
5037 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5038 }
5039 #endif // _LP64
5040 }
5041
5042 // ((OopHandle)result).resolve();
5043 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5044 assert_different_registers(result, tmp);
5045
5046 // Only 64 bit platforms support GCs that require a tmp register
5047 // Only IN_HEAP loads require a thread_tmp register
5048 // OopHandle::resolve is an indirection like jobject.
5049 access_load_at(T_OBJECT, IN_NATIVE,
5050 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5051 }
5052
5053 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5054 // get mirror
5055 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5056 movptr(mirror, Address(method, Method::const_offset()));
5057 movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
5058 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
5059 movptr(mirror, Address(mirror, mirror_offset));
5060 resolve_oop_handle(mirror, tmp);
5061 }
5062
5063 void MacroAssembler::load_klass(Register dst, Register src) {
5064 #ifdef _LP64
5065 if (UseCompressedClassPointers) {
5066 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5067 decode_klass_not_null(dst);
5068 } else
5069 #endif
5070 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5071 }
5072
5073 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5074 load_klass(dst, src);
5075 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5076 }
5077
5078 void MacroAssembler::store_klass(Register dst, Register src) {
5079 #ifdef _LP64
5080 if (UseCompressedClassPointers) {
5081 encode_klass_not_null(src);
5082 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5083 } else
5084 #endif
5085 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5086 }
5087
5088 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5089 Register tmp1, Register thread_tmp) {
5090 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5091 decorators = AccessInternal::decorator_fixup(decorators);
5092 bool as_raw = (decorators & AS_RAW) != 0;
5093 if (as_raw) {
5094 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5095 } else {
5096 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5097 }
5098 }
5099
5100 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
5101 Register tmp1, Register tmp2) {
5102 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5103 decorators = AccessInternal::decorator_fixup(decorators);
5104 bool as_raw = (decorators & AS_RAW) != 0;
5105 if (as_raw) {
5106 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
5107 } else {
5108 bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
5109 }
5110 }
5111
5112 void MacroAssembler::resolve(DecoratorSet decorators, Register obj) {
5113 // Use stronger ACCESS_WRITE|ACCESS_READ by default.
5114 if ((decorators & (ACCESS_READ | ACCESS_WRITE)) == 0) {
5115 decorators |= ACCESS_READ | ACCESS_WRITE;
5116 }
5117 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5118 return bs->resolve(this, decorators, obj);
5119 }
5120
5121 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5122 Register thread_tmp, DecoratorSet decorators) {
5123 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
5124 }
5125
5126 // Doesn't do verfication, generates fixed size code
5127 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5128 Register thread_tmp, DecoratorSet decorators) {
5129 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
5130 }
5131
5132 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
5133 Register tmp2, DecoratorSet decorators) {
5134 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5135 }
5136
5137 // Used for storing NULLs.
5138 void MacroAssembler::store_heap_oop_null(Address dst) {
5139 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
5140 }
5141
5142 #ifdef _LP64
5143 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5144 if (UseCompressedClassPointers) {
5145 // Store to klass gap in destination
5146 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5147 }
5148 }
5149
5150 #ifdef ASSERT
5151 void MacroAssembler::verify_heapbase(const char* msg) {
5152 assert (UseCompressedOops, "should be compressed");
5153 assert (Universe::heap() != NULL, "java heap should be initialized");
5154 if (CheckCompressedOops) {
5155 Label ok;
5156 push(rscratch1); // cmpptr trashes rscratch1
5157 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5158 jcc(Assembler::equal, ok);
5159 STOP(msg);
5160 bind(ok);
5161 pop(rscratch1);
5162 }
5163 }
5164 #endif
5165
5166 // Algorithm must match oop.inline.hpp encode_heap_oop.
5167 void MacroAssembler::encode_heap_oop(Register r) {
5168 #ifdef ASSERT
5169 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5170 #endif
5171 verify_oop(r, "broken oop in encode_heap_oop");
5172 if (Universe::narrow_oop_base() == NULL) {
5173 if (Universe::narrow_oop_shift() != 0) {
5174 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5175 shrq(r, LogMinObjAlignmentInBytes);
5176 }
5177 return;
5178 }
5179 testq(r, r);
5180 cmovq(Assembler::equal, r, r12_heapbase);
5181 subq(r, r12_heapbase);
5182 shrq(r, LogMinObjAlignmentInBytes);
5183 }
5184
5185 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5186 #ifdef ASSERT
5187 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5188 if (CheckCompressedOops) {
5189 Label ok;
5190 testq(r, r);
5191 jcc(Assembler::notEqual, ok);
5192 STOP("null oop passed to encode_heap_oop_not_null");
5193 bind(ok);
5194 }
5195 #endif
5196 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5197 if (Universe::narrow_oop_base() != NULL) {
5198 subq(r, r12_heapbase);
5199 }
5200 if (Universe::narrow_oop_shift() != 0) {
5201 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5202 shrq(r, LogMinObjAlignmentInBytes);
5203 }
5204 }
5205
5206 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5207 #ifdef ASSERT
5208 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5209 if (CheckCompressedOops) {
5210 Label ok;
5211 testq(src, src);
5212 jcc(Assembler::notEqual, ok);
5213 STOP("null oop passed to encode_heap_oop_not_null2");
5214 bind(ok);
5215 }
5216 #endif
5217 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5218 if (dst != src) {
5219 movq(dst, src);
5220 }
5221 if (Universe::narrow_oop_base() != NULL) {
5222 subq(dst, r12_heapbase);
5223 }
5224 if (Universe::narrow_oop_shift() != 0) {
5225 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5226 shrq(dst, LogMinObjAlignmentInBytes);
5227 }
5228 }
5229
5230 void MacroAssembler::decode_heap_oop(Register r) {
5231 #ifdef ASSERT
5232 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5233 #endif
5234 if (Universe::narrow_oop_base() == NULL) {
5235 if (Universe::narrow_oop_shift() != 0) {
5236 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5237 shlq(r, LogMinObjAlignmentInBytes);
5238 }
5239 } else {
5240 Label done;
5241 shlq(r, LogMinObjAlignmentInBytes);
5242 jccb(Assembler::equal, done);
5243 addq(r, r12_heapbase);
5244 bind(done);
5245 }
5246 verify_oop(r, "broken oop in decode_heap_oop");
5247 }
5248
5249 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5250 // Note: it will change flags
5251 assert (UseCompressedOops, "should only be used for compressed headers");
5252 assert (Universe::heap() != NULL, "java heap should be initialized");
5253 // Cannot assert, unverified entry point counts instructions (see .ad file)
5254 // vtableStubs also counts instructions in pd_code_size_limit.
5255 // Also do not verify_oop as this is called by verify_oop.
5256 if (Universe::narrow_oop_shift() != 0) {
5257 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5258 shlq(r, LogMinObjAlignmentInBytes);
5259 if (Universe::narrow_oop_base() != NULL) {
5260 addq(r, r12_heapbase);
5261 }
5262 } else {
5263 assert (Universe::narrow_oop_base() == NULL, "sanity");
5264 }
5265 }
5266
5267 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5268 // Note: it will change flags
5269 assert (UseCompressedOops, "should only be used for compressed headers");
5270 assert (Universe::heap() != NULL, "java heap should be initialized");
5271 // Cannot assert, unverified entry point counts instructions (see .ad file)
5272 // vtableStubs also counts instructions in pd_code_size_limit.
5273 // Also do not verify_oop as this is called by verify_oop.
5274 if (Universe::narrow_oop_shift() != 0) {
5275 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5276 if (LogMinObjAlignmentInBytes == Address::times_8) {
5277 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5278 } else {
5279 if (dst != src) {
5280 movq(dst, src);
5281 }
5282 shlq(dst, LogMinObjAlignmentInBytes);
5283 if (Universe::narrow_oop_base() != NULL) {
5284 addq(dst, r12_heapbase);
5285 }
5286 }
5287 } else {
5288 assert (Universe::narrow_oop_base() == NULL, "sanity");
5289 if (dst != src) {
5290 movq(dst, src);
5291 }
5292 }
5293 }
5294
5295 void MacroAssembler::encode_klass_not_null(Register r) {
5296 if (Universe::narrow_klass_base() != NULL) {
5297 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5298 assert(r != r12_heapbase, "Encoding a klass in r12");
5299 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5300 subq(r, r12_heapbase);
5301 }
5302 if (Universe::narrow_klass_shift() != 0) {
5303 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5304 shrq(r, LogKlassAlignmentInBytes);
5305 }
5306 if (Universe::narrow_klass_base() != NULL) {
5307 reinit_heapbase();
5308 }
5309 }
5310
5311 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5312 if (dst == src) {
5313 encode_klass_not_null(src);
5314 } else {
5315 if (Universe::narrow_klass_base() != NULL) {
5316 mov64(dst, (int64_t)Universe::narrow_klass_base());
5317 negq(dst);
5318 addq(dst, src);
5319 } else {
5320 movptr(dst, src);
5321 }
5322 if (Universe::narrow_klass_shift() != 0) {
5323 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5324 shrq(dst, LogKlassAlignmentInBytes);
5325 }
5326 }
5327 }
5328
5329 // Function instr_size_for_decode_klass_not_null() counts the instructions
5330 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5331 // when (Universe::heap() != NULL). Hence, if the instructions they
5332 // generate change, then this method needs to be updated.
5333 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5334 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5335 if (Universe::narrow_klass_base() != NULL) {
5336 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
5337 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
5338 } else {
5339 // longest load decode klass function, mov64, leaq
5340 return 16;
5341 }
5342 }
5343
5344 // !!! If the instructions that get generated here change then function
5345 // instr_size_for_decode_klass_not_null() needs to get updated.
5346 void MacroAssembler::decode_klass_not_null(Register r) {
5347 // Note: it will change flags
5348 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5349 assert(r != r12_heapbase, "Decoding a klass in r12");
5350 // Cannot assert, unverified entry point counts instructions (see .ad file)
5351 // vtableStubs also counts instructions in pd_code_size_limit.
5352 // Also do not verify_oop as this is called by verify_oop.
5353 if (Universe::narrow_klass_shift() != 0) {
5354 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5355 shlq(r, LogKlassAlignmentInBytes);
5356 }
5357 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5358 if (Universe::narrow_klass_base() != NULL) {
5359 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5360 addq(r, r12_heapbase);
5361 reinit_heapbase();
5362 }
5363 }
5364
5365 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5366 // Note: it will change flags
5367 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5368 if (dst == src) {
5369 decode_klass_not_null(dst);
5370 } else {
5371 // Cannot assert, unverified entry point counts instructions (see .ad file)
5372 // vtableStubs also counts instructions in pd_code_size_limit.
5373 // Also do not verify_oop as this is called by verify_oop.
5374 mov64(dst, (int64_t)Universe::narrow_klass_base());
5375 if (Universe::narrow_klass_shift() != 0) {
5376 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5377 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5378 leaq(dst, Address(dst, src, Address::times_8, 0));
5379 } else {
5380 addq(dst, src);
5381 }
5382 }
5383 }
5384
5385 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5386 assert (UseCompressedOops, "should only be used for compressed headers");
5387 assert (Universe::heap() != NULL, "java heap should be initialized");
5388 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5389 int oop_index = oop_recorder()->find_index(obj);
5390 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5391 mov_narrow_oop(dst, oop_index, rspec);
5392 }
5393
5394 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5395 assert (UseCompressedOops, "should only be used for compressed headers");
5396 assert (Universe::heap() != NULL, "java heap should be initialized");
5397 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5398 int oop_index = oop_recorder()->find_index(obj);
5399 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5400 mov_narrow_oop(dst, oop_index, rspec);
5401 }
5402
5403 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5404 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5405 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5406 int klass_index = oop_recorder()->find_index(k);
5407 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5408 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
5409 }
5410
5411 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5412 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5413 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5414 int klass_index = oop_recorder()->find_index(k);
5415 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5416 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
5417 }
5418
5419 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5420 assert (UseCompressedOops, "should only be used for compressed headers");
5421 assert (Universe::heap() != NULL, "java heap should be initialized");
5422 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5423 int oop_index = oop_recorder()->find_index(obj);
5424 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5425 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5426 }
5427
5428 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5429 assert (UseCompressedOops, "should only be used for compressed headers");
5430 assert (Universe::heap() != NULL, "java heap should be initialized");
5431 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5432 int oop_index = oop_recorder()->find_index(obj);
5433 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5434 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5435 }
5436
5437 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5438 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5439 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5440 int klass_index = oop_recorder()->find_index(k);
5441 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5442 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
5443 }
5444
5445 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5446 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5447 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5448 int klass_index = oop_recorder()->find_index(k);
5449 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5450 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
5451 }
5452
5453 void MacroAssembler::reinit_heapbase() {
5454 if (UseCompressedOops || UseCompressedClassPointers) {
5455 if (Universe::heap() != NULL) {
5456 if (Universe::narrow_oop_base() == NULL) {
5457 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5458 } else {
5459 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
5460 }
5461 } else {
5462 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5463 }
5464 }
5465 }
5466
5467 #endif // _LP64
5468
5469 // C2 compiled method's prolog code.
5470 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub) {
5471
5472 // WARNING: Initial instruction MUST be 5 bytes or longer so that
5473 // NativeJump::patch_verified_entry will be able to patch out the entry
5474 // code safely. The push to verify stack depth is ok at 5 bytes,
5475 // the frame allocation can be either 3 or 6 bytes. So if we don't do
5476 // stack bang then we must use the 6 byte frame allocation even if
5477 // we have no frame. :-(
5478 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
5479
5480 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5481 // Remove word for return addr
5482 framesize -= wordSize;
5483 stack_bang_size -= wordSize;
5484
5485 // Calls to C2R adapters often do not accept exceptional returns.
5486 // We require that their callers must bang for them. But be careful, because
5487 // some VM calls (such as call site linkage) can use several kilobytes of
5488 // stack. But the stack safety zone should account for that.
5489 // See bugs 4446381, 4468289, 4497237.
5490 if (stack_bang_size > 0) {
5491 generate_stack_overflow_check(stack_bang_size);
5492
5493 // We always push rbp, so that on return to interpreter rbp, will be
5494 // restored correctly and we can correct the stack.
5495 push(rbp);
5496 // Save caller's stack pointer into RBP if the frame pointer is preserved.
5497 if (PreserveFramePointer) {
5498 mov(rbp, rsp);
5499 }
5500 // Remove word for ebp
5501 framesize -= wordSize;
5502
5503 // Create frame
5504 if (framesize) {
5505 subptr(rsp, framesize);
5506 }
5507 } else {
5508 // Create frame (force generation of a 4 byte immediate value)
5509 subptr_imm32(rsp, framesize);
5510
5511 // Save RBP register now.
5512 framesize -= wordSize;
5513 movptr(Address(rsp, framesize), rbp);
5514 // Save caller's stack pointer into RBP if the frame pointer is preserved.
5515 if (PreserveFramePointer) {
5516 movptr(rbp, rsp);
5517 if (framesize > 0) {
5518 addptr(rbp, framesize);
5519 }
5520 }
5521 }
5522
5523 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
5524 framesize -= wordSize;
5525 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
5526 }
5527
5528 #ifndef _LP64
5529 // If method sets FPU control word do it now
5530 if (fp_mode_24b) {
5531 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
5532 }
5533 if (UseSSE >= 2 && VerifyFPU) {
5534 verify_FPU(0, "FPU stack must be clean on entry");
5535 }
5536 #endif
5537
5538 #ifdef ASSERT
5539 if (VerifyStackAtCalls) {
5540 Label L;
5541 push(rax);
5542 mov(rax, rsp);
5543 andptr(rax, StackAlignmentInBytes-1);
5544 cmpptr(rax, StackAlignmentInBytes-wordSize);
5545 pop(rax);
5546 jcc(Assembler::equal, L);
5547 STOP("Stack is not properly aligned!");
5548 bind(L);
5549 }
5550 #endif
5551
5552 if (!is_stub) {
5553 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5554 bs->nmethod_entry_barrier(this);
5555 }
5556 }
5557
5558 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
5559 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp) {
5560 // cnt - number of qwords (8-byte words).
5561 // base - start address, qword aligned.
5562 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5563 if (UseAVX >= 2) {
5564 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5565 } else {
5566 pxor(xtmp, xtmp);
5567 }
5568 jmp(L_zero_64_bytes);
5569
5570 BIND(L_loop);
5571 if (UseAVX >= 2) {
5572 vmovdqu(Address(base, 0), xtmp);
5573 vmovdqu(Address(base, 32), xtmp);
5574 } else {
5575 movdqu(Address(base, 0), xtmp);
5576 movdqu(Address(base, 16), xtmp);
5577 movdqu(Address(base, 32), xtmp);
5578 movdqu(Address(base, 48), xtmp);
5579 }
5580 addptr(base, 64);
5581
5582 BIND(L_zero_64_bytes);
5583 subptr(cnt, 8);
5584 jccb(Assembler::greaterEqual, L_loop);
5585 addptr(cnt, 4);
5586 jccb(Assembler::less, L_tail);
5587 // Copy trailing 32 bytes
5588 if (UseAVX >= 2) {
5589 vmovdqu(Address(base, 0), xtmp);
5590 } else {
5591 movdqu(Address(base, 0), xtmp);
5592 movdqu(Address(base, 16), xtmp);
5593 }
5594 addptr(base, 32);
5595 subptr(cnt, 4);
5596
5597 BIND(L_tail);
5598 addptr(cnt, 4);
5599 jccb(Assembler::lessEqual, L_end);
5600 decrement(cnt);
5601
5602 BIND(L_sloop);
5603 movq(Address(base, 0), xtmp);
5604 addptr(base, 8);
5605 decrement(cnt);
5606 jccb(Assembler::greaterEqual, L_sloop);
5607 BIND(L_end);
5608 }
5609
5610 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp, bool is_large) {
5611 // cnt - number of qwords (8-byte words).
5612 // base - start address, qword aligned.
5613 // is_large - if optimizers know cnt is larger than InitArrayShortSize
5614 assert(base==rdi, "base register must be edi for rep stos");
5615 assert(tmp==rax, "tmp register must be eax for rep stos");
5616 assert(cnt==rcx, "cnt register must be ecx for rep stos");
5617 assert(InitArrayShortSize % BytesPerLong == 0,
5618 "InitArrayShortSize should be the multiple of BytesPerLong");
5619
5620 Label DONE;
5621
5622 if (!is_large || !UseXMMForObjInit) {
5623 xorptr(tmp, tmp);
5624 }
5625
5626 if (!is_large) {
5627 Label LOOP, LONG;
5628 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5629 jccb(Assembler::greater, LONG);
5630
5631 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5632
5633 decrement(cnt);
5634 jccb(Assembler::negative, DONE); // Zero length
5635
5636 // Use individual pointer-sized stores for small counts:
5637 BIND(LOOP);
5638 movptr(Address(base, cnt, Address::times_ptr), tmp);
5639 decrement(cnt);
5640 jccb(Assembler::greaterEqual, LOOP);
5641 jmpb(DONE);
5642
5643 BIND(LONG);
5644 }
5645
5646 // Use longer rep-prefixed ops for non-small counts:
5647 if (UseFastStosb) {
5648 shlptr(cnt, 3); // convert to number of bytes
5649 rep_stosb();
5650 } else if (UseXMMForObjInit) {
5651 movptr(tmp, base);
5652 xmm_clear_mem(tmp, cnt, xtmp);
5653 } else {
5654 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5655 rep_stos();
5656 }
5657
5658 BIND(DONE);
5659 }
5660
5661 #ifdef COMPILER2
5662
5663 // IndexOf for constant substrings with size >= 8 chars
5664 // which don't need to be loaded through stack.
5665 void MacroAssembler::string_indexofC8(Register str1, Register str2,
5666 Register cnt1, Register cnt2,
5667 int int_cnt2, Register result,
5668 XMMRegister vec, Register tmp,
5669 int ae) {
5670 ShortBranchVerifier sbv(this);
5671 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
5672 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
5673
5674 // This method uses the pcmpestri instruction with bound registers
5675 // inputs:
5676 // xmm - substring
5677 // rax - substring length (elements count)
5678 // mem - scanned string
5679 // rdx - string length (elements count)
5680 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
5681 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
5682 // outputs:
5683 // rcx - matched index in string
5684 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
5685 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
5686 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
5687 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
5688 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
5689
5690 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
5691 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
5692 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
5693
5694 // Note, inline_string_indexOf() generates checks:
5695 // if (substr.count > string.count) return -1;
5696 // if (substr.count == 0) return 0;
5697 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
5698
5699 // Load substring.
5700 if (ae == StrIntrinsicNode::UL) {
5701 pmovzxbw(vec, Address(str2, 0));
5702 } else {
5703 movdqu(vec, Address(str2, 0));
5704 }
5705 movl(cnt2, int_cnt2);
5706 movptr(result, str1); // string addr
5707
5708 if (int_cnt2 > stride) {
5709 jmpb(SCAN_TO_SUBSTR);
5710
5711 // Reload substr for rescan, this code
5712 // is executed only for large substrings (> 8 chars)
5713 bind(RELOAD_SUBSTR);
5714 if (ae == StrIntrinsicNode::UL) {
5715 pmovzxbw(vec, Address(str2, 0));
5716 } else {
5717 movdqu(vec, Address(str2, 0));
5718 }
5719 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
5720
5721 bind(RELOAD_STR);
5722 // We came here after the beginning of the substring was
5723 // matched but the rest of it was not so we need to search
5724 // again. Start from the next element after the previous match.
5725
5726 // cnt2 is number of substring reminding elements and
5727 // cnt1 is number of string reminding elements when cmp failed.
5728 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
5729 subl(cnt1, cnt2);
5730 addl(cnt1, int_cnt2);
5731 movl(cnt2, int_cnt2); // Now restore cnt2
5732
5733 decrementl(cnt1); // Shift to next element
5734 cmpl(cnt1, cnt2);
5735 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
5736
5737 addptr(result, (1<<scale1));
5738
5739 } // (int_cnt2 > 8)
5740
5741 // Scan string for start of substr in 16-byte vectors
5742 bind(SCAN_TO_SUBSTR);
5743 pcmpestri(vec, Address(result, 0), mode);
5744 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
5745 subl(cnt1, stride);
5746 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
5747 cmpl(cnt1, cnt2);
5748 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
5749 addptr(result, 16);
5750 jmpb(SCAN_TO_SUBSTR);
5751
5752 // Found a potential substr
5753 bind(FOUND_CANDIDATE);
5754 // Matched whole vector if first element matched (tmp(rcx) == 0).
5755 if (int_cnt2 == stride) {
5756 jccb(Assembler::overflow, RET_FOUND); // OF == 1
5757 } else { // int_cnt2 > 8
5758 jccb(Assembler::overflow, FOUND_SUBSTR);
5759 }
5760 // After pcmpestri tmp(rcx) contains matched element index
5761 // Compute start addr of substr
5762 lea(result, Address(result, tmp, scale1));
5763
5764 // Make sure string is still long enough
5765 subl(cnt1, tmp);
5766 cmpl(cnt1, cnt2);
5767 if (int_cnt2 == stride) {
5768 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
5769 } else { // int_cnt2 > 8
5770 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
5771 }
5772 // Left less then substring.
5773
5774 bind(RET_NOT_FOUND);
5775 movl(result, -1);
5776 jmp(EXIT);
5777
5778 if (int_cnt2 > stride) {
5779 // This code is optimized for the case when whole substring
5780 // is matched if its head is matched.
5781 bind(MATCH_SUBSTR_HEAD);
5782 pcmpestri(vec, Address(result, 0), mode);
5783 // Reload only string if does not match
5784 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
5785
5786 Label CONT_SCAN_SUBSTR;
5787 // Compare the rest of substring (> 8 chars).
5788 bind(FOUND_SUBSTR);
5789 // First 8 chars are already matched.
5790 negptr(cnt2);
5791 addptr(cnt2, stride);
5792
5793 bind(SCAN_SUBSTR);
5794 subl(cnt1, stride);
5795 cmpl(cnt2, -stride); // Do not read beyond substring
5796 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
5797 // Back-up strings to avoid reading beyond substring:
5798 // cnt1 = cnt1 - cnt2 + 8
5799 addl(cnt1, cnt2); // cnt2 is negative
5800 addl(cnt1, stride);
5801 movl(cnt2, stride); negptr(cnt2);
5802 bind(CONT_SCAN_SUBSTR);
5803 if (int_cnt2 < (int)G) {
5804 int tail_off1 = int_cnt2<<scale1;
5805 int tail_off2 = int_cnt2<<scale2;
5806 if (ae == StrIntrinsicNode::UL) {
5807 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
5808 } else {
5809 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
5810 }
5811 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
5812 } else {
5813 // calculate index in register to avoid integer overflow (int_cnt2*2)
5814 movl(tmp, int_cnt2);
5815 addptr(tmp, cnt2);
5816 if (ae == StrIntrinsicNode::UL) {
5817 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
5818 } else {
5819 movdqu(vec, Address(str2, tmp, scale2, 0));
5820 }
5821 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
5822 }
5823 // Need to reload strings pointers if not matched whole vector
5824 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
5825 addptr(cnt2, stride);
5826 jcc(Assembler::negative, SCAN_SUBSTR);
5827 // Fall through if found full substring
5828
5829 } // (int_cnt2 > 8)
5830
5831 bind(RET_FOUND);
5832 // Found result if we matched full small substring.
5833 // Compute substr offset
5834 subptr(result, str1);
5835 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
5836 shrl(result, 1); // index
5837 }
5838 bind(EXIT);
5839
5840 } // string_indexofC8
5841
5842 // Small strings are loaded through stack if they cross page boundary.
5843 void MacroAssembler::string_indexof(Register str1, Register str2,
5844 Register cnt1, Register cnt2,
5845 int int_cnt2, Register result,
5846 XMMRegister vec, Register tmp,
5847 int ae) {
5848 ShortBranchVerifier sbv(this);
5849 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
5850 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
5851
5852 //
5853 // int_cnt2 is length of small (< 8 chars) constant substring
5854 // or (-1) for non constant substring in which case its length
5855 // is in cnt2 register.
5856 //
5857 // Note, inline_string_indexOf() generates checks:
5858 // if (substr.count > string.count) return -1;
5859 // if (substr.count == 0) return 0;
5860 //
5861 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
5862 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
5863 // This method uses the pcmpestri instruction with bound registers
5864 // inputs:
5865 // xmm - substring
5866 // rax - substring length (elements count)
5867 // mem - scanned string
5868 // rdx - string length (elements count)
5869 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
5870 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
5871 // outputs:
5872 // rcx - matched index in string
5873 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
5874 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
5875 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
5876 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
5877
5878 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
5879 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
5880 FOUND_CANDIDATE;
5881
5882 { //========================================================
5883 // We don't know where these strings are located
5884 // and we can't read beyond them. Load them through stack.
5885 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
5886
5887 movptr(tmp, rsp); // save old SP
5888
5889 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
5890 if (int_cnt2 == (1>>scale2)) { // One byte
5891 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
5892 load_unsigned_byte(result, Address(str2, 0));
5893 movdl(vec, result); // move 32 bits
5894 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
5895 // Not enough header space in 32-bit VM: 12+3 = 15.
5896 movl(result, Address(str2, -1));
5897 shrl(result, 8);
5898 movdl(vec, result); // move 32 bits
5899 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
5900 load_unsigned_short(result, Address(str2, 0));
5901 movdl(vec, result); // move 32 bits
5902 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
5903 movdl(vec, Address(str2, 0)); // move 32 bits
5904 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
5905 movq(vec, Address(str2, 0)); // move 64 bits
5906 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
5907 // Array header size is 12 bytes in 32-bit VM
5908 // + 6 bytes for 3 chars == 18 bytes,
5909 // enough space to load vec and shift.
5910 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
5911 if (ae == StrIntrinsicNode::UL) {
5912 int tail_off = int_cnt2-8;
5913 pmovzxbw(vec, Address(str2, tail_off));
5914 psrldq(vec, -2*tail_off);
5915 }
5916 else {
5917 int tail_off = int_cnt2*(1<<scale2);
5918 movdqu(vec, Address(str2, tail_off-16));
5919 psrldq(vec, 16-tail_off);
5920 }
5921 }
5922 } else { // not constant substring
5923 cmpl(cnt2, stride);
5924 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
5925
5926 // We can read beyond string if srt+16 does not cross page boundary
5927 // since heaps are aligned and mapped by pages.
5928 assert(os::vm_page_size() < (int)G, "default page should be small");
5929 movl(result, str2); // We need only low 32 bits
5930 andl(result, (os::vm_page_size()-1));
5931 cmpl(result, (os::vm_page_size()-16));
5932 jccb(Assembler::belowEqual, CHECK_STR);
5933
5934 // Move small strings to stack to allow load 16 bytes into vec.
5935 subptr(rsp, 16);
5936 int stk_offset = wordSize-(1<<scale2);
5937 push(cnt2);
5938
5939 bind(COPY_SUBSTR);
5940 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
5941 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
5942 movb(Address(rsp, cnt2, scale2, stk_offset), result);
5943 } else if (ae == StrIntrinsicNode::UU) {
5944 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
5945 movw(Address(rsp, cnt2, scale2, stk_offset), result);
5946 }
5947 decrement(cnt2);
5948 jccb(Assembler::notZero, COPY_SUBSTR);
5949
5950 pop(cnt2);
5951 movptr(str2, rsp); // New substring address
5952 } // non constant
5953
5954 bind(CHECK_STR);
5955 cmpl(cnt1, stride);
5956 jccb(Assembler::aboveEqual, BIG_STRINGS);
5957
5958 // Check cross page boundary.
5959 movl(result, str1); // We need only low 32 bits
5960 andl(result, (os::vm_page_size()-1));
5961 cmpl(result, (os::vm_page_size()-16));
5962 jccb(Assembler::belowEqual, BIG_STRINGS);
5963
5964 subptr(rsp, 16);
5965 int stk_offset = -(1<<scale1);
5966 if (int_cnt2 < 0) { // not constant
5967 push(cnt2);
5968 stk_offset += wordSize;
5969 }
5970 movl(cnt2, cnt1);
5971
5972 bind(COPY_STR);
5973 if (ae == StrIntrinsicNode::LL) {
5974 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
5975 movb(Address(rsp, cnt2, scale1, stk_offset), result);
5976 } else {
5977 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
5978 movw(Address(rsp, cnt2, scale1, stk_offset), result);
5979 }
5980 decrement(cnt2);
5981 jccb(Assembler::notZero, COPY_STR);
5982
5983 if (int_cnt2 < 0) { // not constant
5984 pop(cnt2);
5985 }
5986 movptr(str1, rsp); // New string address
5987
5988 bind(BIG_STRINGS);
5989 // Load substring.
5990 if (int_cnt2 < 0) { // -1
5991 if (ae == StrIntrinsicNode::UL) {
5992 pmovzxbw(vec, Address(str2, 0));
5993 } else {
5994 movdqu(vec, Address(str2, 0));
5995 }
5996 push(cnt2); // substr count
5997 push(str2); // substr addr
5998 push(str1); // string addr
5999 } else {
6000 // Small (< 8 chars) constant substrings are loaded already.
6001 movl(cnt2, int_cnt2);
6002 }
6003 push(tmp); // original SP
6004
6005 } // Finished loading
6006
6007 //========================================================
6008 // Start search
6009 //
6010
6011 movptr(result, str1); // string addr
6012
6013 if (int_cnt2 < 0) { // Only for non constant substring
6014 jmpb(SCAN_TO_SUBSTR);
6015
6016 // SP saved at sp+0
6017 // String saved at sp+1*wordSize
6018 // Substr saved at sp+2*wordSize
6019 // Substr count saved at sp+3*wordSize
6020
6021 // Reload substr for rescan, this code
6022 // is executed only for large substrings (> 8 chars)
6023 bind(RELOAD_SUBSTR);
6024 movptr(str2, Address(rsp, 2*wordSize));
6025 movl(cnt2, Address(rsp, 3*wordSize));
6026 if (ae == StrIntrinsicNode::UL) {
6027 pmovzxbw(vec, Address(str2, 0));
6028 } else {
6029 movdqu(vec, Address(str2, 0));
6030 }
6031 // We came here after the beginning of the substring was
6032 // matched but the rest of it was not so we need to search
6033 // again. Start from the next element after the previous match.
6034 subptr(str1, result); // Restore counter
6035 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6036 shrl(str1, 1);
6037 }
6038 addl(cnt1, str1);
6039 decrementl(cnt1); // Shift to next element
6040 cmpl(cnt1, cnt2);
6041 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6042
6043 addptr(result, (1<<scale1));
6044 } // non constant
6045
6046 // Scan string for start of substr in 16-byte vectors
6047 bind(SCAN_TO_SUBSTR);
6048 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6049 pcmpestri(vec, Address(result, 0), mode);
6050 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6051 subl(cnt1, stride);
6052 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6053 cmpl(cnt1, cnt2);
6054 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6055 addptr(result, 16);
6056
6057 bind(ADJUST_STR);
6058 cmpl(cnt1, stride); // Do not read beyond string
6059 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6060 // Back-up string to avoid reading beyond string.
6061 lea(result, Address(result, cnt1, scale1, -16));
6062 movl(cnt1, stride);
6063 jmpb(SCAN_TO_SUBSTR);
6064
6065 // Found a potential substr
6066 bind(FOUND_CANDIDATE);
6067 // After pcmpestri tmp(rcx) contains matched element index
6068
6069 // Make sure string is still long enough
6070 subl(cnt1, tmp);
6071 cmpl(cnt1, cnt2);
6072 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6073 // Left less then substring.
6074
6075 bind(RET_NOT_FOUND);
6076 movl(result, -1);
6077 jmp(CLEANUP);
6078
6079 bind(FOUND_SUBSTR);
6080 // Compute start addr of substr
6081 lea(result, Address(result, tmp, scale1));
6082 if (int_cnt2 > 0) { // Constant substring
6083 // Repeat search for small substring (< 8 chars)
6084 // from new point without reloading substring.
6085 // Have to check that we don't read beyond string.
6086 cmpl(tmp, stride-int_cnt2);
6087 jccb(Assembler::greater, ADJUST_STR);
6088 // Fall through if matched whole substring.
6089 } else { // non constant
6090 assert(int_cnt2 == -1, "should be != 0");
6091
6092 addl(tmp, cnt2);
6093 // Found result if we matched whole substring.
6094 cmpl(tmp, stride);
6095 jcc(Assembler::lessEqual, RET_FOUND);
6096
6097 // Repeat search for small substring (<= 8 chars)
6098 // from new point 'str1' without reloading substring.
6099 cmpl(cnt2, stride);
6100 // Have to check that we don't read beyond string.
6101 jccb(Assembler::lessEqual, ADJUST_STR);
6102
6103 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6104 // Compare the rest of substring (> 8 chars).
6105 movptr(str1, result);
6106
6107 cmpl(tmp, cnt2);
6108 // First 8 chars are already matched.
6109 jccb(Assembler::equal, CHECK_NEXT);
6110
6111 bind(SCAN_SUBSTR);
6112 pcmpestri(vec, Address(str1, 0), mode);
6113 // Need to reload strings pointers if not matched whole vector
6114 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6115
6116 bind(CHECK_NEXT);
6117 subl(cnt2, stride);
6118 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6119 addptr(str1, 16);
6120 if (ae == StrIntrinsicNode::UL) {
6121 addptr(str2, 8);
6122 } else {
6123 addptr(str2, 16);
6124 }
6125 subl(cnt1, stride);
6126 cmpl(cnt2, stride); // Do not read beyond substring
6127 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6128 // Back-up strings to avoid reading beyond substring.
6129
6130 if (ae == StrIntrinsicNode::UL) {
6131 lea(str2, Address(str2, cnt2, scale2, -8));
6132 lea(str1, Address(str1, cnt2, scale1, -16));
6133 } else {
6134 lea(str2, Address(str2, cnt2, scale2, -16));
6135 lea(str1, Address(str1, cnt2, scale1, -16));
6136 }
6137 subl(cnt1, cnt2);
6138 movl(cnt2, stride);
6139 addl(cnt1, stride);
6140 bind(CONT_SCAN_SUBSTR);
6141 if (ae == StrIntrinsicNode::UL) {
6142 pmovzxbw(vec, Address(str2, 0));
6143 } else {
6144 movdqu(vec, Address(str2, 0));
6145 }
6146 jmp(SCAN_SUBSTR);
6147
6148 bind(RET_FOUND_LONG);
6149 movptr(str1, Address(rsp, wordSize));
6150 } // non constant
6151
6152 bind(RET_FOUND);
6153 // Compute substr offset
6154 subptr(result, str1);
6155 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6156 shrl(result, 1); // index
6157 }
6158 bind(CLEANUP);
6159 pop(rsp); // restore SP
6160
6161 } // string_indexof
6162
6163 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
6164 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
6165 ShortBranchVerifier sbv(this);
6166 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6167
6168 int stride = 8;
6169
6170 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
6171 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
6172 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
6173 FOUND_SEQ_CHAR, DONE_LABEL;
6174
6175 movptr(result, str1);
6176 if (UseAVX >= 2) {
6177 cmpl(cnt1, stride);
6178 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
6179 cmpl(cnt1, 2*stride);
6180 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
6181 movdl(vec1, ch);
6182 vpbroadcastw(vec1, vec1, Assembler::AVX_256bit);
6183 vpxor(vec2, vec2);
6184 movl(tmp, cnt1);
6185 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
6186 andl(cnt1,0x0000000F); //tail count (in chars)
6187
6188 bind(SCAN_TO_16_CHAR_LOOP);
6189 vmovdqu(vec3, Address(result, 0));
6190 vpcmpeqw(vec3, vec3, vec1, 1);
6191 vptest(vec2, vec3);
6192 jcc(Assembler::carryClear, FOUND_CHAR);
6193 addptr(result, 32);
6194 subl(tmp, 2*stride);
6195 jcc(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
6196 jmp(SCAN_TO_8_CHAR);
6197 bind(SCAN_TO_8_CHAR_INIT);
6198 movdl(vec1, ch);
6199 pshuflw(vec1, vec1, 0x00);
6200 pshufd(vec1, vec1, 0);
6201 pxor(vec2, vec2);
6202 }
6203 bind(SCAN_TO_8_CHAR);
6204 cmpl(cnt1, stride);
6205 if (UseAVX >= 2) {
6206 jcc(Assembler::less, SCAN_TO_CHAR);
6207 } else {
6208 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
6209 movdl(vec1, ch);
6210 pshuflw(vec1, vec1, 0x00);
6211 pshufd(vec1, vec1, 0);
6212 pxor(vec2, vec2);
6213 }
6214 movl(tmp, cnt1);
6215 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
6216 andl(cnt1,0x00000007); //tail count (in chars)
6217
6218 bind(SCAN_TO_8_CHAR_LOOP);
6219 movdqu(vec3, Address(result, 0));
6220 pcmpeqw(vec3, vec1);
6221 ptest(vec2, vec3);
6222 jcc(Assembler::carryClear, FOUND_CHAR);
6223 addptr(result, 16);
6224 subl(tmp, stride);
6225 jcc(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
6226 bind(SCAN_TO_CHAR);
6227 testl(cnt1, cnt1);
6228 jcc(Assembler::zero, RET_NOT_FOUND);
6229 bind(SCAN_TO_CHAR_LOOP);
6230 load_unsigned_short(tmp, Address(result, 0));
6231 cmpl(ch, tmp);
6232 jccb(Assembler::equal, FOUND_SEQ_CHAR);
6233 addptr(result, 2);
6234 subl(cnt1, 1);
6235 jccb(Assembler::zero, RET_NOT_FOUND);
6236 jmp(SCAN_TO_CHAR_LOOP);
6237
6238 bind(RET_NOT_FOUND);
6239 movl(result, -1);
6240 jmpb(DONE_LABEL);
6241
6242 bind(FOUND_CHAR);
6243 if (UseAVX >= 2) {
6244 vpmovmskb(tmp, vec3);
6245 } else {
6246 pmovmskb(tmp, vec3);
6247 }
6248 bsfl(ch, tmp);
6249 addl(result, ch);
6250
6251 bind(FOUND_SEQ_CHAR);
6252 subptr(result, str1);
6253 shrl(result, 1);
6254
6255 bind(DONE_LABEL);
6256 } // string_indexof_char
6257
6258 // helper function for string_compare
6259 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
6260 Address::ScaleFactor scale, Address::ScaleFactor scale1,
6261 Address::ScaleFactor scale2, Register index, int ae) {
6262 if (ae == StrIntrinsicNode::LL) {
6263 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
6264 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
6265 } else if (ae == StrIntrinsicNode::UU) {
6266 load_unsigned_short(elem1, Address(str1, index, scale, 0));
6267 load_unsigned_short(elem2, Address(str2, index, scale, 0));
6268 } else {
6269 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
6270 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
6271 }
6272 }
6273
6274 // Compare strings, used for char[] and byte[].
6275 void MacroAssembler::string_compare(Register str1, Register str2,
6276 Register cnt1, Register cnt2, Register result,
6277 XMMRegister vec1, int ae) {
6278 ShortBranchVerifier sbv(this);
6279 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6280 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
6281 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
6282 int stride2x2 = 0x40;
6283 Address::ScaleFactor scale = Address::no_scale;
6284 Address::ScaleFactor scale1 = Address::no_scale;
6285 Address::ScaleFactor scale2 = Address::no_scale;
6286
6287 if (ae != StrIntrinsicNode::LL) {
6288 stride2x2 = 0x20;
6289 }
6290
6291 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
6292 shrl(cnt2, 1);
6293 }
6294 // Compute the minimum of the string lengths and the
6295 // difference of the string lengths (stack).
6296 // Do the conditional move stuff
6297 movl(result, cnt1);
6298 subl(cnt1, cnt2);
6299 push(cnt1);
6300 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
6301
6302 // Is the minimum length zero?
6303 testl(cnt2, cnt2);
6304 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6305 if (ae == StrIntrinsicNode::LL) {
6306 // Load first bytes
6307 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
6308 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
6309 } else if (ae == StrIntrinsicNode::UU) {
6310 // Load first characters
6311 load_unsigned_short(result, Address(str1, 0));
6312 load_unsigned_short(cnt1, Address(str2, 0));
6313 } else {
6314 load_unsigned_byte(result, Address(str1, 0));
6315 load_unsigned_short(cnt1, Address(str2, 0));
6316 }
6317 subl(result, cnt1);
6318 jcc(Assembler::notZero, POP_LABEL);
6319
6320 if (ae == StrIntrinsicNode::UU) {
6321 // Divide length by 2 to get number of chars
6322 shrl(cnt2, 1);
6323 }
6324 cmpl(cnt2, 1);
6325 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6326
6327 // Check if the strings start at the same location and setup scale and stride
6328 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6329 cmpptr(str1, str2);
6330 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6331 if (ae == StrIntrinsicNode::LL) {
6332 scale = Address::times_1;
6333 stride = 16;
6334 } else {
6335 scale = Address::times_2;
6336 stride = 8;
6337 }
6338 } else {
6339 scale1 = Address::times_1;
6340 scale2 = Address::times_2;
6341 // scale not used
6342 stride = 8;
6343 }
6344
6345 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6346 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6347 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6348 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
6349 Label COMPARE_TAIL_LONG;
6350 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
6351
6352 int pcmpmask = 0x19;
6353 if (ae == StrIntrinsicNode::LL) {
6354 pcmpmask &= ~0x01;
6355 }
6356
6357 // Setup to compare 16-chars (32-bytes) vectors,
6358 // start from first character again because it has aligned address.
6359 if (ae == StrIntrinsicNode::LL) {
6360 stride2 = 32;
6361 } else {
6362 stride2 = 16;
6363 }
6364 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6365 adr_stride = stride << scale;
6366 } else {
6367 adr_stride1 = 8; //stride << scale1;
6368 adr_stride2 = 16; //stride << scale2;
6369 }
6370
6371 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6372 // rax and rdx are used by pcmpestri as elements counters
6373 movl(result, cnt2);
6374 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6375 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6376
6377 // fast path : compare first 2 8-char vectors.
6378 bind(COMPARE_16_CHARS);
6379 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6380 movdqu(vec1, Address(str1, 0));
6381 } else {
6382 pmovzxbw(vec1, Address(str1, 0));
6383 }
6384 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6385 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6386
6387 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6388 movdqu(vec1, Address(str1, adr_stride));
6389 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6390 } else {
6391 pmovzxbw(vec1, Address(str1, adr_stride1));
6392 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
6393 }
6394 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6395 addl(cnt1, stride);
6396
6397 // Compare the characters at index in cnt1
6398 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
6399 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6400 subl(result, cnt2);
6401 jmp(POP_LABEL);
6402
6403 // Setup the registers to start vector comparison loop
6404 bind(COMPARE_WIDE_VECTORS);
6405 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6406 lea(str1, Address(str1, result, scale));
6407 lea(str2, Address(str2, result, scale));
6408 } else {
6409 lea(str1, Address(str1, result, scale1));
6410 lea(str2, Address(str2, result, scale2));
6411 }
6412 subl(result, stride2);
6413 subl(cnt2, stride2);
6414 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
6415 negptr(result);
6416
6417 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6418 bind(COMPARE_WIDE_VECTORS_LOOP);
6419
6420 #ifdef _LP64
6421 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
6422 cmpl(cnt2, stride2x2);
6423 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
6424 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
6425 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
6426
6427 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
6428 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6429 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
6430 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6431 } else {
6432 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
6433 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6434 }
6435 kortestql(k7, k7);
6436 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
6437 addptr(result, stride2x2); // update since we already compared at this addr
6438 subl(cnt2, stride2x2); // and sub the size too
6439 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
6440
6441 vpxor(vec1, vec1);
6442 jmpb(COMPARE_WIDE_TAIL);
6443 }//if (VM_Version::supports_avx512vlbw())
6444 #endif // _LP64
6445
6446
6447 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6448 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6449 vmovdqu(vec1, Address(str1, result, scale));
6450 vpxor(vec1, Address(str2, result, scale));
6451 } else {
6452 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
6453 vpxor(vec1, Address(str2, result, scale2));
6454 }
6455 vptest(vec1, vec1);
6456 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
6457 addptr(result, stride2);
6458 subl(cnt2, stride2);
6459 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6460 // clean upper bits of YMM registers
6461 vpxor(vec1, vec1);
6462
6463 // compare wide vectors tail
6464 bind(COMPARE_WIDE_TAIL);
6465 testptr(result, result);
6466 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6467
6468 movl(result, stride2);
6469 movl(cnt2, result);
6470 negptr(result);
6471 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6472
6473 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6474 bind(VECTOR_NOT_EQUAL);
6475 // clean upper bits of YMM registers
6476 vpxor(vec1, vec1);
6477 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6478 lea(str1, Address(str1, result, scale));
6479 lea(str2, Address(str2, result, scale));
6480 } else {
6481 lea(str1, Address(str1, result, scale1));
6482 lea(str2, Address(str2, result, scale2));
6483 }
6484 jmp(COMPARE_16_CHARS);
6485
6486 // Compare tail chars, length between 1 to 15 chars
6487 bind(COMPARE_TAIL_LONG);
6488 movl(cnt2, result);
6489 cmpl(cnt2, stride);
6490 jcc(Assembler::less, COMPARE_SMALL_STR);
6491
6492 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6493 movdqu(vec1, Address(str1, 0));
6494 } else {
6495 pmovzxbw(vec1, Address(str1, 0));
6496 }
6497 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6498 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6499 subptr(cnt2, stride);
6500 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6501 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6502 lea(str1, Address(str1, result, scale));
6503 lea(str2, Address(str2, result, scale));
6504 } else {
6505 lea(str1, Address(str1, result, scale1));
6506 lea(str2, Address(str2, result, scale2));
6507 }
6508 negptr(cnt2);
6509 jmpb(WHILE_HEAD_LABEL);
6510
6511 bind(COMPARE_SMALL_STR);
6512 } else if (UseSSE42Intrinsics) {
6513 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6514 int pcmpmask = 0x19;
6515 // Setup to compare 8-char (16-byte) vectors,
6516 // start from first character again because it has aligned address.
6517 movl(result, cnt2);
6518 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6519 if (ae == StrIntrinsicNode::LL) {
6520 pcmpmask &= ~0x01;
6521 }
6522 jcc(Assembler::zero, COMPARE_TAIL);
6523 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6524 lea(str1, Address(str1, result, scale));
6525 lea(str2, Address(str2, result, scale));
6526 } else {
6527 lea(str1, Address(str1, result, scale1));
6528 lea(str2, Address(str2, result, scale2));
6529 }
6530 negptr(result);
6531
6532 // pcmpestri
6533 // inputs:
6534 // vec1- substring
6535 // rax - negative string length (elements count)
6536 // mem - scanned string
6537 // rdx - string length (elements count)
6538 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6539 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6540 // outputs:
6541 // rcx - first mismatched element index
6542 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6543
6544 bind(COMPARE_WIDE_VECTORS);
6545 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6546 movdqu(vec1, Address(str1, result, scale));
6547 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6548 } else {
6549 pmovzxbw(vec1, Address(str1, result, scale1));
6550 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6551 }
6552 // After pcmpestri cnt1(rcx) contains mismatched element index
6553
6554 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6555 addptr(result, stride);
6556 subptr(cnt2, stride);
6557 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6558
6559 // compare wide vectors tail
6560 testptr(result, result);
6561 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6562
6563 movl(cnt2, stride);
6564 movl(result, stride);
6565 negptr(result);
6566 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6567 movdqu(vec1, Address(str1, result, scale));
6568 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6569 } else {
6570 pmovzxbw(vec1, Address(str1, result, scale1));
6571 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6572 }
6573 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6574
6575 // Mismatched characters in the vectors
6576 bind(VECTOR_NOT_EQUAL);
6577 addptr(cnt1, result);
6578 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6579 subl(result, cnt2);
6580 jmpb(POP_LABEL);
6581
6582 bind(COMPARE_TAIL); // limit is zero
6583 movl(cnt2, result);
6584 // Fallthru to tail compare
6585 }
6586 // Shift str2 and str1 to the end of the arrays, negate min
6587 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6588 lea(str1, Address(str1, cnt2, scale));
6589 lea(str2, Address(str2, cnt2, scale));
6590 } else {
6591 lea(str1, Address(str1, cnt2, scale1));
6592 lea(str2, Address(str2, cnt2, scale2));
6593 }
6594 decrementl(cnt2); // first character was compared already
6595 negptr(cnt2);
6596
6597 // Compare the rest of the elements
6598 bind(WHILE_HEAD_LABEL);
6599 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
6600 subl(result, cnt1);
6601 jccb(Assembler::notZero, POP_LABEL);
6602 increment(cnt2);
6603 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6604
6605 // Strings are equal up to min length. Return the length difference.
6606 bind(LENGTH_DIFF_LABEL);
6607 pop(result);
6608 if (ae == StrIntrinsicNode::UU) {
6609 // Divide diff by 2 to get number of chars
6610 sarl(result, 1);
6611 }
6612 jmpb(DONE_LABEL);
6613
6614 #ifdef _LP64
6615 if (VM_Version::supports_avx512vlbw()) {
6616
6617 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
6618
6619 kmovql(cnt1, k7);
6620 notq(cnt1);
6621 bsfq(cnt2, cnt1);
6622 if (ae != StrIntrinsicNode::LL) {
6623 // Divide diff by 2 to get number of chars
6624 sarl(cnt2, 1);
6625 }
6626 addq(result, cnt2);
6627 if (ae == StrIntrinsicNode::LL) {
6628 load_unsigned_byte(cnt1, Address(str2, result));
6629 load_unsigned_byte(result, Address(str1, result));
6630 } else if (ae == StrIntrinsicNode::UU) {
6631 load_unsigned_short(cnt1, Address(str2, result, scale));
6632 load_unsigned_short(result, Address(str1, result, scale));
6633 } else {
6634 load_unsigned_short(cnt1, Address(str2, result, scale2));
6635 load_unsigned_byte(result, Address(str1, result, scale1));
6636 }
6637 subl(result, cnt1);
6638 jmpb(POP_LABEL);
6639 }//if (VM_Version::supports_avx512vlbw())
6640 #endif // _LP64
6641
6642 // Discard the stored length difference
6643 bind(POP_LABEL);
6644 pop(cnt1);
6645
6646 // That's it
6647 bind(DONE_LABEL);
6648 if(ae == StrIntrinsicNode::UL) {
6649 negl(result);
6650 }
6651
6652 }
6653
6654 // Search for Non-ASCII character (Negative byte value) in a byte array,
6655 // return true if it has any and false otherwise.
6656 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
6657 // @HotSpotIntrinsicCandidate
6658 // private static boolean hasNegatives(byte[] ba, int off, int len) {
6659 // for (int i = off; i < off + len; i++) {
6660 // if (ba[i] < 0) {
6661 // return true;
6662 // }
6663 // }
6664 // return false;
6665 // }
6666 void MacroAssembler::has_negatives(Register ary1, Register len,
6667 Register result, Register tmp1,
6668 XMMRegister vec1, XMMRegister vec2) {
6669 // rsi: byte array
6670 // rcx: len
6671 // rax: result
6672 ShortBranchVerifier sbv(this);
6673 assert_different_registers(ary1, len, result, tmp1);
6674 assert_different_registers(vec1, vec2);
6675 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
6676
6677 // len == 0
6678 testl(len, len);
6679 jcc(Assembler::zero, FALSE_LABEL);
6680
6681 if ((UseAVX > 2) && // AVX512
6682 VM_Version::supports_avx512vlbw() &&
6683 VM_Version::supports_bmi2()) {
6684
6685 Label test_64_loop, test_tail;
6686 Register tmp3_aliased = len;
6687
6688 movl(tmp1, len);
6689 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
6690
6691 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
6692 andl(len, ~(64 - 1)); // vector count (in chars)
6693 jccb(Assembler::zero, test_tail);
6694
6695 lea(ary1, Address(ary1, len, Address::times_1));
6696 negptr(len);
6697
6698 bind(test_64_loop);
6699 // Check whether our 64 elements of size byte contain negatives
6700 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
6701 kortestql(k2, k2);
6702 jcc(Assembler::notZero, TRUE_LABEL);
6703
6704 addptr(len, 64);
6705 jccb(Assembler::notZero, test_64_loop);
6706
6707
6708 bind(test_tail);
6709 // bail out when there is nothing to be done
6710 testl(tmp1, -1);
6711 jcc(Assembler::zero, FALSE_LABEL);
6712
6713 // ~(~0 << len) applied up to two times (for 32-bit scenario)
6714 #ifdef _LP64
6715 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
6716 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
6717 notq(tmp3_aliased);
6718 kmovql(k3, tmp3_aliased);
6719 #else
6720 Label k_init;
6721 jmp(k_init);
6722
6723 // We could not read 64-bits from a general purpose register thus we move
6724 // data required to compose 64 1's to the instruction stream
6725 // We emit 64 byte wide series of elements from 0..63 which later on would
6726 // be used as a compare targets with tail count contained in tmp1 register.
6727 // Result would be a k register having tmp1 consecutive number or 1
6728 // counting from least significant bit.
6729 address tmp = pc();
6730 emit_int64(0x0706050403020100);
6731 emit_int64(0x0F0E0D0C0B0A0908);
6732 emit_int64(0x1716151413121110);
6733 emit_int64(0x1F1E1D1C1B1A1918);
6734 emit_int64(0x2726252423222120);
6735 emit_int64(0x2F2E2D2C2B2A2928);
6736 emit_int64(0x3736353433323130);
6737 emit_int64(0x3F3E3D3C3B3A3938);
6738
6739 bind(k_init);
6740 lea(len, InternalAddress(tmp));
6741 // create mask to test for negative byte inside a vector
6742 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
6743 evpcmpgtb(k3, vec1, Address(len, 0), Assembler::AVX_512bit);
6744
6745 #endif
6746 evpcmpgtb(k2, k3, vec2, Address(ary1, 0), Assembler::AVX_512bit);
6747 ktestq(k2, k3);
6748 jcc(Assembler::notZero, TRUE_LABEL);
6749
6750 jmp(FALSE_LABEL);
6751 } else {
6752 movl(result, len); // copy
6753
6754 if (UseAVX == 2 && UseSSE >= 2) {
6755 // With AVX2, use 32-byte vector compare
6756 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6757
6758 // Compare 32-byte vectors
6759 andl(result, 0x0000001f); // tail count (in bytes)
6760 andl(len, 0xffffffe0); // vector count (in bytes)
6761 jccb(Assembler::zero, COMPARE_TAIL);
6762
6763 lea(ary1, Address(ary1, len, Address::times_1));
6764 negptr(len);
6765
6766 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
6767 movdl(vec2, tmp1);
6768 vpbroadcastd(vec2, vec2, Assembler::AVX_256bit);
6769
6770 bind(COMPARE_WIDE_VECTORS);
6771 vmovdqu(vec1, Address(ary1, len, Address::times_1));
6772 vptest(vec1, vec2);
6773 jccb(Assembler::notZero, TRUE_LABEL);
6774 addptr(len, 32);
6775 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6776
6777 testl(result, result);
6778 jccb(Assembler::zero, FALSE_LABEL);
6779
6780 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6781 vptest(vec1, vec2);
6782 jccb(Assembler::notZero, TRUE_LABEL);
6783 jmpb(FALSE_LABEL);
6784
6785 bind(COMPARE_TAIL); // len is zero
6786 movl(len, result);
6787 // Fallthru to tail compare
6788 } else if (UseSSE42Intrinsics) {
6789 // With SSE4.2, use double quad vector compare
6790 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6791
6792 // Compare 16-byte vectors
6793 andl(result, 0x0000000f); // tail count (in bytes)
6794 andl(len, 0xfffffff0); // vector count (in bytes)
6795 jcc(Assembler::zero, COMPARE_TAIL);
6796
6797 lea(ary1, Address(ary1, len, Address::times_1));
6798 negptr(len);
6799
6800 movl(tmp1, 0x80808080);
6801 movdl(vec2, tmp1);
6802 pshufd(vec2, vec2, 0);
6803
6804 bind(COMPARE_WIDE_VECTORS);
6805 movdqu(vec1, Address(ary1, len, Address::times_1));
6806 ptest(vec1, vec2);
6807 jcc(Assembler::notZero, TRUE_LABEL);
6808 addptr(len, 16);
6809 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6810
6811 testl(result, result);
6812 jcc(Assembler::zero, FALSE_LABEL);
6813
6814 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
6815 ptest(vec1, vec2);
6816 jccb(Assembler::notZero, TRUE_LABEL);
6817 jmpb(FALSE_LABEL);
6818
6819 bind(COMPARE_TAIL); // len is zero
6820 movl(len, result);
6821 // Fallthru to tail compare
6822 }
6823 }
6824 // Compare 4-byte vectors
6825 andl(len, 0xfffffffc); // vector count (in bytes)
6826 jccb(Assembler::zero, COMPARE_CHAR);
6827
6828 lea(ary1, Address(ary1, len, Address::times_1));
6829 negptr(len);
6830
6831 bind(COMPARE_VECTORS);
6832 movl(tmp1, Address(ary1, len, Address::times_1));
6833 andl(tmp1, 0x80808080);
6834 jccb(Assembler::notZero, TRUE_LABEL);
6835 addptr(len, 4);
6836 jcc(Assembler::notZero, COMPARE_VECTORS);
6837
6838 // Compare trailing char (final 2 bytes), if any
6839 bind(COMPARE_CHAR);
6840 testl(result, 0x2); // tail char
6841 jccb(Assembler::zero, COMPARE_BYTE);
6842 load_unsigned_short(tmp1, Address(ary1, 0));
6843 andl(tmp1, 0x00008080);
6844 jccb(Assembler::notZero, TRUE_LABEL);
6845 subptr(result, 2);
6846 lea(ary1, Address(ary1, 2));
6847
6848 bind(COMPARE_BYTE);
6849 testl(result, 0x1); // tail byte
6850 jccb(Assembler::zero, FALSE_LABEL);
6851 load_unsigned_byte(tmp1, Address(ary1, 0));
6852 andl(tmp1, 0x00000080);
6853 jccb(Assembler::notEqual, TRUE_LABEL);
6854 jmpb(FALSE_LABEL);
6855
6856 bind(TRUE_LABEL);
6857 movl(result, 1); // return true
6858 jmpb(DONE);
6859
6860 bind(FALSE_LABEL);
6861 xorl(result, result); // return false
6862
6863 // That's it
6864 bind(DONE);
6865 if (UseAVX >= 2 && UseSSE >= 2) {
6866 // clean upper bits of YMM registers
6867 vpxor(vec1, vec1);
6868 vpxor(vec2, vec2);
6869 }
6870 }
6871 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
6872 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
6873 Register limit, Register result, Register chr,
6874 XMMRegister vec1, XMMRegister vec2, bool is_char) {
6875 ShortBranchVerifier sbv(this);
6876 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
6877
6878 int length_offset = arrayOopDesc::length_offset_in_bytes();
6879 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
6880
6881 if (is_array_equ) {
6882 // Check the input args
6883 cmpoop(ary1, ary2);
6884 jcc(Assembler::equal, TRUE_LABEL);
6885
6886 // Need additional checks for arrays_equals.
6887 testptr(ary1, ary1);
6888 jcc(Assembler::zero, FALSE_LABEL);
6889 testptr(ary2, ary2);
6890 jcc(Assembler::zero, FALSE_LABEL);
6891
6892 // Check the lengths
6893 movl(limit, Address(ary1, length_offset));
6894 cmpl(limit, Address(ary2, length_offset));
6895 jcc(Assembler::notEqual, FALSE_LABEL);
6896 }
6897
6898 // count == 0
6899 testl(limit, limit);
6900 jcc(Assembler::zero, TRUE_LABEL);
6901
6902 if (is_array_equ) {
6903 // Load array address
6904 lea(ary1, Address(ary1, base_offset));
6905 lea(ary2, Address(ary2, base_offset));
6906 }
6907
6908 if (is_array_equ && is_char) {
6909 // arrays_equals when used for char[].
6910 shll(limit, 1); // byte count != 0
6911 }
6912 movl(result, limit); // copy
6913
6914 if (UseAVX >= 2) {
6915 // With AVX2, use 32-byte vector compare
6916 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6917
6918 // Compare 32-byte vectors
6919 andl(result, 0x0000001f); // tail count (in bytes)
6920 andl(limit, 0xffffffe0); // vector count (in bytes)
6921 jcc(Assembler::zero, COMPARE_TAIL);
6922
6923 lea(ary1, Address(ary1, limit, Address::times_1));
6924 lea(ary2, Address(ary2, limit, Address::times_1));
6925 negptr(limit);
6926
6927 bind(COMPARE_WIDE_VECTORS);
6928
6929 #ifdef _LP64
6930 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
6931 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
6932
6933 cmpl(limit, -64);
6934 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
6935
6936 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
6937
6938 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
6939 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
6940 kortestql(k7, k7);
6941 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
6942 addptr(limit, 64); // update since we already compared at this addr
6943 cmpl(limit, -64);
6944 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
6945
6946 // At this point we may still need to compare -limit+result bytes.
6947 // We could execute the next two instruction and just continue via non-wide path:
6948 // cmpl(limit, 0);
6949 // jcc(Assembler::equal, COMPARE_TAIL); // true
6950 // But since we stopped at the points ary{1,2}+limit which are
6951 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
6952 // (|limit| <= 32 and result < 32),
6953 // we may just compare the last 64 bytes.
6954 //
6955 addptr(result, -64); // it is safe, bc we just came from this area
6956 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
6957 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
6958 kortestql(k7, k7);
6959 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
6960
6961 jmp(TRUE_LABEL);
6962
6963 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6964
6965 }//if (VM_Version::supports_avx512vlbw())
6966 #endif //_LP64
6967
6968 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
6969 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
6970 vpxor(vec1, vec2);
6971
6972 vptest(vec1, vec1);
6973 jcc(Assembler::notZero, FALSE_LABEL);
6974 addptr(limit, 32);
6975 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6976
6977 testl(result, result);
6978 jcc(Assembler::zero, TRUE_LABEL);
6979
6980 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6981 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
6982 vpxor(vec1, vec2);
6983
6984 vptest(vec1, vec1);
6985 jccb(Assembler::notZero, FALSE_LABEL);
6986 jmpb(TRUE_LABEL);
6987
6988 bind(COMPARE_TAIL); // limit is zero
6989 movl(limit, result);
6990 // Fallthru to tail compare
6991 } else if (UseSSE42Intrinsics) {
6992 // With SSE4.2, use double quad vector compare
6993 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6994
6995 // Compare 16-byte vectors
6996 andl(result, 0x0000000f); // tail count (in bytes)
6997 andl(limit, 0xfffffff0); // vector count (in bytes)
6998 jcc(Assembler::zero, COMPARE_TAIL);
6999
7000 lea(ary1, Address(ary1, limit, Address::times_1));
7001 lea(ary2, Address(ary2, limit, Address::times_1));
7002 negptr(limit);
7003
7004 bind(COMPARE_WIDE_VECTORS);
7005 movdqu(vec1, Address(ary1, limit, Address::times_1));
7006 movdqu(vec2, Address(ary2, limit, Address::times_1));
7007 pxor(vec1, vec2);
7008
7009 ptest(vec1, vec1);
7010 jcc(Assembler::notZero, FALSE_LABEL);
7011 addptr(limit, 16);
7012 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7013
7014 testl(result, result);
7015 jcc(Assembler::zero, TRUE_LABEL);
7016
7017 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7018 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
7019 pxor(vec1, vec2);
7020
7021 ptest(vec1, vec1);
7022 jccb(Assembler::notZero, FALSE_LABEL);
7023 jmpb(TRUE_LABEL);
7024
7025 bind(COMPARE_TAIL); // limit is zero
7026 movl(limit, result);
7027 // Fallthru to tail compare
7028 }
7029
7030 // Compare 4-byte vectors
7031 andl(limit, 0xfffffffc); // vector count (in bytes)
7032 jccb(Assembler::zero, COMPARE_CHAR);
7033
7034 lea(ary1, Address(ary1, limit, Address::times_1));
7035 lea(ary2, Address(ary2, limit, Address::times_1));
7036 negptr(limit);
7037
7038 bind(COMPARE_VECTORS);
7039 movl(chr, Address(ary1, limit, Address::times_1));
7040 cmpl(chr, Address(ary2, limit, Address::times_1));
7041 jccb(Assembler::notEqual, FALSE_LABEL);
7042 addptr(limit, 4);
7043 jcc(Assembler::notZero, COMPARE_VECTORS);
7044
7045 // Compare trailing char (final 2 bytes), if any
7046 bind(COMPARE_CHAR);
7047 testl(result, 0x2); // tail char
7048 jccb(Assembler::zero, COMPARE_BYTE);
7049 load_unsigned_short(chr, Address(ary1, 0));
7050 load_unsigned_short(limit, Address(ary2, 0));
7051 cmpl(chr, limit);
7052 jccb(Assembler::notEqual, FALSE_LABEL);
7053
7054 if (is_array_equ && is_char) {
7055 bind(COMPARE_BYTE);
7056 } else {
7057 lea(ary1, Address(ary1, 2));
7058 lea(ary2, Address(ary2, 2));
7059
7060 bind(COMPARE_BYTE);
7061 testl(result, 0x1); // tail byte
7062 jccb(Assembler::zero, TRUE_LABEL);
7063 load_unsigned_byte(chr, Address(ary1, 0));
7064 load_unsigned_byte(limit, Address(ary2, 0));
7065 cmpl(chr, limit);
7066 jccb(Assembler::notEqual, FALSE_LABEL);
7067 }
7068 bind(TRUE_LABEL);
7069 movl(result, 1); // return true
7070 jmpb(DONE);
7071
7072 bind(FALSE_LABEL);
7073 xorl(result, result); // return false
7074
7075 // That's it
7076 bind(DONE);
7077 if (UseAVX >= 2) {
7078 // clean upper bits of YMM registers
7079 vpxor(vec1, vec1);
7080 vpxor(vec2, vec2);
7081 }
7082 }
7083
7084 #endif
7085
7086 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7087 Register to, Register value, Register count,
7088 Register rtmp, XMMRegister xtmp) {
7089 ShortBranchVerifier sbv(this);
7090 assert_different_registers(to, value, count, rtmp);
7091 Label L_exit;
7092 Label L_fill_2_bytes, L_fill_4_bytes;
7093
7094 int shift = -1;
7095 switch (t) {
7096 case T_BYTE:
7097 shift = 2;
7098 break;
7099 case T_SHORT:
7100 shift = 1;
7101 break;
7102 case T_INT:
7103 shift = 0;
7104 break;
7105 default: ShouldNotReachHere();
7106 }
7107
7108 if (t == T_BYTE) {
7109 andl(value, 0xff);
7110 movl(rtmp, value);
7111 shll(rtmp, 8);
7112 orl(value, rtmp);
7113 }
7114 if (t == T_SHORT) {
7115 andl(value, 0xffff);
7116 }
7117 if (t == T_BYTE || t == T_SHORT) {
7118 movl(rtmp, value);
7119 shll(rtmp, 16);
7120 orl(value, rtmp);
7121 }
7122
7123 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7124 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7125 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7126 Label L_skip_align2;
7127 // align source address at 4 bytes address boundary
7128 if (t == T_BYTE) {
7129 Label L_skip_align1;
7130 // One byte misalignment happens only for byte arrays
7131 testptr(to, 1);
7132 jccb(Assembler::zero, L_skip_align1);
7133 movb(Address(to, 0), value);
7134 increment(to);
7135 decrement(count);
7136 BIND(L_skip_align1);
7137 }
7138 // Two bytes misalignment happens only for byte and short (char) arrays
7139 testptr(to, 2);
7140 jccb(Assembler::zero, L_skip_align2);
7141 movw(Address(to, 0), value);
7142 addptr(to, 2);
7143 subl(count, 1<<(shift-1));
7144 BIND(L_skip_align2);
7145 }
7146 if (UseSSE < 2) {
7147 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7148 // Fill 32-byte chunks
7149 subl(count, 8 << shift);
7150 jcc(Assembler::less, L_check_fill_8_bytes);
7151 align(16);
7152
7153 BIND(L_fill_32_bytes_loop);
7154
7155 for (int i = 0; i < 32; i += 4) {
7156 movl(Address(to, i), value);
7157 }
7158
7159 addptr(to, 32);
7160 subl(count, 8 << shift);
7161 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7162 BIND(L_check_fill_8_bytes);
7163 addl(count, 8 << shift);
7164 jccb(Assembler::zero, L_exit);
7165 jmpb(L_fill_8_bytes);
7166
7167 //
7168 // length is too short, just fill qwords
7169 //
7170 BIND(L_fill_8_bytes_loop);
7171 movl(Address(to, 0), value);
7172 movl(Address(to, 4), value);
7173 addptr(to, 8);
7174 BIND(L_fill_8_bytes);
7175 subl(count, 1 << (shift + 1));
7176 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7177 // fall through to fill 4 bytes
7178 } else {
7179 Label L_fill_32_bytes;
7180 if (!UseUnalignedLoadStores) {
7181 // align to 8 bytes, we know we are 4 byte aligned to start
7182 testptr(to, 4);
7183 jccb(Assembler::zero, L_fill_32_bytes);
7184 movl(Address(to, 0), value);
7185 addptr(to, 4);
7186 subl(count, 1<<shift);
7187 }
7188 BIND(L_fill_32_bytes);
7189 {
7190 assert( UseSSE >= 2, "supported cpu only" );
7191 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7192 movdl(xtmp, value);
7193 if (UseAVX > 2 && UseUnalignedLoadStores) {
7194 // Fill 64-byte chunks
7195 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7196 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
7197
7198 subl(count, 16 << shift);
7199 jcc(Assembler::less, L_check_fill_32_bytes);
7200 align(16);
7201
7202 BIND(L_fill_64_bytes_loop);
7203 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
7204 addptr(to, 64);
7205 subl(count, 16 << shift);
7206 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7207
7208 BIND(L_check_fill_32_bytes);
7209 addl(count, 8 << shift);
7210 jccb(Assembler::less, L_check_fill_8_bytes);
7211 vmovdqu(Address(to, 0), xtmp);
7212 addptr(to, 32);
7213 subl(count, 8 << shift);
7214
7215 BIND(L_check_fill_8_bytes);
7216 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
7217 // Fill 64-byte chunks
7218 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7219 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
7220
7221 subl(count, 16 << shift);
7222 jcc(Assembler::less, L_check_fill_32_bytes);
7223 align(16);
7224
7225 BIND(L_fill_64_bytes_loop);
7226 vmovdqu(Address(to, 0), xtmp);
7227 vmovdqu(Address(to, 32), xtmp);
7228 addptr(to, 64);
7229 subl(count, 16 << shift);
7230 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7231
7232 BIND(L_check_fill_32_bytes);
7233 addl(count, 8 << shift);
7234 jccb(Assembler::less, L_check_fill_8_bytes);
7235 vmovdqu(Address(to, 0), xtmp);
7236 addptr(to, 32);
7237 subl(count, 8 << shift);
7238
7239 BIND(L_check_fill_8_bytes);
7240 // clean upper bits of YMM registers
7241 movdl(xtmp, value);
7242 pshufd(xtmp, xtmp, 0);
7243 } else {
7244 // Fill 32-byte chunks
7245 pshufd(xtmp, xtmp, 0);
7246
7247 subl(count, 8 << shift);
7248 jcc(Assembler::less, L_check_fill_8_bytes);
7249 align(16);
7250
7251 BIND(L_fill_32_bytes_loop);
7252
7253 if (UseUnalignedLoadStores) {
7254 movdqu(Address(to, 0), xtmp);
7255 movdqu(Address(to, 16), xtmp);
7256 } else {
7257 movq(Address(to, 0), xtmp);
7258 movq(Address(to, 8), xtmp);
7259 movq(Address(to, 16), xtmp);
7260 movq(Address(to, 24), xtmp);
7261 }
7262
7263 addptr(to, 32);
7264 subl(count, 8 << shift);
7265 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7266
7267 BIND(L_check_fill_8_bytes);
7268 }
7269 addl(count, 8 << shift);
7270 jccb(Assembler::zero, L_exit);
7271 jmpb(L_fill_8_bytes);
7272
7273 //
7274 // length is too short, just fill qwords
7275 //
7276 BIND(L_fill_8_bytes_loop);
7277 movq(Address(to, 0), xtmp);
7278 addptr(to, 8);
7279 BIND(L_fill_8_bytes);
7280 subl(count, 1 << (shift + 1));
7281 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7282 }
7283 }
7284 // fill trailing 4 bytes
7285 BIND(L_fill_4_bytes);
7286 testl(count, 1<<shift);
7287 jccb(Assembler::zero, L_fill_2_bytes);
7288 movl(Address(to, 0), value);
7289 if (t == T_BYTE || t == T_SHORT) {
7290 Label L_fill_byte;
7291 addptr(to, 4);
7292 BIND(L_fill_2_bytes);
7293 // fill trailing 2 bytes
7294 testl(count, 1<<(shift-1));
7295 jccb(Assembler::zero, L_fill_byte);
7296 movw(Address(to, 0), value);
7297 if (t == T_BYTE) {
7298 addptr(to, 2);
7299 BIND(L_fill_byte);
7300 // fill trailing byte
7301 testl(count, 1);
7302 jccb(Assembler::zero, L_exit);
7303 movb(Address(to, 0), value);
7304 } else {
7305 BIND(L_fill_byte);
7306 }
7307 } else {
7308 BIND(L_fill_2_bytes);
7309 }
7310 BIND(L_exit);
7311 }
7312
7313 // encode char[] to byte[] in ISO_8859_1
7314 //@HotSpotIntrinsicCandidate
7315 //private static int implEncodeISOArray(byte[] sa, int sp,
7316 //byte[] da, int dp, int len) {
7317 // int i = 0;
7318 // for (; i < len; i++) {
7319 // char c = StringUTF16.getChar(sa, sp++);
7320 // if (c > '\u00FF')
7321 // break;
7322 // da[dp++] = (byte)c;
7323 // }
7324 // return i;
7325 //}
7326 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7327 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7328 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7329 Register tmp5, Register result) {
7330
7331 // rsi: src
7332 // rdi: dst
7333 // rdx: len
7334 // rcx: tmp5
7335 // rax: result
7336 ShortBranchVerifier sbv(this);
7337 assert_different_registers(src, dst, len, tmp5, result);
7338 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7339
7340 // set result
7341 xorl(result, result);
7342 // check for zero length
7343 testl(len, len);
7344 jcc(Assembler::zero, L_done);
7345
7346 movl(result, len);
7347
7348 // Setup pointers
7349 lea(src, Address(src, len, Address::times_2)); // char[]
7350 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7351 negptr(len);
7352
7353 if (UseSSE42Intrinsics || UseAVX >= 2) {
7354 Label L_copy_8_chars, L_copy_8_chars_exit;
7355 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7356
7357 if (UseAVX >= 2) {
7358 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7359 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7360 movdl(tmp1Reg, tmp5);
7361 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7362 jmp(L_chars_32_check);
7363
7364 bind(L_copy_32_chars);
7365 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7366 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7367 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7368 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7369 jccb(Assembler::notZero, L_copy_32_chars_exit);
7370 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7371 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7372 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7373
7374 bind(L_chars_32_check);
7375 addptr(len, 32);
7376 jcc(Assembler::lessEqual, L_copy_32_chars);
7377
7378 bind(L_copy_32_chars_exit);
7379 subptr(len, 16);
7380 jccb(Assembler::greater, L_copy_16_chars_exit);
7381
7382 } else if (UseSSE42Intrinsics) {
7383 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7384 movdl(tmp1Reg, tmp5);
7385 pshufd(tmp1Reg, tmp1Reg, 0);
7386 jmpb(L_chars_16_check);
7387 }
7388
7389 bind(L_copy_16_chars);
7390 if (UseAVX >= 2) {
7391 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7392 vptest(tmp2Reg, tmp1Reg);
7393 jcc(Assembler::notZero, L_copy_16_chars_exit);
7394 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7395 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7396 } else {
7397 if (UseAVX > 0) {
7398 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7399 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7400 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7401 } else {
7402 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7403 por(tmp2Reg, tmp3Reg);
7404 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7405 por(tmp2Reg, tmp4Reg);
7406 }
7407 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7408 jccb(Assembler::notZero, L_copy_16_chars_exit);
7409 packuswb(tmp3Reg, tmp4Reg);
7410 }
7411 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7412
7413 bind(L_chars_16_check);
7414 addptr(len, 16);
7415 jcc(Assembler::lessEqual, L_copy_16_chars);
7416
7417 bind(L_copy_16_chars_exit);
7418 if (UseAVX >= 2) {
7419 // clean upper bits of YMM registers
7420 vpxor(tmp2Reg, tmp2Reg);
7421 vpxor(tmp3Reg, tmp3Reg);
7422 vpxor(tmp4Reg, tmp4Reg);
7423 movdl(tmp1Reg, tmp5);
7424 pshufd(tmp1Reg, tmp1Reg, 0);
7425 }
7426 subptr(len, 8);
7427 jccb(Assembler::greater, L_copy_8_chars_exit);
7428
7429 bind(L_copy_8_chars);
7430 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7431 ptest(tmp3Reg, tmp1Reg);
7432 jccb(Assembler::notZero, L_copy_8_chars_exit);
7433 packuswb(tmp3Reg, tmp1Reg);
7434 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7435 addptr(len, 8);
7436 jccb(Assembler::lessEqual, L_copy_8_chars);
7437
7438 bind(L_copy_8_chars_exit);
7439 subptr(len, 8);
7440 jccb(Assembler::zero, L_done);
7441 }
7442
7443 bind(L_copy_1_char);
7444 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7445 testl(tmp5, 0xff00); // check if Unicode char
7446 jccb(Assembler::notZero, L_copy_1_char_exit);
7447 movb(Address(dst, len, Address::times_1, 0), tmp5);
7448 addptr(len, 1);
7449 jccb(Assembler::less, L_copy_1_char);
7450
7451 bind(L_copy_1_char_exit);
7452 addptr(result, len); // len is negative count of not processed elements
7453
7454 bind(L_done);
7455 }
7456
7457 #ifdef _LP64
7458 /**
7459 * Helper for multiply_to_len().
7460 */
7461 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7462 addq(dest_lo, src1);
7463 adcq(dest_hi, 0);
7464 addq(dest_lo, src2);
7465 adcq(dest_hi, 0);
7466 }
7467
7468 /**
7469 * Multiply 64 bit by 64 bit first loop.
7470 */
7471 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7472 Register y, Register y_idx, Register z,
7473 Register carry, Register product,
7474 Register idx, Register kdx) {
7475 //
7476 // jlong carry, x[], y[], z[];
7477 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7478 // huge_128 product = y[idx] * x[xstart] + carry;
7479 // z[kdx] = (jlong)product;
7480 // carry = (jlong)(product >>> 64);
7481 // }
7482 // z[xstart] = carry;
7483 //
7484
7485 Label L_first_loop, L_first_loop_exit;
7486 Label L_one_x, L_one_y, L_multiply;
7487
7488 decrementl(xstart);
7489 jcc(Assembler::negative, L_one_x);
7490
7491 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7492 rorq(x_xstart, 32); // convert big-endian to little-endian
7493
7494 bind(L_first_loop);
7495 decrementl(idx);
7496 jcc(Assembler::negative, L_first_loop_exit);
7497 decrementl(idx);
7498 jcc(Assembler::negative, L_one_y);
7499 movq(y_idx, Address(y, idx, Address::times_4, 0));
7500 rorq(y_idx, 32); // convert big-endian to little-endian
7501 bind(L_multiply);
7502 movq(product, x_xstart);
7503 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7504 addq(product, carry);
7505 adcq(rdx, 0);
7506 subl(kdx, 2);
7507 movl(Address(z, kdx, Address::times_4, 4), product);
7508 shrq(product, 32);
7509 movl(Address(z, kdx, Address::times_4, 0), product);
7510 movq(carry, rdx);
7511 jmp(L_first_loop);
7512
7513 bind(L_one_y);
7514 movl(y_idx, Address(y, 0));
7515 jmp(L_multiply);
7516
7517 bind(L_one_x);
7518 movl(x_xstart, Address(x, 0));
7519 jmp(L_first_loop);
7520
7521 bind(L_first_loop_exit);
7522 }
7523
7524 /**
7525 * Multiply 64 bit by 64 bit and add 128 bit.
7526 */
7527 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7528 Register yz_idx, Register idx,
7529 Register carry, Register product, int offset) {
7530 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7531 // z[kdx] = (jlong)product;
7532
7533 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7534 rorq(yz_idx, 32); // convert big-endian to little-endian
7535 movq(product, x_xstart);
7536 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7537 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7538 rorq(yz_idx, 32); // convert big-endian to little-endian
7539
7540 add2_with_carry(rdx, product, carry, yz_idx);
7541
7542 movl(Address(z, idx, Address::times_4, offset+4), product);
7543 shrq(product, 32);
7544 movl(Address(z, idx, Address::times_4, offset), product);
7545
7546 }
7547
7548 /**
7549 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7550 */
7551 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7552 Register yz_idx, Register idx, Register jdx,
7553 Register carry, Register product,
7554 Register carry2) {
7555 // jlong carry, x[], y[], z[];
7556 // int kdx = ystart+1;
7557 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7558 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7559 // z[kdx+idx+1] = (jlong)product;
7560 // jlong carry2 = (jlong)(product >>> 64);
7561 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7562 // z[kdx+idx] = (jlong)product;
7563 // carry = (jlong)(product >>> 64);
7564 // }
7565 // idx += 2;
7566 // if (idx > 0) {
7567 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7568 // z[kdx+idx] = (jlong)product;
7569 // carry = (jlong)(product >>> 64);
7570 // }
7571 //
7572
7573 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7574
7575 movl(jdx, idx);
7576 andl(jdx, 0xFFFFFFFC);
7577 shrl(jdx, 2);
7578
7579 bind(L_third_loop);
7580 subl(jdx, 1);
7581 jcc(Assembler::negative, L_third_loop_exit);
7582 subl(idx, 4);
7583
7584 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7585 movq(carry2, rdx);
7586
7587 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7588 movq(carry, rdx);
7589 jmp(L_third_loop);
7590
7591 bind (L_third_loop_exit);
7592
7593 andl (idx, 0x3);
7594 jcc(Assembler::zero, L_post_third_loop_done);
7595
7596 Label L_check_1;
7597 subl(idx, 2);
7598 jcc(Assembler::negative, L_check_1);
7599
7600 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7601 movq(carry, rdx);
7602
7603 bind (L_check_1);
7604 addl (idx, 0x2);
7605 andl (idx, 0x1);
7606 subl(idx, 1);
7607 jcc(Assembler::negative, L_post_third_loop_done);
7608
7609 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7610 movq(product, x_xstart);
7611 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7612 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7613
7614 add2_with_carry(rdx, product, yz_idx, carry);
7615
7616 movl(Address(z, idx, Address::times_4, 0), product);
7617 shrq(product, 32);
7618
7619 shlq(rdx, 32);
7620 orq(product, rdx);
7621 movq(carry, product);
7622
7623 bind(L_post_third_loop_done);
7624 }
7625
7626 /**
7627 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7628 *
7629 */
7630 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7631 Register carry, Register carry2,
7632 Register idx, Register jdx,
7633 Register yz_idx1, Register yz_idx2,
7634 Register tmp, Register tmp3, Register tmp4) {
7635 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7636
7637 // jlong carry, x[], y[], z[];
7638 // int kdx = ystart+1;
7639 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7640 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7641 // jlong carry2 = (jlong)(tmp3 >>> 64);
7642 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7643 // carry = (jlong)(tmp4 >>> 64);
7644 // z[kdx+idx+1] = (jlong)tmp3;
7645 // z[kdx+idx] = (jlong)tmp4;
7646 // }
7647 // idx += 2;
7648 // if (idx > 0) {
7649 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7650 // z[kdx+idx] = (jlong)yz_idx1;
7651 // carry = (jlong)(yz_idx1 >>> 64);
7652 // }
7653 //
7654
7655 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7656
7657 movl(jdx, idx);
7658 andl(jdx, 0xFFFFFFFC);
7659 shrl(jdx, 2);
7660
7661 bind(L_third_loop);
7662 subl(jdx, 1);
7663 jcc(Assembler::negative, L_third_loop_exit);
7664 subl(idx, 4);
7665
7666 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7667 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7668 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7669 rorxq(yz_idx2, yz_idx2, 32);
7670
7671 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7672 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7673
7674 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7675 rorxq(yz_idx1, yz_idx1, 32);
7676 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7677 rorxq(yz_idx2, yz_idx2, 32);
7678
7679 if (VM_Version::supports_adx()) {
7680 adcxq(tmp3, carry);
7681 adoxq(tmp3, yz_idx1);
7682
7683 adcxq(tmp4, tmp);
7684 adoxq(tmp4, yz_idx2);
7685
7686 movl(carry, 0); // does not affect flags
7687 adcxq(carry2, carry);
7688 adoxq(carry2, carry);
7689 } else {
7690 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7691 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7692 }
7693 movq(carry, carry2);
7694
7695 movl(Address(z, idx, Address::times_4, 12), tmp3);
7696 shrq(tmp3, 32);
7697 movl(Address(z, idx, Address::times_4, 8), tmp3);
7698
7699 movl(Address(z, idx, Address::times_4, 4), tmp4);
7700 shrq(tmp4, 32);
7701 movl(Address(z, idx, Address::times_4, 0), tmp4);
7702
7703 jmp(L_third_loop);
7704
7705 bind (L_third_loop_exit);
7706
7707 andl (idx, 0x3);
7708 jcc(Assembler::zero, L_post_third_loop_done);
7709
7710 Label L_check_1;
7711 subl(idx, 2);
7712 jcc(Assembler::negative, L_check_1);
7713
7714 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7715 rorxq(yz_idx1, yz_idx1, 32);
7716 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7717 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7718 rorxq(yz_idx2, yz_idx2, 32);
7719
7720 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7721
7722 movl(Address(z, idx, Address::times_4, 4), tmp3);
7723 shrq(tmp3, 32);
7724 movl(Address(z, idx, Address::times_4, 0), tmp3);
7725 movq(carry, tmp4);
7726
7727 bind (L_check_1);
7728 addl (idx, 0x2);
7729 andl (idx, 0x1);
7730 subl(idx, 1);
7731 jcc(Assembler::negative, L_post_third_loop_done);
7732 movl(tmp4, Address(y, idx, Address::times_4, 0));
7733 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7734 movl(tmp4, Address(z, idx, Address::times_4, 0));
7735
7736 add2_with_carry(carry2, tmp3, tmp4, carry);
7737
7738 movl(Address(z, idx, Address::times_4, 0), tmp3);
7739 shrq(tmp3, 32);
7740
7741 shlq(carry2, 32);
7742 orq(tmp3, carry2);
7743 movq(carry, tmp3);
7744
7745 bind(L_post_third_loop_done);
7746 }
7747
7748 /**
7749 * Code for BigInteger::multiplyToLen() instrinsic.
7750 *
7751 * rdi: x
7752 * rax: xlen
7753 * rsi: y
7754 * rcx: ylen
7755 * r8: z
7756 * r11: zlen
7757 * r12: tmp1
7758 * r13: tmp2
7759 * r14: tmp3
7760 * r15: tmp4
7761 * rbx: tmp5
7762 *
7763 */
7764 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7765 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7766 ShortBranchVerifier sbv(this);
7767 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7768
7769 push(tmp1);
7770 push(tmp2);
7771 push(tmp3);
7772 push(tmp4);
7773 push(tmp5);
7774
7775 push(xlen);
7776 push(zlen);
7777
7778 const Register idx = tmp1;
7779 const Register kdx = tmp2;
7780 const Register xstart = tmp3;
7781
7782 const Register y_idx = tmp4;
7783 const Register carry = tmp5;
7784 const Register product = xlen;
7785 const Register x_xstart = zlen; // reuse register
7786
7787 // First Loop.
7788 //
7789 // final static long LONG_MASK = 0xffffffffL;
7790 // int xstart = xlen - 1;
7791 // int ystart = ylen - 1;
7792 // long carry = 0;
7793 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7794 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7795 // z[kdx] = (int)product;
7796 // carry = product >>> 32;
7797 // }
7798 // z[xstart] = (int)carry;
7799 //
7800
7801 movl(idx, ylen); // idx = ylen;
7802 movl(kdx, zlen); // kdx = xlen+ylen;
7803 xorq(carry, carry); // carry = 0;
7804
7805 Label L_done;
7806
7807 movl(xstart, xlen);
7808 decrementl(xstart);
7809 jcc(Assembler::negative, L_done);
7810
7811 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7812
7813 Label L_second_loop;
7814 testl(kdx, kdx);
7815 jcc(Assembler::zero, L_second_loop);
7816
7817 Label L_carry;
7818 subl(kdx, 1);
7819 jcc(Assembler::zero, L_carry);
7820
7821 movl(Address(z, kdx, Address::times_4, 0), carry);
7822 shrq(carry, 32);
7823 subl(kdx, 1);
7824
7825 bind(L_carry);
7826 movl(Address(z, kdx, Address::times_4, 0), carry);
7827
7828 // Second and third (nested) loops.
7829 //
7830 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7831 // carry = 0;
7832 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7833 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7834 // (z[k] & LONG_MASK) + carry;
7835 // z[k] = (int)product;
7836 // carry = product >>> 32;
7837 // }
7838 // z[i] = (int)carry;
7839 // }
7840 //
7841 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7842
7843 const Register jdx = tmp1;
7844
7845 bind(L_second_loop);
7846 xorl(carry, carry); // carry = 0;
7847 movl(jdx, ylen); // j = ystart+1
7848
7849 subl(xstart, 1); // i = xstart-1;
7850 jcc(Assembler::negative, L_done);
7851
7852 push (z);
7853
7854 Label L_last_x;
7855 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7856 subl(xstart, 1); // i = xstart-1;
7857 jcc(Assembler::negative, L_last_x);
7858
7859 if (UseBMI2Instructions) {
7860 movq(rdx, Address(x, xstart, Address::times_4, 0));
7861 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7862 } else {
7863 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7864 rorq(x_xstart, 32); // convert big-endian to little-endian
7865 }
7866
7867 Label L_third_loop_prologue;
7868 bind(L_third_loop_prologue);
7869
7870 push (x);
7871 push (xstart);
7872 push (ylen);
7873
7874
7875 if (UseBMI2Instructions) {
7876 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7877 } else { // !UseBMI2Instructions
7878 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7879 }
7880
7881 pop(ylen);
7882 pop(xlen);
7883 pop(x);
7884 pop(z);
7885
7886 movl(tmp3, xlen);
7887 addl(tmp3, 1);
7888 movl(Address(z, tmp3, Address::times_4, 0), carry);
7889 subl(tmp3, 1);
7890 jccb(Assembler::negative, L_done);
7891
7892 shrq(carry, 32);
7893 movl(Address(z, tmp3, Address::times_4, 0), carry);
7894 jmp(L_second_loop);
7895
7896 // Next infrequent code is moved outside loops.
7897 bind(L_last_x);
7898 if (UseBMI2Instructions) {
7899 movl(rdx, Address(x, 0));
7900 } else {
7901 movl(x_xstart, Address(x, 0));
7902 }
7903 jmp(L_third_loop_prologue);
7904
7905 bind(L_done);
7906
7907 pop(zlen);
7908 pop(xlen);
7909
7910 pop(tmp5);
7911 pop(tmp4);
7912 pop(tmp3);
7913 pop(tmp2);
7914 pop(tmp1);
7915 }
7916
7917 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7918 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7919 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7920 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7921 Label VECTOR8_TAIL, VECTOR4_TAIL;
7922 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7923 Label SAME_TILL_END, DONE;
7924 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7925
7926 //scale is in rcx in both Win64 and Unix
7927 ShortBranchVerifier sbv(this);
7928
7929 shlq(length);
7930 xorq(result, result);
7931
7932 if ((UseAVX > 2) &&
7933 VM_Version::supports_avx512vlbw()) {
7934 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7935
7936 cmpq(length, 64);
7937 jcc(Assembler::less, VECTOR32_TAIL);
7938 movq(tmp1, length);
7939 andq(tmp1, 0x3F); // tail count
7940 andq(length, ~(0x3F)); //vector count
7941
7942 bind(VECTOR64_LOOP);
7943 // AVX512 code to compare 64 byte vectors.
7944 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7945 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7946 kortestql(k7, k7);
7947 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7948 addq(result, 64);
7949 subq(length, 64);
7950 jccb(Assembler::notZero, VECTOR64_LOOP);
7951
7952 //bind(VECTOR64_TAIL);
7953 testq(tmp1, tmp1);
7954 jcc(Assembler::zero, SAME_TILL_END);
7955
7956 //bind(VECTOR64_TAIL);
7957 // AVX512 code to compare upto 63 byte vectors.
7958 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7959 shlxq(tmp2, tmp2, tmp1);
7960 notq(tmp2);
7961 kmovql(k3, tmp2);
7962
7963 evmovdqub(rymm0, k3, Address(obja, result), Assembler::AVX_512bit);
7964 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7965
7966 ktestql(k7, k3);
7967 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7968
7969 bind(VECTOR64_NOT_EQUAL);
7970 kmovql(tmp1, k7);
7971 notq(tmp1);
7972 tzcntq(tmp1, tmp1);
7973 addq(result, tmp1);
7974 shrq(result);
7975 jmp(DONE);
7976 bind(VECTOR32_TAIL);
7977 }
7978
7979 cmpq(length, 8);
7980 jcc(Assembler::equal, VECTOR8_LOOP);
7981 jcc(Assembler::less, VECTOR4_TAIL);
7982
7983 if (UseAVX >= 2) {
7984 Label VECTOR16_TAIL, VECTOR32_LOOP;
7985
7986 cmpq(length, 16);
7987 jcc(Assembler::equal, VECTOR16_LOOP);
7988 jcc(Assembler::less, VECTOR8_LOOP);
7989
7990 cmpq(length, 32);
7991 jccb(Assembler::less, VECTOR16_TAIL);
7992
7993 subq(length, 32);
7994 bind(VECTOR32_LOOP);
7995 vmovdqu(rymm0, Address(obja, result));
7996 vmovdqu(rymm1, Address(objb, result));
7997 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7998 vptest(rymm2, rymm2);
7999 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
8000 addq(result, 32);
8001 subq(length, 32);
8002 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
8003 addq(length, 32);
8004 jcc(Assembler::equal, SAME_TILL_END);
8005 //falling through if less than 32 bytes left //close the branch here.
8006
8007 bind(VECTOR16_TAIL);
8008 cmpq(length, 16);
8009 jccb(Assembler::less, VECTOR8_TAIL);
8010 bind(VECTOR16_LOOP);
8011 movdqu(rymm0, Address(obja, result));
8012 movdqu(rymm1, Address(objb, result));
8013 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
8014 ptest(rymm2, rymm2);
8015 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8016 addq(result, 16);
8017 subq(length, 16);
8018 jcc(Assembler::equal, SAME_TILL_END);
8019 //falling through if less than 16 bytes left
8020 } else {//regular intrinsics
8021
8022 cmpq(length, 16);
8023 jccb(Assembler::less, VECTOR8_TAIL);
8024
8025 subq(length, 16);
8026 bind(VECTOR16_LOOP);
8027 movdqu(rymm0, Address(obja, result));
8028 movdqu(rymm1, Address(objb, result));
8029 pxor(rymm0, rymm1);
8030 ptest(rymm0, rymm0);
8031 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8032 addq(result, 16);
8033 subq(length, 16);
8034 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
8035 addq(length, 16);
8036 jcc(Assembler::equal, SAME_TILL_END);
8037 //falling through if less than 16 bytes left
8038 }
8039
8040 bind(VECTOR8_TAIL);
8041 cmpq(length, 8);
8042 jccb(Assembler::less, VECTOR4_TAIL);
8043 bind(VECTOR8_LOOP);
8044 movq(tmp1, Address(obja, result));
8045 movq(tmp2, Address(objb, result));
8046 xorq(tmp1, tmp2);
8047 testq(tmp1, tmp1);
8048 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
8049 addq(result, 8);
8050 subq(length, 8);
8051 jcc(Assembler::equal, SAME_TILL_END);
8052 //falling through if less than 8 bytes left
8053
8054 bind(VECTOR4_TAIL);
8055 cmpq(length, 4);
8056 jccb(Assembler::less, BYTES_TAIL);
8057 bind(VECTOR4_LOOP);
8058 movl(tmp1, Address(obja, result));
8059 xorl(tmp1, Address(objb, result));
8060 testl(tmp1, tmp1);
8061 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
8062 addq(result, 4);
8063 subq(length, 4);
8064 jcc(Assembler::equal, SAME_TILL_END);
8065 //falling through if less than 4 bytes left
8066
8067 bind(BYTES_TAIL);
8068 bind(BYTES_LOOP);
8069 load_unsigned_byte(tmp1, Address(obja, result));
8070 load_unsigned_byte(tmp2, Address(objb, result));
8071 xorl(tmp1, tmp2);
8072 testl(tmp1, tmp1);
8073 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8074 decq(length);
8075 jcc(Assembler::zero, SAME_TILL_END);
8076 incq(result);
8077 load_unsigned_byte(tmp1, Address(obja, result));
8078 load_unsigned_byte(tmp2, Address(objb, result));
8079 xorl(tmp1, tmp2);
8080 testl(tmp1, tmp1);
8081 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8082 decq(length);
8083 jcc(Assembler::zero, SAME_TILL_END);
8084 incq(result);
8085 load_unsigned_byte(tmp1, Address(obja, result));
8086 load_unsigned_byte(tmp2, Address(objb, result));
8087 xorl(tmp1, tmp2);
8088 testl(tmp1, tmp1);
8089 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8090 jmp(SAME_TILL_END);
8091
8092 if (UseAVX >= 2) {
8093 bind(VECTOR32_NOT_EQUAL);
8094 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
8095 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
8096 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
8097 vpmovmskb(tmp1, rymm0);
8098 bsfq(tmp1, tmp1);
8099 addq(result, tmp1);
8100 shrq(result);
8101 jmp(DONE);
8102 }
8103
8104 bind(VECTOR16_NOT_EQUAL);
8105 if (UseAVX >= 2) {
8106 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
8107 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
8108 pxor(rymm0, rymm2);
8109 } else {
8110 pcmpeqb(rymm2, rymm2);
8111 pxor(rymm0, rymm1);
8112 pcmpeqb(rymm0, rymm1);
8113 pxor(rymm0, rymm2);
8114 }
8115 pmovmskb(tmp1, rymm0);
8116 bsfq(tmp1, tmp1);
8117 addq(result, tmp1);
8118 shrq(result);
8119 jmpb(DONE);
8120
8121 bind(VECTOR8_NOT_EQUAL);
8122 bind(VECTOR4_NOT_EQUAL);
8123 bsfq(tmp1, tmp1);
8124 shrq(tmp1, 3);
8125 addq(result, tmp1);
8126 bind(BYTES_NOT_EQUAL);
8127 shrq(result);
8128 jmpb(DONE);
8129
8130 bind(SAME_TILL_END);
8131 mov64(result, -1);
8132
8133 bind(DONE);
8134 }
8135
8136 //Helper functions for square_to_len()
8137
8138 /**
8139 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
8140 * Preserves x and z and modifies rest of the registers.
8141 */
8142 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8143 // Perform square and right shift by 1
8144 // Handle odd xlen case first, then for even xlen do the following
8145 // jlong carry = 0;
8146 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
8147 // huge_128 product = x[j:j+1] * x[j:j+1];
8148 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
8149 // z[i+2:i+3] = (jlong)(product >>> 1);
8150 // carry = (jlong)product;
8151 // }
8152
8153 xorq(tmp5, tmp5); // carry
8154 xorq(rdxReg, rdxReg);
8155 xorl(tmp1, tmp1); // index for x
8156 xorl(tmp4, tmp4); // index for z
8157
8158 Label L_first_loop, L_first_loop_exit;
8159
8160 testl(xlen, 1);
8161 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
8162
8163 // Square and right shift by 1 the odd element using 32 bit multiply
8164 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
8165 imulq(raxReg, raxReg);
8166 shrq(raxReg, 1);
8167 adcq(tmp5, 0);
8168 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
8169 incrementl(tmp1);
8170 addl(tmp4, 2);
8171
8172 // Square and right shift by 1 the rest using 64 bit multiply
8173 bind(L_first_loop);
8174 cmpptr(tmp1, xlen);
8175 jccb(Assembler::equal, L_first_loop_exit);
8176
8177 // Square
8178 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
8179 rorq(raxReg, 32); // convert big-endian to little-endian
8180 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
8181
8182 // Right shift by 1 and save carry
8183 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
8184 rcrq(rdxReg, 1);
8185 rcrq(raxReg, 1);
8186 adcq(tmp5, 0);
8187
8188 // Store result in z
8189 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
8190 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
8191
8192 // Update indices for x and z
8193 addl(tmp1, 2);
8194 addl(tmp4, 4);
8195 jmp(L_first_loop);
8196
8197 bind(L_first_loop_exit);
8198 }
8199
8200
8201 /**
8202 * Perform the following multiply add operation using BMI2 instructions
8203 * carry:sum = sum + op1*op2 + carry
8204 * op2 should be in rdx
8205 * op2 is preserved, all other registers are modified
8206 */
8207 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
8208 // assert op2 is rdx
8209 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
8210 addq(sum, carry);
8211 adcq(tmp2, 0);
8212 addq(sum, op1);
8213 adcq(tmp2, 0);
8214 movq(carry, tmp2);
8215 }
8216
8217 /**
8218 * Perform the following multiply add operation:
8219 * carry:sum = sum + op1*op2 + carry
8220 * Preserves op1, op2 and modifies rest of registers
8221 */
8222 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
8223 // rdx:rax = op1 * op2
8224 movq(raxReg, op2);
8225 mulq(op1);
8226
8227 // rdx:rax = sum + carry + rdx:rax
8228 addq(sum, carry);
8229 adcq(rdxReg, 0);
8230 addq(sum, raxReg);
8231 adcq(rdxReg, 0);
8232
8233 // carry:sum = rdx:sum
8234 movq(carry, rdxReg);
8235 }
8236
8237 /**
8238 * Add 64 bit long carry into z[] with carry propogation.
8239 * Preserves z and carry register values and modifies rest of registers.
8240 *
8241 */
8242 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
8243 Label L_fourth_loop, L_fourth_loop_exit;
8244
8245 movl(tmp1, 1);
8246 subl(zlen, 2);
8247 addq(Address(z, zlen, Address::times_4, 0), carry);
8248
8249 bind(L_fourth_loop);
8250 jccb(Assembler::carryClear, L_fourth_loop_exit);
8251 subl(zlen, 2);
8252 jccb(Assembler::negative, L_fourth_loop_exit);
8253 addq(Address(z, zlen, Address::times_4, 0), tmp1);
8254 jmp(L_fourth_loop);
8255 bind(L_fourth_loop_exit);
8256 }
8257
8258 /**
8259 * Shift z[] left by 1 bit.
8260 * Preserves x, len, z and zlen registers and modifies rest of the registers.
8261 *
8262 */
8263 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
8264
8265 Label L_fifth_loop, L_fifth_loop_exit;
8266
8267 // Fifth loop
8268 // Perform primitiveLeftShift(z, zlen, 1)
8269
8270 const Register prev_carry = tmp1;
8271 const Register new_carry = tmp4;
8272 const Register value = tmp2;
8273 const Register zidx = tmp3;
8274
8275 // int zidx, carry;
8276 // long value;
8277 // carry = 0;
8278 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
8279 // (carry:value) = (z[i] << 1) | carry ;
8280 // z[i] = value;
8281 // }
8282
8283 movl(zidx, zlen);
8284 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
8285
8286 bind(L_fifth_loop);
8287 decl(zidx); // Use decl to preserve carry flag
8288 decl(zidx);
8289 jccb(Assembler::negative, L_fifth_loop_exit);
8290
8291 if (UseBMI2Instructions) {
8292 movq(value, Address(z, zidx, Address::times_4, 0));
8293 rclq(value, 1);
8294 rorxq(value, value, 32);
8295 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8296 }
8297 else {
8298 // clear new_carry
8299 xorl(new_carry, new_carry);
8300
8301 // Shift z[i] by 1, or in previous carry and save new carry
8302 movq(value, Address(z, zidx, Address::times_4, 0));
8303 shlq(value, 1);
8304 adcl(new_carry, 0);
8305
8306 orq(value, prev_carry);
8307 rorq(value, 0x20);
8308 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8309
8310 // Set previous carry = new carry
8311 movl(prev_carry, new_carry);
8312 }
8313 jmp(L_fifth_loop);
8314
8315 bind(L_fifth_loop_exit);
8316 }
8317
8318
8319 /**
8320 * Code for BigInteger::squareToLen() intrinsic
8321 *
8322 * rdi: x
8323 * rsi: len
8324 * r8: z
8325 * rcx: zlen
8326 * r12: tmp1
8327 * r13: tmp2
8328 * r14: tmp3
8329 * r15: tmp4
8330 * rbx: tmp5
8331 *
8332 */
8333 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8334
8335 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8336 push(tmp1);
8337 push(tmp2);
8338 push(tmp3);
8339 push(tmp4);
8340 push(tmp5);
8341
8342 // First loop
8343 // Store the squares, right shifted one bit (i.e., divided by 2).
8344 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8345
8346 // Add in off-diagonal sums.
8347 //
8348 // Second, third (nested) and fourth loops.
8349 // zlen +=2;
8350 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8351 // carry = 0;
8352 // long op2 = x[xidx:xidx+1];
8353 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8354 // k -= 2;
8355 // long op1 = x[j:j+1];
8356 // long sum = z[k:k+1];
8357 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8358 // z[k:k+1] = sum;
8359 // }
8360 // add_one_64(z, k, carry, tmp_regs);
8361 // }
8362
8363 const Register carry = tmp5;
8364 const Register sum = tmp3;
8365 const Register op1 = tmp4;
8366 Register op2 = tmp2;
8367
8368 push(zlen);
8369 push(len);
8370 addl(zlen,2);
8371 bind(L_second_loop);
8372 xorq(carry, carry);
8373 subl(zlen, 4);
8374 subl(len, 2);
8375 push(zlen);
8376 push(len);
8377 cmpl(len, 0);
8378 jccb(Assembler::lessEqual, L_second_loop_exit);
8379
8380 // Multiply an array by one 64 bit long.
8381 if (UseBMI2Instructions) {
8382 op2 = rdxReg;
8383 movq(op2, Address(x, len, Address::times_4, 0));
8384 rorxq(op2, op2, 32);
8385 }
8386 else {
8387 movq(op2, Address(x, len, Address::times_4, 0));
8388 rorq(op2, 32);
8389 }
8390
8391 bind(L_third_loop);
8392 decrementl(len);
8393 jccb(Assembler::negative, L_third_loop_exit);
8394 decrementl(len);
8395 jccb(Assembler::negative, L_last_x);
8396
8397 movq(op1, Address(x, len, Address::times_4, 0));
8398 rorq(op1, 32);
8399
8400 bind(L_multiply);
8401 subl(zlen, 2);
8402 movq(sum, Address(z, zlen, Address::times_4, 0));
8403
8404 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8405 if (UseBMI2Instructions) {
8406 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8407 }
8408 else {
8409 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8410 }
8411
8412 movq(Address(z, zlen, Address::times_4, 0), sum);
8413
8414 jmp(L_third_loop);
8415 bind(L_third_loop_exit);
8416
8417 // Fourth loop
8418 // Add 64 bit long carry into z with carry propogation.
8419 // Uses offsetted zlen.
8420 add_one_64(z, zlen, carry, tmp1);
8421
8422 pop(len);
8423 pop(zlen);
8424 jmp(L_second_loop);
8425
8426 // Next infrequent code is moved outside loops.
8427 bind(L_last_x);
8428 movl(op1, Address(x, 0));
8429 jmp(L_multiply);
8430
8431 bind(L_second_loop_exit);
8432 pop(len);
8433 pop(zlen);
8434 pop(len);
8435 pop(zlen);
8436
8437 // Fifth loop
8438 // Shift z left 1 bit.
8439 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8440
8441 // z[zlen-1] |= x[len-1] & 1;
8442 movl(tmp3, Address(x, len, Address::times_4, -4));
8443 andl(tmp3, 1);
8444 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8445
8446 pop(tmp5);
8447 pop(tmp4);
8448 pop(tmp3);
8449 pop(tmp2);
8450 pop(tmp1);
8451 }
8452
8453 /**
8454 * Helper function for mul_add()
8455 * Multiply the in[] by int k and add to out[] starting at offset offs using
8456 * 128 bit by 32 bit multiply and return the carry in tmp5.
8457 * Only quad int aligned length of in[] is operated on in this function.
8458 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8459 * This function preserves out, in and k registers.
8460 * len and offset point to the appropriate index in "in" & "out" correspondingly
8461 * tmp5 has the carry.
8462 * other registers are temporary and are modified.
8463 *
8464 */
8465 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8466 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8467 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8468
8469 Label L_first_loop, L_first_loop_exit;
8470
8471 movl(tmp1, len);
8472 shrl(tmp1, 2);
8473
8474 bind(L_first_loop);
8475 subl(tmp1, 1);
8476 jccb(Assembler::negative, L_first_loop_exit);
8477
8478 subl(len, 4);
8479 subl(offset, 4);
8480
8481 Register op2 = tmp2;
8482 const Register sum = tmp3;
8483 const Register op1 = tmp4;
8484 const Register carry = tmp5;
8485
8486 if (UseBMI2Instructions) {
8487 op2 = rdxReg;
8488 }
8489
8490 movq(op1, Address(in, len, Address::times_4, 8));
8491 rorq(op1, 32);
8492 movq(sum, Address(out, offset, Address::times_4, 8));
8493 rorq(sum, 32);
8494 if (UseBMI2Instructions) {
8495 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8496 }
8497 else {
8498 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8499 }
8500 // Store back in big endian from little endian
8501 rorq(sum, 0x20);
8502 movq(Address(out, offset, Address::times_4, 8), sum);
8503
8504 movq(op1, Address(in, len, Address::times_4, 0));
8505 rorq(op1, 32);
8506 movq(sum, Address(out, offset, Address::times_4, 0));
8507 rorq(sum, 32);
8508 if (UseBMI2Instructions) {
8509 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8510 }
8511 else {
8512 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8513 }
8514 // Store back in big endian from little endian
8515 rorq(sum, 0x20);
8516 movq(Address(out, offset, Address::times_4, 0), sum);
8517
8518 jmp(L_first_loop);
8519 bind(L_first_loop_exit);
8520 }
8521
8522 /**
8523 * Code for BigInteger::mulAdd() intrinsic
8524 *
8525 * rdi: out
8526 * rsi: in
8527 * r11: offs (out.length - offset)
8528 * rcx: len
8529 * r8: k
8530 * r12: tmp1
8531 * r13: tmp2
8532 * r14: tmp3
8533 * r15: tmp4
8534 * rbx: tmp5
8535 * Multiply the in[] by word k and add to out[], return the carry in rax
8536 */
8537 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8538 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8539 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8540
8541 Label L_carry, L_last_in, L_done;
8542
8543 // carry = 0;
8544 // for (int j=len-1; j >= 0; j--) {
8545 // long product = (in[j] & LONG_MASK) * kLong +
8546 // (out[offs] & LONG_MASK) + carry;
8547 // out[offs--] = (int)product;
8548 // carry = product >>> 32;
8549 // }
8550 //
8551 push(tmp1);
8552 push(tmp2);
8553 push(tmp3);
8554 push(tmp4);
8555 push(tmp5);
8556
8557 Register op2 = tmp2;
8558 const Register sum = tmp3;
8559 const Register op1 = tmp4;
8560 const Register carry = tmp5;
8561
8562 if (UseBMI2Instructions) {
8563 op2 = rdxReg;
8564 movl(op2, k);
8565 }
8566 else {
8567 movl(op2, k);
8568 }
8569
8570 xorq(carry, carry);
8571
8572 //First loop
8573
8574 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8575 //The carry is in tmp5
8576 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8577
8578 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8579 decrementl(len);
8580 jccb(Assembler::negative, L_carry);
8581 decrementl(len);
8582 jccb(Assembler::negative, L_last_in);
8583
8584 movq(op1, Address(in, len, Address::times_4, 0));
8585 rorq(op1, 32);
8586
8587 subl(offs, 2);
8588 movq(sum, Address(out, offs, Address::times_4, 0));
8589 rorq(sum, 32);
8590
8591 if (UseBMI2Instructions) {
8592 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8593 }
8594 else {
8595 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8596 }
8597
8598 // Store back in big endian from little endian
8599 rorq(sum, 0x20);
8600 movq(Address(out, offs, Address::times_4, 0), sum);
8601
8602 testl(len, len);
8603 jccb(Assembler::zero, L_carry);
8604
8605 //Multiply the last in[] entry, if any
8606 bind(L_last_in);
8607 movl(op1, Address(in, 0));
8608 movl(sum, Address(out, offs, Address::times_4, -4));
8609
8610 movl(raxReg, k);
8611 mull(op1); //tmp4 * eax -> edx:eax
8612 addl(sum, carry);
8613 adcl(rdxReg, 0);
8614 addl(sum, raxReg);
8615 adcl(rdxReg, 0);
8616 movl(carry, rdxReg);
8617
8618 movl(Address(out, offs, Address::times_4, -4), sum);
8619
8620 bind(L_carry);
8621 //return tmp5/carry as carry in rax
8622 movl(rax, carry);
8623
8624 bind(L_done);
8625 pop(tmp5);
8626 pop(tmp4);
8627 pop(tmp3);
8628 pop(tmp2);
8629 pop(tmp1);
8630 }
8631 #endif
8632
8633 /**
8634 * Emits code to update CRC-32 with a byte value according to constants in table
8635 *
8636 * @param [in,out]crc Register containing the crc.
8637 * @param [in]val Register containing the byte to fold into the CRC.
8638 * @param [in]table Register containing the table of crc constants.
8639 *
8640 * uint32_t crc;
8641 * val = crc_table[(val ^ crc) & 0xFF];
8642 * crc = val ^ (crc >> 8);
8643 *
8644 */
8645 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8646 xorl(val, crc);
8647 andl(val, 0xFF);
8648 shrl(crc, 8); // unsigned shift
8649 xorl(crc, Address(table, val, Address::times_4, 0));
8650 }
8651
8652 /**
8653 * Fold four 128-bit data chunks
8654 */
8655 void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8656 evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64]
8657 evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0]
8658 evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */);
8659 evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */);
8660 }
8661
8662 /**
8663 * Fold 128-bit data chunk
8664 */
8665 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8666 if (UseAVX > 0) {
8667 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8668 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8669 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8670 pxor(xcrc, xtmp);
8671 } else {
8672 movdqa(xtmp, xcrc);
8673 pclmulhdq(xtmp, xK); // [123:64]
8674 pclmulldq(xcrc, xK); // [63:0]
8675 pxor(xcrc, xtmp);
8676 movdqu(xtmp, Address(buf, offset));
8677 pxor(xcrc, xtmp);
8678 }
8679 }
8680
8681 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8682 if (UseAVX > 0) {
8683 vpclmulhdq(xtmp, xK, xcrc);
8684 vpclmulldq(xcrc, xK, xcrc);
8685 pxor(xcrc, xbuf);
8686 pxor(xcrc, xtmp);
8687 } else {
8688 movdqa(xtmp, xcrc);
8689 pclmulhdq(xtmp, xK);
8690 pclmulldq(xcrc, xK);
8691 pxor(xcrc, xbuf);
8692 pxor(xcrc, xtmp);
8693 }
8694 }
8695
8696 /**
8697 * 8-bit folds to compute 32-bit CRC
8698 *
8699 * uint64_t xcrc;
8700 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8701 */
8702 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8703 movdl(tmp, xcrc);
8704 andl(tmp, 0xFF);
8705 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8706 psrldq(xcrc, 1); // unsigned shift one byte
8707 pxor(xcrc, xtmp);
8708 }
8709
8710 /**
8711 * uint32_t crc;
8712 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8713 */
8714 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8715 movl(tmp, crc);
8716 andl(tmp, 0xFF);
8717 shrl(crc, 8);
8718 xorl(crc, Address(table, tmp, Address::times_4, 0));
8719 }
8720
8721 /**
8722 * @param crc register containing existing CRC (32-bit)
8723 * @param buf register pointing to input byte buffer (byte*)
8724 * @param len register containing number of bytes
8725 * @param table register that will contain address of CRC table
8726 * @param tmp scratch register
8727 */
8728 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8729 assert_different_registers(crc, buf, len, table, tmp, rax);
8730
8731 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8732 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8733
8734 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8735 // context for the registers used, where all instructions below are using 128-bit mode
8736 // On EVEX without VL and BW, these instructions will all be AVX.
8737 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8738 notl(crc); // ~crc
8739 cmpl(len, 16);
8740 jcc(Assembler::less, L_tail);
8741
8742 // Align buffer to 16 bytes
8743 movl(tmp, buf);
8744 andl(tmp, 0xF);
8745 jccb(Assembler::zero, L_aligned);
8746 subl(tmp, 16);
8747 addl(len, tmp);
8748
8749 align(4);
8750 BIND(L_align_loop);
8751 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8752 update_byte_crc32(crc, rax, table);
8753 increment(buf);
8754 incrementl(tmp);
8755 jccb(Assembler::less, L_align_loop);
8756
8757 BIND(L_aligned);
8758 movl(tmp, len); // save
8759 shrl(len, 4);
8760 jcc(Assembler::zero, L_tail_restore);
8761
8762 // Fold total 512 bits of polynomial on each iteration
8763 if (VM_Version::supports_vpclmulqdq()) {
8764 Label Parallel_loop, L_No_Parallel;
8765
8766 cmpl(len, 8);
8767 jccb(Assembler::less, L_No_Parallel);
8768
8769 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8770 evmovdquq(xmm1, Address(buf, 0), Assembler::AVX_512bit);
8771 movdl(xmm5, crc);
8772 evpxorq(xmm1, xmm1, xmm5, Assembler::AVX_512bit);
8773 addptr(buf, 64);
8774 subl(len, 7);
8775 evshufi64x2(xmm0, xmm0, xmm0, 0x00, Assembler::AVX_512bit); //propagate the mask from 128 bits to 512 bits
8776
8777 BIND(Parallel_loop);
8778 fold_128bit_crc32_avx512(xmm1, xmm0, xmm5, buf, 0);
8779 addptr(buf, 64);
8780 subl(len, 4);
8781 jcc(Assembler::greater, Parallel_loop);
8782
8783 vextracti64x2(xmm2, xmm1, 0x01);
8784 vextracti64x2(xmm3, xmm1, 0x02);
8785 vextracti64x2(xmm4, xmm1, 0x03);
8786 jmp(L_fold_512b);
8787
8788 BIND(L_No_Parallel);
8789 }
8790 // Fold crc into first bytes of vector
8791 movdqa(xmm1, Address(buf, 0));
8792 movdl(rax, xmm1);
8793 xorl(crc, rax);
8794 if (VM_Version::supports_sse4_1()) {
8795 pinsrd(xmm1, crc, 0);
8796 } else {
8797 pinsrw(xmm1, crc, 0);
8798 shrl(crc, 16);
8799 pinsrw(xmm1, crc, 1);
8800 }
8801 addptr(buf, 16);
8802 subl(len, 4); // len > 0
8803 jcc(Assembler::less, L_fold_tail);
8804
8805 movdqa(xmm2, Address(buf, 0));
8806 movdqa(xmm3, Address(buf, 16));
8807 movdqa(xmm4, Address(buf, 32));
8808 addptr(buf, 48);
8809 subl(len, 3);
8810 jcc(Assembler::lessEqual, L_fold_512b);
8811
8812 // Fold total 512 bits of polynomial on each iteration,
8813 // 128 bits per each of 4 parallel streams.
8814 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8815
8816 align(32);
8817 BIND(L_fold_512b_loop);
8818 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8819 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8820 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8821 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8822 addptr(buf, 64);
8823 subl(len, 4);
8824 jcc(Assembler::greater, L_fold_512b_loop);
8825
8826 // Fold 512 bits to 128 bits.
8827 BIND(L_fold_512b);
8828 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8829 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8830 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8831 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8832
8833 // Fold the rest of 128 bits data chunks
8834 BIND(L_fold_tail);
8835 addl(len, 3);
8836 jccb(Assembler::lessEqual, L_fold_128b);
8837 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8838
8839 BIND(L_fold_tail_loop);
8840 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8841 addptr(buf, 16);
8842 decrementl(len);
8843 jccb(Assembler::greater, L_fold_tail_loop);
8844
8845 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8846 BIND(L_fold_128b);
8847 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
8848 if (UseAVX > 0) {
8849 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8850 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8851 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8852 } else {
8853 movdqa(xmm2, xmm0);
8854 pclmulqdq(xmm2, xmm1, 0x1);
8855 movdqa(xmm3, xmm0);
8856 pand(xmm3, xmm2);
8857 pclmulqdq(xmm0, xmm3, 0x1);
8858 }
8859 psrldq(xmm1, 8);
8860 psrldq(xmm2, 4);
8861 pxor(xmm0, xmm1);
8862 pxor(xmm0, xmm2);
8863
8864 // 8 8-bit folds to compute 32-bit CRC.
8865 for (int j = 0; j < 4; j++) {
8866 fold_8bit_crc32(xmm0, table, xmm1, rax);
8867 }
8868 movdl(crc, xmm0); // mov 32 bits to general register
8869 for (int j = 0; j < 4; j++) {
8870 fold_8bit_crc32(crc, table, rax);
8871 }
8872
8873 BIND(L_tail_restore);
8874 movl(len, tmp); // restore
8875 BIND(L_tail);
8876 andl(len, 0xf);
8877 jccb(Assembler::zero, L_exit);
8878
8879 // Fold the rest of bytes
8880 align(4);
8881 BIND(L_tail_loop);
8882 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8883 update_byte_crc32(crc, rax, table);
8884 increment(buf);
8885 decrementl(len);
8886 jccb(Assembler::greater, L_tail_loop);
8887
8888 BIND(L_exit);
8889 notl(crc); // ~c
8890 }
8891
8892 #ifdef _LP64
8893 // S. Gueron / Information Processing Letters 112 (2012) 184
8894 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8895 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8896 // Output: the 64-bit carry-less product of B * CONST
8897 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8898 Register tmp1, Register tmp2, Register tmp3) {
8899 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8900 if (n > 0) {
8901 addq(tmp3, n * 256 * 8);
8902 }
8903 // Q1 = TABLEExt[n][B & 0xFF];
8904 movl(tmp1, in);
8905 andl(tmp1, 0x000000FF);
8906 shll(tmp1, 3);
8907 addq(tmp1, tmp3);
8908 movq(tmp1, Address(tmp1, 0));
8909
8910 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8911 movl(tmp2, in);
8912 shrl(tmp2, 8);
8913 andl(tmp2, 0x000000FF);
8914 shll(tmp2, 3);
8915 addq(tmp2, tmp3);
8916 movq(tmp2, Address(tmp2, 0));
8917
8918 shlq(tmp2, 8);
8919 xorq(tmp1, tmp2);
8920
8921 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8922 movl(tmp2, in);
8923 shrl(tmp2, 16);
8924 andl(tmp2, 0x000000FF);
8925 shll(tmp2, 3);
8926 addq(tmp2, tmp3);
8927 movq(tmp2, Address(tmp2, 0));
8928
8929 shlq(tmp2, 16);
8930 xorq(tmp1, tmp2);
8931
8932 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8933 shrl(in, 24);
8934 andl(in, 0x000000FF);
8935 shll(in, 3);
8936 addq(in, tmp3);
8937 movq(in, Address(in, 0));
8938
8939 shlq(in, 24);
8940 xorq(in, tmp1);
8941 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8942 }
8943
8944 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8945 Register in_out,
8946 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8947 XMMRegister w_xtmp2,
8948 Register tmp1,
8949 Register n_tmp2, Register n_tmp3) {
8950 if (is_pclmulqdq_supported) {
8951 movdl(w_xtmp1, in_out); // modified blindly
8952
8953 movl(tmp1, const_or_pre_comp_const_index);
8954 movdl(w_xtmp2, tmp1);
8955 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8956
8957 movdq(in_out, w_xtmp1);
8958 } else {
8959 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8960 }
8961 }
8962
8963 // Recombination Alternative 2: No bit-reflections
8964 // T1 = (CRC_A * U1) << 1
8965 // T2 = (CRC_B * U2) << 1
8966 // C1 = T1 >> 32
8967 // C2 = T2 >> 32
8968 // T1 = T1 & 0xFFFFFFFF
8969 // T2 = T2 & 0xFFFFFFFF
8970 // T1 = CRC32(0, T1)
8971 // T2 = CRC32(0, T2)
8972 // C1 = C1 ^ T1
8973 // C2 = C2 ^ T2
8974 // CRC = C1 ^ C2 ^ CRC_C
8975 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8976 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8977 Register tmp1, Register tmp2,
8978 Register n_tmp3) {
8979 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8980 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8981 shlq(in_out, 1);
8982 movl(tmp1, in_out);
8983 shrq(in_out, 32);
8984 xorl(tmp2, tmp2);
8985 crc32(tmp2, tmp1, 4);
8986 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8987 shlq(in1, 1);
8988 movl(tmp1, in1);
8989 shrq(in1, 32);
8990 xorl(tmp2, tmp2);
8991 crc32(tmp2, tmp1, 4);
8992 xorl(in1, tmp2);
8993 xorl(in_out, in1);
8994 xorl(in_out, in2);
8995 }
8996
8997 // Set N to predefined value
8998 // Subtract from a lenght of a buffer
8999 // execute in a loop:
9000 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9001 // for i = 1 to N do
9002 // CRC_A = CRC32(CRC_A, A[i])
9003 // CRC_B = CRC32(CRC_B, B[i])
9004 // CRC_C = CRC32(CRC_C, C[i])
9005 // end for
9006 // Recombine
9007 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9008 Register in_out1, Register in_out2, Register in_out3,
9009 Register tmp1, Register tmp2, Register tmp3,
9010 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9011 Register tmp4, Register tmp5,
9012 Register n_tmp6) {
9013 Label L_processPartitions;
9014 Label L_processPartition;
9015 Label L_exit;
9016
9017 bind(L_processPartitions);
9018 cmpl(in_out1, 3 * size);
9019 jcc(Assembler::less, L_exit);
9020 xorl(tmp1, tmp1);
9021 xorl(tmp2, tmp2);
9022 movq(tmp3, in_out2);
9023 addq(tmp3, size);
9024
9025 bind(L_processPartition);
9026 crc32(in_out3, Address(in_out2, 0), 8);
9027 crc32(tmp1, Address(in_out2, size), 8);
9028 crc32(tmp2, Address(in_out2, size * 2), 8);
9029 addq(in_out2, 8);
9030 cmpq(in_out2, tmp3);
9031 jcc(Assembler::less, L_processPartition);
9032 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9033 w_xtmp1, w_xtmp2, w_xtmp3,
9034 tmp4, tmp5,
9035 n_tmp6);
9036 addq(in_out2, 2 * size);
9037 subl(in_out1, 3 * size);
9038 jmp(L_processPartitions);
9039
9040 bind(L_exit);
9041 }
9042 #else
9043 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
9044 Register tmp1, Register tmp2, Register tmp3,
9045 XMMRegister xtmp1, XMMRegister xtmp2) {
9046 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9047 if (n > 0) {
9048 addl(tmp3, n * 256 * 8);
9049 }
9050 // Q1 = TABLEExt[n][B & 0xFF];
9051 movl(tmp1, in_out);
9052 andl(tmp1, 0x000000FF);
9053 shll(tmp1, 3);
9054 addl(tmp1, tmp3);
9055 movq(xtmp1, Address(tmp1, 0));
9056
9057 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9058 movl(tmp2, in_out);
9059 shrl(tmp2, 8);
9060 andl(tmp2, 0x000000FF);
9061 shll(tmp2, 3);
9062 addl(tmp2, tmp3);
9063 movq(xtmp2, Address(tmp2, 0));
9064
9065 psllq(xtmp2, 8);
9066 pxor(xtmp1, xtmp2);
9067
9068 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9069 movl(tmp2, in_out);
9070 shrl(tmp2, 16);
9071 andl(tmp2, 0x000000FF);
9072 shll(tmp2, 3);
9073 addl(tmp2, tmp3);
9074 movq(xtmp2, Address(tmp2, 0));
9075
9076 psllq(xtmp2, 16);
9077 pxor(xtmp1, xtmp2);
9078
9079 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9080 shrl(in_out, 24);
9081 andl(in_out, 0x000000FF);
9082 shll(in_out, 3);
9083 addl(in_out, tmp3);
9084 movq(xtmp2, Address(in_out, 0));
9085
9086 psllq(xtmp2, 24);
9087 pxor(xtmp1, xtmp2); // Result in CXMM
9088 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9089 }
9090
9091 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9092 Register in_out,
9093 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9094 XMMRegister w_xtmp2,
9095 Register tmp1,
9096 Register n_tmp2, Register n_tmp3) {
9097 if (is_pclmulqdq_supported) {
9098 movdl(w_xtmp1, in_out);
9099
9100 movl(tmp1, const_or_pre_comp_const_index);
9101 movdl(w_xtmp2, tmp1);
9102 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9103 // Keep result in XMM since GPR is 32 bit in length
9104 } else {
9105 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9106 }
9107 }
9108
9109 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9110 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9111 Register tmp1, Register tmp2,
9112 Register n_tmp3) {
9113 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9114 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9115
9116 psllq(w_xtmp1, 1);
9117 movdl(tmp1, w_xtmp1);
9118 psrlq(w_xtmp1, 32);
9119 movdl(in_out, w_xtmp1);
9120
9121 xorl(tmp2, tmp2);
9122 crc32(tmp2, tmp1, 4);
9123 xorl(in_out, tmp2);
9124
9125 psllq(w_xtmp2, 1);
9126 movdl(tmp1, w_xtmp2);
9127 psrlq(w_xtmp2, 32);
9128 movdl(in1, w_xtmp2);
9129
9130 xorl(tmp2, tmp2);
9131 crc32(tmp2, tmp1, 4);
9132 xorl(in1, tmp2);
9133 xorl(in_out, in1);
9134 xorl(in_out, in2);
9135 }
9136
9137 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9138 Register in_out1, Register in_out2, Register in_out3,
9139 Register tmp1, Register tmp2, Register tmp3,
9140 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9141 Register tmp4, Register tmp5,
9142 Register n_tmp6) {
9143 Label L_processPartitions;
9144 Label L_processPartition;
9145 Label L_exit;
9146
9147 bind(L_processPartitions);
9148 cmpl(in_out1, 3 * size);
9149 jcc(Assembler::less, L_exit);
9150 xorl(tmp1, tmp1);
9151 xorl(tmp2, tmp2);
9152 movl(tmp3, in_out2);
9153 addl(tmp3, size);
9154
9155 bind(L_processPartition);
9156 crc32(in_out3, Address(in_out2, 0), 4);
9157 crc32(tmp1, Address(in_out2, size), 4);
9158 crc32(tmp2, Address(in_out2, size*2), 4);
9159 crc32(in_out3, Address(in_out2, 0+4), 4);
9160 crc32(tmp1, Address(in_out2, size+4), 4);
9161 crc32(tmp2, Address(in_out2, size*2+4), 4);
9162 addl(in_out2, 8);
9163 cmpl(in_out2, tmp3);
9164 jcc(Assembler::less, L_processPartition);
9165
9166 push(tmp3);
9167 push(in_out1);
9168 push(in_out2);
9169 tmp4 = tmp3;
9170 tmp5 = in_out1;
9171 n_tmp6 = in_out2;
9172
9173 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9174 w_xtmp1, w_xtmp2, w_xtmp3,
9175 tmp4, tmp5,
9176 n_tmp6);
9177
9178 pop(in_out2);
9179 pop(in_out1);
9180 pop(tmp3);
9181
9182 addl(in_out2, 2 * size);
9183 subl(in_out1, 3 * size);
9184 jmp(L_processPartitions);
9185
9186 bind(L_exit);
9187 }
9188 #endif //LP64
9189
9190 #ifdef _LP64
9191 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9192 // Input: A buffer I of L bytes.
9193 // Output: the CRC32C value of the buffer.
9194 // Notations:
9195 // Write L = 24N + r, with N = floor (L/24).
9196 // r = L mod 24 (0 <= r < 24).
9197 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9198 // N quadwords, and R consists of r bytes.
9199 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9200 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9201 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9202 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9203 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9204 Register tmp1, Register tmp2, Register tmp3,
9205 Register tmp4, Register tmp5, Register tmp6,
9206 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9207 bool is_pclmulqdq_supported) {
9208 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9209 Label L_wordByWord;
9210 Label L_byteByByteProlog;
9211 Label L_byteByByte;
9212 Label L_exit;
9213
9214 if (is_pclmulqdq_supported ) {
9215 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9216 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
9217
9218 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9219 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9220
9221 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9222 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9223 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9224 } else {
9225 const_or_pre_comp_const_index[0] = 1;
9226 const_or_pre_comp_const_index[1] = 0;
9227
9228 const_or_pre_comp_const_index[2] = 3;
9229 const_or_pre_comp_const_index[3] = 2;
9230
9231 const_or_pre_comp_const_index[4] = 5;
9232 const_or_pre_comp_const_index[5] = 4;
9233 }
9234 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9235 in2, in1, in_out,
9236 tmp1, tmp2, tmp3,
9237 w_xtmp1, w_xtmp2, w_xtmp3,
9238 tmp4, tmp5,
9239 tmp6);
9240 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9241 in2, in1, in_out,
9242 tmp1, tmp2, tmp3,
9243 w_xtmp1, w_xtmp2, w_xtmp3,
9244 tmp4, tmp5,
9245 tmp6);
9246 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9247 in2, in1, in_out,
9248 tmp1, tmp2, tmp3,
9249 w_xtmp1, w_xtmp2, w_xtmp3,
9250 tmp4, tmp5,
9251 tmp6);
9252 movl(tmp1, in2);
9253 andl(tmp1, 0x00000007);
9254 negl(tmp1);
9255 addl(tmp1, in2);
9256 addq(tmp1, in1);
9257
9258 BIND(L_wordByWord);
9259 cmpq(in1, tmp1);
9260 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9261 crc32(in_out, Address(in1, 0), 4);
9262 addq(in1, 4);
9263 jmp(L_wordByWord);
9264
9265 BIND(L_byteByByteProlog);
9266 andl(in2, 0x00000007);
9267 movl(tmp2, 1);
9268
9269 BIND(L_byteByByte);
9270 cmpl(tmp2, in2);
9271 jccb(Assembler::greater, L_exit);
9272 crc32(in_out, Address(in1, 0), 1);
9273 incq(in1);
9274 incl(tmp2);
9275 jmp(L_byteByByte);
9276
9277 BIND(L_exit);
9278 }
9279 #else
9280 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9281 Register tmp1, Register tmp2, Register tmp3,
9282 Register tmp4, Register tmp5, Register tmp6,
9283 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9284 bool is_pclmulqdq_supported) {
9285 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9286 Label L_wordByWord;
9287 Label L_byteByByteProlog;
9288 Label L_byteByByte;
9289 Label L_exit;
9290
9291 if (is_pclmulqdq_supported) {
9292 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9293 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9294
9295 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9296 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9297
9298 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9299 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9300 } else {
9301 const_or_pre_comp_const_index[0] = 1;
9302 const_or_pre_comp_const_index[1] = 0;
9303
9304 const_or_pre_comp_const_index[2] = 3;
9305 const_or_pre_comp_const_index[3] = 2;
9306
9307 const_or_pre_comp_const_index[4] = 5;
9308 const_or_pre_comp_const_index[5] = 4;
9309 }
9310 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9311 in2, in1, in_out,
9312 tmp1, tmp2, tmp3,
9313 w_xtmp1, w_xtmp2, w_xtmp3,
9314 tmp4, tmp5,
9315 tmp6);
9316 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9317 in2, in1, in_out,
9318 tmp1, tmp2, tmp3,
9319 w_xtmp1, w_xtmp2, w_xtmp3,
9320 tmp4, tmp5,
9321 tmp6);
9322 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9323 in2, in1, in_out,
9324 tmp1, tmp2, tmp3,
9325 w_xtmp1, w_xtmp2, w_xtmp3,
9326 tmp4, tmp5,
9327 tmp6);
9328 movl(tmp1, in2);
9329 andl(tmp1, 0x00000007);
9330 negl(tmp1);
9331 addl(tmp1, in2);
9332 addl(tmp1, in1);
9333
9334 BIND(L_wordByWord);
9335 cmpl(in1, tmp1);
9336 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9337 crc32(in_out, Address(in1,0), 4);
9338 addl(in1, 4);
9339 jmp(L_wordByWord);
9340
9341 BIND(L_byteByByteProlog);
9342 andl(in2, 0x00000007);
9343 movl(tmp2, 1);
9344
9345 BIND(L_byteByByte);
9346 cmpl(tmp2, in2);
9347 jccb(Assembler::greater, L_exit);
9348 movb(tmp1, Address(in1, 0));
9349 crc32(in_out, tmp1, 1);
9350 incl(in1);
9351 incl(tmp2);
9352 jmp(L_byteByByte);
9353
9354 BIND(L_exit);
9355 }
9356 #endif // LP64
9357 #undef BIND
9358 #undef BLOCK_COMMENT
9359
9360 // Compress char[] array to byte[].
9361 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
9362 // @HotSpotIntrinsicCandidate
9363 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9364 // for (int i = 0; i < len; i++) {
9365 // int c = src[srcOff++];
9366 // if (c >>> 8 != 0) {
9367 // return 0;
9368 // }
9369 // dst[dstOff++] = (byte)c;
9370 // }
9371 // return len;
9372 // }
9373 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9374 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9375 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9376 Register tmp5, Register result) {
9377 Label copy_chars_loop, return_length, return_zero, done;
9378
9379 // rsi: src
9380 // rdi: dst
9381 // rdx: len
9382 // rcx: tmp5
9383 // rax: result
9384
9385 // rsi holds start addr of source char[] to be compressed
9386 // rdi holds start addr of destination byte[]
9387 // rdx holds length
9388
9389 assert(len != result, "");
9390
9391 // save length for return
9392 push(len);
9393
9394 if ((UseAVX > 2) && // AVX512
9395 VM_Version::supports_avx512vlbw() &&
9396 VM_Version::supports_bmi2()) {
9397
9398 Label copy_32_loop, copy_loop_tail, below_threshold;
9399
9400 // alignment
9401 Label post_alignment;
9402
9403 // if length of the string is less than 16, handle it in an old fashioned way
9404 testl(len, -32);
9405 jcc(Assembler::zero, below_threshold);
9406
9407 // First check whether a character is compressable ( <= 0xFF).
9408 // Create mask to test for Unicode chars inside zmm vector
9409 movl(result, 0x00FF);
9410 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
9411
9412 testl(len, -64);
9413 jcc(Assembler::zero, post_alignment);
9414
9415 movl(tmp5, dst);
9416 andl(tmp5, (32 - 1));
9417 negl(tmp5);
9418 andl(tmp5, (32 - 1));
9419
9420 // bail out when there is nothing to be done
9421 testl(tmp5, 0xFFFFFFFF);
9422 jcc(Assembler::zero, post_alignment);
9423
9424 // ~(~0 << len), where len is the # of remaining elements to process
9425 movl(result, 0xFFFFFFFF);
9426 shlxl(result, result, tmp5);
9427 notl(result);
9428 kmovdl(k3, result);
9429
9430 evmovdquw(tmp1Reg, k3, Address(src, 0), Assembler::AVX_512bit);
9431 evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9432 ktestd(k2, k3);
9433 jcc(Assembler::carryClear, return_zero);
9434
9435 evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit);
9436
9437 addptr(src, tmp5);
9438 addptr(src, tmp5);
9439 addptr(dst, tmp5);
9440 subl(len, tmp5);
9441
9442 bind(post_alignment);
9443 // end of alignment
9444
9445 movl(tmp5, len);
9446 andl(tmp5, (32 - 1)); // tail count (in chars)
9447 andl(len, ~(32 - 1)); // vector count (in chars)
9448 jcc(Assembler::zero, copy_loop_tail);
9449
9450 lea(src, Address(src, len, Address::times_2));
9451 lea(dst, Address(dst, len, Address::times_1));
9452 negptr(len);
9453
9454 bind(copy_32_loop);
9455 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9456 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9457 kortestdl(k2, k2);
9458 jcc(Assembler::carryClear, return_zero);
9459
9460 // All elements in current processed chunk are valid candidates for
9461 // compression. Write a truncated byte elements to the memory.
9462 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9463 addptr(len, 32);
9464 jcc(Assembler::notZero, copy_32_loop);
9465
9466 bind(copy_loop_tail);
9467 // bail out when there is nothing to be done
9468 testl(tmp5, 0xFFFFFFFF);
9469 jcc(Assembler::zero, return_length);
9470
9471 movl(len, tmp5);
9472
9473 // ~(~0 << len), where len is the # of remaining elements to process
9474 movl(result, 0xFFFFFFFF);
9475 shlxl(result, result, len);
9476 notl(result);
9477
9478 kmovdl(k3, result);
9479
9480 evmovdquw(tmp1Reg, k3, Address(src, 0), Assembler::AVX_512bit);
9481 evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9482 ktestd(k2, k3);
9483 jcc(Assembler::carryClear, return_zero);
9484
9485 evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit);
9486 jmp(return_length);
9487
9488 bind(below_threshold);
9489 }
9490
9491 if (UseSSE42Intrinsics) {
9492 Label copy_32_loop, copy_16, copy_tail;
9493
9494 movl(result, len);
9495
9496 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9497
9498 // vectored compression
9499 andl(len, 0xfffffff0); // vector count (in chars)
9500 andl(result, 0x0000000f); // tail count (in chars)
9501 testl(len, len);
9502 jcc(Assembler::zero, copy_16);
9503
9504 // compress 16 chars per iter
9505 movdl(tmp1Reg, tmp5);
9506 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9507 pxor(tmp4Reg, tmp4Reg);
9508
9509 lea(src, Address(src, len, Address::times_2));
9510 lea(dst, Address(dst, len, Address::times_1));
9511 negptr(len);
9512
9513 bind(copy_32_loop);
9514 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9515 por(tmp4Reg, tmp2Reg);
9516 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9517 por(tmp4Reg, tmp3Reg);
9518 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9519 jcc(Assembler::notZero, return_zero);
9520 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9521 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9522 addptr(len, 16);
9523 jcc(Assembler::notZero, copy_32_loop);
9524
9525 // compress next vector of 8 chars (if any)
9526 bind(copy_16);
9527 movl(len, result);
9528 andl(len, 0xfffffff8); // vector count (in chars)
9529 andl(result, 0x00000007); // tail count (in chars)
9530 testl(len, len);
9531 jccb(Assembler::zero, copy_tail);
9532
9533 movdl(tmp1Reg, tmp5);
9534 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9535 pxor(tmp3Reg, tmp3Reg);
9536
9537 movdqu(tmp2Reg, Address(src, 0));
9538 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9539 jccb(Assembler::notZero, return_zero);
9540 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9541 movq(Address(dst, 0), tmp2Reg);
9542 addptr(src, 16);
9543 addptr(dst, 8);
9544
9545 bind(copy_tail);
9546 movl(len, result);
9547 }
9548 // compress 1 char per iter
9549 testl(len, len);
9550 jccb(Assembler::zero, return_length);
9551 lea(src, Address(src, len, Address::times_2));
9552 lea(dst, Address(dst, len, Address::times_1));
9553 negptr(len);
9554
9555 bind(copy_chars_loop);
9556 load_unsigned_short(result, Address(src, len, Address::times_2));
9557 testl(result, 0xff00); // check if Unicode char
9558 jccb(Assembler::notZero, return_zero);
9559 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
9560 increment(len);
9561 jcc(Assembler::notZero, copy_chars_loop);
9562
9563 // if compression succeeded, return length
9564 bind(return_length);
9565 pop(result);
9566 jmpb(done);
9567
9568 // if compression failed, return 0
9569 bind(return_zero);
9570 xorl(result, result);
9571 addptr(rsp, wordSize);
9572
9573 bind(done);
9574 }
9575
9576 // Inflate byte[] array to char[].
9577 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9578 // @HotSpotIntrinsicCandidate
9579 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9580 // for (int i = 0; i < len; i++) {
9581 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9582 // }
9583 // }
9584 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9585 XMMRegister tmp1, Register tmp2) {
9586 Label copy_chars_loop, done, below_threshold;
9587 // rsi: src
9588 // rdi: dst
9589 // rdx: len
9590 // rcx: tmp2
9591
9592 // rsi holds start addr of source byte[] to be inflated
9593 // rdi holds start addr of destination char[]
9594 // rdx holds length
9595 assert_different_registers(src, dst, len, tmp2);
9596
9597 if ((UseAVX > 2) && // AVX512
9598 VM_Version::supports_avx512vlbw() &&
9599 VM_Version::supports_bmi2()) {
9600
9601 Label copy_32_loop, copy_tail;
9602 Register tmp3_aliased = len;
9603
9604 // if length of the string is less than 16, handle it in an old fashioned way
9605 testl(len, -16);
9606 jcc(Assembler::zero, below_threshold);
9607
9608 // In order to use only one arithmetic operation for the main loop we use
9609 // this pre-calculation
9610 movl(tmp2, len);
9611 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9612 andl(len, -32); // vector count
9613 jccb(Assembler::zero, copy_tail);
9614
9615 lea(src, Address(src, len, Address::times_1));
9616 lea(dst, Address(dst, len, Address::times_2));
9617 negptr(len);
9618
9619
9620 // inflate 32 chars per iter
9621 bind(copy_32_loop);
9622 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9623 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9624 addptr(len, 32);
9625 jcc(Assembler::notZero, copy_32_loop);
9626
9627 bind(copy_tail);
9628 // bail out when there is nothing to be done
9629 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9630 jcc(Assembler::zero, done);
9631
9632 // ~(~0 << length), where length is the # of remaining elements to process
9633 movl(tmp3_aliased, -1);
9634 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9635 notl(tmp3_aliased);
9636 kmovdl(k2, tmp3_aliased);
9637 evpmovzxbw(tmp1, k2, Address(src, 0), Assembler::AVX_512bit);
9638 evmovdquw(Address(dst, 0), k2, tmp1, Assembler::AVX_512bit);
9639
9640 jmp(done);
9641 }
9642 if (UseSSE42Intrinsics) {
9643 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9644
9645 movl(tmp2, len);
9646
9647 if (UseAVX > 1) {
9648 andl(tmp2, (16 - 1));
9649 andl(len, -16);
9650 jccb(Assembler::zero, copy_new_tail);
9651 } else {
9652 andl(tmp2, 0x00000007); // tail count (in chars)
9653 andl(len, 0xfffffff8); // vector count (in chars)
9654 jccb(Assembler::zero, copy_tail);
9655 }
9656
9657 // vectored inflation
9658 lea(src, Address(src, len, Address::times_1));
9659 lea(dst, Address(dst, len, Address::times_2));
9660 negptr(len);
9661
9662 if (UseAVX > 1) {
9663 bind(copy_16_loop);
9664 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9665 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9666 addptr(len, 16);
9667 jcc(Assembler::notZero, copy_16_loop);
9668
9669 bind(below_threshold);
9670 bind(copy_new_tail);
9671 if ((UseAVX > 2) &&
9672 VM_Version::supports_avx512vlbw() &&
9673 VM_Version::supports_bmi2()) {
9674 movl(tmp2, len);
9675 } else {
9676 movl(len, tmp2);
9677 }
9678 andl(tmp2, 0x00000007);
9679 andl(len, 0xFFFFFFF8);
9680 jccb(Assembler::zero, copy_tail);
9681
9682 pmovzxbw(tmp1, Address(src, 0));
9683 movdqu(Address(dst, 0), tmp1);
9684 addptr(src, 8);
9685 addptr(dst, 2 * 8);
9686
9687 jmp(copy_tail, true);
9688 }
9689
9690 // inflate 8 chars per iter
9691 bind(copy_8_loop);
9692 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9693 movdqu(Address(dst, len, Address::times_2), tmp1);
9694 addptr(len, 8);
9695 jcc(Assembler::notZero, copy_8_loop);
9696
9697 bind(copy_tail);
9698 movl(len, tmp2);
9699
9700 cmpl(len, 4);
9701 jccb(Assembler::less, copy_bytes);
9702
9703 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9704 pmovzxbw(tmp1, tmp1);
9705 movq(Address(dst, 0), tmp1);
9706 subptr(len, 4);
9707 addptr(src, 4);
9708 addptr(dst, 8);
9709
9710 bind(copy_bytes);
9711 } else {
9712 bind(below_threshold);
9713 }
9714
9715 testl(len, len);
9716 jccb(Assembler::zero, done);
9717 lea(src, Address(src, len, Address::times_1));
9718 lea(dst, Address(dst, len, Address::times_2));
9719 negptr(len);
9720
9721 // inflate 1 char per iter
9722 bind(copy_chars_loop);
9723 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9724 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9725 increment(len);
9726 jcc(Assembler::notZero, copy_chars_loop);
9727
9728 bind(done);
9729 }
9730
9731 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9732 switch (cond) {
9733 // Note some conditions are synonyms for others
9734 case Assembler::zero: return Assembler::notZero;
9735 case Assembler::notZero: return Assembler::zero;
9736 case Assembler::less: return Assembler::greaterEqual;
9737 case Assembler::lessEqual: return Assembler::greater;
9738 case Assembler::greater: return Assembler::lessEqual;
9739 case Assembler::greaterEqual: return Assembler::less;
9740 case Assembler::below: return Assembler::aboveEqual;
9741 case Assembler::belowEqual: return Assembler::above;
9742 case Assembler::above: return Assembler::belowEqual;
9743 case Assembler::aboveEqual: return Assembler::below;
9744 case Assembler::overflow: return Assembler::noOverflow;
9745 case Assembler::noOverflow: return Assembler::overflow;
9746 case Assembler::negative: return Assembler::positive;
9747 case Assembler::positive: return Assembler::negative;
9748 case Assembler::parity: return Assembler::noParity;
9749 case Assembler::noParity: return Assembler::parity;
9750 }
9751 ShouldNotReachHere(); return Assembler::overflow;
9752 }
9753
9754 SkipIfEqual::SkipIfEqual(
9755 MacroAssembler* masm, const bool* flag_addr, bool value) {
9756 _masm = masm;
9757 _masm->cmp8(ExternalAddress((address)flag_addr), value);
9758 _masm->jcc(Assembler::equal, _label);
9759 }
9760
9761 SkipIfEqual::~SkipIfEqual() {
9762 _masm->bind(_label);
9763 }
9764
9765 // 32-bit Windows has its own fast-path implementation
9766 // of get_thread
9767 #if !defined(WIN32) || defined(_LP64)
9768
9769 // This is simply a call to Thread::current()
9770 void MacroAssembler::get_thread(Register thread) {
9771 if (thread != rax) {
9772 push(rax);
9773 }
9774 LP64_ONLY(push(rdi);)
9775 LP64_ONLY(push(rsi);)
9776 push(rdx);
9777 push(rcx);
9778 #ifdef _LP64
9779 push(r8);
9780 push(r9);
9781 push(r10);
9782 push(r11);
9783 #endif
9784
9785 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
9786
9787 #ifdef _LP64
9788 pop(r11);
9789 pop(r10);
9790 pop(r9);
9791 pop(r8);
9792 #endif
9793 pop(rcx);
9794 pop(rdx);
9795 LP64_ONLY(pop(rsi);)
9796 LP64_ONLY(pop(rdi);)
9797 if (thread != rax) {
9798 mov(thread, rax);
9799 pop(rax);
9800 }
9801 }
9802
9803 #endif