8932
8933 format %{ "IMUL $op1, $op2\t# overflow check int" %}
8934 ins_encode %{
8935 __ imull($op1$$Register, $op2$$Register);
8936 %}
8937 ins_pipe(ialu_reg_reg_alu0);
8938 %}
8939
8940 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
8941 %{
8942 match(Set cr (OverflowMulI op1 op2));
8943 effect(DEF cr, TEMP tmp, USE op1, USE op2);
8944
8945 format %{ "IMUL $tmp, $op1, $op2\t# overflow check int" %}
8946 ins_encode %{
8947 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
8948 %}
8949 ins_pipe(ialu_reg_reg_alu0);
8950 %}
8951
8952 //----------Long Instructions------------------------------------------------
8953 // Add Long Register with Register
8954 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8955 match(Set dst (AddL dst src));
8956 effect(KILL cr);
8957 ins_cost(200);
8958 format %{ "ADD $dst.lo,$src.lo\n\t"
8959 "ADC $dst.hi,$src.hi" %}
8960 opcode(0x03, 0x13);
8961 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8962 ins_pipe( ialu_reg_reg_long );
8963 %}
8964
8965 // Add Long Register with Immediate
8966 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8967 match(Set dst (AddL dst src));
8968 effect(KILL cr);
8969 format %{ "ADD $dst.lo,$src.lo\n\t"
8970 "ADC $dst.hi,$src.hi" %}
8971 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
|
8932
8933 format %{ "IMUL $op1, $op2\t# overflow check int" %}
8934 ins_encode %{
8935 __ imull($op1$$Register, $op2$$Register);
8936 %}
8937 ins_pipe(ialu_reg_reg_alu0);
8938 %}
8939
8940 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
8941 %{
8942 match(Set cr (OverflowMulI op1 op2));
8943 effect(DEF cr, TEMP tmp, USE op1, USE op2);
8944
8945 format %{ "IMUL $tmp, $op1, $op2\t# overflow check int" %}
8946 ins_encode %{
8947 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
8948 %}
8949 ins_pipe(ialu_reg_reg_alu0);
8950 %}
8951
8952 // Integer Absolute Instructions
8953 instruct absI_rReg(rRegI dst, rRegI src, rRegI tmp, eFlagsReg cr)
8954 %{
8955 match(Set dst (AbsI src));
8956 effect(TEMP dst, TEMP tmp, KILL cr);
8957 format %{ "movl $tmp, $src\n\t"
8958 "sarl $tmp, 31\n\t"
8959 "movl $dst, $src\n\t"
8960 "xorl $dst, $tmp\n\t"
8961 "subl $dst, $tmp\n"
8962 %}
8963 ins_encode %{
8964 __ movl($tmp$$Register, $src$$Register);
8965 __ sarl($tmp$$Register, 31);
8966 __ movl($dst$$Register, $src$$Register);
8967 __ xorl($dst$$Register, $tmp$$Register);
8968 __ subl($dst$$Register, $tmp$$Register);
8969 %}
8970
8971 ins_pipe(ialu_reg_reg);
8972 %}
8973
8974 //----------Long Instructions------------------------------------------------
8975 // Add Long Register with Register
8976 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8977 match(Set dst (AddL dst src));
8978 effect(KILL cr);
8979 ins_cost(200);
8980 format %{ "ADD $dst.lo,$src.lo\n\t"
8981 "ADC $dst.hi,$src.hi" %}
8982 opcode(0x03, 0x13);
8983 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8984 ins_pipe( ialu_reg_reg_long );
8985 %}
8986
8987 // Add Long Register with Immediate
8988 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8989 match(Set dst (AddL dst src));
8990 effect(KILL cr);
8991 format %{ "ADD $dst.lo,$src.lo\n\t"
8992 "ADC $dst.hi,$src.hi" %}
8993 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
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