4360 disp(0x0);
4361 %}
4362 %}
4363
4364 // Indirect Memory Plus Long Offset Operand
4365 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4366 match(AddP reg off);
4367
4368 format %{ "[$reg + $off]" %}
4369 interface(MEMORY_INTER) %{
4370 base($reg);
4371 index(0x4);
4372 scale(0x0);
4373 disp($off);
4374 %}
4375 %}
4376
4377 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4378
4379
4380 //----------Special Memory Operands--------------------------------------------
4381 // Stack Slot Operand - This operand is used for loading and storing temporary
4382 // values on the stack where a match requires a value to
4383 // flow through memory.
4384 operand stackSlotP(sRegP reg) %{
4385 constraint(ALLOC_IN_RC(stack_slots));
4386 // No match rule because this operand is only generated in matching
4387 format %{ "[$reg]" %}
4388 interface(MEMORY_INTER) %{
4389 base(0x4); // ESP
4390 index(0x4); // No Index
4391 scale(0x0); // No Scale
4392 disp($reg); // Stack Offset
4393 %}
4394 %}
4395
4396 operand stackSlotI(sRegI reg) %{
4397 constraint(ALLOC_IN_RC(stack_slots));
4398 // No match rule because this operand is only generated in matching
4399 format %{ "[$reg]" %}
5965 ins_encode %{
5966 __ movdbl ($dst$$XMMRegister, $mem$$Address);
5967 %}
5968 ins_pipe( pipe_slow );
5969 %}
5970
5971 // Load to XMM register (single-precision floating point)
5972 // MOVSS instruction
5973 instruct loadF(regF dst, memory mem) %{
5974 predicate(UseSSE>=1);
5975 match(Set dst (LoadF mem));
5976 ins_cost(145);
5977 format %{ "MOVSS $dst,$mem" %}
5978 ins_encode %{
5979 __ movflt ($dst$$XMMRegister, $mem$$Address);
5980 %}
5981 ins_pipe( pipe_slow );
5982 %}
5983
5984 // Load Float
5985 instruct loadFPR(regFPR dst, memory mem) %{
5986 predicate(UseSSE==0);
5987 match(Set dst (LoadF mem));
5988
5989 ins_cost(150);
5990 format %{ "FLD_S ST,$mem\n\t"
5991 "FSTP $dst" %}
5992 opcode(0xD9); /* D9 /0 */
5993 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5994 Pop_Reg_FPR(dst) );
5995 ins_pipe( fpu_reg_mem );
5996 %}
5997
5998 // Load Effective Address
5999 instruct leaP8(eRegP dst, indOffset8 mem) %{
6000 match(Set dst mem);
6001
6002 ins_cost(110);
6003 format %{ "LEA $dst,$mem" %}
6004 opcode(0x8D);
6194
6195 format %{ "FLD1 ST\n\t"
6196 "FSTP $dst" %}
6197 ins_encode %{
6198 __ fld1();
6199 __ fstp_d($dst$$reg);
6200 %}
6201 ins_pipe(fpu_reg_con);
6202 %}
6203
6204 // The instruction usage is guarded by predicate in operand immD().
6205 instruct loadConD(regD dst, immD con) %{
6206 match(Set dst con);
6207 ins_cost(125);
6208 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6209 ins_encode %{
6210 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6211 %}
6212 ins_pipe(pipe_slow);
6213 %}
6214
6215 // The instruction usage is guarded by predicate in operand immD0().
6216 instruct loadConD0(regD dst, immD0 src) %{
6217 match(Set dst src);
6218 ins_cost(100);
6219 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6220 ins_encode %{
6221 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6222 %}
6223 ins_pipe( pipe_slow );
6224 %}
6225
6226 // Load Stack Slot
6227 instruct loadSSI(rRegI dst, stackSlotI src) %{
6228 match(Set dst src);
6229 ins_cost(125);
6230
6231 format %{ "MOV $dst,$src" %}
6232 opcode(0x8B);
6233 ins_encode( OpcP, RegMem(dst,src));
|
4360 disp(0x0);
4361 %}
4362 %}
4363
4364 // Indirect Memory Plus Long Offset Operand
4365 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4366 match(AddP reg off);
4367
4368 format %{ "[$reg + $off]" %}
4369 interface(MEMORY_INTER) %{
4370 base($reg);
4371 index(0x4);
4372 scale(0x0);
4373 disp($off);
4374 %}
4375 %}
4376
4377 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4378
4379
4380 operand legRegF() %{
4381 predicate( UseSSE>=1 );
4382 constraint(ALLOC_IN_RC(float_reg_legacy));
4383 match(RegF);
4384 format %{ %}
4385 interface(REG_INTER);
4386 %}
4387
4388 operand legRegD() %{
4389 predicate( UseSSE>=2 );
4390 constraint(ALLOC_IN_RC(double_reg_legacy));
4391 match(RegD);
4392 format %{ %}
4393 interface(REG_INTER);
4394 %}
4395
4396
4397
4398 //----------Special Memory Operands--------------------------------------------
4399 // Stack Slot Operand - This operand is used for loading and storing temporary
4400 // values on the stack where a match requires a value to
4401 // flow through memory.
4402 operand stackSlotP(sRegP reg) %{
4403 constraint(ALLOC_IN_RC(stack_slots));
4404 // No match rule because this operand is only generated in matching
4405 format %{ "[$reg]" %}
4406 interface(MEMORY_INTER) %{
4407 base(0x4); // ESP
4408 index(0x4); // No Index
4409 scale(0x0); // No Scale
4410 disp($reg); // Stack Offset
4411 %}
4412 %}
4413
4414 operand stackSlotI(sRegI reg) %{
4415 constraint(ALLOC_IN_RC(stack_slots));
4416 // No match rule because this operand is only generated in matching
4417 format %{ "[$reg]" %}
5983 ins_encode %{
5984 __ movdbl ($dst$$XMMRegister, $mem$$Address);
5985 %}
5986 ins_pipe( pipe_slow );
5987 %}
5988
5989 // Load to XMM register (single-precision floating point)
5990 // MOVSS instruction
5991 instruct loadF(regF dst, memory mem) %{
5992 predicate(UseSSE>=1);
5993 match(Set dst (LoadF mem));
5994 ins_cost(145);
5995 format %{ "MOVSS $dst,$mem" %}
5996 ins_encode %{
5997 __ movflt ($dst$$XMMRegister, $mem$$Address);
5998 %}
5999 ins_pipe( pipe_slow );
6000 %}
6001
6002 // Load Float
6003 instruct MoveF2LEG(legRegF dst, regF src) %{
6004 match(Set dst src);
6005 format %{ "movss $dst,$src\t! if src != dst load float (4 bytes)" %}
6006 ins_encode %{
6007 if ($dst$$reg != $src$$reg) {
6008 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6009 }
6010 %}
6011 ins_pipe( fpu_reg_reg );
6012 %}
6013
6014 // Load Float
6015 instruct MoveLEG2F(regF dst, legRegF src) %{
6016 match(Set dst src);
6017 format %{ "movss $dst,$src\t! if src != dst load float (4 bytes)" %}
6018 ins_encode %{
6019 if ($dst$$reg != $src$$reg) {
6020 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6021 }
6022 %}
6023 ins_pipe( fpu_reg_reg );
6024 %}
6025
6026
6027
6028 // Load Float
6029 instruct loadFPR(regFPR dst, memory mem) %{
6030 predicate(UseSSE==0);
6031 match(Set dst (LoadF mem));
6032
6033 ins_cost(150);
6034 format %{ "FLD_S ST,$mem\n\t"
6035 "FSTP $dst" %}
6036 opcode(0xD9); /* D9 /0 */
6037 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6038 Pop_Reg_FPR(dst) );
6039 ins_pipe( fpu_reg_mem );
6040 %}
6041
6042 // Load Effective Address
6043 instruct leaP8(eRegP dst, indOffset8 mem) %{
6044 match(Set dst mem);
6045
6046 ins_cost(110);
6047 format %{ "LEA $dst,$mem" %}
6048 opcode(0x8D);
6238
6239 format %{ "FLD1 ST\n\t"
6240 "FSTP $dst" %}
6241 ins_encode %{
6242 __ fld1();
6243 __ fstp_d($dst$$reg);
6244 %}
6245 ins_pipe(fpu_reg_con);
6246 %}
6247
6248 // The instruction usage is guarded by predicate in operand immD().
6249 instruct loadConD(regD dst, immD con) %{
6250 match(Set dst con);
6251 ins_cost(125);
6252 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6253 ins_encode %{
6254 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6255 %}
6256 ins_pipe(pipe_slow);
6257 %}
6258
6259 // Load Double
6260 instruct MoveD2LEG(legRegD dst, regD src) %{
6261 match(Set dst src);
6262 format %{ "movsd $dst,$src\t! if src != dst load double (8 bytes)" %}
6263 ins_encode %{
6264 if ($dst$$reg != $src$$reg) {
6265 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6266 }
6267 %}
6268 ins_pipe( fpu_reg_reg );
6269 %}
6270
6271 // Load Double
6272 instruct MoveLEG2D(regD dst, legRegD src) %{
6273 match(Set dst src);
6274 format %{ "movsd $dst,$src\t! if src != dst load double (8 bytes)" %}
6275 ins_encode %{
6276 if ($dst$$reg != $src$$reg) {
6277 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6278 }
6279 %}
6280 ins_pipe( fpu_reg_reg );
6281 %}
6282
6283
6284 // The instruction usage is guarded by predicate in operand immD0().
6285 instruct loadConD0(regD dst, immD0 src) %{
6286 match(Set dst src);
6287 ins_cost(100);
6288 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6289 ins_encode %{
6290 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6291 %}
6292 ins_pipe( pipe_slow );
6293 %}
6294
6295 // Load Stack Slot
6296 instruct loadSSI(rRegI dst, stackSlotI src) %{
6297 match(Set dst src);
6298 ins_cost(125);
6299
6300 format %{ "MOV $dst,$src" %}
6301 opcode(0x8B);
6302 ins_encode( OpcP, RegMem(dst,src));
|