< prev index next >
src/hotspot/cpu/x86/x86_64.ad
Print this page
*** 3655,3664 ****
--- 3655,3674 ----
format %{ %}
interface(REG_INTER);
%}
+
+ // Float register operands
+ operand legRegF() %{
+ constraint(ALLOC_IN_RC(float_reg_legacy));
+ match(RegF);
+
+ format %{ %}
+ interface(REG_INTER);
+ %}
+
// Float register operands
operand vlRegF() %{
constraint(ALLOC_IN_RC(float_reg_vl));
match(RegF);
*** 3674,3683 ****
--- 3684,3702 ----
format %{ %}
interface(REG_INTER);
%}
// Double register operands
+ operand legRegD() %{
+ constraint(ALLOC_IN_RC(double_reg_legacy));
+ match(RegD);
+
+ format %{ %}
+ interface(REG_INTER);
+ %}
+
+ // Double register operands
operand vlRegD() %{
constraint(ALLOC_IN_RC(double_reg_vl));
match(RegD);
format %{ %}
*** 5401,5410 ****
--- 5420,5430 ----
__ movflt($dst$$XMMRegister, $mem$$Address);
%}
ins_pipe(pipe_slow); // XXX
%}
+
// Load Float
instruct MoveF2VL(vlRegF dst, regF src) %{
match(Set dst src);
format %{ "movss $dst,$src\t! load float (4 bytes)" %}
ins_encode %{
*** 5412,5430 ****
--- 5432,5474 ----
%}
ins_pipe( fpu_reg_reg );
%}
// Load Float
+ instruct MoveF2LEG(legRegF dst, regF src) %{
+ match(Set dst src);
+ format %{ "movss $dst,$src\t! if src != dst load float (4 bytes)" %}
+ ins_encode %{
+ if ($dst$$reg != $src$$reg) {
+ __ movflt($dst$$XMMRegister, $src$$XMMRegister);
+ }
+ %}
+ ins_pipe( fpu_reg_reg );
+ %}
+
+ // Load Float
instruct MoveVL2F(regF dst, vlRegF src) %{
match(Set dst src);
format %{ "movss $dst,$src\t! load float (4 bytes)" %}
ins_encode %{
__ movflt($dst$$XMMRegister, $src$$XMMRegister);
%}
ins_pipe( fpu_reg_reg );
%}
+ // Load Float
+ instruct MoveLEG2F(regF dst, legRegF src) %{
+ match(Set dst src);
+ format %{ "movss $dst,$src\t! if src != dst load float (4 bytes)" %}
+ ins_encode %{
+ if ($dst$$reg != $src$$reg) {
+ __ movflt($dst$$XMMRegister, $src$$XMMRegister);
+ }
+ %}
+ ins_pipe( fpu_reg_reg );
+ %}
+
// Load Double
instruct loadD_partial(regD dst, memory mem)
%{
predicate(!UseXmmLoadAndClearUpper);
match(Set dst (LoadD mem));
*** 5435,5444 ****
--- 5479,5489 ----
__ movdbl($dst$$XMMRegister, $mem$$Address);
%}
ins_pipe(pipe_slow); // XXX
%}
+
instruct loadD(regD dst, memory mem)
%{
predicate(UseXmmLoadAndClearUpper);
match(Set dst (LoadD mem));
*** 5459,5477 ****
--- 5504,5546 ----
%}
ins_pipe( fpu_reg_reg );
%}
// Load Double
+ instruct MoveD2LEG(legRegD dst, regD src) %{
+ match(Set dst src);
+ format %{ "movsd $dst,$src\t! if src != dst load double (8 bytes)" %}
+ ins_encode %{
+ if ($dst$$reg != $src$$reg) {
+ __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
+ }
+ %}
+ ins_pipe( fpu_reg_reg );
+ %}
+
+ // Load Double
instruct MoveVL2D(regD dst, vlRegD src) %{
match(Set dst src);
format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
ins_encode %{
__ movdbl($dst$$XMMRegister, $src$$XMMRegister);
%}
ins_pipe( fpu_reg_reg );
%}
+ // Load Double
+ instruct MoveLEG2D(regD dst, legRegD src) %{
+ match(Set dst src);
+ format %{ "movsd $dst,$src\t! if src != dst load double (8 bytes)" %}
+ ins_encode %{
+ if ($dst$$reg != $src$$reg) {
+ __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
+ }
+ %}
+ ins_pipe( fpu_reg_reg );
+ %}
+
// Load Effective Address
instruct leaP8(rRegP dst, indOffset8 mem)
%{
match(Set dst mem);
< prev index next >