1 //
2 // Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers (including RSP and RBP)
173 reg_class any_reg_with_rbp(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP, but excluding RBP)
191 reg_class any_reg_no_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RDI, RDI_H,
194 RSI, RSI_H,
195 RCX, RCX_H,
196 RBX, RBX_H,
197 RSP, RSP_H,
198 R8, R8_H,
199 R9, R9_H,
200 R10, R10_H,
201 R11, R11_H,
202 R12, R12_H,
203 R13, R13_H,
204 R14, R14_H,
205 R15, R15_H);
206
207 // Dynamic register class that selects at runtime between register classes
208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
211
212 // Class for all pointer registers (excluding RSP)
213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
214 RDX, RDX_H,
215 RBP, RBP_H,
216 RDI, RDI_H,
217 RSI, RSI_H,
218 RCX, RCX_H,
219 RBX, RBX_H,
220 R8, R8_H,
221 R9, R9_H,
222 R10, R10_H,
223 R11, R11_H,
224 R13, R13_H,
225 R14, R14_H);
226
227 // Class for all pointer registers (excluding RSP and RBP)
228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
229 RDX, RDX_H,
230 RDI, RDI_H,
231 RSI, RSI_H,
232 RCX, RCX_H,
233 RBX, RBX_H,
234 R8, R8_H,
235 R9, R9_H,
236 R10, R10_H,
237 R11, R11_H,
238 R13, R13_H,
239 R14, R14_H);
240
241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
243
244 // Class for all pointer registers (excluding RAX and RSP)
245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
246 RBP, RBP_H,
247 RDI, RDI_H,
248 RSI, RSI_H,
249 RCX, RCX_H,
250 RBX, RBX_H,
251 R8, R8_H,
252 R9, R9_H,
253 R10, R10_H,
254 R11, R11_H,
255 R13, R13_H,
256 R14, R14_H);
257
258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
260 RDI, RDI_H,
261 RSI, RSI_H,
262 RCX, RCX_H,
263 RBX, RBX_H,
264 R8, R8_H,
265 R9, R9_H,
266 R10, R10_H,
267 R11, R11_H,
268 R13, R13_H,
269 R14, R14_H);
270
271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
273
274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
276 RBP, RBP_H,
277 RDI, RDI_H,
278 RSI, RSI_H,
279 RCX, RCX_H,
280 R8, R8_H,
281 R9, R9_H,
282 R10, R10_H,
283 R11, R11_H,
284 R13, R13_H,
285 R14, R14_H);
286
287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 R8, R8_H,
293 R9, R9_H,
294 R10, R10_H,
295 R11, R11_H,
296 R13, R13_H,
297 R14, R14_H);
298
299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
301
302 // Singleton class for RAX pointer register
303 reg_class ptr_rax_reg(RAX, RAX_H);
304
305 // Singleton class for RBX pointer register
306 reg_class ptr_rbx_reg(RBX, RBX_H);
307
308 // Singleton class for RSI pointer register
309 reg_class ptr_rsi_reg(RSI, RSI_H);
310
311 // Singleton class for RDI pointer register
312 reg_class ptr_rdi_reg(RDI, RDI_H);
313
314 // Singleton class for stack pointer
315 reg_class ptr_rsp_reg(RSP, RSP_H);
316
317 // Singleton class for TLS pointer
318 reg_class ptr_r15_reg(R15, R15_H);
319
320 // Class for all long registers (excluding RSP)
321 reg_class long_reg_with_rbp(RAX, RAX_H,
322 RDX, RDX_H,
323 RBP, RBP_H,
324 RDI, RDI_H,
325 RSI, RSI_H,
326 RCX, RCX_H,
327 RBX, RBX_H,
328 R8, R8_H,
329 R9, R9_H,
330 R10, R10_H,
331 R11, R11_H,
332 R13, R13_H,
333 R14, R14_H);
334
335 // Class for all long registers (excluding RSP and RBP)
336 reg_class long_reg_no_rbp(RAX, RAX_H,
337 RDX, RDX_H,
338 RDI, RDI_H,
339 RSI, RSI_H,
340 RCX, RCX_H,
341 RBX, RBX_H,
342 R8, R8_H,
343 R9, R9_H,
344 R10, R10_H,
345 R11, R11_H,
346 R13, R13_H,
347 R14, R14_H);
348
349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
351
352 // Class for all long registers (excluding RAX, RDX and RSP)
353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
354 RDI, RDI_H,
355 RSI, RSI_H,
356 RCX, RCX_H,
357 RBX, RBX_H,
358 R8, R8_H,
359 R9, R9_H,
360 R10, R10_H,
361 R11, R11_H,
362 R13, R13_H,
363 R14, R14_H);
364
365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
367 RSI, RSI_H,
368 RCX, RCX_H,
369 RBX, RBX_H,
370 R8, R8_H,
371 R9, R9_H,
372 R10, R10_H,
373 R11, R11_H,
374 R13, R13_H,
375 R14, R14_H);
376
377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
379
380 // Class for all long registers (excluding RCX and RSP)
381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
382 RDI, RDI_H,
383 RSI, RSI_H,
384 RAX, RAX_H,
385 RDX, RDX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers (excluding RCX, RSP, and RBP)
395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
396 RSI, RSI_H,
397 RAX, RAX_H,
398 RDX, RDX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
409
410 // Singleton class for RAX long register
411 reg_class long_rax_reg(RAX, RAX_H);
412
413 // Singleton class for RCX long register
414 reg_class long_rcx_reg(RCX, RCX_H);
415
416 // Singleton class for RDX long register
417 reg_class long_rdx_reg(RDX, RDX_H);
418
419 // Class for all int registers (excluding RSP)
420 reg_class int_reg_with_rbp(RAX,
421 RDX,
422 RBP,
423 RDI,
424 RSI,
425 RCX,
426 RBX,
427 R8,
428 R9,
429 R10,
430 R11,
431 R13,
432 R14);
433
434 // Class for all int registers (excluding RSP and RBP)
435 reg_class int_reg_no_rbp(RAX,
436 RDX,
437 RDI,
438 RSI,
439 RCX,
440 RBX,
441 R8,
442 R9,
443 R10,
444 R11,
445 R13,
446 R14);
447
448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
450
451 // Class for all int registers (excluding RCX and RSP)
452 reg_class int_no_rcx_reg_with_rbp(RAX,
453 RDX,
454 RBP,
455 RDI,
456 RSI,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
464
465 // Class for all int registers (excluding RCX, RSP, and RBP)
466 reg_class int_no_rcx_reg_no_rbp(RAX,
467 RDX,
468 RDI,
469 RSI,
470 RBX,
471 R8,
472 R9,
473 R10,
474 R11,
475 R13,
476 R14);
477
478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
480
481 // Class for all int registers (excluding RAX, RDX, and RSP)
482 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
483 RDI,
484 RSI,
485 RCX,
486 RBX,
487 R8,
488 R9,
489 R10,
490 R11,
491 R13,
492 R14);
493
494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
495 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
496 RSI,
497 RCX,
498 RBX,
499 R8,
500 R9,
501 R10,
502 R11,
503 R13,
504 R14);
505
506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
508
509 // Singleton class for RAX int register
510 reg_class int_rax_reg(RAX);
511
512 // Singleton class for RBX int register
513 reg_class int_rbx_reg(RBX);
514
515 // Singleton class for RCX int register
516 reg_class int_rcx_reg(RCX);
517
518 // Singleton class for RCX int register
519 reg_class int_rdx_reg(RDX);
520
521 // Singleton class for RCX int register
522 reg_class int_rdi_reg(RDI);
523
524 // Singleton class for instruction pointer
525 // reg_class ip_reg(RIP);
526
527 %}
528
529 //----------SOURCE BLOCK-------------------------------------------------------
530 // This is a block of C++ code which provides values, functions, and
531 // definitions necessary in the rest of the architecture description
532 source %{
533 #define RELOC_IMM64 Assembler::imm_operand
534 #define RELOC_DISP32 Assembler::disp32_operand
535
536 #define __ _masm.
537
538 static bool generate_vzeroupper(Compile* C) {
539 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
540 }
541
542 static int clear_avx_size() {
543 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
544 }
545
546 // !!!!! Special hack to get all types of calls to specify the byte offset
547 // from the start of the call to the point where the return address
548 // will point.
549 int MachCallStaticJavaNode::ret_addr_offset()
550 {
551 int offset = 5; // 5 bytes from start of call to where return address points
552 offset += clear_avx_size();
553 return offset;
554 }
555
556 int MachCallDynamicJavaNode::ret_addr_offset()
557 {
558 int offset = 15; // 15 bytes from start of call to where return address points
559 offset += clear_avx_size();
560 return offset;
561 }
562
563 int MachCallRuntimeNode::ret_addr_offset() {
564 int offset = 13; // movq r10,#addr; callq (r10)
565 offset += clear_avx_size();
566 return offset;
567 }
568
569 // Indicate if the safepoint node needs the polling page as an input,
570 // it does if the polling page is more than disp32 away.
571 bool SafePointNode::needs_polling_address_input()
572 {
573 return SafepointMechanism::uses_thread_local_poll() || Assembler::is_polling_page_far();
574 }
575
576 //
577 // Compute padding required for nodes which need alignment
578 //
579
580 // The address of the call instruction needs to be 4-byte aligned to
581 // ensure that it does not span a cache line so that it can be patched.
582 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
583 {
584 current_offset += clear_avx_size(); // skip vzeroupper
585 current_offset += 1; // skip call opcode byte
586 return align_up(current_offset, alignment_required()) - current_offset;
587 }
588
589 // The address of the call instruction needs to be 4-byte aligned to
590 // ensure that it does not span a cache line so that it can be patched.
591 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
592 {
593 current_offset += clear_avx_size(); // skip vzeroupper
594 current_offset += 11; // skip movq instruction + call opcode byte
595 return align_up(current_offset, alignment_required()) - current_offset;
596 }
597
598 // EMIT_RM()
599 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
600 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
601 cbuf.insts()->emit_int8(c);
602 }
603
604 // EMIT_CC()
605 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
606 unsigned char c = (unsigned char) (f1 | f2);
607 cbuf.insts()->emit_int8(c);
608 }
609
610 // EMIT_OPCODE()
611 void emit_opcode(CodeBuffer &cbuf, int code) {
612 cbuf.insts()->emit_int8((unsigned char) code);
613 }
614
615 // EMIT_OPCODE() w/ relocation information
616 void emit_opcode(CodeBuffer &cbuf,
617 int code, relocInfo::relocType reloc, int offset, int format)
618 {
619 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
620 emit_opcode(cbuf, code);
621 }
622
623 // EMIT_D8()
624 void emit_d8(CodeBuffer &cbuf, int d8) {
625 cbuf.insts()->emit_int8((unsigned char) d8);
626 }
627
628 // EMIT_D16()
629 void emit_d16(CodeBuffer &cbuf, int d16) {
630 cbuf.insts()->emit_int16(d16);
631 }
632
633 // EMIT_D32()
634 void emit_d32(CodeBuffer &cbuf, int d32) {
635 cbuf.insts()->emit_int32(d32);
636 }
637
638 // EMIT_D64()
639 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
640 cbuf.insts()->emit_int64(d64);
641 }
642
643 // emit 32 bit value and construct relocation entry from relocInfo::relocType
644 void emit_d32_reloc(CodeBuffer& cbuf,
645 int d32,
646 relocInfo::relocType reloc,
647 int format)
648 {
649 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
650 cbuf.relocate(cbuf.insts_mark(), reloc, format);
651 cbuf.insts()->emit_int32(d32);
652 }
653
654 // emit 32 bit value and construct relocation entry from RelocationHolder
655 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
656 #ifdef ASSERT
657 if (rspec.reloc()->type() == relocInfo::oop_type &&
658 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
659 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
660 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop((intptr_t)d32))), "cannot embed scavengable oops in code");
661 }
662 #endif
663 cbuf.relocate(cbuf.insts_mark(), rspec, format);
664 cbuf.insts()->emit_int32(d32);
665 }
666
667 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
668 address next_ip = cbuf.insts_end() + 4;
669 emit_d32_reloc(cbuf, (int) (addr - next_ip),
670 external_word_Relocation::spec(addr),
671 RELOC_DISP32);
672 }
673
674
675 // emit 64 bit value and construct relocation entry from relocInfo::relocType
676 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
677 cbuf.relocate(cbuf.insts_mark(), reloc, format);
678 cbuf.insts()->emit_int64(d64);
679 }
680
681 // emit 64 bit value and construct relocation entry from RelocationHolder
682 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
683 #ifdef ASSERT
684 if (rspec.reloc()->type() == relocInfo::oop_type &&
685 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
686 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
687 assert(oopDesc::is_oop(cast_to_oop(d64)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop(d64))),
688 "cannot embed scavengable oops in code");
689 }
690 #endif
691 cbuf.relocate(cbuf.insts_mark(), rspec, format);
692 cbuf.insts()->emit_int64(d64);
693 }
694
695 // Access stack slot for load or store
696 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
697 {
698 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
699 if (-0x80 <= disp && disp < 0x80) {
700 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
701 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
702 emit_d8(cbuf, disp); // Displacement // R/M byte
703 } else {
704 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
705 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
706 emit_d32(cbuf, disp); // Displacement // R/M byte
707 }
708 }
709
710 // rRegI ereg, memory mem) %{ // emit_reg_mem
711 void encode_RegMem(CodeBuffer &cbuf,
712 int reg,
713 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
714 {
715 assert(disp_reloc == relocInfo::none, "cannot have disp");
716 int regenc = reg & 7;
717 int baseenc = base & 7;
718 int indexenc = index & 7;
719
720 // There is no index & no scale, use form without SIB byte
721 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
722 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
723 if (disp == 0 && base != RBP_enc && base != R13_enc) {
724 emit_rm(cbuf, 0x0, regenc, baseenc); // *
725 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
726 // If 8-bit displacement, mode 0x1
727 emit_rm(cbuf, 0x1, regenc, baseenc); // *
728 emit_d8(cbuf, disp);
729 } else {
730 // If 32-bit displacement
731 if (base == -1) { // Special flag for absolute address
732 emit_rm(cbuf, 0x0, regenc, 0x5); // *
733 if (disp_reloc != relocInfo::none) {
734 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
735 } else {
736 emit_d32(cbuf, disp);
737 }
738 } else {
739 // Normal base + offset
740 emit_rm(cbuf, 0x2, regenc, baseenc); // *
741 if (disp_reloc != relocInfo::none) {
742 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
743 } else {
744 emit_d32(cbuf, disp);
745 }
746 }
747 }
748 } else {
749 // Else, encode with the SIB byte
750 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
751 if (disp == 0 && base != RBP_enc && base != R13_enc) {
752 // If no displacement
753 emit_rm(cbuf, 0x0, regenc, 0x4); // *
754 emit_rm(cbuf, scale, indexenc, baseenc);
755 } else {
756 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
757 // If 8-bit displacement, mode 0x1
758 emit_rm(cbuf, 0x1, regenc, 0x4); // *
759 emit_rm(cbuf, scale, indexenc, baseenc);
760 emit_d8(cbuf, disp);
761 } else {
762 // If 32-bit displacement
763 if (base == 0x04 ) {
764 emit_rm(cbuf, 0x2, regenc, 0x4);
765 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
766 } else {
767 emit_rm(cbuf, 0x2, regenc, 0x4);
768 emit_rm(cbuf, scale, indexenc, baseenc); // *
769 }
770 if (disp_reloc != relocInfo::none) {
771 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
772 } else {
773 emit_d32(cbuf, disp);
774 }
775 }
776 }
777 }
778 }
779
780 // This could be in MacroAssembler but it's fairly C2 specific
781 void emit_cmpfp_fixup(MacroAssembler& _masm) {
782 Label exit;
783 __ jccb(Assembler::noParity, exit);
784 __ pushf();
785 //
786 // comiss/ucomiss instructions set ZF,PF,CF flags and
787 // zero OF,AF,SF for NaN values.
788 // Fixup flags by zeroing ZF,PF so that compare of NaN
789 // values returns 'less than' result (CF is set).
790 // Leave the rest of flags unchanged.
791 //
792 // 7 6 5 4 3 2 1 0
793 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
794 // 0 0 1 0 1 0 1 1 (0x2B)
795 //
796 __ andq(Address(rsp, 0), 0xffffff2b);
797 __ popf();
798 __ bind(exit);
799 }
800
801 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
802 Label done;
803 __ movl(dst, -1);
804 __ jcc(Assembler::parity, done);
805 __ jcc(Assembler::below, done);
806 __ setb(Assembler::notEqual, dst);
807 __ movzbl(dst, dst);
808 __ bind(done);
809 }
810
811
812 //=============================================================================
813 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
814
815 int Compile::ConstantTable::calculate_table_base_offset() const {
816 return 0; // absolute addressing, no offset
817 }
818
819 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
820 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
821 ShouldNotReachHere();
822 }
823
824 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
825 // Empty encoding
826 }
827
828 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
829 return 0;
830 }
831
832 #ifndef PRODUCT
833 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
834 st->print("# MachConstantBaseNode (empty encoding)");
835 }
836 #endif
837
838
839 //=============================================================================
840 #ifndef PRODUCT
841 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
842 Compile* C = ra_->C;
843
844 int framesize = C->frame_size_in_bytes();
845 int bangsize = C->bang_size_in_bytes();
846 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
847 // Remove wordSize for return addr which is already pushed.
848 framesize -= wordSize;
849
850 if (C->need_stack_bang(bangsize)) {
851 framesize -= wordSize;
852 st->print("# stack bang (%d bytes)", bangsize);
853 st->print("\n\t");
854 st->print("pushq rbp\t# Save rbp");
855 if (PreserveFramePointer) {
856 st->print("\n\t");
857 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
858 }
859 if (framesize) {
860 st->print("\n\t");
861 st->print("subq rsp, #%d\t# Create frame",framesize);
862 }
863 } else {
864 st->print("subq rsp, #%d\t# Create frame",framesize);
865 st->print("\n\t");
866 framesize -= wordSize;
867 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
868 if (PreserveFramePointer) {
869 st->print("\n\t");
870 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
871 if (framesize > 0) {
872 st->print("\n\t");
873 st->print("addq rbp, #%d", framesize);
874 }
875 }
876 }
877
878 if (VerifyStackAtCalls) {
879 st->print("\n\t");
880 framesize -= wordSize;
881 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
882 #ifdef ASSERT
883 st->print("\n\t");
884 st->print("# stack alignment check");
885 #endif
886 }
887 if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
888 st->print("\n\t");
889 st->print("cmpl [r15_thread + #disarmed_offset], #disarmed_value\t");
890 st->print("\n\t");
891 st->print("je fast_entry\t");
892 st->print("\n\t");
893 st->print("call #nmethod_entry_barrier_stub\t");
894 st->print("\n\tfast_entry:");
895 }
896 st->cr();
897 }
898 #endif
899
900 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
901 Compile* C = ra_->C;
902 MacroAssembler _masm(&cbuf);
903
904 int framesize = C->frame_size_in_bytes();
905 int bangsize = C->bang_size_in_bytes();
906
907 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL);
908
909 C->set_frame_complete(cbuf.insts_size());
910
911 if (C->has_mach_constant_base_node()) {
912 // NOTE: We set the table base offset here because users might be
913 // emitted before MachConstantBaseNode.
914 Compile::ConstantTable& constant_table = C->constant_table();
915 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
916 }
917 }
918
919 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
920 {
921 return MachNode::size(ra_); // too many variables; just compute it
922 // the hard way
923 }
924
925 int MachPrologNode::reloc() const
926 {
927 return 0; // a large enough number
928 }
929
930 //=============================================================================
931 #ifndef PRODUCT
932 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
933 {
934 Compile* C = ra_->C;
935 if (generate_vzeroupper(C)) {
936 st->print("vzeroupper");
937 st->cr(); st->print("\t");
938 }
939
940 int framesize = C->frame_size_in_bytes();
941 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
942 // Remove word for return adr already pushed
943 // and RBP
944 framesize -= 2*wordSize;
945
946 if (framesize) {
947 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
948 st->print("\t");
949 }
950
951 st->print_cr("popq rbp");
952 if (do_polling() && C->is_method_compilation()) {
953 st->print("\t");
954 if (SafepointMechanism::uses_thread_local_poll()) {
955 st->print_cr("movq rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
956 "testl rax, [rscratch1]\t"
957 "# Safepoint: poll for GC");
958 } else if (Assembler::is_polling_page_far()) {
959 st->print_cr("movq rscratch1, #polling_page_address\n\t"
960 "testl rax, [rscratch1]\t"
961 "# Safepoint: poll for GC");
962 } else {
963 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
964 "# Safepoint: poll for GC");
965 }
966 }
967 }
968 #endif
969
970 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
971 {
972 Compile* C = ra_->C;
973 MacroAssembler _masm(&cbuf);
974
975 if (generate_vzeroupper(C)) {
976 // Clear upper bits of YMM registers when current compiled code uses
977 // wide vectors to avoid AVX <-> SSE transition penalty during call.
978 __ vzeroupper();
979 }
980
981 int framesize = C->frame_size_in_bytes();
982 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
983 // Remove word for return adr already pushed
984 // and RBP
985 framesize -= 2*wordSize;
986
987 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
988
989 if (framesize) {
990 emit_opcode(cbuf, Assembler::REX_W);
991 if (framesize < 0x80) {
992 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
993 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
994 emit_d8(cbuf, framesize);
995 } else {
996 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
997 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
998 emit_d32(cbuf, framesize);
999 }
1000 }
1001
1002 // popq rbp
1003 emit_opcode(cbuf, 0x58 | RBP_enc);
1004
1005 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1006 __ reserved_stack_check();
1007 }
1008
1009 if (do_polling() && C->is_method_compilation()) {
1010 MacroAssembler _masm(&cbuf);
1011 if (SafepointMechanism::uses_thread_local_poll()) {
1012 __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
1013 __ relocate(relocInfo::poll_return_type);
1014 __ testl(rax, Address(rscratch1, 0));
1015 } else {
1016 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
1017 if (Assembler::is_polling_page_far()) {
1018 __ lea(rscratch1, polling_page);
1019 __ relocate(relocInfo::poll_return_type);
1020 __ testl(rax, Address(rscratch1, 0));
1021 } else {
1022 __ testl(rax, polling_page);
1023 }
1024 }
1025 }
1026 }
1027
1028 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1029 {
1030 return MachNode::size(ra_); // too many variables; just compute it
1031 // the hard way
1032 }
1033
1034 int MachEpilogNode::reloc() const
1035 {
1036 return 2; // a large enough number
1037 }
1038
1039 const Pipeline* MachEpilogNode::pipeline() const
1040 {
1041 return MachNode::pipeline_class();
1042 }
1043
1044 int MachEpilogNode::safepoint_offset() const
1045 {
1046 return 0;
1047 }
1048
1049 //=============================================================================
1050
1051 enum RC {
1052 rc_bad,
1053 rc_int,
1054 rc_float,
1055 rc_stack
1056 };
1057
1058 static enum RC rc_class(OptoReg::Name reg)
1059 {
1060 if( !OptoReg::is_valid(reg) ) return rc_bad;
1061
1062 if (OptoReg::is_stack(reg)) return rc_stack;
1063
1064 VMReg r = OptoReg::as_VMReg(reg);
1065
1066 if (r->is_Register()) return rc_int;
1067
1068 assert(r->is_XMMRegister(), "must be");
1069 return rc_float;
1070 }
1071
1072 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1073 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1074 int src_hi, int dst_hi, uint ireg, outputStream* st);
1075
1076 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1077 int stack_offset, int reg, uint ireg, outputStream* st);
1078
1079 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1080 int dst_offset, uint ireg, outputStream* st) {
1081 if (cbuf) {
1082 MacroAssembler _masm(cbuf);
1083 switch (ireg) {
1084 case Op_VecS:
1085 __ movq(Address(rsp, -8), rax);
1086 __ movl(rax, Address(rsp, src_offset));
1087 __ movl(Address(rsp, dst_offset), rax);
1088 __ movq(rax, Address(rsp, -8));
1089 break;
1090 case Op_VecD:
1091 __ pushq(Address(rsp, src_offset));
1092 __ popq (Address(rsp, dst_offset));
1093 break;
1094 case Op_VecX:
1095 __ pushq(Address(rsp, src_offset));
1096 __ popq (Address(rsp, dst_offset));
1097 __ pushq(Address(rsp, src_offset+8));
1098 __ popq (Address(rsp, dst_offset+8));
1099 break;
1100 case Op_VecY:
1101 __ vmovdqu(Address(rsp, -32), xmm0);
1102 __ vmovdqu(xmm0, Address(rsp, src_offset));
1103 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1104 __ vmovdqu(xmm0, Address(rsp, -32));
1105 break;
1106 case Op_VecZ:
1107 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1108 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1109 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1110 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1111 break;
1112 default:
1113 ShouldNotReachHere();
1114 }
1115 #ifndef PRODUCT
1116 } else {
1117 switch (ireg) {
1118 case Op_VecS:
1119 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1120 "movl rax, [rsp + #%d]\n\t"
1121 "movl [rsp + #%d], rax\n\t"
1122 "movq rax, [rsp - #8]",
1123 src_offset, dst_offset);
1124 break;
1125 case Op_VecD:
1126 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1127 "popq [rsp + #%d]",
1128 src_offset, dst_offset);
1129 break;
1130 case Op_VecX:
1131 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1132 "popq [rsp + #%d]\n\t"
1133 "pushq [rsp + #%d]\n\t"
1134 "popq [rsp + #%d]",
1135 src_offset, dst_offset, src_offset+8, dst_offset+8);
1136 break;
1137 case Op_VecY:
1138 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1139 "vmovdqu xmm0, [rsp + #%d]\n\t"
1140 "vmovdqu [rsp + #%d], xmm0\n\t"
1141 "vmovdqu xmm0, [rsp - #32]",
1142 src_offset, dst_offset);
1143 break;
1144 case Op_VecZ:
1145 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1146 "vmovdqu xmm0, [rsp + #%d]\n\t"
1147 "vmovdqu [rsp + #%d], xmm0\n\t"
1148 "vmovdqu xmm0, [rsp - #64]",
1149 src_offset, dst_offset);
1150 break;
1151 default:
1152 ShouldNotReachHere();
1153 }
1154 #endif
1155 }
1156 }
1157
1158 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1159 PhaseRegAlloc* ra_,
1160 bool do_size,
1161 outputStream* st) const {
1162 assert(cbuf != NULL || st != NULL, "sanity");
1163 // Get registers to move
1164 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1165 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1166 OptoReg::Name dst_second = ra_->get_reg_second(this);
1167 OptoReg::Name dst_first = ra_->get_reg_first(this);
1168
1169 enum RC src_second_rc = rc_class(src_second);
1170 enum RC src_first_rc = rc_class(src_first);
1171 enum RC dst_second_rc = rc_class(dst_second);
1172 enum RC dst_first_rc = rc_class(dst_first);
1173
1174 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1175 "must move at least 1 register" );
1176
1177 if (src_first == dst_first && src_second == dst_second) {
1178 // Self copy, no move
1179 return 0;
1180 }
1181 if (bottom_type()->isa_vect() != NULL) {
1182 uint ireg = ideal_reg();
1183 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1184 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1185 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1186 // mem -> mem
1187 int src_offset = ra_->reg2offset(src_first);
1188 int dst_offset = ra_->reg2offset(dst_first);
1189 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1190 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1191 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1192 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1193 int stack_offset = ra_->reg2offset(dst_first);
1194 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1195 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1196 int stack_offset = ra_->reg2offset(src_first);
1197 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1198 } else {
1199 ShouldNotReachHere();
1200 }
1201 return 0;
1202 }
1203 if (src_first_rc == rc_stack) {
1204 // mem ->
1205 if (dst_first_rc == rc_stack) {
1206 // mem -> mem
1207 assert(src_second != dst_first, "overlap");
1208 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1209 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1210 // 64-bit
1211 int src_offset = ra_->reg2offset(src_first);
1212 int dst_offset = ra_->reg2offset(dst_first);
1213 if (cbuf) {
1214 MacroAssembler _masm(cbuf);
1215 __ pushq(Address(rsp, src_offset));
1216 __ popq (Address(rsp, dst_offset));
1217 #ifndef PRODUCT
1218 } else {
1219 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1220 "popq [rsp + #%d]",
1221 src_offset, dst_offset);
1222 #endif
1223 }
1224 } else {
1225 // 32-bit
1226 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1227 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1228 // No pushl/popl, so:
1229 int src_offset = ra_->reg2offset(src_first);
1230 int dst_offset = ra_->reg2offset(dst_first);
1231 if (cbuf) {
1232 MacroAssembler _masm(cbuf);
1233 __ movq(Address(rsp, -8), rax);
1234 __ movl(rax, Address(rsp, src_offset));
1235 __ movl(Address(rsp, dst_offset), rax);
1236 __ movq(rax, Address(rsp, -8));
1237 #ifndef PRODUCT
1238 } else {
1239 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1240 "movl rax, [rsp + #%d]\n\t"
1241 "movl [rsp + #%d], rax\n\t"
1242 "movq rax, [rsp - #8]",
1243 src_offset, dst_offset);
1244 #endif
1245 }
1246 }
1247 return 0;
1248 } else if (dst_first_rc == rc_int) {
1249 // mem -> gpr
1250 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1251 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1252 // 64-bit
1253 int offset = ra_->reg2offset(src_first);
1254 if (cbuf) {
1255 MacroAssembler _masm(cbuf);
1256 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1257 #ifndef PRODUCT
1258 } else {
1259 st->print("movq %s, [rsp + #%d]\t# spill",
1260 Matcher::regName[dst_first],
1261 offset);
1262 #endif
1263 }
1264 } else {
1265 // 32-bit
1266 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1267 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1268 int offset = ra_->reg2offset(src_first);
1269 if (cbuf) {
1270 MacroAssembler _masm(cbuf);
1271 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1272 #ifndef PRODUCT
1273 } else {
1274 st->print("movl %s, [rsp + #%d]\t# spill",
1275 Matcher::regName[dst_first],
1276 offset);
1277 #endif
1278 }
1279 }
1280 return 0;
1281 } else if (dst_first_rc == rc_float) {
1282 // mem-> xmm
1283 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1284 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1285 // 64-bit
1286 int offset = ra_->reg2offset(src_first);
1287 if (cbuf) {
1288 MacroAssembler _masm(cbuf);
1289 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1290 #ifndef PRODUCT
1291 } else {
1292 st->print("%s %s, [rsp + #%d]\t# spill",
1293 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1294 Matcher::regName[dst_first],
1295 offset);
1296 #endif
1297 }
1298 } else {
1299 // 32-bit
1300 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1301 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1302 int offset = ra_->reg2offset(src_first);
1303 if (cbuf) {
1304 MacroAssembler _masm(cbuf);
1305 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1306 #ifndef PRODUCT
1307 } else {
1308 st->print("movss %s, [rsp + #%d]\t# spill",
1309 Matcher::regName[dst_first],
1310 offset);
1311 #endif
1312 }
1313 }
1314 return 0;
1315 }
1316 } else if (src_first_rc == rc_int) {
1317 // gpr ->
1318 if (dst_first_rc == rc_stack) {
1319 // gpr -> mem
1320 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1321 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1322 // 64-bit
1323 int offset = ra_->reg2offset(dst_first);
1324 if (cbuf) {
1325 MacroAssembler _masm(cbuf);
1326 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1327 #ifndef PRODUCT
1328 } else {
1329 st->print("movq [rsp + #%d], %s\t# spill",
1330 offset,
1331 Matcher::regName[src_first]);
1332 #endif
1333 }
1334 } else {
1335 // 32-bit
1336 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1337 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1338 int offset = ra_->reg2offset(dst_first);
1339 if (cbuf) {
1340 MacroAssembler _masm(cbuf);
1341 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1342 #ifndef PRODUCT
1343 } else {
1344 st->print("movl [rsp + #%d], %s\t# spill",
1345 offset,
1346 Matcher::regName[src_first]);
1347 #endif
1348 }
1349 }
1350 return 0;
1351 } else if (dst_first_rc == rc_int) {
1352 // gpr -> gpr
1353 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1354 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1355 // 64-bit
1356 if (cbuf) {
1357 MacroAssembler _masm(cbuf);
1358 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1359 as_Register(Matcher::_regEncode[src_first]));
1360 #ifndef PRODUCT
1361 } else {
1362 st->print("movq %s, %s\t# spill",
1363 Matcher::regName[dst_first],
1364 Matcher::regName[src_first]);
1365 #endif
1366 }
1367 return 0;
1368 } else {
1369 // 32-bit
1370 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1371 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1372 if (cbuf) {
1373 MacroAssembler _masm(cbuf);
1374 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1375 as_Register(Matcher::_regEncode[src_first]));
1376 #ifndef PRODUCT
1377 } else {
1378 st->print("movl %s, %s\t# spill",
1379 Matcher::regName[dst_first],
1380 Matcher::regName[src_first]);
1381 #endif
1382 }
1383 return 0;
1384 }
1385 } else if (dst_first_rc == rc_float) {
1386 // gpr -> xmm
1387 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1388 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1389 // 64-bit
1390 if (cbuf) {
1391 MacroAssembler _masm(cbuf);
1392 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1393 #ifndef PRODUCT
1394 } else {
1395 st->print("movdq %s, %s\t# spill",
1396 Matcher::regName[dst_first],
1397 Matcher::regName[src_first]);
1398 #endif
1399 }
1400 } else {
1401 // 32-bit
1402 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1403 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1404 if (cbuf) {
1405 MacroAssembler _masm(cbuf);
1406 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1407 #ifndef PRODUCT
1408 } else {
1409 st->print("movdl %s, %s\t# spill",
1410 Matcher::regName[dst_first],
1411 Matcher::regName[src_first]);
1412 #endif
1413 }
1414 }
1415 return 0;
1416 }
1417 } else if (src_first_rc == rc_float) {
1418 // xmm ->
1419 if (dst_first_rc == rc_stack) {
1420 // xmm -> mem
1421 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1422 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1423 // 64-bit
1424 int offset = ra_->reg2offset(dst_first);
1425 if (cbuf) {
1426 MacroAssembler _masm(cbuf);
1427 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1428 #ifndef PRODUCT
1429 } else {
1430 st->print("movsd [rsp + #%d], %s\t# spill",
1431 offset,
1432 Matcher::regName[src_first]);
1433 #endif
1434 }
1435 } else {
1436 // 32-bit
1437 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1438 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1439 int offset = ra_->reg2offset(dst_first);
1440 if (cbuf) {
1441 MacroAssembler _masm(cbuf);
1442 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1443 #ifndef PRODUCT
1444 } else {
1445 st->print("movss [rsp + #%d], %s\t# spill",
1446 offset,
1447 Matcher::regName[src_first]);
1448 #endif
1449 }
1450 }
1451 return 0;
1452 } else if (dst_first_rc == rc_int) {
1453 // xmm -> gpr
1454 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1455 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1456 // 64-bit
1457 if (cbuf) {
1458 MacroAssembler _masm(cbuf);
1459 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1460 #ifndef PRODUCT
1461 } else {
1462 st->print("movdq %s, %s\t# spill",
1463 Matcher::regName[dst_first],
1464 Matcher::regName[src_first]);
1465 #endif
1466 }
1467 } else {
1468 // 32-bit
1469 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1470 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1471 if (cbuf) {
1472 MacroAssembler _masm(cbuf);
1473 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1474 #ifndef PRODUCT
1475 } else {
1476 st->print("movdl %s, %s\t# spill",
1477 Matcher::regName[dst_first],
1478 Matcher::regName[src_first]);
1479 #endif
1480 }
1481 }
1482 return 0;
1483 } else if (dst_first_rc == rc_float) {
1484 // xmm -> xmm
1485 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1486 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1487 // 64-bit
1488 if (cbuf) {
1489 MacroAssembler _masm(cbuf);
1490 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1491 #ifndef PRODUCT
1492 } else {
1493 st->print("%s %s, %s\t# spill",
1494 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1495 Matcher::regName[dst_first],
1496 Matcher::regName[src_first]);
1497 #endif
1498 }
1499 } else {
1500 // 32-bit
1501 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1502 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1503 if (cbuf) {
1504 MacroAssembler _masm(cbuf);
1505 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1506 #ifndef PRODUCT
1507 } else {
1508 st->print("%s %s, %s\t# spill",
1509 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1510 Matcher::regName[dst_first],
1511 Matcher::regName[src_first]);
1512 #endif
1513 }
1514 }
1515 return 0;
1516 }
1517 }
1518
1519 assert(0," foo ");
1520 Unimplemented();
1521 return 0;
1522 }
1523
1524 #ifndef PRODUCT
1525 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1526 implementation(NULL, ra_, false, st);
1527 }
1528 #endif
1529
1530 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1531 implementation(&cbuf, ra_, false, NULL);
1532 }
1533
1534 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1535 return MachNode::size(ra_);
1536 }
1537
1538 //=============================================================================
1539 #ifndef PRODUCT
1540 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1541 {
1542 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1543 int reg = ra_->get_reg_first(this);
1544 st->print("leaq %s, [rsp + #%d]\t# box lock",
1545 Matcher::regName[reg], offset);
1546 }
1547 #endif
1548
1549 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1550 {
1551 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1552 int reg = ra_->get_encode(this);
1553 if (offset >= 0x80) {
1554 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1555 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1556 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1557 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1558 emit_d32(cbuf, offset);
1559 } else {
1560 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1561 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1562 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1563 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1564 emit_d8(cbuf, offset);
1565 }
1566 }
1567
1568 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1569 {
1570 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1571 return (offset < 0x80) ? 5 : 8; // REX
1572 }
1573
1574 //=============================================================================
1575 #ifndef PRODUCT
1576 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1577 {
1578 if (UseCompressedClassPointers) {
1579 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1580 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1581 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1582 } else {
1583 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1584 "# Inline cache check");
1585 }
1586 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1587 st->print_cr("\tnop\t# nops to align entry point");
1588 }
1589 #endif
1590
1591 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1592 {
1593 MacroAssembler masm(&cbuf);
1594 uint insts_size = cbuf.insts_size();
1595 if (UseCompressedClassPointers) {
1596 masm.load_klass(rscratch1, j_rarg0);
1597 masm.cmpptr(rax, rscratch1);
1598 } else {
1599 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1600 }
1601
1602 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1603
1604 /* WARNING these NOPs are critical so that verified entry point is properly
1605 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1606 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1607 if (OptoBreakpoint) {
1608 // Leave space for int3
1609 nops_cnt -= 1;
1610 }
1611 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1612 if (nops_cnt > 0)
1613 masm.nop(nops_cnt);
1614 }
1615
1616 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1617 {
1618 return MachNode::size(ra_); // too many variables; just compute it
1619 // the hard way
1620 }
1621
1622
1623 //=============================================================================
1624
1625 int Matcher::regnum_to_fpu_offset(int regnum)
1626 {
1627 return regnum - 32; // The FP registers are in the second chunk
1628 }
1629
1630 // This is UltraSparc specific, true just means we have fast l2f conversion
1631 const bool Matcher::convL2FSupported(void) {
1632 return true;
1633 }
1634
1635 // Is this branch offset short enough that a short branch can be used?
1636 //
1637 // NOTE: If the platform does not provide any short branch variants, then
1638 // this method should return false for offset 0.
1639 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1640 // The passed offset is relative to address of the branch.
1641 // On 86 a branch displacement is calculated relative to address
1642 // of a next instruction.
1643 offset -= br_size;
1644
1645 // the short version of jmpConUCF2 contains multiple branches,
1646 // making the reach slightly less
1647 if (rule == jmpConUCF2_rule)
1648 return (-126 <= offset && offset <= 125);
1649 return (-128 <= offset && offset <= 127);
1650 }
1651
1652 const bool Matcher::isSimpleConstant64(jlong value) {
1653 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1654 //return value == (int) value; // Cf. storeImmL and immL32.
1655
1656 // Probably always true, even if a temp register is required.
1657 return true;
1658 }
1659
1660 // The ecx parameter to rep stosq for the ClearArray node is in words.
1661 const bool Matcher::init_array_count_is_in_bytes = false;
1662
1663 // No additional cost for CMOVL.
1664 const int Matcher::long_cmove_cost() { return 0; }
1665
1666 // No CMOVF/CMOVD with SSE2
1667 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1668
1669 // Does the CPU require late expand (see block.cpp for description of late expand)?
1670 const bool Matcher::require_postalloc_expand = false;
1671
1672 // Do we need to mask the count passed to shift instructions or does
1673 // the cpu only look at the lower 5/6 bits anyway?
1674 const bool Matcher::need_masked_shift_count = false;
1675
1676 bool Matcher::narrow_oop_use_complex_address() {
1677 assert(UseCompressedOops, "only for compressed oops code");
1678 return (LogMinObjAlignmentInBytes <= 3);
1679 }
1680
1681 bool Matcher::narrow_klass_use_complex_address() {
1682 assert(UseCompressedClassPointers, "only for compressed klass code");
1683 return (LogKlassAlignmentInBytes <= 3);
1684 }
1685
1686 bool Matcher::const_oop_prefer_decode() {
1687 // Prefer ConN+DecodeN over ConP.
1688 return true;
1689 }
1690
1691 bool Matcher::const_klass_prefer_decode() {
1692 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1693 // or condisider the following:
1694 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1695 //return Universe::narrow_klass_base() == NULL;
1696 return true;
1697 }
1698
1699 // Is it better to copy float constants, or load them directly from
1700 // memory? Intel can load a float constant from a direct address,
1701 // requiring no extra registers. Most RISCs will have to materialize
1702 // an address into a register first, so they would do better to copy
1703 // the constant from stack.
1704 const bool Matcher::rematerialize_float_constants = true; // XXX
1705
1706 // If CPU can load and store mis-aligned doubles directly then no
1707 // fixup is needed. Else we split the double into 2 integer pieces
1708 // and move it piece-by-piece. Only happens when passing doubles into
1709 // C code as the Java calling convention forces doubles to be aligned.
1710 const bool Matcher::misaligned_doubles_ok = true;
1711
1712 // No-op on amd64
1713 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1714
1715 // Advertise here if the CPU requires explicit rounding operations to
1716 // implement the UseStrictFP mode.
1717 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1718
1719 // Are floats conerted to double when stored to stack during deoptimization?
1720 // On x64 it is stored without convertion so we can use normal access.
1721 bool Matcher::float_in_double() { return false; }
1722
1723 // Do ints take an entire long register or just half?
1724 const bool Matcher::int_in_long = true;
1725
1726 // Return whether or not this register is ever used as an argument.
1727 // This function is used on startup to build the trampoline stubs in
1728 // generateOptoStub. Registers not mentioned will be killed by the VM
1729 // call in the trampoline, and arguments in those registers not be
1730 // available to the callee.
1731 bool Matcher::can_be_java_arg(int reg)
1732 {
1733 return
1734 reg == RDI_num || reg == RDI_H_num ||
1735 reg == RSI_num || reg == RSI_H_num ||
1736 reg == RDX_num || reg == RDX_H_num ||
1737 reg == RCX_num || reg == RCX_H_num ||
1738 reg == R8_num || reg == R8_H_num ||
1739 reg == R9_num || reg == R9_H_num ||
1740 reg == R12_num || reg == R12_H_num ||
1741 reg == XMM0_num || reg == XMM0b_num ||
1742 reg == XMM1_num || reg == XMM1b_num ||
1743 reg == XMM2_num || reg == XMM2b_num ||
1744 reg == XMM3_num || reg == XMM3b_num ||
1745 reg == XMM4_num || reg == XMM4b_num ||
1746 reg == XMM5_num || reg == XMM5b_num ||
1747 reg == XMM6_num || reg == XMM6b_num ||
1748 reg == XMM7_num || reg == XMM7b_num;
1749 }
1750
1751 bool Matcher::is_spillable_arg(int reg)
1752 {
1753 return can_be_java_arg(reg);
1754 }
1755
1756 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1757 // In 64 bit mode a code which use multiply when
1758 // devisor is constant is faster than hardware
1759 // DIV instruction (it uses MulHiL).
1760 return false;
1761 }
1762
1763 // Register for DIVI projection of divmodI
1764 RegMask Matcher::divI_proj_mask() {
1765 return INT_RAX_REG_mask();
1766 }
1767
1768 // Register for MODI projection of divmodI
1769 RegMask Matcher::modI_proj_mask() {
1770 return INT_RDX_REG_mask();
1771 }
1772
1773 // Register for DIVL projection of divmodL
1774 RegMask Matcher::divL_proj_mask() {
1775 return LONG_RAX_REG_mask();
1776 }
1777
1778 // Register for MODL projection of divmodL
1779 RegMask Matcher::modL_proj_mask() {
1780 return LONG_RDX_REG_mask();
1781 }
1782
1783 // Register for saving SP into on method handle invokes. Not used on x86_64.
1784 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1785 return NO_REG_mask();
1786 }
1787
1788 %}
1789
1790 //----------ENCODING BLOCK-----------------------------------------------------
1791 // This block specifies the encoding classes used by the compiler to
1792 // output byte streams. Encoding classes are parameterized macros
1793 // used by Machine Instruction Nodes in order to generate the bit
1794 // encoding of the instruction. Operands specify their base encoding
1795 // interface with the interface keyword. There are currently
1796 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1797 // COND_INTER. REG_INTER causes an operand to generate a function
1798 // which returns its register number when queried. CONST_INTER causes
1799 // an operand to generate a function which returns the value of the
1800 // constant when queried. MEMORY_INTER causes an operand to generate
1801 // four functions which return the Base Register, the Index Register,
1802 // the Scale Value, and the Offset Value of the operand when queried.
1803 // COND_INTER causes an operand to generate six functions which return
1804 // the encoding code (ie - encoding bits for the instruction)
1805 // associated with each basic boolean condition for a conditional
1806 // instruction.
1807 //
1808 // Instructions specify two basic values for encoding. Again, a
1809 // function is available to check if the constant displacement is an
1810 // oop. They use the ins_encode keyword to specify their encoding
1811 // classes (which must be a sequence of enc_class names, and their
1812 // parameters, specified in the encoding block), and they use the
1813 // opcode keyword to specify, in order, their primary, secondary, and
1814 // tertiary opcode. Only the opcode sections which a particular
1815 // instruction needs for encoding need to be specified.
1816 encode %{
1817 // Build emit functions for each basic byte or larger field in the
1818 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1819 // from C++ code in the enc_class source block. Emit functions will
1820 // live in the main source block for now. In future, we can
1821 // generalize this by adding a syntax that specifies the sizes of
1822 // fields in an order, so that the adlc can build the emit functions
1823 // automagically
1824
1825 // Emit primary opcode
1826 enc_class OpcP
1827 %{
1828 emit_opcode(cbuf, $primary);
1829 %}
1830
1831 // Emit secondary opcode
1832 enc_class OpcS
1833 %{
1834 emit_opcode(cbuf, $secondary);
1835 %}
1836
1837 // Emit tertiary opcode
1838 enc_class OpcT
1839 %{
1840 emit_opcode(cbuf, $tertiary);
1841 %}
1842
1843 // Emit opcode directly
1844 enc_class Opcode(immI d8)
1845 %{
1846 emit_opcode(cbuf, $d8$$constant);
1847 %}
1848
1849 // Emit size prefix
1850 enc_class SizePrefix
1851 %{
1852 emit_opcode(cbuf, 0x66);
1853 %}
1854
1855 enc_class reg(rRegI reg)
1856 %{
1857 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1858 %}
1859
1860 enc_class reg_reg(rRegI dst, rRegI src)
1861 %{
1862 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1863 %}
1864
1865 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1866 %{
1867 emit_opcode(cbuf, $opcode$$constant);
1868 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1869 %}
1870
1871 enc_class cdql_enc(no_rax_rdx_RegI div)
1872 %{
1873 // Full implementation of Java idiv and irem; checks for
1874 // special case as described in JVM spec., p.243 & p.271.
1875 //
1876 // normal case special case
1877 //
1878 // input : rax: dividend min_int
1879 // reg: divisor -1
1880 //
1881 // output: rax: quotient (= rax idiv reg) min_int
1882 // rdx: remainder (= rax irem reg) 0
1883 //
1884 // Code sequnce:
1885 //
1886 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1887 // 5: 75 07/08 jne e <normal>
1888 // 7: 33 d2 xor %edx,%edx
1889 // [div >= 8 -> offset + 1]
1890 // [REX_B]
1891 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1892 // c: 74 03/04 je 11 <done>
1893 // 000000000000000e <normal>:
1894 // e: 99 cltd
1895 // [div >= 8 -> offset + 1]
1896 // [REX_B]
1897 // f: f7 f9 idiv $div
1898 // 0000000000000011 <done>:
1899
1900 // cmp $0x80000000,%eax
1901 emit_opcode(cbuf, 0x3d);
1902 emit_d8(cbuf, 0x00);
1903 emit_d8(cbuf, 0x00);
1904 emit_d8(cbuf, 0x00);
1905 emit_d8(cbuf, 0x80);
1906
1907 // jne e <normal>
1908 emit_opcode(cbuf, 0x75);
1909 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1910
1911 // xor %edx,%edx
1912 emit_opcode(cbuf, 0x33);
1913 emit_d8(cbuf, 0xD2);
1914
1915 // cmp $0xffffffffffffffff,%ecx
1916 if ($div$$reg >= 8) {
1917 emit_opcode(cbuf, Assembler::REX_B);
1918 }
1919 emit_opcode(cbuf, 0x83);
1920 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1921 emit_d8(cbuf, 0xFF);
1922
1923 // je 11 <done>
1924 emit_opcode(cbuf, 0x74);
1925 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1926
1927 // <normal>
1928 // cltd
1929 emit_opcode(cbuf, 0x99);
1930
1931 // idivl (note: must be emitted by the user of this rule)
1932 // <done>
1933 %}
1934
1935 enc_class cdqq_enc(no_rax_rdx_RegL div)
1936 %{
1937 // Full implementation of Java ldiv and lrem; checks for
1938 // special case as described in JVM spec., p.243 & p.271.
1939 //
1940 // normal case special case
1941 //
1942 // input : rax: dividend min_long
1943 // reg: divisor -1
1944 //
1945 // output: rax: quotient (= rax idiv reg) min_long
1946 // rdx: remainder (= rax irem reg) 0
1947 //
1948 // Code sequnce:
1949 //
1950 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1951 // 7: 00 00 80
1952 // a: 48 39 d0 cmp %rdx,%rax
1953 // d: 75 08 jne 17 <normal>
1954 // f: 33 d2 xor %edx,%edx
1955 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1956 // 15: 74 05 je 1c <done>
1957 // 0000000000000017 <normal>:
1958 // 17: 48 99 cqto
1959 // 19: 48 f7 f9 idiv $div
1960 // 000000000000001c <done>:
1961
1962 // mov $0x8000000000000000,%rdx
1963 emit_opcode(cbuf, Assembler::REX_W);
1964 emit_opcode(cbuf, 0xBA);
1965 emit_d8(cbuf, 0x00);
1966 emit_d8(cbuf, 0x00);
1967 emit_d8(cbuf, 0x00);
1968 emit_d8(cbuf, 0x00);
1969 emit_d8(cbuf, 0x00);
1970 emit_d8(cbuf, 0x00);
1971 emit_d8(cbuf, 0x00);
1972 emit_d8(cbuf, 0x80);
1973
1974 // cmp %rdx,%rax
1975 emit_opcode(cbuf, Assembler::REX_W);
1976 emit_opcode(cbuf, 0x39);
1977 emit_d8(cbuf, 0xD0);
1978
1979 // jne 17 <normal>
1980 emit_opcode(cbuf, 0x75);
1981 emit_d8(cbuf, 0x08);
1982
1983 // xor %edx,%edx
1984 emit_opcode(cbuf, 0x33);
1985 emit_d8(cbuf, 0xD2);
1986
1987 // cmp $0xffffffffffffffff,$div
1988 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1989 emit_opcode(cbuf, 0x83);
1990 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1991 emit_d8(cbuf, 0xFF);
1992
1993 // je 1e <done>
1994 emit_opcode(cbuf, 0x74);
1995 emit_d8(cbuf, 0x05);
1996
1997 // <normal>
1998 // cqto
1999 emit_opcode(cbuf, Assembler::REX_W);
2000 emit_opcode(cbuf, 0x99);
2001
2002 // idivq (note: must be emitted by the user of this rule)
2003 // <done>
2004 %}
2005
2006 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2007 enc_class OpcSE(immI imm)
2008 %{
2009 // Emit primary opcode and set sign-extend bit
2010 // Check for 8-bit immediate, and set sign extend bit in opcode
2011 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2012 emit_opcode(cbuf, $primary | 0x02);
2013 } else {
2014 // 32-bit immediate
2015 emit_opcode(cbuf, $primary);
2016 }
2017 %}
2018
2019 enc_class OpcSErm(rRegI dst, immI imm)
2020 %{
2021 // OpcSEr/m
2022 int dstenc = $dst$$reg;
2023 if (dstenc >= 8) {
2024 emit_opcode(cbuf, Assembler::REX_B);
2025 dstenc -= 8;
2026 }
2027 // Emit primary opcode and set sign-extend bit
2028 // Check for 8-bit immediate, and set sign extend bit in opcode
2029 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2030 emit_opcode(cbuf, $primary | 0x02);
2031 } else {
2032 // 32-bit immediate
2033 emit_opcode(cbuf, $primary);
2034 }
2035 // Emit r/m byte with secondary opcode, after primary opcode.
2036 emit_rm(cbuf, 0x3, $secondary, dstenc);
2037 %}
2038
2039 enc_class OpcSErm_wide(rRegL dst, immI imm)
2040 %{
2041 // OpcSEr/m
2042 int dstenc = $dst$$reg;
2043 if (dstenc < 8) {
2044 emit_opcode(cbuf, Assembler::REX_W);
2045 } else {
2046 emit_opcode(cbuf, Assembler::REX_WB);
2047 dstenc -= 8;
2048 }
2049 // Emit primary opcode and set sign-extend bit
2050 // Check for 8-bit immediate, and set sign extend bit in opcode
2051 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2052 emit_opcode(cbuf, $primary | 0x02);
2053 } else {
2054 // 32-bit immediate
2055 emit_opcode(cbuf, $primary);
2056 }
2057 // Emit r/m byte with secondary opcode, after primary opcode.
2058 emit_rm(cbuf, 0x3, $secondary, dstenc);
2059 %}
2060
2061 enc_class Con8or32(immI imm)
2062 %{
2063 // Check for 8-bit immediate, and set sign extend bit in opcode
2064 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2065 $$$emit8$imm$$constant;
2066 } else {
2067 // 32-bit immediate
2068 $$$emit32$imm$$constant;
2069 }
2070 %}
2071
2072 enc_class opc2_reg(rRegI dst)
2073 %{
2074 // BSWAP
2075 emit_cc(cbuf, $secondary, $dst$$reg);
2076 %}
2077
2078 enc_class opc3_reg(rRegI dst)
2079 %{
2080 // BSWAP
2081 emit_cc(cbuf, $tertiary, $dst$$reg);
2082 %}
2083
2084 enc_class reg_opc(rRegI div)
2085 %{
2086 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2087 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2088 %}
2089
2090 enc_class enc_cmov(cmpOp cop)
2091 %{
2092 // CMOV
2093 $$$emit8$primary;
2094 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2095 %}
2096
2097 enc_class enc_PartialSubtypeCheck()
2098 %{
2099 Register Rrdi = as_Register(RDI_enc); // result register
2100 Register Rrax = as_Register(RAX_enc); // super class
2101 Register Rrcx = as_Register(RCX_enc); // killed
2102 Register Rrsi = as_Register(RSI_enc); // sub class
2103 Label miss;
2104 const bool set_cond_codes = true;
2105
2106 MacroAssembler _masm(&cbuf);
2107 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2108 NULL, &miss,
2109 /*set_cond_codes:*/ true);
2110 if ($primary) {
2111 __ xorptr(Rrdi, Rrdi);
2112 }
2113 __ bind(miss);
2114 %}
2115
2116 enc_class clear_avx %{
2117 debug_only(int off0 = cbuf.insts_size());
2118 if (generate_vzeroupper(Compile::current())) {
2119 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2120 // Clear upper bits of YMM registers when current compiled code uses
2121 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2122 MacroAssembler _masm(&cbuf);
2123 __ vzeroupper();
2124 }
2125 debug_only(int off1 = cbuf.insts_size());
2126 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2127 %}
2128
2129 enc_class Java_To_Runtime(method meth) %{
2130 // No relocation needed
2131 MacroAssembler _masm(&cbuf);
2132 __ mov64(r10, (int64_t) $meth$$method);
2133 __ call(r10);
2134 %}
2135
2136 enc_class Java_To_Interpreter(method meth)
2137 %{
2138 // CALL Java_To_Interpreter
2139 // This is the instruction starting address for relocation info.
2140 cbuf.set_insts_mark();
2141 $$$emit8$primary;
2142 // CALL directly to the runtime
2143 emit_d32_reloc(cbuf,
2144 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2145 runtime_call_Relocation::spec(),
2146 RELOC_DISP32);
2147 %}
2148
2149 enc_class Java_Static_Call(method meth)
2150 %{
2151 // JAVA STATIC CALL
2152 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2153 // determine who we intended to call.
2154 cbuf.set_insts_mark();
2155 $$$emit8$primary;
2156
2157 if (!_method) {
2158 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2159 runtime_call_Relocation::spec(),
2160 RELOC_DISP32);
2161 } else {
2162 int method_index = resolved_method_index(cbuf);
2163 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2164 : static_call_Relocation::spec(method_index);
2165 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2166 rspec, RELOC_DISP32);
2167 // Emit stubs for static call.
2168 address mark = cbuf.insts_mark();
2169 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2170 if (stub == NULL) {
2171 ciEnv::current()->record_failure("CodeCache is full");
2172 return;
2173 }
2174 #if INCLUDE_AOT
2175 CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2176 #endif
2177 }
2178 %}
2179
2180 enc_class Java_Dynamic_Call(method meth) %{
2181 MacroAssembler _masm(&cbuf);
2182 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2183 %}
2184
2185 enc_class Java_Compiled_Call(method meth)
2186 %{
2187 // JAVA COMPILED CALL
2188 int disp = in_bytes(Method:: from_compiled_offset());
2189
2190 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2191 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2192
2193 // callq *disp(%rax)
2194 cbuf.set_insts_mark();
2195 $$$emit8$primary;
2196 if (disp < 0x80) {
2197 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2198 emit_d8(cbuf, disp); // Displacement
2199 } else {
2200 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2201 emit_d32(cbuf, disp); // Displacement
2202 }
2203 %}
2204
2205 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2206 %{
2207 // SAL, SAR, SHR
2208 int dstenc = $dst$$reg;
2209 if (dstenc >= 8) {
2210 emit_opcode(cbuf, Assembler::REX_B);
2211 dstenc -= 8;
2212 }
2213 $$$emit8$primary;
2214 emit_rm(cbuf, 0x3, $secondary, dstenc);
2215 $$$emit8$shift$$constant;
2216 %}
2217
2218 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2219 %{
2220 // SAL, SAR, SHR
2221 int dstenc = $dst$$reg;
2222 if (dstenc < 8) {
2223 emit_opcode(cbuf, Assembler::REX_W);
2224 } else {
2225 emit_opcode(cbuf, Assembler::REX_WB);
2226 dstenc -= 8;
2227 }
2228 $$$emit8$primary;
2229 emit_rm(cbuf, 0x3, $secondary, dstenc);
2230 $$$emit8$shift$$constant;
2231 %}
2232
2233 enc_class load_immI(rRegI dst, immI src)
2234 %{
2235 int dstenc = $dst$$reg;
2236 if (dstenc >= 8) {
2237 emit_opcode(cbuf, Assembler::REX_B);
2238 dstenc -= 8;
2239 }
2240 emit_opcode(cbuf, 0xB8 | dstenc);
2241 $$$emit32$src$$constant;
2242 %}
2243
2244 enc_class load_immL(rRegL dst, immL src)
2245 %{
2246 int dstenc = $dst$$reg;
2247 if (dstenc < 8) {
2248 emit_opcode(cbuf, Assembler::REX_W);
2249 } else {
2250 emit_opcode(cbuf, Assembler::REX_WB);
2251 dstenc -= 8;
2252 }
2253 emit_opcode(cbuf, 0xB8 | dstenc);
2254 emit_d64(cbuf, $src$$constant);
2255 %}
2256
2257 enc_class load_immUL32(rRegL dst, immUL32 src)
2258 %{
2259 // same as load_immI, but this time we care about zeroes in the high word
2260 int dstenc = $dst$$reg;
2261 if (dstenc >= 8) {
2262 emit_opcode(cbuf, Assembler::REX_B);
2263 dstenc -= 8;
2264 }
2265 emit_opcode(cbuf, 0xB8 | dstenc);
2266 $$$emit32$src$$constant;
2267 %}
2268
2269 enc_class load_immL32(rRegL dst, immL32 src)
2270 %{
2271 int dstenc = $dst$$reg;
2272 if (dstenc < 8) {
2273 emit_opcode(cbuf, Assembler::REX_W);
2274 } else {
2275 emit_opcode(cbuf, Assembler::REX_WB);
2276 dstenc -= 8;
2277 }
2278 emit_opcode(cbuf, 0xC7);
2279 emit_rm(cbuf, 0x03, 0x00, dstenc);
2280 $$$emit32$src$$constant;
2281 %}
2282
2283 enc_class load_immP31(rRegP dst, immP32 src)
2284 %{
2285 // same as load_immI, but this time we care about zeroes in the high word
2286 int dstenc = $dst$$reg;
2287 if (dstenc >= 8) {
2288 emit_opcode(cbuf, Assembler::REX_B);
2289 dstenc -= 8;
2290 }
2291 emit_opcode(cbuf, 0xB8 | dstenc);
2292 $$$emit32$src$$constant;
2293 %}
2294
2295 enc_class load_immP(rRegP dst, immP src)
2296 %{
2297 int dstenc = $dst$$reg;
2298 if (dstenc < 8) {
2299 emit_opcode(cbuf, Assembler::REX_W);
2300 } else {
2301 emit_opcode(cbuf, Assembler::REX_WB);
2302 dstenc -= 8;
2303 }
2304 emit_opcode(cbuf, 0xB8 | dstenc);
2305 // This next line should be generated from ADLC
2306 if ($src->constant_reloc() != relocInfo::none) {
2307 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2308 } else {
2309 emit_d64(cbuf, $src$$constant);
2310 }
2311 %}
2312
2313 enc_class Con32(immI src)
2314 %{
2315 // Output immediate
2316 $$$emit32$src$$constant;
2317 %}
2318
2319 enc_class Con32F_as_bits(immF src)
2320 %{
2321 // Output Float immediate bits
2322 jfloat jf = $src$$constant;
2323 jint jf_as_bits = jint_cast(jf);
2324 emit_d32(cbuf, jf_as_bits);
2325 %}
2326
2327 enc_class Con16(immI src)
2328 %{
2329 // Output immediate
2330 $$$emit16$src$$constant;
2331 %}
2332
2333 // How is this different from Con32??? XXX
2334 enc_class Con_d32(immI src)
2335 %{
2336 emit_d32(cbuf,$src$$constant);
2337 %}
2338
2339 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2340 // Output immediate memory reference
2341 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2342 emit_d32(cbuf, 0x00);
2343 %}
2344
2345 enc_class lock_prefix()
2346 %{
2347 emit_opcode(cbuf, 0xF0); // lock
2348 %}
2349
2350 enc_class REX_mem(memory mem)
2351 %{
2352 if ($mem$$base >= 8) {
2353 if ($mem$$index < 8) {
2354 emit_opcode(cbuf, Assembler::REX_B);
2355 } else {
2356 emit_opcode(cbuf, Assembler::REX_XB);
2357 }
2358 } else {
2359 if ($mem$$index >= 8) {
2360 emit_opcode(cbuf, Assembler::REX_X);
2361 }
2362 }
2363 %}
2364
2365 enc_class REX_mem_wide(memory mem)
2366 %{
2367 if ($mem$$base >= 8) {
2368 if ($mem$$index < 8) {
2369 emit_opcode(cbuf, Assembler::REX_WB);
2370 } else {
2371 emit_opcode(cbuf, Assembler::REX_WXB);
2372 }
2373 } else {
2374 if ($mem$$index < 8) {
2375 emit_opcode(cbuf, Assembler::REX_W);
2376 } else {
2377 emit_opcode(cbuf, Assembler::REX_WX);
2378 }
2379 }
2380 %}
2381
2382 // for byte regs
2383 enc_class REX_breg(rRegI reg)
2384 %{
2385 if ($reg$$reg >= 4) {
2386 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2387 }
2388 %}
2389
2390 // for byte regs
2391 enc_class REX_reg_breg(rRegI dst, rRegI src)
2392 %{
2393 if ($dst$$reg < 8) {
2394 if ($src$$reg >= 4) {
2395 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2396 }
2397 } else {
2398 if ($src$$reg < 8) {
2399 emit_opcode(cbuf, Assembler::REX_R);
2400 } else {
2401 emit_opcode(cbuf, Assembler::REX_RB);
2402 }
2403 }
2404 %}
2405
2406 // for byte regs
2407 enc_class REX_breg_mem(rRegI reg, memory mem)
2408 %{
2409 if ($reg$$reg < 8) {
2410 if ($mem$$base < 8) {
2411 if ($mem$$index >= 8) {
2412 emit_opcode(cbuf, Assembler::REX_X);
2413 } else if ($reg$$reg >= 4) {
2414 emit_opcode(cbuf, Assembler::REX);
2415 }
2416 } else {
2417 if ($mem$$index < 8) {
2418 emit_opcode(cbuf, Assembler::REX_B);
2419 } else {
2420 emit_opcode(cbuf, Assembler::REX_XB);
2421 }
2422 }
2423 } else {
2424 if ($mem$$base < 8) {
2425 if ($mem$$index < 8) {
2426 emit_opcode(cbuf, Assembler::REX_R);
2427 } else {
2428 emit_opcode(cbuf, Assembler::REX_RX);
2429 }
2430 } else {
2431 if ($mem$$index < 8) {
2432 emit_opcode(cbuf, Assembler::REX_RB);
2433 } else {
2434 emit_opcode(cbuf, Assembler::REX_RXB);
2435 }
2436 }
2437 }
2438 %}
2439
2440 enc_class REX_reg(rRegI reg)
2441 %{
2442 if ($reg$$reg >= 8) {
2443 emit_opcode(cbuf, Assembler::REX_B);
2444 }
2445 %}
2446
2447 enc_class REX_reg_wide(rRegI reg)
2448 %{
2449 if ($reg$$reg < 8) {
2450 emit_opcode(cbuf, Assembler::REX_W);
2451 } else {
2452 emit_opcode(cbuf, Assembler::REX_WB);
2453 }
2454 %}
2455
2456 enc_class REX_reg_reg(rRegI dst, rRegI src)
2457 %{
2458 if ($dst$$reg < 8) {
2459 if ($src$$reg >= 8) {
2460 emit_opcode(cbuf, Assembler::REX_B);
2461 }
2462 } else {
2463 if ($src$$reg < 8) {
2464 emit_opcode(cbuf, Assembler::REX_R);
2465 } else {
2466 emit_opcode(cbuf, Assembler::REX_RB);
2467 }
2468 }
2469 %}
2470
2471 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2472 %{
2473 if ($dst$$reg < 8) {
2474 if ($src$$reg < 8) {
2475 emit_opcode(cbuf, Assembler::REX_W);
2476 } else {
2477 emit_opcode(cbuf, Assembler::REX_WB);
2478 }
2479 } else {
2480 if ($src$$reg < 8) {
2481 emit_opcode(cbuf, Assembler::REX_WR);
2482 } else {
2483 emit_opcode(cbuf, Assembler::REX_WRB);
2484 }
2485 }
2486 %}
2487
2488 enc_class REX_reg_mem(rRegI reg, memory mem)
2489 %{
2490 if ($reg$$reg < 8) {
2491 if ($mem$$base < 8) {
2492 if ($mem$$index >= 8) {
2493 emit_opcode(cbuf, Assembler::REX_X);
2494 }
2495 } else {
2496 if ($mem$$index < 8) {
2497 emit_opcode(cbuf, Assembler::REX_B);
2498 } else {
2499 emit_opcode(cbuf, Assembler::REX_XB);
2500 }
2501 }
2502 } else {
2503 if ($mem$$base < 8) {
2504 if ($mem$$index < 8) {
2505 emit_opcode(cbuf, Assembler::REX_R);
2506 } else {
2507 emit_opcode(cbuf, Assembler::REX_RX);
2508 }
2509 } else {
2510 if ($mem$$index < 8) {
2511 emit_opcode(cbuf, Assembler::REX_RB);
2512 } else {
2513 emit_opcode(cbuf, Assembler::REX_RXB);
2514 }
2515 }
2516 }
2517 %}
2518
2519 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2520 %{
2521 if ($reg$$reg < 8) {
2522 if ($mem$$base < 8) {
2523 if ($mem$$index < 8) {
2524 emit_opcode(cbuf, Assembler::REX_W);
2525 } else {
2526 emit_opcode(cbuf, Assembler::REX_WX);
2527 }
2528 } else {
2529 if ($mem$$index < 8) {
2530 emit_opcode(cbuf, Assembler::REX_WB);
2531 } else {
2532 emit_opcode(cbuf, Assembler::REX_WXB);
2533 }
2534 }
2535 } else {
2536 if ($mem$$base < 8) {
2537 if ($mem$$index < 8) {
2538 emit_opcode(cbuf, Assembler::REX_WR);
2539 } else {
2540 emit_opcode(cbuf, Assembler::REX_WRX);
2541 }
2542 } else {
2543 if ($mem$$index < 8) {
2544 emit_opcode(cbuf, Assembler::REX_WRB);
2545 } else {
2546 emit_opcode(cbuf, Assembler::REX_WRXB);
2547 }
2548 }
2549 }
2550 %}
2551
2552 enc_class reg_mem(rRegI ereg, memory mem)
2553 %{
2554 // High registers handle in encode_RegMem
2555 int reg = $ereg$$reg;
2556 int base = $mem$$base;
2557 int index = $mem$$index;
2558 int scale = $mem$$scale;
2559 int disp = $mem$$disp;
2560 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2561
2562 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2563 %}
2564
2565 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2566 %{
2567 int rm_byte_opcode = $rm_opcode$$constant;
2568
2569 // High registers handle in encode_RegMem
2570 int base = $mem$$base;
2571 int index = $mem$$index;
2572 int scale = $mem$$scale;
2573 int displace = $mem$$disp;
2574
2575 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2576 // working with static
2577 // globals
2578 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2579 disp_reloc);
2580 %}
2581
2582 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2583 %{
2584 int reg_encoding = $dst$$reg;
2585 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2586 int index = 0x04; // 0x04 indicates no index
2587 int scale = 0x00; // 0x00 indicates no scale
2588 int displace = $src1$$constant; // 0x00 indicates no displacement
2589 relocInfo::relocType disp_reloc = relocInfo::none;
2590 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2591 disp_reloc);
2592 %}
2593
2594 enc_class neg_reg(rRegI dst)
2595 %{
2596 int dstenc = $dst$$reg;
2597 if (dstenc >= 8) {
2598 emit_opcode(cbuf, Assembler::REX_B);
2599 dstenc -= 8;
2600 }
2601 // NEG $dst
2602 emit_opcode(cbuf, 0xF7);
2603 emit_rm(cbuf, 0x3, 0x03, dstenc);
2604 %}
2605
2606 enc_class neg_reg_wide(rRegI dst)
2607 %{
2608 int dstenc = $dst$$reg;
2609 if (dstenc < 8) {
2610 emit_opcode(cbuf, Assembler::REX_W);
2611 } else {
2612 emit_opcode(cbuf, Assembler::REX_WB);
2613 dstenc -= 8;
2614 }
2615 // NEG $dst
2616 emit_opcode(cbuf, 0xF7);
2617 emit_rm(cbuf, 0x3, 0x03, dstenc);
2618 %}
2619
2620 enc_class setLT_reg(rRegI dst)
2621 %{
2622 int dstenc = $dst$$reg;
2623 if (dstenc >= 8) {
2624 emit_opcode(cbuf, Assembler::REX_B);
2625 dstenc -= 8;
2626 } else if (dstenc >= 4) {
2627 emit_opcode(cbuf, Assembler::REX);
2628 }
2629 // SETLT $dst
2630 emit_opcode(cbuf, 0x0F);
2631 emit_opcode(cbuf, 0x9C);
2632 emit_rm(cbuf, 0x3, 0x0, dstenc);
2633 %}
2634
2635 enc_class setNZ_reg(rRegI dst)
2636 %{
2637 int dstenc = $dst$$reg;
2638 if (dstenc >= 8) {
2639 emit_opcode(cbuf, Assembler::REX_B);
2640 dstenc -= 8;
2641 } else if (dstenc >= 4) {
2642 emit_opcode(cbuf, Assembler::REX);
2643 }
2644 // SETNZ $dst
2645 emit_opcode(cbuf, 0x0F);
2646 emit_opcode(cbuf, 0x95);
2647 emit_rm(cbuf, 0x3, 0x0, dstenc);
2648 %}
2649
2650
2651 // Compare the lonogs and set -1, 0, or 1 into dst
2652 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2653 %{
2654 int src1enc = $src1$$reg;
2655 int src2enc = $src2$$reg;
2656 int dstenc = $dst$$reg;
2657
2658 // cmpq $src1, $src2
2659 if (src1enc < 8) {
2660 if (src2enc < 8) {
2661 emit_opcode(cbuf, Assembler::REX_W);
2662 } else {
2663 emit_opcode(cbuf, Assembler::REX_WB);
2664 }
2665 } else {
2666 if (src2enc < 8) {
2667 emit_opcode(cbuf, Assembler::REX_WR);
2668 } else {
2669 emit_opcode(cbuf, Assembler::REX_WRB);
2670 }
2671 }
2672 emit_opcode(cbuf, 0x3B);
2673 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2674
2675 // movl $dst, -1
2676 if (dstenc >= 8) {
2677 emit_opcode(cbuf, Assembler::REX_B);
2678 }
2679 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2680 emit_d32(cbuf, -1);
2681
2682 // jl,s done
2683 emit_opcode(cbuf, 0x7C);
2684 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2685
2686 // setne $dst
2687 if (dstenc >= 4) {
2688 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2689 }
2690 emit_opcode(cbuf, 0x0F);
2691 emit_opcode(cbuf, 0x95);
2692 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2693
2694 // movzbl $dst, $dst
2695 if (dstenc >= 4) {
2696 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2697 }
2698 emit_opcode(cbuf, 0x0F);
2699 emit_opcode(cbuf, 0xB6);
2700 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2701 %}
2702
2703 enc_class Push_ResultXD(regD dst) %{
2704 MacroAssembler _masm(&cbuf);
2705 __ fstp_d(Address(rsp, 0));
2706 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2707 __ addptr(rsp, 8);
2708 %}
2709
2710 enc_class Push_SrcXD(regD src) %{
2711 MacroAssembler _masm(&cbuf);
2712 __ subptr(rsp, 8);
2713 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2714 __ fld_d(Address(rsp, 0));
2715 %}
2716
2717
2718 enc_class enc_rethrow()
2719 %{
2720 cbuf.set_insts_mark();
2721 emit_opcode(cbuf, 0xE9); // jmp entry
2722 emit_d32_reloc(cbuf,
2723 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2724 runtime_call_Relocation::spec(),
2725 RELOC_DISP32);
2726 %}
2727
2728 %}
2729
2730
2731
2732 //----------FRAME--------------------------------------------------------------
2733 // Definition of frame structure and management information.
2734 //
2735 // S T A C K L A Y O U T Allocators stack-slot number
2736 // | (to get allocators register number
2737 // G Owned by | | v add OptoReg::stack0())
2738 // r CALLER | |
2739 // o | +--------+ pad to even-align allocators stack-slot
2740 // w V | pad0 | numbers; owned by CALLER
2741 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2742 // h ^ | in | 5
2743 // | | args | 4 Holes in incoming args owned by SELF
2744 // | | | | 3
2745 // | | +--------+
2746 // V | | old out| Empty on Intel, window on Sparc
2747 // | old |preserve| Must be even aligned.
2748 // | SP-+--------+----> Matcher::_old_SP, even aligned
2749 // | | in | 3 area for Intel ret address
2750 // Owned by |preserve| Empty on Sparc.
2751 // SELF +--------+
2752 // | | pad2 | 2 pad to align old SP
2753 // | +--------+ 1
2754 // | | locks | 0
2755 // | +--------+----> OptoReg::stack0(), even aligned
2756 // | | pad1 | 11 pad to align new SP
2757 // | +--------+
2758 // | | | 10
2759 // | | spills | 9 spills
2760 // V | | 8 (pad0 slot for callee)
2761 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2762 // ^ | out | 7
2763 // | | args | 6 Holes in outgoing args owned by CALLEE
2764 // Owned by +--------+
2765 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2766 // | new |preserve| Must be even-aligned.
2767 // | SP-+--------+----> Matcher::_new_SP, even aligned
2768 // | | |
2769 //
2770 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2771 // known from SELF's arguments and the Java calling convention.
2772 // Region 6-7 is determined per call site.
2773 // Note 2: If the calling convention leaves holes in the incoming argument
2774 // area, those holes are owned by SELF. Holes in the outgoing area
2775 // are owned by the CALLEE. Holes should not be nessecary in the
2776 // incoming area, as the Java calling convention is completely under
2777 // the control of the AD file. Doubles can be sorted and packed to
2778 // avoid holes. Holes in the outgoing arguments may be nessecary for
2779 // varargs C calling conventions.
2780 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2781 // even aligned with pad0 as needed.
2782 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2783 // region 6-11 is even aligned; it may be padded out more so that
2784 // the region from SP to FP meets the minimum stack alignment.
2785 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2786 // alignment. Region 11, pad1, may be dynamically extended so that
2787 // SP meets the minimum alignment.
2788
2789 frame
2790 %{
2791 // What direction does stack grow in (assumed to be same for C & Java)
2792 stack_direction(TOWARDS_LOW);
2793
2794 // These three registers define part of the calling convention
2795 // between compiled code and the interpreter.
2796 inline_cache_reg(RAX); // Inline Cache Register
2797 interpreter_method_oop_reg(RBX); // Method Oop Register when
2798 // calling interpreter
2799
2800 // Optional: name the operand used by cisc-spilling to access
2801 // [stack_pointer + offset]
2802 cisc_spilling_operand_name(indOffset32);
2803
2804 // Number of stack slots consumed by locking an object
2805 sync_stack_slots(2);
2806
2807 // Compiled code's Frame Pointer
2808 frame_pointer(RSP);
2809
2810 // Interpreter stores its frame pointer in a register which is
2811 // stored to the stack by I2CAdaptors.
2812 // I2CAdaptors convert from interpreted java to compiled java.
2813 interpreter_frame_pointer(RBP);
2814
2815 // Stack alignment requirement
2816 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2817
2818 // Number of stack slots between incoming argument block and the start of
2819 // a new frame. The PROLOG must add this many slots to the stack. The
2820 // EPILOG must remove this many slots. amd64 needs two slots for
2821 // return address.
2822 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2823
2824 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2825 // for calls to C. Supports the var-args backing area for register parms.
2826 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2827
2828 // The after-PROLOG location of the return address. Location of
2829 // return address specifies a type (REG or STACK) and a number
2830 // representing the register number (i.e. - use a register name) or
2831 // stack slot.
2832 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2833 // Otherwise, it is above the locks and verification slot and alignment word
2834 return_addr(STACK - 2 +
2835 align_up((Compile::current()->in_preserve_stack_slots() +
2836 Compile::current()->fixed_slots()),
2837 stack_alignment_in_slots()));
2838
2839 // Body of function which returns an integer array locating
2840 // arguments either in registers or in stack slots. Passed an array
2841 // of ideal registers called "sig" and a "length" count. Stack-slot
2842 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2843 // arguments for a CALLEE. Incoming stack arguments are
2844 // automatically biased by the preserve_stack_slots field above.
2845
2846 calling_convention
2847 %{
2848 // No difference between ingoing/outgoing just pass false
2849 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2850 %}
2851
2852 c_calling_convention
2853 %{
2854 // This is obviously always outgoing
2855 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2856 %}
2857
2858 // Location of compiled Java return values. Same as C for now.
2859 return_value
2860 %{
2861 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2862 "only return normal values");
2863
2864 static const int lo[Op_RegL + 1] = {
2865 0,
2866 0,
2867 RAX_num, // Op_RegN
2868 RAX_num, // Op_RegI
2869 RAX_num, // Op_RegP
2870 XMM0_num, // Op_RegF
2871 XMM0_num, // Op_RegD
2872 RAX_num // Op_RegL
2873 };
2874 static const int hi[Op_RegL + 1] = {
2875 0,
2876 0,
2877 OptoReg::Bad, // Op_RegN
2878 OptoReg::Bad, // Op_RegI
2879 RAX_H_num, // Op_RegP
2880 OptoReg::Bad, // Op_RegF
2881 XMM0b_num, // Op_RegD
2882 RAX_H_num // Op_RegL
2883 };
2884 // Excluded flags and vector registers.
2885 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2886 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2887 %}
2888 %}
2889
2890 //----------ATTRIBUTES---------------------------------------------------------
2891 //----------Operand Attributes-------------------------------------------------
2892 op_attrib op_cost(0); // Required cost attribute
2893
2894 //----------Instruction Attributes---------------------------------------------
2895 ins_attrib ins_cost(100); // Required cost attribute
2896 ins_attrib ins_size(8); // Required size attribute (in bits)
2897 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2898 // a non-matching short branch variant
2899 // of some long branch?
2900 ins_attrib ins_alignment(1); // Required alignment attribute (must
2901 // be a power of 2) specifies the
2902 // alignment that some part of the
2903 // instruction (not necessarily the
2904 // start) requires. If > 1, a
2905 // compute_padding() function must be
2906 // provided for the instruction
2907
2908 //----------OPERANDS-----------------------------------------------------------
2909 // Operand definitions must precede instruction definitions for correct parsing
2910 // in the ADLC because operands constitute user defined types which are used in
2911 // instruction definitions.
2912
2913 //----------Simple Operands----------------------------------------------------
2914 // Immediate Operands
2915 // Integer Immediate
2916 operand immI()
2917 %{
2918 match(ConI);
2919
2920 op_cost(10);
2921 format %{ %}
2922 interface(CONST_INTER);
2923 %}
2924
2925 // Constant for test vs zero
2926 operand immI0()
2927 %{
2928 predicate(n->get_int() == 0);
2929 match(ConI);
2930
2931 op_cost(0);
2932 format %{ %}
2933 interface(CONST_INTER);
2934 %}
2935
2936 // Constant for increment
2937 operand immI1()
2938 %{
2939 predicate(n->get_int() == 1);
2940 match(ConI);
2941
2942 op_cost(0);
2943 format %{ %}
2944 interface(CONST_INTER);
2945 %}
2946
2947 // Constant for decrement
2948 operand immI_M1()
2949 %{
2950 predicate(n->get_int() == -1);
2951 match(ConI);
2952
2953 op_cost(0);
2954 format %{ %}
2955 interface(CONST_INTER);
2956 %}
2957
2958 // Valid scale values for addressing modes
2959 operand immI2()
2960 %{
2961 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2962 match(ConI);
2963
2964 format %{ %}
2965 interface(CONST_INTER);
2966 %}
2967
2968 operand immI8()
2969 %{
2970 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2971 match(ConI);
2972
2973 op_cost(5);
2974 format %{ %}
2975 interface(CONST_INTER);
2976 %}
2977
2978 operand immU8()
2979 %{
2980 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2981 match(ConI);
2982
2983 op_cost(5);
2984 format %{ %}
2985 interface(CONST_INTER);
2986 %}
2987
2988 operand immI16()
2989 %{
2990 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2991 match(ConI);
2992
2993 op_cost(10);
2994 format %{ %}
2995 interface(CONST_INTER);
2996 %}
2997
2998 // Int Immediate non-negative
2999 operand immU31()
3000 %{
3001 predicate(n->get_int() >= 0);
3002 match(ConI);
3003
3004 op_cost(0);
3005 format %{ %}
3006 interface(CONST_INTER);
3007 %}
3008
3009 // Constant for long shifts
3010 operand immI_32()
3011 %{
3012 predicate( n->get_int() == 32 );
3013 match(ConI);
3014
3015 op_cost(0);
3016 format %{ %}
3017 interface(CONST_INTER);
3018 %}
3019
3020 // Constant for long shifts
3021 operand immI_64()
3022 %{
3023 predicate( n->get_int() == 64 );
3024 match(ConI);
3025
3026 op_cost(0);
3027 format %{ %}
3028 interface(CONST_INTER);
3029 %}
3030
3031 // Pointer Immediate
3032 operand immP()
3033 %{
3034 match(ConP);
3035
3036 op_cost(10);
3037 format %{ %}
3038 interface(CONST_INTER);
3039 %}
3040
3041 // NULL Pointer Immediate
3042 operand immP0()
3043 %{
3044 predicate(n->get_ptr() == 0);
3045 match(ConP);
3046
3047 op_cost(5);
3048 format %{ %}
3049 interface(CONST_INTER);
3050 %}
3051
3052 // Pointer Immediate
3053 operand immN() %{
3054 match(ConN);
3055
3056 op_cost(10);
3057 format %{ %}
3058 interface(CONST_INTER);
3059 %}
3060
3061 operand immNKlass() %{
3062 match(ConNKlass);
3063
3064 op_cost(10);
3065 format %{ %}
3066 interface(CONST_INTER);
3067 %}
3068
3069 // NULL Pointer Immediate
3070 operand immN0() %{
3071 predicate(n->get_narrowcon() == 0);
3072 match(ConN);
3073
3074 op_cost(5);
3075 format %{ %}
3076 interface(CONST_INTER);
3077 %}
3078
3079 operand immP31()
3080 %{
3081 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3082 && (n->get_ptr() >> 31) == 0);
3083 match(ConP);
3084
3085 op_cost(5);
3086 format %{ %}
3087 interface(CONST_INTER);
3088 %}
3089
3090
3091 // Long Immediate
3092 operand immL()
3093 %{
3094 match(ConL);
3095
3096 op_cost(20);
3097 format %{ %}
3098 interface(CONST_INTER);
3099 %}
3100
3101 // Long Immediate 8-bit
3102 operand immL8()
3103 %{
3104 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3105 match(ConL);
3106
3107 op_cost(5);
3108 format %{ %}
3109 interface(CONST_INTER);
3110 %}
3111
3112 // Long Immediate 32-bit unsigned
3113 operand immUL32()
3114 %{
3115 predicate(n->get_long() == (unsigned int) (n->get_long()));
3116 match(ConL);
3117
3118 op_cost(10);
3119 format %{ %}
3120 interface(CONST_INTER);
3121 %}
3122
3123 // Long Immediate 32-bit signed
3124 operand immL32()
3125 %{
3126 predicate(n->get_long() == (int) (n->get_long()));
3127 match(ConL);
3128
3129 op_cost(15);
3130 format %{ %}
3131 interface(CONST_INTER);
3132 %}
3133
3134 // Long Immediate zero
3135 operand immL0()
3136 %{
3137 predicate(n->get_long() == 0L);
3138 match(ConL);
3139
3140 op_cost(10);
3141 format %{ %}
3142 interface(CONST_INTER);
3143 %}
3144
3145 // Constant for increment
3146 operand immL1()
3147 %{
3148 predicate(n->get_long() == 1);
3149 match(ConL);
3150
3151 format %{ %}
3152 interface(CONST_INTER);
3153 %}
3154
3155 // Constant for decrement
3156 operand immL_M1()
3157 %{
3158 predicate(n->get_long() == -1);
3159 match(ConL);
3160
3161 format %{ %}
3162 interface(CONST_INTER);
3163 %}
3164
3165 // Long Immediate: the value 10
3166 operand immL10()
3167 %{
3168 predicate(n->get_long() == 10);
3169 match(ConL);
3170
3171 format %{ %}
3172 interface(CONST_INTER);
3173 %}
3174
3175 // Long immediate from 0 to 127.
3176 // Used for a shorter form of long mul by 10.
3177 operand immL_127()
3178 %{
3179 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3180 match(ConL);
3181
3182 op_cost(10);
3183 format %{ %}
3184 interface(CONST_INTER);
3185 %}
3186
3187 // Long Immediate: low 32-bit mask
3188 operand immL_32bits()
3189 %{
3190 predicate(n->get_long() == 0xFFFFFFFFL);
3191 match(ConL);
3192 op_cost(20);
3193
3194 format %{ %}
3195 interface(CONST_INTER);
3196 %}
3197
3198 // Float Immediate zero
3199 operand immF0()
3200 %{
3201 predicate(jint_cast(n->getf()) == 0);
3202 match(ConF);
3203
3204 op_cost(5);
3205 format %{ %}
3206 interface(CONST_INTER);
3207 %}
3208
3209 // Float Immediate
3210 operand immF()
3211 %{
3212 match(ConF);
3213
3214 op_cost(15);
3215 format %{ %}
3216 interface(CONST_INTER);
3217 %}
3218
3219 // Double Immediate zero
3220 operand immD0()
3221 %{
3222 predicate(jlong_cast(n->getd()) == 0);
3223 match(ConD);
3224
3225 op_cost(5);
3226 format %{ %}
3227 interface(CONST_INTER);
3228 %}
3229
3230 // Double Immediate
3231 operand immD()
3232 %{
3233 match(ConD);
3234
3235 op_cost(15);
3236 format %{ %}
3237 interface(CONST_INTER);
3238 %}
3239
3240 // Immediates for special shifts (sign extend)
3241
3242 // Constants for increment
3243 operand immI_16()
3244 %{
3245 predicate(n->get_int() == 16);
3246 match(ConI);
3247
3248 format %{ %}
3249 interface(CONST_INTER);
3250 %}
3251
3252 operand immI_24()
3253 %{
3254 predicate(n->get_int() == 24);
3255 match(ConI);
3256
3257 format %{ %}
3258 interface(CONST_INTER);
3259 %}
3260
3261 // Constant for byte-wide masking
3262 operand immI_255()
3263 %{
3264 predicate(n->get_int() == 255);
3265 match(ConI);
3266
3267 format %{ %}
3268 interface(CONST_INTER);
3269 %}
3270
3271 // Constant for short-wide masking
3272 operand immI_65535()
3273 %{
3274 predicate(n->get_int() == 65535);
3275 match(ConI);
3276
3277 format %{ %}
3278 interface(CONST_INTER);
3279 %}
3280
3281 // Constant for byte-wide masking
3282 operand immL_255()
3283 %{
3284 predicate(n->get_long() == 255);
3285 match(ConL);
3286
3287 format %{ %}
3288 interface(CONST_INTER);
3289 %}
3290
3291 // Constant for short-wide masking
3292 operand immL_65535()
3293 %{
3294 predicate(n->get_long() == 65535);
3295 match(ConL);
3296
3297 format %{ %}
3298 interface(CONST_INTER);
3299 %}
3300
3301 // Register Operands
3302 // Integer Register
3303 operand rRegI()
3304 %{
3305 constraint(ALLOC_IN_RC(int_reg));
3306 match(RegI);
3307
3308 match(rax_RegI);
3309 match(rbx_RegI);
3310 match(rcx_RegI);
3311 match(rdx_RegI);
3312 match(rdi_RegI);
3313
3314 format %{ %}
3315 interface(REG_INTER);
3316 %}
3317
3318 // Special Registers
3319 operand rax_RegI()
3320 %{
3321 constraint(ALLOC_IN_RC(int_rax_reg));
3322 match(RegI);
3323 match(rRegI);
3324
3325 format %{ "RAX" %}
3326 interface(REG_INTER);
3327 %}
3328
3329 // Special Registers
3330 operand rbx_RegI()
3331 %{
3332 constraint(ALLOC_IN_RC(int_rbx_reg));
3333 match(RegI);
3334 match(rRegI);
3335
3336 format %{ "RBX" %}
3337 interface(REG_INTER);
3338 %}
3339
3340 operand rcx_RegI()
3341 %{
3342 constraint(ALLOC_IN_RC(int_rcx_reg));
3343 match(RegI);
3344 match(rRegI);
3345
3346 format %{ "RCX" %}
3347 interface(REG_INTER);
3348 %}
3349
3350 operand rdx_RegI()
3351 %{
3352 constraint(ALLOC_IN_RC(int_rdx_reg));
3353 match(RegI);
3354 match(rRegI);
3355
3356 format %{ "RDX" %}
3357 interface(REG_INTER);
3358 %}
3359
3360 operand rdi_RegI()
3361 %{
3362 constraint(ALLOC_IN_RC(int_rdi_reg));
3363 match(RegI);
3364 match(rRegI);
3365
3366 format %{ "RDI" %}
3367 interface(REG_INTER);
3368 %}
3369
3370 operand no_rcx_RegI()
3371 %{
3372 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3373 match(RegI);
3374 match(rax_RegI);
3375 match(rbx_RegI);
3376 match(rdx_RegI);
3377 match(rdi_RegI);
3378
3379 format %{ %}
3380 interface(REG_INTER);
3381 %}
3382
3383 operand no_rax_rdx_RegI()
3384 %{
3385 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3386 match(RegI);
3387 match(rbx_RegI);
3388 match(rcx_RegI);
3389 match(rdi_RegI);
3390
3391 format %{ %}
3392 interface(REG_INTER);
3393 %}
3394
3395 // Pointer Register
3396 operand any_RegP()
3397 %{
3398 constraint(ALLOC_IN_RC(any_reg));
3399 match(RegP);
3400 match(rax_RegP);
3401 match(rbx_RegP);
3402 match(rdi_RegP);
3403 match(rsi_RegP);
3404 match(rbp_RegP);
3405 match(r15_RegP);
3406 match(rRegP);
3407
3408 format %{ %}
3409 interface(REG_INTER);
3410 %}
3411
3412 operand rRegP()
3413 %{
3414 constraint(ALLOC_IN_RC(ptr_reg));
3415 match(RegP);
3416 match(rax_RegP);
3417 match(rbx_RegP);
3418 match(rdi_RegP);
3419 match(rsi_RegP);
3420 match(rbp_RegP); // See Q&A below about
3421 match(r15_RegP); // r15_RegP and rbp_RegP.
3422
3423 format %{ %}
3424 interface(REG_INTER);
3425 %}
3426
3427 operand rRegN() %{
3428 constraint(ALLOC_IN_RC(int_reg));
3429 match(RegN);
3430
3431 format %{ %}
3432 interface(REG_INTER);
3433 %}
3434
3435 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3436 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3437 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3438 // The output of an instruction is controlled by the allocator, which respects
3439 // register class masks, not match rules. Unless an instruction mentions
3440 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3441 // by the allocator as an input.
3442 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3443 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3444 // result, RBP is not included in the output of the instruction either.
3445
3446 operand no_rax_RegP()
3447 %{
3448 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3449 match(RegP);
3450 match(rbx_RegP);
3451 match(rsi_RegP);
3452 match(rdi_RegP);
3453
3454 format %{ %}
3455 interface(REG_INTER);
3456 %}
3457
3458 // This operand is not allowed to use RBP even if
3459 // RBP is not used to hold the frame pointer.
3460 operand no_rbp_RegP()
3461 %{
3462 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3463 match(RegP);
3464 match(rbx_RegP);
3465 match(rsi_RegP);
3466 match(rdi_RegP);
3467
3468 format %{ %}
3469 interface(REG_INTER);
3470 %}
3471
3472 operand no_rax_rbx_RegP()
3473 %{
3474 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3475 match(RegP);
3476 match(rsi_RegP);
3477 match(rdi_RegP);
3478
3479 format %{ %}
3480 interface(REG_INTER);
3481 %}
3482
3483 // Special Registers
3484 // Return a pointer value
3485 operand rax_RegP()
3486 %{
3487 constraint(ALLOC_IN_RC(ptr_rax_reg));
3488 match(RegP);
3489 match(rRegP);
3490
3491 format %{ %}
3492 interface(REG_INTER);
3493 %}
3494
3495 // Special Registers
3496 // Return a compressed pointer value
3497 operand rax_RegN()
3498 %{
3499 constraint(ALLOC_IN_RC(int_rax_reg));
3500 match(RegN);
3501 match(rRegN);
3502
3503 format %{ %}
3504 interface(REG_INTER);
3505 %}
3506
3507 // Used in AtomicAdd
3508 operand rbx_RegP()
3509 %{
3510 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3511 match(RegP);
3512 match(rRegP);
3513
3514 format %{ %}
3515 interface(REG_INTER);
3516 %}
3517
3518 operand rsi_RegP()
3519 %{
3520 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3521 match(RegP);
3522 match(rRegP);
3523
3524 format %{ %}
3525 interface(REG_INTER);
3526 %}
3527
3528 // Used in rep stosq
3529 operand rdi_RegP()
3530 %{
3531 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3532 match(RegP);
3533 match(rRegP);
3534
3535 format %{ %}
3536 interface(REG_INTER);
3537 %}
3538
3539 operand r15_RegP()
3540 %{
3541 constraint(ALLOC_IN_RC(ptr_r15_reg));
3542 match(RegP);
3543 match(rRegP);
3544
3545 format %{ %}
3546 interface(REG_INTER);
3547 %}
3548
3549 operand rRegL()
3550 %{
3551 constraint(ALLOC_IN_RC(long_reg));
3552 match(RegL);
3553 match(rax_RegL);
3554 match(rdx_RegL);
3555
3556 format %{ %}
3557 interface(REG_INTER);
3558 %}
3559
3560 // Special Registers
3561 operand no_rax_rdx_RegL()
3562 %{
3563 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3564 match(RegL);
3565 match(rRegL);
3566
3567 format %{ %}
3568 interface(REG_INTER);
3569 %}
3570
3571 operand no_rax_RegL()
3572 %{
3573 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3574 match(RegL);
3575 match(rRegL);
3576 match(rdx_RegL);
3577
3578 format %{ %}
3579 interface(REG_INTER);
3580 %}
3581
3582 operand no_rcx_RegL()
3583 %{
3584 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3585 match(RegL);
3586 match(rRegL);
3587
3588 format %{ %}
3589 interface(REG_INTER);
3590 %}
3591
3592 operand rax_RegL()
3593 %{
3594 constraint(ALLOC_IN_RC(long_rax_reg));
3595 match(RegL);
3596 match(rRegL);
3597
3598 format %{ "RAX" %}
3599 interface(REG_INTER);
3600 %}
3601
3602 operand rcx_RegL()
3603 %{
3604 constraint(ALLOC_IN_RC(long_rcx_reg));
3605 match(RegL);
3606 match(rRegL);
3607
3608 format %{ %}
3609 interface(REG_INTER);
3610 %}
3611
3612 operand rdx_RegL()
3613 %{
3614 constraint(ALLOC_IN_RC(long_rdx_reg));
3615 match(RegL);
3616 match(rRegL);
3617
3618 format %{ %}
3619 interface(REG_INTER);
3620 %}
3621
3622 // Flags register, used as output of compare instructions
3623 operand rFlagsReg()
3624 %{
3625 constraint(ALLOC_IN_RC(int_flags));
3626 match(RegFlags);
3627
3628 format %{ "RFLAGS" %}
3629 interface(REG_INTER);
3630 %}
3631
3632 // Flags register, used as output of FLOATING POINT compare instructions
3633 operand rFlagsRegU()
3634 %{
3635 constraint(ALLOC_IN_RC(int_flags));
3636 match(RegFlags);
3637
3638 format %{ "RFLAGS_U" %}
3639 interface(REG_INTER);
3640 %}
3641
3642 operand rFlagsRegUCF() %{
3643 constraint(ALLOC_IN_RC(int_flags));
3644 match(RegFlags);
3645 predicate(false);
3646
3647 format %{ "RFLAGS_U_CF" %}
3648 interface(REG_INTER);
3649 %}
3650
3651 // Float register operands
3652 operand regF() %{
3653 constraint(ALLOC_IN_RC(float_reg));
3654 match(RegF);
3655
3656 format %{ %}
3657 interface(REG_INTER);
3658 %}
3659
3660
3661 // Float register operands
3662 operand legRegF() %{
3663 constraint(ALLOC_IN_RC(float_reg_legacy));
3664 match(RegF);
3665
3666 format %{ %}
3667 interface(REG_INTER);
3668 %}
3669
3670 // Float register operands
3671 operand vlRegF() %{
3672 constraint(ALLOC_IN_RC(float_reg_vl));
3673 match(RegF);
3674
3675 format %{ %}
3676 interface(REG_INTER);
3677 %}
3678
3679 // Double register operands
3680 operand regD() %{
3681 constraint(ALLOC_IN_RC(double_reg));
3682 match(RegD);
3683
3684 format %{ %}
3685 interface(REG_INTER);
3686 %}
3687
3688 // Double register operands
3689 operand legRegD() %{
3690 constraint(ALLOC_IN_RC(double_reg_legacy));
3691 match(RegD);
3692
3693 format %{ %}
3694 interface(REG_INTER);
3695 %}
3696
3697 // Double register operands
3698 operand vlRegD() %{
3699 constraint(ALLOC_IN_RC(double_reg_vl));
3700 match(RegD);
3701
3702 format %{ %}
3703 interface(REG_INTER);
3704 %}
3705
3706 // Vectors
3707 operand vecS() %{
3708 constraint(ALLOC_IN_RC(vectors_reg_vlbwdq));
3709 match(VecS);
3710
3711 format %{ %}
3712 interface(REG_INTER);
3713 %}
3714
3715 // Vectors
3716 operand legVecS() %{
3717 constraint(ALLOC_IN_RC(vectors_reg_legacy));
3718 match(VecS);
3719
3720 format %{ %}
3721 interface(REG_INTER);
3722 %}
3723
3724 operand vecD() %{
3725 constraint(ALLOC_IN_RC(vectord_reg_vlbwdq));
3726 match(VecD);
3727
3728 format %{ %}
3729 interface(REG_INTER);
3730 %}
3731
3732 operand legVecD() %{
3733 constraint(ALLOC_IN_RC(vectord_reg_legacy));
3734 match(VecD);
3735
3736 format %{ %}
3737 interface(REG_INTER);
3738 %}
3739
3740 operand vecX() %{
3741 constraint(ALLOC_IN_RC(vectorx_reg_vlbwdq));
3742 match(VecX);
3743
3744 format %{ %}
3745 interface(REG_INTER);
3746 %}
3747
3748 operand legVecX() %{
3749 constraint(ALLOC_IN_RC(vectorx_reg_legacy));
3750 match(VecX);
3751
3752 format %{ %}
3753 interface(REG_INTER);
3754 %}
3755
3756 operand vecY() %{
3757 constraint(ALLOC_IN_RC(vectory_reg_vlbwdq));
3758 match(VecY);
3759
3760 format %{ %}
3761 interface(REG_INTER);
3762 %}
3763
3764 operand legVecY() %{
3765 constraint(ALLOC_IN_RC(vectory_reg_legacy));
3766 match(VecY);
3767
3768 format %{ %}
3769 interface(REG_INTER);
3770 %}
3771
3772 //----------Memory Operands----------------------------------------------------
3773 // Direct Memory Operand
3774 // operand direct(immP addr)
3775 // %{
3776 // match(addr);
3777
3778 // format %{ "[$addr]" %}
3779 // interface(MEMORY_INTER) %{
3780 // base(0xFFFFFFFF);
3781 // index(0x4);
3782 // scale(0x0);
3783 // disp($addr);
3784 // %}
3785 // %}
3786
3787 // Indirect Memory Operand
3788 operand indirect(any_RegP reg)
3789 %{
3790 constraint(ALLOC_IN_RC(ptr_reg));
3791 match(reg);
3792
3793 format %{ "[$reg]" %}
3794 interface(MEMORY_INTER) %{
3795 base($reg);
3796 index(0x4);
3797 scale(0x0);
3798 disp(0x0);
3799 %}
3800 %}
3801
3802 // Indirect Memory Plus Short Offset Operand
3803 operand indOffset8(any_RegP reg, immL8 off)
3804 %{
3805 constraint(ALLOC_IN_RC(ptr_reg));
3806 match(AddP reg off);
3807
3808 format %{ "[$reg + $off (8-bit)]" %}
3809 interface(MEMORY_INTER) %{
3810 base($reg);
3811 index(0x4);
3812 scale(0x0);
3813 disp($off);
3814 %}
3815 %}
3816
3817 // Indirect Memory Plus Long Offset Operand
3818 operand indOffset32(any_RegP reg, immL32 off)
3819 %{
3820 constraint(ALLOC_IN_RC(ptr_reg));
3821 match(AddP reg off);
3822
3823 format %{ "[$reg + $off (32-bit)]" %}
3824 interface(MEMORY_INTER) %{
3825 base($reg);
3826 index(0x4);
3827 scale(0x0);
3828 disp($off);
3829 %}
3830 %}
3831
3832 // Indirect Memory Plus Index Register Plus Offset Operand
3833 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3834 %{
3835 constraint(ALLOC_IN_RC(ptr_reg));
3836 match(AddP (AddP reg lreg) off);
3837
3838 op_cost(10);
3839 format %{"[$reg + $off + $lreg]" %}
3840 interface(MEMORY_INTER) %{
3841 base($reg);
3842 index($lreg);
3843 scale(0x0);
3844 disp($off);
3845 %}
3846 %}
3847
3848 // Indirect Memory Plus Index Register Plus Offset Operand
3849 operand indIndex(any_RegP reg, rRegL lreg)
3850 %{
3851 constraint(ALLOC_IN_RC(ptr_reg));
3852 match(AddP reg lreg);
3853
3854 op_cost(10);
3855 format %{"[$reg + $lreg]" %}
3856 interface(MEMORY_INTER) %{
3857 base($reg);
3858 index($lreg);
3859 scale(0x0);
3860 disp(0x0);
3861 %}
3862 %}
3863
3864 // Indirect Memory Times Scale Plus Index Register
3865 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3866 %{
3867 constraint(ALLOC_IN_RC(ptr_reg));
3868 match(AddP reg (LShiftL lreg scale));
3869
3870 op_cost(10);
3871 format %{"[$reg + $lreg << $scale]" %}
3872 interface(MEMORY_INTER) %{
3873 base($reg);
3874 index($lreg);
3875 scale($scale);
3876 disp(0x0);
3877 %}
3878 %}
3879
3880 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3881 %{
3882 constraint(ALLOC_IN_RC(ptr_reg));
3883 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3884 match(AddP reg (LShiftL (ConvI2L idx) scale));
3885
3886 op_cost(10);
3887 format %{"[$reg + pos $idx << $scale]" %}
3888 interface(MEMORY_INTER) %{
3889 base($reg);
3890 index($idx);
3891 scale($scale);
3892 disp(0x0);
3893 %}
3894 %}
3895
3896 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3897 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3898 %{
3899 constraint(ALLOC_IN_RC(ptr_reg));
3900 match(AddP (AddP reg (LShiftL lreg scale)) off);
3901
3902 op_cost(10);
3903 format %{"[$reg + $off + $lreg << $scale]" %}
3904 interface(MEMORY_INTER) %{
3905 base($reg);
3906 index($lreg);
3907 scale($scale);
3908 disp($off);
3909 %}
3910 %}
3911
3912 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3913 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3914 %{
3915 constraint(ALLOC_IN_RC(ptr_reg));
3916 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3917 match(AddP (AddP reg (ConvI2L idx)) off);
3918
3919 op_cost(10);
3920 format %{"[$reg + $off + $idx]" %}
3921 interface(MEMORY_INTER) %{
3922 base($reg);
3923 index($idx);
3924 scale(0x0);
3925 disp($off);
3926 %}
3927 %}
3928
3929 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3930 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3931 %{
3932 constraint(ALLOC_IN_RC(ptr_reg));
3933 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3934 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3935
3936 op_cost(10);
3937 format %{"[$reg + $off + $idx << $scale]" %}
3938 interface(MEMORY_INTER) %{
3939 base($reg);
3940 index($idx);
3941 scale($scale);
3942 disp($off);
3943 %}
3944 %}
3945
3946 // Indirect Narrow Oop Plus Offset Operand
3947 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3948 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3949 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3950 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3951 constraint(ALLOC_IN_RC(ptr_reg));
3952 match(AddP (DecodeN reg) off);
3953
3954 op_cost(10);
3955 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3956 interface(MEMORY_INTER) %{
3957 base(0xc); // R12
3958 index($reg);
3959 scale(0x3);
3960 disp($off);
3961 %}
3962 %}
3963
3964 // Indirect Memory Operand
3965 operand indirectNarrow(rRegN reg)
3966 %{
3967 predicate(Universe::narrow_oop_shift() == 0);
3968 constraint(ALLOC_IN_RC(ptr_reg));
3969 match(DecodeN reg);
3970
3971 format %{ "[$reg]" %}
3972 interface(MEMORY_INTER) %{
3973 base($reg);
3974 index(0x4);
3975 scale(0x0);
3976 disp(0x0);
3977 %}
3978 %}
3979
3980 // Indirect Memory Plus Short Offset Operand
3981 operand indOffset8Narrow(rRegN reg, immL8 off)
3982 %{
3983 predicate(Universe::narrow_oop_shift() == 0);
3984 constraint(ALLOC_IN_RC(ptr_reg));
3985 match(AddP (DecodeN reg) off);
3986
3987 format %{ "[$reg + $off (8-bit)]" %}
3988 interface(MEMORY_INTER) %{
3989 base($reg);
3990 index(0x4);
3991 scale(0x0);
3992 disp($off);
3993 %}
3994 %}
3995
3996 // Indirect Memory Plus Long Offset Operand
3997 operand indOffset32Narrow(rRegN reg, immL32 off)
3998 %{
3999 predicate(Universe::narrow_oop_shift() == 0);
4000 constraint(ALLOC_IN_RC(ptr_reg));
4001 match(AddP (DecodeN reg) off);
4002
4003 format %{ "[$reg + $off (32-bit)]" %}
4004 interface(MEMORY_INTER) %{
4005 base($reg);
4006 index(0x4);
4007 scale(0x0);
4008 disp($off);
4009 %}
4010 %}
4011
4012 // Indirect Memory Plus Index Register Plus Offset Operand
4013 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
4014 %{
4015 predicate(Universe::narrow_oop_shift() == 0);
4016 constraint(ALLOC_IN_RC(ptr_reg));
4017 match(AddP (AddP (DecodeN reg) lreg) off);
4018
4019 op_cost(10);
4020 format %{"[$reg + $off + $lreg]" %}
4021 interface(MEMORY_INTER) %{
4022 base($reg);
4023 index($lreg);
4024 scale(0x0);
4025 disp($off);
4026 %}
4027 %}
4028
4029 // Indirect Memory Plus Index Register Plus Offset Operand
4030 operand indIndexNarrow(rRegN reg, rRegL lreg)
4031 %{
4032 predicate(Universe::narrow_oop_shift() == 0);
4033 constraint(ALLOC_IN_RC(ptr_reg));
4034 match(AddP (DecodeN reg) lreg);
4035
4036 op_cost(10);
4037 format %{"[$reg + $lreg]" %}
4038 interface(MEMORY_INTER) %{
4039 base($reg);
4040 index($lreg);
4041 scale(0x0);
4042 disp(0x0);
4043 %}
4044 %}
4045
4046 // Indirect Memory Times Scale Plus Index Register
4047 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4048 %{
4049 predicate(Universe::narrow_oop_shift() == 0);
4050 constraint(ALLOC_IN_RC(ptr_reg));
4051 match(AddP (DecodeN reg) (LShiftL lreg scale));
4052
4053 op_cost(10);
4054 format %{"[$reg + $lreg << $scale]" %}
4055 interface(MEMORY_INTER) %{
4056 base($reg);
4057 index($lreg);
4058 scale($scale);
4059 disp(0x0);
4060 %}
4061 %}
4062
4063 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4064 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4065 %{
4066 predicate(Universe::narrow_oop_shift() == 0);
4067 constraint(ALLOC_IN_RC(ptr_reg));
4068 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4069
4070 op_cost(10);
4071 format %{"[$reg + $off + $lreg << $scale]" %}
4072 interface(MEMORY_INTER) %{
4073 base($reg);
4074 index($lreg);
4075 scale($scale);
4076 disp($off);
4077 %}
4078 %}
4079
4080 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4081 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4082 %{
4083 constraint(ALLOC_IN_RC(ptr_reg));
4084 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4085 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4086
4087 op_cost(10);
4088 format %{"[$reg + $off + $idx]" %}
4089 interface(MEMORY_INTER) %{
4090 base($reg);
4091 index($idx);
4092 scale(0x0);
4093 disp($off);
4094 %}
4095 %}
4096
4097 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4098 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4099 %{
4100 constraint(ALLOC_IN_RC(ptr_reg));
4101 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4102 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4103
4104 op_cost(10);
4105 format %{"[$reg + $off + $idx << $scale]" %}
4106 interface(MEMORY_INTER) %{
4107 base($reg);
4108 index($idx);
4109 scale($scale);
4110 disp($off);
4111 %}
4112 %}
4113
4114 //----------Special Memory Operands--------------------------------------------
4115 // Stack Slot Operand - This operand is used for loading and storing temporary
4116 // values on the stack where a match requires a value to
4117 // flow through memory.
4118 operand stackSlotP(sRegP reg)
4119 %{
4120 constraint(ALLOC_IN_RC(stack_slots));
4121 // No match rule because this operand is only generated in matching
4122
4123 format %{ "[$reg]" %}
4124 interface(MEMORY_INTER) %{
4125 base(0x4); // RSP
4126 index(0x4); // No Index
4127 scale(0x0); // No Scale
4128 disp($reg); // Stack Offset
4129 %}
4130 %}
4131
4132 operand stackSlotI(sRegI reg)
4133 %{
4134 constraint(ALLOC_IN_RC(stack_slots));
4135 // No match rule because this operand is only generated in matching
4136
4137 format %{ "[$reg]" %}
4138 interface(MEMORY_INTER) %{
4139 base(0x4); // RSP
4140 index(0x4); // No Index
4141 scale(0x0); // No Scale
4142 disp($reg); // Stack Offset
4143 %}
4144 %}
4145
4146 operand stackSlotF(sRegF reg)
4147 %{
4148 constraint(ALLOC_IN_RC(stack_slots));
4149 // No match rule because this operand is only generated in matching
4150
4151 format %{ "[$reg]" %}
4152 interface(MEMORY_INTER) %{
4153 base(0x4); // RSP
4154 index(0x4); // No Index
4155 scale(0x0); // No Scale
4156 disp($reg); // Stack Offset
4157 %}
4158 %}
4159
4160 operand stackSlotD(sRegD reg)
4161 %{
4162 constraint(ALLOC_IN_RC(stack_slots));
4163 // No match rule because this operand is only generated in matching
4164
4165 format %{ "[$reg]" %}
4166 interface(MEMORY_INTER) %{
4167 base(0x4); // RSP
4168 index(0x4); // No Index
4169 scale(0x0); // No Scale
4170 disp($reg); // Stack Offset
4171 %}
4172 %}
4173 operand stackSlotL(sRegL reg)
4174 %{
4175 constraint(ALLOC_IN_RC(stack_slots));
4176 // No match rule because this operand is only generated in matching
4177
4178 format %{ "[$reg]" %}
4179 interface(MEMORY_INTER) %{
4180 base(0x4); // RSP
4181 index(0x4); // No Index
4182 scale(0x0); // No Scale
4183 disp($reg); // Stack Offset
4184 %}
4185 %}
4186
4187 //----------Conditional Branch Operands----------------------------------------
4188 // Comparison Op - This is the operation of the comparison, and is limited to
4189 // the following set of codes:
4190 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4191 //
4192 // Other attributes of the comparison, such as unsignedness, are specified
4193 // by the comparison instruction that sets a condition code flags register.
4194 // That result is represented by a flags operand whose subtype is appropriate
4195 // to the unsignedness (etc.) of the comparison.
4196 //
4197 // Later, the instruction which matches both the Comparison Op (a Bool) and
4198 // the flags (produced by the Cmp) specifies the coding of the comparison op
4199 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4200
4201 // Comparision Code
4202 operand cmpOp()
4203 %{
4204 match(Bool);
4205
4206 format %{ "" %}
4207 interface(COND_INTER) %{
4208 equal(0x4, "e");
4209 not_equal(0x5, "ne");
4210 less(0xC, "l");
4211 greater_equal(0xD, "ge");
4212 less_equal(0xE, "le");
4213 greater(0xF, "g");
4214 overflow(0x0, "o");
4215 no_overflow(0x1, "no");
4216 %}
4217 %}
4218
4219 // Comparison Code, unsigned compare. Used by FP also, with
4220 // C2 (unordered) turned into GT or LT already. The other bits
4221 // C0 and C3 are turned into Carry & Zero flags.
4222 operand cmpOpU()
4223 %{
4224 match(Bool);
4225
4226 format %{ "" %}
4227 interface(COND_INTER) %{
4228 equal(0x4, "e");
4229 not_equal(0x5, "ne");
4230 less(0x2, "b");
4231 greater_equal(0x3, "nb");
4232 less_equal(0x6, "be");
4233 greater(0x7, "nbe");
4234 overflow(0x0, "o");
4235 no_overflow(0x1, "no");
4236 %}
4237 %}
4238
4239
4240 // Floating comparisons that don't require any fixup for the unordered case
4241 operand cmpOpUCF() %{
4242 match(Bool);
4243 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4244 n->as_Bool()->_test._test == BoolTest::ge ||
4245 n->as_Bool()->_test._test == BoolTest::le ||
4246 n->as_Bool()->_test._test == BoolTest::gt);
4247 format %{ "" %}
4248 interface(COND_INTER) %{
4249 equal(0x4, "e");
4250 not_equal(0x5, "ne");
4251 less(0x2, "b");
4252 greater_equal(0x3, "nb");
4253 less_equal(0x6, "be");
4254 greater(0x7, "nbe");
4255 overflow(0x0, "o");
4256 no_overflow(0x1, "no");
4257 %}
4258 %}
4259
4260
4261 // Floating comparisons that can be fixed up with extra conditional jumps
4262 operand cmpOpUCF2() %{
4263 match(Bool);
4264 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4265 n->as_Bool()->_test._test == BoolTest::eq);
4266 format %{ "" %}
4267 interface(COND_INTER) %{
4268 equal(0x4, "e");
4269 not_equal(0x5, "ne");
4270 less(0x2, "b");
4271 greater_equal(0x3, "nb");
4272 less_equal(0x6, "be");
4273 greater(0x7, "nbe");
4274 overflow(0x0, "o");
4275 no_overflow(0x1, "no");
4276 %}
4277 %}
4278
4279 // Operands for bound floating pointer register arguments
4280 operand rxmm0() %{
4281 constraint(ALLOC_IN_RC(xmm0_reg));
4282 match(VecX);
4283 format%{%}
4284 interface(REG_INTER);
4285 %}
4286 operand rxmm1() %{
4287 constraint(ALLOC_IN_RC(xmm1_reg));
4288 match(VecX);
4289 format%{%}
4290 interface(REG_INTER);
4291 %}
4292 operand rxmm2() %{
4293 constraint(ALLOC_IN_RC(xmm2_reg));
4294 match(VecX);
4295 format%{%}
4296 interface(REG_INTER);
4297 %}
4298 operand rxmm3() %{
4299 constraint(ALLOC_IN_RC(xmm3_reg));
4300 match(VecX);
4301 format%{%}
4302 interface(REG_INTER);
4303 %}
4304 operand rxmm4() %{
4305 constraint(ALLOC_IN_RC(xmm4_reg));
4306 match(VecX);
4307 format%{%}
4308 interface(REG_INTER);
4309 %}
4310 operand rxmm5() %{
4311 constraint(ALLOC_IN_RC(xmm5_reg));
4312 match(VecX);
4313 format%{%}
4314 interface(REG_INTER);
4315 %}
4316 operand rxmm6() %{
4317 constraint(ALLOC_IN_RC(xmm6_reg));
4318 match(VecX);
4319 format%{%}
4320 interface(REG_INTER);
4321 %}
4322 operand rxmm7() %{
4323 constraint(ALLOC_IN_RC(xmm7_reg));
4324 match(VecX);
4325 format%{%}
4326 interface(REG_INTER);
4327 %}
4328 operand rxmm8() %{
4329 constraint(ALLOC_IN_RC(xmm8_reg));
4330 match(VecX);
4331 format%{%}
4332 interface(REG_INTER);
4333 %}
4334 operand rxmm9() %{
4335 constraint(ALLOC_IN_RC(xmm9_reg));
4336 match(VecX);
4337 format%{%}
4338 interface(REG_INTER);
4339 %}
4340 operand rxmm10() %{
4341 constraint(ALLOC_IN_RC(xmm10_reg));
4342 match(VecX);
4343 format%{%}
4344 interface(REG_INTER);
4345 %}
4346 operand rxmm11() %{
4347 constraint(ALLOC_IN_RC(xmm11_reg));
4348 match(VecX);
4349 format%{%}
4350 interface(REG_INTER);
4351 %}
4352 operand rxmm12() %{
4353 constraint(ALLOC_IN_RC(xmm12_reg));
4354 match(VecX);
4355 format%{%}
4356 interface(REG_INTER);
4357 %}
4358 operand rxmm13() %{
4359 constraint(ALLOC_IN_RC(xmm13_reg));
4360 match(VecX);
4361 format%{%}
4362 interface(REG_INTER);
4363 %}
4364 operand rxmm14() %{
4365 constraint(ALLOC_IN_RC(xmm14_reg));
4366 match(VecX);
4367 format%{%}
4368 interface(REG_INTER);
4369 %}
4370 operand rxmm15() %{
4371 constraint(ALLOC_IN_RC(xmm15_reg));
4372 match(VecX);
4373 format%{%}
4374 interface(REG_INTER);
4375 %}
4376 operand rxmm16() %{
4377 constraint(ALLOC_IN_RC(xmm16_reg));
4378 match(VecX);
4379 format%{%}
4380 interface(REG_INTER);
4381 %}
4382 operand rxmm17() %{
4383 constraint(ALLOC_IN_RC(xmm17_reg));
4384 match(VecX);
4385 format%{%}
4386 interface(REG_INTER);
4387 %}
4388 operand rxmm18() %{
4389 constraint(ALLOC_IN_RC(xmm18_reg));
4390 match(VecX);
4391 format%{%}
4392 interface(REG_INTER);
4393 %}
4394 operand rxmm19() %{
4395 constraint(ALLOC_IN_RC(xmm19_reg));
4396 match(VecX);
4397 format%{%}
4398 interface(REG_INTER);
4399 %}
4400 operand rxmm20() %{
4401 constraint(ALLOC_IN_RC(xmm20_reg));
4402 match(VecX);
4403 format%{%}
4404 interface(REG_INTER);
4405 %}
4406 operand rxmm21() %{
4407 constraint(ALLOC_IN_RC(xmm21_reg));
4408 match(VecX);
4409 format%{%}
4410 interface(REG_INTER);
4411 %}
4412 operand rxmm22() %{
4413 constraint(ALLOC_IN_RC(xmm22_reg));
4414 match(VecX);
4415 format%{%}
4416 interface(REG_INTER);
4417 %}
4418 operand rxmm23() %{
4419 constraint(ALLOC_IN_RC(xmm23_reg));
4420 match(VecX);
4421 format%{%}
4422 interface(REG_INTER);
4423 %}
4424 operand rxmm24() %{
4425 constraint(ALLOC_IN_RC(xmm24_reg));
4426 match(VecX);
4427 format%{%}
4428 interface(REG_INTER);
4429 %}
4430 operand rxmm25() %{
4431 constraint(ALLOC_IN_RC(xmm25_reg));
4432 match(VecX);
4433 format%{%}
4434 interface(REG_INTER);
4435 %}
4436 operand rxmm26() %{
4437 constraint(ALLOC_IN_RC(xmm26_reg));
4438 match(VecX);
4439 format%{%}
4440 interface(REG_INTER);
4441 %}
4442 operand rxmm27() %{
4443 constraint(ALLOC_IN_RC(xmm27_reg));
4444 match(VecX);
4445 format%{%}
4446 interface(REG_INTER);
4447 %}
4448 operand rxmm28() %{
4449 constraint(ALLOC_IN_RC(xmm28_reg));
4450 match(VecX);
4451 format%{%}
4452 interface(REG_INTER);
4453 %}
4454 operand rxmm29() %{
4455 constraint(ALLOC_IN_RC(xmm29_reg));
4456 match(VecX);
4457 format%{%}
4458 interface(REG_INTER);
4459 %}
4460 operand rxmm30() %{
4461 constraint(ALLOC_IN_RC(xmm30_reg));
4462 match(VecX);
4463 format%{%}
4464 interface(REG_INTER);
4465 %}
4466 operand rxmm31() %{
4467 constraint(ALLOC_IN_RC(xmm31_reg));
4468 match(VecX);
4469 format%{%}
4470 interface(REG_INTER);
4471 %}
4472
4473 //----------OPERAND CLASSES----------------------------------------------------
4474 // Operand Classes are groups of operands that are used as to simplify
4475 // instruction definitions by not requiring the AD writer to specify separate
4476 // instructions for every form of operand when the instruction accepts
4477 // multiple operand types with the same basic encoding and format. The classic
4478 // case of this is memory operands.
4479
4480 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4481 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4482 indCompressedOopOffset,
4483 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4484 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4485 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4486
4487 //----------PIPELINE-----------------------------------------------------------
4488 // Rules which define the behavior of the target architectures pipeline.
4489 pipeline %{
4490
4491 //----------ATTRIBUTES---------------------------------------------------------
4492 attributes %{
4493 variable_size_instructions; // Fixed size instructions
4494 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4495 instruction_unit_size = 1; // An instruction is 1 bytes long
4496 instruction_fetch_unit_size = 16; // The processor fetches one line
4497 instruction_fetch_units = 1; // of 16 bytes
4498
4499 // List of nop instructions
4500 nops( MachNop );
4501 %}
4502
4503 //----------RESOURCES----------------------------------------------------------
4504 // Resources are the functional units available to the machine
4505
4506 // Generic P2/P3 pipeline
4507 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4508 // 3 instructions decoded per cycle.
4509 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4510 // 3 ALU op, only ALU0 handles mul instructions.
4511 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4512 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4513 BR, FPU,
4514 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4515
4516 //----------PIPELINE DESCRIPTION-----------------------------------------------
4517 // Pipeline Description specifies the stages in the machine's pipeline
4518
4519 // Generic P2/P3 pipeline
4520 pipe_desc(S0, S1, S2, S3, S4, S5);
4521
4522 //----------PIPELINE CLASSES---------------------------------------------------
4523 // Pipeline Classes describe the stages in which input and output are
4524 // referenced by the hardware pipeline.
4525
4526 // Naming convention: ialu or fpu
4527 // Then: _reg
4528 // Then: _reg if there is a 2nd register
4529 // Then: _long if it's a pair of instructions implementing a long
4530 // Then: _fat if it requires the big decoder
4531 // Or: _mem if it requires the big decoder and a memory unit.
4532
4533 // Integer ALU reg operation
4534 pipe_class ialu_reg(rRegI dst)
4535 %{
4536 single_instruction;
4537 dst : S4(write);
4538 dst : S3(read);
4539 DECODE : S0; // any decoder
4540 ALU : S3; // any alu
4541 %}
4542
4543 // Long ALU reg operation
4544 pipe_class ialu_reg_long(rRegL dst)
4545 %{
4546 instruction_count(2);
4547 dst : S4(write);
4548 dst : S3(read);
4549 DECODE : S0(2); // any 2 decoders
4550 ALU : S3(2); // both alus
4551 %}
4552
4553 // Integer ALU reg operation using big decoder
4554 pipe_class ialu_reg_fat(rRegI dst)
4555 %{
4556 single_instruction;
4557 dst : S4(write);
4558 dst : S3(read);
4559 D0 : S0; // big decoder only
4560 ALU : S3; // any alu
4561 %}
4562
4563 // Long ALU reg operation using big decoder
4564 pipe_class ialu_reg_long_fat(rRegL dst)
4565 %{
4566 instruction_count(2);
4567 dst : S4(write);
4568 dst : S3(read);
4569 D0 : S0(2); // big decoder only; twice
4570 ALU : S3(2); // any 2 alus
4571 %}
4572
4573 // Integer ALU reg-reg operation
4574 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4575 %{
4576 single_instruction;
4577 dst : S4(write);
4578 src : S3(read);
4579 DECODE : S0; // any decoder
4580 ALU : S3; // any alu
4581 %}
4582
4583 // Long ALU reg-reg operation
4584 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4585 %{
4586 instruction_count(2);
4587 dst : S4(write);
4588 src : S3(read);
4589 DECODE : S0(2); // any 2 decoders
4590 ALU : S3(2); // both alus
4591 %}
4592
4593 // Integer ALU reg-reg operation
4594 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4595 %{
4596 single_instruction;
4597 dst : S4(write);
4598 src : S3(read);
4599 D0 : S0; // big decoder only
4600 ALU : S3; // any alu
4601 %}
4602
4603 // Long ALU reg-reg operation
4604 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4605 %{
4606 instruction_count(2);
4607 dst : S4(write);
4608 src : S3(read);
4609 D0 : S0(2); // big decoder only; twice
4610 ALU : S3(2); // both alus
4611 %}
4612
4613 // Integer ALU reg-mem operation
4614 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4615 %{
4616 single_instruction;
4617 dst : S5(write);
4618 mem : S3(read);
4619 D0 : S0; // big decoder only
4620 ALU : S4; // any alu
4621 MEM : S3; // any mem
4622 %}
4623
4624 // Integer mem operation (prefetch)
4625 pipe_class ialu_mem(memory mem)
4626 %{
4627 single_instruction;
4628 mem : S3(read);
4629 D0 : S0; // big decoder only
4630 MEM : S3; // any mem
4631 %}
4632
4633 // Integer Store to Memory
4634 pipe_class ialu_mem_reg(memory mem, rRegI src)
4635 %{
4636 single_instruction;
4637 mem : S3(read);
4638 src : S5(read);
4639 D0 : S0; // big decoder only
4640 ALU : S4; // any alu
4641 MEM : S3;
4642 %}
4643
4644 // // Long Store to Memory
4645 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4646 // %{
4647 // instruction_count(2);
4648 // mem : S3(read);
4649 // src : S5(read);
4650 // D0 : S0(2); // big decoder only; twice
4651 // ALU : S4(2); // any 2 alus
4652 // MEM : S3(2); // Both mems
4653 // %}
4654
4655 // Integer Store to Memory
4656 pipe_class ialu_mem_imm(memory mem)
4657 %{
4658 single_instruction;
4659 mem : S3(read);
4660 D0 : S0; // big decoder only
4661 ALU : S4; // any alu
4662 MEM : S3;
4663 %}
4664
4665 // Integer ALU0 reg-reg operation
4666 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4667 %{
4668 single_instruction;
4669 dst : S4(write);
4670 src : S3(read);
4671 D0 : S0; // Big decoder only
4672 ALU0 : S3; // only alu0
4673 %}
4674
4675 // Integer ALU0 reg-mem operation
4676 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4677 %{
4678 single_instruction;
4679 dst : S5(write);
4680 mem : S3(read);
4681 D0 : S0; // big decoder only
4682 ALU0 : S4; // ALU0 only
4683 MEM : S3; // any mem
4684 %}
4685
4686 // Integer ALU reg-reg operation
4687 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4688 %{
4689 single_instruction;
4690 cr : S4(write);
4691 src1 : S3(read);
4692 src2 : S3(read);
4693 DECODE : S0; // any decoder
4694 ALU : S3; // any alu
4695 %}
4696
4697 // Integer ALU reg-imm operation
4698 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4699 %{
4700 single_instruction;
4701 cr : S4(write);
4702 src1 : S3(read);
4703 DECODE : S0; // any decoder
4704 ALU : S3; // any alu
4705 %}
4706
4707 // Integer ALU reg-mem operation
4708 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4709 %{
4710 single_instruction;
4711 cr : S4(write);
4712 src1 : S3(read);
4713 src2 : S3(read);
4714 D0 : S0; // big decoder only
4715 ALU : S4; // any alu
4716 MEM : S3;
4717 %}
4718
4719 // Conditional move reg-reg
4720 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4721 %{
4722 instruction_count(4);
4723 y : S4(read);
4724 q : S3(read);
4725 p : S3(read);
4726 DECODE : S0(4); // any decoder
4727 %}
4728
4729 // Conditional move reg-reg
4730 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4731 %{
4732 single_instruction;
4733 dst : S4(write);
4734 src : S3(read);
4735 cr : S3(read);
4736 DECODE : S0; // any decoder
4737 %}
4738
4739 // Conditional move reg-mem
4740 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4741 %{
4742 single_instruction;
4743 dst : S4(write);
4744 src : S3(read);
4745 cr : S3(read);
4746 DECODE : S0; // any decoder
4747 MEM : S3;
4748 %}
4749
4750 // Conditional move reg-reg long
4751 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4752 %{
4753 single_instruction;
4754 dst : S4(write);
4755 src : S3(read);
4756 cr : S3(read);
4757 DECODE : S0(2); // any 2 decoders
4758 %}
4759
4760 // XXX
4761 // // Conditional move double reg-reg
4762 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4763 // %{
4764 // single_instruction;
4765 // dst : S4(write);
4766 // src : S3(read);
4767 // cr : S3(read);
4768 // DECODE : S0; // any decoder
4769 // %}
4770
4771 // Float reg-reg operation
4772 pipe_class fpu_reg(regD dst)
4773 %{
4774 instruction_count(2);
4775 dst : S3(read);
4776 DECODE : S0(2); // any 2 decoders
4777 FPU : S3;
4778 %}
4779
4780 // Float reg-reg operation
4781 pipe_class fpu_reg_reg(regD dst, regD src)
4782 %{
4783 instruction_count(2);
4784 dst : S4(write);
4785 src : S3(read);
4786 DECODE : S0(2); // any 2 decoders
4787 FPU : S3;
4788 %}
4789
4790 // Float reg-reg operation
4791 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4792 %{
4793 instruction_count(3);
4794 dst : S4(write);
4795 src1 : S3(read);
4796 src2 : S3(read);
4797 DECODE : S0(3); // any 3 decoders
4798 FPU : S3(2);
4799 %}
4800
4801 // Float reg-reg operation
4802 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4803 %{
4804 instruction_count(4);
4805 dst : S4(write);
4806 src1 : S3(read);
4807 src2 : S3(read);
4808 src3 : S3(read);
4809 DECODE : S0(4); // any 3 decoders
4810 FPU : S3(2);
4811 %}
4812
4813 // Float reg-reg operation
4814 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4815 %{
4816 instruction_count(4);
4817 dst : S4(write);
4818 src1 : S3(read);
4819 src2 : S3(read);
4820 src3 : S3(read);
4821 DECODE : S1(3); // any 3 decoders
4822 D0 : S0; // Big decoder only
4823 FPU : S3(2);
4824 MEM : S3;
4825 %}
4826
4827 // Float reg-mem operation
4828 pipe_class fpu_reg_mem(regD dst, memory mem)
4829 %{
4830 instruction_count(2);
4831 dst : S5(write);
4832 mem : S3(read);
4833 D0 : S0; // big decoder only
4834 DECODE : S1; // any decoder for FPU POP
4835 FPU : S4;
4836 MEM : S3; // any mem
4837 %}
4838
4839 // Float reg-mem operation
4840 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4841 %{
4842 instruction_count(3);
4843 dst : S5(write);
4844 src1 : S3(read);
4845 mem : S3(read);
4846 D0 : S0; // big decoder only
4847 DECODE : S1(2); // any decoder for FPU POP
4848 FPU : S4;
4849 MEM : S3; // any mem
4850 %}
4851
4852 // Float mem-reg operation
4853 pipe_class fpu_mem_reg(memory mem, regD src)
4854 %{
4855 instruction_count(2);
4856 src : S5(read);
4857 mem : S3(read);
4858 DECODE : S0; // any decoder for FPU PUSH
4859 D0 : S1; // big decoder only
4860 FPU : S4;
4861 MEM : S3; // any mem
4862 %}
4863
4864 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4865 %{
4866 instruction_count(3);
4867 src1 : S3(read);
4868 src2 : S3(read);
4869 mem : S3(read);
4870 DECODE : S0(2); // any decoder for FPU PUSH
4871 D0 : S1; // big decoder only
4872 FPU : S4;
4873 MEM : S3; // any mem
4874 %}
4875
4876 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4877 %{
4878 instruction_count(3);
4879 src1 : S3(read);
4880 src2 : S3(read);
4881 mem : S4(read);
4882 DECODE : S0; // any decoder for FPU PUSH
4883 D0 : S0(2); // big decoder only
4884 FPU : S4;
4885 MEM : S3(2); // any mem
4886 %}
4887
4888 pipe_class fpu_mem_mem(memory dst, memory src1)
4889 %{
4890 instruction_count(2);
4891 src1 : S3(read);
4892 dst : S4(read);
4893 D0 : S0(2); // big decoder only
4894 MEM : S3(2); // any mem
4895 %}
4896
4897 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4898 %{
4899 instruction_count(3);
4900 src1 : S3(read);
4901 src2 : S3(read);
4902 dst : S4(read);
4903 D0 : S0(3); // big decoder only
4904 FPU : S4;
4905 MEM : S3(3); // any mem
4906 %}
4907
4908 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4909 %{
4910 instruction_count(3);
4911 src1 : S4(read);
4912 mem : S4(read);
4913 DECODE : S0; // any decoder for FPU PUSH
4914 D0 : S0(2); // big decoder only
4915 FPU : S4;
4916 MEM : S3(2); // any mem
4917 %}
4918
4919 // Float load constant
4920 pipe_class fpu_reg_con(regD dst)
4921 %{
4922 instruction_count(2);
4923 dst : S5(write);
4924 D0 : S0; // big decoder only for the load
4925 DECODE : S1; // any decoder for FPU POP
4926 FPU : S4;
4927 MEM : S3; // any mem
4928 %}
4929
4930 // Float load constant
4931 pipe_class fpu_reg_reg_con(regD dst, regD src)
4932 %{
4933 instruction_count(3);
4934 dst : S5(write);
4935 src : S3(read);
4936 D0 : S0; // big decoder only for the load
4937 DECODE : S1(2); // any decoder for FPU POP
4938 FPU : S4;
4939 MEM : S3; // any mem
4940 %}
4941
4942 // UnConditional branch
4943 pipe_class pipe_jmp(label labl)
4944 %{
4945 single_instruction;
4946 BR : S3;
4947 %}
4948
4949 // Conditional branch
4950 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4951 %{
4952 single_instruction;
4953 cr : S1(read);
4954 BR : S3;
4955 %}
4956
4957 // Allocation idiom
4958 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4959 %{
4960 instruction_count(1); force_serialization;
4961 fixed_latency(6);
4962 heap_ptr : S3(read);
4963 DECODE : S0(3);
4964 D0 : S2;
4965 MEM : S3;
4966 ALU : S3(2);
4967 dst : S5(write);
4968 BR : S5;
4969 %}
4970
4971 // Generic big/slow expanded idiom
4972 pipe_class pipe_slow()
4973 %{
4974 instruction_count(10); multiple_bundles; force_serialization;
4975 fixed_latency(100);
4976 D0 : S0(2);
4977 MEM : S3(2);
4978 %}
4979
4980 // The real do-nothing guy
4981 pipe_class empty()
4982 %{
4983 instruction_count(0);
4984 %}
4985
4986 // Define the class for the Nop node
4987 define
4988 %{
4989 MachNop = empty;
4990 %}
4991
4992 %}
4993
4994 //----------INSTRUCTIONS-------------------------------------------------------
4995 //
4996 // match -- States which machine-independent subtree may be replaced
4997 // by this instruction.
4998 // ins_cost -- The estimated cost of this instruction is used by instruction
4999 // selection to identify a minimum cost tree of machine
5000 // instructions that matches a tree of machine-independent
5001 // instructions.
5002 // format -- A string providing the disassembly for this instruction.
5003 // The value of an instruction's operand may be inserted
5004 // by referring to it with a '$' prefix.
5005 // opcode -- Three instruction opcodes may be provided. These are referred
5006 // to within an encode class as $primary, $secondary, and $tertiary
5007 // rrspectively. The primary opcode is commonly used to
5008 // indicate the type of machine instruction, while secondary
5009 // and tertiary are often used for prefix options or addressing
5010 // modes.
5011 // ins_encode -- A list of encode classes with parameters. The encode class
5012 // name must have been defined in an 'enc_class' specification
5013 // in the encode section of the architecture description.
5014
5015
5016 //----------Load/Store/Move Instructions---------------------------------------
5017 //----------Load Instructions--------------------------------------------------
5018
5019 // Load Byte (8 bit signed)
5020 instruct loadB(rRegI dst, memory mem)
5021 %{
5022 match(Set dst (LoadB mem));
5023
5024 ins_cost(125);
5025 format %{ "movsbl $dst, $mem\t# byte" %}
5026
5027 ins_encode %{
5028 __ movsbl($dst$$Register, $mem$$Address);
5029 %}
5030
5031 ins_pipe(ialu_reg_mem);
5032 %}
5033
5034 // Load Byte (8 bit signed) into Long Register
5035 instruct loadB2L(rRegL dst, memory mem)
5036 %{
5037 match(Set dst (ConvI2L (LoadB mem)));
5038
5039 ins_cost(125);
5040 format %{ "movsbq $dst, $mem\t# byte -> long" %}
5041
5042 ins_encode %{
5043 __ movsbq($dst$$Register, $mem$$Address);
5044 %}
5045
5046 ins_pipe(ialu_reg_mem);
5047 %}
5048
5049 // Load Unsigned Byte (8 bit UNsigned)
5050 instruct loadUB(rRegI dst, memory mem)
5051 %{
5052 match(Set dst (LoadUB mem));
5053
5054 ins_cost(125);
5055 format %{ "movzbl $dst, $mem\t# ubyte" %}
5056
5057 ins_encode %{
5058 __ movzbl($dst$$Register, $mem$$Address);
5059 %}
5060
5061 ins_pipe(ialu_reg_mem);
5062 %}
5063
5064 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5065 instruct loadUB2L(rRegL dst, memory mem)
5066 %{
5067 match(Set dst (ConvI2L (LoadUB mem)));
5068
5069 ins_cost(125);
5070 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
5071
5072 ins_encode %{
5073 __ movzbq($dst$$Register, $mem$$Address);
5074 %}
5075
5076 ins_pipe(ialu_reg_mem);
5077 %}
5078
5079 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5080 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5081 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5082 effect(KILL cr);
5083
5084 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
5085 "andl $dst, right_n_bits($mask, 8)" %}
5086 ins_encode %{
5087 Register Rdst = $dst$$Register;
5088 __ movzbq(Rdst, $mem$$Address);
5089 __ andl(Rdst, $mask$$constant & right_n_bits(8));
5090 %}
5091 ins_pipe(ialu_reg_mem);
5092 %}
5093
5094 // Load Short (16 bit signed)
5095 instruct loadS(rRegI dst, memory mem)
5096 %{
5097 match(Set dst (LoadS mem));
5098
5099 ins_cost(125);
5100 format %{ "movswl $dst, $mem\t# short" %}
5101
5102 ins_encode %{
5103 __ movswl($dst$$Register, $mem$$Address);
5104 %}
5105
5106 ins_pipe(ialu_reg_mem);
5107 %}
5108
5109 // Load Short (16 bit signed) to Byte (8 bit signed)
5110 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5111 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5112
5113 ins_cost(125);
5114 format %{ "movsbl $dst, $mem\t# short -> byte" %}
5115 ins_encode %{
5116 __ movsbl($dst$$Register, $mem$$Address);
5117 %}
5118 ins_pipe(ialu_reg_mem);
5119 %}
5120
5121 // Load Short (16 bit signed) into Long Register
5122 instruct loadS2L(rRegL dst, memory mem)
5123 %{
5124 match(Set dst (ConvI2L (LoadS mem)));
5125
5126 ins_cost(125);
5127 format %{ "movswq $dst, $mem\t# short -> long" %}
5128
5129 ins_encode %{
5130 __ movswq($dst$$Register, $mem$$Address);
5131 %}
5132
5133 ins_pipe(ialu_reg_mem);
5134 %}
5135
5136 // Load Unsigned Short/Char (16 bit UNsigned)
5137 instruct loadUS(rRegI dst, memory mem)
5138 %{
5139 match(Set dst (LoadUS mem));
5140
5141 ins_cost(125);
5142 format %{ "movzwl $dst, $mem\t# ushort/char" %}
5143
5144 ins_encode %{
5145 __ movzwl($dst$$Register, $mem$$Address);
5146 %}
5147
5148 ins_pipe(ialu_reg_mem);
5149 %}
5150
5151 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5152 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5153 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5154
5155 ins_cost(125);
5156 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
5157 ins_encode %{
5158 __ movsbl($dst$$Register, $mem$$Address);
5159 %}
5160 ins_pipe(ialu_reg_mem);
5161 %}
5162
5163 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5164 instruct loadUS2L(rRegL dst, memory mem)
5165 %{
5166 match(Set dst (ConvI2L (LoadUS mem)));
5167
5168 ins_cost(125);
5169 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
5170
5171 ins_encode %{
5172 __ movzwq($dst$$Register, $mem$$Address);
5173 %}
5174
5175 ins_pipe(ialu_reg_mem);
5176 %}
5177
5178 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5179 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5180 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5181
5182 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
5183 ins_encode %{
5184 __ movzbq($dst$$Register, $mem$$Address);
5185 %}
5186 ins_pipe(ialu_reg_mem);
5187 %}
5188
5189 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
5190 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5191 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5192 effect(KILL cr);
5193
5194 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
5195 "andl $dst, right_n_bits($mask, 16)" %}
5196 ins_encode %{
5197 Register Rdst = $dst$$Register;
5198 __ movzwq(Rdst, $mem$$Address);
5199 __ andl(Rdst, $mask$$constant & right_n_bits(16));
5200 %}
5201 ins_pipe(ialu_reg_mem);
5202 %}
5203
5204 // Load Integer
5205 instruct loadI(rRegI dst, memory mem)
5206 %{
5207 match(Set dst (LoadI mem));
5208
5209 ins_cost(125);
5210 format %{ "movl $dst, $mem\t# int" %}
5211
5212 ins_encode %{
5213 __ movl($dst$$Register, $mem$$Address);
5214 %}
5215
5216 ins_pipe(ialu_reg_mem);
5217 %}
5218
5219 // Load Integer (32 bit signed) to Byte (8 bit signed)
5220 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5221 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5222
5223 ins_cost(125);
5224 format %{ "movsbl $dst, $mem\t# int -> byte" %}
5225 ins_encode %{
5226 __ movsbl($dst$$Register, $mem$$Address);
5227 %}
5228 ins_pipe(ialu_reg_mem);
5229 %}
5230
5231 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5232 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5233 match(Set dst (AndI (LoadI mem) mask));
5234
5235 ins_cost(125);
5236 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
5237 ins_encode %{
5238 __ movzbl($dst$$Register, $mem$$Address);
5239 %}
5240 ins_pipe(ialu_reg_mem);
5241 %}
5242
5243 // Load Integer (32 bit signed) to Short (16 bit signed)
5244 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5245 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5246
5247 ins_cost(125);
5248 format %{ "movswl $dst, $mem\t# int -> short" %}
5249 ins_encode %{
5250 __ movswl($dst$$Register, $mem$$Address);
5251 %}
5252 ins_pipe(ialu_reg_mem);
5253 %}
5254
5255 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5256 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5257 match(Set dst (AndI (LoadI mem) mask));
5258
5259 ins_cost(125);
5260 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5261 ins_encode %{
5262 __ movzwl($dst$$Register, $mem$$Address);
5263 %}
5264 ins_pipe(ialu_reg_mem);
5265 %}
5266
5267 // Load Integer into Long Register
5268 instruct loadI2L(rRegL dst, memory mem)
5269 %{
5270 match(Set dst (ConvI2L (LoadI mem)));
5271
5272 ins_cost(125);
5273 format %{ "movslq $dst, $mem\t# int -> long" %}
5274
5275 ins_encode %{
5276 __ movslq($dst$$Register, $mem$$Address);
5277 %}
5278
5279 ins_pipe(ialu_reg_mem);
5280 %}
5281
5282 // Load Integer with mask 0xFF into Long Register
5283 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5284 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5285
5286 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5287 ins_encode %{
5288 __ movzbq($dst$$Register, $mem$$Address);
5289 %}
5290 ins_pipe(ialu_reg_mem);
5291 %}
5292
5293 // Load Integer with mask 0xFFFF into Long Register
5294 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5295 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5296
5297 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5298 ins_encode %{
5299 __ movzwq($dst$$Register, $mem$$Address);
5300 %}
5301 ins_pipe(ialu_reg_mem);
5302 %}
5303
5304 // Load Integer with a 31-bit mask into Long Register
5305 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5306 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5307 effect(KILL cr);
5308
5309 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5310 "andl $dst, $mask" %}
5311 ins_encode %{
5312 Register Rdst = $dst$$Register;
5313 __ movl(Rdst, $mem$$Address);
5314 __ andl(Rdst, $mask$$constant);
5315 %}
5316 ins_pipe(ialu_reg_mem);
5317 %}
5318
5319 // Load Unsigned Integer into Long Register
5320 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5321 %{
5322 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5323
5324 ins_cost(125);
5325 format %{ "movl $dst, $mem\t# uint -> long" %}
5326
5327 ins_encode %{
5328 __ movl($dst$$Register, $mem$$Address);
5329 %}
5330
5331 ins_pipe(ialu_reg_mem);
5332 %}
5333
5334 // Load Long
5335 instruct loadL(rRegL dst, memory mem)
5336 %{
5337 match(Set dst (LoadL mem));
5338
5339 ins_cost(125);
5340 format %{ "movq $dst, $mem\t# long" %}
5341
5342 ins_encode %{
5343 __ movq($dst$$Register, $mem$$Address);
5344 %}
5345
5346 ins_pipe(ialu_reg_mem); // XXX
5347 %}
5348
5349 // Load Range
5350 instruct loadRange(rRegI dst, memory mem)
5351 %{
5352 match(Set dst (LoadRange mem));
5353
5354 ins_cost(125); // XXX
5355 format %{ "movl $dst, $mem\t# range" %}
5356 opcode(0x8B);
5357 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5358 ins_pipe(ialu_reg_mem);
5359 %}
5360
5361 // Load Pointer
5362 instruct loadP(rRegP dst, memory mem)
5363 %{
5364 match(Set dst (LoadP mem));
5365
5366 ins_cost(125); // XXX
5367 format %{ "movq $dst, $mem\t# ptr" %}
5368 opcode(0x8B);
5369 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5370 ins_pipe(ialu_reg_mem); // XXX
5371 %}
5372
5373 // Load Compressed Pointer
5374 instruct loadN(rRegN dst, memory mem)
5375 %{
5376 match(Set dst (LoadN mem));
5377
5378 ins_cost(125); // XXX
5379 format %{ "movl $dst, $mem\t# compressed ptr" %}
5380 ins_encode %{
5381 __ movl($dst$$Register, $mem$$Address);
5382 %}
5383 ins_pipe(ialu_reg_mem); // XXX
5384 %}
5385
5386
5387 // Load Klass Pointer
5388 instruct loadKlass(rRegP dst, memory mem)
5389 %{
5390 match(Set dst (LoadKlass mem));
5391
5392 ins_cost(125); // XXX
5393 format %{ "movq $dst, $mem\t# class" %}
5394 opcode(0x8B);
5395 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5396 ins_pipe(ialu_reg_mem); // XXX
5397 %}
5398
5399 // Load narrow Klass Pointer
5400 instruct loadNKlass(rRegN dst, memory mem)
5401 %{
5402 match(Set dst (LoadNKlass mem));
5403
5404 ins_cost(125); // XXX
5405 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5406 ins_encode %{
5407 __ movl($dst$$Register, $mem$$Address);
5408 %}
5409 ins_pipe(ialu_reg_mem); // XXX
5410 %}
5411
5412 // Load Float
5413 instruct loadF(regF dst, memory mem)
5414 %{
5415 match(Set dst (LoadF mem));
5416
5417 ins_cost(145); // XXX
5418 format %{ "movss $dst, $mem\t# float" %}
5419 ins_encode %{
5420 __ movflt($dst$$XMMRegister, $mem$$Address);
5421 %}
5422 ins_pipe(pipe_slow); // XXX
5423 %}
5424
5425
5426 // Load Float
5427 instruct MoveF2VL(vlRegF dst, regF src) %{
5428 match(Set dst src);
5429 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5430 ins_encode %{
5431 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5432 %}
5433 ins_pipe( fpu_reg_reg );
5434 %}
5435
5436 // Load Float
5437 instruct MoveF2LEG(legRegF dst, regF src) %{
5438 match(Set dst src);
5439 format %{ "movss $dst,$src\t! if src != dst load float (4 bytes)" %}
5440 ins_encode %{
5441 if ($dst$$reg != $src$$reg) {
5442 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5443 }
5444 %}
5445 ins_pipe( fpu_reg_reg );
5446 %}
5447
5448 // Load Float
5449 instruct MoveVL2F(regF dst, vlRegF src) %{
5450 match(Set dst src);
5451 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5452 ins_encode %{
5453 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5454 %}
5455 ins_pipe( fpu_reg_reg );
5456 %}
5457
5458 // Load Float
5459 instruct MoveLEG2F(regF dst, legRegF src) %{
5460 match(Set dst src);
5461 format %{ "movss $dst,$src\t! if src != dst load float (4 bytes)" %}
5462 ins_encode %{
5463 if ($dst$$reg != $src$$reg) {
5464 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5465 }
5466 %}
5467 ins_pipe( fpu_reg_reg );
5468 %}
5469
5470 // Load Double
5471 instruct loadD_partial(regD dst, memory mem)
5472 %{
5473 predicate(!UseXmmLoadAndClearUpper);
5474 match(Set dst (LoadD mem));
5475
5476 ins_cost(145); // XXX
5477 format %{ "movlpd $dst, $mem\t# double" %}
5478 ins_encode %{
5479 __ movdbl($dst$$XMMRegister, $mem$$Address);
5480 %}
5481 ins_pipe(pipe_slow); // XXX
5482 %}
5483
5484
5485 instruct loadD(regD dst, memory mem)
5486 %{
5487 predicate(UseXmmLoadAndClearUpper);
5488 match(Set dst (LoadD mem));
5489
5490 ins_cost(145); // XXX
5491 format %{ "movsd $dst, $mem\t# double" %}
5492 ins_encode %{
5493 __ movdbl($dst$$XMMRegister, $mem$$Address);
5494 %}
5495 ins_pipe(pipe_slow); // XXX
5496 %}
5497
5498 // Load Double
5499 instruct MoveD2VL(vlRegD dst, regD src) %{
5500 match(Set dst src);
5501 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5502 ins_encode %{
5503 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5504 %}
5505 ins_pipe( fpu_reg_reg );
5506 %}
5507
5508 // Load Double
5509 instruct MoveD2LEG(legRegD dst, regD src) %{
5510 match(Set dst src);
5511 format %{ "movsd $dst,$src\t! if src != dst load double (8 bytes)" %}
5512 ins_encode %{
5513 if ($dst$$reg != $src$$reg) {
5514 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5515 }
5516 %}
5517 ins_pipe( fpu_reg_reg );
5518 %}
5519
5520 // Load Double
5521 instruct MoveVL2D(regD dst, vlRegD src) %{
5522 match(Set dst src);
5523 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5524 ins_encode %{
5525 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5526 %}
5527 ins_pipe( fpu_reg_reg );
5528 %}
5529
5530 // Load Double
5531 instruct MoveLEG2D(regD dst, legRegD src) %{
5532 match(Set dst src);
5533 format %{ "movsd $dst,$src\t! if src != dst load double (8 bytes)" %}
5534 ins_encode %{
5535 if ($dst$$reg != $src$$reg) {
5536 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5537 }
5538 %}
5539 ins_pipe( fpu_reg_reg );
5540 %}
5541
5542 // Load Effective Address
5543 instruct leaP8(rRegP dst, indOffset8 mem)
5544 %{
5545 match(Set dst mem);
5546
5547 ins_cost(110); // XXX
5548 format %{ "leaq $dst, $mem\t# ptr 8" %}
5549 opcode(0x8D);
5550 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5551 ins_pipe(ialu_reg_reg_fat);
5552 %}
5553
5554 instruct leaP32(rRegP dst, indOffset32 mem)
5555 %{
5556 match(Set dst mem);
5557
5558 ins_cost(110);
5559 format %{ "leaq $dst, $mem\t# ptr 32" %}
5560 opcode(0x8D);
5561 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5562 ins_pipe(ialu_reg_reg_fat);
5563 %}
5564
5565 // instruct leaPIdx(rRegP dst, indIndex mem)
5566 // %{
5567 // match(Set dst mem);
5568
5569 // ins_cost(110);
5570 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5571 // opcode(0x8D);
5572 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5573 // ins_pipe(ialu_reg_reg_fat);
5574 // %}
5575
5576 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5577 %{
5578 match(Set dst mem);
5579
5580 ins_cost(110);
5581 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5582 opcode(0x8D);
5583 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5584 ins_pipe(ialu_reg_reg_fat);
5585 %}
5586
5587 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5588 %{
5589 match(Set dst mem);
5590
5591 ins_cost(110);
5592 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5593 opcode(0x8D);
5594 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5595 ins_pipe(ialu_reg_reg_fat);
5596 %}
5597
5598 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5599 %{
5600 match(Set dst mem);
5601
5602 ins_cost(110);
5603 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5604 opcode(0x8D);
5605 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5606 ins_pipe(ialu_reg_reg_fat);
5607 %}
5608
5609 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5610 %{
5611 match(Set dst mem);
5612
5613 ins_cost(110);
5614 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5615 opcode(0x8D);
5616 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5617 ins_pipe(ialu_reg_reg_fat);
5618 %}
5619
5620 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5621 %{
5622 match(Set dst mem);
5623
5624 ins_cost(110);
5625 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5626 opcode(0x8D);
5627 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5628 ins_pipe(ialu_reg_reg_fat);
5629 %}
5630
5631 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5632 %{
5633 match(Set dst mem);
5634
5635 ins_cost(110);
5636 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5637 opcode(0x8D);
5638 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5639 ins_pipe(ialu_reg_reg_fat);
5640 %}
5641
5642 // Load Effective Address which uses Narrow (32-bits) oop
5643 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5644 %{
5645 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5646 match(Set dst mem);
5647
5648 ins_cost(110);
5649 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5650 opcode(0x8D);
5651 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5652 ins_pipe(ialu_reg_reg_fat);
5653 %}
5654
5655 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5656 %{
5657 predicate(Universe::narrow_oop_shift() == 0);
5658 match(Set dst mem);
5659
5660 ins_cost(110); // XXX
5661 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5662 opcode(0x8D);
5663 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5664 ins_pipe(ialu_reg_reg_fat);
5665 %}
5666
5667 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5668 %{
5669 predicate(Universe::narrow_oop_shift() == 0);
5670 match(Set dst mem);
5671
5672 ins_cost(110);
5673 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5674 opcode(0x8D);
5675 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5676 ins_pipe(ialu_reg_reg_fat);
5677 %}
5678
5679 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5680 %{
5681 predicate(Universe::narrow_oop_shift() == 0);
5682 match(Set dst mem);
5683
5684 ins_cost(110);
5685 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5686 opcode(0x8D);
5687 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5688 ins_pipe(ialu_reg_reg_fat);
5689 %}
5690
5691 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5692 %{
5693 predicate(Universe::narrow_oop_shift() == 0);
5694 match(Set dst mem);
5695
5696 ins_cost(110);
5697 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5698 opcode(0x8D);
5699 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5700 ins_pipe(ialu_reg_reg_fat);
5701 %}
5702
5703 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5704 %{
5705 predicate(Universe::narrow_oop_shift() == 0);
5706 match(Set dst mem);
5707
5708 ins_cost(110);
5709 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5710 opcode(0x8D);
5711 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5712 ins_pipe(ialu_reg_reg_fat);
5713 %}
5714
5715 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5716 %{
5717 predicate(Universe::narrow_oop_shift() == 0);
5718 match(Set dst mem);
5719
5720 ins_cost(110);
5721 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5722 opcode(0x8D);
5723 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5724 ins_pipe(ialu_reg_reg_fat);
5725 %}
5726
5727 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5728 %{
5729 predicate(Universe::narrow_oop_shift() == 0);
5730 match(Set dst mem);
5731
5732 ins_cost(110);
5733 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5734 opcode(0x8D);
5735 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5736 ins_pipe(ialu_reg_reg_fat);
5737 %}
5738
5739 instruct loadConI(rRegI dst, immI src)
5740 %{
5741 match(Set dst src);
5742
5743 format %{ "movl $dst, $src\t# int" %}
5744 ins_encode(load_immI(dst, src));
5745 ins_pipe(ialu_reg_fat); // XXX
5746 %}
5747
5748 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5749 %{
5750 match(Set dst src);
5751 effect(KILL cr);
5752
5753 ins_cost(50);
5754 format %{ "xorl $dst, $dst\t# int" %}
5755 opcode(0x33); /* + rd */
5756 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5757 ins_pipe(ialu_reg);
5758 %}
5759
5760 instruct loadConL(rRegL dst, immL src)
5761 %{
5762 match(Set dst src);
5763
5764 ins_cost(150);
5765 format %{ "movq $dst, $src\t# long" %}
5766 ins_encode(load_immL(dst, src));
5767 ins_pipe(ialu_reg);
5768 %}
5769
5770 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5771 %{
5772 match(Set dst src);
5773 effect(KILL cr);
5774
5775 ins_cost(50);
5776 format %{ "xorl $dst, $dst\t# long" %}
5777 opcode(0x33); /* + rd */
5778 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5779 ins_pipe(ialu_reg); // XXX
5780 %}
5781
5782 instruct loadConUL32(rRegL dst, immUL32 src)
5783 %{
5784 match(Set dst src);
5785
5786 ins_cost(60);
5787 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5788 ins_encode(load_immUL32(dst, src));
5789 ins_pipe(ialu_reg);
5790 %}
5791
5792 instruct loadConL32(rRegL dst, immL32 src)
5793 %{
5794 match(Set dst src);
5795
5796 ins_cost(70);
5797 format %{ "movq $dst, $src\t# long (32-bit)" %}
5798 ins_encode(load_immL32(dst, src));
5799 ins_pipe(ialu_reg);
5800 %}
5801
5802 instruct loadConP(rRegP dst, immP con) %{
5803 match(Set dst con);
5804
5805 format %{ "movq $dst, $con\t# ptr" %}
5806 ins_encode(load_immP(dst, con));
5807 ins_pipe(ialu_reg_fat); // XXX
5808 %}
5809
5810 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5811 %{
5812 match(Set dst src);
5813 effect(KILL cr);
5814
5815 ins_cost(50);
5816 format %{ "xorl $dst, $dst\t# ptr" %}
5817 opcode(0x33); /* + rd */
5818 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5819 ins_pipe(ialu_reg);
5820 %}
5821
5822 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5823 %{
5824 match(Set dst src);
5825 effect(KILL cr);
5826
5827 ins_cost(60);
5828 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5829 ins_encode(load_immP31(dst, src));
5830 ins_pipe(ialu_reg);
5831 %}
5832
5833 instruct loadConF(regF dst, immF con) %{
5834 match(Set dst con);
5835 ins_cost(125);
5836 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5837 ins_encode %{
5838 __ movflt($dst$$XMMRegister, $constantaddress($con));
5839 %}
5840 ins_pipe(pipe_slow);
5841 %}
5842
5843 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5844 match(Set dst src);
5845 effect(KILL cr);
5846 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5847 ins_encode %{
5848 __ xorq($dst$$Register, $dst$$Register);
5849 %}
5850 ins_pipe(ialu_reg);
5851 %}
5852
5853 instruct loadConN(rRegN dst, immN src) %{
5854 match(Set dst src);
5855
5856 ins_cost(125);
5857 format %{ "movl $dst, $src\t# compressed ptr" %}
5858 ins_encode %{
5859 address con = (address)$src$$constant;
5860 if (con == NULL) {
5861 ShouldNotReachHere();
5862 } else {
5863 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5864 }
5865 %}
5866 ins_pipe(ialu_reg_fat); // XXX
5867 %}
5868
5869 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5870 match(Set dst src);
5871
5872 ins_cost(125);
5873 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5874 ins_encode %{
5875 address con = (address)$src$$constant;
5876 if (con == NULL) {
5877 ShouldNotReachHere();
5878 } else {
5879 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5880 }
5881 %}
5882 ins_pipe(ialu_reg_fat); // XXX
5883 %}
5884
5885 instruct loadConF0(regF dst, immF0 src)
5886 %{
5887 match(Set dst src);
5888 ins_cost(100);
5889
5890 format %{ "xorps $dst, $dst\t# float 0.0" %}
5891 ins_encode %{
5892 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5893 %}
5894 ins_pipe(pipe_slow);
5895 %}
5896
5897 // Use the same format since predicate() can not be used here.
5898 instruct loadConD(regD dst, immD con) %{
5899 match(Set dst con);
5900 ins_cost(125);
5901 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5902 ins_encode %{
5903 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5904 %}
5905 ins_pipe(pipe_slow);
5906 %}
5907
5908 instruct loadConD0(regD dst, immD0 src)
5909 %{
5910 match(Set dst src);
5911 ins_cost(100);
5912
5913 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5914 ins_encode %{
5915 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5916 %}
5917 ins_pipe(pipe_slow);
5918 %}
5919
5920 instruct loadSSI(rRegI dst, stackSlotI src)
5921 %{
5922 match(Set dst src);
5923
5924 ins_cost(125);
5925 format %{ "movl $dst, $src\t# int stk" %}
5926 opcode(0x8B);
5927 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5928 ins_pipe(ialu_reg_mem);
5929 %}
5930
5931 instruct loadSSL(rRegL dst, stackSlotL src)
5932 %{
5933 match(Set dst src);
5934
5935 ins_cost(125);
5936 format %{ "movq $dst, $src\t# long stk" %}
5937 opcode(0x8B);
5938 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5939 ins_pipe(ialu_reg_mem);
5940 %}
5941
5942 instruct loadSSP(rRegP dst, stackSlotP src)
5943 %{
5944 match(Set dst src);
5945
5946 ins_cost(125);
5947 format %{ "movq $dst, $src\t# ptr stk" %}
5948 opcode(0x8B);
5949 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5950 ins_pipe(ialu_reg_mem);
5951 %}
5952
5953 instruct loadSSF(regF dst, stackSlotF src)
5954 %{
5955 match(Set dst src);
5956
5957 ins_cost(125);
5958 format %{ "movss $dst, $src\t# float stk" %}
5959 ins_encode %{
5960 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5961 %}
5962 ins_pipe(pipe_slow); // XXX
5963 %}
5964
5965 // Use the same format since predicate() can not be used here.
5966 instruct loadSSD(regD dst, stackSlotD src)
5967 %{
5968 match(Set dst src);
5969
5970 ins_cost(125);
5971 format %{ "movsd $dst, $src\t# double stk" %}
5972 ins_encode %{
5973 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5974 %}
5975 ins_pipe(pipe_slow); // XXX
5976 %}
5977
5978 // Prefetch instructions for allocation.
5979 // Must be safe to execute with invalid address (cannot fault).
5980
5981 instruct prefetchAlloc( memory mem ) %{
5982 predicate(AllocatePrefetchInstr==3);
5983 match(PrefetchAllocation mem);
5984 ins_cost(125);
5985
5986 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5987 ins_encode %{
5988 __ prefetchw($mem$$Address);
5989 %}
5990 ins_pipe(ialu_mem);
5991 %}
5992
5993 instruct prefetchAllocNTA( memory mem ) %{
5994 predicate(AllocatePrefetchInstr==0);
5995 match(PrefetchAllocation mem);
5996 ins_cost(125);
5997
5998 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5999 ins_encode %{
6000 __ prefetchnta($mem$$Address);
6001 %}
6002 ins_pipe(ialu_mem);
6003 %}
6004
6005 instruct prefetchAllocT0( memory mem ) %{
6006 predicate(AllocatePrefetchInstr==1);
6007 match(PrefetchAllocation mem);
6008 ins_cost(125);
6009
6010 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
6011 ins_encode %{
6012 __ prefetcht0($mem$$Address);
6013 %}
6014 ins_pipe(ialu_mem);
6015 %}
6016
6017 instruct prefetchAllocT2( memory mem ) %{
6018 predicate(AllocatePrefetchInstr==2);
6019 match(PrefetchAllocation mem);
6020 ins_cost(125);
6021
6022 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
6023 ins_encode %{
6024 __ prefetcht2($mem$$Address);
6025 %}
6026 ins_pipe(ialu_mem);
6027 %}
6028
6029 //----------Store Instructions-------------------------------------------------
6030
6031 // Store Byte
6032 instruct storeB(memory mem, rRegI src)
6033 %{
6034 match(Set mem (StoreB mem src));
6035
6036 ins_cost(125); // XXX
6037 format %{ "movb $mem, $src\t# byte" %}
6038 opcode(0x88);
6039 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
6040 ins_pipe(ialu_mem_reg);
6041 %}
6042
6043 // Store Char/Short
6044 instruct storeC(memory mem, rRegI src)
6045 %{
6046 match(Set mem (StoreC mem src));
6047
6048 ins_cost(125); // XXX
6049 format %{ "movw $mem, $src\t# char/short" %}
6050 opcode(0x89);
6051 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6052 ins_pipe(ialu_mem_reg);
6053 %}
6054
6055 // Store Integer
6056 instruct storeI(memory mem, rRegI src)
6057 %{
6058 match(Set mem (StoreI mem src));
6059
6060 ins_cost(125); // XXX
6061 format %{ "movl $mem, $src\t# int" %}
6062 opcode(0x89);
6063 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6064 ins_pipe(ialu_mem_reg);
6065 %}
6066
6067 // Store Long
6068 instruct storeL(memory mem, rRegL src)
6069 %{
6070 match(Set mem (StoreL mem src));
6071
6072 ins_cost(125); // XXX
6073 format %{ "movq $mem, $src\t# long" %}
6074 opcode(0x89);
6075 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6076 ins_pipe(ialu_mem_reg); // XXX
6077 %}
6078
6079 // Store Pointer
6080 instruct storeP(memory mem, any_RegP src)
6081 %{
6082 match(Set mem (StoreP mem src));
6083
6084 ins_cost(125); // XXX
6085 format %{ "movq $mem, $src\t# ptr" %}
6086 opcode(0x89);
6087 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6088 ins_pipe(ialu_mem_reg);
6089 %}
6090
6091 instruct storeImmP0(memory mem, immP0 zero)
6092 %{
6093 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6094 match(Set mem (StoreP mem zero));
6095
6096 ins_cost(125); // XXX
6097 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
6098 ins_encode %{
6099 __ movq($mem$$Address, r12);
6100 %}
6101 ins_pipe(ialu_mem_reg);
6102 %}
6103
6104 // Store NULL Pointer, mark word, or other simple pointer constant.
6105 instruct storeImmP(memory mem, immP31 src)
6106 %{
6107 match(Set mem (StoreP mem src));
6108
6109 ins_cost(150); // XXX
6110 format %{ "movq $mem, $src\t# ptr" %}
6111 opcode(0xC7); /* C7 /0 */
6112 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6113 ins_pipe(ialu_mem_imm);
6114 %}
6115
6116 // Store Compressed Pointer
6117 instruct storeN(memory mem, rRegN src)
6118 %{
6119 match(Set mem (StoreN mem src));
6120
6121 ins_cost(125); // XXX
6122 format %{ "movl $mem, $src\t# compressed ptr" %}
6123 ins_encode %{
6124 __ movl($mem$$Address, $src$$Register);
6125 %}
6126 ins_pipe(ialu_mem_reg);
6127 %}
6128
6129 instruct storeNKlass(memory mem, rRegN src)
6130 %{
6131 match(Set mem (StoreNKlass mem src));
6132
6133 ins_cost(125); // XXX
6134 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6135 ins_encode %{
6136 __ movl($mem$$Address, $src$$Register);
6137 %}
6138 ins_pipe(ialu_mem_reg);
6139 %}
6140
6141 instruct storeImmN0(memory mem, immN0 zero)
6142 %{
6143 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
6144 match(Set mem (StoreN mem zero));
6145
6146 ins_cost(125); // XXX
6147 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6148 ins_encode %{
6149 __ movl($mem$$Address, r12);
6150 %}
6151 ins_pipe(ialu_mem_reg);
6152 %}
6153
6154 instruct storeImmN(memory mem, immN src)
6155 %{
6156 match(Set mem (StoreN mem src));
6157
6158 ins_cost(150); // XXX
6159 format %{ "movl $mem, $src\t# compressed ptr" %}
6160 ins_encode %{
6161 address con = (address)$src$$constant;
6162 if (con == NULL) {
6163 __ movl($mem$$Address, (int32_t)0);
6164 } else {
6165 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6166 }
6167 %}
6168 ins_pipe(ialu_mem_imm);
6169 %}
6170
6171 instruct storeImmNKlass(memory mem, immNKlass src)
6172 %{
6173 match(Set mem (StoreNKlass mem src));
6174
6175 ins_cost(150); // XXX
6176 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6177 ins_encode %{
6178 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6179 %}
6180 ins_pipe(ialu_mem_imm);
6181 %}
6182
6183 // Store Integer Immediate
6184 instruct storeImmI0(memory mem, immI0 zero)
6185 %{
6186 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6187 match(Set mem (StoreI mem zero));
6188
6189 ins_cost(125); // XXX
6190 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6191 ins_encode %{
6192 __ movl($mem$$Address, r12);
6193 %}
6194 ins_pipe(ialu_mem_reg);
6195 %}
6196
6197 instruct storeImmI(memory mem, immI src)
6198 %{
6199 match(Set mem (StoreI mem src));
6200
6201 ins_cost(150);
6202 format %{ "movl $mem, $src\t# int" %}
6203 opcode(0xC7); /* C7 /0 */
6204 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6205 ins_pipe(ialu_mem_imm);
6206 %}
6207
6208 // Store Long Immediate
6209 instruct storeImmL0(memory mem, immL0 zero)
6210 %{
6211 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6212 match(Set mem (StoreL mem zero));
6213
6214 ins_cost(125); // XXX
6215 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6216 ins_encode %{
6217 __ movq($mem$$Address, r12);
6218 %}
6219 ins_pipe(ialu_mem_reg);
6220 %}
6221
6222 instruct storeImmL(memory mem, immL32 src)
6223 %{
6224 match(Set mem (StoreL mem src));
6225
6226 ins_cost(150);
6227 format %{ "movq $mem, $src\t# long" %}
6228 opcode(0xC7); /* C7 /0 */
6229 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6230 ins_pipe(ialu_mem_imm);
6231 %}
6232
6233 // Store Short/Char Immediate
6234 instruct storeImmC0(memory mem, immI0 zero)
6235 %{
6236 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6237 match(Set mem (StoreC mem zero));
6238
6239 ins_cost(125); // XXX
6240 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6241 ins_encode %{
6242 __ movw($mem$$Address, r12);
6243 %}
6244 ins_pipe(ialu_mem_reg);
6245 %}
6246
6247 instruct storeImmI16(memory mem, immI16 src)
6248 %{
6249 predicate(UseStoreImmI16);
6250 match(Set mem (StoreC mem src));
6251
6252 ins_cost(150);
6253 format %{ "movw $mem, $src\t# short/char" %}
6254 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6255 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6256 ins_pipe(ialu_mem_imm);
6257 %}
6258
6259 // Store Byte Immediate
6260 instruct storeImmB0(memory mem, immI0 zero)
6261 %{
6262 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6263 match(Set mem (StoreB mem zero));
6264
6265 ins_cost(125); // XXX
6266 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6267 ins_encode %{
6268 __ movb($mem$$Address, r12);
6269 %}
6270 ins_pipe(ialu_mem_reg);
6271 %}
6272
6273 instruct storeImmB(memory mem, immI8 src)
6274 %{
6275 match(Set mem (StoreB mem src));
6276
6277 ins_cost(150); // XXX
6278 format %{ "movb $mem, $src\t# byte" %}
6279 opcode(0xC6); /* C6 /0 */
6280 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6281 ins_pipe(ialu_mem_imm);
6282 %}
6283
6284 // Store CMS card-mark Immediate
6285 instruct storeImmCM0_reg(memory mem, immI0 zero)
6286 %{
6287 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6288 match(Set mem (StoreCM mem zero));
6289
6290 ins_cost(125); // XXX
6291 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6292 ins_encode %{
6293 __ movb($mem$$Address, r12);
6294 %}
6295 ins_pipe(ialu_mem_reg);
6296 %}
6297
6298 instruct storeImmCM0(memory mem, immI0 src)
6299 %{
6300 match(Set mem (StoreCM mem src));
6301
6302 ins_cost(150); // XXX
6303 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6304 opcode(0xC6); /* C6 /0 */
6305 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6306 ins_pipe(ialu_mem_imm);
6307 %}
6308
6309 // Store Float
6310 instruct storeF(memory mem, regF src)
6311 %{
6312 match(Set mem (StoreF mem src));
6313
6314 ins_cost(95); // XXX
6315 format %{ "movss $mem, $src\t# float" %}
6316 ins_encode %{
6317 __ movflt($mem$$Address, $src$$XMMRegister);
6318 %}
6319 ins_pipe(pipe_slow); // XXX
6320 %}
6321
6322 // Store immediate Float value (it is faster than store from XMM register)
6323 instruct storeF0(memory mem, immF0 zero)
6324 %{
6325 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6326 match(Set mem (StoreF mem zero));
6327
6328 ins_cost(25); // XXX
6329 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
6330 ins_encode %{
6331 __ movl($mem$$Address, r12);
6332 %}
6333 ins_pipe(ialu_mem_reg);
6334 %}
6335
6336 instruct storeF_imm(memory mem, immF src)
6337 %{
6338 match(Set mem (StoreF mem src));
6339
6340 ins_cost(50);
6341 format %{ "movl $mem, $src\t# float" %}
6342 opcode(0xC7); /* C7 /0 */
6343 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6344 ins_pipe(ialu_mem_imm);
6345 %}
6346
6347 // Store Double
6348 instruct storeD(memory mem, regD src)
6349 %{
6350 match(Set mem (StoreD mem src));
6351
6352 ins_cost(95); // XXX
6353 format %{ "movsd $mem, $src\t# double" %}
6354 ins_encode %{
6355 __ movdbl($mem$$Address, $src$$XMMRegister);
6356 %}
6357 ins_pipe(pipe_slow); // XXX
6358 %}
6359
6360 // Store immediate double 0.0 (it is faster than store from XMM register)
6361 instruct storeD0_imm(memory mem, immD0 src)
6362 %{
6363 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6364 match(Set mem (StoreD mem src));
6365
6366 ins_cost(50);
6367 format %{ "movq $mem, $src\t# double 0." %}
6368 opcode(0xC7); /* C7 /0 */
6369 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6370 ins_pipe(ialu_mem_imm);
6371 %}
6372
6373 instruct storeD0(memory mem, immD0 zero)
6374 %{
6375 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6376 match(Set mem (StoreD mem zero));
6377
6378 ins_cost(25); // XXX
6379 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6380 ins_encode %{
6381 __ movq($mem$$Address, r12);
6382 %}
6383 ins_pipe(ialu_mem_reg);
6384 %}
6385
6386 instruct storeSSI(stackSlotI dst, rRegI src)
6387 %{
6388 match(Set dst src);
6389
6390 ins_cost(100);
6391 format %{ "movl $dst, $src\t# int stk" %}
6392 opcode(0x89);
6393 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6394 ins_pipe( ialu_mem_reg );
6395 %}
6396
6397 instruct storeSSL(stackSlotL dst, rRegL src)
6398 %{
6399 match(Set dst src);
6400
6401 ins_cost(100);
6402 format %{ "movq $dst, $src\t# long stk" %}
6403 opcode(0x89);
6404 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6405 ins_pipe(ialu_mem_reg);
6406 %}
6407
6408 instruct storeSSP(stackSlotP dst, rRegP src)
6409 %{
6410 match(Set dst src);
6411
6412 ins_cost(100);
6413 format %{ "movq $dst, $src\t# ptr stk" %}
6414 opcode(0x89);
6415 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6416 ins_pipe(ialu_mem_reg);
6417 %}
6418
6419 instruct storeSSF(stackSlotF dst, regF src)
6420 %{
6421 match(Set dst src);
6422
6423 ins_cost(95); // XXX
6424 format %{ "movss $dst, $src\t# float stk" %}
6425 ins_encode %{
6426 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6427 %}
6428 ins_pipe(pipe_slow); // XXX
6429 %}
6430
6431 instruct storeSSD(stackSlotD dst, regD src)
6432 %{
6433 match(Set dst src);
6434
6435 ins_cost(95); // XXX
6436 format %{ "movsd $dst, $src\t# double stk" %}
6437 ins_encode %{
6438 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6439 %}
6440 ins_pipe(pipe_slow); // XXX
6441 %}
6442
6443 //----------BSWAP Instructions-------------------------------------------------
6444 instruct bytes_reverse_int(rRegI dst) %{
6445 match(Set dst (ReverseBytesI dst));
6446
6447 format %{ "bswapl $dst" %}
6448 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6449 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6450 ins_pipe( ialu_reg );
6451 %}
6452
6453 instruct bytes_reverse_long(rRegL dst) %{
6454 match(Set dst (ReverseBytesL dst));
6455
6456 format %{ "bswapq $dst" %}
6457 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6458 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6459 ins_pipe( ialu_reg);
6460 %}
6461
6462 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6463 match(Set dst (ReverseBytesUS dst));
6464 effect(KILL cr);
6465
6466 format %{ "bswapl $dst\n\t"
6467 "shrl $dst,16\n\t" %}
6468 ins_encode %{
6469 __ bswapl($dst$$Register);
6470 __ shrl($dst$$Register, 16);
6471 %}
6472 ins_pipe( ialu_reg );
6473 %}
6474
6475 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6476 match(Set dst (ReverseBytesS dst));
6477 effect(KILL cr);
6478
6479 format %{ "bswapl $dst\n\t"
6480 "sar $dst,16\n\t" %}
6481 ins_encode %{
6482 __ bswapl($dst$$Register);
6483 __ sarl($dst$$Register, 16);
6484 %}
6485 ins_pipe( ialu_reg );
6486 %}
6487
6488 //---------- Zeros Count Instructions ------------------------------------------
6489
6490 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6491 predicate(UseCountLeadingZerosInstruction);
6492 match(Set dst (CountLeadingZerosI src));
6493 effect(KILL cr);
6494
6495 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6496 ins_encode %{
6497 __ lzcntl($dst$$Register, $src$$Register);
6498 %}
6499 ins_pipe(ialu_reg);
6500 %}
6501
6502 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6503 predicate(!UseCountLeadingZerosInstruction);
6504 match(Set dst (CountLeadingZerosI src));
6505 effect(KILL cr);
6506
6507 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6508 "jnz skip\n\t"
6509 "movl $dst, -1\n"
6510 "skip:\n\t"
6511 "negl $dst\n\t"
6512 "addl $dst, 31" %}
6513 ins_encode %{
6514 Register Rdst = $dst$$Register;
6515 Register Rsrc = $src$$Register;
6516 Label skip;
6517 __ bsrl(Rdst, Rsrc);
6518 __ jccb(Assembler::notZero, skip);
6519 __ movl(Rdst, -1);
6520 __ bind(skip);
6521 __ negl(Rdst);
6522 __ addl(Rdst, BitsPerInt - 1);
6523 %}
6524 ins_pipe(ialu_reg);
6525 %}
6526
6527 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6528 predicate(UseCountLeadingZerosInstruction);
6529 match(Set dst (CountLeadingZerosL src));
6530 effect(KILL cr);
6531
6532 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6533 ins_encode %{
6534 __ lzcntq($dst$$Register, $src$$Register);
6535 %}
6536 ins_pipe(ialu_reg);
6537 %}
6538
6539 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6540 predicate(!UseCountLeadingZerosInstruction);
6541 match(Set dst (CountLeadingZerosL src));
6542 effect(KILL cr);
6543
6544 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6545 "jnz skip\n\t"
6546 "movl $dst, -1\n"
6547 "skip:\n\t"
6548 "negl $dst\n\t"
6549 "addl $dst, 63" %}
6550 ins_encode %{
6551 Register Rdst = $dst$$Register;
6552 Register Rsrc = $src$$Register;
6553 Label skip;
6554 __ bsrq(Rdst, Rsrc);
6555 __ jccb(Assembler::notZero, skip);
6556 __ movl(Rdst, -1);
6557 __ bind(skip);
6558 __ negl(Rdst);
6559 __ addl(Rdst, BitsPerLong - 1);
6560 %}
6561 ins_pipe(ialu_reg);
6562 %}
6563
6564 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6565 predicate(UseCountTrailingZerosInstruction);
6566 match(Set dst (CountTrailingZerosI src));
6567 effect(KILL cr);
6568
6569 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6570 ins_encode %{
6571 __ tzcntl($dst$$Register, $src$$Register);
6572 %}
6573 ins_pipe(ialu_reg);
6574 %}
6575
6576 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6577 predicate(!UseCountTrailingZerosInstruction);
6578 match(Set dst (CountTrailingZerosI src));
6579 effect(KILL cr);
6580
6581 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6582 "jnz done\n\t"
6583 "movl $dst, 32\n"
6584 "done:" %}
6585 ins_encode %{
6586 Register Rdst = $dst$$Register;
6587 Label done;
6588 __ bsfl(Rdst, $src$$Register);
6589 __ jccb(Assembler::notZero, done);
6590 __ movl(Rdst, BitsPerInt);
6591 __ bind(done);
6592 %}
6593 ins_pipe(ialu_reg);
6594 %}
6595
6596 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6597 predicate(UseCountTrailingZerosInstruction);
6598 match(Set dst (CountTrailingZerosL src));
6599 effect(KILL cr);
6600
6601 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6602 ins_encode %{
6603 __ tzcntq($dst$$Register, $src$$Register);
6604 %}
6605 ins_pipe(ialu_reg);
6606 %}
6607
6608 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6609 predicate(!UseCountTrailingZerosInstruction);
6610 match(Set dst (CountTrailingZerosL src));
6611 effect(KILL cr);
6612
6613 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6614 "jnz done\n\t"
6615 "movl $dst, 64\n"
6616 "done:" %}
6617 ins_encode %{
6618 Register Rdst = $dst$$Register;
6619 Label done;
6620 __ bsfq(Rdst, $src$$Register);
6621 __ jccb(Assembler::notZero, done);
6622 __ movl(Rdst, BitsPerLong);
6623 __ bind(done);
6624 %}
6625 ins_pipe(ialu_reg);
6626 %}
6627
6628
6629 //---------- Population Count Instructions -------------------------------------
6630
6631 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6632 predicate(UsePopCountInstruction);
6633 match(Set dst (PopCountI src));
6634 effect(KILL cr);
6635
6636 format %{ "popcnt $dst, $src" %}
6637 ins_encode %{
6638 __ popcntl($dst$$Register, $src$$Register);
6639 %}
6640 ins_pipe(ialu_reg);
6641 %}
6642
6643 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6644 predicate(UsePopCountInstruction);
6645 match(Set dst (PopCountI (LoadI mem)));
6646 effect(KILL cr);
6647
6648 format %{ "popcnt $dst, $mem" %}
6649 ins_encode %{
6650 __ popcntl($dst$$Register, $mem$$Address);
6651 %}
6652 ins_pipe(ialu_reg);
6653 %}
6654
6655 // Note: Long.bitCount(long) returns an int.
6656 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6657 predicate(UsePopCountInstruction);
6658 match(Set dst (PopCountL src));
6659 effect(KILL cr);
6660
6661 format %{ "popcnt $dst, $src" %}
6662 ins_encode %{
6663 __ popcntq($dst$$Register, $src$$Register);
6664 %}
6665 ins_pipe(ialu_reg);
6666 %}
6667
6668 // Note: Long.bitCount(long) returns an int.
6669 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6670 predicate(UsePopCountInstruction);
6671 match(Set dst (PopCountL (LoadL mem)));
6672 effect(KILL cr);
6673
6674 format %{ "popcnt $dst, $mem" %}
6675 ins_encode %{
6676 __ popcntq($dst$$Register, $mem$$Address);
6677 %}
6678 ins_pipe(ialu_reg);
6679 %}
6680
6681
6682 //----------MemBar Instructions-----------------------------------------------
6683 // Memory barrier flavors
6684
6685 instruct membar_acquire()
6686 %{
6687 match(MemBarAcquire);
6688 match(LoadFence);
6689 ins_cost(0);
6690
6691 size(0);
6692 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6693 ins_encode();
6694 ins_pipe(empty);
6695 %}
6696
6697 instruct membar_acquire_lock()
6698 %{
6699 match(MemBarAcquireLock);
6700 ins_cost(0);
6701
6702 size(0);
6703 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6704 ins_encode();
6705 ins_pipe(empty);
6706 %}
6707
6708 instruct membar_release()
6709 %{
6710 match(MemBarRelease);
6711 match(StoreFence);
6712 ins_cost(0);
6713
6714 size(0);
6715 format %{ "MEMBAR-release ! (empty encoding)" %}
6716 ins_encode();
6717 ins_pipe(empty);
6718 %}
6719
6720 instruct membar_release_lock()
6721 %{
6722 match(MemBarReleaseLock);
6723 ins_cost(0);
6724
6725 size(0);
6726 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6727 ins_encode();
6728 ins_pipe(empty);
6729 %}
6730
6731 instruct membar_volatile(rFlagsReg cr) %{
6732 match(MemBarVolatile);
6733 effect(KILL cr);
6734 ins_cost(400);
6735
6736 format %{
6737 $$template
6738 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6739 %}
6740 ins_encode %{
6741 __ membar(Assembler::StoreLoad);
6742 %}
6743 ins_pipe(pipe_slow);
6744 %}
6745
6746 instruct unnecessary_membar_volatile()
6747 %{
6748 match(MemBarVolatile);
6749 predicate(Matcher::post_store_load_barrier(n));
6750 ins_cost(0);
6751
6752 size(0);
6753 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6754 ins_encode();
6755 ins_pipe(empty);
6756 %}
6757
6758 instruct membar_storestore() %{
6759 match(MemBarStoreStore);
6760 ins_cost(0);
6761
6762 size(0);
6763 format %{ "MEMBAR-storestore (empty encoding)" %}
6764 ins_encode( );
6765 ins_pipe(empty);
6766 %}
6767
6768 //----------Move Instructions--------------------------------------------------
6769
6770 instruct castX2P(rRegP dst, rRegL src)
6771 %{
6772 match(Set dst (CastX2P src));
6773
6774 format %{ "movq $dst, $src\t# long->ptr" %}
6775 ins_encode %{
6776 if ($dst$$reg != $src$$reg) {
6777 __ movptr($dst$$Register, $src$$Register);
6778 }
6779 %}
6780 ins_pipe(ialu_reg_reg); // XXX
6781 %}
6782
6783 instruct castP2X(rRegL dst, rRegP src)
6784 %{
6785 match(Set dst (CastP2X src));
6786
6787 format %{ "movq $dst, $src\t# ptr -> long" %}
6788 ins_encode %{
6789 if ($dst$$reg != $src$$reg) {
6790 __ movptr($dst$$Register, $src$$Register);
6791 }
6792 %}
6793 ins_pipe(ialu_reg_reg); // XXX
6794 %}
6795
6796 // Convert oop into int for vectors alignment masking
6797 instruct convP2I(rRegI dst, rRegP src)
6798 %{
6799 match(Set dst (ConvL2I (CastP2X src)));
6800
6801 format %{ "movl $dst, $src\t# ptr -> int" %}
6802 ins_encode %{
6803 __ movl($dst$$Register, $src$$Register);
6804 %}
6805 ins_pipe(ialu_reg_reg); // XXX
6806 %}
6807
6808 // Convert compressed oop into int for vectors alignment masking
6809 // in case of 32bit oops (heap < 4Gb).
6810 instruct convN2I(rRegI dst, rRegN src)
6811 %{
6812 predicate(Universe::narrow_oop_shift() == 0);
6813 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6814
6815 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6816 ins_encode %{
6817 __ movl($dst$$Register, $src$$Register);
6818 %}
6819 ins_pipe(ialu_reg_reg); // XXX
6820 %}
6821
6822 // Convert oop pointer into compressed form
6823 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6824 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6825 match(Set dst (EncodeP src));
6826 effect(KILL cr);
6827 format %{ "encode_heap_oop $dst,$src" %}
6828 ins_encode %{
6829 Register s = $src$$Register;
6830 Register d = $dst$$Register;
6831 if (s != d) {
6832 __ movq(d, s);
6833 }
6834 __ encode_heap_oop(d);
6835 %}
6836 ins_pipe(ialu_reg_long);
6837 %}
6838
6839 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6840 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6841 match(Set dst (EncodeP src));
6842 effect(KILL cr);
6843 format %{ "encode_heap_oop_not_null $dst,$src" %}
6844 ins_encode %{
6845 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6846 %}
6847 ins_pipe(ialu_reg_long);
6848 %}
6849
6850 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6851 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6852 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6853 match(Set dst (DecodeN src));
6854 effect(KILL cr);
6855 format %{ "decode_heap_oop $dst,$src" %}
6856 ins_encode %{
6857 Register s = $src$$Register;
6858 Register d = $dst$$Register;
6859 if (s != d) {
6860 __ movq(d, s);
6861 }
6862 __ decode_heap_oop(d);
6863 %}
6864 ins_pipe(ialu_reg_long);
6865 %}
6866
6867 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6868 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6869 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6870 match(Set dst (DecodeN src));
6871 effect(KILL cr);
6872 format %{ "decode_heap_oop_not_null $dst,$src" %}
6873 ins_encode %{
6874 Register s = $src$$Register;
6875 Register d = $dst$$Register;
6876 if (s != d) {
6877 __ decode_heap_oop_not_null(d, s);
6878 } else {
6879 __ decode_heap_oop_not_null(d);
6880 }
6881 %}
6882 ins_pipe(ialu_reg_long);
6883 %}
6884
6885 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6886 match(Set dst (EncodePKlass src));
6887 effect(KILL cr);
6888 format %{ "encode_klass_not_null $dst,$src" %}
6889 ins_encode %{
6890 __ encode_klass_not_null($dst$$Register, $src$$Register);
6891 %}
6892 ins_pipe(ialu_reg_long);
6893 %}
6894
6895 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6896 match(Set dst (DecodeNKlass src));
6897 effect(KILL cr);
6898 format %{ "decode_klass_not_null $dst,$src" %}
6899 ins_encode %{
6900 Register s = $src$$Register;
6901 Register d = $dst$$Register;
6902 if (s != d) {
6903 __ decode_klass_not_null(d, s);
6904 } else {
6905 __ decode_klass_not_null(d);
6906 }
6907 %}
6908 ins_pipe(ialu_reg_long);
6909 %}
6910
6911
6912 //----------Conditional Move---------------------------------------------------
6913 // Jump
6914 // dummy instruction for generating temp registers
6915 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6916 match(Jump (LShiftL switch_val shift));
6917 ins_cost(350);
6918 predicate(false);
6919 effect(TEMP dest);
6920
6921 format %{ "leaq $dest, [$constantaddress]\n\t"
6922 "jmp [$dest + $switch_val << $shift]\n\t" %}
6923 ins_encode %{
6924 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6925 // to do that and the compiler is using that register as one it can allocate.
6926 // So we build it all by hand.
6927 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6928 // ArrayAddress dispatch(table, index);
6929 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6930 __ lea($dest$$Register, $constantaddress);
6931 __ jmp(dispatch);
6932 %}
6933 ins_pipe(pipe_jmp);
6934 %}
6935
6936 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6937 match(Jump (AddL (LShiftL switch_val shift) offset));
6938 ins_cost(350);
6939 effect(TEMP dest);
6940
6941 format %{ "leaq $dest, [$constantaddress]\n\t"
6942 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6943 ins_encode %{
6944 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6945 // to do that and the compiler is using that register as one it can allocate.
6946 // So we build it all by hand.
6947 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6948 // ArrayAddress dispatch(table, index);
6949 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6950 __ lea($dest$$Register, $constantaddress);
6951 __ jmp(dispatch);
6952 %}
6953 ins_pipe(pipe_jmp);
6954 %}
6955
6956 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6957 match(Jump switch_val);
6958 ins_cost(350);
6959 effect(TEMP dest);
6960
6961 format %{ "leaq $dest, [$constantaddress]\n\t"
6962 "jmp [$dest + $switch_val]\n\t" %}
6963 ins_encode %{
6964 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6965 // to do that and the compiler is using that register as one it can allocate.
6966 // So we build it all by hand.
6967 // Address index(noreg, switch_reg, Address::times_1);
6968 // ArrayAddress dispatch(table, index);
6969 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6970 __ lea($dest$$Register, $constantaddress);
6971 __ jmp(dispatch);
6972 %}
6973 ins_pipe(pipe_jmp);
6974 %}
6975
6976 // Conditional move
6977 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6978 %{
6979 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6980
6981 ins_cost(200); // XXX
6982 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6983 opcode(0x0F, 0x40);
6984 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6985 ins_pipe(pipe_cmov_reg);
6986 %}
6987
6988 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6989 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6990
6991 ins_cost(200); // XXX
6992 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6993 opcode(0x0F, 0x40);
6994 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6995 ins_pipe(pipe_cmov_reg);
6996 %}
6997
6998 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6999 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7000 ins_cost(200);
7001 expand %{
7002 cmovI_regU(cop, cr, dst, src);
7003 %}
7004 %}
7005
7006 // Conditional move
7007 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
7008 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7009
7010 ins_cost(250); // XXX
7011 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7012 opcode(0x0F, 0x40);
7013 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7014 ins_pipe(pipe_cmov_mem);
7015 %}
7016
7017 // Conditional move
7018 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
7019 %{
7020 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7021
7022 ins_cost(250); // XXX
7023 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7024 opcode(0x0F, 0x40);
7025 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7026 ins_pipe(pipe_cmov_mem);
7027 %}
7028
7029 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
7030 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7031 ins_cost(250);
7032 expand %{
7033 cmovI_memU(cop, cr, dst, src);
7034 %}
7035 %}
7036
7037 // Conditional move
7038 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
7039 %{
7040 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7041
7042 ins_cost(200); // XXX
7043 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
7044 opcode(0x0F, 0x40);
7045 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7046 ins_pipe(pipe_cmov_reg);
7047 %}
7048
7049 // Conditional move
7050 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
7051 %{
7052 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7053
7054 ins_cost(200); // XXX
7055 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7056 opcode(0x0F, 0x40);
7057 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7058 ins_pipe(pipe_cmov_reg);
7059 %}
7060
7061 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
7062 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7063 ins_cost(200);
7064 expand %{
7065 cmovN_regU(cop, cr, dst, src);
7066 %}
7067 %}
7068
7069 // Conditional move
7070 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7071 %{
7072 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7073
7074 ins_cost(200); // XXX
7075 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7076 opcode(0x0F, 0x40);
7077 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7078 ins_pipe(pipe_cmov_reg); // XXX
7079 %}
7080
7081 // Conditional move
7082 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7083 %{
7084 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7085
7086 ins_cost(200); // XXX
7087 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7088 opcode(0x0F, 0x40);
7089 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7090 ins_pipe(pipe_cmov_reg); // XXX
7091 %}
7092
7093 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7094 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7095 ins_cost(200);
7096 expand %{
7097 cmovP_regU(cop, cr, dst, src);
7098 %}
7099 %}
7100
7101 // DISABLED: Requires the ADLC to emit a bottom_type call that
7102 // correctly meets the two pointer arguments; one is an incoming
7103 // register but the other is a memory operand. ALSO appears to
7104 // be buggy with implicit null checks.
7105 //
7106 //// Conditional move
7107 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7108 //%{
7109 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7110 // ins_cost(250);
7111 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7112 // opcode(0x0F,0x40);
7113 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7114 // ins_pipe( pipe_cmov_mem );
7115 //%}
7116 //
7117 //// Conditional move
7118 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7119 //%{
7120 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7121 // ins_cost(250);
7122 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7123 // opcode(0x0F,0x40);
7124 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7125 // ins_pipe( pipe_cmov_mem );
7126 //%}
7127
7128 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7129 %{
7130 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7131
7132 ins_cost(200); // XXX
7133 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7134 opcode(0x0F, 0x40);
7135 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7136 ins_pipe(pipe_cmov_reg); // XXX
7137 %}
7138
7139 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7140 %{
7141 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7142
7143 ins_cost(200); // XXX
7144 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7145 opcode(0x0F, 0x40);
7146 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7147 ins_pipe(pipe_cmov_mem); // XXX
7148 %}
7149
7150 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7151 %{
7152 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7153
7154 ins_cost(200); // XXX
7155 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7156 opcode(0x0F, 0x40);
7157 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7158 ins_pipe(pipe_cmov_reg); // XXX
7159 %}
7160
7161 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7162 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7163 ins_cost(200);
7164 expand %{
7165 cmovL_regU(cop, cr, dst, src);
7166 %}
7167 %}
7168
7169 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7170 %{
7171 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7172
7173 ins_cost(200); // XXX
7174 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7175 opcode(0x0F, 0x40);
7176 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7177 ins_pipe(pipe_cmov_mem); // XXX
7178 %}
7179
7180 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7181 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7182 ins_cost(200);
7183 expand %{
7184 cmovL_memU(cop, cr, dst, src);
7185 %}
7186 %}
7187
7188 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7189 %{
7190 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7191
7192 ins_cost(200); // XXX
7193 format %{ "jn$cop skip\t# signed cmove float\n\t"
7194 "movss $dst, $src\n"
7195 "skip:" %}
7196 ins_encode %{
7197 Label Lskip;
7198 // Invert sense of branch from sense of CMOV
7199 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7200 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7201 __ bind(Lskip);
7202 %}
7203 ins_pipe(pipe_slow);
7204 %}
7205
7206 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7207 // %{
7208 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7209
7210 // ins_cost(200); // XXX
7211 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7212 // "movss $dst, $src\n"
7213 // "skip:" %}
7214 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7215 // ins_pipe(pipe_slow);
7216 // %}
7217
7218 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7219 %{
7220 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7221
7222 ins_cost(200); // XXX
7223 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7224 "movss $dst, $src\n"
7225 "skip:" %}
7226 ins_encode %{
7227 Label Lskip;
7228 // Invert sense of branch from sense of CMOV
7229 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7230 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7231 __ bind(Lskip);
7232 %}
7233 ins_pipe(pipe_slow);
7234 %}
7235
7236 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7237 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7238 ins_cost(200);
7239 expand %{
7240 cmovF_regU(cop, cr, dst, src);
7241 %}
7242 %}
7243
7244 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7245 %{
7246 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7247
7248 ins_cost(200); // XXX
7249 format %{ "jn$cop skip\t# signed cmove double\n\t"
7250 "movsd $dst, $src\n"
7251 "skip:" %}
7252 ins_encode %{
7253 Label Lskip;
7254 // Invert sense of branch from sense of CMOV
7255 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7256 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7257 __ bind(Lskip);
7258 %}
7259 ins_pipe(pipe_slow);
7260 %}
7261
7262 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7263 %{
7264 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7265
7266 ins_cost(200); // XXX
7267 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7268 "movsd $dst, $src\n"
7269 "skip:" %}
7270 ins_encode %{
7271 Label Lskip;
7272 // Invert sense of branch from sense of CMOV
7273 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7274 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7275 __ bind(Lskip);
7276 %}
7277 ins_pipe(pipe_slow);
7278 %}
7279
7280 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7281 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7282 ins_cost(200);
7283 expand %{
7284 cmovD_regU(cop, cr, dst, src);
7285 %}
7286 %}
7287
7288 //----------Arithmetic Instructions--------------------------------------------
7289 //----------Addition Instructions----------------------------------------------
7290
7291 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7292 %{
7293 match(Set dst (AddI dst src));
7294 effect(KILL cr);
7295
7296 format %{ "addl $dst, $src\t# int" %}
7297 opcode(0x03);
7298 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7299 ins_pipe(ialu_reg_reg);
7300 %}
7301
7302 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7303 %{
7304 match(Set dst (AddI dst src));
7305 effect(KILL cr);
7306
7307 format %{ "addl $dst, $src\t# int" %}
7308 opcode(0x81, 0x00); /* /0 id */
7309 ins_encode(OpcSErm(dst, src), Con8or32(src));
7310 ins_pipe( ialu_reg );
7311 %}
7312
7313 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7314 %{
7315 match(Set dst (AddI dst (LoadI src)));
7316 effect(KILL cr);
7317
7318 ins_cost(125); // XXX
7319 format %{ "addl $dst, $src\t# int" %}
7320 opcode(0x03);
7321 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7322 ins_pipe(ialu_reg_mem);
7323 %}
7324
7325 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7326 %{
7327 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7328 effect(KILL cr);
7329
7330 ins_cost(150); // XXX
7331 format %{ "addl $dst, $src\t# int" %}
7332 opcode(0x01); /* Opcode 01 /r */
7333 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7334 ins_pipe(ialu_mem_reg);
7335 %}
7336
7337 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7338 %{
7339 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7340 effect(KILL cr);
7341
7342 ins_cost(125); // XXX
7343 format %{ "addl $dst, $src\t# int" %}
7344 opcode(0x81); /* Opcode 81 /0 id */
7345 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7346 ins_pipe(ialu_mem_imm);
7347 %}
7348
7349 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7350 %{
7351 predicate(UseIncDec);
7352 match(Set dst (AddI dst src));
7353 effect(KILL cr);
7354
7355 format %{ "incl $dst\t# int" %}
7356 opcode(0xFF, 0x00); // FF /0
7357 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7358 ins_pipe(ialu_reg);
7359 %}
7360
7361 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7362 %{
7363 predicate(UseIncDec);
7364 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7365 effect(KILL cr);
7366
7367 ins_cost(125); // XXX
7368 format %{ "incl $dst\t# int" %}
7369 opcode(0xFF); /* Opcode FF /0 */
7370 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7371 ins_pipe(ialu_mem_imm);
7372 %}
7373
7374 // XXX why does that use AddI
7375 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7376 %{
7377 predicate(UseIncDec);
7378 match(Set dst (AddI dst src));
7379 effect(KILL cr);
7380
7381 format %{ "decl $dst\t# int" %}
7382 opcode(0xFF, 0x01); // FF /1
7383 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7384 ins_pipe(ialu_reg);
7385 %}
7386
7387 // XXX why does that use AddI
7388 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7389 %{
7390 predicate(UseIncDec);
7391 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7392 effect(KILL cr);
7393
7394 ins_cost(125); // XXX
7395 format %{ "decl $dst\t# int" %}
7396 opcode(0xFF); /* Opcode FF /1 */
7397 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7398 ins_pipe(ialu_mem_imm);
7399 %}
7400
7401 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7402 %{
7403 match(Set dst (AddI src0 src1));
7404
7405 ins_cost(110);
7406 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7407 opcode(0x8D); /* 0x8D /r */
7408 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7409 ins_pipe(ialu_reg_reg);
7410 %}
7411
7412 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7413 %{
7414 match(Set dst (AddL dst src));
7415 effect(KILL cr);
7416
7417 format %{ "addq $dst, $src\t# long" %}
7418 opcode(0x03);
7419 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7420 ins_pipe(ialu_reg_reg);
7421 %}
7422
7423 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7424 %{
7425 match(Set dst (AddL dst src));
7426 effect(KILL cr);
7427
7428 format %{ "addq $dst, $src\t# long" %}
7429 opcode(0x81, 0x00); /* /0 id */
7430 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7431 ins_pipe( ialu_reg );
7432 %}
7433
7434 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7435 %{
7436 match(Set dst (AddL dst (LoadL src)));
7437 effect(KILL cr);
7438
7439 ins_cost(125); // XXX
7440 format %{ "addq $dst, $src\t# long" %}
7441 opcode(0x03);
7442 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7443 ins_pipe(ialu_reg_mem);
7444 %}
7445
7446 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7447 %{
7448 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7449 effect(KILL cr);
7450
7451 ins_cost(150); // XXX
7452 format %{ "addq $dst, $src\t# long" %}
7453 opcode(0x01); /* Opcode 01 /r */
7454 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7455 ins_pipe(ialu_mem_reg);
7456 %}
7457
7458 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7459 %{
7460 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7461 effect(KILL cr);
7462
7463 ins_cost(125); // XXX
7464 format %{ "addq $dst, $src\t# long" %}
7465 opcode(0x81); /* Opcode 81 /0 id */
7466 ins_encode(REX_mem_wide(dst),
7467 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7468 ins_pipe(ialu_mem_imm);
7469 %}
7470
7471 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7472 %{
7473 predicate(UseIncDec);
7474 match(Set dst (AddL dst src));
7475 effect(KILL cr);
7476
7477 format %{ "incq $dst\t# long" %}
7478 opcode(0xFF, 0x00); // FF /0
7479 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7480 ins_pipe(ialu_reg);
7481 %}
7482
7483 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7484 %{
7485 predicate(UseIncDec);
7486 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7487 effect(KILL cr);
7488
7489 ins_cost(125); // XXX
7490 format %{ "incq $dst\t# long" %}
7491 opcode(0xFF); /* Opcode FF /0 */
7492 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7493 ins_pipe(ialu_mem_imm);
7494 %}
7495
7496 // XXX why does that use AddL
7497 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7498 %{
7499 predicate(UseIncDec);
7500 match(Set dst (AddL dst src));
7501 effect(KILL cr);
7502
7503 format %{ "decq $dst\t# long" %}
7504 opcode(0xFF, 0x01); // FF /1
7505 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7506 ins_pipe(ialu_reg);
7507 %}
7508
7509 // XXX why does that use AddL
7510 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7511 %{
7512 predicate(UseIncDec);
7513 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7514 effect(KILL cr);
7515
7516 ins_cost(125); // XXX
7517 format %{ "decq $dst\t# long" %}
7518 opcode(0xFF); /* Opcode FF /1 */
7519 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7520 ins_pipe(ialu_mem_imm);
7521 %}
7522
7523 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7524 %{
7525 match(Set dst (AddL src0 src1));
7526
7527 ins_cost(110);
7528 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7529 opcode(0x8D); /* 0x8D /r */
7530 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7531 ins_pipe(ialu_reg_reg);
7532 %}
7533
7534 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7535 %{
7536 match(Set dst (AddP dst src));
7537 effect(KILL cr);
7538
7539 format %{ "addq $dst, $src\t# ptr" %}
7540 opcode(0x03);
7541 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7542 ins_pipe(ialu_reg_reg);
7543 %}
7544
7545 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7546 %{
7547 match(Set dst (AddP dst src));
7548 effect(KILL cr);
7549
7550 format %{ "addq $dst, $src\t# ptr" %}
7551 opcode(0x81, 0x00); /* /0 id */
7552 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7553 ins_pipe( ialu_reg );
7554 %}
7555
7556 // XXX addP mem ops ????
7557
7558 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7559 %{
7560 match(Set dst (AddP src0 src1));
7561
7562 ins_cost(110);
7563 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7564 opcode(0x8D); /* 0x8D /r */
7565 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7566 ins_pipe(ialu_reg_reg);
7567 %}
7568
7569 instruct checkCastPP(rRegP dst)
7570 %{
7571 match(Set dst (CheckCastPP dst));
7572
7573 size(0);
7574 format %{ "# checkcastPP of $dst" %}
7575 ins_encode(/* empty encoding */);
7576 ins_pipe(empty);
7577 %}
7578
7579 instruct castPP(rRegP dst)
7580 %{
7581 match(Set dst (CastPP dst));
7582
7583 size(0);
7584 format %{ "# castPP of $dst" %}
7585 ins_encode(/* empty encoding */);
7586 ins_pipe(empty);
7587 %}
7588
7589 instruct castII(rRegI dst)
7590 %{
7591 match(Set dst (CastII dst));
7592
7593 size(0);
7594 format %{ "# castII of $dst" %}
7595 ins_encode(/* empty encoding */);
7596 ins_cost(0);
7597 ins_pipe(empty);
7598 %}
7599
7600 // LoadP-locked same as a regular LoadP when used with compare-swap
7601 instruct loadPLocked(rRegP dst, memory mem)
7602 %{
7603 match(Set dst (LoadPLocked mem));
7604
7605 ins_cost(125); // XXX
7606 format %{ "movq $dst, $mem\t# ptr locked" %}
7607 opcode(0x8B);
7608 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7609 ins_pipe(ialu_reg_mem); // XXX
7610 %}
7611
7612 // Conditional-store of the updated heap-top.
7613 // Used during allocation of the shared heap.
7614 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7615
7616 instruct storePConditional(memory heap_top_ptr,
7617 rax_RegP oldval, rRegP newval,
7618 rFlagsReg cr)
7619 %{
7620 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7621
7622 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7623 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7624 opcode(0x0F, 0xB1);
7625 ins_encode(lock_prefix,
7626 REX_reg_mem_wide(newval, heap_top_ptr),
7627 OpcP, OpcS,
7628 reg_mem(newval, heap_top_ptr));
7629 ins_pipe(pipe_cmpxchg);
7630 %}
7631
7632 // Conditional-store of an int value.
7633 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7634 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7635 %{
7636 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7637 effect(KILL oldval);
7638
7639 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7640 opcode(0x0F, 0xB1);
7641 ins_encode(lock_prefix,
7642 REX_reg_mem(newval, mem),
7643 OpcP, OpcS,
7644 reg_mem(newval, mem));
7645 ins_pipe(pipe_cmpxchg);
7646 %}
7647
7648 // Conditional-store of a long value.
7649 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7650 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7651 %{
7652 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7653 effect(KILL oldval);
7654
7655 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7656 opcode(0x0F, 0xB1);
7657 ins_encode(lock_prefix,
7658 REX_reg_mem_wide(newval, mem),
7659 OpcP, OpcS,
7660 reg_mem(newval, mem));
7661 ins_pipe(pipe_cmpxchg);
7662 %}
7663
7664
7665 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7666 instruct compareAndSwapP(rRegI res,
7667 memory mem_ptr,
7668 rax_RegP oldval, rRegP newval,
7669 rFlagsReg cr)
7670 %{
7671 predicate(VM_Version::supports_cx8());
7672 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7673 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7674 effect(KILL cr, KILL oldval);
7675
7676 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7677 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7678 "sete $res\n\t"
7679 "movzbl $res, $res" %}
7680 opcode(0x0F, 0xB1);
7681 ins_encode(lock_prefix,
7682 REX_reg_mem_wide(newval, mem_ptr),
7683 OpcP, OpcS,
7684 reg_mem(newval, mem_ptr),
7685 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7686 REX_reg_breg(res, res), // movzbl
7687 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7688 ins_pipe( pipe_cmpxchg );
7689 %}
7690
7691 instruct compareAndSwapL(rRegI res,
7692 memory mem_ptr,
7693 rax_RegL oldval, rRegL newval,
7694 rFlagsReg cr)
7695 %{
7696 predicate(VM_Version::supports_cx8());
7697 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7698 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7699 effect(KILL cr, KILL oldval);
7700
7701 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7702 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7703 "sete $res\n\t"
7704 "movzbl $res, $res" %}
7705 opcode(0x0F, 0xB1);
7706 ins_encode(lock_prefix,
7707 REX_reg_mem_wide(newval, mem_ptr),
7708 OpcP, OpcS,
7709 reg_mem(newval, mem_ptr),
7710 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7711 REX_reg_breg(res, res), // movzbl
7712 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7713 ins_pipe( pipe_cmpxchg );
7714 %}
7715
7716 instruct compareAndSwapI(rRegI res,
7717 memory mem_ptr,
7718 rax_RegI oldval, rRegI newval,
7719 rFlagsReg cr)
7720 %{
7721 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7722 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7723 effect(KILL cr, KILL oldval);
7724
7725 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7726 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7727 "sete $res\n\t"
7728 "movzbl $res, $res" %}
7729 opcode(0x0F, 0xB1);
7730 ins_encode(lock_prefix,
7731 REX_reg_mem(newval, mem_ptr),
7732 OpcP, OpcS,
7733 reg_mem(newval, mem_ptr),
7734 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7735 REX_reg_breg(res, res), // movzbl
7736 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7737 ins_pipe( pipe_cmpxchg );
7738 %}
7739
7740 instruct compareAndSwapB(rRegI res,
7741 memory mem_ptr,
7742 rax_RegI oldval, rRegI newval,
7743 rFlagsReg cr)
7744 %{
7745 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7746 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7747 effect(KILL cr, KILL oldval);
7748
7749 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7750 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7751 "sete $res\n\t"
7752 "movzbl $res, $res" %}
7753 opcode(0x0F, 0xB0);
7754 ins_encode(lock_prefix,
7755 REX_breg_mem(newval, mem_ptr),
7756 OpcP, OpcS,
7757 reg_mem(newval, mem_ptr),
7758 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7759 REX_reg_breg(res, res), // movzbl
7760 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7761 ins_pipe( pipe_cmpxchg );
7762 %}
7763
7764 instruct compareAndSwapS(rRegI res,
7765 memory mem_ptr,
7766 rax_RegI oldval, rRegI newval,
7767 rFlagsReg cr)
7768 %{
7769 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7770 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7771 effect(KILL cr, KILL oldval);
7772
7773 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7774 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7775 "sete $res\n\t"
7776 "movzbl $res, $res" %}
7777 opcode(0x0F, 0xB1);
7778 ins_encode(lock_prefix,
7779 SizePrefix,
7780 REX_reg_mem(newval, mem_ptr),
7781 OpcP, OpcS,
7782 reg_mem(newval, mem_ptr),
7783 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7784 REX_reg_breg(res, res), // movzbl
7785 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7786 ins_pipe( pipe_cmpxchg );
7787 %}
7788
7789 instruct compareAndSwapN(rRegI res,
7790 memory mem_ptr,
7791 rax_RegN oldval, rRegN newval,
7792 rFlagsReg cr) %{
7793 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7794 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7795 effect(KILL cr, KILL oldval);
7796
7797 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7798 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7799 "sete $res\n\t"
7800 "movzbl $res, $res" %}
7801 opcode(0x0F, 0xB1);
7802 ins_encode(lock_prefix,
7803 REX_reg_mem(newval, mem_ptr),
7804 OpcP, OpcS,
7805 reg_mem(newval, mem_ptr),
7806 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7807 REX_reg_breg(res, res), // movzbl
7808 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7809 ins_pipe( pipe_cmpxchg );
7810 %}
7811
7812 instruct compareAndExchangeB(
7813 memory mem_ptr,
7814 rax_RegI oldval, rRegI newval,
7815 rFlagsReg cr)
7816 %{
7817 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7818 effect(KILL cr);
7819
7820 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7821 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7822 opcode(0x0F, 0xB0);
7823 ins_encode(lock_prefix,
7824 REX_breg_mem(newval, mem_ptr),
7825 OpcP, OpcS,
7826 reg_mem(newval, mem_ptr) // lock cmpxchg
7827 );
7828 ins_pipe( pipe_cmpxchg );
7829 %}
7830
7831 instruct compareAndExchangeS(
7832 memory mem_ptr,
7833 rax_RegI oldval, rRegI newval,
7834 rFlagsReg cr)
7835 %{
7836 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7837 effect(KILL cr);
7838
7839 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7840 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7841 opcode(0x0F, 0xB1);
7842 ins_encode(lock_prefix,
7843 SizePrefix,
7844 REX_reg_mem(newval, mem_ptr),
7845 OpcP, OpcS,
7846 reg_mem(newval, mem_ptr) // lock cmpxchg
7847 );
7848 ins_pipe( pipe_cmpxchg );
7849 %}
7850
7851 instruct compareAndExchangeI(
7852 memory mem_ptr,
7853 rax_RegI oldval, rRegI newval,
7854 rFlagsReg cr)
7855 %{
7856 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7857 effect(KILL cr);
7858
7859 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7860 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7861 opcode(0x0F, 0xB1);
7862 ins_encode(lock_prefix,
7863 REX_reg_mem(newval, mem_ptr),
7864 OpcP, OpcS,
7865 reg_mem(newval, mem_ptr) // lock cmpxchg
7866 );
7867 ins_pipe( pipe_cmpxchg );
7868 %}
7869
7870 instruct compareAndExchangeL(
7871 memory mem_ptr,
7872 rax_RegL oldval, rRegL newval,
7873 rFlagsReg cr)
7874 %{
7875 predicate(VM_Version::supports_cx8());
7876 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7877 effect(KILL cr);
7878
7879 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7880 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7881 opcode(0x0F, 0xB1);
7882 ins_encode(lock_prefix,
7883 REX_reg_mem_wide(newval, mem_ptr),
7884 OpcP, OpcS,
7885 reg_mem(newval, mem_ptr) // lock cmpxchg
7886 );
7887 ins_pipe( pipe_cmpxchg );
7888 %}
7889
7890 instruct compareAndExchangeN(
7891 memory mem_ptr,
7892 rax_RegN oldval, rRegN newval,
7893 rFlagsReg cr) %{
7894 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7895 effect(KILL cr);
7896
7897 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7898 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7899 opcode(0x0F, 0xB1);
7900 ins_encode(lock_prefix,
7901 REX_reg_mem(newval, mem_ptr),
7902 OpcP, OpcS,
7903 reg_mem(newval, mem_ptr) // lock cmpxchg
7904 );
7905 ins_pipe( pipe_cmpxchg );
7906 %}
7907
7908 instruct compareAndExchangeP(
7909 memory mem_ptr,
7910 rax_RegP oldval, rRegP newval,
7911 rFlagsReg cr)
7912 %{
7913 predicate(VM_Version::supports_cx8());
7914 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7915 effect(KILL cr);
7916
7917 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7918 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7919 opcode(0x0F, 0xB1);
7920 ins_encode(lock_prefix,
7921 REX_reg_mem_wide(newval, mem_ptr),
7922 OpcP, OpcS,
7923 reg_mem(newval, mem_ptr) // lock cmpxchg
7924 );
7925 ins_pipe( pipe_cmpxchg );
7926 %}
7927
7928 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7929 predicate(n->as_LoadStore()->result_not_used());
7930 match(Set dummy (GetAndAddB mem add));
7931 effect(KILL cr);
7932 format %{ "ADDB [$mem],$add" %}
7933 ins_encode %{
7934 __ lock();
7935 __ addb($mem$$Address, $add$$constant);
7936 %}
7937 ins_pipe( pipe_cmpxchg );
7938 %}
7939
7940 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7941 match(Set newval (GetAndAddB mem newval));
7942 effect(KILL cr);
7943 format %{ "XADDB [$mem],$newval" %}
7944 ins_encode %{
7945 __ lock();
7946 __ xaddb($mem$$Address, $newval$$Register);
7947 %}
7948 ins_pipe( pipe_cmpxchg );
7949 %}
7950
7951 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7952 predicate(n->as_LoadStore()->result_not_used());
7953 match(Set dummy (GetAndAddS mem add));
7954 effect(KILL cr);
7955 format %{ "ADDW [$mem],$add" %}
7956 ins_encode %{
7957 __ lock();
7958 __ addw($mem$$Address, $add$$constant);
7959 %}
7960 ins_pipe( pipe_cmpxchg );
7961 %}
7962
7963 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
7964 match(Set newval (GetAndAddS mem newval));
7965 effect(KILL cr);
7966 format %{ "XADDW [$mem],$newval" %}
7967 ins_encode %{
7968 __ lock();
7969 __ xaddw($mem$$Address, $newval$$Register);
7970 %}
7971 ins_pipe( pipe_cmpxchg );
7972 %}
7973
7974 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7975 predicate(n->as_LoadStore()->result_not_used());
7976 match(Set dummy (GetAndAddI mem add));
7977 effect(KILL cr);
7978 format %{ "ADDL [$mem],$add" %}
7979 ins_encode %{
7980 __ lock();
7981 __ addl($mem$$Address, $add$$constant);
7982 %}
7983 ins_pipe( pipe_cmpxchg );
7984 %}
7985
7986 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7987 match(Set newval (GetAndAddI mem newval));
7988 effect(KILL cr);
7989 format %{ "XADDL [$mem],$newval" %}
7990 ins_encode %{
7991 __ lock();
7992 __ xaddl($mem$$Address, $newval$$Register);
7993 %}
7994 ins_pipe( pipe_cmpxchg );
7995 %}
7996
7997 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7998 predicate(n->as_LoadStore()->result_not_used());
7999 match(Set dummy (GetAndAddL mem add));
8000 effect(KILL cr);
8001 format %{ "ADDQ [$mem],$add" %}
8002 ins_encode %{
8003 __ lock();
8004 __ addq($mem$$Address, $add$$constant);
8005 %}
8006 ins_pipe( pipe_cmpxchg );
8007 %}
8008
8009 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
8010 match(Set newval (GetAndAddL mem newval));
8011 effect(KILL cr);
8012 format %{ "XADDQ [$mem],$newval" %}
8013 ins_encode %{
8014 __ lock();
8015 __ xaddq($mem$$Address, $newval$$Register);
8016 %}
8017 ins_pipe( pipe_cmpxchg );
8018 %}
8019
8020 instruct xchgB( memory mem, rRegI newval) %{
8021 match(Set newval (GetAndSetB mem newval));
8022 format %{ "XCHGB $newval,[$mem]" %}
8023 ins_encode %{
8024 __ xchgb($newval$$Register, $mem$$Address);
8025 %}
8026 ins_pipe( pipe_cmpxchg );
8027 %}
8028
8029 instruct xchgS( memory mem, rRegI newval) %{
8030 match(Set newval (GetAndSetS mem newval));
8031 format %{ "XCHGW $newval,[$mem]" %}
8032 ins_encode %{
8033 __ xchgw($newval$$Register, $mem$$Address);
8034 %}
8035 ins_pipe( pipe_cmpxchg );
8036 %}
8037
8038 instruct xchgI( memory mem, rRegI newval) %{
8039 match(Set newval (GetAndSetI mem newval));
8040 format %{ "XCHGL $newval,[$mem]" %}
8041 ins_encode %{
8042 __ xchgl($newval$$Register, $mem$$Address);
8043 %}
8044 ins_pipe( pipe_cmpxchg );
8045 %}
8046
8047 instruct xchgL( memory mem, rRegL newval) %{
8048 match(Set newval (GetAndSetL mem newval));
8049 format %{ "XCHGL $newval,[$mem]" %}
8050 ins_encode %{
8051 __ xchgq($newval$$Register, $mem$$Address);
8052 %}
8053 ins_pipe( pipe_cmpxchg );
8054 %}
8055
8056 instruct xchgP( memory mem, rRegP newval) %{
8057 match(Set newval (GetAndSetP mem newval));
8058 format %{ "XCHGQ $newval,[$mem]" %}
8059 ins_encode %{
8060 __ xchgq($newval$$Register, $mem$$Address);
8061 %}
8062 ins_pipe( pipe_cmpxchg );
8063 %}
8064
8065 instruct xchgN( memory mem, rRegN newval) %{
8066 match(Set newval (GetAndSetN mem newval));
8067 format %{ "XCHGL $newval,$mem]" %}
8068 ins_encode %{
8069 __ xchgl($newval$$Register, $mem$$Address);
8070 %}
8071 ins_pipe( pipe_cmpxchg );
8072 %}
8073
8074 //----------Subtraction Instructions-------------------------------------------
8075
8076 // Integer Subtraction Instructions
8077 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8078 %{
8079 match(Set dst (SubI dst src));
8080 effect(KILL cr);
8081
8082 format %{ "subl $dst, $src\t# int" %}
8083 opcode(0x2B);
8084 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8085 ins_pipe(ialu_reg_reg);
8086 %}
8087
8088 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8089 %{
8090 match(Set dst (SubI dst src));
8091 effect(KILL cr);
8092
8093 format %{ "subl $dst, $src\t# int" %}
8094 opcode(0x81, 0x05); /* Opcode 81 /5 */
8095 ins_encode(OpcSErm(dst, src), Con8or32(src));
8096 ins_pipe(ialu_reg);
8097 %}
8098
8099 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8100 %{
8101 match(Set dst (SubI dst (LoadI src)));
8102 effect(KILL cr);
8103
8104 ins_cost(125);
8105 format %{ "subl $dst, $src\t# int" %}
8106 opcode(0x2B);
8107 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8108 ins_pipe(ialu_reg_mem);
8109 %}
8110
8111 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8112 %{
8113 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8114 effect(KILL cr);
8115
8116 ins_cost(150);
8117 format %{ "subl $dst, $src\t# int" %}
8118 opcode(0x29); /* Opcode 29 /r */
8119 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8120 ins_pipe(ialu_mem_reg);
8121 %}
8122
8123 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8124 %{
8125 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8126 effect(KILL cr);
8127
8128 ins_cost(125); // XXX
8129 format %{ "subl $dst, $src\t# int" %}
8130 opcode(0x81); /* Opcode 81 /5 id */
8131 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8132 ins_pipe(ialu_mem_imm);
8133 %}
8134
8135 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8136 %{
8137 match(Set dst (SubL dst src));
8138 effect(KILL cr);
8139
8140 format %{ "subq $dst, $src\t# long" %}
8141 opcode(0x2B);
8142 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8143 ins_pipe(ialu_reg_reg);
8144 %}
8145
8146 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8147 %{
8148 match(Set dst (SubL dst src));
8149 effect(KILL cr);
8150
8151 format %{ "subq $dst, $src\t# long" %}
8152 opcode(0x81, 0x05); /* Opcode 81 /5 */
8153 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8154 ins_pipe(ialu_reg);
8155 %}
8156
8157 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8158 %{
8159 match(Set dst (SubL dst (LoadL src)));
8160 effect(KILL cr);
8161
8162 ins_cost(125);
8163 format %{ "subq $dst, $src\t# long" %}
8164 opcode(0x2B);
8165 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8166 ins_pipe(ialu_reg_mem);
8167 %}
8168
8169 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8170 %{
8171 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8172 effect(KILL cr);
8173
8174 ins_cost(150);
8175 format %{ "subq $dst, $src\t# long" %}
8176 opcode(0x29); /* Opcode 29 /r */
8177 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8178 ins_pipe(ialu_mem_reg);
8179 %}
8180
8181 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8182 %{
8183 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8184 effect(KILL cr);
8185
8186 ins_cost(125); // XXX
8187 format %{ "subq $dst, $src\t# long" %}
8188 opcode(0x81); /* Opcode 81 /5 id */
8189 ins_encode(REX_mem_wide(dst),
8190 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8191 ins_pipe(ialu_mem_imm);
8192 %}
8193
8194 // Subtract from a pointer
8195 // XXX hmpf???
8196 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8197 %{
8198 match(Set dst (AddP dst (SubI zero src)));
8199 effect(KILL cr);
8200
8201 format %{ "subq $dst, $src\t# ptr - int" %}
8202 opcode(0x2B);
8203 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8204 ins_pipe(ialu_reg_reg);
8205 %}
8206
8207 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8208 %{
8209 match(Set dst (SubI zero dst));
8210 effect(KILL cr);
8211
8212 format %{ "negl $dst\t# int" %}
8213 opcode(0xF7, 0x03); // Opcode F7 /3
8214 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8215 ins_pipe(ialu_reg);
8216 %}
8217
8218 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8219 %{
8220 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8221 effect(KILL cr);
8222
8223 format %{ "negl $dst\t# int" %}
8224 opcode(0xF7, 0x03); // Opcode F7 /3
8225 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8226 ins_pipe(ialu_reg);
8227 %}
8228
8229 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8230 %{
8231 match(Set dst (SubL zero dst));
8232 effect(KILL cr);
8233
8234 format %{ "negq $dst\t# long" %}
8235 opcode(0xF7, 0x03); // Opcode F7 /3
8236 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8237 ins_pipe(ialu_reg);
8238 %}
8239
8240 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8241 %{
8242 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8243 effect(KILL cr);
8244
8245 format %{ "negq $dst\t# long" %}
8246 opcode(0xF7, 0x03); // Opcode F7 /3
8247 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8248 ins_pipe(ialu_reg);
8249 %}
8250
8251 //----------Multiplication/Division Instructions-------------------------------
8252 // Integer Multiplication Instructions
8253 // Multiply Register
8254
8255 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8256 %{
8257 match(Set dst (MulI dst src));
8258 effect(KILL cr);
8259
8260 ins_cost(300);
8261 format %{ "imull $dst, $src\t# int" %}
8262 opcode(0x0F, 0xAF);
8263 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8264 ins_pipe(ialu_reg_reg_alu0);
8265 %}
8266
8267 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8268 %{
8269 match(Set dst (MulI src imm));
8270 effect(KILL cr);
8271
8272 ins_cost(300);
8273 format %{ "imull $dst, $src, $imm\t# int" %}
8274 opcode(0x69); /* 69 /r id */
8275 ins_encode(REX_reg_reg(dst, src),
8276 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8277 ins_pipe(ialu_reg_reg_alu0);
8278 %}
8279
8280 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8281 %{
8282 match(Set dst (MulI dst (LoadI src)));
8283 effect(KILL cr);
8284
8285 ins_cost(350);
8286 format %{ "imull $dst, $src\t# int" %}
8287 opcode(0x0F, 0xAF);
8288 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8289 ins_pipe(ialu_reg_mem_alu0);
8290 %}
8291
8292 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8293 %{
8294 match(Set dst (MulI (LoadI src) imm));
8295 effect(KILL cr);
8296
8297 ins_cost(300);
8298 format %{ "imull $dst, $src, $imm\t# int" %}
8299 opcode(0x69); /* 69 /r id */
8300 ins_encode(REX_reg_mem(dst, src),
8301 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8302 ins_pipe(ialu_reg_mem_alu0);
8303 %}
8304
8305 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
8306 %{
8307 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
8308 effect(KILL cr, KILL src2);
8309
8310 expand %{ mulI_rReg(dst, src1, cr);
8311 mulI_rReg(src2, src3, cr);
8312 addI_rReg(dst, src2, cr); %}
8313 %}
8314
8315 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8316 %{
8317 match(Set dst (MulL dst src));
8318 effect(KILL cr);
8319
8320 ins_cost(300);
8321 format %{ "imulq $dst, $src\t# long" %}
8322 opcode(0x0F, 0xAF);
8323 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8324 ins_pipe(ialu_reg_reg_alu0);
8325 %}
8326
8327 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8328 %{
8329 match(Set dst (MulL src imm));
8330 effect(KILL cr);
8331
8332 ins_cost(300);
8333 format %{ "imulq $dst, $src, $imm\t# long" %}
8334 opcode(0x69); /* 69 /r id */
8335 ins_encode(REX_reg_reg_wide(dst, src),
8336 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8337 ins_pipe(ialu_reg_reg_alu0);
8338 %}
8339
8340 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8341 %{
8342 match(Set dst (MulL dst (LoadL src)));
8343 effect(KILL cr);
8344
8345 ins_cost(350);
8346 format %{ "imulq $dst, $src\t# long" %}
8347 opcode(0x0F, 0xAF);
8348 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8349 ins_pipe(ialu_reg_mem_alu0);
8350 %}
8351
8352 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8353 %{
8354 match(Set dst (MulL (LoadL src) imm));
8355 effect(KILL cr);
8356
8357 ins_cost(300);
8358 format %{ "imulq $dst, $src, $imm\t# long" %}
8359 opcode(0x69); /* 69 /r id */
8360 ins_encode(REX_reg_mem_wide(dst, src),
8361 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8362 ins_pipe(ialu_reg_mem_alu0);
8363 %}
8364
8365 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8366 %{
8367 match(Set dst (MulHiL src rax));
8368 effect(USE_KILL rax, KILL cr);
8369
8370 ins_cost(300);
8371 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8372 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8373 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8374 ins_pipe(ialu_reg_reg_alu0);
8375 %}
8376
8377 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8378 rFlagsReg cr)
8379 %{
8380 match(Set rax (DivI rax div));
8381 effect(KILL rdx, KILL cr);
8382
8383 ins_cost(30*100+10*100); // XXX
8384 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8385 "jne,s normal\n\t"
8386 "xorl rdx, rdx\n\t"
8387 "cmpl $div, -1\n\t"
8388 "je,s done\n"
8389 "normal: cdql\n\t"
8390 "idivl $div\n"
8391 "done:" %}
8392 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8393 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8394 ins_pipe(ialu_reg_reg_alu0);
8395 %}
8396
8397 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8398 rFlagsReg cr)
8399 %{
8400 match(Set rax (DivL rax div));
8401 effect(KILL rdx, KILL cr);
8402
8403 ins_cost(30*100+10*100); // XXX
8404 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8405 "cmpq rax, rdx\n\t"
8406 "jne,s normal\n\t"
8407 "xorl rdx, rdx\n\t"
8408 "cmpq $div, -1\n\t"
8409 "je,s done\n"
8410 "normal: cdqq\n\t"
8411 "idivq $div\n"
8412 "done:" %}
8413 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8414 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8415 ins_pipe(ialu_reg_reg_alu0);
8416 %}
8417
8418 // Integer DIVMOD with Register, both quotient and mod results
8419 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8420 rFlagsReg cr)
8421 %{
8422 match(DivModI rax div);
8423 effect(KILL cr);
8424
8425 ins_cost(30*100+10*100); // XXX
8426 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8427 "jne,s normal\n\t"
8428 "xorl rdx, rdx\n\t"
8429 "cmpl $div, -1\n\t"
8430 "je,s done\n"
8431 "normal: cdql\n\t"
8432 "idivl $div\n"
8433 "done:" %}
8434 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8435 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8436 ins_pipe(pipe_slow);
8437 %}
8438
8439 // Long DIVMOD with Register, both quotient and mod results
8440 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8441 rFlagsReg cr)
8442 %{
8443 match(DivModL rax div);
8444 effect(KILL cr);
8445
8446 ins_cost(30*100+10*100); // XXX
8447 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8448 "cmpq rax, rdx\n\t"
8449 "jne,s normal\n\t"
8450 "xorl rdx, rdx\n\t"
8451 "cmpq $div, -1\n\t"
8452 "je,s done\n"
8453 "normal: cdqq\n\t"
8454 "idivq $div\n"
8455 "done:" %}
8456 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8457 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8458 ins_pipe(pipe_slow);
8459 %}
8460
8461 //----------- DivL-By-Constant-Expansions--------------------------------------
8462 // DivI cases are handled by the compiler
8463
8464 // Magic constant, reciprocal of 10
8465 instruct loadConL_0x6666666666666667(rRegL dst)
8466 %{
8467 effect(DEF dst);
8468
8469 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8470 ins_encode(load_immL(dst, 0x6666666666666667));
8471 ins_pipe(ialu_reg);
8472 %}
8473
8474 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8475 %{
8476 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8477
8478 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8479 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8480 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8481 ins_pipe(ialu_reg_reg_alu0);
8482 %}
8483
8484 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8485 %{
8486 effect(USE_DEF dst, KILL cr);
8487
8488 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8489 opcode(0xC1, 0x7); /* C1 /7 ib */
8490 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8491 ins_pipe(ialu_reg);
8492 %}
8493
8494 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8495 %{
8496 effect(USE_DEF dst, KILL cr);
8497
8498 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8499 opcode(0xC1, 0x7); /* C1 /7 ib */
8500 ins_encode(reg_opc_imm_wide(dst, 0x2));
8501 ins_pipe(ialu_reg);
8502 %}
8503
8504 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8505 %{
8506 match(Set dst (DivL src div));
8507
8508 ins_cost((5+8)*100);
8509 expand %{
8510 rax_RegL rax; // Killed temp
8511 rFlagsReg cr; // Killed
8512 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8513 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8514 sarL_rReg_63(src, cr); // sarq src, 63
8515 sarL_rReg_2(dst, cr); // sarq rdx, 2
8516 subL_rReg(dst, src, cr); // subl rdx, src
8517 %}
8518 %}
8519
8520 //-----------------------------------------------------------------------------
8521
8522 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8523 rFlagsReg cr)
8524 %{
8525 match(Set rdx (ModI rax div));
8526 effect(KILL rax, KILL cr);
8527
8528 ins_cost(300); // XXX
8529 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8530 "jne,s normal\n\t"
8531 "xorl rdx, rdx\n\t"
8532 "cmpl $div, -1\n\t"
8533 "je,s done\n"
8534 "normal: cdql\n\t"
8535 "idivl $div\n"
8536 "done:" %}
8537 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8538 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8539 ins_pipe(ialu_reg_reg_alu0);
8540 %}
8541
8542 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8543 rFlagsReg cr)
8544 %{
8545 match(Set rdx (ModL rax div));
8546 effect(KILL rax, KILL cr);
8547
8548 ins_cost(300); // XXX
8549 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8550 "cmpq rax, rdx\n\t"
8551 "jne,s normal\n\t"
8552 "xorl rdx, rdx\n\t"
8553 "cmpq $div, -1\n\t"
8554 "je,s done\n"
8555 "normal: cdqq\n\t"
8556 "idivq $div\n"
8557 "done:" %}
8558 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8559 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8560 ins_pipe(ialu_reg_reg_alu0);
8561 %}
8562
8563 // Integer Shift Instructions
8564 // Shift Left by one
8565 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8566 %{
8567 match(Set dst (LShiftI dst shift));
8568 effect(KILL cr);
8569
8570 format %{ "sall $dst, $shift" %}
8571 opcode(0xD1, 0x4); /* D1 /4 */
8572 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8573 ins_pipe(ialu_reg);
8574 %}
8575
8576 // Shift Left by one
8577 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8578 %{
8579 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8580 effect(KILL cr);
8581
8582 format %{ "sall $dst, $shift\t" %}
8583 opcode(0xD1, 0x4); /* D1 /4 */
8584 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8585 ins_pipe(ialu_mem_imm);
8586 %}
8587
8588 // Shift Left by 8-bit immediate
8589 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8590 %{
8591 match(Set dst (LShiftI dst shift));
8592 effect(KILL cr);
8593
8594 format %{ "sall $dst, $shift" %}
8595 opcode(0xC1, 0x4); /* C1 /4 ib */
8596 ins_encode(reg_opc_imm(dst, shift));
8597 ins_pipe(ialu_reg);
8598 %}
8599
8600 // Shift Left by 8-bit immediate
8601 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8602 %{
8603 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8604 effect(KILL cr);
8605
8606 format %{ "sall $dst, $shift" %}
8607 opcode(0xC1, 0x4); /* C1 /4 ib */
8608 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8609 ins_pipe(ialu_mem_imm);
8610 %}
8611
8612 // Shift Left by variable
8613 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8614 %{
8615 match(Set dst (LShiftI dst shift));
8616 effect(KILL cr);
8617
8618 format %{ "sall $dst, $shift" %}
8619 opcode(0xD3, 0x4); /* D3 /4 */
8620 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8621 ins_pipe(ialu_reg_reg);
8622 %}
8623
8624 // Shift Left by variable
8625 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8626 %{
8627 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8628 effect(KILL cr);
8629
8630 format %{ "sall $dst, $shift" %}
8631 opcode(0xD3, 0x4); /* D3 /4 */
8632 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8633 ins_pipe(ialu_mem_reg);
8634 %}
8635
8636 // Arithmetic shift right by one
8637 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8638 %{
8639 match(Set dst (RShiftI dst shift));
8640 effect(KILL cr);
8641
8642 format %{ "sarl $dst, $shift" %}
8643 opcode(0xD1, 0x7); /* D1 /7 */
8644 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8645 ins_pipe(ialu_reg);
8646 %}
8647
8648 // Arithmetic shift right by one
8649 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8650 %{
8651 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8652 effect(KILL cr);
8653
8654 format %{ "sarl $dst, $shift" %}
8655 opcode(0xD1, 0x7); /* D1 /7 */
8656 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8657 ins_pipe(ialu_mem_imm);
8658 %}
8659
8660 // Arithmetic Shift Right by 8-bit immediate
8661 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8662 %{
8663 match(Set dst (RShiftI dst shift));
8664 effect(KILL cr);
8665
8666 format %{ "sarl $dst, $shift" %}
8667 opcode(0xC1, 0x7); /* C1 /7 ib */
8668 ins_encode(reg_opc_imm(dst, shift));
8669 ins_pipe(ialu_mem_imm);
8670 %}
8671
8672 // Arithmetic Shift Right by 8-bit immediate
8673 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8674 %{
8675 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8676 effect(KILL cr);
8677
8678 format %{ "sarl $dst, $shift" %}
8679 opcode(0xC1, 0x7); /* C1 /7 ib */
8680 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8681 ins_pipe(ialu_mem_imm);
8682 %}
8683
8684 // Arithmetic Shift Right by variable
8685 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8686 %{
8687 match(Set dst (RShiftI dst shift));
8688 effect(KILL cr);
8689
8690 format %{ "sarl $dst, $shift" %}
8691 opcode(0xD3, 0x7); /* D3 /7 */
8692 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8693 ins_pipe(ialu_reg_reg);
8694 %}
8695
8696 // Arithmetic Shift Right by variable
8697 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8698 %{
8699 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8700 effect(KILL cr);
8701
8702 format %{ "sarl $dst, $shift" %}
8703 opcode(0xD3, 0x7); /* D3 /7 */
8704 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8705 ins_pipe(ialu_mem_reg);
8706 %}
8707
8708 // Logical shift right by one
8709 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8710 %{
8711 match(Set dst (URShiftI dst shift));
8712 effect(KILL cr);
8713
8714 format %{ "shrl $dst, $shift" %}
8715 opcode(0xD1, 0x5); /* D1 /5 */
8716 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8717 ins_pipe(ialu_reg);
8718 %}
8719
8720 // Logical shift right by one
8721 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8722 %{
8723 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8724 effect(KILL cr);
8725
8726 format %{ "shrl $dst, $shift" %}
8727 opcode(0xD1, 0x5); /* D1 /5 */
8728 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8729 ins_pipe(ialu_mem_imm);
8730 %}
8731
8732 // Logical Shift Right by 8-bit immediate
8733 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8734 %{
8735 match(Set dst (URShiftI dst shift));
8736 effect(KILL cr);
8737
8738 format %{ "shrl $dst, $shift" %}
8739 opcode(0xC1, 0x5); /* C1 /5 ib */
8740 ins_encode(reg_opc_imm(dst, shift));
8741 ins_pipe(ialu_reg);
8742 %}
8743
8744 // Logical Shift Right by 8-bit immediate
8745 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8746 %{
8747 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8748 effect(KILL cr);
8749
8750 format %{ "shrl $dst, $shift" %}
8751 opcode(0xC1, 0x5); /* C1 /5 ib */
8752 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8753 ins_pipe(ialu_mem_imm);
8754 %}
8755
8756 // Logical Shift Right by variable
8757 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8758 %{
8759 match(Set dst (URShiftI dst shift));
8760 effect(KILL cr);
8761
8762 format %{ "shrl $dst, $shift" %}
8763 opcode(0xD3, 0x5); /* D3 /5 */
8764 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8765 ins_pipe(ialu_reg_reg);
8766 %}
8767
8768 // Logical Shift Right by variable
8769 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8770 %{
8771 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8772 effect(KILL cr);
8773
8774 format %{ "shrl $dst, $shift" %}
8775 opcode(0xD3, 0x5); /* D3 /5 */
8776 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8777 ins_pipe(ialu_mem_reg);
8778 %}
8779
8780 // Long Shift Instructions
8781 // Shift Left by one
8782 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8783 %{
8784 match(Set dst (LShiftL dst shift));
8785 effect(KILL cr);
8786
8787 format %{ "salq $dst, $shift" %}
8788 opcode(0xD1, 0x4); /* D1 /4 */
8789 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8790 ins_pipe(ialu_reg);
8791 %}
8792
8793 // Shift Left by one
8794 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8795 %{
8796 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8797 effect(KILL cr);
8798
8799 format %{ "salq $dst, $shift" %}
8800 opcode(0xD1, 0x4); /* D1 /4 */
8801 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8802 ins_pipe(ialu_mem_imm);
8803 %}
8804
8805 // Shift Left by 8-bit immediate
8806 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8807 %{
8808 match(Set dst (LShiftL dst shift));
8809 effect(KILL cr);
8810
8811 format %{ "salq $dst, $shift" %}
8812 opcode(0xC1, 0x4); /* C1 /4 ib */
8813 ins_encode(reg_opc_imm_wide(dst, shift));
8814 ins_pipe(ialu_reg);
8815 %}
8816
8817 // Shift Left by 8-bit immediate
8818 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8819 %{
8820 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8821 effect(KILL cr);
8822
8823 format %{ "salq $dst, $shift" %}
8824 opcode(0xC1, 0x4); /* C1 /4 ib */
8825 ins_encode(REX_mem_wide(dst), OpcP,
8826 RM_opc_mem(secondary, dst), Con8or32(shift));
8827 ins_pipe(ialu_mem_imm);
8828 %}
8829
8830 // Shift Left by variable
8831 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8832 %{
8833 match(Set dst (LShiftL dst shift));
8834 effect(KILL cr);
8835
8836 format %{ "salq $dst, $shift" %}
8837 opcode(0xD3, 0x4); /* D3 /4 */
8838 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8839 ins_pipe(ialu_reg_reg);
8840 %}
8841
8842 // Shift Left by variable
8843 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8844 %{
8845 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8846 effect(KILL cr);
8847
8848 format %{ "salq $dst, $shift" %}
8849 opcode(0xD3, 0x4); /* D3 /4 */
8850 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8851 ins_pipe(ialu_mem_reg);
8852 %}
8853
8854 // Arithmetic shift right by one
8855 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8856 %{
8857 match(Set dst (RShiftL dst shift));
8858 effect(KILL cr);
8859
8860 format %{ "sarq $dst, $shift" %}
8861 opcode(0xD1, 0x7); /* D1 /7 */
8862 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8863 ins_pipe(ialu_reg);
8864 %}
8865
8866 // Arithmetic shift right by one
8867 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8868 %{
8869 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8870 effect(KILL cr);
8871
8872 format %{ "sarq $dst, $shift" %}
8873 opcode(0xD1, 0x7); /* D1 /7 */
8874 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8875 ins_pipe(ialu_mem_imm);
8876 %}
8877
8878 // Arithmetic Shift Right by 8-bit immediate
8879 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8880 %{
8881 match(Set dst (RShiftL dst shift));
8882 effect(KILL cr);
8883
8884 format %{ "sarq $dst, $shift" %}
8885 opcode(0xC1, 0x7); /* C1 /7 ib */
8886 ins_encode(reg_opc_imm_wide(dst, shift));
8887 ins_pipe(ialu_mem_imm);
8888 %}
8889
8890 // Arithmetic Shift Right by 8-bit immediate
8891 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8892 %{
8893 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8894 effect(KILL cr);
8895
8896 format %{ "sarq $dst, $shift" %}
8897 opcode(0xC1, 0x7); /* C1 /7 ib */
8898 ins_encode(REX_mem_wide(dst), OpcP,
8899 RM_opc_mem(secondary, dst), Con8or32(shift));
8900 ins_pipe(ialu_mem_imm);
8901 %}
8902
8903 // Arithmetic Shift Right by variable
8904 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8905 %{
8906 match(Set dst (RShiftL dst shift));
8907 effect(KILL cr);
8908
8909 format %{ "sarq $dst, $shift" %}
8910 opcode(0xD3, 0x7); /* D3 /7 */
8911 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8912 ins_pipe(ialu_reg_reg);
8913 %}
8914
8915 // Arithmetic Shift Right by variable
8916 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8917 %{
8918 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8919 effect(KILL cr);
8920
8921 format %{ "sarq $dst, $shift" %}
8922 opcode(0xD3, 0x7); /* D3 /7 */
8923 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8924 ins_pipe(ialu_mem_reg);
8925 %}
8926
8927 // Logical shift right by one
8928 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8929 %{
8930 match(Set dst (URShiftL dst shift));
8931 effect(KILL cr);
8932
8933 format %{ "shrq $dst, $shift" %}
8934 opcode(0xD1, 0x5); /* D1 /5 */
8935 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8936 ins_pipe(ialu_reg);
8937 %}
8938
8939 // Logical shift right by one
8940 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8941 %{
8942 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8943 effect(KILL cr);
8944
8945 format %{ "shrq $dst, $shift" %}
8946 opcode(0xD1, 0x5); /* D1 /5 */
8947 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8948 ins_pipe(ialu_mem_imm);
8949 %}
8950
8951 // Logical Shift Right by 8-bit immediate
8952 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8953 %{
8954 match(Set dst (URShiftL dst shift));
8955 effect(KILL cr);
8956
8957 format %{ "shrq $dst, $shift" %}
8958 opcode(0xC1, 0x5); /* C1 /5 ib */
8959 ins_encode(reg_opc_imm_wide(dst, shift));
8960 ins_pipe(ialu_reg);
8961 %}
8962
8963
8964 // Logical Shift Right by 8-bit immediate
8965 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8966 %{
8967 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8968 effect(KILL cr);
8969
8970 format %{ "shrq $dst, $shift" %}
8971 opcode(0xC1, 0x5); /* C1 /5 ib */
8972 ins_encode(REX_mem_wide(dst), OpcP,
8973 RM_opc_mem(secondary, dst), Con8or32(shift));
8974 ins_pipe(ialu_mem_imm);
8975 %}
8976
8977 // Logical Shift Right by variable
8978 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8979 %{
8980 match(Set dst (URShiftL dst shift));
8981 effect(KILL cr);
8982
8983 format %{ "shrq $dst, $shift" %}
8984 opcode(0xD3, 0x5); /* D3 /5 */
8985 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8986 ins_pipe(ialu_reg_reg);
8987 %}
8988
8989 // Logical Shift Right by variable
8990 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8991 %{
8992 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8993 effect(KILL cr);
8994
8995 format %{ "shrq $dst, $shift" %}
8996 opcode(0xD3, 0x5); /* D3 /5 */
8997 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8998 ins_pipe(ialu_mem_reg);
8999 %}
9000
9001 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9002 // This idiom is used by the compiler for the i2b bytecode.
9003 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9004 %{
9005 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9006
9007 format %{ "movsbl $dst, $src\t# i2b" %}
9008 opcode(0x0F, 0xBE);
9009 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9010 ins_pipe(ialu_reg_reg);
9011 %}
9012
9013 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9014 // This idiom is used by the compiler the i2s bytecode.
9015 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9016 %{
9017 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9018
9019 format %{ "movswl $dst, $src\t# i2s" %}
9020 opcode(0x0F, 0xBF);
9021 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9022 ins_pipe(ialu_reg_reg);
9023 %}
9024
9025 // ROL/ROR instructions
9026
9027 // ROL expand
9028 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
9029 effect(KILL cr, USE_DEF dst);
9030
9031 format %{ "roll $dst" %}
9032 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9033 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9034 ins_pipe(ialu_reg);
9035 %}
9036
9037 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
9038 effect(USE_DEF dst, USE shift, KILL cr);
9039
9040 format %{ "roll $dst, $shift" %}
9041 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9042 ins_encode( reg_opc_imm(dst, shift) );
9043 ins_pipe(ialu_reg);
9044 %}
9045
9046 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9047 %{
9048 effect(USE_DEF dst, USE shift, KILL cr);
9049
9050 format %{ "roll $dst, $shift" %}
9051 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9052 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9053 ins_pipe(ialu_reg_reg);
9054 %}
9055 // end of ROL expand
9056
9057 // Rotate Left by one
9058 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9059 %{
9060 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9061
9062 expand %{
9063 rolI_rReg_imm1(dst, cr);
9064 %}
9065 %}
9066
9067 // Rotate Left by 8-bit immediate
9068 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9069 %{
9070 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9071 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9072
9073 expand %{
9074 rolI_rReg_imm8(dst, lshift, cr);
9075 %}
9076 %}
9077
9078 // Rotate Left by variable
9079 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9080 %{
9081 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9082
9083 expand %{
9084 rolI_rReg_CL(dst, shift, cr);
9085 %}
9086 %}
9087
9088 // Rotate Left by variable
9089 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9090 %{
9091 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9092
9093 expand %{
9094 rolI_rReg_CL(dst, shift, cr);
9095 %}
9096 %}
9097
9098 // ROR expand
9099 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9100 %{
9101 effect(USE_DEF dst, KILL cr);
9102
9103 format %{ "rorl $dst" %}
9104 opcode(0xD1, 0x1); /* D1 /1 */
9105 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9106 ins_pipe(ialu_reg);
9107 %}
9108
9109 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
9110 %{
9111 effect(USE_DEF dst, USE shift, KILL cr);
9112
9113 format %{ "rorl $dst, $shift" %}
9114 opcode(0xC1, 0x1); /* C1 /1 ib */
9115 ins_encode(reg_opc_imm(dst, shift));
9116 ins_pipe(ialu_reg);
9117 %}
9118
9119 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9120 %{
9121 effect(USE_DEF dst, USE shift, KILL cr);
9122
9123 format %{ "rorl $dst, $shift" %}
9124 opcode(0xD3, 0x1); /* D3 /1 */
9125 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9126 ins_pipe(ialu_reg_reg);
9127 %}
9128 // end of ROR expand
9129
9130 // Rotate Right by one
9131 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9132 %{
9133 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9134
9135 expand %{
9136 rorI_rReg_imm1(dst, cr);
9137 %}
9138 %}
9139
9140 // Rotate Right by 8-bit immediate
9141 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9142 %{
9143 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9144 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9145
9146 expand %{
9147 rorI_rReg_imm8(dst, rshift, cr);
9148 %}
9149 %}
9150
9151 // Rotate Right by variable
9152 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9153 %{
9154 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9155
9156 expand %{
9157 rorI_rReg_CL(dst, shift, cr);
9158 %}
9159 %}
9160
9161 // Rotate Right by variable
9162 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9163 %{
9164 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9165
9166 expand %{
9167 rorI_rReg_CL(dst, shift, cr);
9168 %}
9169 %}
9170
9171 // for long rotate
9172 // ROL expand
9173 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9174 effect(USE_DEF dst, KILL cr);
9175
9176 format %{ "rolq $dst" %}
9177 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9178 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9179 ins_pipe(ialu_reg);
9180 %}
9181
9182 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9183 effect(USE_DEF dst, USE shift, KILL cr);
9184
9185 format %{ "rolq $dst, $shift" %}
9186 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9187 ins_encode( reg_opc_imm_wide(dst, shift) );
9188 ins_pipe(ialu_reg);
9189 %}
9190
9191 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9192 %{
9193 effect(USE_DEF dst, USE shift, KILL cr);
9194
9195 format %{ "rolq $dst, $shift" %}
9196 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9197 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9198 ins_pipe(ialu_reg_reg);
9199 %}
9200 // end of ROL expand
9201
9202 // Rotate Left by one
9203 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9204 %{
9205 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9206
9207 expand %{
9208 rolL_rReg_imm1(dst, cr);
9209 %}
9210 %}
9211
9212 // Rotate Left by 8-bit immediate
9213 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9214 %{
9215 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9216 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9217
9218 expand %{
9219 rolL_rReg_imm8(dst, lshift, cr);
9220 %}
9221 %}
9222
9223 // Rotate Left by variable
9224 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9225 %{
9226 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9227
9228 expand %{
9229 rolL_rReg_CL(dst, shift, cr);
9230 %}
9231 %}
9232
9233 // Rotate Left by variable
9234 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9235 %{
9236 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9237
9238 expand %{
9239 rolL_rReg_CL(dst, shift, cr);
9240 %}
9241 %}
9242
9243 // ROR expand
9244 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9245 %{
9246 effect(USE_DEF dst, KILL cr);
9247
9248 format %{ "rorq $dst" %}
9249 opcode(0xD1, 0x1); /* D1 /1 */
9250 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9251 ins_pipe(ialu_reg);
9252 %}
9253
9254 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9255 %{
9256 effect(USE_DEF dst, USE shift, KILL cr);
9257
9258 format %{ "rorq $dst, $shift" %}
9259 opcode(0xC1, 0x1); /* C1 /1 ib */
9260 ins_encode(reg_opc_imm_wide(dst, shift));
9261 ins_pipe(ialu_reg);
9262 %}
9263
9264 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9265 %{
9266 effect(USE_DEF dst, USE shift, KILL cr);
9267
9268 format %{ "rorq $dst, $shift" %}
9269 opcode(0xD3, 0x1); /* D3 /1 */
9270 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9271 ins_pipe(ialu_reg_reg);
9272 %}
9273 // end of ROR expand
9274
9275 // Rotate Right by one
9276 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9277 %{
9278 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9279
9280 expand %{
9281 rorL_rReg_imm1(dst, cr);
9282 %}
9283 %}
9284
9285 // Rotate Right by 8-bit immediate
9286 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9287 %{
9288 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9289 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9290
9291 expand %{
9292 rorL_rReg_imm8(dst, rshift, cr);
9293 %}
9294 %}
9295
9296 // Rotate Right by variable
9297 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9298 %{
9299 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9300
9301 expand %{
9302 rorL_rReg_CL(dst, shift, cr);
9303 %}
9304 %}
9305
9306 // Rotate Right by variable
9307 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9308 %{
9309 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9310
9311 expand %{
9312 rorL_rReg_CL(dst, shift, cr);
9313 %}
9314 %}
9315
9316 // Logical Instructions
9317
9318 // Integer Logical Instructions
9319
9320 // And Instructions
9321 // And Register with Register
9322 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9323 %{
9324 match(Set dst (AndI dst src));
9325 effect(KILL cr);
9326
9327 format %{ "andl $dst, $src\t# int" %}
9328 opcode(0x23);
9329 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9330 ins_pipe(ialu_reg_reg);
9331 %}
9332
9333 // And Register with Immediate 255
9334 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9335 %{
9336 match(Set dst (AndI dst src));
9337
9338 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9339 opcode(0x0F, 0xB6);
9340 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9341 ins_pipe(ialu_reg);
9342 %}
9343
9344 // And Register with Immediate 255 and promote to long
9345 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9346 %{
9347 match(Set dst (ConvI2L (AndI src mask)));
9348
9349 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9350 opcode(0x0F, 0xB6);
9351 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9352 ins_pipe(ialu_reg);
9353 %}
9354
9355 // And Register with Immediate 65535
9356 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9357 %{
9358 match(Set dst (AndI dst src));
9359
9360 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9361 opcode(0x0F, 0xB7);
9362 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9363 ins_pipe(ialu_reg);
9364 %}
9365
9366 // And Register with Immediate 65535 and promote to long
9367 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9368 %{
9369 match(Set dst (ConvI2L (AndI src mask)));
9370
9371 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9372 opcode(0x0F, 0xB7);
9373 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9374 ins_pipe(ialu_reg);
9375 %}
9376
9377 // And Register with Immediate
9378 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9379 %{
9380 match(Set dst (AndI dst src));
9381 effect(KILL cr);
9382
9383 format %{ "andl $dst, $src\t# int" %}
9384 opcode(0x81, 0x04); /* Opcode 81 /4 */
9385 ins_encode(OpcSErm(dst, src), Con8or32(src));
9386 ins_pipe(ialu_reg);
9387 %}
9388
9389 // And Register with Memory
9390 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9391 %{
9392 match(Set dst (AndI dst (LoadI src)));
9393 effect(KILL cr);
9394
9395 ins_cost(125);
9396 format %{ "andl $dst, $src\t# int" %}
9397 opcode(0x23);
9398 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9399 ins_pipe(ialu_reg_mem);
9400 %}
9401
9402 // And Memory with Register
9403 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9404 %{
9405 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
9406 effect(KILL cr);
9407
9408 ins_cost(150);
9409 format %{ "andb $dst, $src\t# byte" %}
9410 opcode(0x20);
9411 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9412 ins_pipe(ialu_mem_reg);
9413 %}
9414
9415 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9416 %{
9417 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9418 effect(KILL cr);
9419
9420 ins_cost(150);
9421 format %{ "andl $dst, $src\t# int" %}
9422 opcode(0x21); /* Opcode 21 /r */
9423 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9424 ins_pipe(ialu_mem_reg);
9425 %}
9426
9427 // And Memory with Immediate
9428 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9429 %{
9430 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9431 effect(KILL cr);
9432
9433 ins_cost(125);
9434 format %{ "andl $dst, $src\t# int" %}
9435 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9436 ins_encode(REX_mem(dst), OpcSE(src),
9437 RM_opc_mem(secondary, dst), Con8or32(src));
9438 ins_pipe(ialu_mem_imm);
9439 %}
9440
9441 // BMI1 instructions
9442 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9443 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9444 predicate(UseBMI1Instructions);
9445 effect(KILL cr);
9446
9447 ins_cost(125);
9448 format %{ "andnl $dst, $src1, $src2" %}
9449
9450 ins_encode %{
9451 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9452 %}
9453 ins_pipe(ialu_reg_mem);
9454 %}
9455
9456 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9457 match(Set dst (AndI (XorI src1 minus_1) src2));
9458 predicate(UseBMI1Instructions);
9459 effect(KILL cr);
9460
9461 format %{ "andnl $dst, $src1, $src2" %}
9462
9463 ins_encode %{
9464 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9465 %}
9466 ins_pipe(ialu_reg);
9467 %}
9468
9469 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9470 match(Set dst (AndI (SubI imm_zero src) src));
9471 predicate(UseBMI1Instructions);
9472 effect(KILL cr);
9473
9474 format %{ "blsil $dst, $src" %}
9475
9476 ins_encode %{
9477 __ blsil($dst$$Register, $src$$Register);
9478 %}
9479 ins_pipe(ialu_reg);
9480 %}
9481
9482 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9483 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9484 predicate(UseBMI1Instructions);
9485 effect(KILL cr);
9486
9487 ins_cost(125);
9488 format %{ "blsil $dst, $src" %}
9489
9490 ins_encode %{
9491 __ blsil($dst$$Register, $src$$Address);
9492 %}
9493 ins_pipe(ialu_reg_mem);
9494 %}
9495
9496 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9497 %{
9498 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9499 predicate(UseBMI1Instructions);
9500 effect(KILL cr);
9501
9502 ins_cost(125);
9503 format %{ "blsmskl $dst, $src" %}
9504
9505 ins_encode %{
9506 __ blsmskl($dst$$Register, $src$$Address);
9507 %}
9508 ins_pipe(ialu_reg_mem);
9509 %}
9510
9511 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9512 %{
9513 match(Set dst (XorI (AddI src minus_1) src));
9514 predicate(UseBMI1Instructions);
9515 effect(KILL cr);
9516
9517 format %{ "blsmskl $dst, $src" %}
9518
9519 ins_encode %{
9520 __ blsmskl($dst$$Register, $src$$Register);
9521 %}
9522
9523 ins_pipe(ialu_reg);
9524 %}
9525
9526 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9527 %{
9528 match(Set dst (AndI (AddI src minus_1) src) );
9529 predicate(UseBMI1Instructions);
9530 effect(KILL cr);
9531
9532 format %{ "blsrl $dst, $src" %}
9533
9534 ins_encode %{
9535 __ blsrl($dst$$Register, $src$$Register);
9536 %}
9537
9538 ins_pipe(ialu_reg_mem);
9539 %}
9540
9541 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9542 %{
9543 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9544 predicate(UseBMI1Instructions);
9545 effect(KILL cr);
9546
9547 ins_cost(125);
9548 format %{ "blsrl $dst, $src" %}
9549
9550 ins_encode %{
9551 __ blsrl($dst$$Register, $src$$Address);
9552 %}
9553
9554 ins_pipe(ialu_reg);
9555 %}
9556
9557 // Or Instructions
9558 // Or Register with Register
9559 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9560 %{
9561 match(Set dst (OrI dst src));
9562 effect(KILL cr);
9563
9564 format %{ "orl $dst, $src\t# int" %}
9565 opcode(0x0B);
9566 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9567 ins_pipe(ialu_reg_reg);
9568 %}
9569
9570 // Or Register with Immediate
9571 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9572 %{
9573 match(Set dst (OrI dst src));
9574 effect(KILL cr);
9575
9576 format %{ "orl $dst, $src\t# int" %}
9577 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9578 ins_encode(OpcSErm(dst, src), Con8or32(src));
9579 ins_pipe(ialu_reg);
9580 %}
9581
9582 // Or Register with Memory
9583 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9584 %{
9585 match(Set dst (OrI dst (LoadI src)));
9586 effect(KILL cr);
9587
9588 ins_cost(125);
9589 format %{ "orl $dst, $src\t# int" %}
9590 opcode(0x0B);
9591 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9592 ins_pipe(ialu_reg_mem);
9593 %}
9594
9595 // Or Memory with Register
9596 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9597 %{
9598 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
9599 effect(KILL cr);
9600
9601 ins_cost(150);
9602 format %{ "orb $dst, $src\t# byte" %}
9603 opcode(0x08);
9604 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9605 ins_pipe(ialu_mem_reg);
9606 %}
9607
9608 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9609 %{
9610 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9611 effect(KILL cr);
9612
9613 ins_cost(150);
9614 format %{ "orl $dst, $src\t# int" %}
9615 opcode(0x09); /* Opcode 09 /r */
9616 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9617 ins_pipe(ialu_mem_reg);
9618 %}
9619
9620 // Or Memory with Immediate
9621 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9622 %{
9623 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9624 effect(KILL cr);
9625
9626 ins_cost(125);
9627 format %{ "orl $dst, $src\t# int" %}
9628 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9629 ins_encode(REX_mem(dst), OpcSE(src),
9630 RM_opc_mem(secondary, dst), Con8or32(src));
9631 ins_pipe(ialu_mem_imm);
9632 %}
9633
9634 // Xor Instructions
9635 // Xor Register with Register
9636 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9637 %{
9638 match(Set dst (XorI dst src));
9639 effect(KILL cr);
9640
9641 format %{ "xorl $dst, $src\t# int" %}
9642 opcode(0x33);
9643 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9644 ins_pipe(ialu_reg_reg);
9645 %}
9646
9647 // Xor Register with Immediate -1
9648 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9649 match(Set dst (XorI dst imm));
9650
9651 format %{ "not $dst" %}
9652 ins_encode %{
9653 __ notl($dst$$Register);
9654 %}
9655 ins_pipe(ialu_reg);
9656 %}
9657
9658 // Xor Register with Immediate
9659 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9660 %{
9661 match(Set dst (XorI dst src));
9662 effect(KILL cr);
9663
9664 format %{ "xorl $dst, $src\t# int" %}
9665 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9666 ins_encode(OpcSErm(dst, src), Con8or32(src));
9667 ins_pipe(ialu_reg);
9668 %}
9669
9670 // Xor Register with Memory
9671 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9672 %{
9673 match(Set dst (XorI dst (LoadI src)));
9674 effect(KILL cr);
9675
9676 ins_cost(125);
9677 format %{ "xorl $dst, $src\t# int" %}
9678 opcode(0x33);
9679 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9680 ins_pipe(ialu_reg_mem);
9681 %}
9682
9683 // Xor Memory with Register
9684 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9685 %{
9686 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
9687 effect(KILL cr);
9688
9689 ins_cost(150);
9690 format %{ "xorb $dst, $src\t# byte" %}
9691 opcode(0x30);
9692 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9693 ins_pipe(ialu_mem_reg);
9694 %}
9695
9696 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9697 %{
9698 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9699 effect(KILL cr);
9700
9701 ins_cost(150);
9702 format %{ "xorl $dst, $src\t# int" %}
9703 opcode(0x31); /* Opcode 31 /r */
9704 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9705 ins_pipe(ialu_mem_reg);
9706 %}
9707
9708 // Xor Memory with Immediate
9709 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9710 %{
9711 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9712 effect(KILL cr);
9713
9714 ins_cost(125);
9715 format %{ "xorl $dst, $src\t# int" %}
9716 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9717 ins_encode(REX_mem(dst), OpcSE(src),
9718 RM_opc_mem(secondary, dst), Con8or32(src));
9719 ins_pipe(ialu_mem_imm);
9720 %}
9721
9722
9723 // Long Logical Instructions
9724
9725 // And Instructions
9726 // And Register with Register
9727 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9728 %{
9729 match(Set dst (AndL dst src));
9730 effect(KILL cr);
9731
9732 format %{ "andq $dst, $src\t# long" %}
9733 opcode(0x23);
9734 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9735 ins_pipe(ialu_reg_reg);
9736 %}
9737
9738 // And Register with Immediate 255
9739 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9740 %{
9741 match(Set dst (AndL dst src));
9742
9743 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9744 opcode(0x0F, 0xB6);
9745 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9746 ins_pipe(ialu_reg);
9747 %}
9748
9749 // And Register with Immediate 65535
9750 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9751 %{
9752 match(Set dst (AndL dst src));
9753
9754 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9755 opcode(0x0F, 0xB7);
9756 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9757 ins_pipe(ialu_reg);
9758 %}
9759
9760 // And Register with Immediate
9761 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9762 %{
9763 match(Set dst (AndL dst src));
9764 effect(KILL cr);
9765
9766 format %{ "andq $dst, $src\t# long" %}
9767 opcode(0x81, 0x04); /* Opcode 81 /4 */
9768 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9769 ins_pipe(ialu_reg);
9770 %}
9771
9772 // And Register with Memory
9773 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9774 %{
9775 match(Set dst (AndL dst (LoadL src)));
9776 effect(KILL cr);
9777
9778 ins_cost(125);
9779 format %{ "andq $dst, $src\t# long" %}
9780 opcode(0x23);
9781 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9782 ins_pipe(ialu_reg_mem);
9783 %}
9784
9785 // And Memory with Register
9786 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9787 %{
9788 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9789 effect(KILL cr);
9790
9791 ins_cost(150);
9792 format %{ "andq $dst, $src\t# long" %}
9793 opcode(0x21); /* Opcode 21 /r */
9794 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9795 ins_pipe(ialu_mem_reg);
9796 %}
9797
9798 // And Memory with Immediate
9799 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9800 %{
9801 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9802 effect(KILL cr);
9803
9804 ins_cost(125);
9805 format %{ "andq $dst, $src\t# long" %}
9806 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9807 ins_encode(REX_mem_wide(dst), OpcSE(src),
9808 RM_opc_mem(secondary, dst), Con8or32(src));
9809 ins_pipe(ialu_mem_imm);
9810 %}
9811
9812 // BMI1 instructions
9813 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9814 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9815 predicate(UseBMI1Instructions);
9816 effect(KILL cr);
9817
9818 ins_cost(125);
9819 format %{ "andnq $dst, $src1, $src2" %}
9820
9821 ins_encode %{
9822 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9823 %}
9824 ins_pipe(ialu_reg_mem);
9825 %}
9826
9827 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9828 match(Set dst (AndL (XorL src1 minus_1) src2));
9829 predicate(UseBMI1Instructions);
9830 effect(KILL cr);
9831
9832 format %{ "andnq $dst, $src1, $src2" %}
9833
9834 ins_encode %{
9835 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9836 %}
9837 ins_pipe(ialu_reg_mem);
9838 %}
9839
9840 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9841 match(Set dst (AndL (SubL imm_zero src) src));
9842 predicate(UseBMI1Instructions);
9843 effect(KILL cr);
9844
9845 format %{ "blsiq $dst, $src" %}
9846
9847 ins_encode %{
9848 __ blsiq($dst$$Register, $src$$Register);
9849 %}
9850 ins_pipe(ialu_reg);
9851 %}
9852
9853 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9854 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9855 predicate(UseBMI1Instructions);
9856 effect(KILL cr);
9857
9858 ins_cost(125);
9859 format %{ "blsiq $dst, $src" %}
9860
9861 ins_encode %{
9862 __ blsiq($dst$$Register, $src$$Address);
9863 %}
9864 ins_pipe(ialu_reg_mem);
9865 %}
9866
9867 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9868 %{
9869 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9870 predicate(UseBMI1Instructions);
9871 effect(KILL cr);
9872
9873 ins_cost(125);
9874 format %{ "blsmskq $dst, $src" %}
9875
9876 ins_encode %{
9877 __ blsmskq($dst$$Register, $src$$Address);
9878 %}
9879 ins_pipe(ialu_reg_mem);
9880 %}
9881
9882 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9883 %{
9884 match(Set dst (XorL (AddL src minus_1) src));
9885 predicate(UseBMI1Instructions);
9886 effect(KILL cr);
9887
9888 format %{ "blsmskq $dst, $src" %}
9889
9890 ins_encode %{
9891 __ blsmskq($dst$$Register, $src$$Register);
9892 %}
9893
9894 ins_pipe(ialu_reg);
9895 %}
9896
9897 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9898 %{
9899 match(Set dst (AndL (AddL src minus_1) src) );
9900 predicate(UseBMI1Instructions);
9901 effect(KILL cr);
9902
9903 format %{ "blsrq $dst, $src" %}
9904
9905 ins_encode %{
9906 __ blsrq($dst$$Register, $src$$Register);
9907 %}
9908
9909 ins_pipe(ialu_reg);
9910 %}
9911
9912 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9913 %{
9914 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9915 predicate(UseBMI1Instructions);
9916 effect(KILL cr);
9917
9918 ins_cost(125);
9919 format %{ "blsrq $dst, $src" %}
9920
9921 ins_encode %{
9922 __ blsrq($dst$$Register, $src$$Address);
9923 %}
9924
9925 ins_pipe(ialu_reg);
9926 %}
9927
9928 // Or Instructions
9929 // Or Register with Register
9930 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9931 %{
9932 match(Set dst (OrL dst src));
9933 effect(KILL cr);
9934
9935 format %{ "orq $dst, $src\t# long" %}
9936 opcode(0x0B);
9937 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9938 ins_pipe(ialu_reg_reg);
9939 %}
9940
9941 // Use any_RegP to match R15 (TLS register) without spilling.
9942 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9943 match(Set dst (OrL dst (CastP2X src)));
9944 effect(KILL cr);
9945
9946 format %{ "orq $dst, $src\t# long" %}
9947 opcode(0x0B);
9948 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9949 ins_pipe(ialu_reg_reg);
9950 %}
9951
9952
9953 // Or Register with Immediate
9954 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9955 %{
9956 match(Set dst (OrL dst src));
9957 effect(KILL cr);
9958
9959 format %{ "orq $dst, $src\t# long" %}
9960 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9961 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9962 ins_pipe(ialu_reg);
9963 %}
9964
9965 // Or Register with Memory
9966 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9967 %{
9968 match(Set dst (OrL dst (LoadL src)));
9969 effect(KILL cr);
9970
9971 ins_cost(125);
9972 format %{ "orq $dst, $src\t# long" %}
9973 opcode(0x0B);
9974 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9975 ins_pipe(ialu_reg_mem);
9976 %}
9977
9978 // Or Memory with Register
9979 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9980 %{
9981 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9982 effect(KILL cr);
9983
9984 ins_cost(150);
9985 format %{ "orq $dst, $src\t# long" %}
9986 opcode(0x09); /* Opcode 09 /r */
9987 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9988 ins_pipe(ialu_mem_reg);
9989 %}
9990
9991 // Or Memory with Immediate
9992 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9993 %{
9994 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9995 effect(KILL cr);
9996
9997 ins_cost(125);
9998 format %{ "orq $dst, $src\t# long" %}
9999 opcode(0x81, 0x1); /* Opcode 81 /1 id */
10000 ins_encode(REX_mem_wide(dst), OpcSE(src),
10001 RM_opc_mem(secondary, dst), Con8or32(src));
10002 ins_pipe(ialu_mem_imm);
10003 %}
10004
10005 // Xor Instructions
10006 // Xor Register with Register
10007 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10008 %{
10009 match(Set dst (XorL dst src));
10010 effect(KILL cr);
10011
10012 format %{ "xorq $dst, $src\t# long" %}
10013 opcode(0x33);
10014 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10015 ins_pipe(ialu_reg_reg);
10016 %}
10017
10018 // Xor Register with Immediate -1
10019 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10020 match(Set dst (XorL dst imm));
10021
10022 format %{ "notq $dst" %}
10023 ins_encode %{
10024 __ notq($dst$$Register);
10025 %}
10026 ins_pipe(ialu_reg);
10027 %}
10028
10029 // Xor Register with Immediate
10030 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10031 %{
10032 match(Set dst (XorL dst src));
10033 effect(KILL cr);
10034
10035 format %{ "xorq $dst, $src\t# long" %}
10036 opcode(0x81, 0x06); /* Opcode 81 /6 id */
10037 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10038 ins_pipe(ialu_reg);
10039 %}
10040
10041 // Xor Register with Memory
10042 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10043 %{
10044 match(Set dst (XorL dst (LoadL src)));
10045 effect(KILL cr);
10046
10047 ins_cost(125);
10048 format %{ "xorq $dst, $src\t# long" %}
10049 opcode(0x33);
10050 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10051 ins_pipe(ialu_reg_mem);
10052 %}
10053
10054 // Xor Memory with Register
10055 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10056 %{
10057 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10058 effect(KILL cr);
10059
10060 ins_cost(150);
10061 format %{ "xorq $dst, $src\t# long" %}
10062 opcode(0x31); /* Opcode 31 /r */
10063 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10064 ins_pipe(ialu_mem_reg);
10065 %}
10066
10067 // Xor Memory with Immediate
10068 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10069 %{
10070 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10071 effect(KILL cr);
10072
10073 ins_cost(125);
10074 format %{ "xorq $dst, $src\t# long" %}
10075 opcode(0x81, 0x6); /* Opcode 81 /6 id */
10076 ins_encode(REX_mem_wide(dst), OpcSE(src),
10077 RM_opc_mem(secondary, dst), Con8or32(src));
10078 ins_pipe(ialu_mem_imm);
10079 %}
10080
10081 // Convert Int to Boolean
10082 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10083 %{
10084 match(Set dst (Conv2B src));
10085 effect(KILL cr);
10086
10087 format %{ "testl $src, $src\t# ci2b\n\t"
10088 "setnz $dst\n\t"
10089 "movzbl $dst, $dst" %}
10090 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
10091 setNZ_reg(dst),
10092 REX_reg_breg(dst, dst), // movzbl
10093 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10094 ins_pipe(pipe_slow); // XXX
10095 %}
10096
10097 // Convert Pointer to Boolean
10098 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10099 %{
10100 match(Set dst (Conv2B src));
10101 effect(KILL cr);
10102
10103 format %{ "testq $src, $src\t# cp2b\n\t"
10104 "setnz $dst\n\t"
10105 "movzbl $dst, $dst" %}
10106 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
10107 setNZ_reg(dst),
10108 REX_reg_breg(dst, dst), // movzbl
10109 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10110 ins_pipe(pipe_slow); // XXX
10111 %}
10112
10113 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10114 %{
10115 match(Set dst (CmpLTMask p q));
10116 effect(KILL cr);
10117
10118 ins_cost(400);
10119 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10120 "setlt $dst\n\t"
10121 "movzbl $dst, $dst\n\t"
10122 "negl $dst" %}
10123 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10124 setLT_reg(dst),
10125 REX_reg_breg(dst, dst), // movzbl
10126 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10127 neg_reg(dst));
10128 ins_pipe(pipe_slow);
10129 %}
10130
10131 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
10132 %{
10133 match(Set dst (CmpLTMask dst zero));
10134 effect(KILL cr);
10135
10136 ins_cost(100);
10137 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10138 ins_encode %{
10139 __ sarl($dst$$Register, 31);
10140 %}
10141 ins_pipe(ialu_reg);
10142 %}
10143
10144 /* Better to save a register than avoid a branch */
10145 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10146 %{
10147 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10148 effect(KILL cr);
10149 ins_cost(300);
10150 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
10151 "jge done\n\t"
10152 "addl $p,$y\n"
10153 "done: " %}
10154 ins_encode %{
10155 Register Rp = $p$$Register;
10156 Register Rq = $q$$Register;
10157 Register Ry = $y$$Register;
10158 Label done;
10159 __ subl(Rp, Rq);
10160 __ jccb(Assembler::greaterEqual, done);
10161 __ addl(Rp, Ry);
10162 __ bind(done);
10163 %}
10164 ins_pipe(pipe_cmplt);
10165 %}
10166
10167 /* Better to save a register than avoid a branch */
10168 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10169 %{
10170 match(Set y (AndI (CmpLTMask p q) y));
10171 effect(KILL cr);
10172
10173 ins_cost(300);
10174
10175 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
10176 "jlt done\n\t"
10177 "xorl $y, $y\n"
10178 "done: " %}
10179 ins_encode %{
10180 Register Rp = $p$$Register;
10181 Register Rq = $q$$Register;
10182 Register Ry = $y$$Register;
10183 Label done;
10184 __ cmpl(Rp, Rq);
10185 __ jccb(Assembler::less, done);
10186 __ xorl(Ry, Ry);
10187 __ bind(done);
10188 %}
10189 ins_pipe(pipe_cmplt);
10190 %}
10191
10192
10193 //---------- FP Instructions------------------------------------------------
10194
10195 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10196 %{
10197 match(Set cr (CmpF src1 src2));
10198
10199 ins_cost(145);
10200 format %{ "ucomiss $src1, $src2\n\t"
10201 "jnp,s exit\n\t"
10202 "pushfq\t# saw NaN, set CF\n\t"
10203 "andq [rsp], #0xffffff2b\n\t"
10204 "popfq\n"
10205 "exit:" %}
10206 ins_encode %{
10207 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10208 emit_cmpfp_fixup(_masm);
10209 %}
10210 ins_pipe(pipe_slow);
10211 %}
10212
10213 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10214 match(Set cr (CmpF src1 src2));
10215
10216 ins_cost(100);
10217 format %{ "ucomiss $src1, $src2" %}
10218 ins_encode %{
10219 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10220 %}
10221 ins_pipe(pipe_slow);
10222 %}
10223
10224 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10225 %{
10226 match(Set cr (CmpF src1 (LoadF src2)));
10227
10228 ins_cost(145);
10229 format %{ "ucomiss $src1, $src2\n\t"
10230 "jnp,s exit\n\t"
10231 "pushfq\t# saw NaN, set CF\n\t"
10232 "andq [rsp], #0xffffff2b\n\t"
10233 "popfq\n"
10234 "exit:" %}
10235 ins_encode %{
10236 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10237 emit_cmpfp_fixup(_masm);
10238 %}
10239 ins_pipe(pipe_slow);
10240 %}
10241
10242 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10243 match(Set cr (CmpF src1 (LoadF src2)));
10244
10245 ins_cost(100);
10246 format %{ "ucomiss $src1, $src2" %}
10247 ins_encode %{
10248 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10249 %}
10250 ins_pipe(pipe_slow);
10251 %}
10252
10253 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10254 match(Set cr (CmpF src con));
10255
10256 ins_cost(145);
10257 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10258 "jnp,s exit\n\t"
10259 "pushfq\t# saw NaN, set CF\n\t"
10260 "andq [rsp], #0xffffff2b\n\t"
10261 "popfq\n"
10262 "exit:" %}
10263 ins_encode %{
10264 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10265 emit_cmpfp_fixup(_masm);
10266 %}
10267 ins_pipe(pipe_slow);
10268 %}
10269
10270 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10271 match(Set cr (CmpF src con));
10272 ins_cost(100);
10273 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10274 ins_encode %{
10275 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10276 %}
10277 ins_pipe(pipe_slow);
10278 %}
10279
10280 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10281 %{
10282 match(Set cr (CmpD src1 src2));
10283
10284 ins_cost(145);
10285 format %{ "ucomisd $src1, $src2\n\t"
10286 "jnp,s exit\n\t"
10287 "pushfq\t# saw NaN, set CF\n\t"
10288 "andq [rsp], #0xffffff2b\n\t"
10289 "popfq\n"
10290 "exit:" %}
10291 ins_encode %{
10292 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10293 emit_cmpfp_fixup(_masm);
10294 %}
10295 ins_pipe(pipe_slow);
10296 %}
10297
10298 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10299 match(Set cr (CmpD src1 src2));
10300
10301 ins_cost(100);
10302 format %{ "ucomisd $src1, $src2 test" %}
10303 ins_encode %{
10304 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10305 %}
10306 ins_pipe(pipe_slow);
10307 %}
10308
10309 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10310 %{
10311 match(Set cr (CmpD src1 (LoadD src2)));
10312
10313 ins_cost(145);
10314 format %{ "ucomisd $src1, $src2\n\t"
10315 "jnp,s exit\n\t"
10316 "pushfq\t# saw NaN, set CF\n\t"
10317 "andq [rsp], #0xffffff2b\n\t"
10318 "popfq\n"
10319 "exit:" %}
10320 ins_encode %{
10321 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10322 emit_cmpfp_fixup(_masm);
10323 %}
10324 ins_pipe(pipe_slow);
10325 %}
10326
10327 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10328 match(Set cr (CmpD src1 (LoadD src2)));
10329
10330 ins_cost(100);
10331 format %{ "ucomisd $src1, $src2" %}
10332 ins_encode %{
10333 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10334 %}
10335 ins_pipe(pipe_slow);
10336 %}
10337
10338 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10339 match(Set cr (CmpD src con));
10340
10341 ins_cost(145);
10342 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10343 "jnp,s exit\n\t"
10344 "pushfq\t# saw NaN, set CF\n\t"
10345 "andq [rsp], #0xffffff2b\n\t"
10346 "popfq\n"
10347 "exit:" %}
10348 ins_encode %{
10349 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10350 emit_cmpfp_fixup(_masm);
10351 %}
10352 ins_pipe(pipe_slow);
10353 %}
10354
10355 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10356 match(Set cr (CmpD src con));
10357 ins_cost(100);
10358 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10359 ins_encode %{
10360 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10361 %}
10362 ins_pipe(pipe_slow);
10363 %}
10364
10365 // Compare into -1,0,1
10366 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10367 %{
10368 match(Set dst (CmpF3 src1 src2));
10369 effect(KILL cr);
10370
10371 ins_cost(275);
10372 format %{ "ucomiss $src1, $src2\n\t"
10373 "movl $dst, #-1\n\t"
10374 "jp,s done\n\t"
10375 "jb,s done\n\t"
10376 "setne $dst\n\t"
10377 "movzbl $dst, $dst\n"
10378 "done:" %}
10379 ins_encode %{
10380 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10381 emit_cmpfp3(_masm, $dst$$Register);
10382 %}
10383 ins_pipe(pipe_slow);
10384 %}
10385
10386 // Compare into -1,0,1
10387 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10388 %{
10389 match(Set dst (CmpF3 src1 (LoadF src2)));
10390 effect(KILL cr);
10391
10392 ins_cost(275);
10393 format %{ "ucomiss $src1, $src2\n\t"
10394 "movl $dst, #-1\n\t"
10395 "jp,s done\n\t"
10396 "jb,s done\n\t"
10397 "setne $dst\n\t"
10398 "movzbl $dst, $dst\n"
10399 "done:" %}
10400 ins_encode %{
10401 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10402 emit_cmpfp3(_masm, $dst$$Register);
10403 %}
10404 ins_pipe(pipe_slow);
10405 %}
10406
10407 // Compare into -1,0,1
10408 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10409 match(Set dst (CmpF3 src con));
10410 effect(KILL cr);
10411
10412 ins_cost(275);
10413 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10414 "movl $dst, #-1\n\t"
10415 "jp,s done\n\t"
10416 "jb,s done\n\t"
10417 "setne $dst\n\t"
10418 "movzbl $dst, $dst\n"
10419 "done:" %}
10420 ins_encode %{
10421 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10422 emit_cmpfp3(_masm, $dst$$Register);
10423 %}
10424 ins_pipe(pipe_slow);
10425 %}
10426
10427 // Compare into -1,0,1
10428 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10429 %{
10430 match(Set dst (CmpD3 src1 src2));
10431 effect(KILL cr);
10432
10433 ins_cost(275);
10434 format %{ "ucomisd $src1, $src2\n\t"
10435 "movl $dst, #-1\n\t"
10436 "jp,s done\n\t"
10437 "jb,s done\n\t"
10438 "setne $dst\n\t"
10439 "movzbl $dst, $dst\n"
10440 "done:" %}
10441 ins_encode %{
10442 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10443 emit_cmpfp3(_masm, $dst$$Register);
10444 %}
10445 ins_pipe(pipe_slow);
10446 %}
10447
10448 // Compare into -1,0,1
10449 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10450 %{
10451 match(Set dst (CmpD3 src1 (LoadD src2)));
10452 effect(KILL cr);
10453
10454 ins_cost(275);
10455 format %{ "ucomisd $src1, $src2\n\t"
10456 "movl $dst, #-1\n\t"
10457 "jp,s done\n\t"
10458 "jb,s done\n\t"
10459 "setne $dst\n\t"
10460 "movzbl $dst, $dst\n"
10461 "done:" %}
10462 ins_encode %{
10463 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10464 emit_cmpfp3(_masm, $dst$$Register);
10465 %}
10466 ins_pipe(pipe_slow);
10467 %}
10468
10469 // Compare into -1,0,1
10470 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10471 match(Set dst (CmpD3 src con));
10472 effect(KILL cr);
10473
10474 ins_cost(275);
10475 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10476 "movl $dst, #-1\n\t"
10477 "jp,s done\n\t"
10478 "jb,s done\n\t"
10479 "setne $dst\n\t"
10480 "movzbl $dst, $dst\n"
10481 "done:" %}
10482 ins_encode %{
10483 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10484 emit_cmpfp3(_masm, $dst$$Register);
10485 %}
10486 ins_pipe(pipe_slow);
10487 %}
10488
10489 //----------Arithmetic Conversion Instructions---------------------------------
10490
10491 instruct roundFloat_nop(regF dst)
10492 %{
10493 match(Set dst (RoundFloat dst));
10494
10495 ins_cost(0);
10496 ins_encode();
10497 ins_pipe(empty);
10498 %}
10499
10500 instruct roundDouble_nop(regD dst)
10501 %{
10502 match(Set dst (RoundDouble dst));
10503
10504 ins_cost(0);
10505 ins_encode();
10506 ins_pipe(empty);
10507 %}
10508
10509 instruct convF2D_reg_reg(regD dst, regF src)
10510 %{
10511 match(Set dst (ConvF2D src));
10512
10513 format %{ "cvtss2sd $dst, $src" %}
10514 ins_encode %{
10515 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10516 %}
10517 ins_pipe(pipe_slow); // XXX
10518 %}
10519
10520 instruct convF2D_reg_mem(regD dst, memory src)
10521 %{
10522 match(Set dst (ConvF2D (LoadF src)));
10523
10524 format %{ "cvtss2sd $dst, $src" %}
10525 ins_encode %{
10526 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10527 %}
10528 ins_pipe(pipe_slow); // XXX
10529 %}
10530
10531 instruct convD2F_reg_reg(regF dst, regD src)
10532 %{
10533 match(Set dst (ConvD2F src));
10534
10535 format %{ "cvtsd2ss $dst, $src" %}
10536 ins_encode %{
10537 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10538 %}
10539 ins_pipe(pipe_slow); // XXX
10540 %}
10541
10542 instruct convD2F_reg_mem(regF dst, memory src)
10543 %{
10544 match(Set dst (ConvD2F (LoadD src)));
10545
10546 format %{ "cvtsd2ss $dst, $src" %}
10547 ins_encode %{
10548 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10549 %}
10550 ins_pipe(pipe_slow); // XXX
10551 %}
10552
10553 // XXX do mem variants
10554 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10555 %{
10556 match(Set dst (ConvF2I src));
10557 effect(KILL cr);
10558
10559 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10560 "cmpl $dst, #0x80000000\n\t"
10561 "jne,s done\n\t"
10562 "subq rsp, #8\n\t"
10563 "movss [rsp], $src\n\t"
10564 "call f2i_fixup\n\t"
10565 "popq $dst\n"
10566 "done: "%}
10567 ins_encode %{
10568 Label done;
10569 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10570 __ cmpl($dst$$Register, 0x80000000);
10571 __ jccb(Assembler::notEqual, done);
10572 __ subptr(rsp, 8);
10573 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10574 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10575 __ pop($dst$$Register);
10576 __ bind(done);
10577 %}
10578 ins_pipe(pipe_slow);
10579 %}
10580
10581 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10582 %{
10583 match(Set dst (ConvF2L src));
10584 effect(KILL cr);
10585
10586 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10587 "cmpq $dst, [0x8000000000000000]\n\t"
10588 "jne,s done\n\t"
10589 "subq rsp, #8\n\t"
10590 "movss [rsp], $src\n\t"
10591 "call f2l_fixup\n\t"
10592 "popq $dst\n"
10593 "done: "%}
10594 ins_encode %{
10595 Label done;
10596 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10597 __ cmp64($dst$$Register,
10598 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10599 __ jccb(Assembler::notEqual, done);
10600 __ subptr(rsp, 8);
10601 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10602 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10603 __ pop($dst$$Register);
10604 __ bind(done);
10605 %}
10606 ins_pipe(pipe_slow);
10607 %}
10608
10609 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10610 %{
10611 match(Set dst (ConvD2I src));
10612 effect(KILL cr);
10613
10614 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10615 "cmpl $dst, #0x80000000\n\t"
10616 "jne,s done\n\t"
10617 "subq rsp, #8\n\t"
10618 "movsd [rsp], $src\n\t"
10619 "call d2i_fixup\n\t"
10620 "popq $dst\n"
10621 "done: "%}
10622 ins_encode %{
10623 Label done;
10624 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10625 __ cmpl($dst$$Register, 0x80000000);
10626 __ jccb(Assembler::notEqual, done);
10627 __ subptr(rsp, 8);
10628 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10629 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10630 __ pop($dst$$Register);
10631 __ bind(done);
10632 %}
10633 ins_pipe(pipe_slow);
10634 %}
10635
10636 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10637 %{
10638 match(Set dst (ConvD2L src));
10639 effect(KILL cr);
10640
10641 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10642 "cmpq $dst, [0x8000000000000000]\n\t"
10643 "jne,s done\n\t"
10644 "subq rsp, #8\n\t"
10645 "movsd [rsp], $src\n\t"
10646 "call d2l_fixup\n\t"
10647 "popq $dst\n"
10648 "done: "%}
10649 ins_encode %{
10650 Label done;
10651 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10652 __ cmp64($dst$$Register,
10653 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10654 __ jccb(Assembler::notEqual, done);
10655 __ subptr(rsp, 8);
10656 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10657 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10658 __ pop($dst$$Register);
10659 __ bind(done);
10660 %}
10661 ins_pipe(pipe_slow);
10662 %}
10663
10664 instruct convI2F_reg_reg(regF dst, rRegI src)
10665 %{
10666 predicate(!UseXmmI2F);
10667 match(Set dst (ConvI2F src));
10668
10669 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10670 ins_encode %{
10671 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10672 %}
10673 ins_pipe(pipe_slow); // XXX
10674 %}
10675
10676 instruct convI2F_reg_mem(regF dst, memory src)
10677 %{
10678 match(Set dst (ConvI2F (LoadI src)));
10679
10680 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10681 ins_encode %{
10682 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10683 %}
10684 ins_pipe(pipe_slow); // XXX
10685 %}
10686
10687 instruct convI2D_reg_reg(regD dst, rRegI src)
10688 %{
10689 predicate(!UseXmmI2D);
10690 match(Set dst (ConvI2D src));
10691
10692 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10693 ins_encode %{
10694 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10695 %}
10696 ins_pipe(pipe_slow); // XXX
10697 %}
10698
10699 instruct convI2D_reg_mem(regD dst, memory src)
10700 %{
10701 match(Set dst (ConvI2D (LoadI src)));
10702
10703 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10704 ins_encode %{
10705 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10706 %}
10707 ins_pipe(pipe_slow); // XXX
10708 %}
10709
10710 instruct convXI2F_reg(regF dst, rRegI src)
10711 %{
10712 predicate(UseXmmI2F);
10713 match(Set dst (ConvI2F src));
10714
10715 format %{ "movdl $dst, $src\n\t"
10716 "cvtdq2psl $dst, $dst\t# i2f" %}
10717 ins_encode %{
10718 __ movdl($dst$$XMMRegister, $src$$Register);
10719 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10720 %}
10721 ins_pipe(pipe_slow); // XXX
10722 %}
10723
10724 instruct convXI2D_reg(regD dst, rRegI src)
10725 %{
10726 predicate(UseXmmI2D);
10727 match(Set dst (ConvI2D src));
10728
10729 format %{ "movdl $dst, $src\n\t"
10730 "cvtdq2pdl $dst, $dst\t# i2d" %}
10731 ins_encode %{
10732 __ movdl($dst$$XMMRegister, $src$$Register);
10733 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10734 %}
10735 ins_pipe(pipe_slow); // XXX
10736 %}
10737
10738 instruct convL2F_reg_reg(regF dst, rRegL src)
10739 %{
10740 match(Set dst (ConvL2F src));
10741
10742 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10743 ins_encode %{
10744 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10745 %}
10746 ins_pipe(pipe_slow); // XXX
10747 %}
10748
10749 instruct convL2F_reg_mem(regF dst, memory src)
10750 %{
10751 match(Set dst (ConvL2F (LoadL src)));
10752
10753 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10754 ins_encode %{
10755 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10756 %}
10757 ins_pipe(pipe_slow); // XXX
10758 %}
10759
10760 instruct convL2D_reg_reg(regD dst, rRegL src)
10761 %{
10762 match(Set dst (ConvL2D src));
10763
10764 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10765 ins_encode %{
10766 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10767 %}
10768 ins_pipe(pipe_slow); // XXX
10769 %}
10770
10771 instruct convL2D_reg_mem(regD dst, memory src)
10772 %{
10773 match(Set dst (ConvL2D (LoadL src)));
10774
10775 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10776 ins_encode %{
10777 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10778 %}
10779 ins_pipe(pipe_slow); // XXX
10780 %}
10781
10782 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10783 %{
10784 match(Set dst (ConvI2L src));
10785
10786 ins_cost(125);
10787 format %{ "movslq $dst, $src\t# i2l" %}
10788 ins_encode %{
10789 __ movslq($dst$$Register, $src$$Register);
10790 %}
10791 ins_pipe(ialu_reg_reg);
10792 %}
10793
10794 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10795 // %{
10796 // match(Set dst (ConvI2L src));
10797 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10798 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10799 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10800 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10801 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10802 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10803
10804 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10805 // ins_encode(enc_copy(dst, src));
10806 // // opcode(0x63); // needs REX.W
10807 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10808 // ins_pipe(ialu_reg_reg);
10809 // %}
10810
10811 // Zero-extend convert int to long
10812 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10813 %{
10814 match(Set dst (AndL (ConvI2L src) mask));
10815
10816 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10817 ins_encode %{
10818 if ($dst$$reg != $src$$reg) {
10819 __ movl($dst$$Register, $src$$Register);
10820 }
10821 %}
10822 ins_pipe(ialu_reg_reg);
10823 %}
10824
10825 // Zero-extend convert int to long
10826 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10827 %{
10828 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10829
10830 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10831 ins_encode %{
10832 __ movl($dst$$Register, $src$$Address);
10833 %}
10834 ins_pipe(ialu_reg_mem);
10835 %}
10836
10837 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10838 %{
10839 match(Set dst (AndL src mask));
10840
10841 format %{ "movl $dst, $src\t# zero-extend long" %}
10842 ins_encode %{
10843 __ movl($dst$$Register, $src$$Register);
10844 %}
10845 ins_pipe(ialu_reg_reg);
10846 %}
10847
10848 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10849 %{
10850 match(Set dst (ConvL2I src));
10851
10852 format %{ "movl $dst, $src\t# l2i" %}
10853 ins_encode %{
10854 __ movl($dst$$Register, $src$$Register);
10855 %}
10856 ins_pipe(ialu_reg_reg);
10857 %}
10858
10859
10860 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10861 match(Set dst (MoveF2I src));
10862 effect(DEF dst, USE src);
10863
10864 ins_cost(125);
10865 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10866 ins_encode %{
10867 __ movl($dst$$Register, Address(rsp, $src$$disp));
10868 %}
10869 ins_pipe(ialu_reg_mem);
10870 %}
10871
10872 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10873 match(Set dst (MoveI2F src));
10874 effect(DEF dst, USE src);
10875
10876 ins_cost(125);
10877 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10878 ins_encode %{
10879 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10880 %}
10881 ins_pipe(pipe_slow);
10882 %}
10883
10884 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10885 match(Set dst (MoveD2L src));
10886 effect(DEF dst, USE src);
10887
10888 ins_cost(125);
10889 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10890 ins_encode %{
10891 __ movq($dst$$Register, Address(rsp, $src$$disp));
10892 %}
10893 ins_pipe(ialu_reg_mem);
10894 %}
10895
10896 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10897 predicate(!UseXmmLoadAndClearUpper);
10898 match(Set dst (MoveL2D src));
10899 effect(DEF dst, USE src);
10900
10901 ins_cost(125);
10902 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10903 ins_encode %{
10904 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10905 %}
10906 ins_pipe(pipe_slow);
10907 %}
10908
10909 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10910 predicate(UseXmmLoadAndClearUpper);
10911 match(Set dst (MoveL2D src));
10912 effect(DEF dst, USE src);
10913
10914 ins_cost(125);
10915 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10916 ins_encode %{
10917 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10918 %}
10919 ins_pipe(pipe_slow);
10920 %}
10921
10922
10923 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10924 match(Set dst (MoveF2I src));
10925 effect(DEF dst, USE src);
10926
10927 ins_cost(95); // XXX
10928 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10929 ins_encode %{
10930 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10931 %}
10932 ins_pipe(pipe_slow);
10933 %}
10934
10935 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10936 match(Set dst (MoveI2F src));
10937 effect(DEF dst, USE src);
10938
10939 ins_cost(100);
10940 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10941 ins_encode %{
10942 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10943 %}
10944 ins_pipe( ialu_mem_reg );
10945 %}
10946
10947 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10948 match(Set dst (MoveD2L src));
10949 effect(DEF dst, USE src);
10950
10951 ins_cost(95); // XXX
10952 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10953 ins_encode %{
10954 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10955 %}
10956 ins_pipe(pipe_slow);
10957 %}
10958
10959 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10960 match(Set dst (MoveL2D src));
10961 effect(DEF dst, USE src);
10962
10963 ins_cost(100);
10964 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10965 ins_encode %{
10966 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10967 %}
10968 ins_pipe(ialu_mem_reg);
10969 %}
10970
10971 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10972 match(Set dst (MoveF2I src));
10973 effect(DEF dst, USE src);
10974 ins_cost(85);
10975 format %{ "movd $dst,$src\t# MoveF2I" %}
10976 ins_encode %{
10977 __ movdl($dst$$Register, $src$$XMMRegister);
10978 %}
10979 ins_pipe( pipe_slow );
10980 %}
10981
10982 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10983 match(Set dst (MoveD2L src));
10984 effect(DEF dst, USE src);
10985 ins_cost(85);
10986 format %{ "movd $dst,$src\t# MoveD2L" %}
10987 ins_encode %{
10988 __ movdq($dst$$Register, $src$$XMMRegister);
10989 %}
10990 ins_pipe( pipe_slow );
10991 %}
10992
10993 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10994 match(Set dst (MoveI2F src));
10995 effect(DEF dst, USE src);
10996 ins_cost(100);
10997 format %{ "movd $dst,$src\t# MoveI2F" %}
10998 ins_encode %{
10999 __ movdl($dst$$XMMRegister, $src$$Register);
11000 %}
11001 ins_pipe( pipe_slow );
11002 %}
11003
11004 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
11005 match(Set dst (MoveL2D src));
11006 effect(DEF dst, USE src);
11007 ins_cost(100);
11008 format %{ "movd $dst,$src\t# MoveL2D" %}
11009 ins_encode %{
11010 __ movdq($dst$$XMMRegister, $src$$Register);
11011 %}
11012 ins_pipe( pipe_slow );
11013 %}
11014
11015
11016 // =======================================================================
11017 // fast clearing of an array
11018 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11019 Universe dummy, rFlagsReg cr)
11020 %{
11021 predicate(!((ClearArrayNode*)n)->is_large());
11022 match(Set dummy (ClearArray cnt base));
11023 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11024
11025 format %{ $$template
11026 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11027 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
11028 $$emit$$"jg LARGE\n\t"
11029 $$emit$$"dec rcx\n\t"
11030 $$emit$$"js DONE\t# Zero length\n\t"
11031 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
11032 $$emit$$"dec rcx\n\t"
11033 $$emit$$"jge LOOP\n\t"
11034 $$emit$$"jmp DONE\n\t"
11035 $$emit$$"# LARGE:\n\t"
11036 if (UseFastStosb) {
11037 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11038 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
11039 } else if (UseXMMForObjInit) {
11040 $$emit$$"mov rdi,rax\n\t"
11041 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11042 $$emit$$"jmpq L_zero_64_bytes\n\t"
11043 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11044 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11045 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11046 $$emit$$"add 0x40,rax\n\t"
11047 $$emit$$"# L_zero_64_bytes:\n\t"
11048 $$emit$$"sub 0x8,rcx\n\t"
11049 $$emit$$"jge L_loop\n\t"
11050 $$emit$$"add 0x4,rcx\n\t"
11051 $$emit$$"jl L_tail\n\t"
11052 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11053 $$emit$$"add 0x20,rax\n\t"
11054 $$emit$$"sub 0x4,rcx\n\t"
11055 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11056 $$emit$$"add 0x4,rcx\n\t"
11057 $$emit$$"jle L_end\n\t"
11058 $$emit$$"dec rcx\n\t"
11059 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11060 $$emit$$"vmovq xmm0,(rax)\n\t"
11061 $$emit$$"add 0x8,rax\n\t"
11062 $$emit$$"dec rcx\n\t"
11063 $$emit$$"jge L_sloop\n\t"
11064 $$emit$$"# L_end:\n\t"
11065 } else {
11066 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
11067 }
11068 $$emit$$"# DONE"
11069 %}
11070 ins_encode %{
11071 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11072 $tmp$$XMMRegister, false);
11073 %}
11074 ins_pipe(pipe_slow);
11075 %}
11076
11077 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11078 Universe dummy, rFlagsReg cr)
11079 %{
11080 predicate(((ClearArrayNode*)n)->is_large());
11081 match(Set dummy (ClearArray cnt base));
11082 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11083
11084 format %{ $$template
11085 if (UseFastStosb) {
11086 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11087 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11088 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
11089 } else if (UseXMMForObjInit) {
11090 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
11091 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11092 $$emit$$"jmpq L_zero_64_bytes\n\t"
11093 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11094 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11095 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11096 $$emit$$"add 0x40,rax\n\t"
11097 $$emit$$"# L_zero_64_bytes:\n\t"
11098 $$emit$$"sub 0x8,rcx\n\t"
11099 $$emit$$"jge L_loop\n\t"
11100 $$emit$$"add 0x4,rcx\n\t"
11101 $$emit$$"jl L_tail\n\t"
11102 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11103 $$emit$$"add 0x20,rax\n\t"
11104 $$emit$$"sub 0x4,rcx\n\t"
11105 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11106 $$emit$$"add 0x4,rcx\n\t"
11107 $$emit$$"jle L_end\n\t"
11108 $$emit$$"dec rcx\n\t"
11109 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11110 $$emit$$"vmovq xmm0,(rax)\n\t"
11111 $$emit$$"add 0x8,rax\n\t"
11112 $$emit$$"dec rcx\n\t"
11113 $$emit$$"jge L_sloop\n\t"
11114 $$emit$$"# L_end:\n\t"
11115 } else {
11116 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11117 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
11118 }
11119 %}
11120 ins_encode %{
11121 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11122 $tmp$$XMMRegister, true);
11123 %}
11124 ins_pipe(pipe_slow);
11125 %}
11126
11127 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11128 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11129 %{
11130 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11131 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11132 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11133
11134 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11135 ins_encode %{
11136 __ string_compare($str1$$Register, $str2$$Register,
11137 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11138 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
11139 %}
11140 ins_pipe( pipe_slow );
11141 %}
11142
11143 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11144 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11145 %{
11146 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11147 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11148 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11149
11150 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11151 ins_encode %{
11152 __ string_compare($str1$$Register, $str2$$Register,
11153 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11154 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
11155 %}
11156 ins_pipe( pipe_slow );
11157 %}
11158
11159 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11160 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11161 %{
11162 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11163 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11164 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11165
11166 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11167 ins_encode %{
11168 __ string_compare($str1$$Register, $str2$$Register,
11169 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11170 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
11171 %}
11172 ins_pipe( pipe_slow );
11173 %}
11174
11175 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11176 rax_RegI result, legVecS tmp1, rFlagsReg cr)
11177 %{
11178 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11179 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11180 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11181
11182 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11183 ins_encode %{
11184 __ string_compare($str2$$Register, $str1$$Register,
11185 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11186 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
11187 %}
11188 ins_pipe( pipe_slow );
11189 %}
11190
11191 // fast search of substring with known size.
11192 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11193 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11194 %{
11195 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11196 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11197 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11198
11199 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11200 ins_encode %{
11201 int icnt2 = (int)$int_cnt2$$constant;
11202 if (icnt2 >= 16) {
11203 // IndexOf for constant substrings with size >= 16 elements
11204 // which don't need to be loaded through stack.
11205 __ string_indexofC8($str1$$Register, $str2$$Register,
11206 $cnt1$$Register, $cnt2$$Register,
11207 icnt2, $result$$Register,
11208 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11209 } else {
11210 // Small strings are loaded through stack if they cross page boundary.
11211 __ string_indexof($str1$$Register, $str2$$Register,
11212 $cnt1$$Register, $cnt2$$Register,
11213 icnt2, $result$$Register,
11214 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11215 }
11216 %}
11217 ins_pipe( pipe_slow );
11218 %}
11219
11220 // fast search of substring with known size.
11221 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11222 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11223 %{
11224 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11225 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11226 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11227
11228 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11229 ins_encode %{
11230 int icnt2 = (int)$int_cnt2$$constant;
11231 if (icnt2 >= 8) {
11232 // IndexOf for constant substrings with size >= 8 elements
11233 // which don't need to be loaded through stack.
11234 __ string_indexofC8($str1$$Register, $str2$$Register,
11235 $cnt1$$Register, $cnt2$$Register,
11236 icnt2, $result$$Register,
11237 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11238 } else {
11239 // Small strings are loaded through stack if they cross page boundary.
11240 __ string_indexof($str1$$Register, $str2$$Register,
11241 $cnt1$$Register, $cnt2$$Register,
11242 icnt2, $result$$Register,
11243 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11244 }
11245 %}
11246 ins_pipe( pipe_slow );
11247 %}
11248
11249 // fast search of substring with known size.
11250 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11251 rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11252 %{
11253 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11254 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11255 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11256
11257 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11258 ins_encode %{
11259 int icnt2 = (int)$int_cnt2$$constant;
11260 if (icnt2 >= 8) {
11261 // IndexOf for constant substrings with size >= 8 elements
11262 // which don't need to be loaded through stack.
11263 __ string_indexofC8($str1$$Register, $str2$$Register,
11264 $cnt1$$Register, $cnt2$$Register,
11265 icnt2, $result$$Register,
11266 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11267 } else {
11268 // Small strings are loaded through stack if they cross page boundary.
11269 __ string_indexof($str1$$Register, $str2$$Register,
11270 $cnt1$$Register, $cnt2$$Register,
11271 icnt2, $result$$Register,
11272 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11273 }
11274 %}
11275 ins_pipe( pipe_slow );
11276 %}
11277
11278 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11279 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11280 %{
11281 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11282 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11283 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11284
11285 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11286 ins_encode %{
11287 __ string_indexof($str1$$Register, $str2$$Register,
11288 $cnt1$$Register, $cnt2$$Register,
11289 (-1), $result$$Register,
11290 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11291 %}
11292 ins_pipe( pipe_slow );
11293 %}
11294
11295 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11296 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11297 %{
11298 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11299 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11300 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11301
11302 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11303 ins_encode %{
11304 __ string_indexof($str1$$Register, $str2$$Register,
11305 $cnt1$$Register, $cnt2$$Register,
11306 (-1), $result$$Register,
11307 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11308 %}
11309 ins_pipe( pipe_slow );
11310 %}
11311
11312 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11313 rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11314 %{
11315 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11316 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11317 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11318
11319 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11320 ins_encode %{
11321 __ string_indexof($str1$$Register, $str2$$Register,
11322 $cnt1$$Register, $cnt2$$Register,
11323 (-1), $result$$Register,
11324 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11325 %}
11326 ins_pipe( pipe_slow );
11327 %}
11328
11329 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11330 rbx_RegI result, legVecS vec1, legVecS vec2, legVecS vec3, rcx_RegI tmp, rFlagsReg cr)
11331 %{
11332 predicate(UseSSE42Intrinsics);
11333 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11334 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11335 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11336 ins_encode %{
11337 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11338 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
11339 %}
11340 ins_pipe( pipe_slow );
11341 %}
11342
11343 // fast string equals
11344 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11345 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11346 %{
11347 match(Set result (StrEquals (Binary str1 str2) cnt));
11348 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11349
11350 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11351 ins_encode %{
11352 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11353 $cnt$$Register, $result$$Register, $tmp3$$Register,
11354 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11355 %}
11356 ins_pipe( pipe_slow );
11357 %}
11358
11359 // fast array equals
11360 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11361 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11362 %{
11363 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11364 match(Set result (AryEq ary1 ary2));
11365 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11366
11367 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11368 ins_encode %{
11369 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11370 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11371 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11372 %}
11373 ins_pipe( pipe_slow );
11374 %}
11375
11376 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11377 legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11378 %{
11379 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11380 match(Set result (AryEq ary1 ary2));
11381 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11382
11383 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11384 ins_encode %{
11385 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11386 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11387 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
11388 %}
11389 ins_pipe( pipe_slow );
11390 %}
11391
11392 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11393 legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11394 %{
11395 match(Set result (HasNegatives ary1 len));
11396 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11397
11398 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11399 ins_encode %{
11400 __ has_negatives($ary1$$Register, $len$$Register,
11401 $result$$Register, $tmp3$$Register,
11402 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11403 %}
11404 ins_pipe( pipe_slow );
11405 %}
11406
11407 // fast char[] to byte[] compression
11408 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11409 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11410 match(Set result (StrCompressedCopy src (Binary dst len)));
11411 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11412
11413 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11414 ins_encode %{
11415 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11416 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11417 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11418 %}
11419 ins_pipe( pipe_slow );
11420 %}
11421
11422 // fast byte[] to char[] inflation
11423 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11424 legVecS tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11425 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11426 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11427
11428 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11429 ins_encode %{
11430 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11431 $tmp1$$XMMRegister, $tmp2$$Register);
11432 %}
11433 ins_pipe( pipe_slow );
11434 %}
11435
11436 // encode char[] to byte[] in ISO_8859_1
11437 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11438 legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11439 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11440 match(Set result (EncodeISOArray src (Binary dst len)));
11441 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11442
11443 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11444 ins_encode %{
11445 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11446 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11447 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11448 %}
11449 ins_pipe( pipe_slow );
11450 %}
11451
11452 //----------Overflow Math Instructions-----------------------------------------
11453
11454 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11455 %{
11456 match(Set cr (OverflowAddI op1 op2));
11457 effect(DEF cr, USE_KILL op1, USE op2);
11458
11459 format %{ "addl $op1, $op2\t# overflow check int" %}
11460
11461 ins_encode %{
11462 __ addl($op1$$Register, $op2$$Register);
11463 %}
11464 ins_pipe(ialu_reg_reg);
11465 %}
11466
11467 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11468 %{
11469 match(Set cr (OverflowAddI op1 op2));
11470 effect(DEF cr, USE_KILL op1, USE op2);
11471
11472 format %{ "addl $op1, $op2\t# overflow check int" %}
11473
11474 ins_encode %{
11475 __ addl($op1$$Register, $op2$$constant);
11476 %}
11477 ins_pipe(ialu_reg_reg);
11478 %}
11479
11480 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11481 %{
11482 match(Set cr (OverflowAddL op1 op2));
11483 effect(DEF cr, USE_KILL op1, USE op2);
11484
11485 format %{ "addq $op1, $op2\t# overflow check long" %}
11486 ins_encode %{
11487 __ addq($op1$$Register, $op2$$Register);
11488 %}
11489 ins_pipe(ialu_reg_reg);
11490 %}
11491
11492 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11493 %{
11494 match(Set cr (OverflowAddL op1 op2));
11495 effect(DEF cr, USE_KILL op1, USE op2);
11496
11497 format %{ "addq $op1, $op2\t# overflow check long" %}
11498 ins_encode %{
11499 __ addq($op1$$Register, $op2$$constant);
11500 %}
11501 ins_pipe(ialu_reg_reg);
11502 %}
11503
11504 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11505 %{
11506 match(Set cr (OverflowSubI op1 op2));
11507
11508 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11509 ins_encode %{
11510 __ cmpl($op1$$Register, $op2$$Register);
11511 %}
11512 ins_pipe(ialu_reg_reg);
11513 %}
11514
11515 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11516 %{
11517 match(Set cr (OverflowSubI op1 op2));
11518
11519 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11520 ins_encode %{
11521 __ cmpl($op1$$Register, $op2$$constant);
11522 %}
11523 ins_pipe(ialu_reg_reg);
11524 %}
11525
11526 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11527 %{
11528 match(Set cr (OverflowSubL op1 op2));
11529
11530 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11531 ins_encode %{
11532 __ cmpq($op1$$Register, $op2$$Register);
11533 %}
11534 ins_pipe(ialu_reg_reg);
11535 %}
11536
11537 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11538 %{
11539 match(Set cr (OverflowSubL op1 op2));
11540
11541 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11542 ins_encode %{
11543 __ cmpq($op1$$Register, $op2$$constant);
11544 %}
11545 ins_pipe(ialu_reg_reg);
11546 %}
11547
11548 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11549 %{
11550 match(Set cr (OverflowSubI zero op2));
11551 effect(DEF cr, USE_KILL op2);
11552
11553 format %{ "negl $op2\t# overflow check int" %}
11554 ins_encode %{
11555 __ negl($op2$$Register);
11556 %}
11557 ins_pipe(ialu_reg_reg);
11558 %}
11559
11560 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11561 %{
11562 match(Set cr (OverflowSubL zero op2));
11563 effect(DEF cr, USE_KILL op2);
11564
11565 format %{ "negq $op2\t# overflow check long" %}
11566 ins_encode %{
11567 __ negq($op2$$Register);
11568 %}
11569 ins_pipe(ialu_reg_reg);
11570 %}
11571
11572 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11573 %{
11574 match(Set cr (OverflowMulI op1 op2));
11575 effect(DEF cr, USE_KILL op1, USE op2);
11576
11577 format %{ "imull $op1, $op2\t# overflow check int" %}
11578 ins_encode %{
11579 __ imull($op1$$Register, $op2$$Register);
11580 %}
11581 ins_pipe(ialu_reg_reg_alu0);
11582 %}
11583
11584 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11585 %{
11586 match(Set cr (OverflowMulI op1 op2));
11587 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11588
11589 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11590 ins_encode %{
11591 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11592 %}
11593 ins_pipe(ialu_reg_reg_alu0);
11594 %}
11595
11596 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11597 %{
11598 match(Set cr (OverflowMulL op1 op2));
11599 effect(DEF cr, USE_KILL op1, USE op2);
11600
11601 format %{ "imulq $op1, $op2\t# overflow check long" %}
11602 ins_encode %{
11603 __ imulq($op1$$Register, $op2$$Register);
11604 %}
11605 ins_pipe(ialu_reg_reg_alu0);
11606 %}
11607
11608 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11609 %{
11610 match(Set cr (OverflowMulL op1 op2));
11611 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11612
11613 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11614 ins_encode %{
11615 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11616 %}
11617 ins_pipe(ialu_reg_reg_alu0);
11618 %}
11619
11620
11621 //----------Control Flow Instructions------------------------------------------
11622 // Signed compare Instructions
11623
11624 // XXX more variants!!
11625 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11626 %{
11627 match(Set cr (CmpI op1 op2));
11628 effect(DEF cr, USE op1, USE op2);
11629
11630 format %{ "cmpl $op1, $op2" %}
11631 opcode(0x3B); /* Opcode 3B /r */
11632 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11633 ins_pipe(ialu_cr_reg_reg);
11634 %}
11635
11636 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11637 %{
11638 match(Set cr (CmpI op1 op2));
11639
11640 format %{ "cmpl $op1, $op2" %}
11641 opcode(0x81, 0x07); /* Opcode 81 /7 */
11642 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11643 ins_pipe(ialu_cr_reg_imm);
11644 %}
11645
11646 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11647 %{
11648 match(Set cr (CmpI op1 (LoadI op2)));
11649
11650 ins_cost(500); // XXX
11651 format %{ "cmpl $op1, $op2" %}
11652 opcode(0x3B); /* Opcode 3B /r */
11653 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11654 ins_pipe(ialu_cr_reg_mem);
11655 %}
11656
11657 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11658 %{
11659 match(Set cr (CmpI src zero));
11660
11661 format %{ "testl $src, $src" %}
11662 opcode(0x85);
11663 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11664 ins_pipe(ialu_cr_reg_imm);
11665 %}
11666
11667 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11668 %{
11669 match(Set cr (CmpI (AndI src con) zero));
11670
11671 format %{ "testl $src, $con" %}
11672 opcode(0xF7, 0x00);
11673 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11674 ins_pipe(ialu_cr_reg_imm);
11675 %}
11676
11677 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11678 %{
11679 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11680
11681 format %{ "testl $src, $mem" %}
11682 opcode(0x85);
11683 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11684 ins_pipe(ialu_cr_reg_mem);
11685 %}
11686
11687 // Unsigned compare Instructions; really, same as signed except they
11688 // produce an rFlagsRegU instead of rFlagsReg.
11689 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11690 %{
11691 match(Set cr (CmpU op1 op2));
11692
11693 format %{ "cmpl $op1, $op2\t# unsigned" %}
11694 opcode(0x3B); /* Opcode 3B /r */
11695 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11696 ins_pipe(ialu_cr_reg_reg);
11697 %}
11698
11699 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11700 %{
11701 match(Set cr (CmpU op1 op2));
11702
11703 format %{ "cmpl $op1, $op2\t# unsigned" %}
11704 opcode(0x81,0x07); /* Opcode 81 /7 */
11705 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11706 ins_pipe(ialu_cr_reg_imm);
11707 %}
11708
11709 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11710 %{
11711 match(Set cr (CmpU op1 (LoadI op2)));
11712
11713 ins_cost(500); // XXX
11714 format %{ "cmpl $op1, $op2\t# unsigned" %}
11715 opcode(0x3B); /* Opcode 3B /r */
11716 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11717 ins_pipe(ialu_cr_reg_mem);
11718 %}
11719
11720 // // // Cisc-spilled version of cmpU_rReg
11721 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11722 // //%{
11723 // // match(Set cr (CmpU (LoadI op1) op2));
11724 // //
11725 // // format %{ "CMPu $op1,$op2" %}
11726 // // ins_cost(500);
11727 // // opcode(0x39); /* Opcode 39 /r */
11728 // // ins_encode( OpcP, reg_mem( op1, op2) );
11729 // //%}
11730
11731 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11732 %{
11733 match(Set cr (CmpU src zero));
11734
11735 format %{ "testl $src, $src\t# unsigned" %}
11736 opcode(0x85);
11737 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11738 ins_pipe(ialu_cr_reg_imm);
11739 %}
11740
11741 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11742 %{
11743 match(Set cr (CmpP op1 op2));
11744
11745 format %{ "cmpq $op1, $op2\t# ptr" %}
11746 opcode(0x3B); /* Opcode 3B /r */
11747 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11748 ins_pipe(ialu_cr_reg_reg);
11749 %}
11750
11751 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11752 %{
11753 match(Set cr (CmpP op1 (LoadP op2)));
11754
11755 ins_cost(500); // XXX
11756 format %{ "cmpq $op1, $op2\t# ptr" %}
11757 opcode(0x3B); /* Opcode 3B /r */
11758 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11759 ins_pipe(ialu_cr_reg_mem);
11760 %}
11761
11762 // // // Cisc-spilled version of cmpP_rReg
11763 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11764 // //%{
11765 // // match(Set cr (CmpP (LoadP op1) op2));
11766 // //
11767 // // format %{ "CMPu $op1,$op2" %}
11768 // // ins_cost(500);
11769 // // opcode(0x39); /* Opcode 39 /r */
11770 // // ins_encode( OpcP, reg_mem( op1, op2) );
11771 // //%}
11772
11773 // XXX this is generalized by compP_rReg_mem???
11774 // Compare raw pointer (used in out-of-heap check).
11775 // Only works because non-oop pointers must be raw pointers
11776 // and raw pointers have no anti-dependencies.
11777 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11778 %{
11779 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11780 match(Set cr (CmpP op1 (LoadP op2)));
11781
11782 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11783 opcode(0x3B); /* Opcode 3B /r */
11784 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11785 ins_pipe(ialu_cr_reg_mem);
11786 %}
11787
11788 // This will generate a signed flags result. This should be OK since
11789 // any compare to a zero should be eq/neq.
11790 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11791 %{
11792 match(Set cr (CmpP src zero));
11793
11794 format %{ "testq $src, $src\t# ptr" %}
11795 opcode(0x85);
11796 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11797 ins_pipe(ialu_cr_reg_imm);
11798 %}
11799
11800 // This will generate a signed flags result. This should be OK since
11801 // any compare to a zero should be eq/neq.
11802 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11803 %{
11804 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11805 match(Set cr (CmpP (LoadP op) zero));
11806
11807 ins_cost(500); // XXX
11808 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11809 opcode(0xF7); /* Opcode F7 /0 */
11810 ins_encode(REX_mem_wide(op),
11811 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11812 ins_pipe(ialu_cr_reg_imm);
11813 %}
11814
11815 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11816 %{
11817 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
11818 match(Set cr (CmpP (LoadP mem) zero));
11819
11820 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11821 ins_encode %{
11822 __ cmpq(r12, $mem$$Address);
11823 %}
11824 ins_pipe(ialu_cr_reg_mem);
11825 %}
11826
11827 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11828 %{
11829 match(Set cr (CmpN op1 op2));
11830
11831 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11832 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11833 ins_pipe(ialu_cr_reg_reg);
11834 %}
11835
11836 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11837 %{
11838 match(Set cr (CmpN src (LoadN mem)));
11839
11840 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11841 ins_encode %{
11842 __ cmpl($src$$Register, $mem$$Address);
11843 %}
11844 ins_pipe(ialu_cr_reg_mem);
11845 %}
11846
11847 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11848 match(Set cr (CmpN op1 op2));
11849
11850 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11851 ins_encode %{
11852 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11853 %}
11854 ins_pipe(ialu_cr_reg_imm);
11855 %}
11856
11857 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11858 %{
11859 match(Set cr (CmpN src (LoadN mem)));
11860
11861 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11862 ins_encode %{
11863 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11864 %}
11865 ins_pipe(ialu_cr_reg_mem);
11866 %}
11867
11868 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11869 match(Set cr (CmpN op1 op2));
11870
11871 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11872 ins_encode %{
11873 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11874 %}
11875 ins_pipe(ialu_cr_reg_imm);
11876 %}
11877
11878 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11879 %{
11880 match(Set cr (CmpN src (LoadNKlass mem)));
11881
11882 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11883 ins_encode %{
11884 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11885 %}
11886 ins_pipe(ialu_cr_reg_mem);
11887 %}
11888
11889 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11890 match(Set cr (CmpN src zero));
11891
11892 format %{ "testl $src, $src\t# compressed ptr" %}
11893 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11894 ins_pipe(ialu_cr_reg_imm);
11895 %}
11896
11897 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11898 %{
11899 predicate(Universe::narrow_oop_base() != NULL);
11900 match(Set cr (CmpN (LoadN mem) zero));
11901
11902 ins_cost(500); // XXX
11903 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11904 ins_encode %{
11905 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11906 %}
11907 ins_pipe(ialu_cr_reg_mem);
11908 %}
11909
11910 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11911 %{
11912 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
11913 match(Set cr (CmpN (LoadN mem) zero));
11914
11915 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11916 ins_encode %{
11917 __ cmpl(r12, $mem$$Address);
11918 %}
11919 ins_pipe(ialu_cr_reg_mem);
11920 %}
11921
11922 // Yanked all unsigned pointer compare operations.
11923 // Pointer compares are done with CmpP which is already unsigned.
11924
11925 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11926 %{
11927 match(Set cr (CmpL op1 op2));
11928
11929 format %{ "cmpq $op1, $op2" %}
11930 opcode(0x3B); /* Opcode 3B /r */
11931 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11932 ins_pipe(ialu_cr_reg_reg);
11933 %}
11934
11935 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11936 %{
11937 match(Set cr (CmpL op1 op2));
11938
11939 format %{ "cmpq $op1, $op2" %}
11940 opcode(0x81, 0x07); /* Opcode 81 /7 */
11941 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11942 ins_pipe(ialu_cr_reg_imm);
11943 %}
11944
11945 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11946 %{
11947 match(Set cr (CmpL op1 (LoadL op2)));
11948
11949 format %{ "cmpq $op1, $op2" %}
11950 opcode(0x3B); /* Opcode 3B /r */
11951 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11952 ins_pipe(ialu_cr_reg_mem);
11953 %}
11954
11955 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11956 %{
11957 match(Set cr (CmpL src zero));
11958
11959 format %{ "testq $src, $src" %}
11960 opcode(0x85);
11961 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11962 ins_pipe(ialu_cr_reg_imm);
11963 %}
11964
11965 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11966 %{
11967 match(Set cr (CmpL (AndL src con) zero));
11968
11969 format %{ "testq $src, $con\t# long" %}
11970 opcode(0xF7, 0x00);
11971 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11972 ins_pipe(ialu_cr_reg_imm);
11973 %}
11974
11975 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11976 %{
11977 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11978
11979 format %{ "testq $src, $mem" %}
11980 opcode(0x85);
11981 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11982 ins_pipe(ialu_cr_reg_mem);
11983 %}
11984
11985 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
11986 %{
11987 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
11988
11989 format %{ "testq $src, $mem" %}
11990 opcode(0x85);
11991 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11992 ins_pipe(ialu_cr_reg_mem);
11993 %}
11994
11995 // Manifest a CmpL result in an integer register. Very painful.
11996 // This is the test to avoid.
11997 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11998 %{
11999 match(Set dst (CmpL3 src1 src2));
12000 effect(KILL flags);
12001
12002 ins_cost(275); // XXX
12003 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12004 "movl $dst, -1\n\t"
12005 "jl,s done\n\t"
12006 "setne $dst\n\t"
12007 "movzbl $dst, $dst\n\t"
12008 "done:" %}
12009 ins_encode(cmpl3_flag(src1, src2, dst));
12010 ins_pipe(pipe_slow);
12011 %}
12012
12013 // Unsigned long compare Instructions; really, same as signed long except they
12014 // produce an rFlagsRegU instead of rFlagsReg.
12015 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
12016 %{
12017 match(Set cr (CmpUL op1 op2));
12018
12019 format %{ "cmpq $op1, $op2\t# unsigned" %}
12020 opcode(0x3B); /* Opcode 3B /r */
12021 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
12022 ins_pipe(ialu_cr_reg_reg);
12023 %}
12024
12025 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
12026 %{
12027 match(Set cr (CmpUL op1 op2));
12028
12029 format %{ "cmpq $op1, $op2\t# unsigned" %}
12030 opcode(0x81, 0x07); /* Opcode 81 /7 */
12031 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
12032 ins_pipe(ialu_cr_reg_imm);
12033 %}
12034
12035 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
12036 %{
12037 match(Set cr (CmpUL op1 (LoadL op2)));
12038
12039 format %{ "cmpq $op1, $op2\t# unsigned" %}
12040 opcode(0x3B); /* Opcode 3B /r */
12041 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
12042 ins_pipe(ialu_cr_reg_mem);
12043 %}
12044
12045 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
12046 %{
12047 match(Set cr (CmpUL src zero));
12048
12049 format %{ "testq $src, $src\t# unsigned" %}
12050 opcode(0x85);
12051 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12052 ins_pipe(ialu_cr_reg_imm);
12053 %}
12054
12055 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12056 %{
12057 match(Set cr (CmpI (LoadB mem) imm));
12058
12059 ins_cost(125);
12060 format %{ "cmpb $mem, $imm" %}
12061 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12062 ins_pipe(ialu_cr_reg_mem);
12063 %}
12064
12065 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI0 zero)
12066 %{
12067 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12068
12069 ins_cost(125);
12070 format %{ "testb $mem, $imm\t# ubyte" %}
12071 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12072 ins_pipe(ialu_cr_reg_mem);
12073 %}
12074
12075 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI0 zero)
12076 %{
12077 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12078
12079 ins_cost(125);
12080 format %{ "testb $mem, $imm\t# byte" %}
12081 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12082 ins_pipe(ialu_cr_reg_mem);
12083 %}
12084
12085 //----------Max and Min--------------------------------------------------------
12086 // Min Instructions
12087
12088 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12089 %{
12090 effect(USE_DEF dst, USE src, USE cr);
12091
12092 format %{ "cmovlgt $dst, $src\t# min" %}
12093 opcode(0x0F, 0x4F);
12094 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12095 ins_pipe(pipe_cmov_reg);
12096 %}
12097
12098
12099 instruct minI_rReg(rRegI dst, rRegI src)
12100 %{
12101 match(Set dst (MinI dst src));
12102
12103 ins_cost(200);
12104 expand %{
12105 rFlagsReg cr;
12106 compI_rReg(cr, dst, src);
12107 cmovI_reg_g(dst, src, cr);
12108 %}
12109 %}
12110
12111 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12112 %{
12113 effect(USE_DEF dst, USE src, USE cr);
12114
12115 format %{ "cmovllt $dst, $src\t# max" %}
12116 opcode(0x0F, 0x4C);
12117 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12118 ins_pipe(pipe_cmov_reg);
12119 %}
12120
12121
12122 instruct maxI_rReg(rRegI dst, rRegI src)
12123 %{
12124 match(Set dst (MaxI dst src));
12125
12126 ins_cost(200);
12127 expand %{
12128 rFlagsReg cr;
12129 compI_rReg(cr, dst, src);
12130 cmovI_reg_l(dst, src, cr);
12131 %}
12132 %}
12133
12134 // ============================================================================
12135 // Branch Instructions
12136
12137 // Jump Direct - Label defines a relative address from JMP+1
12138 instruct jmpDir(label labl)
12139 %{
12140 match(Goto);
12141 effect(USE labl);
12142
12143 ins_cost(300);
12144 format %{ "jmp $labl" %}
12145 size(5);
12146 ins_encode %{
12147 Label* L = $labl$$label;
12148 __ jmp(*L, false); // Always long jump
12149 %}
12150 ins_pipe(pipe_jmp);
12151 %}
12152
12153 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12154 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12155 %{
12156 match(If cop cr);
12157 effect(USE labl);
12158
12159 ins_cost(300);
12160 format %{ "j$cop $labl" %}
12161 size(6);
12162 ins_encode %{
12163 Label* L = $labl$$label;
12164 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12165 %}
12166 ins_pipe(pipe_jcc);
12167 %}
12168
12169 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12170 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12171 %{
12172 predicate(!n->has_vector_mask_set());
12173 match(CountedLoopEnd cop cr);
12174 effect(USE labl);
12175
12176 ins_cost(300);
12177 format %{ "j$cop $labl\t# loop end" %}
12178 size(6);
12179 ins_encode %{
12180 Label* L = $labl$$label;
12181 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12182 %}
12183 ins_pipe(pipe_jcc);
12184 %}
12185
12186 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12187 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12188 predicate(!n->has_vector_mask_set());
12189 match(CountedLoopEnd cop cmp);
12190 effect(USE labl);
12191
12192 ins_cost(300);
12193 format %{ "j$cop,u $labl\t# loop end" %}
12194 size(6);
12195 ins_encode %{
12196 Label* L = $labl$$label;
12197 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12198 %}
12199 ins_pipe(pipe_jcc);
12200 %}
12201
12202 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12203 predicate(!n->has_vector_mask_set());
12204 match(CountedLoopEnd cop cmp);
12205 effect(USE labl);
12206
12207 ins_cost(200);
12208 format %{ "j$cop,u $labl\t# loop end" %}
12209 size(6);
12210 ins_encode %{
12211 Label* L = $labl$$label;
12212 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12213 %}
12214 ins_pipe(pipe_jcc);
12215 %}
12216
12217 // mask version
12218 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12219 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
12220 %{
12221 predicate(n->has_vector_mask_set());
12222 match(CountedLoopEnd cop cr);
12223 effect(USE labl);
12224
12225 ins_cost(400);
12226 format %{ "j$cop $labl\t# loop end\n\t"
12227 "restorevectmask \t# vector mask restore for loops" %}
12228 size(10);
12229 ins_encode %{
12230 Label* L = $labl$$label;
12231 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12232 __ restorevectmask();
12233 %}
12234 ins_pipe(pipe_jcc);
12235 %}
12236
12237 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12238 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12239 predicate(n->has_vector_mask_set());
12240 match(CountedLoopEnd cop cmp);
12241 effect(USE labl);
12242
12243 ins_cost(400);
12244 format %{ "j$cop,u $labl\t# loop end\n\t"
12245 "restorevectmask \t# vector mask restore for loops" %}
12246 size(10);
12247 ins_encode %{
12248 Label* L = $labl$$label;
12249 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12250 __ restorevectmask();
12251 %}
12252 ins_pipe(pipe_jcc);
12253 %}
12254
12255 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12256 predicate(n->has_vector_mask_set());
12257 match(CountedLoopEnd cop cmp);
12258 effect(USE labl);
12259
12260 ins_cost(300);
12261 format %{ "j$cop,u $labl\t# loop end\n\t"
12262 "restorevectmask \t# vector mask restore for loops" %}
12263 size(10);
12264 ins_encode %{
12265 Label* L = $labl$$label;
12266 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12267 __ restorevectmask();
12268 %}
12269 ins_pipe(pipe_jcc);
12270 %}
12271
12272 // Jump Direct Conditional - using unsigned comparison
12273 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12274 match(If cop cmp);
12275 effect(USE labl);
12276
12277 ins_cost(300);
12278 format %{ "j$cop,u $labl" %}
12279 size(6);
12280 ins_encode %{
12281 Label* L = $labl$$label;
12282 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12283 %}
12284 ins_pipe(pipe_jcc);
12285 %}
12286
12287 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12288 match(If cop cmp);
12289 effect(USE labl);
12290
12291 ins_cost(200);
12292 format %{ "j$cop,u $labl" %}
12293 size(6);
12294 ins_encode %{
12295 Label* L = $labl$$label;
12296 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12297 %}
12298 ins_pipe(pipe_jcc);
12299 %}
12300
12301 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12302 match(If cop cmp);
12303 effect(USE labl);
12304
12305 ins_cost(200);
12306 format %{ $$template
12307 if ($cop$$cmpcode == Assembler::notEqual) {
12308 $$emit$$"jp,u $labl\n\t"
12309 $$emit$$"j$cop,u $labl"
12310 } else {
12311 $$emit$$"jp,u done\n\t"
12312 $$emit$$"j$cop,u $labl\n\t"
12313 $$emit$$"done:"
12314 }
12315 %}
12316 ins_encode %{
12317 Label* l = $labl$$label;
12318 if ($cop$$cmpcode == Assembler::notEqual) {
12319 __ jcc(Assembler::parity, *l, false);
12320 __ jcc(Assembler::notEqual, *l, false);
12321 } else if ($cop$$cmpcode == Assembler::equal) {
12322 Label done;
12323 __ jccb(Assembler::parity, done);
12324 __ jcc(Assembler::equal, *l, false);
12325 __ bind(done);
12326 } else {
12327 ShouldNotReachHere();
12328 }
12329 %}
12330 ins_pipe(pipe_jcc);
12331 %}
12332
12333 // ============================================================================
12334 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12335 // superklass array for an instance of the superklass. Set a hidden
12336 // internal cache on a hit (cache is checked with exposed code in
12337 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12338 // encoding ALSO sets flags.
12339
12340 instruct partialSubtypeCheck(rdi_RegP result,
12341 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12342 rFlagsReg cr)
12343 %{
12344 match(Set result (PartialSubtypeCheck sub super));
12345 effect(KILL rcx, KILL cr);
12346
12347 ins_cost(1100); // slightly larger than the next version
12348 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12349 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12350 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12351 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12352 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12353 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12354 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12355 "miss:\t" %}
12356
12357 opcode(0x1); // Force a XOR of RDI
12358 ins_encode(enc_PartialSubtypeCheck());
12359 ins_pipe(pipe_slow);
12360 %}
12361
12362 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12363 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12364 immP0 zero,
12365 rdi_RegP result)
12366 %{
12367 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12368 effect(KILL rcx, KILL result);
12369
12370 ins_cost(1000);
12371 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12372 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12373 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12374 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12375 "jne,s miss\t\t# Missed: flags nz\n\t"
12376 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12377 "miss:\t" %}
12378
12379 opcode(0x0); // No need to XOR RDI
12380 ins_encode(enc_PartialSubtypeCheck());
12381 ins_pipe(pipe_slow);
12382 %}
12383
12384 // ============================================================================
12385 // Branch Instructions -- short offset versions
12386 //
12387 // These instructions are used to replace jumps of a long offset (the default
12388 // match) with jumps of a shorter offset. These instructions are all tagged
12389 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12390 // match rules in general matching. Instead, the ADLC generates a conversion
12391 // method in the MachNode which can be used to do in-place replacement of the
12392 // long variant with the shorter variant. The compiler will determine if a
12393 // branch can be taken by the is_short_branch_offset() predicate in the machine
12394 // specific code section of the file.
12395
12396 // Jump Direct - Label defines a relative address from JMP+1
12397 instruct jmpDir_short(label labl) %{
12398 match(Goto);
12399 effect(USE labl);
12400
12401 ins_cost(300);
12402 format %{ "jmp,s $labl" %}
12403 size(2);
12404 ins_encode %{
12405 Label* L = $labl$$label;
12406 __ jmpb(*L);
12407 %}
12408 ins_pipe(pipe_jmp);
12409 ins_short_branch(1);
12410 %}
12411
12412 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12413 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12414 match(If cop cr);
12415 effect(USE labl);
12416
12417 ins_cost(300);
12418 format %{ "j$cop,s $labl" %}
12419 size(2);
12420 ins_encode %{
12421 Label* L = $labl$$label;
12422 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12423 %}
12424 ins_pipe(pipe_jcc);
12425 ins_short_branch(1);
12426 %}
12427
12428 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12429 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12430 match(CountedLoopEnd cop cr);
12431 effect(USE labl);
12432
12433 ins_cost(300);
12434 format %{ "j$cop,s $labl\t# loop end" %}
12435 size(2);
12436 ins_encode %{
12437 Label* L = $labl$$label;
12438 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12439 %}
12440 ins_pipe(pipe_jcc);
12441 ins_short_branch(1);
12442 %}
12443
12444 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12445 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12446 match(CountedLoopEnd cop cmp);
12447 effect(USE labl);
12448
12449 ins_cost(300);
12450 format %{ "j$cop,us $labl\t# loop end" %}
12451 size(2);
12452 ins_encode %{
12453 Label* L = $labl$$label;
12454 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12455 %}
12456 ins_pipe(pipe_jcc);
12457 ins_short_branch(1);
12458 %}
12459
12460 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12461 match(CountedLoopEnd cop cmp);
12462 effect(USE labl);
12463
12464 ins_cost(300);
12465 format %{ "j$cop,us $labl\t# loop end" %}
12466 size(2);
12467 ins_encode %{
12468 Label* L = $labl$$label;
12469 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12470 %}
12471 ins_pipe(pipe_jcc);
12472 ins_short_branch(1);
12473 %}
12474
12475 // Jump Direct Conditional - using unsigned comparison
12476 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12477 match(If cop cmp);
12478 effect(USE labl);
12479
12480 ins_cost(300);
12481 format %{ "j$cop,us $labl" %}
12482 size(2);
12483 ins_encode %{
12484 Label* L = $labl$$label;
12485 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12486 %}
12487 ins_pipe(pipe_jcc);
12488 ins_short_branch(1);
12489 %}
12490
12491 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12492 match(If cop cmp);
12493 effect(USE labl);
12494
12495 ins_cost(300);
12496 format %{ "j$cop,us $labl" %}
12497 size(2);
12498 ins_encode %{
12499 Label* L = $labl$$label;
12500 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12501 %}
12502 ins_pipe(pipe_jcc);
12503 ins_short_branch(1);
12504 %}
12505
12506 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12507 match(If cop cmp);
12508 effect(USE labl);
12509
12510 ins_cost(300);
12511 format %{ $$template
12512 if ($cop$$cmpcode == Assembler::notEqual) {
12513 $$emit$$"jp,u,s $labl\n\t"
12514 $$emit$$"j$cop,u,s $labl"
12515 } else {
12516 $$emit$$"jp,u,s done\n\t"
12517 $$emit$$"j$cop,u,s $labl\n\t"
12518 $$emit$$"done:"
12519 }
12520 %}
12521 size(4);
12522 ins_encode %{
12523 Label* l = $labl$$label;
12524 if ($cop$$cmpcode == Assembler::notEqual) {
12525 __ jccb(Assembler::parity, *l);
12526 __ jccb(Assembler::notEqual, *l);
12527 } else if ($cop$$cmpcode == Assembler::equal) {
12528 Label done;
12529 __ jccb(Assembler::parity, done);
12530 __ jccb(Assembler::equal, *l);
12531 __ bind(done);
12532 } else {
12533 ShouldNotReachHere();
12534 }
12535 %}
12536 ins_pipe(pipe_jcc);
12537 ins_short_branch(1);
12538 %}
12539
12540 // ============================================================================
12541 // inlined locking and unlocking
12542
12543 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12544 predicate(Compile::current()->use_rtm());
12545 match(Set cr (FastLock object box));
12546 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12547 ins_cost(300);
12548 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12549 ins_encode %{
12550 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12551 $scr$$Register, $cx1$$Register, $cx2$$Register,
12552 _counters, _rtm_counters, _stack_rtm_counters,
12553 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12554 true, ra_->C->profile_rtm());
12555 %}
12556 ins_pipe(pipe_slow);
12557 %}
12558
12559 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12560 predicate(!Compile::current()->use_rtm());
12561 match(Set cr (FastLock object box));
12562 effect(TEMP tmp, TEMP scr, USE_KILL box);
12563 ins_cost(300);
12564 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12565 ins_encode %{
12566 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12567 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12568 %}
12569 ins_pipe(pipe_slow);
12570 %}
12571
12572 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12573 match(Set cr (FastUnlock object box));
12574 effect(TEMP tmp, USE_KILL box);
12575 ins_cost(300);
12576 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12577 ins_encode %{
12578 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12579 %}
12580 ins_pipe(pipe_slow);
12581 %}
12582
12583
12584 // ============================================================================
12585 // Safepoint Instructions
12586 instruct safePoint_poll(rFlagsReg cr)
12587 %{
12588 predicate(!Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12589 match(SafePoint);
12590 effect(KILL cr);
12591
12592 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12593 "# Safepoint: poll for GC" %}
12594 ins_cost(125);
12595 ins_encode %{
12596 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12597 __ testl(rax, addr);
12598 %}
12599 ins_pipe(ialu_reg_mem);
12600 %}
12601
12602 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12603 %{
12604 predicate(Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12605 match(SafePoint poll);
12606 effect(KILL cr, USE poll);
12607
12608 format %{ "testl rax, [$poll]\t"
12609 "# Safepoint: poll for GC" %}
12610 ins_cost(125);
12611 ins_encode %{
12612 __ relocate(relocInfo::poll_type);
12613 __ testl(rax, Address($poll$$Register, 0));
12614 %}
12615 ins_pipe(ialu_reg_mem);
12616 %}
12617
12618 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12619 %{
12620 predicate(SafepointMechanism::uses_thread_local_poll());
12621 match(SafePoint poll);
12622 effect(KILL cr, USE poll);
12623
12624 format %{ "testl rax, [$poll]\t"
12625 "# Safepoint: poll for GC" %}
12626 ins_cost(125);
12627 size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12628 ins_encode %{
12629 __ relocate(relocInfo::poll_type);
12630 address pre_pc = __ pc();
12631 __ testl(rax, Address($poll$$Register, 0));
12632 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
12633 %}
12634 ins_pipe(ialu_reg_mem);
12635 %}
12636
12637 // ============================================================================
12638 // Procedure Call/Return Instructions
12639 // Call Java Static Instruction
12640 // Note: If this code changes, the corresponding ret_addr_offset() and
12641 // compute_padding() functions will have to be adjusted.
12642 instruct CallStaticJavaDirect(method meth) %{
12643 match(CallStaticJava);
12644 effect(USE meth);
12645
12646 ins_cost(300);
12647 format %{ "call,static " %}
12648 opcode(0xE8); /* E8 cd */
12649 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12650 ins_pipe(pipe_slow);
12651 ins_alignment(4);
12652 %}
12653
12654 // Call Java Dynamic Instruction
12655 // Note: If this code changes, the corresponding ret_addr_offset() and
12656 // compute_padding() functions will have to be adjusted.
12657 instruct CallDynamicJavaDirect(method meth)
12658 %{
12659 match(CallDynamicJava);
12660 effect(USE meth);
12661
12662 ins_cost(300);
12663 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12664 "call,dynamic " %}
12665 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12666 ins_pipe(pipe_slow);
12667 ins_alignment(4);
12668 %}
12669
12670 // Call Runtime Instruction
12671 instruct CallRuntimeDirect(method meth)
12672 %{
12673 match(CallRuntime);
12674 effect(USE meth);
12675
12676 ins_cost(300);
12677 format %{ "call,runtime " %}
12678 ins_encode(clear_avx, Java_To_Runtime(meth));
12679 ins_pipe(pipe_slow);
12680 %}
12681
12682 // Call runtime without safepoint
12683 instruct CallLeafDirect(method meth)
12684 %{
12685 match(CallLeaf);
12686 effect(USE meth);
12687
12688 ins_cost(300);
12689 format %{ "call_leaf,runtime " %}
12690 ins_encode(clear_avx, Java_To_Runtime(meth));
12691 ins_pipe(pipe_slow);
12692 %}
12693
12694 // Call runtime without safepoint
12695 instruct CallLeafNoFPDirect(method meth)
12696 %{
12697 match(CallLeafNoFP);
12698 effect(USE meth);
12699
12700 ins_cost(300);
12701 format %{ "call_leaf_nofp,runtime " %}
12702 ins_encode(clear_avx, Java_To_Runtime(meth));
12703 ins_pipe(pipe_slow);
12704 %}
12705
12706 // Return Instruction
12707 // Remove the return address & jump to it.
12708 // Notice: We always emit a nop after a ret to make sure there is room
12709 // for safepoint patching
12710 instruct Ret()
12711 %{
12712 match(Return);
12713
12714 format %{ "ret" %}
12715 opcode(0xC3);
12716 ins_encode(OpcP);
12717 ins_pipe(pipe_jmp);
12718 %}
12719
12720 // Tail Call; Jump from runtime stub to Java code.
12721 // Also known as an 'interprocedural jump'.
12722 // Target of jump will eventually return to caller.
12723 // TailJump below removes the return address.
12724 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12725 %{
12726 match(TailCall jump_target method_oop);
12727
12728 ins_cost(300);
12729 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12730 opcode(0xFF, 0x4); /* Opcode FF /4 */
12731 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12732 ins_pipe(pipe_jmp);
12733 %}
12734
12735 // Tail Jump; remove the return address; jump to target.
12736 // TailCall above leaves the return address around.
12737 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12738 %{
12739 match(TailJump jump_target ex_oop);
12740
12741 ins_cost(300);
12742 format %{ "popq rdx\t# pop return address\n\t"
12743 "jmp $jump_target" %}
12744 opcode(0xFF, 0x4); /* Opcode FF /4 */
12745 ins_encode(Opcode(0x5a), // popq rdx
12746 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12747 ins_pipe(pipe_jmp);
12748 %}
12749
12750 // Create exception oop: created by stack-crawling runtime code.
12751 // Created exception is now available to this handler, and is setup
12752 // just prior to jumping to this handler. No code emitted.
12753 instruct CreateException(rax_RegP ex_oop)
12754 %{
12755 match(Set ex_oop (CreateEx));
12756
12757 size(0);
12758 // use the following format syntax
12759 format %{ "# exception oop is in rax; no code emitted" %}
12760 ins_encode();
12761 ins_pipe(empty);
12762 %}
12763
12764 // Rethrow exception:
12765 // The exception oop will come in the first argument position.
12766 // Then JUMP (not call) to the rethrow stub code.
12767 instruct RethrowException()
12768 %{
12769 match(Rethrow);
12770
12771 // use the following format syntax
12772 format %{ "jmp rethrow_stub" %}
12773 ins_encode(enc_rethrow);
12774 ins_pipe(pipe_jmp);
12775 %}
12776
12777 // ============================================================================
12778 // This name is KNOWN by the ADLC and cannot be changed.
12779 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12780 // for this guy.
12781 instruct tlsLoadP(r15_RegP dst) %{
12782 match(Set dst (ThreadLocal));
12783 effect(DEF dst);
12784
12785 size(0);
12786 format %{ "# TLS is in R15" %}
12787 ins_encode( /*empty encoding*/ );
12788 ins_pipe(ialu_reg_reg);
12789 %}
12790
12791
12792 //----------PEEPHOLE RULES-----------------------------------------------------
12793 // These must follow all instruction definitions as they use the names
12794 // defined in the instructions definitions.
12795 //
12796 // peepmatch ( root_instr_name [preceding_instruction]* );
12797 //
12798 // peepconstraint %{
12799 // (instruction_number.operand_name relational_op instruction_number.operand_name
12800 // [, ...] );
12801 // // instruction numbers are zero-based using left to right order in peepmatch
12802 //
12803 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12804 // // provide an instruction_number.operand_name for each operand that appears
12805 // // in the replacement instruction's match rule
12806 //
12807 // ---------VM FLAGS---------------------------------------------------------
12808 //
12809 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12810 //
12811 // Each peephole rule is given an identifying number starting with zero and
12812 // increasing by one in the order seen by the parser. An individual peephole
12813 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12814 // on the command-line.
12815 //
12816 // ---------CURRENT LIMITATIONS----------------------------------------------
12817 //
12818 // Only match adjacent instructions in same basic block
12819 // Only equality constraints
12820 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12821 // Only one replacement instruction
12822 //
12823 // ---------EXAMPLE----------------------------------------------------------
12824 //
12825 // // pertinent parts of existing instructions in architecture description
12826 // instruct movI(rRegI dst, rRegI src)
12827 // %{
12828 // match(Set dst (CopyI src));
12829 // %}
12830 //
12831 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12832 // %{
12833 // match(Set dst (AddI dst src));
12834 // effect(KILL cr);
12835 // %}
12836 //
12837 // // Change (inc mov) to lea
12838 // peephole %{
12839 // // increment preceeded by register-register move
12840 // peepmatch ( incI_rReg movI );
12841 // // require that the destination register of the increment
12842 // // match the destination register of the move
12843 // peepconstraint ( 0.dst == 1.dst );
12844 // // construct a replacement instruction that sets
12845 // // the destination to ( move's source register + one )
12846 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12847 // %}
12848 //
12849
12850 // Implementation no longer uses movX instructions since
12851 // machine-independent system no longer uses CopyX nodes.
12852 //
12853 // peephole
12854 // %{
12855 // peepmatch (incI_rReg movI);
12856 // peepconstraint (0.dst == 1.dst);
12857 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12858 // %}
12859
12860 // peephole
12861 // %{
12862 // peepmatch (decI_rReg movI);
12863 // peepconstraint (0.dst == 1.dst);
12864 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12865 // %}
12866
12867 // peephole
12868 // %{
12869 // peepmatch (addI_rReg_imm movI);
12870 // peepconstraint (0.dst == 1.dst);
12871 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12872 // %}
12873
12874 // peephole
12875 // %{
12876 // peepmatch (incL_rReg movL);
12877 // peepconstraint (0.dst == 1.dst);
12878 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12879 // %}
12880
12881 // peephole
12882 // %{
12883 // peepmatch (decL_rReg movL);
12884 // peepconstraint (0.dst == 1.dst);
12885 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12886 // %}
12887
12888 // peephole
12889 // %{
12890 // peepmatch (addL_rReg_imm movL);
12891 // peepconstraint (0.dst == 1.dst);
12892 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12893 // %}
12894
12895 // peephole
12896 // %{
12897 // peepmatch (addP_rReg_imm movP);
12898 // peepconstraint (0.dst == 1.dst);
12899 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12900 // %}
12901
12902 // // Change load of spilled value to only a spill
12903 // instruct storeI(memory mem, rRegI src)
12904 // %{
12905 // match(Set mem (StoreI mem src));
12906 // %}
12907 //
12908 // instruct loadI(rRegI dst, memory mem)
12909 // %{
12910 // match(Set dst (LoadI mem));
12911 // %}
12912 //
12913
12914 peephole
12915 %{
12916 peepmatch (loadI storeI);
12917 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12918 peepreplace (storeI(1.mem 1.mem 1.src));
12919 %}
12920
12921 peephole
12922 %{
12923 peepmatch (loadL storeL);
12924 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12925 peepreplace (storeL(1.mem 1.mem 1.src));
12926 %}
12927
12928 //----------SMARTSPILL RULES---------------------------------------------------
12929 // These must follow all instruction definitions as they use the names
12930 // defined in the instructions definitions.