--- old/src/hotspot/cpu/x86/x86.ad 2020-07-16 18:40:51.276810747 -0700 +++ new/src/hotspot/cpu/x86/x86.ad 2020-07-16 18:40:51.156810747 -0700 @@ -1166,14 +1166,6 @@ #endif }; -class Node::PD { -public: - enum NodeFlags { - Flag_intel_jcc_erratum = Node::_last_flag << 1, - _last_flag = Flag_intel_jcc_erratum - }; -}; - inline uint vector_length(const Node* n) { const TypeVect* vt = n->bottom_type()->is_vect(); @@ -1232,6 +1224,14 @@ return vector_length_encoding(def); } +class Node::PD { +public: + enum NodeFlags { + Flag_intel_jcc_erratum = Node::_last_flag << 1, + _last_flag = Flag_intel_jcc_erratum + }; +}; + %} // end source_hpp source %{ @@ -1505,14 +1505,6 @@ return false; // 128bit vroundpd is not available } break; - case Op_MacroLogicV: - if (UseAVX < 3 || !UseVectorMacroLogic) { - return false; - } - break; - case Op_VLShiftV: - case Op_VRShiftV: - case Op_VURShiftV: case Op_LoadVectorGather: if (UseAVX < 2) { return false; @@ -1524,6 +1516,11 @@ return false; } break; + case Op_MacroLogicV: + if (UseAVX < 3 || !UseVectorMacroLogic) { + return false; + } + break; #ifndef _LP64 case Op_AddReductionVF: case Op_AddReductionVD: @@ -1562,7 +1559,6 @@ // * AVX512BW supports 512bit vectors for BYTE, SHORT, and CHAR types. // There's also a limit on minimum vector size supported: 2 elements (or 4 bytes for BYTE). // And MaxVectorSize is taken into account as well. - if (!vector_size_supported(bt, vlen)) { return false; } @@ -1795,6 +1791,10 @@ //------------------------------------------------------------------------ +bool Matcher::supports_vector_variable_shifts(void) { + return (UseAVX >= 2); +} + const bool Matcher::has_predicated_vectors(void) { bool ret_value = false; if (UseAVX > 2) { @@ -4193,12 +4193,12 @@ // ====================VECTOR INSERT======================================= instruct insert(vec dst, rRegI val, immU8 idx) %{ - predicate(vector_length_in_bytes(n) >= 8 && - vector_length_in_bytes(n) <= 16); + predicate(vector_length_in_bytes(n) < 32); match(Set dst (VectorInsert (Binary dst val) idx)); format %{ "vector_insert $dst,$val,$idx" %} ins_encode %{ assert(UseSSE >= 4, "required"); + assert(vector_length_in_bytes(this) >= 8, "required"); BasicType elem_bt = vector_element_basic_type(this); @@ -4228,7 +4228,7 @@ uint y_idx = ($idx$$constant >> log2epr) & 1; __ vextracti128($vtmp$$XMMRegister, $src$$XMMRegister, y_idx); __ vinsert(elem_bt, $vtmp$$XMMRegister, $vtmp$$XMMRegister, $val$$Register, x_idx); - __ vinserti128($dst$$XMMRegister, $dst$$XMMRegister, $vtmp$$XMMRegister, y_idx); + __ vinserti128($dst$$XMMRegister, $src$$XMMRegister, $vtmp$$XMMRegister, y_idx); %} ins_pipe( pipe_slow ); %} @@ -4252,7 +4252,7 @@ uint y_idx = ($idx$$constant >> log2epr) & 3; __ vextracti32x4($vtmp$$XMMRegister, $src$$XMMRegister, y_idx); __ vinsert(elem_bt, $vtmp$$XMMRegister, $vtmp$$XMMRegister, $val$$Register, x_idx); - __ vinserti32x4($dst$$XMMRegister, $dst$$XMMRegister, $vtmp$$XMMRegister, y_idx); + __ vinserti32x4($dst$$XMMRegister, $src$$XMMRegister, $vtmp$$XMMRegister, y_idx); %} ins_pipe( pipe_slow ); %} @@ -4286,7 +4286,7 @@ int vlen_enc = Assembler::AVX_256bit; __ vextracti128($vtmp$$XMMRegister, $src$$XMMRegister, y_idx); __ vpinsrq($vtmp$$XMMRegister, $vtmp$$XMMRegister, $val$$Register, x_idx); - __ vinserti128($dst$$XMMRegister, $dst$$XMMRegister, $vtmp$$XMMRegister, y_idx); + __ vinserti128($dst$$XMMRegister, $src$$XMMRegister, $vtmp$$XMMRegister, y_idx); %} ins_pipe( pipe_slow ); %} @@ -4304,15 +4304,14 @@ uint y_idx = ($idx$$constant >> 1) & 3; __ vextracti32x4($vtmp$$XMMRegister, $src$$XMMRegister, y_idx); __ vpinsrq($vtmp$$XMMRegister, $vtmp$$XMMRegister, $val$$Register, x_idx); - __ vinserti32x4($dst$$XMMRegister, $dst$$XMMRegister, $vtmp$$XMMRegister, y_idx); + __ vinserti32x4($dst$$XMMRegister, $src$$XMMRegister, $vtmp$$XMMRegister, y_idx); %} ins_pipe( pipe_slow ); %} #endif instruct insertF(vec dst, regF val, immU8 idx) %{ - predicate(vector_length(n) >= 2 && - vector_length(n) <= 4); + predicate(vector_length(n) < 8); match(Set dst (VectorInsert (Binary dst val) idx)); format %{ "vector_insert $dst,$val,$idx" %} ins_encode %{ @@ -4342,13 +4341,13 @@ int vlen_enc = Assembler::AVX_256bit; __ vextracti128($vtmp$$XMMRegister, $src$$XMMRegister, y_idx); __ vinsertps($vtmp$$XMMRegister, $vtmp$$XMMRegister, $val$$XMMRegister, x_idx); - __ vinserti128($dst$$XMMRegister, $dst$$XMMRegister, $vtmp$$XMMRegister, y_idx); + __ vinserti128($dst$$XMMRegister, $src$$XMMRegister, $vtmp$$XMMRegister, y_idx); } else { assert(vlen == 16, "sanity"); uint y_idx = ($idx$$constant >> 2) & 3; __ vextracti32x4($vtmp$$XMMRegister, $src$$XMMRegister, y_idx); __ vinsertps($vtmp$$XMMRegister, $vtmp$$XMMRegister, $val$$XMMRegister, x_idx); - __ vinserti32x4($dst$$XMMRegister, $dst$$XMMRegister, $vtmp$$XMMRegister, y_idx); + __ vinserti32x4($dst$$XMMRegister, $src$$XMMRegister, $vtmp$$XMMRegister, y_idx); } %} ins_pipe( pipe_slow ); @@ -4386,7 +4385,7 @@ __ movq($tmp$$Register, $val$$XMMRegister); __ vextracti128($vtmp$$XMMRegister, $src$$XMMRegister, y_idx); __ vpinsrq($vtmp$$XMMRegister, $vtmp$$XMMRegister, $tmp$$Register, x_idx); - __ vinserti128($dst$$XMMRegister, $dst$$XMMRegister, $vtmp$$XMMRegister, y_idx); + __ vinserti128($dst$$XMMRegister, $src$$XMMRegister, $vtmp$$XMMRegister, y_idx); %} ins_pipe( pipe_slow ); %} @@ -4405,7 +4404,7 @@ __ movq($tmp$$Register, $val$$XMMRegister); __ vextracti32x4($vtmp$$XMMRegister, $src$$XMMRegister, y_idx); __ vpinsrq($vtmp$$XMMRegister, $vtmp$$XMMRegister, $tmp$$Register, x_idx); - __ vinserti32x4($dst$$XMMRegister, $dst$$XMMRegister, $vtmp$$XMMRegister, y_idx); + __ vinserti32x4($dst$$XMMRegister, $src$$XMMRegister, $vtmp$$XMMRegister, y_idx); %} ins_pipe( pipe_slow ); %} @@ -5904,7 +5903,7 @@ // Byte vector shift instruct vshiftB(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{ - predicate(vector_length(n) <= 8); + predicate(vector_length(n) <= 8 && VectorNode::is_vshift_cnt(n->in(2))); match(Set dst ( LShiftVB src shift)); match(Set dst ( RShiftVB src shift)); match(Set dst (URShiftVB src shift)); @@ -5913,7 +5912,7 @@ ins_encode %{ assert(UseSSE > 3, "required"); int opcode = this->ideal_Opcode(); - bool sign = (opcode == Op_URShiftVB) ? false : true; + bool sign = (opcode != Op_URShiftVB); __ vextendbw(sign, $tmp$$XMMRegister, $src$$XMMRegister); __ vshiftw(opcode, $tmp$$XMMRegister, $shift$$XMMRegister); __ movdqu($dst$$XMMRegister, ExternalAddress(vector_short_to_byte_mask()), $scratch$$Register); @@ -5924,7 +5923,8 @@ %} instruct vshift16B(vec dst, vec src, vec shift, vec tmp1, vec tmp2, rRegI scratch) %{ - predicate(vector_length(n) == 16 && UseAVX <= 1); + predicate(vector_length(n) == 16 && VectorNode::is_vshift_cnt(n->in(2)) && + UseAVX <= 1); match(Set dst ( LShiftVB src shift)); match(Set dst ( RShiftVB src shift)); match(Set dst (URShiftVB src shift)); @@ -5933,7 +5933,7 @@ ins_encode %{ assert(UseSSE > 3, "required"); int opcode = this->ideal_Opcode(); - bool sign = (opcode == Op_URShiftVB) ? false : true; + bool sign = (opcode != Op_URShiftVB); __ vextendbw(sign, $tmp1$$XMMRegister, $src$$XMMRegister); __ vshiftw(opcode, $tmp1$$XMMRegister, $shift$$XMMRegister); __ pshufd($tmp2$$XMMRegister, $src$$XMMRegister, 0xE); @@ -5948,7 +5948,8 @@ %} instruct vshift16B_avx(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{ - predicate(vector_length(n) == 16 && UseAVX > 1); + predicate(vector_length(n) == 16 && VectorNode::is_vshift_cnt(n->in(2)) && + UseAVX > 1); match(Set dst ( LShiftVB src shift)); match(Set dst ( RShiftVB src shift)); match(Set dst (URShiftVB src shift)); @@ -5956,7 +5957,7 @@ format %{"vector_byte_shift $dst,$src,$shift" %} ins_encode %{ int opcode = this->ideal_Opcode(); - bool sign = (opcode == Op_URShiftVB) ? false : true; + bool sign = (opcode != Op_URShiftVB); int vlen_enc = Assembler::AVX_256bit; __ vextendbw(sign, $tmp$$XMMRegister, $src$$XMMRegister, vlen_enc); __ vshiftw(opcode, $tmp$$XMMRegister, $tmp$$XMMRegister, $shift$$XMMRegister, vlen_enc); @@ -5968,7 +5969,7 @@ %} instruct vshift32B_avx(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{ - predicate(vector_length(n) == 32); + predicate(vector_length(n) == 32 && VectorNode::is_vshift_cnt(n->in(2))); match(Set dst ( LShiftVB src shift)); match(Set dst ( RShiftVB src shift)); match(Set dst (URShiftVB src shift)); @@ -5977,7 +5978,7 @@ ins_encode %{ assert(UseAVX > 1, "required"); int opcode = this->ideal_Opcode(); - bool sign = (opcode == Op_URShiftVB) ? false : true; + bool sign = (opcode != Op_URShiftVB); int vlen_enc = Assembler::AVX_256bit; __ vextracti128_high($tmp$$XMMRegister, $src$$XMMRegister); __ vextendbw(sign, $tmp$$XMMRegister, $tmp$$XMMRegister, vlen_enc); @@ -5993,7 +5994,7 @@ %} instruct vshift64B_avx(vec dst, vec src, vec shift, vec tmp1, vec tmp2, rRegI scratch) %{ - predicate(vector_length(n) == 64); + predicate(vector_length(n) == 64 && VectorNode::is_vshift_cnt(n->in(2))); match(Set dst ( LShiftVB src shift)); match(Set dst (RShiftVB src shift)); match(Set dst (URShiftVB src shift)); @@ -6002,7 +6003,7 @@ ins_encode %{ assert(UseAVX > 2, "required"); int opcode = this->ideal_Opcode(); - bool sign = (opcode == Op_URShiftVB) ? false : true; + bool sign = (opcode != Op_URShiftVB); int vlen_enc = Assembler::AVX_512bit; __ vextracti64x4($tmp1$$XMMRegister, $src$$XMMRegister, 1); __ vextendbw(sign, $tmp1$$XMMRegister, $tmp1$$XMMRegister, vlen_enc); @@ -6026,6 +6027,7 @@ // unsigned values. // Shorts/Chars vector left shift instruct vshiftS(vec dst, vec src, vec shift) %{ + predicate(VectorNode::is_vshift_cnt(n->in(2))); match(Set dst ( LShiftVS src shift)); match(Set dst ( RShiftVS src shift)); match(Set dst (URShiftVS src shift)); @@ -6056,6 +6058,7 @@ // Integers vector left shift instruct vshiftI(vec dst, vec src, vec shift) %{ + predicate(VectorNode::is_vshift_cnt(n->in(2))); match(Set dst ( LShiftVI src shift)); match(Set dst ( RShiftVI src shift)); match(Set dst (URShiftVI src shift)); @@ -6083,6 +6086,7 @@ // Longs vector shift instruct vshiftL(vec dst, vec src, vec shift) %{ + predicate(VectorNode::is_vshift_cnt(n->in(2))); match(Set dst ( LShiftVL src shift)); match(Set dst (URShiftVL src shift)); effect(TEMP dst, USE src, USE shift); @@ -6104,7 +6108,7 @@ // -------------------ArithmeticRightShift ----------------------------------- // Long vector arithmetic right shift instruct vshiftL_arith_reg(vec dst, vec src, vec shift, vec tmp, rRegI scratch) %{ - predicate(UseAVX <= 2); + predicate(VectorNode::is_vshift_cnt(n->in(2)) && UseAVX <= 2); match(Set dst (RShiftVL src shift)); effect(TEMP dst, TEMP tmp, TEMP scratch); format %{ "vshiftq $dst,$src,$shift" %} @@ -6133,7 +6137,7 @@ %} instruct vshiftL_arith_reg_evex(vec dst, vec src, vec shift) %{ - predicate(UseAVX > 2); + predicate(VectorNode::is_vshift_cnt(n->in(2)) && UseAVX > 2); match(Set dst (RShiftVL src shift)); format %{ "vshiftq $dst,$src,$shift" %} ins_encode %{ @@ -6146,11 +6150,12 @@ // ------------------- Variable Shift ----------------------------- // Byte variable shift instruct vshift8B_var_nobw(vec dst, vec src, vec shift, vec vtmp, rRegP scratch) %{ - predicate(vector_length(n) <= 8 && vector_element_basic_type(n) == T_BYTE && + predicate(vector_length(n) <= 8 && + !VectorNode::is_vshift_cnt(n->in(2)) && !VM_Version::supports_avx512bw()); - match(Set dst ( VLShiftV src shift)); - match(Set dst ( VRShiftV src shift)); - match(Set dst (VURShiftV src shift)); + match(Set dst ( LShiftVB src shift)); + match(Set dst ( RShiftVB src shift)); + match(Set dst (URShiftVB src shift)); effect(TEMP dst, TEMP vtmp, TEMP scratch); format %{ "vector_varshift_byte $dst, $src, $shift\n\t! using $vtmp, $scratch as TEMP" %} ins_encode %{ @@ -6165,11 +6170,12 @@ %} instruct vshift16B_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, rRegP scratch) %{ - predicate(vector_length(n) == 16 && vector_element_basic_type(n) == T_BYTE && + predicate(vector_length(n) == 16 && + !VectorNode::is_vshift_cnt(n->in(2)) && !VM_Version::supports_avx512bw()); - match(Set dst ( VLShiftV src shift)); - match(Set dst ( VRShiftV src shift)); - match(Set dst (VURShiftV src shift)); + match(Set dst ( LShiftVB src shift)); + match(Set dst ( RShiftVB src shift)); + match(Set dst (URShiftVB src shift)); effect(TEMP dst, TEMP vtmp1, TEMP vtmp2, TEMP scratch); format %{ "vector_varshift_byte $dst, $src, $shift\n\t! using $vtmp1, $vtmp2 and $scratch as TEMP" %} ins_encode %{ @@ -6192,11 +6198,12 @@ %} instruct vshift32B_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, vec vtmp3, vec vtmp4, rRegP scratch) %{ - predicate(vector_length(n) == 32 && vector_element_basic_type(n) == T_BYTE && + predicate(vector_length(n) == 32 && + !VectorNode::is_vshift_cnt(n->in(2)) && !VM_Version::supports_avx512bw()); - match(Set dst ( VLShiftV src shift)); - match(Set dst ( VRShiftV src shift)); - match(Set dst (VURShiftV src shift)); + match(Set dst ( LShiftVB src shift)); + match(Set dst ( RShiftVB src shift)); + match(Set dst (URShiftVB src shift)); effect(TEMP dst, TEMP vtmp1, TEMP vtmp2, TEMP vtmp3, TEMP vtmp4, TEMP scratch); format %{ "vector_varshift_byte $dst, $src, $shift\n\t using $vtmp1, $vtmp2, $vtmp3, $vtmp4 and $scratch as TEMP" %} ins_encode %{ @@ -6227,11 +6234,12 @@ %} instruct vshiftB_var_evex_bw(vec dst, vec src, vec shift, vec vtmp, rRegP scratch) %{ - predicate(vector_length(n) <= 32 && vector_element_basic_type(n) == T_BYTE && + predicate(vector_length(n) <= 32 && + !VectorNode::is_vshift_cnt(n->in(2)) && VM_Version::supports_avx512bw()); - match(Set dst ( VLShiftV src shift)); - match(Set dst ( VRShiftV src shift)); - match(Set dst (VURShiftV src shift)); + match(Set dst ( LShiftVB src shift)); + match(Set dst ( RShiftVB src shift)); + match(Set dst (URShiftVB src shift)); effect(TEMP dst, TEMP vtmp, TEMP scratch); format %{ "vector_varshift_byte $dst, $src, $shift\n\t! using $vtmp, $scratch as TEMP" %} ins_encode %{ @@ -6245,11 +6253,12 @@ %} instruct vshift64B_var_evex_bw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, rRegP scratch) %{ - predicate(vector_length(n) == 64 && vector_element_basic_type(n) == T_BYTE && + predicate(vector_length(n) == 64 && + !VectorNode::is_vshift_cnt(n->in(2)) && VM_Version::supports_avx512bw()); - match(Set dst ( VLShiftV src shift)); - match(Set dst ( VRShiftV src shift)); - match(Set dst (VURShiftV src shift)); + match(Set dst ( LShiftVB src shift)); + match(Set dst ( RShiftVB src shift)); + match(Set dst (URShiftVB src shift)); effect(TEMP dst, TEMP vtmp1, TEMP vtmp2, TEMP scratch); format %{ "vector_varshift_byte $dst, $src, $shift\n\t! using $vtmp1, $vtmp2 and $scratch as TEMP" %} ins_encode %{ @@ -6268,18 +6277,19 @@ // Short variable shift instruct vshift8S_var_nobw(vec dst, vec src, vec shift, vec vtmp, rRegP scratch) %{ - predicate(vector_length(n) <= 8 && vector_element_basic_type(n) == T_SHORT && + predicate(vector_length(n) <= 8 && + !VectorNode::is_vshift_cnt(n->in(2)) && !VM_Version::supports_avx512bw()); - match(Set dst (VLShiftV src shift)); - match(Set dst (VRShiftV src shift)); - match(Set dst (VURShiftV src shift)); + match(Set dst ( LShiftVS src shift)); + match(Set dst ( RShiftVS src shift)); + match(Set dst (URShiftVS src shift)); effect(TEMP dst, TEMP vtmp, TEMP scratch); format %{ "vector_var_shift_left_short $dst, $src, $shift\n\t" %} ins_encode %{ assert(UseAVX >= 2, "required"); int opcode = this->ideal_Opcode(); - bool sign = (opcode == Op_VURShiftV) ? false : true; + bool sign = (opcode != Op_URShiftVS); int vlen_enc = Assembler::AVX_256bit; __ vextendwd(sign, $dst$$XMMRegister, $src$$XMMRegister, 1); __ vpmovzxwd($vtmp$$XMMRegister, $shift$$XMMRegister, 1); @@ -6292,18 +6302,19 @@ %} instruct vshift16S_var_nobw(vec dst, vec src, vec shift, vec vtmp1, vec vtmp2, rRegP scratch) %{ - predicate(vector_length(n) == 16 && vector_element_basic_type(n) == T_SHORT && + predicate(vector_length(n) == 16 && + !VectorNode::is_vshift_cnt(n->in(2)) && !VM_Version::supports_avx512bw()); - match(Set dst (VLShiftV src shift)); - match(Set dst (VRShiftV src shift)); - match(Set dst (VURShiftV src shift)); + match(Set dst ( LShiftVS src shift)); + match(Set dst ( RShiftVS src shift)); + match(Set dst (URShiftVS src shift)); effect(TEMP dst, TEMP vtmp1, TEMP vtmp2, TEMP scratch); format %{ "vector_var_shift_left_short $dst, $src, $shift\n\t" %} ins_encode %{ assert(UseAVX >= 2, "required"); int opcode = this->ideal_Opcode(); - bool sign = (opcode == Op_VURShiftV) ? false : true; + bool sign = (opcode != Op_URShiftVS); int vlen_enc = Assembler::AVX_256bit; // Shift lower half, with result in vtmp2 usign vtmp1 as TEMP __ vextendwd(sign, $vtmp2$$XMMRegister, $src$$XMMRegister, vlen_enc); @@ -6327,11 +6338,11 @@ %} instruct vshift16S_var_evex_bw(vec dst, vec src, vec shift) %{ - predicate(vector_element_basic_type(n) == T_SHORT && + predicate(!VectorNode::is_vshift_cnt(n->in(2)) && VM_Version::supports_avx512bw()); - match(Set dst (VLShiftV src shift)); - match(Set dst (VRShiftV src shift)); - match(Set dst (VURShiftV src shift)); + match(Set dst ( LShiftVS src shift)); + match(Set dst ( RShiftVS src shift)); + match(Set dst (URShiftVS src shift)); format %{ "vector_varshift_short $dst,$src,$shift\t!" %} ins_encode %{ assert(UseAVX > 2, "required"); @@ -6348,10 +6359,10 @@ //Integer variable shift instruct vshiftI_var(vec dst, vec src, vec shift) %{ - predicate(vector_element_basic_type(n) == T_INT); - match(Set dst ( VLShiftV src shift)); - match(Set dst ( VRShiftV src shift)); - match(Set dst (VURShiftV src shift)); + predicate(!VectorNode::is_vshift_cnt(n->in(2))); + match(Set dst ( LShiftVI src shift)); + match(Set dst ( RShiftVI src shift)); + match(Set dst (URShiftVI src shift)); format %{ "vector_varshift_int $dst,$src,$shift\t!" %} ins_encode %{ assert(UseAVX >= 2, "required"); @@ -6365,9 +6376,9 @@ //Long variable shift instruct vshiftL_var(vec dst, vec src, vec shift) %{ - predicate(vector_element_basic_type(n) == T_LONG); - match(Set dst ( VLShiftV src shift)); - match(Set dst (VURShiftV src shift)); + predicate(!VectorNode::is_vshift_cnt(n->in(2))); + match(Set dst ( LShiftVL src shift)); + match(Set dst (URShiftVL src shift)); format %{ "vector_varshift_long $dst,$src,$shift\t!" %} ins_encode %{ assert(UseAVX >= 2, "required"); @@ -6381,9 +6392,10 @@ //Long variable right shift arithmetic instruct vshiftL_arith_var(vec dst, vec src, vec shift, vec vtmp) %{ - predicate(vector_length(n) <= 4 && vector_element_basic_type(n) == T_LONG && + predicate(vector_length(n) <= 4 && + !VectorNode::is_vshift_cnt(n->in(2)) && UseAVX == 2); - match(Set dst (VRShiftV src shift)); + match(Set dst (RShiftVL src shift)); effect(TEMP dst, TEMP vtmp); format %{ "vector_varshift_long $dst,$src,$shift\n\t! using $vtmp as TEMP" %} ins_encode %{ @@ -6396,9 +6408,9 @@ %} instruct vshiftL_arith_var_evex(vec dst, vec src, vec shift) %{ - predicate(vector_element_basic_type(n) == T_LONG && + predicate(!VectorNode::is_vshift_cnt(n->in(2)) && UseAVX > 2); - match(Set dst (VRShiftV src shift)); + match(Set dst (RShiftVL src shift)); format %{ "vector_varfshift_long $dst,$src,$shift\t!" %} ins_encode %{ int opcode = this->ideal_Opcode(); @@ -6834,10 +6846,11 @@ ins_encode %{ int vlen_enc = vector_length_encoding(this, $src1); Assembler::ComparisonPredicateFP cmp = booltest_pred_to_comparison_pred_fp($cond$$constant); - if (vector_element_basic_type(this, $src1) == T_FLOAT) + if (vector_element_basic_type(this, $src1) == T_FLOAT) { __ vcmpps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, cmp, vlen_enc); - else + } else { __ vcmppd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, cmp, vlen_enc); + } %} ins_pipe( pipe_slow ); %} @@ -7216,48 +7229,6 @@ ins_pipe( pipe_slow ); %} -//------------------------------------- NOT -------------------------------------------- - -instruct vnotB(vec dst, vec src) %{ - predicate(UseAVX == 0); - match(Set dst (NotV src)); - effect(TEMP dst); - format %{ "vector_not $dst,$src\t!" %} - ins_encode %{ - int vlen = vector_length_in_bytes(this); - switch(vlen) { - default: - assert(0, "Incorrect vector length"); - break; - case 4: { - __ movdl($dst$$XMMRegister, ExternalAddress(vector_all_bits_set())); - __ pxor($dst$$XMMRegister, $src$$XMMRegister); - } break; - case 8: { - __ movq($dst$$XMMRegister, ExternalAddress(vector_all_bits_set())); - __ pxor($dst$$XMMRegister, $src$$XMMRegister); - } break; - case 16: { - __ movdqu($dst$$XMMRegister, ExternalAddress(vector_all_bits_set())); - __ pxor($dst$$XMMRegister, $src$$XMMRegister); - } break; - } - %} - ins_pipe( pipe_slow ); -%} - -instruct vnotB_reg(vec dst, vec src, rRegP scratch) %{ - predicate(UseAVX > 0); - match(Set dst (NotV src)); - effect(TEMP scratch); - format %{ "vector_not $dst,$src\t! using $scratch as rRegP" %} - ins_encode %{ - int vlen_enc = vector_length_encoding(this); - __ vpxor($dst$$XMMRegister, $src$$XMMRegister, ExternalAddress(vector_all_bits_set()), vlen_enc, $scratch$$Register); - %} - ins_pipe( pipe_slow ); -%} - //------------------------------------- VectorTest -------------------------------------------- #ifdef _LP64 @@ -7598,7 +7569,7 @@ instruct rearrangeS_evex(vec dst, vec src, vec shuffle) %{ predicate(vector_element_basic_type(n) == T_SHORT && - VM_Version::supports_avx512bw()); + VM_Version::supports_avx512bw()); match(Set dst (VectorRearrange src shuffle)); format %{ "vector_rearrange $dst, $shuffle, $src" %} ins_encode %{