1 /* 2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_ASSEMBLER_X86_HPP 26 #define CPU_X86_ASSEMBLER_X86_HPP 27 28 #include "asm/register.hpp" 29 #include "runtime/vm_version.hpp" 30 #include "utilities/powerOfTwo.hpp" 31 32 class BiasedLockingCounters; 33 34 // Contains all the definitions needed for x86 assembly code generation. 35 36 // Calling convention 37 class Argument { 38 public: 39 enum { 40 #ifdef _LP64 41 #ifdef _WIN64 42 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) 43 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) 44 #else 45 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) 46 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) 47 #endif // _WIN64 48 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... 49 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... 50 #else 51 n_register_parameters = 0 // 0 registers used to pass arguments 52 #endif // _LP64 53 }; 54 }; 55 56 57 #ifdef _LP64 58 // Symbolically name the register arguments used by the c calling convention. 59 // Windows is different from linux/solaris. So much for standards... 60 61 #ifdef _WIN64 62 63 REGISTER_DECLARATION(Register, c_rarg0, rcx); 64 REGISTER_DECLARATION(Register, c_rarg1, rdx); 65 REGISTER_DECLARATION(Register, c_rarg2, r8); 66 REGISTER_DECLARATION(Register, c_rarg3, r9); 67 68 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); 69 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); 70 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); 71 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); 72 73 #else 74 75 REGISTER_DECLARATION(Register, c_rarg0, rdi); 76 REGISTER_DECLARATION(Register, c_rarg1, rsi); 77 REGISTER_DECLARATION(Register, c_rarg2, rdx); 78 REGISTER_DECLARATION(Register, c_rarg3, rcx); 79 REGISTER_DECLARATION(Register, c_rarg4, r8); 80 REGISTER_DECLARATION(Register, c_rarg5, r9); 81 82 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); 83 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); 84 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); 85 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); 86 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); 87 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); 88 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); 89 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); 90 91 #endif // _WIN64 92 93 // Symbolically name the register arguments used by the Java calling convention. 94 // We have control over the convention for java so we can do what we please. 95 // What pleases us is to offset the java calling convention so that when 96 // we call a suitable jni method the arguments are lined up and we don't 97 // have to do little shuffling. A suitable jni method is non-static and a 98 // small number of arguments (two fewer args on windows) 99 // 100 // |-------------------------------------------------------| 101 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | 102 // |-------------------------------------------------------| 103 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) 104 // | rdi rsi rdx rcx r8 r9 | solaris/linux 105 // |-------------------------------------------------------| 106 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | 107 // |-------------------------------------------------------| 108 109 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); 110 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); 111 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); 112 // Windows runs out of register args here 113 #ifdef _WIN64 114 REGISTER_DECLARATION(Register, j_rarg3, rdi); 115 REGISTER_DECLARATION(Register, j_rarg4, rsi); 116 #else 117 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); 118 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); 119 #endif /* _WIN64 */ 120 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); 121 122 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); 123 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); 124 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); 125 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); 126 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); 127 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); 128 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); 129 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); 130 131 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile 132 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile 133 134 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved 135 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved 136 137 #else 138 // rscratch1 will apear in 32bit code that is dead but of course must compile 139 // Using noreg ensures if the dead code is incorrectly live and executed it 140 // will cause an assertion failure 141 #define rscratch1 noreg 142 #define rscratch2 noreg 143 144 #endif // _LP64 145 146 // JSR 292 147 // On x86, the SP does not have to be saved when invoking method handle intrinsics 148 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg. 149 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg); 150 151 // Address is an abstraction used to represent a memory location 152 // using any of the amd64 addressing modes with one object. 153 // 154 // Note: A register location is represented via a Register, not 155 // via an address for efficiency & simplicity reasons. 156 157 class ArrayAddress; 158 159 class Address { 160 public: 161 enum ScaleFactor { 162 no_scale = -1, 163 times_1 = 0, 164 times_2 = 1, 165 times_4 = 2, 166 times_8 = 3, 167 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) 168 }; 169 static ScaleFactor times(int size) { 170 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); 171 if (size == 8) return times_8; 172 if (size == 4) return times_4; 173 if (size == 2) return times_2; 174 return times_1; 175 } 176 static int scale_size(ScaleFactor scale) { 177 assert(scale != no_scale, ""); 178 assert(((1 << (int)times_1) == 1 && 179 (1 << (int)times_2) == 2 && 180 (1 << (int)times_4) == 4 && 181 (1 << (int)times_8) == 8), ""); 182 return (1 << (int)scale); 183 } 184 185 private: 186 Register _base; 187 Register _index; 188 XMMRegister _xmmindex; 189 ScaleFactor _scale; 190 int _disp; 191 bool _isxmmindex; 192 RelocationHolder _rspec; 193 194 // Easily misused constructors make them private 195 // %%% can we make these go away? 196 NOT_LP64(Address(address loc, RelocationHolder spec);) 197 Address(int disp, address loc, relocInfo::relocType rtype); 198 Address(int disp, address loc, RelocationHolder spec); 199 200 public: 201 202 int disp() { return _disp; } 203 // creation 204 Address() 205 : _base(noreg), 206 _index(noreg), 207 _xmmindex(xnoreg), 208 _scale(no_scale), 209 _disp(0), 210 _isxmmindex(false){ 211 } 212 213 // No default displacement otherwise Register can be implicitly 214 // converted to 0(Register) which is quite a different animal. 215 216 Address(Register base, int disp) 217 : _base(base), 218 _index(noreg), 219 _xmmindex(xnoreg), 220 _scale(no_scale), 221 _disp(disp), 222 _isxmmindex(false){ 223 } 224 225 Address(Register base, Register index, ScaleFactor scale, int disp = 0) 226 : _base (base), 227 _index(index), 228 _xmmindex(xnoreg), 229 _scale(scale), 230 _disp (disp), 231 _isxmmindex(false) { 232 assert(!index->is_valid() == (scale == Address::no_scale), 233 "inconsistent address"); 234 } 235 236 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) 237 : _base (base), 238 _index(index.register_or_noreg()), 239 _xmmindex(xnoreg), 240 _scale(scale), 241 _disp (disp + (index.constant_or_zero() * scale_size(scale))), 242 _isxmmindex(false){ 243 if (!index.is_register()) scale = Address::no_scale; 244 assert(!_index->is_valid() == (scale == Address::no_scale), 245 "inconsistent address"); 246 } 247 248 Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0) 249 : _base (base), 250 _index(noreg), 251 _xmmindex(index), 252 _scale(scale), 253 _disp(disp), 254 _isxmmindex(true) { 255 assert(!index->is_valid() == (scale == Address::no_scale), 256 "inconsistent address"); 257 } 258 259 Address plus_disp(int disp) const { 260 Address a = (*this); 261 a._disp += disp; 262 return a; 263 } 264 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { 265 Address a = (*this); 266 a._disp += disp.constant_or_zero() * scale_size(scale); 267 if (disp.is_register()) { 268 assert(!a.index()->is_valid(), "competing indexes"); 269 a._index = disp.as_register(); 270 a._scale = scale; 271 } 272 return a; 273 } 274 bool is_same_address(Address a) const { 275 // disregard _rspec 276 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; 277 } 278 279 // The following two overloads are used in connection with the 280 // ByteSize type (see sizes.hpp). They simplify the use of 281 // ByteSize'd arguments in assembly code. Note that their equivalent 282 // for the optimized build are the member functions with int disp 283 // argument since ByteSize is mapped to an int type in that case. 284 // 285 // Note: DO NOT introduce similar overloaded functions for WordSize 286 // arguments as in the optimized mode, both ByteSize and WordSize 287 // are mapped to the same type and thus the compiler cannot make a 288 // distinction anymore (=> compiler errors). 289 290 #ifdef ASSERT 291 Address(Register base, ByteSize disp) 292 : _base(base), 293 _index(noreg), 294 _xmmindex(xnoreg), 295 _scale(no_scale), 296 _disp(in_bytes(disp)), 297 _isxmmindex(false){ 298 } 299 300 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) 301 : _base(base), 302 _index(index), 303 _xmmindex(xnoreg), 304 _scale(scale), 305 _disp(in_bytes(disp)), 306 _isxmmindex(false){ 307 assert(!index->is_valid() == (scale == Address::no_scale), 308 "inconsistent address"); 309 } 310 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) 311 : _base (base), 312 _index(index.register_or_noreg()), 313 _xmmindex(xnoreg), 314 _scale(scale), 315 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))), 316 _isxmmindex(false) { 317 if (!index.is_register()) scale = Address::no_scale; 318 assert(!_index->is_valid() == (scale == Address::no_scale), 319 "inconsistent address"); 320 } 321 322 #endif // ASSERT 323 324 // accessors 325 bool uses(Register reg) const { return _base == reg || _index == reg; } 326 Register base() const { return _base; } 327 Register index() const { return _index; } 328 XMMRegister xmmindex() const { return _xmmindex; } 329 ScaleFactor scale() const { return _scale; } 330 int disp() const { return _disp; } 331 bool isxmmindex() const { return _isxmmindex; } 332 333 // Convert the raw encoding form into the form expected by the constructor for 334 // Address. An index of 4 (rsp) corresponds to having no index, so convert 335 // that to noreg for the Address constructor. 336 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); 337 338 static Address make_array(ArrayAddress); 339 340 private: 341 bool base_needs_rex() const { 342 return _base->is_valid() && _base->encoding() >= 8; 343 } 344 345 bool index_needs_rex() const { 346 return _index->is_valid() &&_index->encoding() >= 8; 347 } 348 349 bool xmmindex_needs_rex() const { 350 return _xmmindex->is_valid() && _xmmindex->encoding() >= 8; 351 } 352 353 relocInfo::relocType reloc() const { return _rspec.type(); } 354 355 friend class Assembler; 356 friend class MacroAssembler; 357 friend class LIR_Assembler; // base/index/scale/disp 358 }; 359 360 // 361 // AddressLiteral has been split out from Address because operands of this type 362 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out 363 // the few instructions that need to deal with address literals are unique and the 364 // MacroAssembler does not have to implement every instruction in the Assembler 365 // in order to search for address literals that may need special handling depending 366 // on the instruction and the platform. As small step on the way to merging i486/amd64 367 // directories. 368 // 369 class AddressLiteral { 370 friend class ArrayAddress; 371 RelocationHolder _rspec; 372 // Typically we use AddressLiterals we want to use their rval 373 // However in some situations we want the lval (effect address) of the item. 374 // We provide a special factory for making those lvals. 375 bool _is_lval; 376 377 // If the target is far we'll need to load the ea of this to 378 // a register to reach it. Otherwise if near we can do rip 379 // relative addressing. 380 381 address _target; 382 383 protected: 384 // creation 385 AddressLiteral() 386 : _is_lval(false), 387 _target(NULL) 388 {} 389 390 public: 391 392 393 AddressLiteral(address target, relocInfo::relocType rtype); 394 395 AddressLiteral(address target, RelocationHolder const& rspec) 396 : _rspec(rspec), 397 _is_lval(false), 398 _target(target) 399 {} 400 401 AddressLiteral addr() { 402 AddressLiteral ret = *this; 403 ret._is_lval = true; 404 return ret; 405 } 406 407 408 private: 409 410 address target() { return _target; } 411 bool is_lval() { return _is_lval; } 412 413 relocInfo::relocType reloc() const { return _rspec.type(); } 414 const RelocationHolder& rspec() const { return _rspec; } 415 416 friend class Assembler; 417 friend class MacroAssembler; 418 friend class Address; 419 friend class LIR_Assembler; 420 }; 421 422 // Convience classes 423 class RuntimeAddress: public AddressLiteral { 424 425 public: 426 427 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} 428 429 }; 430 431 class ExternalAddress: public AddressLiteral { 432 private: 433 static relocInfo::relocType reloc_for_target(address target) { 434 // Sometimes ExternalAddress is used for values which aren't 435 // exactly addresses, like the card table base. 436 // external_word_type can't be used for values in the first page 437 // so just skip the reloc in that case. 438 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; 439 } 440 441 public: 442 443 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} 444 445 }; 446 447 class InternalAddress: public AddressLiteral { 448 449 public: 450 451 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} 452 453 }; 454 455 // x86 can do array addressing as a single operation since disp can be an absolute 456 // address amd64 can't. We create a class that expresses the concept but does extra 457 // magic on amd64 to get the final result 458 459 class ArrayAddress { 460 private: 461 462 AddressLiteral _base; 463 Address _index; 464 465 public: 466 467 ArrayAddress() {}; 468 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; 469 AddressLiteral base() { return _base; } 470 Address index() { return _index; } 471 472 }; 473 474 class InstructionAttr; 475 476 // 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes 477 // See fxsave and xsave(EVEX enabled) documentation for layout 478 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize); 479 480 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction 481 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write 482 // is what you get. The Assembler is generating code into a CodeBuffer. 483 484 class Assembler : public AbstractAssembler { 485 friend class AbstractAssembler; // for the non-virtual hack 486 friend class LIR_Assembler; // as_Address() 487 friend class StubGenerator; 488 489 public: 490 enum Condition { // The x86 condition codes used for conditional jumps/moves. 491 zero = 0x4, 492 notZero = 0x5, 493 equal = 0x4, 494 notEqual = 0x5, 495 less = 0xc, 496 lessEqual = 0xe, 497 greater = 0xf, 498 greaterEqual = 0xd, 499 below = 0x2, 500 belowEqual = 0x6, 501 above = 0x7, 502 aboveEqual = 0x3, 503 overflow = 0x0, 504 noOverflow = 0x1, 505 carrySet = 0x2, 506 carryClear = 0x3, 507 negative = 0x8, 508 positive = 0x9, 509 parity = 0xa, 510 noParity = 0xb 511 }; 512 513 enum Prefix { 514 // segment overrides 515 CS_segment = 0x2e, 516 SS_segment = 0x36, 517 DS_segment = 0x3e, 518 ES_segment = 0x26, 519 FS_segment = 0x64, 520 GS_segment = 0x65, 521 522 REX = 0x40, 523 524 REX_B = 0x41, 525 REX_X = 0x42, 526 REX_XB = 0x43, 527 REX_R = 0x44, 528 REX_RB = 0x45, 529 REX_RX = 0x46, 530 REX_RXB = 0x47, 531 532 REX_W = 0x48, 533 534 REX_WB = 0x49, 535 REX_WX = 0x4A, 536 REX_WXB = 0x4B, 537 REX_WR = 0x4C, 538 REX_WRB = 0x4D, 539 REX_WRX = 0x4E, 540 REX_WRXB = 0x4F, 541 542 VEX_3bytes = 0xC4, 543 VEX_2bytes = 0xC5, 544 EVEX_4bytes = 0x62, 545 Prefix_EMPTY = 0x0 546 }; 547 548 enum VexPrefix { 549 VEX_B = 0x20, 550 VEX_X = 0x40, 551 VEX_R = 0x80, 552 VEX_W = 0x80 553 }; 554 555 enum ExexPrefix { 556 EVEX_F = 0x04, 557 EVEX_V = 0x08, 558 EVEX_Rb = 0x10, 559 EVEX_X = 0x40, 560 EVEX_Z = 0x80 561 }; 562 563 enum VexSimdPrefix { 564 VEX_SIMD_NONE = 0x0, 565 VEX_SIMD_66 = 0x1, 566 VEX_SIMD_F3 = 0x2, 567 VEX_SIMD_F2 = 0x3 568 }; 569 570 enum VexOpcode { 571 VEX_OPCODE_NONE = 0x0, 572 VEX_OPCODE_0F = 0x1, 573 VEX_OPCODE_0F_38 = 0x2, 574 VEX_OPCODE_0F_3A = 0x3, 575 VEX_OPCODE_MASK = 0x1F 576 }; 577 578 enum AvxVectorLen { 579 AVX_128bit = 0x0, 580 AVX_256bit = 0x1, 581 AVX_512bit = 0x2, 582 AVX_NoVec = 0x4 583 }; 584 585 enum EvexTupleType { 586 EVEX_FV = 0, 587 EVEX_HV = 4, 588 EVEX_FVM = 6, 589 EVEX_T1S = 7, 590 EVEX_T1F = 11, 591 EVEX_T2 = 13, 592 EVEX_T4 = 15, 593 EVEX_T8 = 17, 594 EVEX_HVM = 18, 595 EVEX_QVM = 19, 596 EVEX_OVM = 20, 597 EVEX_M128 = 21, 598 EVEX_DUP = 22, 599 EVEX_ETUP = 23 600 }; 601 602 enum EvexInputSizeInBits { 603 EVEX_8bit = 0, 604 EVEX_16bit = 1, 605 EVEX_32bit = 2, 606 EVEX_64bit = 3, 607 EVEX_NObit = 4 608 }; 609 610 enum WhichOperand { 611 // input to locate_operand, and format code for relocations 612 imm_operand = 0, // embedded 32-bit|64-bit immediate operand 613 disp32_operand = 1, // embedded 32-bit displacement or address 614 call32_operand = 2, // embedded 32-bit self-relative displacement 615 #ifndef _LP64 616 _WhichOperand_limit = 3 617 #else 618 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop 619 _WhichOperand_limit = 4 620 #endif 621 }; 622 623 // Comparison predicates for integral types & FP types when using SSE 624 enum ComparisonPredicate { 625 eq = 0, 626 lt = 1, 627 le = 2, 628 _false = 3, 629 neq = 4, 630 nlt = 5, 631 nle = 6, 632 _true = 7 633 }; 634 635 // Comparison predicates for FP types when using AVX 636 // O means ordered. U is unordered. When using ordered, any NaN comparison is false. Otherwise, it is true. 637 // S means signaling. Q means non-signaling. When signaling is true, instruction signals #IA on NaN. 638 enum ComparisonPredicateFP { 639 EQ_OQ = 0, 640 LT_OS = 1, 641 LE_OS = 2, 642 UNORD_Q = 3, 643 NEQ_UQ = 4, 644 NLT_US = 5, 645 NLE_US = 6, 646 ORD_Q = 7, 647 EQ_UQ = 8, 648 NGE_US = 9, 649 NGT_US = 0xA, 650 FALSE_OQ = 0XB, 651 NEQ_OQ = 0xC, 652 GE_OS = 0xD, 653 GT_OS = 0xE, 654 TRUE_UQ = 0xF, 655 EQ_OS = 0x10, 656 LT_OQ = 0x11, 657 LE_OQ = 0x12, 658 UNORD_S = 0x13, 659 NEQ_US = 0x14, 660 NLT_UQ = 0x15, 661 NLE_UQ = 0x16, 662 ORD_S = 0x17, 663 EQ_US = 0x18, 664 NGE_UQ = 0x19, 665 NGT_UQ = 0x1A, 666 FALSE_OS = 0x1B, 667 NEQ_OS = 0x1C, 668 GE_OQ = 0x1D, 669 GT_OQ = 0x1E, 670 TRUE_US =0x1F 671 }; 672 673 enum Width { 674 B = 0, 675 W = 1, 676 D = 2, 677 Q = 3 678 }; 679 680 //---< calculate length of instruction >--- 681 // As instruction size can't be found out easily on x86/x64, 682 // we just use '4' for len and maxlen. 683 // instruction must start at passed address 684 static unsigned int instr_len(unsigned char *instr) { return 4; } 685 686 //---< longest instructions >--- 687 // Max instruction length is not specified in architecture documentation. 688 // We could use a "safe enough" estimate (15), but just default to 689 // instruction length guess from above. 690 static unsigned int instr_maxlen() { return 4; } 691 692 // NOTE: The general philopsophy of the declarations here is that 64bit versions 693 // of instructions are freely declared without the need for wrapping them an ifdef. 694 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) 695 // In the .cpp file the implementations are wrapped so that they are dropped out 696 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL 697 // to the size it was prior to merging up the 32bit and 64bit assemblers. 698 // 699 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction 700 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. 701 702 private: 703 704 bool _legacy_mode_bw; 705 bool _legacy_mode_dq; 706 bool _legacy_mode_vl; 707 bool _legacy_mode_vlbw; 708 NOT_LP64(bool _is_managed;) 709 710 class InstructionAttr *_attributes; 711 712 // 64bit prefixes 713 void prefix(Register reg); 714 void prefix(Register dst, Register src, Prefix p); 715 void prefix(Register dst, Address adr, Prefix p); 716 717 void prefix(Address adr); 718 void prefix(Address adr, Register reg, bool byteinst = false); 719 void prefix(Address adr, XMMRegister reg); 720 721 int prefix_and_encode(int reg_enc, bool byteinst = false); 722 int prefix_and_encode(int dst_enc, int src_enc) { 723 return prefix_and_encode(dst_enc, false, src_enc, false); 724 } 725 int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte); 726 727 // Some prefixq variants always emit exactly one prefix byte, so besides a 728 // prefix-emitting method we provide a method to get the prefix byte to emit, 729 // which can then be folded into a byte stream. 730 int8_t get_prefixq(Address adr); 731 int8_t get_prefixq(Address adr, Register reg); 732 733 void prefixq(Address adr); 734 void prefixq(Address adr, Register reg); 735 void prefixq(Address adr, XMMRegister reg); 736 737 int prefixq_and_encode(int reg_enc); 738 int prefixq_and_encode(int dst_enc, int src_enc); 739 740 void rex_prefix(Address adr, XMMRegister xreg, 741 VexSimdPrefix pre, VexOpcode opc, bool rex_w); 742 int rex_prefix_and_encode(int dst_enc, int src_enc, 743 VexSimdPrefix pre, VexOpcode opc, bool rex_w); 744 745 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc); 746 747 void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, 748 int nds_enc, VexSimdPrefix pre, VexOpcode opc); 749 750 void vex_prefix(Address adr, int nds_enc, int xreg_enc, 751 VexSimdPrefix pre, VexOpcode opc, 752 InstructionAttr *attributes); 753 754 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, 755 VexSimdPrefix pre, VexOpcode opc, 756 InstructionAttr *attributes); 757 758 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, 759 VexOpcode opc, InstructionAttr *attributes); 760 761 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, 762 VexOpcode opc, InstructionAttr *attributes); 763 764 // Helper functions for groups of instructions 765 void emit_arith_b(int op1, int op2, Register dst, int imm8); 766 767 void emit_arith(int op1, int op2, Register dst, int32_t imm32); 768 // Force generation of a 4 byte immediate value even if it fits into 8bit 769 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); 770 void emit_arith(int op1, int op2, Register dst, Register src); 771 772 bool emit_compressed_disp_byte(int &disp); 773 774 void emit_modrm(int mod, int dst_enc, int src_enc); 775 void emit_modrm_disp8(int mod, int dst_enc, int src_enc, 776 int disp); 777 void emit_modrm_sib(int mod, int dst_enc, int src_enc, 778 Address::ScaleFactor scale, int index_enc, int base_enc); 779 void emit_modrm_sib_disp8(int mod, int dst_enc, int src_enc, 780 Address::ScaleFactor scale, int index_enc, int base_enc, 781 int disp); 782 783 void emit_operand_helper(int reg_enc, 784 int base_enc, int index_enc, Address::ScaleFactor scale, 785 int disp, 786 RelocationHolder const& rspec, 787 int rip_relative_correction = 0); 788 789 void emit_operand(Register reg, 790 Register base, Register index, Address::ScaleFactor scale, 791 int disp, 792 RelocationHolder const& rspec, 793 int rip_relative_correction = 0); 794 795 void emit_operand(Register reg, 796 Register base, XMMRegister index, Address::ScaleFactor scale, 797 int disp, 798 RelocationHolder const& rspec); 799 800 void emit_operand(XMMRegister xreg, 801 Register base, XMMRegister xindex, Address::ScaleFactor scale, 802 int disp, 803 RelocationHolder const& rspec); 804 805 void emit_operand(Register reg, Address adr, 806 int rip_relative_correction = 0); 807 808 void emit_operand(XMMRegister reg, 809 Register base, Register index, Address::ScaleFactor scale, 810 int disp, 811 RelocationHolder const& rspec); 812 813 void emit_operand(XMMRegister reg, Address adr); 814 815 // Immediate-to-memory forms 816 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); 817 818 protected: 819 #ifdef ASSERT 820 void check_relocation(RelocationHolder const& rspec, int format); 821 #endif 822 823 void emit_data(jint data, relocInfo::relocType rtype, int format); 824 void emit_data(jint data, RelocationHolder const& rspec, int format); 825 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); 826 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); 827 828 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); 829 830 // These are all easily abused and hence protected 831 832 // 32BIT ONLY SECTION 833 #ifndef _LP64 834 // Make these disappear in 64bit mode since they would never be correct 835 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 836 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 837 838 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 839 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 840 841 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 842 #else 843 // 64BIT ONLY SECTION 844 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY 845 846 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); 847 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); 848 849 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); 850 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); 851 #endif // _LP64 852 853 // These are unique in that we are ensured by the caller that the 32bit 854 // relative in these instructions will always be able to reach the potentially 855 // 64bit address described by entry. Since they can take a 64bit address they 856 // don't have the 32 suffix like the other instructions in this class. 857 858 void call_literal(address entry, RelocationHolder const& rspec); 859 void jmp_literal(address entry, RelocationHolder const& rspec); 860 861 // Avoid using directly section 862 // Instructions in this section are actually usable by anyone without danger 863 // of failure but have performance issues that are addressed my enhanced 864 // instructions which will do the proper thing base on the particular cpu. 865 // We protect them because we don't trust you... 866 867 // Don't use next inc() and dec() methods directly. INC & DEC instructions 868 // could cause a partial flag stall since they don't set CF flag. 869 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods 870 // which call inc() & dec() or add() & sub() in accordance with 871 // the product flag UseIncDec value. 872 873 void decl(Register dst); 874 void decl(Address dst); 875 void decq(Register dst); 876 void decq(Address dst); 877 878 void incl(Register dst); 879 void incl(Address dst); 880 void incq(Register dst); 881 void incq(Address dst); 882 883 // New cpus require use of movsd and movss to avoid partial register stall 884 // when loading from memory. But for old Opteron use movlpd instead of movsd. 885 // The selection is done in MacroAssembler::movdbl() and movflt(). 886 887 // Move Scalar Single-Precision Floating-Point Values 888 void movss(XMMRegister dst, Address src); 889 void movss(XMMRegister dst, XMMRegister src); 890 void movss(Address dst, XMMRegister src); 891 892 // Move Scalar Double-Precision Floating-Point Values 893 void movsd(XMMRegister dst, Address src); 894 void movsd(XMMRegister dst, XMMRegister src); 895 void movsd(Address dst, XMMRegister src); 896 void movlpd(XMMRegister dst, Address src); 897 898 // New cpus require use of movaps and movapd to avoid partial register stall 899 // when moving between registers. 900 void movaps(XMMRegister dst, XMMRegister src); 901 void movapd(XMMRegister dst, XMMRegister src); 902 903 // End avoid using directly 904 905 906 // Instruction prefixes 907 void prefix(Prefix p); 908 909 public: 910 911 // Creation 912 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 913 init_attributes(); 914 } 915 916 // Decoding 917 static address locate_operand(address inst, WhichOperand which); 918 static address locate_next_instruction(address inst); 919 920 // Utilities 921 static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len, 922 int cur_tuple_type, int in_size_in_bits, int cur_encoding); 923 924 // Generic instructions 925 // Does 32bit or 64bit as needed for the platform. In some sense these 926 // belong in macro assembler but there is no need for both varieties to exist 927 928 void init_attributes(void) { 929 _legacy_mode_bw = (VM_Version::supports_avx512bw() == false); 930 _legacy_mode_dq = (VM_Version::supports_avx512dq() == false); 931 _legacy_mode_vl = (VM_Version::supports_avx512vl() == false); 932 _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false); 933 NOT_LP64(_is_managed = false;) 934 _attributes = NULL; 935 } 936 937 void set_attributes(InstructionAttr *attributes) { _attributes = attributes; } 938 void clear_attributes(void) { _attributes = NULL; } 939 940 void set_managed(void) { NOT_LP64(_is_managed = true;) } 941 void clear_managed(void) { NOT_LP64(_is_managed = false;) } 942 bool is_managed(void) { 943 NOT_LP64(return _is_managed;) 944 LP64_ONLY(return false;) } 945 946 void lea(Register dst, Address src); 947 948 void mov(Register dst, Register src); 949 950 #ifdef _LP64 951 // support caching the result of some routines 952 953 // must be called before pusha(), popa(), vzeroupper() - checked with asserts 954 static void precompute_instructions(); 955 956 void pusha_uncached(); 957 void popa_uncached(); 958 #endif 959 void vzeroupper_uncached(); 960 961 void pusha(); 962 void popa(); 963 964 void pushf(); 965 void popf(); 966 967 void push(int32_t imm32); 968 969 void push(Register src); 970 971 void pop(Register dst); 972 973 // These are dummies to prevent surprise implicit conversions to Register 974 void push(void* v); 975 void pop(void* v); 976 977 // These do register sized moves/scans 978 void rep_mov(); 979 void rep_stos(); 980 void rep_stosb(); 981 void repne_scan(); 982 #ifdef _LP64 983 void repne_scanl(); 984 #endif 985 986 // Vanilla instructions in lexical order 987 988 void adcl(Address dst, int32_t imm32); 989 void adcl(Address dst, Register src); 990 void adcl(Register dst, int32_t imm32); 991 void adcl(Register dst, Address src); 992 void adcl(Register dst, Register src); 993 994 void adcq(Register dst, int32_t imm32); 995 void adcq(Register dst, Address src); 996 void adcq(Register dst, Register src); 997 998 void addb(Address dst, int imm8); 999 void addw(Register dst, Register src); 1000 void addw(Address dst, int imm16); 1001 1002 void addl(Address dst, int32_t imm32); 1003 void addl(Address dst, Register src); 1004 void addl(Register dst, int32_t imm32); 1005 void addl(Register dst, Address src); 1006 void addl(Register dst, Register src); 1007 1008 void addq(Address dst, int32_t imm32); 1009 void addq(Address dst, Register src); 1010 void addq(Register dst, int32_t imm32); 1011 void addq(Register dst, Address src); 1012 void addq(Register dst, Register src); 1013 1014 #ifdef _LP64 1015 //Add Unsigned Integers with Carry Flag 1016 void adcxq(Register dst, Register src); 1017 1018 //Add Unsigned Integers with Overflow Flag 1019 void adoxq(Register dst, Register src); 1020 #endif 1021 1022 void addr_nop_4(); 1023 void addr_nop_5(); 1024 void addr_nop_7(); 1025 void addr_nop_8(); 1026 1027 // Add Scalar Double-Precision Floating-Point Values 1028 void addsd(XMMRegister dst, Address src); 1029 void addsd(XMMRegister dst, XMMRegister src); 1030 1031 // Add Scalar Single-Precision Floating-Point Values 1032 void addss(XMMRegister dst, Address src); 1033 void addss(XMMRegister dst, XMMRegister src); 1034 1035 // AES instructions 1036 void aesdec(XMMRegister dst, Address src); 1037 void aesdec(XMMRegister dst, XMMRegister src); 1038 void aesdeclast(XMMRegister dst, Address src); 1039 void aesdeclast(XMMRegister dst, XMMRegister src); 1040 void aesenc(XMMRegister dst, Address src); 1041 void aesenc(XMMRegister dst, XMMRegister src); 1042 void aesenclast(XMMRegister dst, Address src); 1043 void aesenclast(XMMRegister dst, XMMRegister src); 1044 // Vector AES instructions 1045 void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1046 void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1047 void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1048 void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1049 1050 void andw(Register dst, Register src); 1051 1052 void andl(Address dst, int32_t imm32); 1053 void andl(Register dst, int32_t imm32); 1054 void andl(Register dst, Address src); 1055 void andl(Register dst, Register src); 1056 1057 void andq(Address dst, int32_t imm32); 1058 void andq(Register dst, int32_t imm32); 1059 void andq(Register dst, Address src); 1060 void andq(Register dst, Register src); 1061 1062 // BMI instructions 1063 void andnl(Register dst, Register src1, Register src2); 1064 void andnl(Register dst, Register src1, Address src2); 1065 void andnq(Register dst, Register src1, Register src2); 1066 void andnq(Register dst, Register src1, Address src2); 1067 1068 void blsil(Register dst, Register src); 1069 void blsil(Register dst, Address src); 1070 void blsiq(Register dst, Register src); 1071 void blsiq(Register dst, Address src); 1072 1073 void blsmskl(Register dst, Register src); 1074 void blsmskl(Register dst, Address src); 1075 void blsmskq(Register dst, Register src); 1076 void blsmskq(Register dst, Address src); 1077 1078 void blsrl(Register dst, Register src); 1079 void blsrl(Register dst, Address src); 1080 void blsrq(Register dst, Register src); 1081 void blsrq(Register dst, Address src); 1082 1083 void bsfl(Register dst, Register src); 1084 void bsrl(Register dst, Register src); 1085 1086 #ifdef _LP64 1087 void bsfq(Register dst, Register src); 1088 void bsrq(Register dst, Register src); 1089 #endif 1090 1091 void bswapl(Register reg); 1092 1093 void bswapq(Register reg); 1094 1095 void call(Label& L, relocInfo::relocType rtype); 1096 void call(Register reg); // push pc; pc <- reg 1097 void call(Address adr); // push pc; pc <- adr 1098 1099 void cdql(); 1100 1101 void cdqq(); 1102 1103 void cld(); 1104 1105 void clflush(Address adr); 1106 void clflushopt(Address adr); 1107 void clwb(Address adr); 1108 1109 void cmovl(Condition cc, Register dst, Register src); 1110 void cmovl(Condition cc, Register dst, Address src); 1111 1112 void cmovq(Condition cc, Register dst, Register src); 1113 void cmovq(Condition cc, Register dst, Address src); 1114 1115 1116 void cmpb(Address dst, int imm8); 1117 1118 void cmpl(Address dst, int32_t imm32); 1119 1120 void cmpl(Register dst, int32_t imm32); 1121 void cmpl(Register dst, Register src); 1122 void cmpl(Register dst, Address src); 1123 1124 void cmpq(Address dst, int32_t imm32); 1125 void cmpq(Address dst, Register src); 1126 1127 void cmpq(Register dst, int32_t imm32); 1128 void cmpq(Register dst, Register src); 1129 void cmpq(Register dst, Address src); 1130 1131 // these are dummies used to catch attempting to convert NULL to Register 1132 void cmpl(Register dst, void* junk); // dummy 1133 void cmpq(Register dst, void* junk); // dummy 1134 1135 void cmpw(Address dst, int imm16); 1136 1137 void cmpxchg8 (Address adr); 1138 1139 void cmpxchgb(Register reg, Address adr); 1140 void cmpxchgl(Register reg, Address adr); 1141 1142 void cmpxchgq(Register reg, Address adr); 1143 1144 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 1145 void comisd(XMMRegister dst, Address src); 1146 void comisd(XMMRegister dst, XMMRegister src); 1147 1148 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 1149 void comiss(XMMRegister dst, Address src); 1150 void comiss(XMMRegister dst, XMMRegister src); 1151 1152 // Identify processor type and features 1153 void cpuid(); 1154 1155 // CRC32C 1156 void crc32(Register crc, Register v, int8_t sizeInBytes); 1157 void crc32(Register crc, Address adr, int8_t sizeInBytes); 1158 1159 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value 1160 void cvtsd2ss(XMMRegister dst, XMMRegister src); 1161 void cvtsd2ss(XMMRegister dst, Address src); 1162 1163 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value 1164 void cvtsi2sdl(XMMRegister dst, Register src); 1165 void cvtsi2sdl(XMMRegister dst, Address src); 1166 void cvtsi2sdq(XMMRegister dst, Register src); 1167 void cvtsi2sdq(XMMRegister dst, Address src); 1168 1169 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value 1170 void cvtsi2ssl(XMMRegister dst, Register src); 1171 void cvtsi2ssl(XMMRegister dst, Address src); 1172 void cvtsi2ssq(XMMRegister dst, Register src); 1173 void cvtsi2ssq(XMMRegister dst, Address src); 1174 1175 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value 1176 void cvtdq2pd(XMMRegister dst, XMMRegister src); 1177 void vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len); 1178 1179 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value 1180 void cvtdq2ps(XMMRegister dst, XMMRegister src); 1181 void vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len); 1182 1183 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value 1184 void cvtss2sd(XMMRegister dst, XMMRegister src); 1185 void cvtss2sd(XMMRegister dst, Address src); 1186 1187 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer 1188 void cvttsd2sil(Register dst, Address src); 1189 void cvttsd2sil(Register dst, XMMRegister src); 1190 void cvttsd2siq(Register dst, Address src); 1191 void cvttsd2siq(Register dst, XMMRegister src); 1192 1193 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer 1194 void cvttss2sil(Register dst, XMMRegister src); 1195 void cvttss2siq(Register dst, XMMRegister src); 1196 1197 // Convert vector double to int 1198 void cvttpd2dq(XMMRegister dst, XMMRegister src); 1199 1200 // Convert vector float and double 1201 void vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len); 1202 void vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len); 1203 1204 // Convert vector long to vector FP 1205 void evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len); 1206 void evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len); 1207 1208 // Evex casts with truncation 1209 void evpmovwb(XMMRegister dst, XMMRegister src, int vector_len); 1210 void evpmovdw(XMMRegister dst, XMMRegister src, int vector_len); 1211 void evpmovdb(XMMRegister dst, XMMRegister src, int vector_len); 1212 void evpmovqd(XMMRegister dst, XMMRegister src, int vector_len); 1213 void evpmovqb(XMMRegister dst, XMMRegister src, int vector_len); 1214 void evpmovqw(XMMRegister dst, XMMRegister src, int vector_len); 1215 1216 //Abs of packed Integer values 1217 void pabsb(XMMRegister dst, XMMRegister src); 1218 void pabsw(XMMRegister dst, XMMRegister src); 1219 void pabsd(XMMRegister dst, XMMRegister src); 1220 void vpabsb(XMMRegister dst, XMMRegister src, int vector_len); 1221 void vpabsw(XMMRegister dst, XMMRegister src, int vector_len); 1222 void vpabsd(XMMRegister dst, XMMRegister src, int vector_len); 1223 void evpabsq(XMMRegister dst, XMMRegister src, int vector_len); 1224 1225 // Divide Scalar Double-Precision Floating-Point Values 1226 void divsd(XMMRegister dst, Address src); 1227 void divsd(XMMRegister dst, XMMRegister src); 1228 1229 // Divide Scalar Single-Precision Floating-Point Values 1230 void divss(XMMRegister dst, Address src); 1231 void divss(XMMRegister dst, XMMRegister src); 1232 1233 1234 #ifndef _LP64 1235 private: 1236 // operands that only take the original 32bit registers 1237 void emit_operand32(Register reg, Address adr); 1238 1239 void emit_farith(int b1, int b2, int i); 1240 1241 public: 1242 void emms(); 1243 1244 void fabs(); 1245 1246 void fadd(int i); 1247 1248 void fadd_d(Address src); 1249 void fadd_s(Address src); 1250 1251 // "Alternate" versions of x87 instructions place result down in FPU 1252 // stack instead of on TOS 1253 1254 void fadda(int i); // "alternate" fadd 1255 void faddp(int i = 1); 1256 1257 void fchs(); 1258 1259 void fcom(int i); 1260 1261 void fcomp(int i = 1); 1262 void fcomp_d(Address src); 1263 void fcomp_s(Address src); 1264 1265 void fcompp(); 1266 1267 void fcos(); 1268 1269 void fdecstp(); 1270 1271 void fdiv(int i); 1272 void fdiv_d(Address src); 1273 void fdivr_s(Address src); 1274 void fdiva(int i); // "alternate" fdiv 1275 void fdivp(int i = 1); 1276 1277 void fdivr(int i); 1278 void fdivr_d(Address src); 1279 void fdiv_s(Address src); 1280 1281 void fdivra(int i); // "alternate" reversed fdiv 1282 1283 void fdivrp(int i = 1); 1284 1285 void ffree(int i = 0); 1286 1287 void fild_d(Address adr); 1288 void fild_s(Address adr); 1289 1290 void fincstp(); 1291 1292 void finit(); 1293 1294 void fist_s (Address adr); 1295 void fistp_d(Address adr); 1296 void fistp_s(Address adr); 1297 1298 void fld1(); 1299 1300 void fld_d(Address adr); 1301 void fld_s(Address adr); 1302 void fld_s(int index); 1303 void fld_x(Address adr); // extended-precision (80-bit) format 1304 1305 void fldcw(Address src); 1306 1307 void fldenv(Address src); 1308 1309 void fldlg2(); 1310 1311 void fldln2(); 1312 1313 void fldz(); 1314 1315 void flog(); 1316 void flog10(); 1317 1318 void fmul(int i); 1319 1320 void fmul_d(Address src); 1321 void fmul_s(Address src); 1322 1323 void fmula(int i); // "alternate" fmul 1324 1325 void fmulp(int i = 1); 1326 1327 void fnsave(Address dst); 1328 1329 void fnstcw(Address src); 1330 1331 void fnstsw_ax(); 1332 1333 void fprem(); 1334 void fprem1(); 1335 1336 void frstor(Address src); 1337 1338 void fsin(); 1339 1340 void fsqrt(); 1341 1342 void fst_d(Address adr); 1343 void fst_s(Address adr); 1344 1345 void fstp_d(Address adr); 1346 void fstp_d(int index); 1347 void fstp_s(Address adr); 1348 void fstp_x(Address adr); // extended-precision (80-bit) format 1349 1350 void fsub(int i); 1351 void fsub_d(Address src); 1352 void fsub_s(Address src); 1353 1354 void fsuba(int i); // "alternate" fsub 1355 1356 void fsubp(int i = 1); 1357 1358 void fsubr(int i); 1359 void fsubr_d(Address src); 1360 void fsubr_s(Address src); 1361 1362 void fsubra(int i); // "alternate" reversed fsub 1363 1364 void fsubrp(int i = 1); 1365 1366 void ftan(); 1367 1368 void ftst(); 1369 1370 void fucomi(int i = 1); 1371 void fucomip(int i = 1); 1372 1373 void fwait(); 1374 1375 void fxch(int i = 1); 1376 1377 void fyl2x(); 1378 void frndint(); 1379 void f2xm1(); 1380 void fldl2e(); 1381 #endif // !_LP64 1382 1383 void fxrstor(Address src); 1384 void xrstor(Address src); 1385 1386 void fxsave(Address dst); 1387 void xsave(Address dst); 1388 1389 void hlt(); 1390 1391 void idivl(Register src); 1392 void divl(Register src); // Unsigned division 1393 1394 #ifdef _LP64 1395 void idivq(Register src); 1396 #endif 1397 1398 void imull(Register src); 1399 void imull(Register dst, Register src); 1400 void imull(Register dst, Register src, int value); 1401 void imull(Register dst, Address src); 1402 1403 #ifdef _LP64 1404 void imulq(Register dst, Register src); 1405 void imulq(Register dst, Register src, int value); 1406 void imulq(Register dst, Address src); 1407 #endif 1408 1409 // jcc is the generic conditional branch generator to run- 1410 // time routines, jcc is used for branches to labels. jcc 1411 // takes a branch opcode (cc) and a label (L) and generates 1412 // either a backward branch or a forward branch and links it 1413 // to the label fixup chain. Usage: 1414 // 1415 // Label L; // unbound label 1416 // jcc(cc, L); // forward branch to unbound label 1417 // bind(L); // bind label to the current pc 1418 // jcc(cc, L); // backward branch to bound label 1419 // bind(L); // illegal: a label may be bound only once 1420 // 1421 // Note: The same Label can be used for forward and backward branches 1422 // but it may be bound only once. 1423 1424 void jcc(Condition cc, Label& L, bool maybe_short = true); 1425 1426 // Conditional jump to a 8-bit offset to L. 1427 // WARNING: be very careful using this for forward jumps. If the label is 1428 // not bound within an 8-bit offset of this instruction, a run-time error 1429 // will occur. 1430 1431 // Use macro to record file and line number. 1432 #define jccb(cc, L) jccb_0(cc, L, __FILE__, __LINE__) 1433 1434 void jccb_0(Condition cc, Label& L, const char* file, int line); 1435 1436 void jmp(Address entry); // pc <- entry 1437 1438 // Label operations & relative jumps (PPUM Appendix D) 1439 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L 1440 1441 void jmp(Register entry); // pc <- entry 1442 1443 // Unconditional 8-bit offset jump to L. 1444 // WARNING: be very careful using this for forward jumps. If the label is 1445 // not bound within an 8-bit offset of this instruction, a run-time error 1446 // will occur. 1447 1448 // Use macro to record file and line number. 1449 #define jmpb(L) jmpb_0(L, __FILE__, __LINE__) 1450 1451 void jmpb_0(Label& L, const char* file, int line); 1452 1453 void ldmxcsr( Address src ); 1454 1455 void leal(Register dst, Address src); 1456 1457 void leaq(Register dst, Address src); 1458 1459 void lfence(); 1460 1461 void lock(); 1462 1463 void lzcntl(Register dst, Register src); 1464 1465 #ifdef _LP64 1466 void lzcntq(Register dst, Register src); 1467 #endif 1468 1469 enum Membar_mask_bits { 1470 StoreStore = 1 << 3, 1471 LoadStore = 1 << 2, 1472 StoreLoad = 1 << 1, 1473 LoadLoad = 1 << 0 1474 }; 1475 1476 // Serializes memory and blows flags 1477 void membar(Membar_mask_bits order_constraint) { 1478 // We only have to handle StoreLoad 1479 if (order_constraint & StoreLoad) { 1480 // All usable chips support "locked" instructions which suffice 1481 // as barriers, and are much faster than the alternative of 1482 // using cpuid instruction. We use here a locked add [esp-C],0. 1483 // This is conveniently otherwise a no-op except for blowing 1484 // flags, and introducing a false dependency on target memory 1485 // location. We can't do anything with flags, but we can avoid 1486 // memory dependencies in the current method by locked-adding 1487 // somewhere else on the stack. Doing [esp+C] will collide with 1488 // something on stack in current method, hence we go for [esp-C]. 1489 // It is convenient since it is almost always in data cache, for 1490 // any small C. We need to step back from SP to avoid data 1491 // dependencies with other things on below SP (callee-saves, for 1492 // example). Without a clear way to figure out the minimal safe 1493 // distance from SP, it makes sense to step back the complete 1494 // cache line, as this will also avoid possible second-order effects 1495 // with locked ops against the cache line. Our choice of offset 1496 // is bounded by x86 operand encoding, which should stay within 1497 // [-128; +127] to have the 8-byte displacement encoding. 1498 // 1499 // Any change to this code may need to revisit other places in 1500 // the code where this idiom is used, in particular the 1501 // orderAccess code. 1502 1503 int offset = -VM_Version::L1_line_size(); 1504 if (offset < -128) { 1505 offset = -128; 1506 } 1507 1508 lock(); 1509 addl(Address(rsp, offset), 0);// Assert the lock# signal here 1510 } 1511 } 1512 1513 void mfence(); 1514 void sfence(); 1515 1516 // Moves 1517 1518 void mov64(Register dst, int64_t imm64); 1519 1520 void movb(Address dst, Register src); 1521 void movb(Address dst, int imm8); 1522 void movb(Register dst, Address src); 1523 1524 void movddup(XMMRegister dst, XMMRegister src); 1525 1526 void kmovbl(KRegister dst, Register src); 1527 void kmovbl(Register dst, KRegister src); 1528 void kmovwl(KRegister dst, Register src); 1529 void kmovwl(KRegister dst, Address src); 1530 void kmovwl(Register dst, KRegister src); 1531 void kmovdl(KRegister dst, Register src); 1532 void kmovdl(Register dst, KRegister src); 1533 void kmovql(KRegister dst, KRegister src); 1534 void kmovql(Address dst, KRegister src); 1535 void kmovql(KRegister dst, Address src); 1536 void kmovql(KRegister dst, Register src); 1537 void kmovql(Register dst, KRegister src); 1538 1539 void knotwl(KRegister dst, KRegister src); 1540 1541 void kortestbl(KRegister dst, KRegister src); 1542 void kortestwl(KRegister dst, KRegister src); 1543 void kortestdl(KRegister dst, KRegister src); 1544 void kortestql(KRegister dst, KRegister src); 1545 1546 void ktestq(KRegister src1, KRegister src2); 1547 void ktestd(KRegister src1, KRegister src2); 1548 1549 void ktestql(KRegister dst, KRegister src); 1550 1551 void movdl(XMMRegister dst, Register src); 1552 void movdl(Register dst, XMMRegister src); 1553 void movdl(XMMRegister dst, Address src); 1554 void movdl(Address dst, XMMRegister src); 1555 1556 // Move Double Quadword 1557 void movdq(XMMRegister dst, Register src); 1558 void movdq(Register dst, XMMRegister src); 1559 1560 // Move Aligned Double Quadword 1561 void movdqa(XMMRegister dst, XMMRegister src); 1562 void movdqa(XMMRegister dst, Address src); 1563 1564 // Move Unaligned Double Quadword 1565 void movdqu(Address dst, XMMRegister src); 1566 void movdqu(XMMRegister dst, Address src); 1567 void movdqu(XMMRegister dst, XMMRegister src); 1568 1569 // Move Unaligned 256bit Vector 1570 void vmovdqu(Address dst, XMMRegister src); 1571 void vmovdqu(XMMRegister dst, Address src); 1572 void vmovdqu(XMMRegister dst, XMMRegister src); 1573 1574 // Move Unaligned 512bit Vector 1575 void evmovdqub(Address dst, XMMRegister src, bool merge, int vector_len); 1576 void evmovdqub(XMMRegister dst, Address src, bool merge, int vector_len); 1577 void evmovdqub(XMMRegister dst, XMMRegister src, bool merge, int vector_len); 1578 void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len); 1579 void evmovdquw(Address dst, XMMRegister src, bool merge, int vector_len); 1580 void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1581 void evmovdquw(XMMRegister dst, Address src, bool merge, int vector_len); 1582 void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len); 1583 void evmovdqul(Address dst, XMMRegister src, int vector_len); 1584 void evmovdqul(XMMRegister dst, Address src, int vector_len); 1585 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len); 1586 void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1587 void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len); 1588 void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1589 void evmovdquq(Address dst, XMMRegister src, int vector_len); 1590 void evmovdquq(XMMRegister dst, Address src, int vector_len); 1591 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len); 1592 void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1593 void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len); 1594 void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1595 1596 // Move lower 64bit to high 64bit in 128bit register 1597 void movlhps(XMMRegister dst, XMMRegister src); 1598 1599 void movl(Register dst, int32_t imm32); 1600 void movl(Address dst, int32_t imm32); 1601 void movl(Register dst, Register src); 1602 void movl(Register dst, Address src); 1603 void movl(Address dst, Register src); 1604 1605 // These dummies prevent using movl from converting a zero (like NULL) into Register 1606 // by giving the compiler two choices it can't resolve 1607 1608 void movl(Address dst, void* junk); 1609 void movl(Register dst, void* junk); 1610 1611 #ifdef _LP64 1612 void movq(Register dst, Register src); 1613 void movq(Register dst, Address src); 1614 void movq(Address dst, Register src); 1615 1616 // These dummies prevent using movq from converting a zero (like NULL) into Register 1617 // by giving the compiler two choices it can't resolve 1618 1619 void movq(Address dst, void* dummy); 1620 void movq(Register dst, void* dummy); 1621 #endif 1622 1623 // Move Quadword 1624 void movq(Address dst, XMMRegister src); 1625 void movq(XMMRegister dst, Address src); 1626 void movq(XMMRegister dst, XMMRegister src); 1627 void movq(Register dst, XMMRegister src); 1628 void movq(XMMRegister dst, Register src); 1629 1630 void movsbl(Register dst, Address src); 1631 void movsbl(Register dst, Register src); 1632 1633 #ifdef _LP64 1634 void movsbq(Register dst, Address src); 1635 void movsbq(Register dst, Register src); 1636 1637 // Move signed 32bit immediate to 64bit extending sign 1638 void movslq(Address dst, int32_t imm64); 1639 void movslq(Register dst, int32_t imm64); 1640 1641 void movslq(Register dst, Address src); 1642 void movslq(Register dst, Register src); 1643 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous 1644 #endif 1645 1646 void movswl(Register dst, Address src); 1647 void movswl(Register dst, Register src); 1648 1649 #ifdef _LP64 1650 void movswq(Register dst, Address src); 1651 void movswq(Register dst, Register src); 1652 #endif 1653 1654 void movw(Address dst, int imm16); 1655 void movw(Register dst, Address src); 1656 void movw(Address dst, Register src); 1657 1658 void movzbl(Register dst, Address src); 1659 void movzbl(Register dst, Register src); 1660 1661 #ifdef _LP64 1662 void movzbq(Register dst, Address src); 1663 void movzbq(Register dst, Register src); 1664 #endif 1665 1666 void movzwl(Register dst, Address src); 1667 void movzwl(Register dst, Register src); 1668 1669 #ifdef _LP64 1670 void movzwq(Register dst, Address src); 1671 void movzwq(Register dst, Register src); 1672 #endif 1673 1674 // Unsigned multiply with RAX destination register 1675 void mull(Address src); 1676 void mull(Register src); 1677 1678 #ifdef _LP64 1679 void mulq(Address src); 1680 void mulq(Register src); 1681 void mulxq(Register dst1, Register dst2, Register src); 1682 #endif 1683 1684 // Multiply Scalar Double-Precision Floating-Point Values 1685 void mulsd(XMMRegister dst, Address src); 1686 void mulsd(XMMRegister dst, XMMRegister src); 1687 1688 // Multiply Scalar Single-Precision Floating-Point Values 1689 void mulss(XMMRegister dst, Address src); 1690 void mulss(XMMRegister dst, XMMRegister src); 1691 1692 void negl(Register dst); 1693 1694 #ifdef _LP64 1695 void negq(Register dst); 1696 #endif 1697 1698 void nop(int i = 1); 1699 1700 void notl(Register dst); 1701 1702 #ifdef _LP64 1703 void notq(Register dst); 1704 1705 void btsq(Address dst, int imm8); 1706 void btrq(Address dst, int imm8); 1707 #endif 1708 1709 void orw(Register dst, Register src); 1710 1711 void orl(Address dst, int32_t imm32); 1712 void orl(Register dst, int32_t imm32); 1713 void orl(Register dst, Address src); 1714 void orl(Register dst, Register src); 1715 void orl(Address dst, Register src); 1716 1717 void orb(Address dst, int imm8); 1718 1719 void orq(Address dst, int32_t imm32); 1720 void orq(Register dst, int32_t imm32); 1721 void orq(Register dst, Address src); 1722 void orq(Register dst, Register src); 1723 1724 // Pack with signed saturation 1725 void packsswb(XMMRegister dst, XMMRegister src); 1726 void vpacksswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1727 void packssdw(XMMRegister dst, XMMRegister src); 1728 void vpackssdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1729 1730 // Pack with unsigned saturation 1731 void packuswb(XMMRegister dst, XMMRegister src); 1732 void packuswb(XMMRegister dst, Address src); 1733 void packusdw(XMMRegister dst, XMMRegister src); 1734 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1735 void vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1736 1737 // Permutations 1738 void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len); 1739 void vpermq(XMMRegister dst, XMMRegister src, int imm8); 1740 void vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1741 void vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1742 void vpermw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1743 void vpermd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 1744 void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1745 void vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8); 1746 void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8); 1747 void vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len); 1748 void vpermilpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len); 1749 void vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len); 1750 void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1751 1752 void pause(); 1753 1754 // Undefined Instruction 1755 void ud2(); 1756 1757 // SSE4.2 string instructions 1758 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); 1759 void pcmpestri(XMMRegister xmm1, Address src, int imm8); 1760 1761 void pcmpeqb(XMMRegister dst, XMMRegister src); 1762 void vpcmpCCbwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len); 1763 1764 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1765 void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len); 1766 void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len); 1767 void evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len); 1768 1769 void vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1770 void evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len); 1771 void evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len); 1772 1773 void evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len); 1774 void evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate of, int vector_len); 1775 void evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len); 1776 1777 void pcmpeqw(XMMRegister dst, XMMRegister src); 1778 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1779 void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len); 1780 void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len); 1781 1782 void vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1783 1784 void pcmpeqd(XMMRegister dst, XMMRegister src); 1785 void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1786 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len); 1787 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len); 1788 1789 void pcmpeqq(XMMRegister dst, XMMRegister src); 1790 void vpcmpCCq(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len); 1791 void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1792 void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len); 1793 void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len); 1794 1795 void pcmpgtq(XMMRegister dst, XMMRegister src); 1796 void vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1797 1798 void pmovmskb(Register dst, XMMRegister src); 1799 void vpmovmskb(Register dst, XMMRegister src); 1800 1801 // SSE 4.1 extract 1802 void pextrd(Register dst, XMMRegister src, int imm8); 1803 void pextrq(Register dst, XMMRegister src, int imm8); 1804 void pextrd(Address dst, XMMRegister src, int imm8); 1805 void pextrq(Address dst, XMMRegister src, int imm8); 1806 void pextrb(Register dst, XMMRegister src, int imm8); 1807 void pextrb(Address dst, XMMRegister src, int imm8); 1808 // SSE 2 extract 1809 void pextrw(Register dst, XMMRegister src, int imm8); 1810 void pextrw(Address dst, XMMRegister src, int imm8); 1811 1812 // SSE 4.1 insert 1813 void pinsrd(XMMRegister dst, Register src, int imm8); 1814 void pinsrq(XMMRegister dst, Register src, int imm8); 1815 void pinsrb(XMMRegister dst, Register src, int imm8); 1816 void pinsrd(XMMRegister dst, Address src, int imm8); 1817 void pinsrq(XMMRegister dst, Address src, int imm8); 1818 void pinsrb(XMMRegister dst, Address src, int imm8); 1819 void insertps(XMMRegister dst, XMMRegister src, int imm8); 1820 // SSE 2 insert 1821 void pinsrw(XMMRegister dst, Register src, int imm8); 1822 void pinsrw(XMMRegister dst, Address src, int imm8); 1823 1824 // AVX insert 1825 void vpinsrd(XMMRegister dst, XMMRegister nds, Register src, int imm8); 1826 void vpinsrb(XMMRegister dst, XMMRegister nds, Register src, int imm8); 1827 void vpinsrq(XMMRegister dst, XMMRegister nds, Register src, int imm8); 1828 void vpinsrw(XMMRegister dst, XMMRegister nds, Register src, int imm8); 1829 void vinsertps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8); 1830 1831 // Zero extend moves 1832 void pmovzxbw(XMMRegister dst, XMMRegister src); 1833 void pmovzxbw(XMMRegister dst, Address src); 1834 void pmovzxbd(XMMRegister dst, XMMRegister src); 1835 void vpmovzxbw( XMMRegister dst, Address src, int vector_len); 1836 void pmovzxdq(XMMRegister dst, XMMRegister src); 1837 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len); 1838 void vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len); 1839 void vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len); 1840 void vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len); 1841 void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len); 1842 1843 // Sign extend moves 1844 void pmovsxbd(XMMRegister dst, XMMRegister src); 1845 void pmovsxbq(XMMRegister dst, XMMRegister src); 1846 void pmovsxbw(XMMRegister dst, XMMRegister src); 1847 void pmovsxwd(XMMRegister dst, XMMRegister src); 1848 void vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len); 1849 void vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len); 1850 void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len); 1851 void vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len); 1852 void vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len); 1853 void vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len); 1854 1855 void evpmovwb(Address dst, XMMRegister src, int vector_len); 1856 void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len); 1857 1858 void vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len); 1859 1860 void evpmovdb(Address dst, XMMRegister src, int vector_len); 1861 1862 // Multiply add 1863 void pmaddwd(XMMRegister dst, XMMRegister src); 1864 void vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1865 // Multiply add accumulate 1866 void evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1867 1868 #ifndef _LP64 // no 32bit push/pop on amd64 1869 void popl(Address dst); 1870 #endif 1871 1872 #ifdef _LP64 1873 void popq(Address dst); 1874 #endif 1875 1876 void popcntl(Register dst, Address src); 1877 void popcntl(Register dst, Register src); 1878 1879 void vpopcntd(XMMRegister dst, XMMRegister src, int vector_len); 1880 1881 #ifdef _LP64 1882 void popcntq(Register dst, Address src); 1883 void popcntq(Register dst, Register src); 1884 #endif 1885 1886 // Prefetches (SSE, SSE2, 3DNOW only) 1887 1888 void prefetchnta(Address src); 1889 void prefetchr(Address src); 1890 void prefetcht0(Address src); 1891 void prefetcht1(Address src); 1892 void prefetcht2(Address src); 1893 void prefetchw(Address src); 1894 1895 // Shuffle Bytes 1896 void pshufb(XMMRegister dst, XMMRegister src); 1897 void pshufb(XMMRegister dst, Address src); 1898 void vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1899 1900 // Shuffle Packed Doublewords 1901 void pshufd(XMMRegister dst, XMMRegister src, int mode); 1902 void pshufd(XMMRegister dst, Address src, int mode); 1903 void vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len); 1904 1905 // Shuffle Packed High/Low Words 1906 void pshufhw(XMMRegister dst, XMMRegister src, int mode); 1907 void pshuflw(XMMRegister dst, XMMRegister src, int mode); 1908 void pshuflw(XMMRegister dst, Address src, int mode); 1909 1910 //shuffle floats and doubles 1911 void pshufps(XMMRegister, XMMRegister, int); 1912 void pshufpd(XMMRegister, XMMRegister, int); 1913 void vpshufps(XMMRegister, XMMRegister, XMMRegister, int, int); 1914 void vpshufpd(XMMRegister, XMMRegister, XMMRegister, int, int); 1915 1916 // Shuffle packed values at 128 bit granularity 1917 void evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len); 1918 1919 // Shift Right by bytes Logical DoubleQuadword Immediate 1920 void psrldq(XMMRegister dst, int shift); 1921 // Shift Left by bytes Logical DoubleQuadword Immediate 1922 void pslldq(XMMRegister dst, int shift); 1923 1924 // Logical Compare 128bit 1925 void ptest(XMMRegister dst, XMMRegister src); 1926 void ptest(XMMRegister dst, Address src); 1927 // Logical Compare 256bit 1928 void vptest(XMMRegister dst, XMMRegister src); 1929 void vptest(XMMRegister dst, Address src); 1930 1931 // Vector compare 1932 void vptest(XMMRegister dst, XMMRegister src, int vector_len); 1933 1934 // Interleave Low Bytes 1935 void punpcklbw(XMMRegister dst, XMMRegister src); 1936 void punpcklbw(XMMRegister dst, Address src); 1937 1938 // Interleave Low Doublewords 1939 void punpckldq(XMMRegister dst, XMMRegister src); 1940 void punpckldq(XMMRegister dst, Address src); 1941 1942 // Interleave Low Quadwords 1943 void punpcklqdq(XMMRegister dst, XMMRegister src); 1944 1945 #ifndef _LP64 // no 32bit push/pop on amd64 1946 void pushl(Address src); 1947 #endif 1948 1949 void pushq(Address src); 1950 1951 void rcll(Register dst, int imm8); 1952 1953 void rclq(Register dst, int imm8); 1954 1955 void rcrq(Register dst, int imm8); 1956 1957 void rcpps(XMMRegister dst, XMMRegister src); 1958 1959 void rcpss(XMMRegister dst, XMMRegister src); 1960 1961 void rdtsc(); 1962 1963 void ret(int imm16); 1964 1965 #ifdef _LP64 1966 void rorq(Register dst, int imm8); 1967 void rorxq(Register dst, Register src, int imm8); 1968 void rorxd(Register dst, Register src, int imm8); 1969 #endif 1970 1971 void sahf(); 1972 1973 void sarl(Register dst, int imm8); 1974 void sarl(Register dst); 1975 1976 void sarq(Register dst, int imm8); 1977 void sarq(Register dst); 1978 1979 void sbbl(Address dst, int32_t imm32); 1980 void sbbl(Register dst, int32_t imm32); 1981 void sbbl(Register dst, Address src); 1982 void sbbl(Register dst, Register src); 1983 1984 void sbbq(Address dst, int32_t imm32); 1985 void sbbq(Register dst, int32_t imm32); 1986 void sbbq(Register dst, Address src); 1987 void sbbq(Register dst, Register src); 1988 1989 void setb(Condition cc, Register dst); 1990 1991 void palignr(XMMRegister dst, XMMRegister src, int imm8); 1992 void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len); 1993 void evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); 1994 1995 void pblendw(XMMRegister dst, XMMRegister src, int imm8); 1996 void vblendps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len); 1997 1998 void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8); 1999 void sha1nexte(XMMRegister dst, XMMRegister src); 2000 void sha1msg1(XMMRegister dst, XMMRegister src); 2001 void sha1msg2(XMMRegister dst, XMMRegister src); 2002 // xmm0 is implicit additional source to the following instruction. 2003 void sha256rnds2(XMMRegister dst, XMMRegister src); 2004 void sha256msg1(XMMRegister dst, XMMRegister src); 2005 void sha256msg2(XMMRegister dst, XMMRegister src); 2006 2007 void shldl(Register dst, Register src); 2008 void shldl(Register dst, Register src, int8_t imm8); 2009 void shrdl(Register dst, Register src); 2010 void shrdl(Register dst, Register src, int8_t imm8); 2011 2012 void shll(Register dst, int imm8); 2013 void shll(Register dst); 2014 2015 void shlq(Register dst, int imm8); 2016 void shlq(Register dst); 2017 2018 void shrl(Register dst, int imm8); 2019 void shrl(Register dst); 2020 2021 void shrq(Register dst, int imm8); 2022 void shrq(Register dst); 2023 2024 void smovl(); // QQQ generic? 2025 2026 // Compute Square Root of Scalar Double-Precision Floating-Point Value 2027 void sqrtsd(XMMRegister dst, Address src); 2028 void sqrtsd(XMMRegister dst, XMMRegister src); 2029 2030 void roundsd(XMMRegister dst, Address src, int32_t rmode); 2031 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode); 2032 2033 // Compute Square Root of Scalar Single-Precision Floating-Point Value 2034 void sqrtss(XMMRegister dst, Address src); 2035 void sqrtss(XMMRegister dst, XMMRegister src); 2036 2037 void std(); 2038 2039 void stmxcsr( Address dst ); 2040 2041 void subl(Address dst, int32_t imm32); 2042 void subl(Address dst, Register src); 2043 void subl(Register dst, int32_t imm32); 2044 void subl(Register dst, Address src); 2045 void subl(Register dst, Register src); 2046 2047 void subq(Address dst, int32_t imm32); 2048 void subq(Address dst, Register src); 2049 void subq(Register dst, int32_t imm32); 2050 void subq(Register dst, Address src); 2051 void subq(Register dst, Register src); 2052 2053 // Force generation of a 4 byte immediate value even if it fits into 8bit 2054 void subl_imm32(Register dst, int32_t imm32); 2055 void subq_imm32(Register dst, int32_t imm32); 2056 2057 // Subtract Scalar Double-Precision Floating-Point Values 2058 void subsd(XMMRegister dst, Address src); 2059 void subsd(XMMRegister dst, XMMRegister src); 2060 2061 // Subtract Scalar Single-Precision Floating-Point Values 2062 void subss(XMMRegister dst, Address src); 2063 void subss(XMMRegister dst, XMMRegister src); 2064 2065 void testb(Register dst, int imm8); 2066 void testb(Address dst, int imm8); 2067 2068 void testl(Register dst, int32_t imm32); 2069 void testl(Register dst, Register src); 2070 void testl(Register dst, Address src); 2071 2072 void testq(Register dst, int32_t imm32); 2073 void testq(Register dst, Register src); 2074 void testq(Register dst, Address src); 2075 2076 // BMI - count trailing zeros 2077 void tzcntl(Register dst, Register src); 2078 void tzcntq(Register dst, Register src); 2079 2080 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 2081 void ucomisd(XMMRegister dst, Address src); 2082 void ucomisd(XMMRegister dst, XMMRegister src); 2083 2084 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 2085 void ucomiss(XMMRegister dst, Address src); 2086 void ucomiss(XMMRegister dst, XMMRegister src); 2087 2088 void xabort(int8_t imm8); 2089 2090 void xaddb(Address dst, Register src); 2091 void xaddw(Address dst, Register src); 2092 void xaddl(Address dst, Register src); 2093 void xaddq(Address dst, Register src); 2094 2095 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none); 2096 2097 void xchgb(Register reg, Address adr); 2098 void xchgw(Register reg, Address adr); 2099 void xchgl(Register reg, Address adr); 2100 void xchgl(Register dst, Register src); 2101 2102 void xchgq(Register reg, Address adr); 2103 void xchgq(Register dst, Register src); 2104 2105 void xend(); 2106 2107 // Get Value of Extended Control Register 2108 void xgetbv(); 2109 2110 void xorl(Register dst, int32_t imm32); 2111 void xorl(Register dst, Address src); 2112 void xorl(Register dst, Register src); 2113 2114 void xorb(Register dst, Address src); 2115 void xorw(Register dst, Register src); 2116 2117 void xorq(Register dst, Address src); 2118 void xorq(Register dst, Register src); 2119 2120 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 2121 2122 // AVX 3-operands scalar instructions (encoded with VEX prefix) 2123 2124 void vaddsd(XMMRegister dst, XMMRegister nds, Address src); 2125 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 2126 void vaddss(XMMRegister dst, XMMRegister nds, Address src); 2127 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); 2128 void vdivsd(XMMRegister dst, XMMRegister nds, Address src); 2129 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 2130 void vdivss(XMMRegister dst, XMMRegister nds, Address src); 2131 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src); 2132 void vfmadd231sd(XMMRegister dst, XMMRegister nds, XMMRegister src); 2133 void vfmadd231ss(XMMRegister dst, XMMRegister nds, XMMRegister src); 2134 void vmulsd(XMMRegister dst, XMMRegister nds, Address src); 2135 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 2136 void vmulss(XMMRegister dst, XMMRegister nds, Address src); 2137 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src); 2138 void vsubsd(XMMRegister dst, XMMRegister nds, Address src); 2139 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 2140 void vsubss(XMMRegister dst, XMMRegister nds, Address src); 2141 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); 2142 2143 void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src); 2144 void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 2145 void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src); 2146 void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 2147 2148 void shlxl(Register dst, Register src1, Register src2); 2149 void shlxq(Register dst, Register src1, Register src2); 2150 2151 //====================VECTOR ARITHMETIC===================================== 2152 void evpmovd2m(KRegister kdst, XMMRegister src, int vector_len); 2153 void evpmovq2m(KRegister kdst, XMMRegister src, int vector_len); 2154 2155 // Add Packed Floating-Point Values 2156 void addpd(XMMRegister dst, XMMRegister src); 2157 void addpd(XMMRegister dst, Address src); 2158 void addps(XMMRegister dst, XMMRegister src); 2159 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2160 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2161 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2162 void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2163 2164 // Subtract Packed Floating-Point Values 2165 void subpd(XMMRegister dst, XMMRegister src); 2166 void subps(XMMRegister dst, XMMRegister src); 2167 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2168 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2169 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2170 void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2171 2172 // Multiply Packed Floating-Point Values 2173 void mulpd(XMMRegister dst, XMMRegister src); 2174 void mulpd(XMMRegister dst, Address src); 2175 void mulps(XMMRegister dst, XMMRegister src); 2176 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2177 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2178 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2179 void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2180 2181 void vfmadd231pd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2182 void vfmadd231ps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2183 void vfmadd231pd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2184 void vfmadd231ps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2185 2186 // Divide Packed Floating-Point Values 2187 void divpd(XMMRegister dst, XMMRegister src); 2188 void divps(XMMRegister dst, XMMRegister src); 2189 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2190 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2191 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2192 void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2193 2194 // Sqrt Packed Floating-Point Values 2195 void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len); 2196 void vsqrtpd(XMMRegister dst, Address src, int vector_len); 2197 void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len); 2198 void vsqrtps(XMMRegister dst, Address src, int vector_len); 2199 2200 // Round Packed Double precision value. 2201 void vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len); 2202 void vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len); 2203 void vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len); 2204 void vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len); 2205 2206 // Bitwise Logical AND of Packed Floating-Point Values 2207 void andpd(XMMRegister dst, XMMRegister src); 2208 void andps(XMMRegister dst, XMMRegister src); 2209 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2210 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2211 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2212 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2213 2214 void unpckhpd(XMMRegister dst, XMMRegister src); 2215 void unpcklpd(XMMRegister dst, XMMRegister src); 2216 2217 // Bitwise Logical XOR of Packed Floating-Point Values 2218 void xorpd(XMMRegister dst, XMMRegister src); 2219 void xorps(XMMRegister dst, XMMRegister src); 2220 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2221 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2222 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2223 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2224 2225 // Add horizontal packed integers 2226 void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2227 void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2228 void phaddw(XMMRegister dst, XMMRegister src); 2229 void phaddd(XMMRegister dst, XMMRegister src); 2230 2231 // Add packed integers 2232 void paddb(XMMRegister dst, XMMRegister src); 2233 void paddw(XMMRegister dst, XMMRegister src); 2234 void paddd(XMMRegister dst, XMMRegister src); 2235 void paddd(XMMRegister dst, Address src); 2236 void paddq(XMMRegister dst, XMMRegister src); 2237 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2238 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2239 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2240 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2241 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2242 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2243 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2244 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2245 2246 // Sub packed integers 2247 void psubb(XMMRegister dst, XMMRegister src); 2248 void psubw(XMMRegister dst, XMMRegister src); 2249 void psubd(XMMRegister dst, XMMRegister src); 2250 void psubq(XMMRegister dst, XMMRegister src); 2251 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2252 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2253 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2254 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2255 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2256 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2257 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2258 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2259 2260 // Multiply packed integers (only shorts and ints) 2261 void pmullw(XMMRegister dst, XMMRegister src); 2262 void pmulld(XMMRegister dst, XMMRegister src); 2263 void pmuludq(XMMRegister dst, XMMRegister src); 2264 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2265 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2266 void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2267 void vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2268 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2269 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2270 void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2271 2272 // Minimum of packed integers 2273 void pminsb(XMMRegister dst, XMMRegister src); 2274 void vpminsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2275 void pminsw(XMMRegister dst, XMMRegister src); 2276 void vpminsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2277 void pminsd(XMMRegister dst, XMMRegister src); 2278 void vpminsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2279 void vpminsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2280 void minps(XMMRegister dst, XMMRegister src); 2281 void vminps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2282 void minpd(XMMRegister dst, XMMRegister src); 2283 void vminpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2284 2285 // Maximum of packed integers 2286 void pmaxsb(XMMRegister dst, XMMRegister src); 2287 void vpmaxsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2288 void pmaxsw(XMMRegister dst, XMMRegister src); 2289 void vpmaxsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2290 void pmaxsd(XMMRegister dst, XMMRegister src); 2291 void vpmaxsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2292 void vpmaxsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2293 void maxps(XMMRegister dst, XMMRegister src); 2294 void vmaxps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2295 void maxpd(XMMRegister dst, XMMRegister src); 2296 void vmaxpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2297 2298 // Shift left packed integers 2299 void psllw(XMMRegister dst, int shift); 2300 void pslld(XMMRegister dst, int shift); 2301 void psllq(XMMRegister dst, int shift); 2302 void psllw(XMMRegister dst, XMMRegister shift); 2303 void pslld(XMMRegister dst, XMMRegister shift); 2304 void psllq(XMMRegister dst, XMMRegister shift); 2305 void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2306 void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2307 void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2308 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2309 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2310 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2311 void vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2312 2313 // Logical shift right packed integers 2314 void psrlw(XMMRegister dst, int shift); 2315 void psrld(XMMRegister dst, int shift); 2316 void psrlq(XMMRegister dst, int shift); 2317 void psrlw(XMMRegister dst, XMMRegister shift); 2318 void psrld(XMMRegister dst, XMMRegister shift); 2319 void psrlq(XMMRegister dst, XMMRegister shift); 2320 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2321 void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2322 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2323 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2324 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2325 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2326 void vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2327 void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2328 void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2329 2330 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs) 2331 void psraw(XMMRegister dst, int shift); 2332 void psrad(XMMRegister dst, int shift); 2333 void psraw(XMMRegister dst, XMMRegister shift); 2334 void psrad(XMMRegister dst, XMMRegister shift); 2335 void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2336 void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2337 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2338 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2339 void evpsravw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2340 void evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2341 void evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2342 2343 // Variable shift left packed integers 2344 void vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2345 void vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2346 2347 // Variable shift right packed integers 2348 void vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2349 void vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2350 2351 // Variable shift right arithmetic packed integers 2352 void vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2353 void evpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2354 2355 void vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2356 void vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2357 2358 // And packed integers 2359 void pand(XMMRegister dst, XMMRegister src); 2360 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2361 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2362 void evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2363 void vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2364 2365 // Andn packed integers 2366 void pandn(XMMRegister dst, XMMRegister src); 2367 void vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2368 2369 // Or packed integers 2370 void por(XMMRegister dst, XMMRegister src); 2371 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2372 void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2373 void vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2374 2375 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2376 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2377 2378 // Xor packed integers 2379 void pxor(XMMRegister dst, XMMRegister src); 2380 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2381 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2382 void vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2383 void evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2384 void evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2385 void evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2386 2387 // vinserti forms 2388 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); 2389 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); 2390 void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); 2391 void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); 2392 void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); 2393 2394 // vinsertf forms 2395 void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); 2396 void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); 2397 void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); 2398 void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); 2399 void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); 2400 void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); 2401 2402 // vextracti forms 2403 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8); 2404 void vextracti128(Address dst, XMMRegister src, uint8_t imm8); 2405 void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8); 2406 void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8); 2407 void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8); 2408 void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8); 2409 void vextracti64x4(Address dst, XMMRegister src, uint8_t imm8); 2410 2411 // vextractf forms 2412 void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8); 2413 void vextractf128(Address dst, XMMRegister src, uint8_t imm8); 2414 void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8); 2415 void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8); 2416 void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8); 2417 void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8); 2418 void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8); 2419 2420 // xmm/mem sourced byte/word/dword/qword replicate 2421 void vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len); 2422 void vpbroadcastb(XMMRegister dst, Address src, int vector_len); 2423 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len); 2424 void vpbroadcastw(XMMRegister dst, Address src, int vector_len); 2425 void vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len); 2426 void vpbroadcastd(XMMRegister dst, Address src, int vector_len); 2427 void vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len); 2428 void vpbroadcastq(XMMRegister dst, Address src, int vector_len); 2429 2430 void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len); 2431 void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len); 2432 2433 // scalar single/double precision replicate 2434 void vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len); 2435 void vbroadcastss(XMMRegister dst, Address src, int vector_len); 2436 void vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len); 2437 void vbroadcastsd(XMMRegister dst, Address src, int vector_len); 2438 2439 // gpr sourced byte/word/dword/qword replicate 2440 void evpbroadcastb(XMMRegister dst, Register src, int vector_len); 2441 void evpbroadcastw(XMMRegister dst, Register src, int vector_len); 2442 void evpbroadcastd(XMMRegister dst, Register src, int vector_len); 2443 void evpbroadcastq(XMMRegister dst, Register src, int vector_len); 2444 2445 // Gather AVX2 and AVX3 2446 void vpgatherdd(XMMRegister dst, Address src, XMMRegister mask, int vector_len); 2447 void vpgatherdq(XMMRegister dst, Address src, XMMRegister mask, int vector_len); 2448 void vgatherdpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len); 2449 void vgatherdps(XMMRegister dst, Address src, XMMRegister mask, int vector_len); 2450 void evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len); 2451 void evpgatherdq(XMMRegister dst, KRegister mask, Address src, int vector_len); 2452 void evgatherdpd(XMMRegister dst, KRegister mask, Address src, int vector_len); 2453 void evgatherdps(XMMRegister dst, KRegister mask, Address src, int vector_len); 2454 2455 //Scatter AVX3 only 2456 void evpscatterdd(Address dst, KRegister mask, XMMRegister src, int vector_len); 2457 void evpscatterdq(Address dst, KRegister mask, XMMRegister src, int vector_len); 2458 void evscatterdps(Address dst, KRegister mask, XMMRegister src, int vector_len); 2459 void evscatterdpd(Address dst, KRegister mask, XMMRegister src, int vector_len); 2460 2461 // Carry-Less Multiplication Quadword 2462 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask); 2463 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask); 2464 void evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len); 2465 // AVX instruction which is used to clear upper 128 bits of YMM registers and 2466 // to avoid transaction penalty between AVX and SSE states. There is no 2467 // penalty if legacy SSE instructions are encoded using VEX prefix because 2468 // they always clear upper 128 bits. It should be used before calling 2469 // runtime code and native libraries. 2470 void vzeroupper(); 2471 2472 // Vector double compares 2473 void vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len); 2474 void evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, 2475 ComparisonPredicateFP comparison, int vector_len); 2476 2477 // Vector float compares 2478 void vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len); 2479 void evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, 2480 ComparisonPredicateFP comparison, int vector_len); 2481 2482 // Vector integer compares 2483 void vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2484 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, 2485 int comparison, int vector_len); 2486 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, 2487 int comparison, int vector_len); 2488 2489 // Vector long compares 2490 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, 2491 int comparison, int vector_len); 2492 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src, 2493 int comparison, int vector_len); 2494 2495 // Vector byte compares 2496 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, 2497 int comparison, int vector_len); 2498 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, 2499 int comparison, int vector_len); 2500 2501 // Vector short compares 2502 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, 2503 int comparison, int vector_len); 2504 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src, 2505 int comparison, int vector_len); 2506 2507 // Vector blends 2508 void blendvps(XMMRegister dst, XMMRegister src); 2509 void blendvpd(XMMRegister dst, XMMRegister src); 2510 void pblendvb(XMMRegister dst, XMMRegister src); 2511 void vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len); 2512 void vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len); 2513 void vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len); 2514 void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len); 2515 void evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2516 void evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2517 void evpblendmb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2518 void evpblendmw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2519 void evpblendmd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2520 void evpblendmq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2521 protected: 2522 // Next instructions require address alignment 16 bytes SSE mode. 2523 // They should be called only from corresponding MacroAssembler instructions. 2524 void andpd(XMMRegister dst, Address src); 2525 void andps(XMMRegister dst, Address src); 2526 void xorpd(XMMRegister dst, Address src); 2527 void xorps(XMMRegister dst, Address src); 2528 2529 }; 2530 2531 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions. 2532 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction 2533 // are applied. 2534 class InstructionAttr { 2535 public: 2536 InstructionAttr( 2537 int vector_len, // The length of vector to be applied in encoding - for both AVX and EVEX 2538 bool rex_vex_w, // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true 2539 bool legacy_mode, // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX 2540 bool no_reg_mask, // when true, k0 is used when EVEX encoding is chosen, else embedded_opmask_register_specifier is used 2541 bool uses_vl) // This instruction may have legacy constraints based on vector length for EVEX 2542 : 2543 _rex_vex_w(rex_vex_w), 2544 _legacy_mode(legacy_mode || UseAVX < 3), 2545 _no_reg_mask(no_reg_mask), 2546 _uses_vl(uses_vl), 2547 _rex_vex_w_reverted(false), 2548 _is_evex_instruction(false), 2549 _is_clear_context(true), 2550 _is_extended_context(false), 2551 _avx_vector_len(vector_len), 2552 _tuple_type(Assembler::EVEX_ETUP), 2553 _input_size_in_bits(Assembler::EVEX_NObit), 2554 _evex_encoding(0), 2555 _embedded_opmask_register_specifier(0), // hard code k0 2556 _current_assembler(NULL) { } 2557 2558 ~InstructionAttr() { 2559 if (_current_assembler != NULL) { 2560 _current_assembler->clear_attributes(); 2561 } 2562 _current_assembler = NULL; 2563 } 2564 2565 private: 2566 bool _rex_vex_w; 2567 bool _legacy_mode; 2568 bool _no_reg_mask; 2569 bool _uses_vl; 2570 bool _rex_vex_w_reverted; 2571 bool _is_evex_instruction; 2572 bool _is_clear_context; 2573 bool _is_extended_context; 2574 int _avx_vector_len; 2575 int _tuple_type; 2576 int _input_size_in_bits; 2577 int _evex_encoding; 2578 int _embedded_opmask_register_specifier; 2579 2580 Assembler *_current_assembler; 2581 2582 public: 2583 // query functions for field accessors 2584 bool is_rex_vex_w(void) const { return _rex_vex_w; } 2585 bool is_legacy_mode(void) const { return _legacy_mode; } 2586 bool is_no_reg_mask(void) const { return _no_reg_mask; } 2587 bool uses_vl(void) const { return _uses_vl; } 2588 bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; } 2589 bool is_evex_instruction(void) const { return _is_evex_instruction; } 2590 bool is_clear_context(void) const { return _is_clear_context; } 2591 bool is_extended_context(void) const { return _is_extended_context; } 2592 int get_vector_len(void) const { return _avx_vector_len; } 2593 int get_tuple_type(void) const { return _tuple_type; } 2594 int get_input_size(void) const { return _input_size_in_bits; } 2595 int get_evex_encoding(void) const { return _evex_encoding; } 2596 int get_embedded_opmask_register_specifier(void) const { return _embedded_opmask_register_specifier; } 2597 2598 // Set the vector len manually 2599 void set_vector_len(int vector_len) { _avx_vector_len = vector_len; } 2600 2601 // Set revert rex_vex_w for avx encoding 2602 void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; } 2603 2604 // Set rex_vex_w based on state 2605 void set_rex_vex_w(bool state) { _rex_vex_w = state; } 2606 2607 // Set the instruction to be encoded in AVX mode 2608 void set_is_legacy_mode(void) { _legacy_mode = true; } 2609 2610 // Set the current instuction to be encoded as an EVEX instuction 2611 void set_is_evex_instruction(void) { _is_evex_instruction = true; } 2612 2613 // Internal encoding data used in compressed immediate offset programming 2614 void set_evex_encoding(int value) { _evex_encoding = value; } 2615 2616 // When the Evex.Z field is set (true), it is used to clear all non directed XMM/YMM/ZMM components. 2617 // This method unsets it so that merge semantics are used instead. 2618 void reset_is_clear_context(void) { _is_clear_context = false; } 2619 2620 // Map back to current asembler so that we can manage object level assocation 2621 void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; } 2622 2623 // Address modifiers used for compressed displacement calculation 2624 void set_address_attributes(int tuple_type, int input_size_in_bits) { 2625 if (VM_Version::supports_evex()) { 2626 _tuple_type = tuple_type; 2627 _input_size_in_bits = input_size_in_bits; 2628 } 2629 } 2630 2631 // Set embedded opmask register specifier. 2632 void set_embedded_opmask_register_specifier(KRegister mask) { 2633 _embedded_opmask_register_specifier = (*mask).encoding() & 0x7; 2634 } 2635 2636 }; 2637 2638 #endif // CPU_X86_ASSEMBLER_X86_HPP