1 /* 2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "jvm.h" 27 #include "asm/assembler.hpp" 28 #include "asm/assembler.inline.hpp" 29 #include "compiler/disassembler.hpp" 30 #include "gc/shared/barrierSet.hpp" 31 #include "gc/shared/barrierSetAssembler.hpp" 32 #include "gc/shared/collectedHeap.inline.hpp" 33 #include "interpreter/interpreter.hpp" 34 #include "memory/resourceArea.hpp" 35 #include "memory/universe.hpp" 36 #include "oops/accessDecorators.hpp" 37 #include "oops/compressedOops.inline.hpp" 38 #include "oops/klass.inline.hpp" 39 #include "prims/methodHandles.hpp" 40 #include "runtime/biasedLocking.hpp" 41 #include "runtime/flags/flagSetting.hpp" 42 #include "runtime/interfaceSupport.inline.hpp" 43 #include "runtime/objectMonitor.hpp" 44 #include "runtime/os.hpp" 45 #include "runtime/safepoint.hpp" 46 #include "runtime/safepointMechanism.hpp" 47 #include "runtime/sharedRuntime.hpp" 48 #include "runtime/stubRoutines.hpp" 49 #include "runtime/thread.hpp" 50 #include "utilities/macros.hpp" 51 #include "crc32c.h" 52 53 #ifdef PRODUCT 54 #define BLOCK_COMMENT(str) /* nothing */ 55 #define STOP(error) stop(error) 56 #else 57 #define BLOCK_COMMENT(str) block_comment(str) 58 #define STOP(error) block_comment(error); stop(error) 59 #endif 60 61 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 62 63 #ifdef ASSERT 64 bool AbstractAssembler::pd_check_instruction_mark() { return true; } 65 #endif 66 67 static Assembler::Condition reverse[] = { 68 Assembler::noOverflow /* overflow = 0x0 */ , 69 Assembler::overflow /* noOverflow = 0x1 */ , 70 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 71 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 72 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 73 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 74 Assembler::above /* belowEqual = 0x6 */ , 75 Assembler::belowEqual /* above = 0x7 */ , 76 Assembler::positive /* negative = 0x8 */ , 77 Assembler::negative /* positive = 0x9 */ , 78 Assembler::noParity /* parity = 0xa */ , 79 Assembler::parity /* noParity = 0xb */ , 80 Assembler::greaterEqual /* less = 0xc */ , 81 Assembler::less /* greaterEqual = 0xd */ , 82 Assembler::greater /* lessEqual = 0xe */ , 83 Assembler::lessEqual /* greater = 0xf, */ 84 85 }; 86 87 88 // Implementation of MacroAssembler 89 90 // First all the versions that have distinct versions depending on 32/64 bit 91 // Unless the difference is trivial (1 line or so). 92 93 #ifndef _LP64 94 95 // 32bit versions 96 97 Address MacroAssembler::as_Address(AddressLiteral adr) { 98 return Address(adr.target(), adr.rspec()); 99 } 100 101 Address MacroAssembler::as_Address(ArrayAddress adr) { 102 return Address::make_array(adr); 103 } 104 105 void MacroAssembler::call_VM_leaf_base(address entry_point, 106 int number_of_arguments) { 107 call(RuntimeAddress(entry_point)); 108 increment(rsp, number_of_arguments * wordSize); 109 } 110 111 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { 112 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 113 } 114 115 116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { 117 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 118 } 119 120 void MacroAssembler::cmpoop_raw(Address src1, jobject obj) { 121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 122 } 123 124 void MacroAssembler::cmpoop_raw(Register src1, jobject obj) { 125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 126 } 127 128 void MacroAssembler::cmpoop(Address src1, jobject obj) { 129 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 130 bs->obj_equals(this, src1, obj); 131 } 132 133 void MacroAssembler::cmpoop(Register src1, jobject obj) { 134 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 135 bs->obj_equals(this, src1, obj); 136 } 137 138 void MacroAssembler::extend_sign(Register hi, Register lo) { 139 // According to Intel Doc. AP-526, "Integer Divide", p.18. 140 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 141 cdql(); 142 } else { 143 movl(hi, lo); 144 sarl(hi, 31); 145 } 146 } 147 148 void MacroAssembler::jC2(Register tmp, Label& L) { 149 // set parity bit if FPU flag C2 is set (via rax) 150 save_rax(tmp); 151 fwait(); fnstsw_ax(); 152 sahf(); 153 restore_rax(tmp); 154 // branch 155 jcc(Assembler::parity, L); 156 } 157 158 void MacroAssembler::jnC2(Register tmp, Label& L) { 159 // set parity bit if FPU flag C2 is set (via rax) 160 save_rax(tmp); 161 fwait(); fnstsw_ax(); 162 sahf(); 163 restore_rax(tmp); 164 // branch 165 jcc(Assembler::noParity, L); 166 } 167 168 // 32bit can do a case table jump in one instruction but we no longer allow the base 169 // to be installed in the Address class 170 void MacroAssembler::jump(ArrayAddress entry) { 171 jmp(as_Address(entry)); 172 } 173 174 // Note: y_lo will be destroyed 175 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 176 // Long compare for Java (semantics as described in JVM spec.) 177 Label high, low, done; 178 179 cmpl(x_hi, y_hi); 180 jcc(Assembler::less, low); 181 jcc(Assembler::greater, high); 182 // x_hi is the return register 183 xorl(x_hi, x_hi); 184 cmpl(x_lo, y_lo); 185 jcc(Assembler::below, low); 186 jcc(Assembler::equal, done); 187 188 bind(high); 189 xorl(x_hi, x_hi); 190 increment(x_hi); 191 jmp(done); 192 193 bind(low); 194 xorl(x_hi, x_hi); 195 decrementl(x_hi); 196 197 bind(done); 198 } 199 200 void MacroAssembler::lea(Register dst, AddressLiteral src) { 201 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 202 } 203 204 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 205 // leal(dst, as_Address(adr)); 206 // see note in movl as to why we must use a move 207 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); 208 } 209 210 void MacroAssembler::leave() { 211 mov(rsp, rbp); 212 pop(rbp); 213 } 214 215 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 216 // Multiplication of two Java long values stored on the stack 217 // as illustrated below. Result is in rdx:rax. 218 // 219 // rsp ---> [ ?? ] \ \ 220 // .... | y_rsp_offset | 221 // [ y_lo ] / (in bytes) | x_rsp_offset 222 // [ y_hi ] | (in bytes) 223 // .... | 224 // [ x_lo ] / 225 // [ x_hi ] 226 // .... 227 // 228 // Basic idea: lo(result) = lo(x_lo * y_lo) 229 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 230 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 231 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 232 Label quick; 233 // load x_hi, y_hi and check if quick 234 // multiplication is possible 235 movl(rbx, x_hi); 236 movl(rcx, y_hi); 237 movl(rax, rbx); 238 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 239 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 240 // do full multiplication 241 // 1st step 242 mull(y_lo); // x_hi * y_lo 243 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 244 // 2nd step 245 movl(rax, x_lo); 246 mull(rcx); // x_lo * y_hi 247 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 248 // 3rd step 249 bind(quick); // note: rbx, = 0 if quick multiply! 250 movl(rax, x_lo); 251 mull(y_lo); // x_lo * y_lo 252 addl(rdx, rbx); // correct hi(x_lo * y_lo) 253 } 254 255 void MacroAssembler::lneg(Register hi, Register lo) { 256 negl(lo); 257 adcl(hi, 0); 258 negl(hi); 259 } 260 261 void MacroAssembler::lshl(Register hi, Register lo) { 262 // Java shift left long support (semantics as described in JVM spec., p.305) 263 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 264 // shift value is in rcx ! 265 assert(hi != rcx, "must not use rcx"); 266 assert(lo != rcx, "must not use rcx"); 267 const Register s = rcx; // shift count 268 const int n = BitsPerWord; 269 Label L; 270 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 271 cmpl(s, n); // if (s < n) 272 jcc(Assembler::less, L); // else (s >= n) 273 movl(hi, lo); // x := x << n 274 xorl(lo, lo); 275 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 276 bind(L); // s (mod n) < n 277 shldl(hi, lo); // x := x << s 278 shll(lo); 279 } 280 281 282 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 283 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 284 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 285 assert(hi != rcx, "must not use rcx"); 286 assert(lo != rcx, "must not use rcx"); 287 const Register s = rcx; // shift count 288 const int n = BitsPerWord; 289 Label L; 290 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 291 cmpl(s, n); // if (s < n) 292 jcc(Assembler::less, L); // else (s >= n) 293 movl(lo, hi); // x := x >> n 294 if (sign_extension) sarl(hi, 31); 295 else xorl(hi, hi); 296 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 297 bind(L); // s (mod n) < n 298 shrdl(lo, hi); // x := x >> s 299 if (sign_extension) sarl(hi); 300 else shrl(hi); 301 } 302 303 void MacroAssembler::movoop(Register dst, jobject obj) { 304 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 305 } 306 307 void MacroAssembler::movoop(Address dst, jobject obj) { 308 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 309 } 310 311 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 312 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 313 } 314 315 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 316 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 317 } 318 319 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 320 // scratch register is not used, 321 // it is defined to match parameters of 64-bit version of this method. 322 if (src.is_lval()) { 323 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 324 } else { 325 movl(dst, as_Address(src)); 326 } 327 } 328 329 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 330 movl(as_Address(dst), src); 331 } 332 333 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 334 movl(dst, as_Address(src)); 335 } 336 337 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 338 void MacroAssembler::movptr(Address dst, intptr_t src) { 339 movl(dst, src); 340 } 341 342 343 void MacroAssembler::pop_callee_saved_registers() { 344 pop(rcx); 345 pop(rdx); 346 pop(rdi); 347 pop(rsi); 348 } 349 350 void MacroAssembler::push_callee_saved_registers() { 351 push(rsi); 352 push(rdi); 353 push(rdx); 354 push(rcx); 355 } 356 357 void MacroAssembler::pushoop(jobject obj) { 358 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 359 } 360 361 void MacroAssembler::pushklass(Metadata* obj) { 362 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); 363 } 364 365 void MacroAssembler::pushptr(AddressLiteral src) { 366 if (src.is_lval()) { 367 push_literal32((int32_t)src.target(), src.rspec()); 368 } else { 369 pushl(as_Address(src)); 370 } 371 } 372 373 void MacroAssembler::set_word_if_not_zero(Register dst) { 374 xorl(dst, dst); 375 set_byte_if_not_zero(dst); 376 } 377 378 static void pass_arg0(MacroAssembler* masm, Register arg) { 379 masm->push(arg); 380 } 381 382 static void pass_arg1(MacroAssembler* masm, Register arg) { 383 masm->push(arg); 384 } 385 386 static void pass_arg2(MacroAssembler* masm, Register arg) { 387 masm->push(arg); 388 } 389 390 static void pass_arg3(MacroAssembler* masm, Register arg) { 391 masm->push(arg); 392 } 393 394 #ifndef PRODUCT 395 extern "C" void findpc(intptr_t x); 396 #endif 397 398 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 399 // In order to get locks to work, we need to fake a in_VM state 400 JavaThread* thread = JavaThread::current(); 401 JavaThreadState saved_state = thread->thread_state(); 402 thread->set_thread_state(_thread_in_vm); 403 if (ShowMessageBoxOnError) { 404 JavaThread* thread = JavaThread::current(); 405 JavaThreadState saved_state = thread->thread_state(); 406 thread->set_thread_state(_thread_in_vm); 407 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 408 ttyLocker ttyl; 409 BytecodeCounter::print(); 410 } 411 // To see where a verify_oop failed, get $ebx+40/X for this frame. 412 // This is the value of eip which points to where verify_oop will return. 413 if (os::message_box(msg, "Execution stopped, print registers?")) { 414 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); 415 BREAKPOINT; 416 } 417 } 418 fatal("DEBUG MESSAGE: %s", msg); 419 } 420 421 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { 422 ttyLocker ttyl; 423 FlagSetting fs(Debugging, true); 424 tty->print_cr("eip = 0x%08x", eip); 425 #ifndef PRODUCT 426 if ((WizardMode || Verbose) && PrintMiscellaneous) { 427 tty->cr(); 428 findpc(eip); 429 tty->cr(); 430 } 431 #endif 432 #define PRINT_REG(rax) \ 433 { tty->print("%s = ", #rax); os::print_location(tty, rax); } 434 PRINT_REG(rax); 435 PRINT_REG(rbx); 436 PRINT_REG(rcx); 437 PRINT_REG(rdx); 438 PRINT_REG(rdi); 439 PRINT_REG(rsi); 440 PRINT_REG(rbp); 441 PRINT_REG(rsp); 442 #undef PRINT_REG 443 // Print some words near top of staack. 444 int* dump_sp = (int*) rsp; 445 for (int col1 = 0; col1 < 8; col1++) { 446 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 447 os::print_location(tty, *dump_sp++); 448 } 449 for (int row = 0; row < 16; row++) { 450 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 451 for (int col = 0; col < 8; col++) { 452 tty->print(" 0x%08x", *dump_sp++); 453 } 454 tty->cr(); 455 } 456 // Print some instructions around pc: 457 Disassembler::decode((address)eip-64, (address)eip); 458 tty->print_cr("--------"); 459 Disassembler::decode((address)eip, (address)eip+32); 460 } 461 462 void MacroAssembler::stop(const char* msg) { 463 ExternalAddress message((address)msg); 464 // push address of message 465 pushptr(message.addr()); 466 { Label L; call(L, relocInfo::none); bind(L); } // push eip 467 pusha(); // push registers 468 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 469 hlt(); 470 } 471 472 void MacroAssembler::warn(const char* msg) { 473 push_CPU_state(); 474 475 ExternalAddress message((address) msg); 476 // push address of message 477 pushptr(message.addr()); 478 479 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 480 addl(rsp, wordSize); // discard argument 481 pop_CPU_state(); 482 } 483 484 void MacroAssembler::print_state() { 485 { Label L; call(L, relocInfo::none); bind(L); } // push eip 486 pusha(); // push registers 487 488 push_CPU_state(); 489 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); 490 pop_CPU_state(); 491 492 popa(); 493 addl(rsp, wordSize); 494 } 495 496 #else // _LP64 497 498 // 64 bit versions 499 500 Address MacroAssembler::as_Address(AddressLiteral adr) { 501 // amd64 always does this as a pc-rel 502 // we can be absolute or disp based on the instruction type 503 // jmp/call are displacements others are absolute 504 assert(!adr.is_lval(), "must be rval"); 505 assert(reachable(adr), "must be"); 506 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); 507 508 } 509 510 Address MacroAssembler::as_Address(ArrayAddress adr) { 511 AddressLiteral base = adr.base(); 512 lea(rscratch1, base); 513 Address index = adr.index(); 514 assert(index._disp == 0, "must not have disp"); // maybe it can? 515 Address array(rscratch1, index._index, index._scale, index._disp); 516 return array; 517 } 518 519 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 520 Label L, E; 521 522 #ifdef _WIN64 523 // Windows always allocates space for it's register args 524 assert(num_args <= 4, "only register arguments supported"); 525 subq(rsp, frame::arg_reg_save_area_bytes); 526 #endif 527 528 // Align stack if necessary 529 testl(rsp, 15); 530 jcc(Assembler::zero, L); 531 532 subq(rsp, 8); 533 { 534 call(RuntimeAddress(entry_point)); 535 } 536 addq(rsp, 8); 537 jmp(E); 538 539 bind(L); 540 { 541 call(RuntimeAddress(entry_point)); 542 } 543 544 bind(E); 545 546 #ifdef _WIN64 547 // restore stack pointer 548 addq(rsp, frame::arg_reg_save_area_bytes); 549 #endif 550 551 } 552 553 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { 554 assert(!src2.is_lval(), "should use cmpptr"); 555 556 if (reachable(src2)) { 557 cmpq(src1, as_Address(src2)); 558 } else { 559 lea(rscratch1, src2); 560 Assembler::cmpq(src1, Address(rscratch1, 0)); 561 } 562 } 563 564 int MacroAssembler::corrected_idivq(Register reg) { 565 // Full implementation of Java ldiv and lrem; checks for special 566 // case as described in JVM spec., p.243 & p.271. The function 567 // returns the (pc) offset of the idivl instruction - may be needed 568 // for implicit exceptions. 569 // 570 // normal case special case 571 // 572 // input : rax: dividend min_long 573 // reg: divisor (may not be eax/edx) -1 574 // 575 // output: rax: quotient (= rax idiv reg) min_long 576 // rdx: remainder (= rax irem reg) 0 577 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 578 static const int64_t min_long = 0x8000000000000000; 579 Label normal_case, special_case; 580 581 // check for special case 582 cmp64(rax, ExternalAddress((address) &min_long)); 583 jcc(Assembler::notEqual, normal_case); 584 xorl(rdx, rdx); // prepare rdx for possible special case (where 585 // remainder = 0) 586 cmpq(reg, -1); 587 jcc(Assembler::equal, special_case); 588 589 // handle normal case 590 bind(normal_case); 591 cdqq(); 592 int idivq_offset = offset(); 593 idivq(reg); 594 595 // normal and special case exit 596 bind(special_case); 597 598 return idivq_offset; 599 } 600 601 void MacroAssembler::decrementq(Register reg, int value) { 602 if (value == min_jint) { subq(reg, value); return; } 603 if (value < 0) { incrementq(reg, -value); return; } 604 if (value == 0) { ; return; } 605 if (value == 1 && UseIncDec) { decq(reg) ; return; } 606 /* else */ { subq(reg, value) ; return; } 607 } 608 609 void MacroAssembler::decrementq(Address dst, int value) { 610 if (value == min_jint) { subq(dst, value); return; } 611 if (value < 0) { incrementq(dst, -value); return; } 612 if (value == 0) { ; return; } 613 if (value == 1 && UseIncDec) { decq(dst) ; return; } 614 /* else */ { subq(dst, value) ; return; } 615 } 616 617 void MacroAssembler::incrementq(AddressLiteral dst) { 618 if (reachable(dst)) { 619 incrementq(as_Address(dst)); 620 } else { 621 lea(rscratch1, dst); 622 incrementq(Address(rscratch1, 0)); 623 } 624 } 625 626 void MacroAssembler::incrementq(Register reg, int value) { 627 if (value == min_jint) { addq(reg, value); return; } 628 if (value < 0) { decrementq(reg, -value); return; } 629 if (value == 0) { ; return; } 630 if (value == 1 && UseIncDec) { incq(reg) ; return; } 631 /* else */ { addq(reg, value) ; return; } 632 } 633 634 void MacroAssembler::incrementq(Address dst, int value) { 635 if (value == min_jint) { addq(dst, value); return; } 636 if (value < 0) { decrementq(dst, -value); return; } 637 if (value == 0) { ; return; } 638 if (value == 1 && UseIncDec) { incq(dst) ; return; } 639 /* else */ { addq(dst, value) ; return; } 640 } 641 642 // 32bit can do a case table jump in one instruction but we no longer allow the base 643 // to be installed in the Address class 644 void MacroAssembler::jump(ArrayAddress entry) { 645 lea(rscratch1, entry.base()); 646 Address dispatch = entry.index(); 647 assert(dispatch._base == noreg, "must be"); 648 dispatch._base = rscratch1; 649 jmp(dispatch); 650 } 651 652 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 653 ShouldNotReachHere(); // 64bit doesn't use two regs 654 cmpq(x_lo, y_lo); 655 } 656 657 void MacroAssembler::lea(Register dst, AddressLiteral src) { 658 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 659 } 660 661 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 662 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); 663 movptr(dst, rscratch1); 664 } 665 666 void MacroAssembler::leave() { 667 // %%% is this really better? Why not on 32bit too? 668 emit_int8((unsigned char)0xC9); // LEAVE 669 } 670 671 void MacroAssembler::lneg(Register hi, Register lo) { 672 ShouldNotReachHere(); // 64bit doesn't use two regs 673 negq(lo); 674 } 675 676 void MacroAssembler::movoop(Register dst, jobject obj) { 677 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 678 } 679 680 void MacroAssembler::movoop(Address dst, jobject obj) { 681 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 682 movq(dst, rscratch1); 683 } 684 685 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 686 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 687 } 688 689 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 690 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 691 movq(dst, rscratch1); 692 } 693 694 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 695 if (src.is_lval()) { 696 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 697 } else { 698 if (reachable(src)) { 699 movq(dst, as_Address(src)); 700 } else { 701 lea(scratch, src); 702 movq(dst, Address(scratch, 0)); 703 } 704 } 705 } 706 707 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 708 movq(as_Address(dst), src); 709 } 710 711 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 712 movq(dst, as_Address(src)); 713 } 714 715 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 716 void MacroAssembler::movptr(Address dst, intptr_t src) { 717 mov64(rscratch1, src); 718 movq(dst, rscratch1); 719 } 720 721 // These are mostly for initializing NULL 722 void MacroAssembler::movptr(Address dst, int32_t src) { 723 movslq(dst, src); 724 } 725 726 void MacroAssembler::movptr(Register dst, int32_t src) { 727 mov64(dst, (intptr_t)src); 728 } 729 730 void MacroAssembler::pushoop(jobject obj) { 731 movoop(rscratch1, obj); 732 push(rscratch1); 733 } 734 735 void MacroAssembler::pushklass(Metadata* obj) { 736 mov_metadata(rscratch1, obj); 737 push(rscratch1); 738 } 739 740 void MacroAssembler::pushptr(AddressLiteral src) { 741 lea(rscratch1, src); 742 if (src.is_lval()) { 743 push(rscratch1); 744 } else { 745 pushq(Address(rscratch1, 0)); 746 } 747 } 748 749 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { 750 // we must set sp to zero to clear frame 751 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 752 // must clear fp, so that compiled frames are not confused; it is 753 // possible that we need it only for debugging 754 if (clear_fp) { 755 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 756 } 757 758 // Always clear the pc because it could have been set by make_walkable() 759 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 760 vzeroupper(); 761 } 762 763 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 764 Register last_java_fp, 765 address last_java_pc) { 766 vzeroupper(); 767 // determine last_java_sp register 768 if (!last_java_sp->is_valid()) { 769 last_java_sp = rsp; 770 } 771 772 // last_java_fp is optional 773 if (last_java_fp->is_valid()) { 774 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), 775 last_java_fp); 776 } 777 778 // last_java_pc is optional 779 if (last_java_pc != NULL) { 780 Address java_pc(r15_thread, 781 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 782 lea(rscratch1, InternalAddress(last_java_pc)); 783 movptr(java_pc, rscratch1); 784 } 785 786 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 787 } 788 789 static void pass_arg0(MacroAssembler* masm, Register arg) { 790 if (c_rarg0 != arg ) { 791 masm->mov(c_rarg0, arg); 792 } 793 } 794 795 static void pass_arg1(MacroAssembler* masm, Register arg) { 796 if (c_rarg1 != arg ) { 797 masm->mov(c_rarg1, arg); 798 } 799 } 800 801 static void pass_arg2(MacroAssembler* masm, Register arg) { 802 if (c_rarg2 != arg ) { 803 masm->mov(c_rarg2, arg); 804 } 805 } 806 807 static void pass_arg3(MacroAssembler* masm, Register arg) { 808 if (c_rarg3 != arg ) { 809 masm->mov(c_rarg3, arg); 810 } 811 } 812 813 void MacroAssembler::stop(const char* msg) { 814 if (ShowMessageBoxOnError) { 815 address rip = pc(); 816 pusha(); // get regs on stack 817 lea(c_rarg1, InternalAddress(rip)); 818 movq(c_rarg2, rsp); // pass pointer to regs array 819 } 820 lea(c_rarg0, ExternalAddress((address) msg)); 821 andq(rsp, -16); // align stack as required by ABI 822 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 823 hlt(); 824 } 825 826 void MacroAssembler::warn(const char* msg) { 827 push(rbp); 828 movq(rbp, rsp); 829 andq(rsp, -16); // align stack as required by push_CPU_state and call 830 push_CPU_state(); // keeps alignment at 16 bytes 831 lea(c_rarg0, ExternalAddress((address) msg)); 832 lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning))); 833 call(rax); 834 pop_CPU_state(); 835 mov(rsp, rbp); 836 pop(rbp); 837 } 838 839 void MacroAssembler::print_state() { 840 address rip = pc(); 841 pusha(); // get regs on stack 842 push(rbp); 843 movq(rbp, rsp); 844 andq(rsp, -16); // align stack as required by push_CPU_state and call 845 push_CPU_state(); // keeps alignment at 16 bytes 846 847 lea(c_rarg0, InternalAddress(rip)); 848 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array 849 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); 850 851 pop_CPU_state(); 852 mov(rsp, rbp); 853 pop(rbp); 854 popa(); 855 } 856 857 #ifndef PRODUCT 858 extern "C" void findpc(intptr_t x); 859 #endif 860 861 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 862 // In order to get locks to work, we need to fake a in_VM state 863 if (ShowMessageBoxOnError) { 864 JavaThread* thread = JavaThread::current(); 865 JavaThreadState saved_state = thread->thread_state(); 866 thread->set_thread_state(_thread_in_vm); 867 #ifndef PRODUCT 868 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 869 ttyLocker ttyl; 870 BytecodeCounter::print(); 871 } 872 #endif 873 // To see where a verify_oop failed, get $ebx+40/X for this frame. 874 // XXX correct this offset for amd64 875 // This is the value of eip which points to where verify_oop will return. 876 if (os::message_box(msg, "Execution stopped, print registers?")) { 877 print_state64(pc, regs); 878 BREAKPOINT; 879 } 880 } 881 fatal("DEBUG MESSAGE: %s", msg); 882 } 883 884 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { 885 ttyLocker ttyl; 886 FlagSetting fs(Debugging, true); 887 tty->print_cr("rip = 0x%016lx", (intptr_t)pc); 888 #ifndef PRODUCT 889 tty->cr(); 890 findpc(pc); 891 tty->cr(); 892 #endif 893 #define PRINT_REG(rax, value) \ 894 { tty->print("%s = ", #rax); os::print_location(tty, value); } 895 PRINT_REG(rax, regs[15]); 896 PRINT_REG(rbx, regs[12]); 897 PRINT_REG(rcx, regs[14]); 898 PRINT_REG(rdx, regs[13]); 899 PRINT_REG(rdi, regs[8]); 900 PRINT_REG(rsi, regs[9]); 901 PRINT_REG(rbp, regs[10]); 902 PRINT_REG(rsp, regs[11]); 903 PRINT_REG(r8 , regs[7]); 904 PRINT_REG(r9 , regs[6]); 905 PRINT_REG(r10, regs[5]); 906 PRINT_REG(r11, regs[4]); 907 PRINT_REG(r12, regs[3]); 908 PRINT_REG(r13, regs[2]); 909 PRINT_REG(r14, regs[1]); 910 PRINT_REG(r15, regs[0]); 911 #undef PRINT_REG 912 // Print some words near top of staack. 913 int64_t* rsp = (int64_t*) regs[11]; 914 int64_t* dump_sp = rsp; 915 for (int col1 = 0; col1 < 8; col1++) { 916 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 917 os::print_location(tty, *dump_sp++); 918 } 919 for (int row = 0; row < 25; row++) { 920 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 921 for (int col = 0; col < 4; col++) { 922 tty->print(" 0x%016lx", (intptr_t)*dump_sp++); 923 } 924 tty->cr(); 925 } 926 // Print some instructions around pc: 927 Disassembler::decode((address)pc-64, (address)pc); 928 tty->print_cr("--------"); 929 Disassembler::decode((address)pc, (address)pc+32); 930 } 931 932 #endif // _LP64 933 934 // Now versions that are common to 32/64 bit 935 936 void MacroAssembler::addptr(Register dst, int32_t imm32) { 937 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 938 } 939 940 void MacroAssembler::addptr(Register dst, Register src) { 941 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 942 } 943 944 void MacroAssembler::addptr(Address dst, Register src) { 945 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 946 } 947 948 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { 949 if (reachable(src)) { 950 Assembler::addsd(dst, as_Address(src)); 951 } else { 952 lea(rscratch1, src); 953 Assembler::addsd(dst, Address(rscratch1, 0)); 954 } 955 } 956 957 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { 958 if (reachable(src)) { 959 addss(dst, as_Address(src)); 960 } else { 961 lea(rscratch1, src); 962 addss(dst, Address(rscratch1, 0)); 963 } 964 } 965 966 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) { 967 if (reachable(src)) { 968 Assembler::addpd(dst, as_Address(src)); 969 } else { 970 lea(rscratch1, src); 971 Assembler::addpd(dst, Address(rscratch1, 0)); 972 } 973 } 974 975 void MacroAssembler::align(int modulus) { 976 align(modulus, offset()); 977 } 978 979 void MacroAssembler::align(int modulus, int target) { 980 if (target % modulus != 0) { 981 nop(modulus - (target % modulus)); 982 } 983 } 984 985 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) { 986 // Used in sign-masking with aligned address. 987 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 988 if (reachable(src)) { 989 Assembler::andpd(dst, as_Address(src)); 990 } else { 991 lea(scratch_reg, src); 992 Assembler::andpd(dst, Address(scratch_reg, 0)); 993 } 994 } 995 996 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register scratch_reg) { 997 // Used in sign-masking with aligned address. 998 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 999 if (reachable(src)) { 1000 Assembler::andps(dst, as_Address(src)); 1001 } else { 1002 lea(scratch_reg, src); 1003 Assembler::andps(dst, Address(scratch_reg, 0)); 1004 } 1005 } 1006 1007 void MacroAssembler::andptr(Register dst, int32_t imm32) { 1008 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 1009 } 1010 1011 void MacroAssembler::atomic_incl(Address counter_addr) { 1012 lock(); 1013 incrementl(counter_addr); 1014 } 1015 1016 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) { 1017 if (reachable(counter_addr)) { 1018 atomic_incl(as_Address(counter_addr)); 1019 } else { 1020 lea(scr, counter_addr); 1021 atomic_incl(Address(scr, 0)); 1022 } 1023 } 1024 1025 #ifdef _LP64 1026 void MacroAssembler::atomic_incq(Address counter_addr) { 1027 lock(); 1028 incrementq(counter_addr); 1029 } 1030 1031 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) { 1032 if (reachable(counter_addr)) { 1033 atomic_incq(as_Address(counter_addr)); 1034 } else { 1035 lea(scr, counter_addr); 1036 atomic_incq(Address(scr, 0)); 1037 } 1038 } 1039 #endif 1040 1041 // Writes to stack successive pages until offset reached to check for 1042 // stack overflow + shadow pages. This clobbers tmp. 1043 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 1044 movptr(tmp, rsp); 1045 // Bang stack for total size given plus shadow page size. 1046 // Bang one page at a time because large size can bang beyond yellow and 1047 // red zones. 1048 Label loop; 1049 bind(loop); 1050 movl(Address(tmp, (-os::vm_page_size())), size ); 1051 subptr(tmp, os::vm_page_size()); 1052 subl(size, os::vm_page_size()); 1053 jcc(Assembler::greater, loop); 1054 1055 // Bang down shadow pages too. 1056 // At this point, (tmp-0) is the last address touched, so don't 1057 // touch it again. (It was touched as (tmp-pagesize) but then tmp 1058 // was post-decremented.) Skip this address by starting at i=1, and 1059 // touch a few more pages below. N.B. It is important to touch all 1060 // the way down including all pages in the shadow zone. 1061 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) { 1062 // this could be any sized move but this is can be a debugging crumb 1063 // so the bigger the better. 1064 movptr(Address(tmp, (-i*os::vm_page_size())), size ); 1065 } 1066 } 1067 1068 void MacroAssembler::reserved_stack_check() { 1069 // testing if reserved zone needs to be enabled 1070 Label no_reserved_zone_enabling; 1071 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 1072 NOT_LP64(get_thread(rsi);) 1073 1074 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset())); 1075 jcc(Assembler::below, no_reserved_zone_enabling); 1076 1077 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread); 1078 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); 1079 should_not_reach_here(); 1080 1081 bind(no_reserved_zone_enabling); 1082 } 1083 1084 int MacroAssembler::biased_locking_enter(Register lock_reg, 1085 Register obj_reg, 1086 Register swap_reg, 1087 Register tmp_reg, 1088 bool swap_reg_contains_mark, 1089 Label& done, 1090 Label* slow_case, 1091 BiasedLockingCounters* counters) { 1092 assert(UseBiasedLocking, "why call this otherwise?"); 1093 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); 1094 assert(tmp_reg != noreg, "tmp_reg must be supplied"); 1095 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); 1096 assert(markWord::age_shift == markWord::lock_bits + markWord::biased_lock_bits, "biased locking makes assumptions about bit layout"); 1097 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 1098 NOT_LP64( Address saved_mark_addr(lock_reg, 0); ) 1099 1100 if (PrintBiasedLockingStatistics && counters == NULL) { 1101 counters = BiasedLocking::counters(); 1102 } 1103 // Biased locking 1104 // See whether the lock is currently biased toward our thread and 1105 // whether the epoch is still valid 1106 // Note that the runtime guarantees sufficient alignment of JavaThread 1107 // pointers to allow age to be placed into low bits 1108 // First check to see whether biasing is even enabled for this object 1109 Label cas_label; 1110 int null_check_offset = -1; 1111 if (!swap_reg_contains_mark) { 1112 null_check_offset = offset(); 1113 movptr(swap_reg, mark_addr); 1114 } 1115 movptr(tmp_reg, swap_reg); 1116 andptr(tmp_reg, markWord::biased_lock_mask_in_place); 1117 cmpptr(tmp_reg, markWord::biased_lock_pattern); 1118 jcc(Assembler::notEqual, cas_label); 1119 // The bias pattern is present in the object's header. Need to check 1120 // whether the bias owner and the epoch are both still current. 1121 #ifndef _LP64 1122 // Note that because there is no current thread register on x86_32 we 1123 // need to store off the mark word we read out of the object to 1124 // avoid reloading it and needing to recheck invariants below. This 1125 // store is unfortunate but it makes the overall code shorter and 1126 // simpler. 1127 movptr(saved_mark_addr, swap_reg); 1128 #endif 1129 if (swap_reg_contains_mark) { 1130 null_check_offset = offset(); 1131 } 1132 load_prototype_header(tmp_reg, obj_reg); 1133 #ifdef _LP64 1134 orptr(tmp_reg, r15_thread); 1135 xorptr(tmp_reg, swap_reg); 1136 Register header_reg = tmp_reg; 1137 #else 1138 xorptr(tmp_reg, swap_reg); 1139 get_thread(swap_reg); 1140 xorptr(swap_reg, tmp_reg); 1141 Register header_reg = swap_reg; 1142 #endif 1143 andptr(header_reg, ~((int) markWord::age_mask_in_place)); 1144 if (counters != NULL) { 1145 cond_inc32(Assembler::zero, 1146 ExternalAddress((address) counters->biased_lock_entry_count_addr())); 1147 } 1148 jcc(Assembler::equal, done); 1149 1150 Label try_revoke_bias; 1151 Label try_rebias; 1152 1153 // At this point we know that the header has the bias pattern and 1154 // that we are not the bias owner in the current epoch. We need to 1155 // figure out more details about the state of the header in order to 1156 // know what operations can be legally performed on the object's 1157 // header. 1158 1159 // If the low three bits in the xor result aren't clear, that means 1160 // the prototype header is no longer biased and we have to revoke 1161 // the bias on this object. 1162 testptr(header_reg, markWord::biased_lock_mask_in_place); 1163 jccb(Assembler::notZero, try_revoke_bias); 1164 1165 // Biasing is still enabled for this data type. See whether the 1166 // epoch of the current bias is still valid, meaning that the epoch 1167 // bits of the mark word are equal to the epoch bits of the 1168 // prototype header. (Note that the prototype header's epoch bits 1169 // only change at a safepoint.) If not, attempt to rebias the object 1170 // toward the current thread. Note that we must be absolutely sure 1171 // that the current epoch is invalid in order to do this because 1172 // otherwise the manipulations it performs on the mark word are 1173 // illegal. 1174 testptr(header_reg, markWord::epoch_mask_in_place); 1175 jccb(Assembler::notZero, try_rebias); 1176 1177 // The epoch of the current bias is still valid but we know nothing 1178 // about the owner; it might be set or it might be clear. Try to 1179 // acquire the bias of the object using an atomic operation. If this 1180 // fails we will go in to the runtime to revoke the object's bias. 1181 // Note that we first construct the presumed unbiased header so we 1182 // don't accidentally blow away another thread's valid bias. 1183 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1184 andptr(swap_reg, 1185 markWord::biased_lock_mask_in_place | markWord::age_mask_in_place | markWord::epoch_mask_in_place); 1186 #ifdef _LP64 1187 movptr(tmp_reg, swap_reg); 1188 orptr(tmp_reg, r15_thread); 1189 #else 1190 get_thread(tmp_reg); 1191 orptr(tmp_reg, swap_reg); 1192 #endif 1193 lock(); 1194 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1195 // If the biasing toward our thread failed, this means that 1196 // another thread succeeded in biasing it toward itself and we 1197 // need to revoke that bias. The revocation will occur in the 1198 // interpreter runtime in the slow case. 1199 if (counters != NULL) { 1200 cond_inc32(Assembler::zero, 1201 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); 1202 } 1203 if (slow_case != NULL) { 1204 jcc(Assembler::notZero, *slow_case); 1205 } 1206 jmp(done); 1207 1208 bind(try_rebias); 1209 // At this point we know the epoch has expired, meaning that the 1210 // current "bias owner", if any, is actually invalid. Under these 1211 // circumstances _only_, we are allowed to use the current header's 1212 // value as the comparison value when doing the cas to acquire the 1213 // bias in the current epoch. In other words, we allow transfer of 1214 // the bias from one thread to another directly in this situation. 1215 // 1216 // FIXME: due to a lack of registers we currently blow away the age 1217 // bits in this situation. Should attempt to preserve them. 1218 load_prototype_header(tmp_reg, obj_reg); 1219 #ifdef _LP64 1220 orptr(tmp_reg, r15_thread); 1221 #else 1222 get_thread(swap_reg); 1223 orptr(tmp_reg, swap_reg); 1224 movptr(swap_reg, saved_mark_addr); 1225 #endif 1226 lock(); 1227 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1228 // If the biasing toward our thread failed, then another thread 1229 // succeeded in biasing it toward itself and we need to revoke that 1230 // bias. The revocation will occur in the runtime in the slow case. 1231 if (counters != NULL) { 1232 cond_inc32(Assembler::zero, 1233 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); 1234 } 1235 if (slow_case != NULL) { 1236 jcc(Assembler::notZero, *slow_case); 1237 } 1238 jmp(done); 1239 1240 bind(try_revoke_bias); 1241 // The prototype mark in the klass doesn't have the bias bit set any 1242 // more, indicating that objects of this data type are not supposed 1243 // to be biased any more. We are going to try to reset the mark of 1244 // this object to the prototype value and fall through to the 1245 // CAS-based locking scheme. Note that if our CAS fails, it means 1246 // that another thread raced us for the privilege of revoking the 1247 // bias of this particular object, so it's okay to continue in the 1248 // normal locking code. 1249 // 1250 // FIXME: due to a lack of registers we currently blow away the age 1251 // bits in this situation. Should attempt to preserve them. 1252 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1253 load_prototype_header(tmp_reg, obj_reg); 1254 lock(); 1255 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1256 // Fall through to the normal CAS-based lock, because no matter what 1257 // the result of the above CAS, some thread must have succeeded in 1258 // removing the bias bit from the object's header. 1259 if (counters != NULL) { 1260 cond_inc32(Assembler::zero, 1261 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); 1262 } 1263 1264 bind(cas_label); 1265 1266 return null_check_offset; 1267 } 1268 1269 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 1270 assert(UseBiasedLocking, "why call this otherwise?"); 1271 1272 // Check for biased locking unlock case, which is a no-op 1273 // Note: we do not have to check the thread ID for two reasons. 1274 // First, the interpreter checks for IllegalMonitorStateException at 1275 // a higher level. Second, if the bias was revoked while we held the 1276 // lock, the object could not be rebiased toward another thread, so 1277 // the bias bit would be clear. 1278 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 1279 andptr(temp_reg, markWord::biased_lock_mask_in_place); 1280 cmpptr(temp_reg, markWord::biased_lock_pattern); 1281 jcc(Assembler::equal, done); 1282 } 1283 1284 void MacroAssembler::c2bool(Register x) { 1285 // implements x == 0 ? 0 : 1 1286 // note: must only look at least-significant byte of x 1287 // since C-style booleans are stored in one byte 1288 // only! (was bug) 1289 andl(x, 0xFF); 1290 setb(Assembler::notZero, x); 1291 } 1292 1293 // Wouldn't need if AddressLiteral version had new name 1294 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 1295 Assembler::call(L, rtype); 1296 } 1297 1298 void MacroAssembler::call(Register entry) { 1299 Assembler::call(entry); 1300 } 1301 1302 void MacroAssembler::call(AddressLiteral entry) { 1303 if (reachable(entry)) { 1304 Assembler::call_literal(entry.target(), entry.rspec()); 1305 } else { 1306 lea(rscratch1, entry); 1307 Assembler::call(rscratch1); 1308 } 1309 } 1310 1311 void MacroAssembler::ic_call(address entry, jint method_index) { 1312 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 1313 movptr(rax, (intptr_t)Universe::non_oop_word()); 1314 call(AddressLiteral(entry, rh)); 1315 } 1316 1317 // Implementation of call_VM versions 1318 1319 void MacroAssembler::call_VM(Register oop_result, 1320 address entry_point, 1321 bool check_exceptions) { 1322 Label C, E; 1323 call(C, relocInfo::none); 1324 jmp(E); 1325 1326 bind(C); 1327 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 1328 ret(0); 1329 1330 bind(E); 1331 } 1332 1333 void MacroAssembler::call_VM(Register oop_result, 1334 address entry_point, 1335 Register arg_1, 1336 bool check_exceptions) { 1337 Label C, E; 1338 call(C, relocInfo::none); 1339 jmp(E); 1340 1341 bind(C); 1342 pass_arg1(this, arg_1); 1343 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 1344 ret(0); 1345 1346 bind(E); 1347 } 1348 1349 void MacroAssembler::call_VM(Register oop_result, 1350 address entry_point, 1351 Register arg_1, 1352 Register arg_2, 1353 bool check_exceptions) { 1354 Label C, E; 1355 call(C, relocInfo::none); 1356 jmp(E); 1357 1358 bind(C); 1359 1360 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1361 1362 pass_arg2(this, arg_2); 1363 pass_arg1(this, arg_1); 1364 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 1365 ret(0); 1366 1367 bind(E); 1368 } 1369 1370 void MacroAssembler::call_VM(Register oop_result, 1371 address entry_point, 1372 Register arg_1, 1373 Register arg_2, 1374 Register arg_3, 1375 bool check_exceptions) { 1376 Label C, E; 1377 call(C, relocInfo::none); 1378 jmp(E); 1379 1380 bind(C); 1381 1382 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 1383 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 1384 pass_arg3(this, arg_3); 1385 1386 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1387 pass_arg2(this, arg_2); 1388 1389 pass_arg1(this, arg_1); 1390 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 1391 ret(0); 1392 1393 bind(E); 1394 } 1395 1396 void MacroAssembler::call_VM(Register oop_result, 1397 Register last_java_sp, 1398 address entry_point, 1399 int number_of_arguments, 1400 bool check_exceptions) { 1401 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 1402 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 1403 } 1404 1405 void MacroAssembler::call_VM(Register oop_result, 1406 Register last_java_sp, 1407 address entry_point, 1408 Register arg_1, 1409 bool check_exceptions) { 1410 pass_arg1(this, arg_1); 1411 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 1412 } 1413 1414 void MacroAssembler::call_VM(Register oop_result, 1415 Register last_java_sp, 1416 address entry_point, 1417 Register arg_1, 1418 Register arg_2, 1419 bool check_exceptions) { 1420 1421 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1422 pass_arg2(this, arg_2); 1423 pass_arg1(this, arg_1); 1424 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 1425 } 1426 1427 void MacroAssembler::call_VM(Register oop_result, 1428 Register last_java_sp, 1429 address entry_point, 1430 Register arg_1, 1431 Register arg_2, 1432 Register arg_3, 1433 bool check_exceptions) { 1434 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 1435 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 1436 pass_arg3(this, arg_3); 1437 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1438 pass_arg2(this, arg_2); 1439 pass_arg1(this, arg_1); 1440 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 1441 } 1442 1443 void MacroAssembler::super_call_VM(Register oop_result, 1444 Register last_java_sp, 1445 address entry_point, 1446 int number_of_arguments, 1447 bool check_exceptions) { 1448 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 1449 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 1450 } 1451 1452 void MacroAssembler::super_call_VM(Register oop_result, 1453 Register last_java_sp, 1454 address entry_point, 1455 Register arg_1, 1456 bool check_exceptions) { 1457 pass_arg1(this, arg_1); 1458 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 1459 } 1460 1461 void MacroAssembler::super_call_VM(Register oop_result, 1462 Register last_java_sp, 1463 address entry_point, 1464 Register arg_1, 1465 Register arg_2, 1466 bool check_exceptions) { 1467 1468 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1469 pass_arg2(this, arg_2); 1470 pass_arg1(this, arg_1); 1471 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 1472 } 1473 1474 void MacroAssembler::super_call_VM(Register oop_result, 1475 Register last_java_sp, 1476 address entry_point, 1477 Register arg_1, 1478 Register arg_2, 1479 Register arg_3, 1480 bool check_exceptions) { 1481 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 1482 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 1483 pass_arg3(this, arg_3); 1484 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1485 pass_arg2(this, arg_2); 1486 pass_arg1(this, arg_1); 1487 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 1488 } 1489 1490 void MacroAssembler::call_VM_base(Register oop_result, 1491 Register java_thread, 1492 Register last_java_sp, 1493 address entry_point, 1494 int number_of_arguments, 1495 bool check_exceptions) { 1496 // determine java_thread register 1497 if (!java_thread->is_valid()) { 1498 #ifdef _LP64 1499 java_thread = r15_thread; 1500 #else 1501 java_thread = rdi; 1502 get_thread(java_thread); 1503 #endif // LP64 1504 } 1505 // determine last_java_sp register 1506 if (!last_java_sp->is_valid()) { 1507 last_java_sp = rsp; 1508 } 1509 // debugging support 1510 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 1511 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 1512 #ifdef ASSERT 1513 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 1514 // r12 is the heapbase. 1515 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) 1516 #endif // ASSERT 1517 1518 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 1519 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 1520 1521 // push java thread (becomes first argument of C function) 1522 1523 NOT_LP64(push(java_thread); number_of_arguments++); 1524 LP64_ONLY(mov(c_rarg0, r15_thread)); 1525 1526 // set last Java frame before call 1527 assert(last_java_sp != rbp, "can't use ebp/rbp"); 1528 1529 // Only interpreter should have to set fp 1530 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); 1531 1532 // do the call, remove parameters 1533 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 1534 1535 // restore the thread (cannot use the pushed argument since arguments 1536 // may be overwritten by C code generated by an optimizing compiler); 1537 // however can use the register value directly if it is callee saved. 1538 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 1539 // rdi & rsi (also r15) are callee saved -> nothing to do 1540 #ifdef ASSERT 1541 guarantee(java_thread != rax, "change this code"); 1542 push(rax); 1543 { Label L; 1544 get_thread(rax); 1545 cmpptr(java_thread, rax); 1546 jcc(Assembler::equal, L); 1547 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); 1548 bind(L); 1549 } 1550 pop(rax); 1551 #endif 1552 } else { 1553 get_thread(java_thread); 1554 } 1555 // reset last Java frame 1556 // Only interpreter should have to clear fp 1557 reset_last_Java_frame(java_thread, true); 1558 1559 // C++ interp handles this in the interpreter 1560 check_and_handle_popframe(java_thread); 1561 check_and_handle_earlyret(java_thread); 1562 1563 if (check_exceptions) { 1564 // check for pending exceptions (java_thread is set upon return) 1565 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); 1566 #ifndef _LP64 1567 jump_cc(Assembler::notEqual, 1568 RuntimeAddress(StubRoutines::forward_exception_entry())); 1569 #else 1570 // This used to conditionally jump to forward_exception however it is 1571 // possible if we relocate that the branch will not reach. So we must jump 1572 // around so we can always reach 1573 1574 Label ok; 1575 jcc(Assembler::equal, ok); 1576 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 1577 bind(ok); 1578 #endif // LP64 1579 } 1580 1581 // get oop result if there is one and reset the value in the thread 1582 if (oop_result->is_valid()) { 1583 get_vm_result(oop_result, java_thread); 1584 } 1585 } 1586 1587 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 1588 1589 // Calculate the value for last_Java_sp 1590 // somewhat subtle. call_VM does an intermediate call 1591 // which places a return address on the stack just under the 1592 // stack pointer as the user finsihed with it. This allows 1593 // use to retrieve last_Java_pc from last_Java_sp[-1]. 1594 // On 32bit we then have to push additional args on the stack to accomplish 1595 // the actual requested call. On 64bit call_VM only can use register args 1596 // so the only extra space is the return address that call_VM created. 1597 // This hopefully explains the calculations here. 1598 1599 #ifdef _LP64 1600 // We've pushed one address, correct last_Java_sp 1601 lea(rax, Address(rsp, wordSize)); 1602 #else 1603 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 1604 #endif // LP64 1605 1606 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 1607 1608 } 1609 1610 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter. 1611 void MacroAssembler::call_VM_leaf0(address entry_point) { 1612 MacroAssembler::call_VM_leaf_base(entry_point, 0); 1613 } 1614 1615 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 1616 call_VM_leaf_base(entry_point, number_of_arguments); 1617 } 1618 1619 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 1620 pass_arg0(this, arg_0); 1621 call_VM_leaf(entry_point, 1); 1622 } 1623 1624 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1625 1626 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1627 pass_arg1(this, arg_1); 1628 pass_arg0(this, arg_0); 1629 call_VM_leaf(entry_point, 2); 1630 } 1631 1632 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 1633 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 1634 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1635 pass_arg2(this, arg_2); 1636 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1637 pass_arg1(this, arg_1); 1638 pass_arg0(this, arg_0); 1639 call_VM_leaf(entry_point, 3); 1640 } 1641 1642 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 1643 pass_arg0(this, arg_0); 1644 MacroAssembler::call_VM_leaf_base(entry_point, 1); 1645 } 1646 1647 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1648 1649 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1650 pass_arg1(this, arg_1); 1651 pass_arg0(this, arg_0); 1652 MacroAssembler::call_VM_leaf_base(entry_point, 2); 1653 } 1654 1655 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 1656 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 1657 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1658 pass_arg2(this, arg_2); 1659 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1660 pass_arg1(this, arg_1); 1661 pass_arg0(this, arg_0); 1662 MacroAssembler::call_VM_leaf_base(entry_point, 3); 1663 } 1664 1665 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 1666 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 1667 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 1668 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 1669 pass_arg3(this, arg_3); 1670 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 1671 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1672 pass_arg2(this, arg_2); 1673 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1674 pass_arg1(this, arg_1); 1675 pass_arg0(this, arg_0); 1676 MacroAssembler::call_VM_leaf_base(entry_point, 4); 1677 } 1678 1679 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 1680 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 1681 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 1682 verify_oop_msg(oop_result, "broken oop in call_VM_base"); 1683 } 1684 1685 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 1686 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 1687 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); 1688 } 1689 1690 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 1691 } 1692 1693 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 1694 } 1695 1696 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { 1697 if (reachable(src1)) { 1698 cmpl(as_Address(src1), imm); 1699 } else { 1700 lea(rscratch1, src1); 1701 cmpl(Address(rscratch1, 0), imm); 1702 } 1703 } 1704 1705 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { 1706 assert(!src2.is_lval(), "use cmpptr"); 1707 if (reachable(src2)) { 1708 cmpl(src1, as_Address(src2)); 1709 } else { 1710 lea(rscratch1, src2); 1711 cmpl(src1, Address(rscratch1, 0)); 1712 } 1713 } 1714 1715 void MacroAssembler::cmp32(Register src1, int32_t imm) { 1716 Assembler::cmpl(src1, imm); 1717 } 1718 1719 void MacroAssembler::cmp32(Register src1, Address src2) { 1720 Assembler::cmpl(src1, src2); 1721 } 1722 1723 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 1724 ucomisd(opr1, opr2); 1725 1726 Label L; 1727 if (unordered_is_less) { 1728 movl(dst, -1); 1729 jcc(Assembler::parity, L); 1730 jcc(Assembler::below , L); 1731 movl(dst, 0); 1732 jcc(Assembler::equal , L); 1733 increment(dst); 1734 } else { // unordered is greater 1735 movl(dst, 1); 1736 jcc(Assembler::parity, L); 1737 jcc(Assembler::above , L); 1738 movl(dst, 0); 1739 jcc(Assembler::equal , L); 1740 decrementl(dst); 1741 } 1742 bind(L); 1743 } 1744 1745 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 1746 ucomiss(opr1, opr2); 1747 1748 Label L; 1749 if (unordered_is_less) { 1750 movl(dst, -1); 1751 jcc(Assembler::parity, L); 1752 jcc(Assembler::below , L); 1753 movl(dst, 0); 1754 jcc(Assembler::equal , L); 1755 increment(dst); 1756 } else { // unordered is greater 1757 movl(dst, 1); 1758 jcc(Assembler::parity, L); 1759 jcc(Assembler::above , L); 1760 movl(dst, 0); 1761 jcc(Assembler::equal , L); 1762 decrementl(dst); 1763 } 1764 bind(L); 1765 } 1766 1767 1768 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { 1769 if (reachable(src1)) { 1770 cmpb(as_Address(src1), imm); 1771 } else { 1772 lea(rscratch1, src1); 1773 cmpb(Address(rscratch1, 0), imm); 1774 } 1775 } 1776 1777 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { 1778 #ifdef _LP64 1779 if (src2.is_lval()) { 1780 movptr(rscratch1, src2); 1781 Assembler::cmpq(src1, rscratch1); 1782 } else if (reachable(src2)) { 1783 cmpq(src1, as_Address(src2)); 1784 } else { 1785 lea(rscratch1, src2); 1786 Assembler::cmpq(src1, Address(rscratch1, 0)); 1787 } 1788 #else 1789 if (src2.is_lval()) { 1790 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 1791 } else { 1792 cmpl(src1, as_Address(src2)); 1793 } 1794 #endif // _LP64 1795 } 1796 1797 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { 1798 assert(src2.is_lval(), "not a mem-mem compare"); 1799 #ifdef _LP64 1800 // moves src2's literal address 1801 movptr(rscratch1, src2); 1802 Assembler::cmpq(src1, rscratch1); 1803 #else 1804 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 1805 #endif // _LP64 1806 } 1807 1808 void MacroAssembler::cmpoop(Register src1, Register src2) { 1809 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 1810 bs->obj_equals(this, src1, src2); 1811 } 1812 1813 void MacroAssembler::cmpoop(Register src1, Address src2) { 1814 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 1815 bs->obj_equals(this, src1, src2); 1816 } 1817 1818 #ifdef _LP64 1819 void MacroAssembler::cmpoop(Register src1, jobject src2) { 1820 movoop(rscratch1, src2); 1821 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 1822 bs->obj_equals(this, src1, rscratch1); 1823 } 1824 #endif 1825 1826 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { 1827 if (reachable(adr)) { 1828 lock(); 1829 cmpxchgptr(reg, as_Address(adr)); 1830 } else { 1831 lea(rscratch1, adr); 1832 lock(); 1833 cmpxchgptr(reg, Address(rscratch1, 0)); 1834 } 1835 } 1836 1837 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 1838 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 1839 } 1840 1841 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 1842 if (reachable(src)) { 1843 Assembler::comisd(dst, as_Address(src)); 1844 } else { 1845 lea(rscratch1, src); 1846 Assembler::comisd(dst, Address(rscratch1, 0)); 1847 } 1848 } 1849 1850 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 1851 if (reachable(src)) { 1852 Assembler::comiss(dst, as_Address(src)); 1853 } else { 1854 lea(rscratch1, src); 1855 Assembler::comiss(dst, Address(rscratch1, 0)); 1856 } 1857 } 1858 1859 1860 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 1861 Condition negated_cond = negate_condition(cond); 1862 Label L; 1863 jcc(negated_cond, L); 1864 pushf(); // Preserve flags 1865 atomic_incl(counter_addr); 1866 popf(); 1867 bind(L); 1868 } 1869 1870 int MacroAssembler::corrected_idivl(Register reg) { 1871 // Full implementation of Java idiv and irem; checks for 1872 // special case as described in JVM spec., p.243 & p.271. 1873 // The function returns the (pc) offset of the idivl 1874 // instruction - may be needed for implicit exceptions. 1875 // 1876 // normal case special case 1877 // 1878 // input : rax,: dividend min_int 1879 // reg: divisor (may not be rax,/rdx) -1 1880 // 1881 // output: rax,: quotient (= rax, idiv reg) min_int 1882 // rdx: remainder (= rax, irem reg) 0 1883 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 1884 const int min_int = 0x80000000; 1885 Label normal_case, special_case; 1886 1887 // check for special case 1888 cmpl(rax, min_int); 1889 jcc(Assembler::notEqual, normal_case); 1890 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 1891 cmpl(reg, -1); 1892 jcc(Assembler::equal, special_case); 1893 1894 // handle normal case 1895 bind(normal_case); 1896 cdql(); 1897 int idivl_offset = offset(); 1898 idivl(reg); 1899 1900 // normal and special case exit 1901 bind(special_case); 1902 1903 return idivl_offset; 1904 } 1905 1906 1907 1908 void MacroAssembler::decrementl(Register reg, int value) { 1909 if (value == min_jint) {subl(reg, value) ; return; } 1910 if (value < 0) { incrementl(reg, -value); return; } 1911 if (value == 0) { ; return; } 1912 if (value == 1 && UseIncDec) { decl(reg) ; return; } 1913 /* else */ { subl(reg, value) ; return; } 1914 } 1915 1916 void MacroAssembler::decrementl(Address dst, int value) { 1917 if (value == min_jint) {subl(dst, value) ; return; } 1918 if (value < 0) { incrementl(dst, -value); return; } 1919 if (value == 0) { ; return; } 1920 if (value == 1 && UseIncDec) { decl(dst) ; return; } 1921 /* else */ { subl(dst, value) ; return; } 1922 } 1923 1924 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 1925 assert (shift_value > 0, "illegal shift value"); 1926 Label _is_positive; 1927 testl (reg, reg); 1928 jcc (Assembler::positive, _is_positive); 1929 int offset = (1 << shift_value) - 1 ; 1930 1931 if (offset == 1) { 1932 incrementl(reg); 1933 } else { 1934 addl(reg, offset); 1935 } 1936 1937 bind (_is_positive); 1938 sarl(reg, shift_value); 1939 } 1940 1941 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { 1942 if (reachable(src)) { 1943 Assembler::divsd(dst, as_Address(src)); 1944 } else { 1945 lea(rscratch1, src); 1946 Assembler::divsd(dst, Address(rscratch1, 0)); 1947 } 1948 } 1949 1950 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { 1951 if (reachable(src)) { 1952 Assembler::divss(dst, as_Address(src)); 1953 } else { 1954 lea(rscratch1, src); 1955 Assembler::divss(dst, Address(rscratch1, 0)); 1956 } 1957 } 1958 1959 void MacroAssembler::enter() { 1960 push(rbp); 1961 mov(rbp, rsp); 1962 } 1963 1964 // A 5 byte nop that is safe for patching (see patch_verified_entry) 1965 void MacroAssembler::fat_nop() { 1966 if (UseAddressNop) { 1967 addr_nop_5(); 1968 } else { 1969 emit_int8(0x26); // es: 1970 emit_int8(0x2e); // cs: 1971 emit_int8(0x64); // fs: 1972 emit_int8(0x65); // gs: 1973 emit_int8((unsigned char)0x90); 1974 } 1975 } 1976 1977 #ifndef _LP64 1978 void MacroAssembler::fcmp(Register tmp) { 1979 fcmp(tmp, 1, true, true); 1980 } 1981 1982 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 1983 assert(!pop_right || pop_left, "usage error"); 1984 if (VM_Version::supports_cmov()) { 1985 assert(tmp == noreg, "unneeded temp"); 1986 if (pop_left) { 1987 fucomip(index); 1988 } else { 1989 fucomi(index); 1990 } 1991 if (pop_right) { 1992 fpop(); 1993 } 1994 } else { 1995 assert(tmp != noreg, "need temp"); 1996 if (pop_left) { 1997 if (pop_right) { 1998 fcompp(); 1999 } else { 2000 fcomp(index); 2001 } 2002 } else { 2003 fcom(index); 2004 } 2005 // convert FPU condition into eflags condition via rax, 2006 save_rax(tmp); 2007 fwait(); fnstsw_ax(); 2008 sahf(); 2009 restore_rax(tmp); 2010 } 2011 // condition codes set as follows: 2012 // 2013 // CF (corresponds to C0) if x < y 2014 // PF (corresponds to C2) if unordered 2015 // ZF (corresponds to C3) if x = y 2016 } 2017 2018 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 2019 fcmp2int(dst, unordered_is_less, 1, true, true); 2020 } 2021 2022 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 2023 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 2024 Label L; 2025 if (unordered_is_less) { 2026 movl(dst, -1); 2027 jcc(Assembler::parity, L); 2028 jcc(Assembler::below , L); 2029 movl(dst, 0); 2030 jcc(Assembler::equal , L); 2031 increment(dst); 2032 } else { // unordered is greater 2033 movl(dst, 1); 2034 jcc(Assembler::parity, L); 2035 jcc(Assembler::above , L); 2036 movl(dst, 0); 2037 jcc(Assembler::equal , L); 2038 decrementl(dst); 2039 } 2040 bind(L); 2041 } 2042 2043 void MacroAssembler::fld_d(AddressLiteral src) { 2044 fld_d(as_Address(src)); 2045 } 2046 2047 void MacroAssembler::fld_s(AddressLiteral src) { 2048 fld_s(as_Address(src)); 2049 } 2050 2051 void MacroAssembler::fld_x(AddressLiteral src) { 2052 Assembler::fld_x(as_Address(src)); 2053 } 2054 2055 void MacroAssembler::fldcw(AddressLiteral src) { 2056 Assembler::fldcw(as_Address(src)); 2057 } 2058 2059 void MacroAssembler::fpop() { 2060 ffree(); 2061 fincstp(); 2062 } 2063 2064 void MacroAssembler::fremr(Register tmp) { 2065 save_rax(tmp); 2066 { Label L; 2067 bind(L); 2068 fprem(); 2069 fwait(); fnstsw_ax(); 2070 sahf(); 2071 jcc(Assembler::parity, L); 2072 } 2073 restore_rax(tmp); 2074 // Result is in ST0. 2075 // Note: fxch & fpop to get rid of ST1 2076 // (otherwise FPU stack could overflow eventually) 2077 fxch(1); 2078 fpop(); 2079 } 2080 2081 void MacroAssembler::empty_FPU_stack() { 2082 if (VM_Version::supports_mmx()) { 2083 emms(); 2084 } else { 2085 for (int i = 8; i-- > 0; ) ffree(i); 2086 } 2087 } 2088 #endif // !LP64 2089 2090 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) { 2091 if (reachable(src)) { 2092 Assembler::mulpd(dst, as_Address(src)); 2093 } else { 2094 lea(rscratch1, src); 2095 Assembler::mulpd(dst, Address(rscratch1, 0)); 2096 } 2097 } 2098 2099 void MacroAssembler::load_float(Address src) { 2100 #ifdef _LP64 2101 movflt(xmm0, src); 2102 #else 2103 if (UseSSE >= 1) { 2104 movflt(xmm0, src); 2105 } else { 2106 fld_s(src); 2107 } 2108 #endif // LP64 2109 } 2110 2111 void MacroAssembler::store_float(Address dst) { 2112 #ifdef _LP64 2113 movflt(dst, xmm0); 2114 #else 2115 if (UseSSE >= 1) { 2116 movflt(dst, xmm0); 2117 } else { 2118 fstp_s(dst); 2119 } 2120 #endif // LP64 2121 } 2122 2123 void MacroAssembler::load_double(Address src) { 2124 #ifdef _LP64 2125 movdbl(xmm0, src); 2126 #else 2127 if (UseSSE >= 2) { 2128 movdbl(xmm0, src); 2129 } else { 2130 fld_d(src); 2131 } 2132 #endif // LP64 2133 } 2134 2135 void MacroAssembler::store_double(Address dst) { 2136 #ifdef _LP64 2137 movdbl(dst, xmm0); 2138 #else 2139 if (UseSSE >= 2) { 2140 movdbl(dst, xmm0); 2141 } else { 2142 fstp_d(dst); 2143 } 2144 #endif // LP64 2145 } 2146 2147 // dst = c = a * b + c 2148 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 2149 Assembler::vfmadd231sd(c, a, b); 2150 if (dst != c) { 2151 movdbl(dst, c); 2152 } 2153 } 2154 2155 // dst = c = a * b + c 2156 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 2157 Assembler::vfmadd231ss(c, a, b); 2158 if (dst != c) { 2159 movflt(dst, c); 2160 } 2161 } 2162 2163 // dst = c = a * b + c 2164 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) { 2165 Assembler::vfmadd231pd(c, a, b, vector_len); 2166 if (dst != c) { 2167 vmovdqu(dst, c); 2168 } 2169 } 2170 2171 // dst = c = a * b + c 2172 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) { 2173 Assembler::vfmadd231ps(c, a, b, vector_len); 2174 if (dst != c) { 2175 vmovdqu(dst, c); 2176 } 2177 } 2178 2179 // dst = c = a * b + c 2180 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) { 2181 Assembler::vfmadd231pd(c, a, b, vector_len); 2182 if (dst != c) { 2183 vmovdqu(dst, c); 2184 } 2185 } 2186 2187 // dst = c = a * b + c 2188 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) { 2189 Assembler::vfmadd231ps(c, a, b, vector_len); 2190 if (dst != c) { 2191 vmovdqu(dst, c); 2192 } 2193 } 2194 2195 void MacroAssembler::incrementl(AddressLiteral dst) { 2196 if (reachable(dst)) { 2197 incrementl(as_Address(dst)); 2198 } else { 2199 lea(rscratch1, dst); 2200 incrementl(Address(rscratch1, 0)); 2201 } 2202 } 2203 2204 void MacroAssembler::incrementl(ArrayAddress dst) { 2205 incrementl(as_Address(dst)); 2206 } 2207 2208 void MacroAssembler::incrementl(Register reg, int value) { 2209 if (value == min_jint) {addl(reg, value) ; return; } 2210 if (value < 0) { decrementl(reg, -value); return; } 2211 if (value == 0) { ; return; } 2212 if (value == 1 && UseIncDec) { incl(reg) ; return; } 2213 /* else */ { addl(reg, value) ; return; } 2214 } 2215 2216 void MacroAssembler::incrementl(Address dst, int value) { 2217 if (value == min_jint) {addl(dst, value) ; return; } 2218 if (value < 0) { decrementl(dst, -value); return; } 2219 if (value == 0) { ; return; } 2220 if (value == 1 && UseIncDec) { incl(dst) ; return; } 2221 /* else */ { addl(dst, value) ; return; } 2222 } 2223 2224 void MacroAssembler::jump(AddressLiteral dst) { 2225 if (reachable(dst)) { 2226 jmp_literal(dst.target(), dst.rspec()); 2227 } else { 2228 lea(rscratch1, dst); 2229 jmp(rscratch1); 2230 } 2231 } 2232 2233 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { 2234 if (reachable(dst)) { 2235 InstructionMark im(this); 2236 relocate(dst.reloc()); 2237 const int short_size = 2; 2238 const int long_size = 6; 2239 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); 2240 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 2241 // 0111 tttn #8-bit disp 2242 emit_int8(0x70 | cc); 2243 emit_int8((offs - short_size) & 0xFF); 2244 } else { 2245 // 0000 1111 1000 tttn #32-bit disp 2246 emit_int8(0x0F); 2247 emit_int8((unsigned char)(0x80 | cc)); 2248 emit_int32(offs - long_size); 2249 } 2250 } else { 2251 #ifdef ASSERT 2252 warning("reversing conditional branch"); 2253 #endif /* ASSERT */ 2254 Label skip; 2255 jccb(reverse[cc], skip); 2256 lea(rscratch1, dst); 2257 Assembler::jmp(rscratch1); 2258 bind(skip); 2259 } 2260 } 2261 2262 void MacroAssembler::ldmxcsr(AddressLiteral src) { 2263 if (reachable(src)) { 2264 Assembler::ldmxcsr(as_Address(src)); 2265 } else { 2266 lea(rscratch1, src); 2267 Assembler::ldmxcsr(Address(rscratch1, 0)); 2268 } 2269 } 2270 2271 int MacroAssembler::load_signed_byte(Register dst, Address src) { 2272 int off; 2273 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 2274 off = offset(); 2275 movsbl(dst, src); // movsxb 2276 } else { 2277 off = load_unsigned_byte(dst, src); 2278 shll(dst, 24); 2279 sarl(dst, 24); 2280 } 2281 return off; 2282 } 2283 2284 // Note: load_signed_short used to be called load_signed_word. 2285 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 2286 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 2287 // The term "word" in HotSpot means a 32- or 64-bit machine word. 2288 int MacroAssembler::load_signed_short(Register dst, Address src) { 2289 int off; 2290 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 2291 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 2292 // version but this is what 64bit has always done. This seems to imply 2293 // that users are only using 32bits worth. 2294 off = offset(); 2295 movswl(dst, src); // movsxw 2296 } else { 2297 off = load_unsigned_short(dst, src); 2298 shll(dst, 16); 2299 sarl(dst, 16); 2300 } 2301 return off; 2302 } 2303 2304 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 2305 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 2306 // and "3.9 Partial Register Penalties", p. 22). 2307 int off; 2308 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 2309 off = offset(); 2310 movzbl(dst, src); // movzxb 2311 } else { 2312 xorl(dst, dst); 2313 off = offset(); 2314 movb(dst, src); 2315 } 2316 return off; 2317 } 2318 2319 // Note: load_unsigned_short used to be called load_unsigned_word. 2320 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 2321 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 2322 // and "3.9 Partial Register Penalties", p. 22). 2323 int off; 2324 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 2325 off = offset(); 2326 movzwl(dst, src); // movzxw 2327 } else { 2328 xorl(dst, dst); 2329 off = offset(); 2330 movw(dst, src); 2331 } 2332 return off; 2333 } 2334 2335 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 2336 switch (size_in_bytes) { 2337 #ifndef _LP64 2338 case 8: 2339 assert(dst2 != noreg, "second dest register required"); 2340 movl(dst, src); 2341 movl(dst2, src.plus_disp(BytesPerInt)); 2342 break; 2343 #else 2344 case 8: movq(dst, src); break; 2345 #endif 2346 case 4: movl(dst, src); break; 2347 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 2348 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 2349 default: ShouldNotReachHere(); 2350 } 2351 } 2352 2353 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 2354 switch (size_in_bytes) { 2355 #ifndef _LP64 2356 case 8: 2357 assert(src2 != noreg, "second source register required"); 2358 movl(dst, src); 2359 movl(dst.plus_disp(BytesPerInt), src2); 2360 break; 2361 #else 2362 case 8: movq(dst, src); break; 2363 #endif 2364 case 4: movl(dst, src); break; 2365 case 2: movw(dst, src); break; 2366 case 1: movb(dst, src); break; 2367 default: ShouldNotReachHere(); 2368 } 2369 } 2370 2371 void MacroAssembler::mov32(AddressLiteral dst, Register src) { 2372 if (reachable(dst)) { 2373 movl(as_Address(dst), src); 2374 } else { 2375 lea(rscratch1, dst); 2376 movl(Address(rscratch1, 0), src); 2377 } 2378 } 2379 2380 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 2381 if (reachable(src)) { 2382 movl(dst, as_Address(src)); 2383 } else { 2384 lea(rscratch1, src); 2385 movl(dst, Address(rscratch1, 0)); 2386 } 2387 } 2388 2389 // C++ bool manipulation 2390 2391 void MacroAssembler::movbool(Register dst, Address src) { 2392 if(sizeof(bool) == 1) 2393 movb(dst, src); 2394 else if(sizeof(bool) == 2) 2395 movw(dst, src); 2396 else if(sizeof(bool) == 4) 2397 movl(dst, src); 2398 else 2399 // unsupported 2400 ShouldNotReachHere(); 2401 } 2402 2403 void MacroAssembler::movbool(Address dst, bool boolconst) { 2404 if(sizeof(bool) == 1) 2405 movb(dst, (int) boolconst); 2406 else if(sizeof(bool) == 2) 2407 movw(dst, (int) boolconst); 2408 else if(sizeof(bool) == 4) 2409 movl(dst, (int) boolconst); 2410 else 2411 // unsupported 2412 ShouldNotReachHere(); 2413 } 2414 2415 void MacroAssembler::movbool(Address dst, Register src) { 2416 if(sizeof(bool) == 1) 2417 movb(dst, src); 2418 else if(sizeof(bool) == 2) 2419 movw(dst, src); 2420 else if(sizeof(bool) == 4) 2421 movl(dst, src); 2422 else 2423 // unsupported 2424 ShouldNotReachHere(); 2425 } 2426 2427 void MacroAssembler::movbyte(ArrayAddress dst, int src) { 2428 movb(as_Address(dst), src); 2429 } 2430 2431 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { 2432 if (reachable(src)) { 2433 movdl(dst, as_Address(src)); 2434 } else { 2435 lea(rscratch1, src); 2436 movdl(dst, Address(rscratch1, 0)); 2437 } 2438 } 2439 2440 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { 2441 if (reachable(src)) { 2442 movq(dst, as_Address(src)); 2443 } else { 2444 lea(rscratch1, src); 2445 movq(dst, Address(rscratch1, 0)); 2446 } 2447 } 2448 2449 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { 2450 if (reachable(src)) { 2451 if (UseXmmLoadAndClearUpper) { 2452 movsd (dst, as_Address(src)); 2453 } else { 2454 movlpd(dst, as_Address(src)); 2455 } 2456 } else { 2457 lea(rscratch1, src); 2458 if (UseXmmLoadAndClearUpper) { 2459 movsd (dst, Address(rscratch1, 0)); 2460 } else { 2461 movlpd(dst, Address(rscratch1, 0)); 2462 } 2463 } 2464 } 2465 2466 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { 2467 if (reachable(src)) { 2468 movss(dst, as_Address(src)); 2469 } else { 2470 lea(rscratch1, src); 2471 movss(dst, Address(rscratch1, 0)); 2472 } 2473 } 2474 2475 void MacroAssembler::movptr(Register dst, Register src) { 2476 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 2477 } 2478 2479 void MacroAssembler::movptr(Register dst, Address src) { 2480 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 2481 } 2482 2483 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 2484 void MacroAssembler::movptr(Register dst, intptr_t src) { 2485 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 2486 } 2487 2488 void MacroAssembler::movptr(Address dst, Register src) { 2489 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 2490 } 2491 2492 void MacroAssembler::movdqu(Address dst, XMMRegister src) { 2493 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2494 Assembler::movdqu(dst, src); 2495 } 2496 2497 void MacroAssembler::movdqu(XMMRegister dst, Address src) { 2498 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2499 Assembler::movdqu(dst, src); 2500 } 2501 2502 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) { 2503 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2504 if (dst->encoding() == src->encoding()) return; 2505 Assembler::movdqu(dst, src); 2506 } 2507 2508 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) { 2509 if (reachable(src)) { 2510 movdqu(dst, as_Address(src)); 2511 } else { 2512 lea(scratchReg, src); 2513 movdqu(dst, Address(scratchReg, 0)); 2514 } 2515 } 2516 2517 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) { 2518 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2519 Assembler::vmovdqu(dst, src); 2520 } 2521 2522 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) { 2523 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2524 Assembler::vmovdqu(dst, src); 2525 } 2526 2527 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) { 2528 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2529 if (dst->encoding() == src->encoding()) return; 2530 Assembler::vmovdqu(dst, src); 2531 } 2532 2533 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg) { 2534 if (reachable(src)) { 2535 vmovdqu(dst, as_Address(src)); 2536 } 2537 else { 2538 lea(scratch_reg, src); 2539 vmovdqu(dst, Address(scratch_reg, 0)); 2540 } 2541 } 2542 2543 2544 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register scratch_reg) { 2545 if (reachable(src)) { 2546 kmovwl(dst, as_Address(src)); 2547 } else { 2548 lea(scratch_reg, src); 2549 kmovwl(dst, Address(scratch_reg, 0)); 2550 } 2551 } 2552 2553 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, 2554 int vector_len, Register scratch_reg) { 2555 if (reachable(src)) { 2556 if (mask == k0) { 2557 Assembler::evmovdqub(dst, as_Address(src), merge, vector_len); 2558 } else { 2559 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len); 2560 } 2561 } else { 2562 lea(scratch_reg, src); 2563 if (mask == k0) { 2564 Assembler::evmovdqub(dst, Address(scratch_reg, 0), merge, vector_len); 2565 } else { 2566 Assembler::evmovdqub(dst, mask, Address(scratch_reg, 0), merge, vector_len); 2567 } 2568 } 2569 } 2570 2571 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, 2572 int vector_len, Register scratch_reg) { 2573 if (reachable(src)) { 2574 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len); 2575 } else { 2576 lea(scratch_reg, src); 2577 Assembler::evmovdquw(dst, mask, Address(scratch_reg, 0), merge, vector_len); 2578 } 2579 } 2580 2581 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, 2582 int vector_len, Register scratch_reg) { 2583 if (reachable(src)) { 2584 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len); 2585 } else { 2586 lea(scratch_reg, src); 2587 Assembler::evmovdqul(dst, mask, Address(scratch_reg, 0), merge, vector_len); 2588 } 2589 } 2590 2591 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, 2592 int vector_len, Register scratch_reg) { 2593 if (reachable(src)) { 2594 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len); 2595 } else { 2596 lea(scratch_reg, src); 2597 Assembler::evmovdquq(dst, mask, Address(scratch_reg, 0), merge, vector_len); 2598 } 2599 } 2600 2601 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) { 2602 if (reachable(src)) { 2603 Assembler::evmovdquq(dst, as_Address(src), vector_len); 2604 } else { 2605 lea(rscratch, src); 2606 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len); 2607 } 2608 } 2609 2610 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) { 2611 if (reachable(src)) { 2612 Assembler::movdqa(dst, as_Address(src)); 2613 } else { 2614 lea(rscratch1, src); 2615 Assembler::movdqa(dst, Address(rscratch1, 0)); 2616 } 2617 } 2618 2619 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 2620 if (reachable(src)) { 2621 Assembler::movsd(dst, as_Address(src)); 2622 } else { 2623 lea(rscratch1, src); 2624 Assembler::movsd(dst, Address(rscratch1, 0)); 2625 } 2626 } 2627 2628 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { 2629 if (reachable(src)) { 2630 Assembler::movss(dst, as_Address(src)); 2631 } else { 2632 lea(rscratch1, src); 2633 Assembler::movss(dst, Address(rscratch1, 0)); 2634 } 2635 } 2636 2637 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { 2638 if (reachable(src)) { 2639 Assembler::mulsd(dst, as_Address(src)); 2640 } else { 2641 lea(rscratch1, src); 2642 Assembler::mulsd(dst, Address(rscratch1, 0)); 2643 } 2644 } 2645 2646 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { 2647 if (reachable(src)) { 2648 Assembler::mulss(dst, as_Address(src)); 2649 } else { 2650 lea(rscratch1, src); 2651 Assembler::mulss(dst, Address(rscratch1, 0)); 2652 } 2653 } 2654 2655 void MacroAssembler::null_check(Register reg, int offset) { 2656 if (needs_explicit_null_check(offset)) { 2657 // provoke OS NULL exception if reg = NULL by 2658 // accessing M[reg] w/o changing any (non-CC) registers 2659 // NOTE: cmpl is plenty here to provoke a segv 2660 cmpptr(rax, Address(reg, 0)); 2661 // Note: should probably use testl(rax, Address(reg, 0)); 2662 // may be shorter code (however, this version of 2663 // testl needs to be implemented first) 2664 } else { 2665 // nothing to do, (later) access of M[reg + offset] 2666 // will provoke OS NULL exception if reg = NULL 2667 } 2668 } 2669 2670 void MacroAssembler::os_breakpoint() { 2671 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 2672 // (e.g., MSVC can't call ps() otherwise) 2673 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 2674 } 2675 2676 void MacroAssembler::unimplemented(const char* what) { 2677 const char* buf = NULL; 2678 { 2679 ResourceMark rm; 2680 stringStream ss; 2681 ss.print("unimplemented: %s", what); 2682 buf = code_string(ss.as_string()); 2683 } 2684 stop(buf); 2685 } 2686 2687 #ifdef _LP64 2688 #define XSTATE_BV 0x200 2689 #endif 2690 2691 void MacroAssembler::pop_CPU_state() { 2692 pop_FPU_state(); 2693 pop_IU_state(); 2694 } 2695 2696 void MacroAssembler::pop_FPU_state() { 2697 #ifndef _LP64 2698 frstor(Address(rsp, 0)); 2699 #else 2700 fxrstor(Address(rsp, 0)); 2701 #endif 2702 addptr(rsp, FPUStateSizeInWords * wordSize); 2703 } 2704 2705 void MacroAssembler::pop_IU_state() { 2706 popa(); 2707 LP64_ONLY(addq(rsp, 8)); 2708 popf(); 2709 } 2710 2711 // Save Integer and Float state 2712 // Warning: Stack must be 16 byte aligned (64bit) 2713 void MacroAssembler::push_CPU_state() { 2714 push_IU_state(); 2715 push_FPU_state(); 2716 } 2717 2718 void MacroAssembler::push_FPU_state() { 2719 subptr(rsp, FPUStateSizeInWords * wordSize); 2720 #ifndef _LP64 2721 fnsave(Address(rsp, 0)); 2722 fwait(); 2723 #else 2724 fxsave(Address(rsp, 0)); 2725 #endif // LP64 2726 } 2727 2728 void MacroAssembler::push_IU_state() { 2729 // Push flags first because pusha kills them 2730 pushf(); 2731 // Make sure rsp stays 16-byte aligned 2732 LP64_ONLY(subq(rsp, 8)); 2733 pusha(); 2734 } 2735 2736 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register 2737 if (!java_thread->is_valid()) { 2738 java_thread = rdi; 2739 get_thread(java_thread); 2740 } 2741 // we must set sp to zero to clear frame 2742 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 2743 if (clear_fp) { 2744 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 2745 } 2746 2747 // Always clear the pc because it could have been set by make_walkable() 2748 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 2749 2750 vzeroupper(); 2751 } 2752 2753 void MacroAssembler::restore_rax(Register tmp) { 2754 if (tmp == noreg) pop(rax); 2755 else if (tmp != rax) mov(rax, tmp); 2756 } 2757 2758 void MacroAssembler::round_to(Register reg, int modulus) { 2759 addptr(reg, modulus - 1); 2760 andptr(reg, -modulus); 2761 } 2762 2763 void MacroAssembler::save_rax(Register tmp) { 2764 if (tmp == noreg) push(rax); 2765 else if (tmp != rax) mov(tmp, rax); 2766 } 2767 2768 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) { 2769 #ifdef _LP64 2770 assert(thread_reg == r15_thread, "should be"); 2771 #else 2772 if (thread_reg == noreg) { 2773 thread_reg = temp_reg; 2774 get_thread(thread_reg); 2775 } 2776 #endif 2777 testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit()); 2778 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll 2779 } 2780 2781 // Calls to C land 2782 // 2783 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 2784 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 2785 // has to be reset to 0. This is required to allow proper stack traversal. 2786 void MacroAssembler::set_last_Java_frame(Register java_thread, 2787 Register last_java_sp, 2788 Register last_java_fp, 2789 address last_java_pc) { 2790 vzeroupper(); 2791 // determine java_thread register 2792 if (!java_thread->is_valid()) { 2793 java_thread = rdi; 2794 get_thread(java_thread); 2795 } 2796 // determine last_java_sp register 2797 if (!last_java_sp->is_valid()) { 2798 last_java_sp = rsp; 2799 } 2800 2801 // last_java_fp is optional 2802 2803 if (last_java_fp->is_valid()) { 2804 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 2805 } 2806 2807 // last_java_pc is optional 2808 2809 if (last_java_pc != NULL) { 2810 lea(Address(java_thread, 2811 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), 2812 InternalAddress(last_java_pc)); 2813 2814 } 2815 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 2816 } 2817 2818 void MacroAssembler::shlptr(Register dst, int imm8) { 2819 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 2820 } 2821 2822 void MacroAssembler::shrptr(Register dst, int imm8) { 2823 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 2824 } 2825 2826 void MacroAssembler::sign_extend_byte(Register reg) { 2827 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 2828 movsbl(reg, reg); // movsxb 2829 } else { 2830 shll(reg, 24); 2831 sarl(reg, 24); 2832 } 2833 } 2834 2835 void MacroAssembler::sign_extend_short(Register reg) { 2836 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 2837 movswl(reg, reg); // movsxw 2838 } else { 2839 shll(reg, 16); 2840 sarl(reg, 16); 2841 } 2842 } 2843 2844 void MacroAssembler::testl(Register dst, AddressLiteral src) { 2845 assert(reachable(src), "Address should be reachable"); 2846 testl(dst, as_Address(src)); 2847 } 2848 2849 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 2850 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 2851 Assembler::pcmpeqb(dst, src); 2852 } 2853 2854 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 2855 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 2856 Assembler::pcmpeqw(dst, src); 2857 } 2858 2859 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 2860 assert((dst->encoding() < 16),"XMM register should be 0-15"); 2861 Assembler::pcmpestri(dst, src, imm8); 2862 } 2863 2864 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 2865 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15"); 2866 Assembler::pcmpestri(dst, src, imm8); 2867 } 2868 2869 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 2870 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 2871 Assembler::pmovzxbw(dst, src); 2872 } 2873 2874 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) { 2875 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 2876 Assembler::pmovzxbw(dst, src); 2877 } 2878 2879 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) { 2880 assert((src->encoding() < 16),"XMM register should be 0-15"); 2881 Assembler::pmovmskb(dst, src); 2882 } 2883 2884 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) { 2885 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15"); 2886 Assembler::ptest(dst, src); 2887 } 2888 2889 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { 2890 if (reachable(src)) { 2891 Assembler::sqrtsd(dst, as_Address(src)); 2892 } else { 2893 lea(rscratch1, src); 2894 Assembler::sqrtsd(dst, Address(rscratch1, 0)); 2895 } 2896 } 2897 2898 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { 2899 if (reachable(src)) { 2900 Assembler::sqrtss(dst, as_Address(src)); 2901 } else { 2902 lea(rscratch1, src); 2903 Assembler::sqrtss(dst, Address(rscratch1, 0)); 2904 } 2905 } 2906 2907 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { 2908 if (reachable(src)) { 2909 Assembler::subsd(dst, as_Address(src)); 2910 } else { 2911 lea(rscratch1, src); 2912 Assembler::subsd(dst, Address(rscratch1, 0)); 2913 } 2914 } 2915 2916 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg) { 2917 if (reachable(src)) { 2918 Assembler::roundsd(dst, as_Address(src), rmode); 2919 } else { 2920 lea(scratch_reg, src); 2921 Assembler::roundsd(dst, Address(scratch_reg, 0), rmode); 2922 } 2923 } 2924 2925 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { 2926 if (reachable(src)) { 2927 Assembler::subss(dst, as_Address(src)); 2928 } else { 2929 lea(rscratch1, src); 2930 Assembler::subss(dst, Address(rscratch1, 0)); 2931 } 2932 } 2933 2934 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { 2935 if (reachable(src)) { 2936 Assembler::ucomisd(dst, as_Address(src)); 2937 } else { 2938 lea(rscratch1, src); 2939 Assembler::ucomisd(dst, Address(rscratch1, 0)); 2940 } 2941 } 2942 2943 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { 2944 if (reachable(src)) { 2945 Assembler::ucomiss(dst, as_Address(src)); 2946 } else { 2947 lea(rscratch1, src); 2948 Assembler::ucomiss(dst, Address(rscratch1, 0)); 2949 } 2950 } 2951 2952 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) { 2953 // Used in sign-bit flipping with aligned address. 2954 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 2955 if (reachable(src)) { 2956 Assembler::xorpd(dst, as_Address(src)); 2957 } else { 2958 lea(scratch_reg, src); 2959 Assembler::xorpd(dst, Address(scratch_reg, 0)); 2960 } 2961 } 2962 2963 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) { 2964 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 2965 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 2966 } 2967 else { 2968 Assembler::xorpd(dst, src); 2969 } 2970 } 2971 2972 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) { 2973 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 2974 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 2975 } else { 2976 Assembler::xorps(dst, src); 2977 } 2978 } 2979 2980 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg) { 2981 // Used in sign-bit flipping with aligned address. 2982 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 2983 if (reachable(src)) { 2984 Assembler::xorps(dst, as_Address(src)); 2985 } else { 2986 lea(scratch_reg, src); 2987 Assembler::xorps(dst, Address(scratch_reg, 0)); 2988 } 2989 } 2990 2991 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { 2992 // Used in sign-bit flipping with aligned address. 2993 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); 2994 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); 2995 if (reachable(src)) { 2996 Assembler::pshufb(dst, as_Address(src)); 2997 } else { 2998 lea(rscratch1, src); 2999 Assembler::pshufb(dst, Address(rscratch1, 0)); 3000 } 3001 } 3002 3003 // AVX 3-operands instructions 3004 3005 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3006 if (reachable(src)) { 3007 vaddsd(dst, nds, as_Address(src)); 3008 } else { 3009 lea(rscratch1, src); 3010 vaddsd(dst, nds, Address(rscratch1, 0)); 3011 } 3012 } 3013 3014 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3015 if (reachable(src)) { 3016 vaddss(dst, nds, as_Address(src)); 3017 } else { 3018 lea(rscratch1, src); 3019 vaddss(dst, nds, Address(rscratch1, 0)); 3020 } 3021 } 3022 3023 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 3024 assert(UseAVX > 0, "requires some form of AVX"); 3025 if (reachable(src)) { 3026 Assembler::vpaddd(dst, nds, as_Address(src), vector_len); 3027 } else { 3028 lea(rscratch, src); 3029 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len); 3030 } 3031 } 3032 3033 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 3034 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15"); 3035 vandps(dst, nds, negate_field, vector_len); 3036 } 3037 3038 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 3039 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15"); 3040 vandpd(dst, nds, negate_field, vector_len); 3041 } 3042 3043 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3044 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3045 Assembler::vpaddb(dst, nds, src, vector_len); 3046 } 3047 3048 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3049 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3050 Assembler::vpaddb(dst, nds, src, vector_len); 3051 } 3052 3053 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3054 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3055 Assembler::vpaddw(dst, nds, src, vector_len); 3056 } 3057 3058 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3059 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3060 Assembler::vpaddw(dst, nds, src, vector_len); 3061 } 3062 3063 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3064 if (reachable(src)) { 3065 Assembler::vpand(dst, nds, as_Address(src), vector_len); 3066 } else { 3067 lea(scratch_reg, src); 3068 Assembler::vpand(dst, nds, Address(scratch_reg, 0), vector_len); 3069 } 3070 } 3071 3072 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) { 3073 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3074 Assembler::vpbroadcastw(dst, src, vector_len); 3075 } 3076 3077 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3078 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3079 Assembler::vpcmpeqb(dst, nds, src, vector_len); 3080 } 3081 3082 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3083 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3084 Assembler::vpcmpeqw(dst, nds, src, vector_len); 3085 } 3086 3087 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, 3088 AddressLiteral src, int vector_len, Register scratch_reg) { 3089 if (reachable(src)) { 3090 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len); 3091 } else { 3092 lea(scratch_reg, src); 3093 Assembler::evpcmpeqd(kdst, mask, nds, Address(scratch_reg, 0), vector_len); 3094 } 3095 } 3096 3097 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, 3098 int comparison, int vector_len, Register scratch_reg) { 3099 if (reachable(src)) { 3100 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, vector_len); 3101 } else { 3102 lea(scratch_reg, src); 3103 Assembler::evpcmpd(kdst, mask, nds, Address(scratch_reg, 0), comparison, vector_len); 3104 } 3105 } 3106 3107 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, 3108 int comparison, int vector_len, Register scratch_reg) { 3109 if (reachable(src)) { 3110 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, vector_len); 3111 } else { 3112 lea(scratch_reg, src); 3113 Assembler::evpcmpq(kdst, mask, nds, Address(scratch_reg, 0), comparison, vector_len); 3114 } 3115 } 3116 3117 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, 3118 int comparison, int vector_len, Register scratch_reg) { 3119 if (reachable(src)) { 3120 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, vector_len); 3121 } else { 3122 lea(scratch_reg, src); 3123 Assembler::evpcmpb(kdst, mask, nds, Address(scratch_reg, 0), comparison, vector_len); 3124 } 3125 } 3126 3127 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, 3128 int comparison, int vector_len, Register scratch_reg) { 3129 if (reachable(src)) { 3130 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, vector_len); 3131 } else { 3132 lea(scratch_reg, src); 3133 Assembler::evpcmpw(kdst, mask, nds, Address(scratch_reg, 0), comparison, vector_len); 3134 } 3135 } 3136 3137 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) { 3138 if (width == Assembler::Q) { 3139 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len); 3140 } else { 3141 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len); 3142 } 3143 } 3144 3145 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, ComparisonPredicate cond, Width width, int vector_len, Register scratch_reg) { 3146 int eq_cond_enc = 0x29; 3147 int gt_cond_enc = 0x37; 3148 if (width != Assembler::Q) { 3149 eq_cond_enc = 0x74 + width; 3150 gt_cond_enc = 0x64 + width; 3151 } 3152 switch (cond) { 3153 case eq: 3154 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len); 3155 break; 3156 case neq: 3157 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len); 3158 vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg); 3159 break; 3160 case le: 3161 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len); 3162 vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg); 3163 break; 3164 case nlt: 3165 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len); 3166 vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg); 3167 break; 3168 case lt: 3169 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len); 3170 break; 3171 case nle: 3172 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len); 3173 break; 3174 default: 3175 assert(false, "Should not reach here"); 3176 } 3177 } 3178 3179 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 3180 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3181 Assembler::vpmovzxbw(dst, src, vector_len); 3182 } 3183 3184 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) { 3185 assert((src->encoding() < 16),"XMM register should be 0-15"); 3186 Assembler::vpmovmskb(dst, src); 3187 } 3188 3189 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3190 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3191 Assembler::vpmullw(dst, nds, src, vector_len); 3192 } 3193 3194 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3195 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3196 Assembler::vpmullw(dst, nds, src, vector_len); 3197 } 3198 3199 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3200 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3201 Assembler::vpsubb(dst, nds, src, vector_len); 3202 } 3203 3204 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3205 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3206 Assembler::vpsubb(dst, nds, src, vector_len); 3207 } 3208 3209 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3210 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3211 Assembler::vpsubw(dst, nds, src, vector_len); 3212 } 3213 3214 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3215 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3216 Assembler::vpsubw(dst, nds, src, vector_len); 3217 } 3218 3219 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 3220 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3221 Assembler::vpsraw(dst, nds, shift, vector_len); 3222 } 3223 3224 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 3225 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3226 Assembler::vpsraw(dst, nds, shift, vector_len); 3227 } 3228 3229 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 3230 assert(UseAVX > 2,""); 3231 if (!VM_Version::supports_avx512vl() && vector_len < 2) { 3232 vector_len = 2; 3233 } 3234 Assembler::evpsraq(dst, nds, shift, vector_len); 3235 } 3236 3237 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 3238 assert(UseAVX > 2,""); 3239 if (!VM_Version::supports_avx512vl() && vector_len < 2) { 3240 vector_len = 2; 3241 } 3242 Assembler::evpsraq(dst, nds, shift, vector_len); 3243 } 3244 3245 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 3246 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3247 Assembler::vpsrlw(dst, nds, shift, vector_len); 3248 } 3249 3250 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 3251 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3252 Assembler::vpsrlw(dst, nds, shift, vector_len); 3253 } 3254 3255 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 3256 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3257 Assembler::vpsllw(dst, nds, shift, vector_len); 3258 } 3259 3260 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 3261 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3262 Assembler::vpsllw(dst, nds, shift, vector_len); 3263 } 3264 3265 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) { 3266 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15"); 3267 Assembler::vptest(dst, src); 3268 } 3269 3270 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) { 3271 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3272 Assembler::punpcklbw(dst, src); 3273 } 3274 3275 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) { 3276 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 3277 Assembler::pshufd(dst, src, mode); 3278 } 3279 3280 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 3281 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3282 Assembler::pshuflw(dst, src, mode); 3283 } 3284 3285 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3286 if (reachable(src)) { 3287 vandpd(dst, nds, as_Address(src), vector_len); 3288 } else { 3289 lea(scratch_reg, src); 3290 vandpd(dst, nds, Address(scratch_reg, 0), vector_len); 3291 } 3292 } 3293 3294 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3295 if (reachable(src)) { 3296 vandps(dst, nds, as_Address(src), vector_len); 3297 } else { 3298 lea(scratch_reg, src); 3299 vandps(dst, nds, Address(scratch_reg, 0), vector_len); 3300 } 3301 } 3302 3303 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, 3304 bool merge, int vector_len, Register scratch_reg) { 3305 if (reachable(src)) { 3306 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len); 3307 } else { 3308 lea(scratch_reg, src); 3309 Assembler::evpord(dst, mask, nds, Address(scratch_reg, 0), merge, vector_len); 3310 } 3311 } 3312 3313 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3314 if (reachable(src)) { 3315 vdivsd(dst, nds, as_Address(src)); 3316 } else { 3317 lea(rscratch1, src); 3318 vdivsd(dst, nds, Address(rscratch1, 0)); 3319 } 3320 } 3321 3322 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3323 if (reachable(src)) { 3324 vdivss(dst, nds, as_Address(src)); 3325 } else { 3326 lea(rscratch1, src); 3327 vdivss(dst, nds, Address(rscratch1, 0)); 3328 } 3329 } 3330 3331 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3332 if (reachable(src)) { 3333 vmulsd(dst, nds, as_Address(src)); 3334 } else { 3335 lea(rscratch1, src); 3336 vmulsd(dst, nds, Address(rscratch1, 0)); 3337 } 3338 } 3339 3340 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3341 if (reachable(src)) { 3342 vmulss(dst, nds, as_Address(src)); 3343 } else { 3344 lea(rscratch1, src); 3345 vmulss(dst, nds, Address(rscratch1, 0)); 3346 } 3347 } 3348 3349 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3350 if (reachable(src)) { 3351 vsubsd(dst, nds, as_Address(src)); 3352 } else { 3353 lea(rscratch1, src); 3354 vsubsd(dst, nds, Address(rscratch1, 0)); 3355 } 3356 } 3357 3358 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3359 if (reachable(src)) { 3360 vsubss(dst, nds, as_Address(src)); 3361 } else { 3362 lea(rscratch1, src); 3363 vsubss(dst, nds, Address(rscratch1, 0)); 3364 } 3365 } 3366 3367 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3368 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15"); 3369 vxorps(dst, nds, src, Assembler::AVX_128bit); 3370 } 3371 3372 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3373 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15"); 3374 vxorpd(dst, nds, src, Assembler::AVX_128bit); 3375 } 3376 3377 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3378 if (reachable(src)) { 3379 vxorpd(dst, nds, as_Address(src), vector_len); 3380 } else { 3381 lea(scratch_reg, src); 3382 vxorpd(dst, nds, Address(scratch_reg, 0), vector_len); 3383 } 3384 } 3385 3386 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3387 if (reachable(src)) { 3388 vxorps(dst, nds, as_Address(src), vector_len); 3389 } else { 3390 lea(scratch_reg, src); 3391 vxorps(dst, nds, Address(scratch_reg, 0), vector_len); 3392 } 3393 } 3394 3395 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3396 if (UseAVX > 1 || (vector_len < 1)) { 3397 if (reachable(src)) { 3398 Assembler::vpxor(dst, nds, as_Address(src), vector_len); 3399 } else { 3400 lea(scratch_reg, src); 3401 Assembler::vpxor(dst, nds, Address(scratch_reg, 0), vector_len); 3402 } 3403 } 3404 else { 3405 MacroAssembler::vxorpd(dst, nds, src, vector_len, scratch_reg); 3406 } 3407 } 3408 3409 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3410 if (reachable(src)) { 3411 Assembler::vpermd(dst, nds, as_Address(src), vector_len); 3412 } else { 3413 lea(scratch_reg, src); 3414 Assembler::vpermd(dst, nds, Address(scratch_reg, 0), vector_len); 3415 } 3416 } 3417 3418 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) { 3419 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask); 3420 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code 3421 // The inverted mask is sign-extended 3422 andptr(possibly_jweak, inverted_jweak_mask); 3423 } 3424 3425 void MacroAssembler::resolve_jobject(Register value, 3426 Register thread, 3427 Register tmp) { 3428 assert_different_registers(value, thread, tmp); 3429 Label done, not_weak; 3430 testptr(value, value); 3431 jcc(Assembler::zero, done); // Use NULL as-is. 3432 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag. 3433 jcc(Assembler::zero, not_weak); 3434 // Resolve jweak. 3435 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, 3436 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread); 3437 verify_oop(value); 3438 jmp(done); 3439 bind(not_weak); 3440 // Resolve (untagged) jobject. 3441 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread); 3442 verify_oop(value); 3443 bind(done); 3444 } 3445 3446 void MacroAssembler::subptr(Register dst, int32_t imm32) { 3447 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 3448 } 3449 3450 // Force generation of a 4 byte immediate value even if it fits into 8bit 3451 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { 3452 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); 3453 } 3454 3455 void MacroAssembler::subptr(Register dst, Register src) { 3456 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 3457 } 3458 3459 // C++ bool manipulation 3460 void MacroAssembler::testbool(Register dst) { 3461 if(sizeof(bool) == 1) 3462 testb(dst, 0xff); 3463 else if(sizeof(bool) == 2) { 3464 // testw implementation needed for two byte bools 3465 ShouldNotReachHere(); 3466 } else if(sizeof(bool) == 4) 3467 testl(dst, dst); 3468 else 3469 // unsupported 3470 ShouldNotReachHere(); 3471 } 3472 3473 void MacroAssembler::testptr(Register dst, Register src) { 3474 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 3475 } 3476 3477 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 3478 void MacroAssembler::tlab_allocate(Register thread, Register obj, 3479 Register var_size_in_bytes, 3480 int con_size_in_bytes, 3481 Register t1, 3482 Register t2, 3483 Label& slow_case) { 3484 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 3485 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case); 3486 } 3487 3488 // Defines obj, preserves var_size_in_bytes 3489 void MacroAssembler::eden_allocate(Register thread, Register obj, 3490 Register var_size_in_bytes, 3491 int con_size_in_bytes, 3492 Register t1, 3493 Label& slow_case) { 3494 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 3495 bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case); 3496 } 3497 3498 // Preserves the contents of address, destroys the contents length_in_bytes and temp. 3499 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) { 3500 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different"); 3501 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord"); 3502 Label done; 3503 3504 testptr(length_in_bytes, length_in_bytes); 3505 jcc(Assembler::zero, done); 3506 3507 // initialize topmost word, divide index by 2, check if odd and test if zero 3508 // note: for the remaining code to work, index must be a multiple of BytesPerWord 3509 #ifdef ASSERT 3510 { 3511 Label L; 3512 testptr(length_in_bytes, BytesPerWord - 1); 3513 jcc(Assembler::zero, L); 3514 stop("length must be a multiple of BytesPerWord"); 3515 bind(L); 3516 } 3517 #endif 3518 Register index = length_in_bytes; 3519 xorptr(temp, temp); // use _zero reg to clear memory (shorter code) 3520 if (UseIncDec) { 3521 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set 3522 } else { 3523 shrptr(index, 2); // use 2 instructions to avoid partial flag stall 3524 shrptr(index, 1); 3525 } 3526 #ifndef _LP64 3527 // index could have not been a multiple of 8 (i.e., bit 2 was set) 3528 { 3529 Label even; 3530 // note: if index was a multiple of 8, then it cannot 3531 // be 0 now otherwise it must have been 0 before 3532 // => if it is even, we don't need to check for 0 again 3533 jcc(Assembler::carryClear, even); 3534 // clear topmost word (no jump would be needed if conditional assignment worked here) 3535 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp); 3536 // index could be 0 now, must check again 3537 jcc(Assembler::zero, done); 3538 bind(even); 3539 } 3540 #endif // !_LP64 3541 // initialize remaining object fields: index is a multiple of 2 now 3542 { 3543 Label loop; 3544 bind(loop); 3545 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp); 3546 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);) 3547 decrement(index); 3548 jcc(Assembler::notZero, loop); 3549 } 3550 3551 bind(done); 3552 } 3553 3554 // Look up the method for a megamorphic invokeinterface call. 3555 // The target method is determined by <intf_klass, itable_index>. 3556 // The receiver klass is in recv_klass. 3557 // On success, the result will be in method_result, and execution falls through. 3558 // On failure, execution transfers to the given label. 3559 void MacroAssembler::lookup_interface_method(Register recv_klass, 3560 Register intf_klass, 3561 RegisterOrConstant itable_index, 3562 Register method_result, 3563 Register scan_temp, 3564 Label& L_no_such_interface, 3565 bool return_method) { 3566 assert_different_registers(recv_klass, intf_klass, scan_temp); 3567 assert_different_registers(method_result, intf_klass, scan_temp); 3568 assert(recv_klass != method_result || !return_method, 3569 "recv_klass can be destroyed when method isn't needed"); 3570 3571 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 3572 "caller must use same register for non-constant itable index as for method"); 3573 3574 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 3575 int vtable_base = in_bytes(Klass::vtable_start_offset()); 3576 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 3577 int scan_step = itableOffsetEntry::size() * wordSize; 3578 int vte_size = vtableEntry::size_in_bytes(); 3579 Address::ScaleFactor times_vte_scale = Address::times_ptr; 3580 assert(vte_size == wordSize, "else adjust times_vte_scale"); 3581 3582 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 3583 3584 // %%% Could store the aligned, prescaled offset in the klassoop. 3585 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 3586 3587 if (return_method) { 3588 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 3589 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 3590 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 3591 } 3592 3593 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 3594 // if (scan->interface() == intf) { 3595 // result = (klass + scan->offset() + itable_index); 3596 // } 3597 // } 3598 Label search, found_method; 3599 3600 for (int peel = 1; peel >= 0; peel--) { 3601 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 3602 cmpptr(intf_klass, method_result); 3603 3604 if (peel) { 3605 jccb(Assembler::equal, found_method); 3606 } else { 3607 jccb(Assembler::notEqual, search); 3608 // (invert the test to fall through to found_method...) 3609 } 3610 3611 if (!peel) break; 3612 3613 bind(search); 3614 3615 // Check that the previous entry is non-null. A null entry means that 3616 // the receiver class doesn't implement the interface, and wasn't the 3617 // same as when the caller was compiled. 3618 testptr(method_result, method_result); 3619 jcc(Assembler::zero, L_no_such_interface); 3620 addptr(scan_temp, scan_step); 3621 } 3622 3623 bind(found_method); 3624 3625 if (return_method) { 3626 // Got a hit. 3627 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 3628 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 3629 } 3630 } 3631 3632 3633 // virtual method calling 3634 void MacroAssembler::lookup_virtual_method(Register recv_klass, 3635 RegisterOrConstant vtable_index, 3636 Register method_result) { 3637 const int base = in_bytes(Klass::vtable_start_offset()); 3638 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); 3639 Address vtable_entry_addr(recv_klass, 3640 vtable_index, Address::times_ptr, 3641 base + vtableEntry::method_offset_in_bytes()); 3642 movptr(method_result, vtable_entry_addr); 3643 } 3644 3645 3646 void MacroAssembler::check_klass_subtype(Register sub_klass, 3647 Register super_klass, 3648 Register temp_reg, 3649 Label& L_success) { 3650 Label L_failure; 3651 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 3652 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 3653 bind(L_failure); 3654 } 3655 3656 3657 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 3658 Register super_klass, 3659 Register temp_reg, 3660 Label* L_success, 3661 Label* L_failure, 3662 Label* L_slow_path, 3663 RegisterOrConstant super_check_offset) { 3664 assert_different_registers(sub_klass, super_klass, temp_reg); 3665 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 3666 if (super_check_offset.is_register()) { 3667 assert_different_registers(sub_klass, super_klass, 3668 super_check_offset.as_register()); 3669 } else if (must_load_sco) { 3670 assert(temp_reg != noreg, "supply either a temp or a register offset"); 3671 } 3672 3673 Label L_fallthrough; 3674 int label_nulls = 0; 3675 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 3676 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 3677 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 3678 assert(label_nulls <= 1, "at most one NULL in the batch"); 3679 3680 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 3681 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 3682 Address super_check_offset_addr(super_klass, sco_offset); 3683 3684 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 3685 // range of a jccb. If this routine grows larger, reconsider at 3686 // least some of these. 3687 #define local_jcc(assembler_cond, label) \ 3688 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 3689 else jcc( assembler_cond, label) /*omit semi*/ 3690 3691 // Hacked jmp, which may only be used just before L_fallthrough. 3692 #define final_jmp(label) \ 3693 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 3694 else jmp(label) /*omit semi*/ 3695 3696 // If the pointers are equal, we are done (e.g., String[] elements). 3697 // This self-check enables sharing of secondary supertype arrays among 3698 // non-primary types such as array-of-interface. Otherwise, each such 3699 // type would need its own customized SSA. 3700 // We move this check to the front of the fast path because many 3701 // type checks are in fact trivially successful in this manner, 3702 // so we get a nicely predicted branch right at the start of the check. 3703 cmpptr(sub_klass, super_klass); 3704 local_jcc(Assembler::equal, *L_success); 3705 3706 // Check the supertype display: 3707 if (must_load_sco) { 3708 // Positive movl does right thing on LP64. 3709 movl(temp_reg, super_check_offset_addr); 3710 super_check_offset = RegisterOrConstant(temp_reg); 3711 } 3712 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 3713 cmpptr(super_klass, super_check_addr); // load displayed supertype 3714 3715 // This check has worked decisively for primary supers. 3716 // Secondary supers are sought in the super_cache ('super_cache_addr'). 3717 // (Secondary supers are interfaces and very deeply nested subtypes.) 3718 // This works in the same check above because of a tricky aliasing 3719 // between the super_cache and the primary super display elements. 3720 // (The 'super_check_addr' can address either, as the case requires.) 3721 // Note that the cache is updated below if it does not help us find 3722 // what we need immediately. 3723 // So if it was a primary super, we can just fail immediately. 3724 // Otherwise, it's the slow path for us (no success at this point). 3725 3726 if (super_check_offset.is_register()) { 3727 local_jcc(Assembler::equal, *L_success); 3728 cmpl(super_check_offset.as_register(), sc_offset); 3729 if (L_failure == &L_fallthrough) { 3730 local_jcc(Assembler::equal, *L_slow_path); 3731 } else { 3732 local_jcc(Assembler::notEqual, *L_failure); 3733 final_jmp(*L_slow_path); 3734 } 3735 } else if (super_check_offset.as_constant() == sc_offset) { 3736 // Need a slow path; fast failure is impossible. 3737 if (L_slow_path == &L_fallthrough) { 3738 local_jcc(Assembler::equal, *L_success); 3739 } else { 3740 local_jcc(Assembler::notEqual, *L_slow_path); 3741 final_jmp(*L_success); 3742 } 3743 } else { 3744 // No slow path; it's a fast decision. 3745 if (L_failure == &L_fallthrough) { 3746 local_jcc(Assembler::equal, *L_success); 3747 } else { 3748 local_jcc(Assembler::notEqual, *L_failure); 3749 final_jmp(*L_success); 3750 } 3751 } 3752 3753 bind(L_fallthrough); 3754 3755 #undef local_jcc 3756 #undef final_jmp 3757 } 3758 3759 3760 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 3761 Register super_klass, 3762 Register temp_reg, 3763 Register temp2_reg, 3764 Label* L_success, 3765 Label* L_failure, 3766 bool set_cond_codes) { 3767 assert_different_registers(sub_klass, super_klass, temp_reg); 3768 if (temp2_reg != noreg) 3769 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 3770 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 3771 3772 Label L_fallthrough; 3773 int label_nulls = 0; 3774 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 3775 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 3776 assert(label_nulls <= 1, "at most one NULL in the batch"); 3777 3778 // a couple of useful fields in sub_klass: 3779 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 3780 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 3781 Address secondary_supers_addr(sub_klass, ss_offset); 3782 Address super_cache_addr( sub_klass, sc_offset); 3783 3784 // Do a linear scan of the secondary super-klass chain. 3785 // This code is rarely used, so simplicity is a virtue here. 3786 // The repne_scan instruction uses fixed registers, which we must spill. 3787 // Don't worry too much about pre-existing connections with the input regs. 3788 3789 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 3790 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 3791 3792 // Get super_klass value into rax (even if it was in rdi or rcx). 3793 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 3794 if (super_klass != rax || UseCompressedOops) { 3795 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 3796 mov(rax, super_klass); 3797 } 3798 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 3799 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 3800 3801 #ifndef PRODUCT 3802 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 3803 ExternalAddress pst_counter_addr((address) pst_counter); 3804 NOT_LP64( incrementl(pst_counter_addr) ); 3805 LP64_ONLY( lea(rcx, pst_counter_addr) ); 3806 LP64_ONLY( incrementl(Address(rcx, 0)) ); 3807 #endif //PRODUCT 3808 3809 // We will consult the secondary-super array. 3810 movptr(rdi, secondary_supers_addr); 3811 // Load the array length. (Positive movl does right thing on LP64.) 3812 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); 3813 // Skip to start of data. 3814 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); 3815 3816 // Scan RCX words at [RDI] for an occurrence of RAX. 3817 // Set NZ/Z based on last compare. 3818 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 3819 // not change flags (only scas instruction which is repeated sets flags). 3820 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 3821 3822 testptr(rax,rax); // Set Z = 0 3823 repne_scan(); 3824 3825 // Unspill the temp. registers: 3826 if (pushed_rdi) pop(rdi); 3827 if (pushed_rcx) pop(rcx); 3828 if (pushed_rax) pop(rax); 3829 3830 if (set_cond_codes) { 3831 // Special hack for the AD files: rdi is guaranteed non-zero. 3832 assert(!pushed_rdi, "rdi must be left non-NULL"); 3833 // Also, the condition codes are properly set Z/NZ on succeed/failure. 3834 } 3835 3836 if (L_failure == &L_fallthrough) 3837 jccb(Assembler::notEqual, *L_failure); 3838 else jcc(Assembler::notEqual, *L_failure); 3839 3840 // Success. Cache the super we found and proceed in triumph. 3841 movptr(super_cache_addr, super_klass); 3842 3843 if (L_success != &L_fallthrough) { 3844 jmp(*L_success); 3845 } 3846 3847 #undef IS_A_TEMP 3848 3849 bind(L_fallthrough); 3850 } 3851 3852 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) { 3853 assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required"); 3854 3855 Label L_fallthrough; 3856 if (L_fast_path == NULL) { 3857 L_fast_path = &L_fallthrough; 3858 } else if (L_slow_path == NULL) { 3859 L_slow_path = &L_fallthrough; 3860 } 3861 3862 // Fast path check: class is fully initialized 3863 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized); 3864 jcc(Assembler::equal, *L_fast_path); 3865 3866 // Fast path check: current thread is initializer thread 3867 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset())); 3868 if (L_slow_path == &L_fallthrough) { 3869 jcc(Assembler::equal, *L_fast_path); 3870 bind(*L_slow_path); 3871 } else if (L_fast_path == &L_fallthrough) { 3872 jcc(Assembler::notEqual, *L_slow_path); 3873 bind(*L_fast_path); 3874 } else { 3875 Unimplemented(); 3876 } 3877 } 3878 3879 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 3880 if (VM_Version::supports_cmov()) { 3881 cmovl(cc, dst, src); 3882 } else { 3883 Label L; 3884 jccb(negate_condition(cc), L); 3885 movl(dst, src); 3886 bind(L); 3887 } 3888 } 3889 3890 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 3891 if (VM_Version::supports_cmov()) { 3892 cmovl(cc, dst, src); 3893 } else { 3894 Label L; 3895 jccb(negate_condition(cc), L); 3896 movl(dst, src); 3897 bind(L); 3898 } 3899 } 3900 3901 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) { 3902 if (!VerifyOops) return; 3903 3904 // Pass register number to verify_oop_subroutine 3905 const char* b = NULL; 3906 { 3907 ResourceMark rm; 3908 stringStream ss; 3909 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line); 3910 b = code_string(ss.as_string()); 3911 } 3912 BLOCK_COMMENT("verify_oop {"); 3913 #ifdef _LP64 3914 push(rscratch1); // save r10, trashed by movptr() 3915 #endif 3916 push(rax); // save rax, 3917 push(reg); // pass register argument 3918 ExternalAddress buffer((address) b); 3919 // avoid using pushptr, as it modifies scratch registers 3920 // and our contract is not to modify anything 3921 movptr(rax, buffer.addr()); 3922 push(rax); 3923 // call indirectly to solve generation ordering problem 3924 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 3925 call(rax); 3926 // Caller pops the arguments (oop, message) and restores rax, r10 3927 BLOCK_COMMENT("} verify_oop"); 3928 } 3929 3930 3931 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 3932 Register tmp, 3933 int offset) { 3934 intptr_t value = *delayed_value_addr; 3935 if (value != 0) 3936 return RegisterOrConstant(value + offset); 3937 3938 // load indirectly to solve generation ordering problem 3939 movptr(tmp, ExternalAddress((address) delayed_value_addr)); 3940 3941 #ifdef ASSERT 3942 { Label L; 3943 testptr(tmp, tmp); 3944 if (WizardMode) { 3945 const char* buf = NULL; 3946 { 3947 ResourceMark rm; 3948 stringStream ss; 3949 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]); 3950 buf = code_string(ss.as_string()); 3951 } 3952 jcc(Assembler::notZero, L); 3953 STOP(buf); 3954 } else { 3955 jccb(Assembler::notZero, L); 3956 hlt(); 3957 } 3958 bind(L); 3959 } 3960 #endif 3961 3962 if (offset != 0) 3963 addptr(tmp, offset); 3964 3965 return RegisterOrConstant(tmp); 3966 } 3967 3968 3969 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 3970 int extra_slot_offset) { 3971 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 3972 int stackElementSize = Interpreter::stackElementSize; 3973 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 3974 #ifdef ASSERT 3975 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 3976 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 3977 #endif 3978 Register scale_reg = noreg; 3979 Address::ScaleFactor scale_factor = Address::no_scale; 3980 if (arg_slot.is_constant()) { 3981 offset += arg_slot.as_constant() * stackElementSize; 3982 } else { 3983 scale_reg = arg_slot.as_register(); 3984 scale_factor = Address::times(stackElementSize); 3985 } 3986 offset += wordSize; // return PC is on stack 3987 return Address(rsp, scale_reg, scale_factor, offset); 3988 } 3989 3990 3991 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) { 3992 if (!VerifyOops) return; 3993 3994 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); 3995 // Pass register number to verify_oop_subroutine 3996 const char* b = NULL; 3997 { 3998 ResourceMark rm; 3999 stringStream ss; 4000 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line); 4001 b = code_string(ss.as_string()); 4002 } 4003 #ifdef _LP64 4004 push(rscratch1); // save r10, trashed by movptr() 4005 #endif 4006 push(rax); // save rax, 4007 // addr may contain rsp so we will have to adjust it based on the push 4008 // we just did (and on 64 bit we do two pushes) 4009 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 4010 // stores rax into addr which is backwards of what was intended. 4011 if (addr.uses(rsp)) { 4012 lea(rax, addr); 4013 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 4014 } else { 4015 pushptr(addr); 4016 } 4017 4018 ExternalAddress buffer((address) b); 4019 // pass msg argument 4020 // avoid using pushptr, as it modifies scratch registers 4021 // and our contract is not to modify anything 4022 movptr(rax, buffer.addr()); 4023 push(rax); 4024 4025 // call indirectly to solve generation ordering problem 4026 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 4027 call(rax); 4028 // Caller pops the arguments (addr, message) and restores rax, r10. 4029 } 4030 4031 void MacroAssembler::verify_tlab() { 4032 #ifdef ASSERT 4033 if (UseTLAB && VerifyOops) { 4034 Label next, ok; 4035 Register t1 = rsi; 4036 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 4037 4038 push(t1); 4039 NOT_LP64(push(thread_reg)); 4040 NOT_LP64(get_thread(thread_reg)); 4041 4042 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 4043 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 4044 jcc(Assembler::aboveEqual, next); 4045 STOP("assert(top >= start)"); 4046 should_not_reach_here(); 4047 4048 bind(next); 4049 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 4050 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 4051 jcc(Assembler::aboveEqual, ok); 4052 STOP("assert(top <= end)"); 4053 should_not_reach_here(); 4054 4055 bind(ok); 4056 NOT_LP64(pop(thread_reg)); 4057 pop(t1); 4058 } 4059 #endif 4060 } 4061 4062 class ControlWord { 4063 public: 4064 int32_t _value; 4065 4066 int rounding_control() const { return (_value >> 10) & 3 ; } 4067 int precision_control() const { return (_value >> 8) & 3 ; } 4068 bool precision() const { return ((_value >> 5) & 1) != 0; } 4069 bool underflow() const { return ((_value >> 4) & 1) != 0; } 4070 bool overflow() const { return ((_value >> 3) & 1) != 0; } 4071 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 4072 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 4073 bool invalid() const { return ((_value >> 0) & 1) != 0; } 4074 4075 void print() const { 4076 // rounding control 4077 const char* rc; 4078 switch (rounding_control()) { 4079 case 0: rc = "round near"; break; 4080 case 1: rc = "round down"; break; 4081 case 2: rc = "round up "; break; 4082 case 3: rc = "chop "; break; 4083 }; 4084 // precision control 4085 const char* pc; 4086 switch (precision_control()) { 4087 case 0: pc = "24 bits "; break; 4088 case 1: pc = "reserved"; break; 4089 case 2: pc = "53 bits "; break; 4090 case 3: pc = "64 bits "; break; 4091 }; 4092 // flags 4093 char f[9]; 4094 f[0] = ' '; 4095 f[1] = ' '; 4096 f[2] = (precision ()) ? 'P' : 'p'; 4097 f[3] = (underflow ()) ? 'U' : 'u'; 4098 f[4] = (overflow ()) ? 'O' : 'o'; 4099 f[5] = (zero_divide ()) ? 'Z' : 'z'; 4100 f[6] = (denormalized()) ? 'D' : 'd'; 4101 f[7] = (invalid ()) ? 'I' : 'i'; 4102 f[8] = '\x0'; 4103 // output 4104 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 4105 } 4106 4107 }; 4108 4109 class StatusWord { 4110 public: 4111 int32_t _value; 4112 4113 bool busy() const { return ((_value >> 15) & 1) != 0; } 4114 bool C3() const { return ((_value >> 14) & 1) != 0; } 4115 bool C2() const { return ((_value >> 10) & 1) != 0; } 4116 bool C1() const { return ((_value >> 9) & 1) != 0; } 4117 bool C0() const { return ((_value >> 8) & 1) != 0; } 4118 int top() const { return (_value >> 11) & 7 ; } 4119 bool error_status() const { return ((_value >> 7) & 1) != 0; } 4120 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 4121 bool precision() const { return ((_value >> 5) & 1) != 0; } 4122 bool underflow() const { return ((_value >> 4) & 1) != 0; } 4123 bool overflow() const { return ((_value >> 3) & 1) != 0; } 4124 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 4125 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 4126 bool invalid() const { return ((_value >> 0) & 1) != 0; } 4127 4128 void print() const { 4129 // condition codes 4130 char c[5]; 4131 c[0] = (C3()) ? '3' : '-'; 4132 c[1] = (C2()) ? '2' : '-'; 4133 c[2] = (C1()) ? '1' : '-'; 4134 c[3] = (C0()) ? '0' : '-'; 4135 c[4] = '\x0'; 4136 // flags 4137 char f[9]; 4138 f[0] = (error_status()) ? 'E' : '-'; 4139 f[1] = (stack_fault ()) ? 'S' : '-'; 4140 f[2] = (precision ()) ? 'P' : '-'; 4141 f[3] = (underflow ()) ? 'U' : '-'; 4142 f[4] = (overflow ()) ? 'O' : '-'; 4143 f[5] = (zero_divide ()) ? 'Z' : '-'; 4144 f[6] = (denormalized()) ? 'D' : '-'; 4145 f[7] = (invalid ()) ? 'I' : '-'; 4146 f[8] = '\x0'; 4147 // output 4148 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 4149 } 4150 4151 }; 4152 4153 class TagWord { 4154 public: 4155 int32_t _value; 4156 4157 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 4158 4159 void print() const { 4160 printf("%04x", _value & 0xFFFF); 4161 } 4162 4163 }; 4164 4165 class FPU_Register { 4166 public: 4167 int32_t _m0; 4168 int32_t _m1; 4169 int16_t _ex; 4170 4171 bool is_indefinite() const { 4172 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 4173 } 4174 4175 void print() const { 4176 char sign = (_ex < 0) ? '-' : '+'; 4177 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 4178 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 4179 }; 4180 4181 }; 4182 4183 class FPU_State { 4184 public: 4185 enum { 4186 register_size = 10, 4187 number_of_registers = 8, 4188 register_mask = 7 4189 }; 4190 4191 ControlWord _control_word; 4192 StatusWord _status_word; 4193 TagWord _tag_word; 4194 int32_t _error_offset; 4195 int32_t _error_selector; 4196 int32_t _data_offset; 4197 int32_t _data_selector; 4198 int8_t _register[register_size * number_of_registers]; 4199 4200 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 4201 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 4202 4203 const char* tag_as_string(int tag) const { 4204 switch (tag) { 4205 case 0: return "valid"; 4206 case 1: return "zero"; 4207 case 2: return "special"; 4208 case 3: return "empty"; 4209 } 4210 ShouldNotReachHere(); 4211 return NULL; 4212 } 4213 4214 void print() const { 4215 // print computation registers 4216 { int t = _status_word.top(); 4217 for (int i = 0; i < number_of_registers; i++) { 4218 int j = (i - t) & register_mask; 4219 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 4220 st(j)->print(); 4221 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 4222 } 4223 } 4224 printf("\n"); 4225 // print control registers 4226 printf("ctrl = "); _control_word.print(); printf("\n"); 4227 printf("stat = "); _status_word .print(); printf("\n"); 4228 printf("tags = "); _tag_word .print(); printf("\n"); 4229 } 4230 4231 }; 4232 4233 class Flag_Register { 4234 public: 4235 int32_t _value; 4236 4237 bool overflow() const { return ((_value >> 11) & 1) != 0; } 4238 bool direction() const { return ((_value >> 10) & 1) != 0; } 4239 bool sign() const { return ((_value >> 7) & 1) != 0; } 4240 bool zero() const { return ((_value >> 6) & 1) != 0; } 4241 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 4242 bool parity() const { return ((_value >> 2) & 1) != 0; } 4243 bool carry() const { return ((_value >> 0) & 1) != 0; } 4244 4245 void print() const { 4246 // flags 4247 char f[8]; 4248 f[0] = (overflow ()) ? 'O' : '-'; 4249 f[1] = (direction ()) ? 'D' : '-'; 4250 f[2] = (sign ()) ? 'S' : '-'; 4251 f[3] = (zero ()) ? 'Z' : '-'; 4252 f[4] = (auxiliary_carry()) ? 'A' : '-'; 4253 f[5] = (parity ()) ? 'P' : '-'; 4254 f[6] = (carry ()) ? 'C' : '-'; 4255 f[7] = '\x0'; 4256 // output 4257 printf("%08x flags = %s", _value, f); 4258 } 4259 4260 }; 4261 4262 class IU_Register { 4263 public: 4264 int32_t _value; 4265 4266 void print() const { 4267 printf("%08x %11d", _value, _value); 4268 } 4269 4270 }; 4271 4272 class IU_State { 4273 public: 4274 Flag_Register _eflags; 4275 IU_Register _rdi; 4276 IU_Register _rsi; 4277 IU_Register _rbp; 4278 IU_Register _rsp; 4279 IU_Register _rbx; 4280 IU_Register _rdx; 4281 IU_Register _rcx; 4282 IU_Register _rax; 4283 4284 void print() const { 4285 // computation registers 4286 printf("rax, = "); _rax.print(); printf("\n"); 4287 printf("rbx, = "); _rbx.print(); printf("\n"); 4288 printf("rcx = "); _rcx.print(); printf("\n"); 4289 printf("rdx = "); _rdx.print(); printf("\n"); 4290 printf("rdi = "); _rdi.print(); printf("\n"); 4291 printf("rsi = "); _rsi.print(); printf("\n"); 4292 printf("rbp, = "); _rbp.print(); printf("\n"); 4293 printf("rsp = "); _rsp.print(); printf("\n"); 4294 printf("\n"); 4295 // control registers 4296 printf("flgs = "); _eflags.print(); printf("\n"); 4297 } 4298 }; 4299 4300 4301 class CPU_State { 4302 public: 4303 FPU_State _fpu_state; 4304 IU_State _iu_state; 4305 4306 void print() const { 4307 printf("--------------------------------------------------\n"); 4308 _iu_state .print(); 4309 printf("\n"); 4310 _fpu_state.print(); 4311 printf("--------------------------------------------------\n"); 4312 } 4313 4314 }; 4315 4316 4317 static void _print_CPU_state(CPU_State* state) { 4318 state->print(); 4319 }; 4320 4321 4322 void MacroAssembler::print_CPU_state() { 4323 push_CPU_state(); 4324 push(rsp); // pass CPU state 4325 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 4326 addptr(rsp, wordSize); // discard argument 4327 pop_CPU_state(); 4328 } 4329 4330 4331 #ifndef _LP64 4332 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 4333 static int counter = 0; 4334 FPU_State* fs = &state->_fpu_state; 4335 counter++; 4336 // For leaf calls, only verify that the top few elements remain empty. 4337 // We only need 1 empty at the top for C2 code. 4338 if( stack_depth < 0 ) { 4339 if( fs->tag_for_st(7) != 3 ) { 4340 printf("FPR7 not empty\n"); 4341 state->print(); 4342 assert(false, "error"); 4343 return false; 4344 } 4345 return true; // All other stack states do not matter 4346 } 4347 4348 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, 4349 "bad FPU control word"); 4350 4351 // compute stack depth 4352 int i = 0; 4353 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 4354 int d = i; 4355 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 4356 // verify findings 4357 if (i != FPU_State::number_of_registers) { 4358 // stack not contiguous 4359 printf("%s: stack not contiguous at ST%d\n", s, i); 4360 state->print(); 4361 assert(false, "error"); 4362 return false; 4363 } 4364 // check if computed stack depth corresponds to expected stack depth 4365 if (stack_depth < 0) { 4366 // expected stack depth is -stack_depth or less 4367 if (d > -stack_depth) { 4368 // too many elements on the stack 4369 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 4370 state->print(); 4371 assert(false, "error"); 4372 return false; 4373 } 4374 } else { 4375 // expected stack depth is stack_depth 4376 if (d != stack_depth) { 4377 // wrong stack depth 4378 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 4379 state->print(); 4380 assert(false, "error"); 4381 return false; 4382 } 4383 } 4384 // everything is cool 4385 return true; 4386 } 4387 4388 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 4389 if (!VerifyFPU) return; 4390 push_CPU_state(); 4391 push(rsp); // pass CPU state 4392 ExternalAddress msg((address) s); 4393 // pass message string s 4394 pushptr(msg.addr()); 4395 push(stack_depth); // pass stack depth 4396 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 4397 addptr(rsp, 3 * wordSize); // discard arguments 4398 // check for error 4399 { Label L; 4400 testl(rax, rax); 4401 jcc(Assembler::notZero, L); 4402 int3(); // break if error condition 4403 bind(L); 4404 } 4405 pop_CPU_state(); 4406 } 4407 #endif // _LP64 4408 4409 void MacroAssembler::restore_cpu_control_state_after_jni() { 4410 // Either restore the MXCSR register after returning from the JNI Call 4411 // or verify that it wasn't changed (with -Xcheck:jni flag). 4412 if (VM_Version::supports_sse()) { 4413 if (RestoreMXCSROnJNICalls) { 4414 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std())); 4415 } else if (CheckJNICalls) { 4416 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); 4417 } 4418 } 4419 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. 4420 vzeroupper(); 4421 // Reset k1 to 0xffff. 4422 4423 #ifdef COMPILER2 4424 if (PostLoopMultiversioning && VM_Version::supports_evex()) { 4425 push(rcx); 4426 movl(rcx, 0xffff); 4427 kmovwl(k1, rcx); 4428 pop(rcx); 4429 } 4430 #endif // COMPILER2 4431 4432 #ifndef _LP64 4433 // Either restore the x87 floating pointer control word after returning 4434 // from the JNI call or verify that it wasn't changed. 4435 if (CheckJNICalls) { 4436 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); 4437 } 4438 #endif // _LP64 4439 } 4440 4441 // ((OopHandle)result).resolve(); 4442 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) { 4443 assert_different_registers(result, tmp); 4444 4445 // Only 64 bit platforms support GCs that require a tmp register 4446 // Only IN_HEAP loads require a thread_tmp register 4447 // OopHandle::resolve is an indirection like jobject. 4448 access_load_at(T_OBJECT, IN_NATIVE, 4449 result, Address(result, 0), tmp, /*tmp_thread*/noreg); 4450 } 4451 4452 // ((WeakHandle)result).resolve(); 4453 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) { 4454 assert_different_registers(rresult, rtmp); 4455 Label resolved; 4456 4457 // A null weak handle resolves to null. 4458 cmpptr(rresult, 0); 4459 jcc(Assembler::equal, resolved); 4460 4461 // Only 64 bit platforms support GCs that require a tmp register 4462 // Only IN_HEAP loads require a thread_tmp register 4463 // WeakHandle::resolve is an indirection like jweak. 4464 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, 4465 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg); 4466 bind(resolved); 4467 } 4468 4469 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) { 4470 // get mirror 4471 const int mirror_offset = in_bytes(Klass::java_mirror_offset()); 4472 load_method_holder(mirror, method); 4473 movptr(mirror, Address(mirror, mirror_offset)); 4474 resolve_oop_handle(mirror, tmp); 4475 } 4476 4477 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) { 4478 load_method_holder(rresult, rmethod); 4479 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset())); 4480 } 4481 4482 void MacroAssembler::load_method_holder(Register holder, Register method) { 4483 movptr(holder, Address(method, Method::const_offset())); // ConstMethod* 4484 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool* 4485 movptr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass* 4486 } 4487 4488 void MacroAssembler::load_klass(Register dst, Register src) { 4489 #ifdef _LP64 4490 if (UseCompressedClassPointers) { 4491 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 4492 decode_klass_not_null(dst); 4493 } else 4494 #endif 4495 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 4496 } 4497 4498 void MacroAssembler::load_prototype_header(Register dst, Register src) { 4499 load_klass(dst, src); 4500 movptr(dst, Address(dst, Klass::prototype_header_offset())); 4501 } 4502 4503 void MacroAssembler::store_klass(Register dst, Register src) { 4504 #ifdef _LP64 4505 if (UseCompressedClassPointers) { 4506 encode_klass_not_null(src); 4507 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); 4508 } else 4509 #endif 4510 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 4511 } 4512 4513 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src, 4514 Register tmp1, Register thread_tmp) { 4515 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 4516 decorators = AccessInternal::decorator_fixup(decorators); 4517 bool as_raw = (decorators & AS_RAW) != 0; 4518 if (as_raw) { 4519 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp); 4520 } else { 4521 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp); 4522 } 4523 } 4524 4525 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src, 4526 Register tmp1, Register tmp2) { 4527 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 4528 decorators = AccessInternal::decorator_fixup(decorators); 4529 bool as_raw = (decorators & AS_RAW) != 0; 4530 if (as_raw) { 4531 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2); 4532 } else { 4533 bs->store_at(this, decorators, type, dst, src, tmp1, tmp2); 4534 } 4535 } 4536 4537 void MacroAssembler::resolve(DecoratorSet decorators, Register obj) { 4538 // Use stronger ACCESS_WRITE|ACCESS_READ by default. 4539 if ((decorators & (ACCESS_READ | ACCESS_WRITE)) == 0) { 4540 decorators |= ACCESS_READ | ACCESS_WRITE; 4541 } 4542 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 4543 return bs->resolve(this, decorators, obj); 4544 } 4545 4546 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, 4547 Register thread_tmp, DecoratorSet decorators) { 4548 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp); 4549 } 4550 4551 // Doesn't do verfication, generates fixed size code 4552 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, 4553 Register thread_tmp, DecoratorSet decorators) { 4554 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp); 4555 } 4556 4557 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1, 4558 Register tmp2, DecoratorSet decorators) { 4559 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2); 4560 } 4561 4562 // Used for storing NULLs. 4563 void MacroAssembler::store_heap_oop_null(Address dst) { 4564 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg); 4565 } 4566 4567 #ifdef _LP64 4568 void MacroAssembler::store_klass_gap(Register dst, Register src) { 4569 if (UseCompressedClassPointers) { 4570 // Store to klass gap in destination 4571 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); 4572 } 4573 } 4574 4575 #ifdef ASSERT 4576 void MacroAssembler::verify_heapbase(const char* msg) { 4577 assert (UseCompressedOops, "should be compressed"); 4578 assert (Universe::heap() != NULL, "java heap should be initialized"); 4579 if (CheckCompressedOops) { 4580 Label ok; 4581 push(rscratch1); // cmpptr trashes rscratch1 4582 cmpptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr())); 4583 jcc(Assembler::equal, ok); 4584 STOP(msg); 4585 bind(ok); 4586 pop(rscratch1); 4587 } 4588 } 4589 #endif 4590 4591 // Algorithm must match oop.inline.hpp encode_heap_oop. 4592 void MacroAssembler::encode_heap_oop(Register r) { 4593 #ifdef ASSERT 4594 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 4595 #endif 4596 verify_oop_msg(r, "broken oop in encode_heap_oop"); 4597 if (CompressedOops::base() == NULL) { 4598 if (CompressedOops::shift() != 0) { 4599 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 4600 shrq(r, LogMinObjAlignmentInBytes); 4601 } 4602 return; 4603 } 4604 testq(r, r); 4605 cmovq(Assembler::equal, r, r12_heapbase); 4606 subq(r, r12_heapbase); 4607 shrq(r, LogMinObjAlignmentInBytes); 4608 } 4609 4610 void MacroAssembler::encode_heap_oop_not_null(Register r) { 4611 #ifdef ASSERT 4612 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 4613 if (CheckCompressedOops) { 4614 Label ok; 4615 testq(r, r); 4616 jcc(Assembler::notEqual, ok); 4617 STOP("null oop passed to encode_heap_oop_not_null"); 4618 bind(ok); 4619 } 4620 #endif 4621 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null"); 4622 if (CompressedOops::base() != NULL) { 4623 subq(r, r12_heapbase); 4624 } 4625 if (CompressedOops::shift() != 0) { 4626 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 4627 shrq(r, LogMinObjAlignmentInBytes); 4628 } 4629 } 4630 4631 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 4632 #ifdef ASSERT 4633 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 4634 if (CheckCompressedOops) { 4635 Label ok; 4636 testq(src, src); 4637 jcc(Assembler::notEqual, ok); 4638 STOP("null oop passed to encode_heap_oop_not_null2"); 4639 bind(ok); 4640 } 4641 #endif 4642 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2"); 4643 if (dst != src) { 4644 movq(dst, src); 4645 } 4646 if (CompressedOops::base() != NULL) { 4647 subq(dst, r12_heapbase); 4648 } 4649 if (CompressedOops::shift() != 0) { 4650 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 4651 shrq(dst, LogMinObjAlignmentInBytes); 4652 } 4653 } 4654 4655 void MacroAssembler::decode_heap_oop(Register r) { 4656 #ifdef ASSERT 4657 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 4658 #endif 4659 if (CompressedOops::base() == NULL) { 4660 if (CompressedOops::shift() != 0) { 4661 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 4662 shlq(r, LogMinObjAlignmentInBytes); 4663 } 4664 } else { 4665 Label done; 4666 shlq(r, LogMinObjAlignmentInBytes); 4667 jccb(Assembler::equal, done); 4668 addq(r, r12_heapbase); 4669 bind(done); 4670 } 4671 verify_oop_msg(r, "broken oop in decode_heap_oop"); 4672 } 4673 4674 void MacroAssembler::decode_heap_oop_not_null(Register r) { 4675 // Note: it will change flags 4676 assert (UseCompressedOops, "should only be used for compressed headers"); 4677 assert (Universe::heap() != NULL, "java heap should be initialized"); 4678 // Cannot assert, unverified entry point counts instructions (see .ad file) 4679 // vtableStubs also counts instructions in pd_code_size_limit. 4680 // Also do not verify_oop as this is called by verify_oop. 4681 if (CompressedOops::shift() != 0) { 4682 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 4683 shlq(r, LogMinObjAlignmentInBytes); 4684 if (CompressedOops::base() != NULL) { 4685 addq(r, r12_heapbase); 4686 } 4687 } else { 4688 assert (CompressedOops::base() == NULL, "sanity"); 4689 } 4690 } 4691 4692 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 4693 // Note: it will change flags 4694 assert (UseCompressedOops, "should only be used for compressed headers"); 4695 assert (Universe::heap() != NULL, "java heap should be initialized"); 4696 // Cannot assert, unverified entry point counts instructions (see .ad file) 4697 // vtableStubs also counts instructions in pd_code_size_limit. 4698 // Also do not verify_oop as this is called by verify_oop. 4699 if (CompressedOops::shift() != 0) { 4700 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 4701 if (LogMinObjAlignmentInBytes == Address::times_8) { 4702 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 4703 } else { 4704 if (dst != src) { 4705 movq(dst, src); 4706 } 4707 shlq(dst, LogMinObjAlignmentInBytes); 4708 if (CompressedOops::base() != NULL) { 4709 addq(dst, r12_heapbase); 4710 } 4711 } 4712 } else { 4713 assert (CompressedOops::base() == NULL, "sanity"); 4714 if (dst != src) { 4715 movq(dst, src); 4716 } 4717 } 4718 } 4719 4720 void MacroAssembler::encode_klass_not_null(Register r) { 4721 if (CompressedKlassPointers::base() != NULL) { 4722 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 4723 assert(r != r12_heapbase, "Encoding a klass in r12"); 4724 mov64(r12_heapbase, (int64_t)CompressedKlassPointers::base()); 4725 subq(r, r12_heapbase); 4726 } 4727 if (CompressedKlassPointers::shift() != 0) { 4728 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong"); 4729 shrq(r, LogKlassAlignmentInBytes); 4730 } 4731 if (CompressedKlassPointers::base() != NULL) { 4732 reinit_heapbase(); 4733 } 4734 } 4735 4736 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 4737 if (dst == src) { 4738 encode_klass_not_null(src); 4739 } else { 4740 if (CompressedKlassPointers::base() != NULL) { 4741 mov64(dst, (int64_t)CompressedKlassPointers::base()); 4742 negq(dst); 4743 addq(dst, src); 4744 } else { 4745 movptr(dst, src); 4746 } 4747 if (CompressedKlassPointers::shift() != 0) { 4748 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong"); 4749 shrq(dst, LogKlassAlignmentInBytes); 4750 } 4751 } 4752 } 4753 4754 // Function instr_size_for_decode_klass_not_null() counts the instructions 4755 // generated by decode_klass_not_null(register r) and reinit_heapbase(), 4756 // when (Universe::heap() != NULL). Hence, if the instructions they 4757 // generate change, then this method needs to be updated. 4758 int MacroAssembler::instr_size_for_decode_klass_not_null() { 4759 assert (UseCompressedClassPointers, "only for compressed klass ptrs"); 4760 if (CompressedKlassPointers::base() != NULL) { 4761 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()). 4762 return (CompressedKlassPointers::shift() == 0 ? 20 : 24); 4763 } else { 4764 // longest load decode klass function, mov64, leaq 4765 return 16; 4766 } 4767 } 4768 4769 // !!! If the instructions that get generated here change then function 4770 // instr_size_for_decode_klass_not_null() needs to get updated. 4771 void MacroAssembler::decode_klass_not_null(Register r) { 4772 // Note: it will change flags 4773 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 4774 assert(r != r12_heapbase, "Decoding a klass in r12"); 4775 // Cannot assert, unverified entry point counts instructions (see .ad file) 4776 // vtableStubs also counts instructions in pd_code_size_limit. 4777 // Also do not verify_oop as this is called by verify_oop. 4778 if (CompressedKlassPointers::shift() != 0) { 4779 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong"); 4780 shlq(r, LogKlassAlignmentInBytes); 4781 } 4782 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 4783 if (CompressedKlassPointers::base() != NULL) { 4784 mov64(r12_heapbase, (int64_t)CompressedKlassPointers::base()); 4785 addq(r, r12_heapbase); 4786 reinit_heapbase(); 4787 } 4788 } 4789 4790 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 4791 // Note: it will change flags 4792 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 4793 if (dst == src) { 4794 decode_klass_not_null(dst); 4795 } else { 4796 // Cannot assert, unverified entry point counts instructions (see .ad file) 4797 // vtableStubs also counts instructions in pd_code_size_limit. 4798 // Also do not verify_oop as this is called by verify_oop. 4799 mov64(dst, (int64_t)CompressedKlassPointers::base()); 4800 if (CompressedKlassPointers::shift() != 0) { 4801 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong"); 4802 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); 4803 leaq(dst, Address(dst, src, Address::times_8, 0)); 4804 } else { 4805 addq(dst, src); 4806 } 4807 } 4808 } 4809 4810 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 4811 assert (UseCompressedOops, "should only be used for compressed headers"); 4812 assert (Universe::heap() != NULL, "java heap should be initialized"); 4813 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 4814 int oop_index = oop_recorder()->find_index(obj); 4815 RelocationHolder rspec = oop_Relocation::spec(oop_index); 4816 mov_narrow_oop(dst, oop_index, rspec); 4817 } 4818 4819 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 4820 assert (UseCompressedOops, "should only be used for compressed headers"); 4821 assert (Universe::heap() != NULL, "java heap should be initialized"); 4822 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 4823 int oop_index = oop_recorder()->find_index(obj); 4824 RelocationHolder rspec = oop_Relocation::spec(oop_index); 4825 mov_narrow_oop(dst, oop_index, rspec); 4826 } 4827 4828 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 4829 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 4830 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 4831 int klass_index = oop_recorder()->find_index(k); 4832 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 4833 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec); 4834 } 4835 4836 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { 4837 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 4838 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 4839 int klass_index = oop_recorder()->find_index(k); 4840 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 4841 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec); 4842 } 4843 4844 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 4845 assert (UseCompressedOops, "should only be used for compressed headers"); 4846 assert (Universe::heap() != NULL, "java heap should be initialized"); 4847 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 4848 int oop_index = oop_recorder()->find_index(obj); 4849 RelocationHolder rspec = oop_Relocation::spec(oop_index); 4850 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 4851 } 4852 4853 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 4854 assert (UseCompressedOops, "should only be used for compressed headers"); 4855 assert (Universe::heap() != NULL, "java heap should be initialized"); 4856 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 4857 int oop_index = oop_recorder()->find_index(obj); 4858 RelocationHolder rspec = oop_Relocation::spec(oop_index); 4859 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 4860 } 4861 4862 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { 4863 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 4864 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 4865 int klass_index = oop_recorder()->find_index(k); 4866 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 4867 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec); 4868 } 4869 4870 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { 4871 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 4872 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 4873 int klass_index = oop_recorder()->find_index(k); 4874 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 4875 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec); 4876 } 4877 4878 void MacroAssembler::reinit_heapbase() { 4879 if (UseCompressedOops || UseCompressedClassPointers) { 4880 if (Universe::heap() != NULL) { 4881 if (CompressedOops::base() == NULL) { 4882 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); 4883 } else { 4884 mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base()); 4885 } 4886 } else { 4887 movptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr())); 4888 } 4889 } 4890 } 4891 4892 #endif // _LP64 4893 4894 // C2 compiled method's prolog code. 4895 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub) { 4896 4897 // WARNING: Initial instruction MUST be 5 bytes or longer so that 4898 // NativeJump::patch_verified_entry will be able to patch out the entry 4899 // code safely. The push to verify stack depth is ok at 5 bytes, 4900 // the frame allocation can be either 3 or 6 bytes. So if we don't do 4901 // stack bang then we must use the 6 byte frame allocation even if 4902 // we have no frame. :-( 4903 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect"); 4904 4905 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 4906 // Remove word for return addr 4907 framesize -= wordSize; 4908 stack_bang_size -= wordSize; 4909 4910 // Calls to C2R adapters often do not accept exceptional returns. 4911 // We require that their callers must bang for them. But be careful, because 4912 // some VM calls (such as call site linkage) can use several kilobytes of 4913 // stack. But the stack safety zone should account for that. 4914 // See bugs 4446381, 4468289, 4497237. 4915 if (stack_bang_size > 0) { 4916 generate_stack_overflow_check(stack_bang_size); 4917 4918 // We always push rbp, so that on return to interpreter rbp, will be 4919 // restored correctly and we can correct the stack. 4920 push(rbp); 4921 // Save caller's stack pointer into RBP if the frame pointer is preserved. 4922 if (PreserveFramePointer) { 4923 mov(rbp, rsp); 4924 } 4925 // Remove word for ebp 4926 framesize -= wordSize; 4927 4928 // Create frame 4929 if (framesize) { 4930 subptr(rsp, framesize); 4931 } 4932 } else { 4933 // Create frame (force generation of a 4 byte immediate value) 4934 subptr_imm32(rsp, framesize); 4935 4936 // Save RBP register now. 4937 framesize -= wordSize; 4938 movptr(Address(rsp, framesize), rbp); 4939 // Save caller's stack pointer into RBP if the frame pointer is preserved. 4940 if (PreserveFramePointer) { 4941 movptr(rbp, rsp); 4942 if (framesize > 0) { 4943 addptr(rbp, framesize); 4944 } 4945 } 4946 } 4947 4948 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth 4949 framesize -= wordSize; 4950 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); 4951 } 4952 4953 #ifndef _LP64 4954 // If method sets FPU control word do it now 4955 if (fp_mode_24b) { 4956 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 4957 } 4958 if (UseSSE >= 2 && VerifyFPU) { 4959 verify_FPU(0, "FPU stack must be clean on entry"); 4960 } 4961 #endif 4962 4963 #ifdef ASSERT 4964 if (VerifyStackAtCalls) { 4965 Label L; 4966 push(rax); 4967 mov(rax, rsp); 4968 andptr(rax, StackAlignmentInBytes-1); 4969 cmpptr(rax, StackAlignmentInBytes-wordSize); 4970 pop(rax); 4971 jcc(Assembler::equal, L); 4972 STOP("Stack is not properly aligned!"); 4973 bind(L); 4974 } 4975 #endif 4976 4977 if (!is_stub) { 4978 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 4979 bs->nmethod_entry_barrier(this); 4980 } 4981 } 4982 4983 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers 4984 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp) { 4985 // cnt - number of qwords (8-byte words). 4986 // base - start address, qword aligned. 4987 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end; 4988 if (UseAVX >= 2) { 4989 vpxor(xtmp, xtmp, xtmp, AVX_256bit); 4990 } else { 4991 pxor(xtmp, xtmp); 4992 } 4993 jmp(L_zero_64_bytes); 4994 4995 BIND(L_loop); 4996 if (UseAVX >= 2) { 4997 vmovdqu(Address(base, 0), xtmp); 4998 vmovdqu(Address(base, 32), xtmp); 4999 } else { 5000 movdqu(Address(base, 0), xtmp); 5001 movdqu(Address(base, 16), xtmp); 5002 movdqu(Address(base, 32), xtmp); 5003 movdqu(Address(base, 48), xtmp); 5004 } 5005 addptr(base, 64); 5006 5007 BIND(L_zero_64_bytes); 5008 subptr(cnt, 8); 5009 jccb(Assembler::greaterEqual, L_loop); 5010 addptr(cnt, 4); 5011 jccb(Assembler::less, L_tail); 5012 // Copy trailing 32 bytes 5013 if (UseAVX >= 2) { 5014 vmovdqu(Address(base, 0), xtmp); 5015 } else { 5016 movdqu(Address(base, 0), xtmp); 5017 movdqu(Address(base, 16), xtmp); 5018 } 5019 addptr(base, 32); 5020 subptr(cnt, 4); 5021 5022 BIND(L_tail); 5023 addptr(cnt, 4); 5024 jccb(Assembler::lessEqual, L_end); 5025 decrement(cnt); 5026 5027 BIND(L_sloop); 5028 movq(Address(base, 0), xtmp); 5029 addptr(base, 8); 5030 decrement(cnt); 5031 jccb(Assembler::greaterEqual, L_sloop); 5032 BIND(L_end); 5033 } 5034 5035 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp, bool is_large) { 5036 // cnt - number of qwords (8-byte words). 5037 // base - start address, qword aligned. 5038 // is_large - if optimizers know cnt is larger than InitArrayShortSize 5039 assert(base==rdi, "base register must be edi for rep stos"); 5040 assert(tmp==rax, "tmp register must be eax for rep stos"); 5041 assert(cnt==rcx, "cnt register must be ecx for rep stos"); 5042 assert(InitArrayShortSize % BytesPerLong == 0, 5043 "InitArrayShortSize should be the multiple of BytesPerLong"); 5044 5045 Label DONE; 5046 5047 if (!is_large || !UseXMMForObjInit) { 5048 xorptr(tmp, tmp); 5049 } 5050 5051 if (!is_large) { 5052 Label LOOP, LONG; 5053 cmpptr(cnt, InitArrayShortSize/BytesPerLong); 5054 jccb(Assembler::greater, LONG); 5055 5056 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 5057 5058 decrement(cnt); 5059 jccb(Assembler::negative, DONE); // Zero length 5060 5061 // Use individual pointer-sized stores for small counts: 5062 BIND(LOOP); 5063 movptr(Address(base, cnt, Address::times_ptr), tmp); 5064 decrement(cnt); 5065 jccb(Assembler::greaterEqual, LOOP); 5066 jmpb(DONE); 5067 5068 BIND(LONG); 5069 } 5070 5071 // Use longer rep-prefixed ops for non-small counts: 5072 if (UseFastStosb) { 5073 shlptr(cnt, 3); // convert to number of bytes 5074 rep_stosb(); 5075 } else if (UseXMMForObjInit) { 5076 movptr(tmp, base); 5077 xmm_clear_mem(tmp, cnt, xtmp); 5078 } else { 5079 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 5080 rep_stos(); 5081 } 5082 5083 BIND(DONE); 5084 } 5085 5086 void MacroAssembler::generate_fill(BasicType t, bool aligned, 5087 Register to, Register value, Register count, 5088 Register rtmp, XMMRegister xtmp) { 5089 ShortBranchVerifier sbv(this); 5090 assert_different_registers(to, value, count, rtmp); 5091 Label L_exit; 5092 Label L_fill_2_bytes, L_fill_4_bytes; 5093 5094 int shift = -1; 5095 switch (t) { 5096 case T_BYTE: 5097 shift = 2; 5098 break; 5099 case T_SHORT: 5100 shift = 1; 5101 break; 5102 case T_INT: 5103 shift = 0; 5104 break; 5105 default: ShouldNotReachHere(); 5106 } 5107 5108 if (t == T_BYTE) { 5109 andl(value, 0xff); 5110 movl(rtmp, value); 5111 shll(rtmp, 8); 5112 orl(value, rtmp); 5113 } 5114 if (t == T_SHORT) { 5115 andl(value, 0xffff); 5116 } 5117 if (t == T_BYTE || t == T_SHORT) { 5118 movl(rtmp, value); 5119 shll(rtmp, 16); 5120 orl(value, rtmp); 5121 } 5122 5123 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 5124 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 5125 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 5126 Label L_skip_align2; 5127 // align source address at 4 bytes address boundary 5128 if (t == T_BYTE) { 5129 Label L_skip_align1; 5130 // One byte misalignment happens only for byte arrays 5131 testptr(to, 1); 5132 jccb(Assembler::zero, L_skip_align1); 5133 movb(Address(to, 0), value); 5134 increment(to); 5135 decrement(count); 5136 BIND(L_skip_align1); 5137 } 5138 // Two bytes misalignment happens only for byte and short (char) arrays 5139 testptr(to, 2); 5140 jccb(Assembler::zero, L_skip_align2); 5141 movw(Address(to, 0), value); 5142 addptr(to, 2); 5143 subl(count, 1<<(shift-1)); 5144 BIND(L_skip_align2); 5145 } 5146 if (UseSSE < 2) { 5147 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 5148 // Fill 32-byte chunks 5149 subl(count, 8 << shift); 5150 jcc(Assembler::less, L_check_fill_8_bytes); 5151 align(16); 5152 5153 BIND(L_fill_32_bytes_loop); 5154 5155 for (int i = 0; i < 32; i += 4) { 5156 movl(Address(to, i), value); 5157 } 5158 5159 addptr(to, 32); 5160 subl(count, 8 << shift); 5161 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 5162 BIND(L_check_fill_8_bytes); 5163 addl(count, 8 << shift); 5164 jccb(Assembler::zero, L_exit); 5165 jmpb(L_fill_8_bytes); 5166 5167 // 5168 // length is too short, just fill qwords 5169 // 5170 BIND(L_fill_8_bytes_loop); 5171 movl(Address(to, 0), value); 5172 movl(Address(to, 4), value); 5173 addptr(to, 8); 5174 BIND(L_fill_8_bytes); 5175 subl(count, 1 << (shift + 1)); 5176 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 5177 // fall through to fill 4 bytes 5178 } else { 5179 Label L_fill_32_bytes; 5180 if (!UseUnalignedLoadStores) { 5181 // align to 8 bytes, we know we are 4 byte aligned to start 5182 testptr(to, 4); 5183 jccb(Assembler::zero, L_fill_32_bytes); 5184 movl(Address(to, 0), value); 5185 addptr(to, 4); 5186 subl(count, 1<<shift); 5187 } 5188 BIND(L_fill_32_bytes); 5189 { 5190 assert( UseSSE >= 2, "supported cpu only" ); 5191 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 5192 movdl(xtmp, value); 5193 if (UseAVX >= 2 && UseUnalignedLoadStores) { 5194 Label L_check_fill_32_bytes; 5195 if (UseAVX > 2) { 5196 // Fill 64-byte chunks 5197 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2; 5198 5199 // If number of bytes to fill < AVX3Threshold, perform fill using AVX2 5200 cmpl(count, AVX3Threshold); 5201 jccb(Assembler::below, L_check_fill_64_bytes_avx2); 5202 5203 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); 5204 5205 subl(count, 16 << shift); 5206 jccb(Assembler::less, L_check_fill_32_bytes); 5207 align(16); 5208 5209 BIND(L_fill_64_bytes_loop_avx3); 5210 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit); 5211 addptr(to, 64); 5212 subl(count, 16 << shift); 5213 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3); 5214 jmpb(L_check_fill_32_bytes); 5215 5216 BIND(L_check_fill_64_bytes_avx2); 5217 } 5218 // Fill 64-byte chunks 5219 Label L_fill_64_bytes_loop; 5220 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit); 5221 5222 subl(count, 16 << shift); 5223 jcc(Assembler::less, L_check_fill_32_bytes); 5224 align(16); 5225 5226 BIND(L_fill_64_bytes_loop); 5227 vmovdqu(Address(to, 0), xtmp); 5228 vmovdqu(Address(to, 32), xtmp); 5229 addptr(to, 64); 5230 subl(count, 16 << shift); 5231 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 5232 5233 BIND(L_check_fill_32_bytes); 5234 addl(count, 8 << shift); 5235 jccb(Assembler::less, L_check_fill_8_bytes); 5236 vmovdqu(Address(to, 0), xtmp); 5237 addptr(to, 32); 5238 subl(count, 8 << shift); 5239 5240 BIND(L_check_fill_8_bytes); 5241 // clean upper bits of YMM registers 5242 movdl(xtmp, value); 5243 pshufd(xtmp, xtmp, 0); 5244 } else { 5245 // Fill 32-byte chunks 5246 pshufd(xtmp, xtmp, 0); 5247 5248 subl(count, 8 << shift); 5249 jcc(Assembler::less, L_check_fill_8_bytes); 5250 align(16); 5251 5252 BIND(L_fill_32_bytes_loop); 5253 5254 if (UseUnalignedLoadStores) { 5255 movdqu(Address(to, 0), xtmp); 5256 movdqu(Address(to, 16), xtmp); 5257 } else { 5258 movq(Address(to, 0), xtmp); 5259 movq(Address(to, 8), xtmp); 5260 movq(Address(to, 16), xtmp); 5261 movq(Address(to, 24), xtmp); 5262 } 5263 5264 addptr(to, 32); 5265 subl(count, 8 << shift); 5266 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 5267 5268 BIND(L_check_fill_8_bytes); 5269 } 5270 addl(count, 8 << shift); 5271 jccb(Assembler::zero, L_exit); 5272 jmpb(L_fill_8_bytes); 5273 5274 // 5275 // length is too short, just fill qwords 5276 // 5277 BIND(L_fill_8_bytes_loop); 5278 movq(Address(to, 0), xtmp); 5279 addptr(to, 8); 5280 BIND(L_fill_8_bytes); 5281 subl(count, 1 << (shift + 1)); 5282 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 5283 } 5284 } 5285 // fill trailing 4 bytes 5286 BIND(L_fill_4_bytes); 5287 testl(count, 1<<shift); 5288 jccb(Assembler::zero, L_fill_2_bytes); 5289 movl(Address(to, 0), value); 5290 if (t == T_BYTE || t == T_SHORT) { 5291 Label L_fill_byte; 5292 addptr(to, 4); 5293 BIND(L_fill_2_bytes); 5294 // fill trailing 2 bytes 5295 testl(count, 1<<(shift-1)); 5296 jccb(Assembler::zero, L_fill_byte); 5297 movw(Address(to, 0), value); 5298 if (t == T_BYTE) { 5299 addptr(to, 2); 5300 BIND(L_fill_byte); 5301 // fill trailing byte 5302 testl(count, 1); 5303 jccb(Assembler::zero, L_exit); 5304 movb(Address(to, 0), value); 5305 } else { 5306 BIND(L_fill_byte); 5307 } 5308 } else { 5309 BIND(L_fill_2_bytes); 5310 } 5311 BIND(L_exit); 5312 } 5313 5314 // encode char[] to byte[] in ISO_8859_1 5315 //@HotSpotIntrinsicCandidate 5316 //private static int implEncodeISOArray(byte[] sa, int sp, 5317 //byte[] da, int dp, int len) { 5318 // int i = 0; 5319 // for (; i < len; i++) { 5320 // char c = StringUTF16.getChar(sa, sp++); 5321 // if (c > '\u00FF') 5322 // break; 5323 // da[dp++] = (byte)c; 5324 // } 5325 // return i; 5326 //} 5327 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, 5328 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 5329 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 5330 Register tmp5, Register result) { 5331 5332 // rsi: src 5333 // rdi: dst 5334 // rdx: len 5335 // rcx: tmp5 5336 // rax: result 5337 ShortBranchVerifier sbv(this); 5338 assert_different_registers(src, dst, len, tmp5, result); 5339 Label L_done, L_copy_1_char, L_copy_1_char_exit; 5340 5341 // set result 5342 xorl(result, result); 5343 // check for zero length 5344 testl(len, len); 5345 jcc(Assembler::zero, L_done); 5346 5347 movl(result, len); 5348 5349 // Setup pointers 5350 lea(src, Address(src, len, Address::times_2)); // char[] 5351 lea(dst, Address(dst, len, Address::times_1)); // byte[] 5352 negptr(len); 5353 5354 if (UseSSE42Intrinsics || UseAVX >= 2) { 5355 Label L_copy_8_chars, L_copy_8_chars_exit; 5356 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; 5357 5358 if (UseAVX >= 2) { 5359 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; 5360 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 5361 movdl(tmp1Reg, tmp5); 5362 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit); 5363 jmp(L_chars_32_check); 5364 5365 bind(L_copy_32_chars); 5366 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); 5367 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); 5368 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 5369 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 5370 jccb(Assembler::notZero, L_copy_32_chars_exit); 5371 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 5372 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1); 5373 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); 5374 5375 bind(L_chars_32_check); 5376 addptr(len, 32); 5377 jcc(Assembler::lessEqual, L_copy_32_chars); 5378 5379 bind(L_copy_32_chars_exit); 5380 subptr(len, 16); 5381 jccb(Assembler::greater, L_copy_16_chars_exit); 5382 5383 } else if (UseSSE42Intrinsics) { 5384 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 5385 movdl(tmp1Reg, tmp5); 5386 pshufd(tmp1Reg, tmp1Reg, 0); 5387 jmpb(L_chars_16_check); 5388 } 5389 5390 bind(L_copy_16_chars); 5391 if (UseAVX >= 2) { 5392 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); 5393 vptest(tmp2Reg, tmp1Reg); 5394 jcc(Assembler::notZero, L_copy_16_chars_exit); 5395 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1); 5396 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1); 5397 } else { 5398 if (UseAVX > 0) { 5399 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 5400 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 5401 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0); 5402 } else { 5403 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 5404 por(tmp2Reg, tmp3Reg); 5405 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 5406 por(tmp2Reg, tmp4Reg); 5407 } 5408 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 5409 jccb(Assembler::notZero, L_copy_16_chars_exit); 5410 packuswb(tmp3Reg, tmp4Reg); 5411 } 5412 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); 5413 5414 bind(L_chars_16_check); 5415 addptr(len, 16); 5416 jcc(Assembler::lessEqual, L_copy_16_chars); 5417 5418 bind(L_copy_16_chars_exit); 5419 if (UseAVX >= 2) { 5420 // clean upper bits of YMM registers 5421 vpxor(tmp2Reg, tmp2Reg); 5422 vpxor(tmp3Reg, tmp3Reg); 5423 vpxor(tmp4Reg, tmp4Reg); 5424 movdl(tmp1Reg, tmp5); 5425 pshufd(tmp1Reg, tmp1Reg, 0); 5426 } 5427 subptr(len, 8); 5428 jccb(Assembler::greater, L_copy_8_chars_exit); 5429 5430 bind(L_copy_8_chars); 5431 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); 5432 ptest(tmp3Reg, tmp1Reg); 5433 jccb(Assembler::notZero, L_copy_8_chars_exit); 5434 packuswb(tmp3Reg, tmp1Reg); 5435 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); 5436 addptr(len, 8); 5437 jccb(Assembler::lessEqual, L_copy_8_chars); 5438 5439 bind(L_copy_8_chars_exit); 5440 subptr(len, 8); 5441 jccb(Assembler::zero, L_done); 5442 } 5443 5444 bind(L_copy_1_char); 5445 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); 5446 testl(tmp5, 0xff00); // check if Unicode char 5447 jccb(Assembler::notZero, L_copy_1_char_exit); 5448 movb(Address(dst, len, Address::times_1, 0), tmp5); 5449 addptr(len, 1); 5450 jccb(Assembler::less, L_copy_1_char); 5451 5452 bind(L_copy_1_char_exit); 5453 addptr(result, len); // len is negative count of not processed elements 5454 5455 bind(L_done); 5456 } 5457 5458 #ifdef _LP64 5459 /** 5460 * Helper for multiply_to_len(). 5461 */ 5462 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 5463 addq(dest_lo, src1); 5464 adcq(dest_hi, 0); 5465 addq(dest_lo, src2); 5466 adcq(dest_hi, 0); 5467 } 5468 5469 /** 5470 * Multiply 64 bit by 64 bit first loop. 5471 */ 5472 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 5473 Register y, Register y_idx, Register z, 5474 Register carry, Register product, 5475 Register idx, Register kdx) { 5476 // 5477 // jlong carry, x[], y[], z[]; 5478 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 5479 // huge_128 product = y[idx] * x[xstart] + carry; 5480 // z[kdx] = (jlong)product; 5481 // carry = (jlong)(product >>> 64); 5482 // } 5483 // z[xstart] = carry; 5484 // 5485 5486 Label L_first_loop, L_first_loop_exit; 5487 Label L_one_x, L_one_y, L_multiply; 5488 5489 decrementl(xstart); 5490 jcc(Assembler::negative, L_one_x); 5491 5492 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 5493 rorq(x_xstart, 32); // convert big-endian to little-endian 5494 5495 bind(L_first_loop); 5496 decrementl(idx); 5497 jcc(Assembler::negative, L_first_loop_exit); 5498 decrementl(idx); 5499 jcc(Assembler::negative, L_one_y); 5500 movq(y_idx, Address(y, idx, Address::times_4, 0)); 5501 rorq(y_idx, 32); // convert big-endian to little-endian 5502 bind(L_multiply); 5503 movq(product, x_xstart); 5504 mulq(y_idx); // product(rax) * y_idx -> rdx:rax 5505 addq(product, carry); 5506 adcq(rdx, 0); 5507 subl(kdx, 2); 5508 movl(Address(z, kdx, Address::times_4, 4), product); 5509 shrq(product, 32); 5510 movl(Address(z, kdx, Address::times_4, 0), product); 5511 movq(carry, rdx); 5512 jmp(L_first_loop); 5513 5514 bind(L_one_y); 5515 movl(y_idx, Address(y, 0)); 5516 jmp(L_multiply); 5517 5518 bind(L_one_x); 5519 movl(x_xstart, Address(x, 0)); 5520 jmp(L_first_loop); 5521 5522 bind(L_first_loop_exit); 5523 } 5524 5525 /** 5526 * Multiply 64 bit by 64 bit and add 128 bit. 5527 */ 5528 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z, 5529 Register yz_idx, Register idx, 5530 Register carry, Register product, int offset) { 5531 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry; 5532 // z[kdx] = (jlong)product; 5533 5534 movq(yz_idx, Address(y, idx, Address::times_4, offset)); 5535 rorq(yz_idx, 32); // convert big-endian to little-endian 5536 movq(product, x_xstart); 5537 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 5538 movq(yz_idx, Address(z, idx, Address::times_4, offset)); 5539 rorq(yz_idx, 32); // convert big-endian to little-endian 5540 5541 add2_with_carry(rdx, product, carry, yz_idx); 5542 5543 movl(Address(z, idx, Address::times_4, offset+4), product); 5544 shrq(product, 32); 5545 movl(Address(z, idx, Address::times_4, offset), product); 5546 5547 } 5548 5549 /** 5550 * Multiply 128 bit by 128 bit. Unrolled inner loop. 5551 */ 5552 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 5553 Register yz_idx, Register idx, Register jdx, 5554 Register carry, Register product, 5555 Register carry2) { 5556 // jlong carry, x[], y[], z[]; 5557 // int kdx = ystart+1; 5558 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 5559 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry; 5560 // z[kdx+idx+1] = (jlong)product; 5561 // jlong carry2 = (jlong)(product >>> 64); 5562 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2; 5563 // z[kdx+idx] = (jlong)product; 5564 // carry = (jlong)(product >>> 64); 5565 // } 5566 // idx += 2; 5567 // if (idx > 0) { 5568 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry; 5569 // z[kdx+idx] = (jlong)product; 5570 // carry = (jlong)(product >>> 64); 5571 // } 5572 // 5573 5574 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 5575 5576 movl(jdx, idx); 5577 andl(jdx, 0xFFFFFFFC); 5578 shrl(jdx, 2); 5579 5580 bind(L_third_loop); 5581 subl(jdx, 1); 5582 jcc(Assembler::negative, L_third_loop_exit); 5583 subl(idx, 4); 5584 5585 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8); 5586 movq(carry2, rdx); 5587 5588 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0); 5589 movq(carry, rdx); 5590 jmp(L_third_loop); 5591 5592 bind (L_third_loop_exit); 5593 5594 andl (idx, 0x3); 5595 jcc(Assembler::zero, L_post_third_loop_done); 5596 5597 Label L_check_1; 5598 subl(idx, 2); 5599 jcc(Assembler::negative, L_check_1); 5600 5601 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0); 5602 movq(carry, rdx); 5603 5604 bind (L_check_1); 5605 addl (idx, 0x2); 5606 andl (idx, 0x1); 5607 subl(idx, 1); 5608 jcc(Assembler::negative, L_post_third_loop_done); 5609 5610 movl(yz_idx, Address(y, idx, Address::times_4, 0)); 5611 movq(product, x_xstart); 5612 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 5613 movl(yz_idx, Address(z, idx, Address::times_4, 0)); 5614 5615 add2_with_carry(rdx, product, yz_idx, carry); 5616 5617 movl(Address(z, idx, Address::times_4, 0), product); 5618 shrq(product, 32); 5619 5620 shlq(rdx, 32); 5621 orq(product, rdx); 5622 movq(carry, product); 5623 5624 bind(L_post_third_loop_done); 5625 } 5626 5627 /** 5628 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop. 5629 * 5630 */ 5631 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z, 5632 Register carry, Register carry2, 5633 Register idx, Register jdx, 5634 Register yz_idx1, Register yz_idx2, 5635 Register tmp, Register tmp3, Register tmp4) { 5636 assert(UseBMI2Instructions, "should be used only when BMI2 is available"); 5637 5638 // jlong carry, x[], y[], z[]; 5639 // int kdx = ystart+1; 5640 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 5641 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry; 5642 // jlong carry2 = (jlong)(tmp3 >>> 64); 5643 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2; 5644 // carry = (jlong)(tmp4 >>> 64); 5645 // z[kdx+idx+1] = (jlong)tmp3; 5646 // z[kdx+idx] = (jlong)tmp4; 5647 // } 5648 // idx += 2; 5649 // if (idx > 0) { 5650 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry; 5651 // z[kdx+idx] = (jlong)yz_idx1; 5652 // carry = (jlong)(yz_idx1 >>> 64); 5653 // } 5654 // 5655 5656 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 5657 5658 movl(jdx, idx); 5659 andl(jdx, 0xFFFFFFFC); 5660 shrl(jdx, 2); 5661 5662 bind(L_third_loop); 5663 subl(jdx, 1); 5664 jcc(Assembler::negative, L_third_loop_exit); 5665 subl(idx, 4); 5666 5667 movq(yz_idx1, Address(y, idx, Address::times_4, 8)); 5668 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 5669 movq(yz_idx2, Address(y, idx, Address::times_4, 0)); 5670 rorxq(yz_idx2, yz_idx2, 32); 5671 5672 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 5673 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp 5674 5675 movq(yz_idx1, Address(z, idx, Address::times_4, 8)); 5676 rorxq(yz_idx1, yz_idx1, 32); 5677 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 5678 rorxq(yz_idx2, yz_idx2, 32); 5679 5680 if (VM_Version::supports_adx()) { 5681 adcxq(tmp3, carry); 5682 adoxq(tmp3, yz_idx1); 5683 5684 adcxq(tmp4, tmp); 5685 adoxq(tmp4, yz_idx2); 5686 5687 movl(carry, 0); // does not affect flags 5688 adcxq(carry2, carry); 5689 adoxq(carry2, carry); 5690 } else { 5691 add2_with_carry(tmp4, tmp3, carry, yz_idx1); 5692 add2_with_carry(carry2, tmp4, tmp, yz_idx2); 5693 } 5694 movq(carry, carry2); 5695 5696 movl(Address(z, idx, Address::times_4, 12), tmp3); 5697 shrq(tmp3, 32); 5698 movl(Address(z, idx, Address::times_4, 8), tmp3); 5699 5700 movl(Address(z, idx, Address::times_4, 4), tmp4); 5701 shrq(tmp4, 32); 5702 movl(Address(z, idx, Address::times_4, 0), tmp4); 5703 5704 jmp(L_third_loop); 5705 5706 bind (L_third_loop_exit); 5707 5708 andl (idx, 0x3); 5709 jcc(Assembler::zero, L_post_third_loop_done); 5710 5711 Label L_check_1; 5712 subl(idx, 2); 5713 jcc(Assembler::negative, L_check_1); 5714 5715 movq(yz_idx1, Address(y, idx, Address::times_4, 0)); 5716 rorxq(yz_idx1, yz_idx1, 32); 5717 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 5718 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 5719 rorxq(yz_idx2, yz_idx2, 32); 5720 5721 add2_with_carry(tmp4, tmp3, carry, yz_idx2); 5722 5723 movl(Address(z, idx, Address::times_4, 4), tmp3); 5724 shrq(tmp3, 32); 5725 movl(Address(z, idx, Address::times_4, 0), tmp3); 5726 movq(carry, tmp4); 5727 5728 bind (L_check_1); 5729 addl (idx, 0x2); 5730 andl (idx, 0x1); 5731 subl(idx, 1); 5732 jcc(Assembler::negative, L_post_third_loop_done); 5733 movl(tmp4, Address(y, idx, Address::times_4, 0)); 5734 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3 5735 movl(tmp4, Address(z, idx, Address::times_4, 0)); 5736 5737 add2_with_carry(carry2, tmp3, tmp4, carry); 5738 5739 movl(Address(z, idx, Address::times_4, 0), tmp3); 5740 shrq(tmp3, 32); 5741 5742 shlq(carry2, 32); 5743 orq(tmp3, carry2); 5744 movq(carry, tmp3); 5745 5746 bind(L_post_third_loop_done); 5747 } 5748 5749 /** 5750 * Code for BigInteger::multiplyToLen() instrinsic. 5751 * 5752 * rdi: x 5753 * rax: xlen 5754 * rsi: y 5755 * rcx: ylen 5756 * r8: z 5757 * r11: zlen 5758 * r12: tmp1 5759 * r13: tmp2 5760 * r14: tmp3 5761 * r15: tmp4 5762 * rbx: tmp5 5763 * 5764 */ 5765 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 5766 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) { 5767 ShortBranchVerifier sbv(this); 5768 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx); 5769 5770 push(tmp1); 5771 push(tmp2); 5772 push(tmp3); 5773 push(tmp4); 5774 push(tmp5); 5775 5776 push(xlen); 5777 push(zlen); 5778 5779 const Register idx = tmp1; 5780 const Register kdx = tmp2; 5781 const Register xstart = tmp3; 5782 5783 const Register y_idx = tmp4; 5784 const Register carry = tmp5; 5785 const Register product = xlen; 5786 const Register x_xstart = zlen; // reuse register 5787 5788 // First Loop. 5789 // 5790 // final static long LONG_MASK = 0xffffffffL; 5791 // int xstart = xlen - 1; 5792 // int ystart = ylen - 1; 5793 // long carry = 0; 5794 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 5795 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 5796 // z[kdx] = (int)product; 5797 // carry = product >>> 32; 5798 // } 5799 // z[xstart] = (int)carry; 5800 // 5801 5802 movl(idx, ylen); // idx = ylen; 5803 movl(kdx, zlen); // kdx = xlen+ylen; 5804 xorq(carry, carry); // carry = 0; 5805 5806 Label L_done; 5807 5808 movl(xstart, xlen); 5809 decrementl(xstart); 5810 jcc(Assembler::negative, L_done); 5811 5812 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 5813 5814 Label L_second_loop; 5815 testl(kdx, kdx); 5816 jcc(Assembler::zero, L_second_loop); 5817 5818 Label L_carry; 5819 subl(kdx, 1); 5820 jcc(Assembler::zero, L_carry); 5821 5822 movl(Address(z, kdx, Address::times_4, 0), carry); 5823 shrq(carry, 32); 5824 subl(kdx, 1); 5825 5826 bind(L_carry); 5827 movl(Address(z, kdx, Address::times_4, 0), carry); 5828 5829 // Second and third (nested) loops. 5830 // 5831 // for (int i = xstart-1; i >= 0; i--) { // Second loop 5832 // carry = 0; 5833 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 5834 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 5835 // (z[k] & LONG_MASK) + carry; 5836 // z[k] = (int)product; 5837 // carry = product >>> 32; 5838 // } 5839 // z[i] = (int)carry; 5840 // } 5841 // 5842 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx 5843 5844 const Register jdx = tmp1; 5845 5846 bind(L_second_loop); 5847 xorl(carry, carry); // carry = 0; 5848 movl(jdx, ylen); // j = ystart+1 5849 5850 subl(xstart, 1); // i = xstart-1; 5851 jcc(Assembler::negative, L_done); 5852 5853 push (z); 5854 5855 Label L_last_x; 5856 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j 5857 subl(xstart, 1); // i = xstart-1; 5858 jcc(Assembler::negative, L_last_x); 5859 5860 if (UseBMI2Instructions) { 5861 movq(rdx, Address(x, xstart, Address::times_4, 0)); 5862 rorxq(rdx, rdx, 32); // convert big-endian to little-endian 5863 } else { 5864 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 5865 rorq(x_xstart, 32); // convert big-endian to little-endian 5866 } 5867 5868 Label L_third_loop_prologue; 5869 bind(L_third_loop_prologue); 5870 5871 push (x); 5872 push (xstart); 5873 push (ylen); 5874 5875 5876 if (UseBMI2Instructions) { 5877 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4); 5878 } else { // !UseBMI2Instructions 5879 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x); 5880 } 5881 5882 pop(ylen); 5883 pop(xlen); 5884 pop(x); 5885 pop(z); 5886 5887 movl(tmp3, xlen); 5888 addl(tmp3, 1); 5889 movl(Address(z, tmp3, Address::times_4, 0), carry); 5890 subl(tmp3, 1); 5891 jccb(Assembler::negative, L_done); 5892 5893 shrq(carry, 32); 5894 movl(Address(z, tmp3, Address::times_4, 0), carry); 5895 jmp(L_second_loop); 5896 5897 // Next infrequent code is moved outside loops. 5898 bind(L_last_x); 5899 if (UseBMI2Instructions) { 5900 movl(rdx, Address(x, 0)); 5901 } else { 5902 movl(x_xstart, Address(x, 0)); 5903 } 5904 jmp(L_third_loop_prologue); 5905 5906 bind(L_done); 5907 5908 pop(zlen); 5909 pop(xlen); 5910 5911 pop(tmp5); 5912 pop(tmp4); 5913 pop(tmp3); 5914 pop(tmp2); 5915 pop(tmp1); 5916 } 5917 5918 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale, 5919 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){ 5920 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled."); 5921 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP; 5922 Label VECTOR8_TAIL, VECTOR4_TAIL; 5923 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL; 5924 Label SAME_TILL_END, DONE; 5925 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL; 5926 5927 //scale is in rcx in both Win64 and Unix 5928 ShortBranchVerifier sbv(this); 5929 5930 shlq(length); 5931 xorq(result, result); 5932 5933 if ((AVX3Threshold == 0) && (UseAVX > 2) && 5934 VM_Version::supports_avx512vlbw()) { 5935 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL; 5936 5937 cmpq(length, 64); 5938 jcc(Assembler::less, VECTOR32_TAIL); 5939 5940 movq(tmp1, length); 5941 andq(tmp1, 0x3F); // tail count 5942 andq(length, ~(0x3F)); //vector count 5943 5944 bind(VECTOR64_LOOP); 5945 // AVX512 code to compare 64 byte vectors. 5946 evmovdqub(rymm0, Address(obja, result), false, Assembler::AVX_512bit); 5947 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit); 5948 kortestql(k7, k7); 5949 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch 5950 addq(result, 64); 5951 subq(length, 64); 5952 jccb(Assembler::notZero, VECTOR64_LOOP); 5953 5954 //bind(VECTOR64_TAIL); 5955 testq(tmp1, tmp1); 5956 jcc(Assembler::zero, SAME_TILL_END); 5957 5958 //bind(VECTOR64_TAIL); 5959 // AVX512 code to compare upto 63 byte vectors. 5960 mov64(tmp2, 0xFFFFFFFFFFFFFFFF); 5961 shlxq(tmp2, tmp2, tmp1); 5962 notq(tmp2); 5963 kmovql(k3, tmp2); 5964 5965 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit); 5966 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit); 5967 5968 ktestql(k7, k3); 5969 jcc(Assembler::below, SAME_TILL_END); // not mismatch 5970 5971 bind(VECTOR64_NOT_EQUAL); 5972 kmovql(tmp1, k7); 5973 notq(tmp1); 5974 tzcntq(tmp1, tmp1); 5975 addq(result, tmp1); 5976 shrq(result); 5977 jmp(DONE); 5978 bind(VECTOR32_TAIL); 5979 } 5980 5981 cmpq(length, 8); 5982 jcc(Assembler::equal, VECTOR8_LOOP); 5983 jcc(Assembler::less, VECTOR4_TAIL); 5984 5985 if (UseAVX >= 2) { 5986 Label VECTOR16_TAIL, VECTOR32_LOOP; 5987 5988 cmpq(length, 16); 5989 jcc(Assembler::equal, VECTOR16_LOOP); 5990 jcc(Assembler::less, VECTOR8_LOOP); 5991 5992 cmpq(length, 32); 5993 jccb(Assembler::less, VECTOR16_TAIL); 5994 5995 subq(length, 32); 5996 bind(VECTOR32_LOOP); 5997 vmovdqu(rymm0, Address(obja, result)); 5998 vmovdqu(rymm1, Address(objb, result)); 5999 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit); 6000 vptest(rymm2, rymm2); 6001 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found 6002 addq(result, 32); 6003 subq(length, 32); 6004 jcc(Assembler::greaterEqual, VECTOR32_LOOP); 6005 addq(length, 32); 6006 jcc(Assembler::equal, SAME_TILL_END); 6007 //falling through if less than 32 bytes left //close the branch here. 6008 6009 bind(VECTOR16_TAIL); 6010 cmpq(length, 16); 6011 jccb(Assembler::less, VECTOR8_TAIL); 6012 bind(VECTOR16_LOOP); 6013 movdqu(rymm0, Address(obja, result)); 6014 movdqu(rymm1, Address(objb, result)); 6015 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit); 6016 ptest(rymm2, rymm2); 6017 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 6018 addq(result, 16); 6019 subq(length, 16); 6020 jcc(Assembler::equal, SAME_TILL_END); 6021 //falling through if less than 16 bytes left 6022 } else {//regular intrinsics 6023 6024 cmpq(length, 16); 6025 jccb(Assembler::less, VECTOR8_TAIL); 6026 6027 subq(length, 16); 6028 bind(VECTOR16_LOOP); 6029 movdqu(rymm0, Address(obja, result)); 6030 movdqu(rymm1, Address(objb, result)); 6031 pxor(rymm0, rymm1); 6032 ptest(rymm0, rymm0); 6033 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 6034 addq(result, 16); 6035 subq(length, 16); 6036 jccb(Assembler::greaterEqual, VECTOR16_LOOP); 6037 addq(length, 16); 6038 jcc(Assembler::equal, SAME_TILL_END); 6039 //falling through if less than 16 bytes left 6040 } 6041 6042 bind(VECTOR8_TAIL); 6043 cmpq(length, 8); 6044 jccb(Assembler::less, VECTOR4_TAIL); 6045 bind(VECTOR8_LOOP); 6046 movq(tmp1, Address(obja, result)); 6047 movq(tmp2, Address(objb, result)); 6048 xorq(tmp1, tmp2); 6049 testq(tmp1, tmp1); 6050 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found 6051 addq(result, 8); 6052 subq(length, 8); 6053 jcc(Assembler::equal, SAME_TILL_END); 6054 //falling through if less than 8 bytes left 6055 6056 bind(VECTOR4_TAIL); 6057 cmpq(length, 4); 6058 jccb(Assembler::less, BYTES_TAIL); 6059 bind(VECTOR4_LOOP); 6060 movl(tmp1, Address(obja, result)); 6061 xorl(tmp1, Address(objb, result)); 6062 testl(tmp1, tmp1); 6063 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found 6064 addq(result, 4); 6065 subq(length, 4); 6066 jcc(Assembler::equal, SAME_TILL_END); 6067 //falling through if less than 4 bytes left 6068 6069 bind(BYTES_TAIL); 6070 bind(BYTES_LOOP); 6071 load_unsigned_byte(tmp1, Address(obja, result)); 6072 load_unsigned_byte(tmp2, Address(objb, result)); 6073 xorl(tmp1, tmp2); 6074 testl(tmp1, tmp1); 6075 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 6076 decq(length); 6077 jcc(Assembler::zero, SAME_TILL_END); 6078 incq(result); 6079 load_unsigned_byte(tmp1, Address(obja, result)); 6080 load_unsigned_byte(tmp2, Address(objb, result)); 6081 xorl(tmp1, tmp2); 6082 testl(tmp1, tmp1); 6083 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 6084 decq(length); 6085 jcc(Assembler::zero, SAME_TILL_END); 6086 incq(result); 6087 load_unsigned_byte(tmp1, Address(obja, result)); 6088 load_unsigned_byte(tmp2, Address(objb, result)); 6089 xorl(tmp1, tmp2); 6090 testl(tmp1, tmp1); 6091 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 6092 jmp(SAME_TILL_END); 6093 6094 if (UseAVX >= 2) { 6095 bind(VECTOR32_NOT_EQUAL); 6096 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit); 6097 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit); 6098 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit); 6099 vpmovmskb(tmp1, rymm0); 6100 bsfq(tmp1, tmp1); 6101 addq(result, tmp1); 6102 shrq(result); 6103 jmp(DONE); 6104 } 6105 6106 bind(VECTOR16_NOT_EQUAL); 6107 if (UseAVX >= 2) { 6108 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit); 6109 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit); 6110 pxor(rymm0, rymm2); 6111 } else { 6112 pcmpeqb(rymm2, rymm2); 6113 pxor(rymm0, rymm1); 6114 pcmpeqb(rymm0, rymm1); 6115 pxor(rymm0, rymm2); 6116 } 6117 pmovmskb(tmp1, rymm0); 6118 bsfq(tmp1, tmp1); 6119 addq(result, tmp1); 6120 shrq(result); 6121 jmpb(DONE); 6122 6123 bind(VECTOR8_NOT_EQUAL); 6124 bind(VECTOR4_NOT_EQUAL); 6125 bsfq(tmp1, tmp1); 6126 shrq(tmp1, 3); 6127 addq(result, tmp1); 6128 bind(BYTES_NOT_EQUAL); 6129 shrq(result); 6130 jmpb(DONE); 6131 6132 bind(SAME_TILL_END); 6133 mov64(result, -1); 6134 6135 bind(DONE); 6136 } 6137 6138 //Helper functions for square_to_len() 6139 6140 /** 6141 * Store the squares of x[], right shifted one bit (divided by 2) into z[] 6142 * Preserves x and z and modifies rest of the registers. 6143 */ 6144 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 6145 // Perform square and right shift by 1 6146 // Handle odd xlen case first, then for even xlen do the following 6147 // jlong carry = 0; 6148 // for (int j=0, i=0; j < xlen; j+=2, i+=4) { 6149 // huge_128 product = x[j:j+1] * x[j:j+1]; 6150 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65); 6151 // z[i+2:i+3] = (jlong)(product >>> 1); 6152 // carry = (jlong)product; 6153 // } 6154 6155 xorq(tmp5, tmp5); // carry 6156 xorq(rdxReg, rdxReg); 6157 xorl(tmp1, tmp1); // index for x 6158 xorl(tmp4, tmp4); // index for z 6159 6160 Label L_first_loop, L_first_loop_exit; 6161 6162 testl(xlen, 1); 6163 jccb(Assembler::zero, L_first_loop); //jump if xlen is even 6164 6165 // Square and right shift by 1 the odd element using 32 bit multiply 6166 movl(raxReg, Address(x, tmp1, Address::times_4, 0)); 6167 imulq(raxReg, raxReg); 6168 shrq(raxReg, 1); 6169 adcq(tmp5, 0); 6170 movq(Address(z, tmp4, Address::times_4, 0), raxReg); 6171 incrementl(tmp1); 6172 addl(tmp4, 2); 6173 6174 // Square and right shift by 1 the rest using 64 bit multiply 6175 bind(L_first_loop); 6176 cmpptr(tmp1, xlen); 6177 jccb(Assembler::equal, L_first_loop_exit); 6178 6179 // Square 6180 movq(raxReg, Address(x, tmp1, Address::times_4, 0)); 6181 rorq(raxReg, 32); // convert big-endian to little-endian 6182 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax 6183 6184 // Right shift by 1 and save carry 6185 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1 6186 rcrq(rdxReg, 1); 6187 rcrq(raxReg, 1); 6188 adcq(tmp5, 0); 6189 6190 // Store result in z 6191 movq(Address(z, tmp4, Address::times_4, 0), rdxReg); 6192 movq(Address(z, tmp4, Address::times_4, 8), raxReg); 6193 6194 // Update indices for x and z 6195 addl(tmp1, 2); 6196 addl(tmp4, 4); 6197 jmp(L_first_loop); 6198 6199 bind(L_first_loop_exit); 6200 } 6201 6202 6203 /** 6204 * Perform the following multiply add operation using BMI2 instructions 6205 * carry:sum = sum + op1*op2 + carry 6206 * op2 should be in rdx 6207 * op2 is preserved, all other registers are modified 6208 */ 6209 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) { 6210 // assert op2 is rdx 6211 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1 6212 addq(sum, carry); 6213 adcq(tmp2, 0); 6214 addq(sum, op1); 6215 adcq(tmp2, 0); 6216 movq(carry, tmp2); 6217 } 6218 6219 /** 6220 * Perform the following multiply add operation: 6221 * carry:sum = sum + op1*op2 + carry 6222 * Preserves op1, op2 and modifies rest of registers 6223 */ 6224 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) { 6225 // rdx:rax = op1 * op2 6226 movq(raxReg, op2); 6227 mulq(op1); 6228 6229 // rdx:rax = sum + carry + rdx:rax 6230 addq(sum, carry); 6231 adcq(rdxReg, 0); 6232 addq(sum, raxReg); 6233 adcq(rdxReg, 0); 6234 6235 // carry:sum = rdx:sum 6236 movq(carry, rdxReg); 6237 } 6238 6239 /** 6240 * Add 64 bit long carry into z[] with carry propogation. 6241 * Preserves z and carry register values and modifies rest of registers. 6242 * 6243 */ 6244 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) { 6245 Label L_fourth_loop, L_fourth_loop_exit; 6246 6247 movl(tmp1, 1); 6248 subl(zlen, 2); 6249 addq(Address(z, zlen, Address::times_4, 0), carry); 6250 6251 bind(L_fourth_loop); 6252 jccb(Assembler::carryClear, L_fourth_loop_exit); 6253 subl(zlen, 2); 6254 jccb(Assembler::negative, L_fourth_loop_exit); 6255 addq(Address(z, zlen, Address::times_4, 0), tmp1); 6256 jmp(L_fourth_loop); 6257 bind(L_fourth_loop_exit); 6258 } 6259 6260 /** 6261 * Shift z[] left by 1 bit. 6262 * Preserves x, len, z and zlen registers and modifies rest of the registers. 6263 * 6264 */ 6265 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) { 6266 6267 Label L_fifth_loop, L_fifth_loop_exit; 6268 6269 // Fifth loop 6270 // Perform primitiveLeftShift(z, zlen, 1) 6271 6272 const Register prev_carry = tmp1; 6273 const Register new_carry = tmp4; 6274 const Register value = tmp2; 6275 const Register zidx = tmp3; 6276 6277 // int zidx, carry; 6278 // long value; 6279 // carry = 0; 6280 // for (zidx = zlen-2; zidx >=0; zidx -= 2) { 6281 // (carry:value) = (z[i] << 1) | carry ; 6282 // z[i] = value; 6283 // } 6284 6285 movl(zidx, zlen); 6286 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register 6287 6288 bind(L_fifth_loop); 6289 decl(zidx); // Use decl to preserve carry flag 6290 decl(zidx); 6291 jccb(Assembler::negative, L_fifth_loop_exit); 6292 6293 if (UseBMI2Instructions) { 6294 movq(value, Address(z, zidx, Address::times_4, 0)); 6295 rclq(value, 1); 6296 rorxq(value, value, 32); 6297 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 6298 } 6299 else { 6300 // clear new_carry 6301 xorl(new_carry, new_carry); 6302 6303 // Shift z[i] by 1, or in previous carry and save new carry 6304 movq(value, Address(z, zidx, Address::times_4, 0)); 6305 shlq(value, 1); 6306 adcl(new_carry, 0); 6307 6308 orq(value, prev_carry); 6309 rorq(value, 0x20); 6310 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 6311 6312 // Set previous carry = new carry 6313 movl(prev_carry, new_carry); 6314 } 6315 jmp(L_fifth_loop); 6316 6317 bind(L_fifth_loop_exit); 6318 } 6319 6320 6321 /** 6322 * Code for BigInteger::squareToLen() intrinsic 6323 * 6324 * rdi: x 6325 * rsi: len 6326 * r8: z 6327 * rcx: zlen 6328 * r12: tmp1 6329 * r13: tmp2 6330 * r14: tmp3 6331 * r15: tmp4 6332 * rbx: tmp5 6333 * 6334 */ 6335 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 6336 6337 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply; 6338 push(tmp1); 6339 push(tmp2); 6340 push(tmp3); 6341 push(tmp4); 6342 push(tmp5); 6343 6344 // First loop 6345 // Store the squares, right shifted one bit (i.e., divided by 2). 6346 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg); 6347 6348 // Add in off-diagonal sums. 6349 // 6350 // Second, third (nested) and fourth loops. 6351 // zlen +=2; 6352 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) { 6353 // carry = 0; 6354 // long op2 = x[xidx:xidx+1]; 6355 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) { 6356 // k -= 2; 6357 // long op1 = x[j:j+1]; 6358 // long sum = z[k:k+1]; 6359 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs); 6360 // z[k:k+1] = sum; 6361 // } 6362 // add_one_64(z, k, carry, tmp_regs); 6363 // } 6364 6365 const Register carry = tmp5; 6366 const Register sum = tmp3; 6367 const Register op1 = tmp4; 6368 Register op2 = tmp2; 6369 6370 push(zlen); 6371 push(len); 6372 addl(zlen,2); 6373 bind(L_second_loop); 6374 xorq(carry, carry); 6375 subl(zlen, 4); 6376 subl(len, 2); 6377 push(zlen); 6378 push(len); 6379 cmpl(len, 0); 6380 jccb(Assembler::lessEqual, L_second_loop_exit); 6381 6382 // Multiply an array by one 64 bit long. 6383 if (UseBMI2Instructions) { 6384 op2 = rdxReg; 6385 movq(op2, Address(x, len, Address::times_4, 0)); 6386 rorxq(op2, op2, 32); 6387 } 6388 else { 6389 movq(op2, Address(x, len, Address::times_4, 0)); 6390 rorq(op2, 32); 6391 } 6392 6393 bind(L_third_loop); 6394 decrementl(len); 6395 jccb(Assembler::negative, L_third_loop_exit); 6396 decrementl(len); 6397 jccb(Assembler::negative, L_last_x); 6398 6399 movq(op1, Address(x, len, Address::times_4, 0)); 6400 rorq(op1, 32); 6401 6402 bind(L_multiply); 6403 subl(zlen, 2); 6404 movq(sum, Address(z, zlen, Address::times_4, 0)); 6405 6406 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry. 6407 if (UseBMI2Instructions) { 6408 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2); 6409 } 6410 else { 6411 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 6412 } 6413 6414 movq(Address(z, zlen, Address::times_4, 0), sum); 6415 6416 jmp(L_third_loop); 6417 bind(L_third_loop_exit); 6418 6419 // Fourth loop 6420 // Add 64 bit long carry into z with carry propogation. 6421 // Uses offsetted zlen. 6422 add_one_64(z, zlen, carry, tmp1); 6423 6424 pop(len); 6425 pop(zlen); 6426 jmp(L_second_loop); 6427 6428 // Next infrequent code is moved outside loops. 6429 bind(L_last_x); 6430 movl(op1, Address(x, 0)); 6431 jmp(L_multiply); 6432 6433 bind(L_second_loop_exit); 6434 pop(len); 6435 pop(zlen); 6436 pop(len); 6437 pop(zlen); 6438 6439 // Fifth loop 6440 // Shift z left 1 bit. 6441 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4); 6442 6443 // z[zlen-1] |= x[len-1] & 1; 6444 movl(tmp3, Address(x, len, Address::times_4, -4)); 6445 andl(tmp3, 1); 6446 orl(Address(z, zlen, Address::times_4, -4), tmp3); 6447 6448 pop(tmp5); 6449 pop(tmp4); 6450 pop(tmp3); 6451 pop(tmp2); 6452 pop(tmp1); 6453 } 6454 6455 /** 6456 * Helper function for mul_add() 6457 * Multiply the in[] by int k and add to out[] starting at offset offs using 6458 * 128 bit by 32 bit multiply and return the carry in tmp5. 6459 * Only quad int aligned length of in[] is operated on in this function. 6460 * k is in rdxReg for BMI2Instructions, for others it is in tmp2. 6461 * This function preserves out, in and k registers. 6462 * len and offset point to the appropriate index in "in" & "out" correspondingly 6463 * tmp5 has the carry. 6464 * other registers are temporary and are modified. 6465 * 6466 */ 6467 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in, 6468 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3, 6469 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 6470 6471 Label L_first_loop, L_first_loop_exit; 6472 6473 movl(tmp1, len); 6474 shrl(tmp1, 2); 6475 6476 bind(L_first_loop); 6477 subl(tmp1, 1); 6478 jccb(Assembler::negative, L_first_loop_exit); 6479 6480 subl(len, 4); 6481 subl(offset, 4); 6482 6483 Register op2 = tmp2; 6484 const Register sum = tmp3; 6485 const Register op1 = tmp4; 6486 const Register carry = tmp5; 6487 6488 if (UseBMI2Instructions) { 6489 op2 = rdxReg; 6490 } 6491 6492 movq(op1, Address(in, len, Address::times_4, 8)); 6493 rorq(op1, 32); 6494 movq(sum, Address(out, offset, Address::times_4, 8)); 6495 rorq(sum, 32); 6496 if (UseBMI2Instructions) { 6497 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 6498 } 6499 else { 6500 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 6501 } 6502 // Store back in big endian from little endian 6503 rorq(sum, 0x20); 6504 movq(Address(out, offset, Address::times_4, 8), sum); 6505 6506 movq(op1, Address(in, len, Address::times_4, 0)); 6507 rorq(op1, 32); 6508 movq(sum, Address(out, offset, Address::times_4, 0)); 6509 rorq(sum, 32); 6510 if (UseBMI2Instructions) { 6511 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 6512 } 6513 else { 6514 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 6515 } 6516 // Store back in big endian from little endian 6517 rorq(sum, 0x20); 6518 movq(Address(out, offset, Address::times_4, 0), sum); 6519 6520 jmp(L_first_loop); 6521 bind(L_first_loop_exit); 6522 } 6523 6524 /** 6525 * Code for BigInteger::mulAdd() intrinsic 6526 * 6527 * rdi: out 6528 * rsi: in 6529 * r11: offs (out.length - offset) 6530 * rcx: len 6531 * r8: k 6532 * r12: tmp1 6533 * r13: tmp2 6534 * r14: tmp3 6535 * r15: tmp4 6536 * rbx: tmp5 6537 * Multiply the in[] by word k and add to out[], return the carry in rax 6538 */ 6539 void MacroAssembler::mul_add(Register out, Register in, Register offs, 6540 Register len, Register k, Register tmp1, Register tmp2, Register tmp3, 6541 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 6542 6543 Label L_carry, L_last_in, L_done; 6544 6545 // carry = 0; 6546 // for (int j=len-1; j >= 0; j--) { 6547 // long product = (in[j] & LONG_MASK) * kLong + 6548 // (out[offs] & LONG_MASK) + carry; 6549 // out[offs--] = (int)product; 6550 // carry = product >>> 32; 6551 // } 6552 // 6553 push(tmp1); 6554 push(tmp2); 6555 push(tmp3); 6556 push(tmp4); 6557 push(tmp5); 6558 6559 Register op2 = tmp2; 6560 const Register sum = tmp3; 6561 const Register op1 = tmp4; 6562 const Register carry = tmp5; 6563 6564 if (UseBMI2Instructions) { 6565 op2 = rdxReg; 6566 movl(op2, k); 6567 } 6568 else { 6569 movl(op2, k); 6570 } 6571 6572 xorq(carry, carry); 6573 6574 //First loop 6575 6576 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply 6577 //The carry is in tmp5 6578 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg); 6579 6580 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any 6581 decrementl(len); 6582 jccb(Assembler::negative, L_carry); 6583 decrementl(len); 6584 jccb(Assembler::negative, L_last_in); 6585 6586 movq(op1, Address(in, len, Address::times_4, 0)); 6587 rorq(op1, 32); 6588 6589 subl(offs, 2); 6590 movq(sum, Address(out, offs, Address::times_4, 0)); 6591 rorq(sum, 32); 6592 6593 if (UseBMI2Instructions) { 6594 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 6595 } 6596 else { 6597 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 6598 } 6599 6600 // Store back in big endian from little endian 6601 rorq(sum, 0x20); 6602 movq(Address(out, offs, Address::times_4, 0), sum); 6603 6604 testl(len, len); 6605 jccb(Assembler::zero, L_carry); 6606 6607 //Multiply the last in[] entry, if any 6608 bind(L_last_in); 6609 movl(op1, Address(in, 0)); 6610 movl(sum, Address(out, offs, Address::times_4, -4)); 6611 6612 movl(raxReg, k); 6613 mull(op1); //tmp4 * eax -> edx:eax 6614 addl(sum, carry); 6615 adcl(rdxReg, 0); 6616 addl(sum, raxReg); 6617 adcl(rdxReg, 0); 6618 movl(carry, rdxReg); 6619 6620 movl(Address(out, offs, Address::times_4, -4), sum); 6621 6622 bind(L_carry); 6623 //return tmp5/carry as carry in rax 6624 movl(rax, carry); 6625 6626 bind(L_done); 6627 pop(tmp5); 6628 pop(tmp4); 6629 pop(tmp3); 6630 pop(tmp2); 6631 pop(tmp1); 6632 } 6633 #endif 6634 6635 /** 6636 * Emits code to update CRC-32 with a byte value according to constants in table 6637 * 6638 * @param [in,out]crc Register containing the crc. 6639 * @param [in]val Register containing the byte to fold into the CRC. 6640 * @param [in]table Register containing the table of crc constants. 6641 * 6642 * uint32_t crc; 6643 * val = crc_table[(val ^ crc) & 0xFF]; 6644 * crc = val ^ (crc >> 8); 6645 * 6646 */ 6647 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 6648 xorl(val, crc); 6649 andl(val, 0xFF); 6650 shrl(crc, 8); // unsigned shift 6651 xorl(crc, Address(table, val, Address::times_4, 0)); 6652 } 6653 6654 /** 6655 * Fold four 128-bit data chunks 6656 */ 6657 void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 6658 evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64] 6659 evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0] 6660 evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */); 6661 evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */); 6662 } 6663 6664 /** 6665 * Fold 128-bit data chunk 6666 */ 6667 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 6668 if (UseAVX > 0) { 6669 vpclmulhdq(xtmp, xK, xcrc); // [123:64] 6670 vpclmulldq(xcrc, xK, xcrc); // [63:0] 6671 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */); 6672 pxor(xcrc, xtmp); 6673 } else { 6674 movdqa(xtmp, xcrc); 6675 pclmulhdq(xtmp, xK); // [123:64] 6676 pclmulldq(xcrc, xK); // [63:0] 6677 pxor(xcrc, xtmp); 6678 movdqu(xtmp, Address(buf, offset)); 6679 pxor(xcrc, xtmp); 6680 } 6681 } 6682 6683 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { 6684 if (UseAVX > 0) { 6685 vpclmulhdq(xtmp, xK, xcrc); 6686 vpclmulldq(xcrc, xK, xcrc); 6687 pxor(xcrc, xbuf); 6688 pxor(xcrc, xtmp); 6689 } else { 6690 movdqa(xtmp, xcrc); 6691 pclmulhdq(xtmp, xK); 6692 pclmulldq(xcrc, xK); 6693 pxor(xcrc, xbuf); 6694 pxor(xcrc, xtmp); 6695 } 6696 } 6697 6698 /** 6699 * 8-bit folds to compute 32-bit CRC 6700 * 6701 * uint64_t xcrc; 6702 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); 6703 */ 6704 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { 6705 movdl(tmp, xcrc); 6706 andl(tmp, 0xFF); 6707 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); 6708 psrldq(xcrc, 1); // unsigned shift one byte 6709 pxor(xcrc, xtmp); 6710 } 6711 6712 /** 6713 * uint32_t crc; 6714 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); 6715 */ 6716 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 6717 movl(tmp, crc); 6718 andl(tmp, 0xFF); 6719 shrl(crc, 8); 6720 xorl(crc, Address(table, tmp, Address::times_4, 0)); 6721 } 6722 6723 /** 6724 * @param crc register containing existing CRC (32-bit) 6725 * @param buf register pointing to input byte buffer (byte*) 6726 * @param len register containing number of bytes 6727 * @param table register that will contain address of CRC table 6728 * @param tmp scratch register 6729 */ 6730 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { 6731 assert_different_registers(crc, buf, len, table, tmp, rax); 6732 6733 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 6734 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 6735 6736 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge 6737 // context for the registers used, where all instructions below are using 128-bit mode 6738 // On EVEX without VL and BW, these instructions will all be AVX. 6739 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); 6740 notl(crc); // ~crc 6741 cmpl(len, 16); 6742 jcc(Assembler::less, L_tail); 6743 6744 // Align buffer to 16 bytes 6745 movl(tmp, buf); 6746 andl(tmp, 0xF); 6747 jccb(Assembler::zero, L_aligned); 6748 subl(tmp, 16); 6749 addl(len, tmp); 6750 6751 align(4); 6752 BIND(L_align_loop); 6753 movsbl(rax, Address(buf, 0)); // load byte with sign extension 6754 update_byte_crc32(crc, rax, table); 6755 increment(buf); 6756 incrementl(tmp); 6757 jccb(Assembler::less, L_align_loop); 6758 6759 BIND(L_aligned); 6760 movl(tmp, len); // save 6761 shrl(len, 4); 6762 jcc(Assembler::zero, L_tail_restore); 6763 6764 // Fold crc into first bytes of vector 6765 movdqa(xmm1, Address(buf, 0)); 6766 movdl(rax, xmm1); 6767 xorl(crc, rax); 6768 if (VM_Version::supports_sse4_1()) { 6769 pinsrd(xmm1, crc, 0); 6770 } else { 6771 pinsrw(xmm1, crc, 0); 6772 shrl(crc, 16); 6773 pinsrw(xmm1, crc, 1); 6774 } 6775 addptr(buf, 16); 6776 subl(len, 4); // len > 0 6777 jcc(Assembler::less, L_fold_tail); 6778 6779 movdqa(xmm2, Address(buf, 0)); 6780 movdqa(xmm3, Address(buf, 16)); 6781 movdqa(xmm4, Address(buf, 32)); 6782 addptr(buf, 48); 6783 subl(len, 3); 6784 jcc(Assembler::lessEqual, L_fold_512b); 6785 6786 // Fold total 512 bits of polynomial on each iteration, 6787 // 128 bits per each of 4 parallel streams. 6788 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); 6789 6790 align(32); 6791 BIND(L_fold_512b_loop); 6792 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 6793 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); 6794 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); 6795 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); 6796 addptr(buf, 64); 6797 subl(len, 4); 6798 jcc(Assembler::greater, L_fold_512b_loop); 6799 6800 // Fold 512 bits to 128 bits. 6801 BIND(L_fold_512b); 6802 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 6803 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); 6804 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); 6805 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); 6806 6807 // Fold the rest of 128 bits data chunks 6808 BIND(L_fold_tail); 6809 addl(len, 3); 6810 jccb(Assembler::lessEqual, L_fold_128b); 6811 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 6812 6813 BIND(L_fold_tail_loop); 6814 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 6815 addptr(buf, 16); 6816 decrementl(len); 6817 jccb(Assembler::greater, L_fold_tail_loop); 6818 6819 // Fold 128 bits in xmm1 down into 32 bits in crc register. 6820 BIND(L_fold_128b); 6821 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr())); 6822 if (UseAVX > 0) { 6823 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); 6824 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */); 6825 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); 6826 } else { 6827 movdqa(xmm2, xmm0); 6828 pclmulqdq(xmm2, xmm1, 0x1); 6829 movdqa(xmm3, xmm0); 6830 pand(xmm3, xmm2); 6831 pclmulqdq(xmm0, xmm3, 0x1); 6832 } 6833 psrldq(xmm1, 8); 6834 psrldq(xmm2, 4); 6835 pxor(xmm0, xmm1); 6836 pxor(xmm0, xmm2); 6837 6838 // 8 8-bit folds to compute 32-bit CRC. 6839 for (int j = 0; j < 4; j++) { 6840 fold_8bit_crc32(xmm0, table, xmm1, rax); 6841 } 6842 movdl(crc, xmm0); // mov 32 bits to general register 6843 for (int j = 0; j < 4; j++) { 6844 fold_8bit_crc32(crc, table, rax); 6845 } 6846 6847 BIND(L_tail_restore); 6848 movl(len, tmp); // restore 6849 BIND(L_tail); 6850 andl(len, 0xf); 6851 jccb(Assembler::zero, L_exit); 6852 6853 // Fold the rest of bytes 6854 align(4); 6855 BIND(L_tail_loop); 6856 movsbl(rax, Address(buf, 0)); // load byte with sign extension 6857 update_byte_crc32(crc, rax, table); 6858 increment(buf); 6859 decrementl(len); 6860 jccb(Assembler::greater, L_tail_loop); 6861 6862 BIND(L_exit); 6863 notl(crc); // ~c 6864 } 6865 6866 #ifdef _LP64 6867 // S. Gueron / Information Processing Letters 112 (2012) 184 6868 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table. 6869 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0]. 6870 // Output: the 64-bit carry-less product of B * CONST 6871 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n, 6872 Register tmp1, Register tmp2, Register tmp3) { 6873 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 6874 if (n > 0) { 6875 addq(tmp3, n * 256 * 8); 6876 } 6877 // Q1 = TABLEExt[n][B & 0xFF]; 6878 movl(tmp1, in); 6879 andl(tmp1, 0x000000FF); 6880 shll(tmp1, 3); 6881 addq(tmp1, tmp3); 6882 movq(tmp1, Address(tmp1, 0)); 6883 6884 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 6885 movl(tmp2, in); 6886 shrl(tmp2, 8); 6887 andl(tmp2, 0x000000FF); 6888 shll(tmp2, 3); 6889 addq(tmp2, tmp3); 6890 movq(tmp2, Address(tmp2, 0)); 6891 6892 shlq(tmp2, 8); 6893 xorq(tmp1, tmp2); 6894 6895 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 6896 movl(tmp2, in); 6897 shrl(tmp2, 16); 6898 andl(tmp2, 0x000000FF); 6899 shll(tmp2, 3); 6900 addq(tmp2, tmp3); 6901 movq(tmp2, Address(tmp2, 0)); 6902 6903 shlq(tmp2, 16); 6904 xorq(tmp1, tmp2); 6905 6906 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 6907 shrl(in, 24); 6908 andl(in, 0x000000FF); 6909 shll(in, 3); 6910 addq(in, tmp3); 6911 movq(in, Address(in, 0)); 6912 6913 shlq(in, 24); 6914 xorq(in, tmp1); 6915 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 6916 } 6917 6918 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 6919 Register in_out, 6920 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 6921 XMMRegister w_xtmp2, 6922 Register tmp1, 6923 Register n_tmp2, Register n_tmp3) { 6924 if (is_pclmulqdq_supported) { 6925 movdl(w_xtmp1, in_out); // modified blindly 6926 6927 movl(tmp1, const_or_pre_comp_const_index); 6928 movdl(w_xtmp2, tmp1); 6929 pclmulqdq(w_xtmp1, w_xtmp2, 0); 6930 6931 movdq(in_out, w_xtmp1); 6932 } else { 6933 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3); 6934 } 6935 } 6936 6937 // Recombination Alternative 2: No bit-reflections 6938 // T1 = (CRC_A * U1) << 1 6939 // T2 = (CRC_B * U2) << 1 6940 // C1 = T1 >> 32 6941 // C2 = T2 >> 32 6942 // T1 = T1 & 0xFFFFFFFF 6943 // T2 = T2 & 0xFFFFFFFF 6944 // T1 = CRC32(0, T1) 6945 // T2 = CRC32(0, T2) 6946 // C1 = C1 ^ T1 6947 // C2 = C2 ^ T2 6948 // CRC = C1 ^ C2 ^ CRC_C 6949 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 6950 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 6951 Register tmp1, Register tmp2, 6952 Register n_tmp3) { 6953 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 6954 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 6955 shlq(in_out, 1); 6956 movl(tmp1, in_out); 6957 shrq(in_out, 32); 6958 xorl(tmp2, tmp2); 6959 crc32(tmp2, tmp1, 4); 6960 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here 6961 shlq(in1, 1); 6962 movl(tmp1, in1); 6963 shrq(in1, 32); 6964 xorl(tmp2, tmp2); 6965 crc32(tmp2, tmp1, 4); 6966 xorl(in1, tmp2); 6967 xorl(in_out, in1); 6968 xorl(in_out, in2); 6969 } 6970 6971 // Set N to predefined value 6972 // Subtract from a lenght of a buffer 6973 // execute in a loop: 6974 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0 6975 // for i = 1 to N do 6976 // CRC_A = CRC32(CRC_A, A[i]) 6977 // CRC_B = CRC32(CRC_B, B[i]) 6978 // CRC_C = CRC32(CRC_C, C[i]) 6979 // end for 6980 // Recombine 6981 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 6982 Register in_out1, Register in_out2, Register in_out3, 6983 Register tmp1, Register tmp2, Register tmp3, 6984 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 6985 Register tmp4, Register tmp5, 6986 Register n_tmp6) { 6987 Label L_processPartitions; 6988 Label L_processPartition; 6989 Label L_exit; 6990 6991 bind(L_processPartitions); 6992 cmpl(in_out1, 3 * size); 6993 jcc(Assembler::less, L_exit); 6994 xorl(tmp1, tmp1); 6995 xorl(tmp2, tmp2); 6996 movq(tmp3, in_out2); 6997 addq(tmp3, size); 6998 6999 bind(L_processPartition); 7000 crc32(in_out3, Address(in_out2, 0), 8); 7001 crc32(tmp1, Address(in_out2, size), 8); 7002 crc32(tmp2, Address(in_out2, size * 2), 8); 7003 addq(in_out2, 8); 7004 cmpq(in_out2, tmp3); 7005 jcc(Assembler::less, L_processPartition); 7006 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 7007 w_xtmp1, w_xtmp2, w_xtmp3, 7008 tmp4, tmp5, 7009 n_tmp6); 7010 addq(in_out2, 2 * size); 7011 subl(in_out1, 3 * size); 7012 jmp(L_processPartitions); 7013 7014 bind(L_exit); 7015 } 7016 #else 7017 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n, 7018 Register tmp1, Register tmp2, Register tmp3, 7019 XMMRegister xtmp1, XMMRegister xtmp2) { 7020 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 7021 if (n > 0) { 7022 addl(tmp3, n * 256 * 8); 7023 } 7024 // Q1 = TABLEExt[n][B & 0xFF]; 7025 movl(tmp1, in_out); 7026 andl(tmp1, 0x000000FF); 7027 shll(tmp1, 3); 7028 addl(tmp1, tmp3); 7029 movq(xtmp1, Address(tmp1, 0)); 7030 7031 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 7032 movl(tmp2, in_out); 7033 shrl(tmp2, 8); 7034 andl(tmp2, 0x000000FF); 7035 shll(tmp2, 3); 7036 addl(tmp2, tmp3); 7037 movq(xtmp2, Address(tmp2, 0)); 7038 7039 psllq(xtmp2, 8); 7040 pxor(xtmp1, xtmp2); 7041 7042 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 7043 movl(tmp2, in_out); 7044 shrl(tmp2, 16); 7045 andl(tmp2, 0x000000FF); 7046 shll(tmp2, 3); 7047 addl(tmp2, tmp3); 7048 movq(xtmp2, Address(tmp2, 0)); 7049 7050 psllq(xtmp2, 16); 7051 pxor(xtmp1, xtmp2); 7052 7053 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 7054 shrl(in_out, 24); 7055 andl(in_out, 0x000000FF); 7056 shll(in_out, 3); 7057 addl(in_out, tmp3); 7058 movq(xtmp2, Address(in_out, 0)); 7059 7060 psllq(xtmp2, 24); 7061 pxor(xtmp1, xtmp2); // Result in CXMM 7062 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 7063 } 7064 7065 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 7066 Register in_out, 7067 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 7068 XMMRegister w_xtmp2, 7069 Register tmp1, 7070 Register n_tmp2, Register n_tmp3) { 7071 if (is_pclmulqdq_supported) { 7072 movdl(w_xtmp1, in_out); 7073 7074 movl(tmp1, const_or_pre_comp_const_index); 7075 movdl(w_xtmp2, tmp1); 7076 pclmulqdq(w_xtmp1, w_xtmp2, 0); 7077 // Keep result in XMM since GPR is 32 bit in length 7078 } else { 7079 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2); 7080 } 7081 } 7082 7083 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 7084 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 7085 Register tmp1, Register tmp2, 7086 Register n_tmp3) { 7087 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 7088 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 7089 7090 psllq(w_xtmp1, 1); 7091 movdl(tmp1, w_xtmp1); 7092 psrlq(w_xtmp1, 32); 7093 movdl(in_out, w_xtmp1); 7094 7095 xorl(tmp2, tmp2); 7096 crc32(tmp2, tmp1, 4); 7097 xorl(in_out, tmp2); 7098 7099 psllq(w_xtmp2, 1); 7100 movdl(tmp1, w_xtmp2); 7101 psrlq(w_xtmp2, 32); 7102 movdl(in1, w_xtmp2); 7103 7104 xorl(tmp2, tmp2); 7105 crc32(tmp2, tmp1, 4); 7106 xorl(in1, tmp2); 7107 xorl(in_out, in1); 7108 xorl(in_out, in2); 7109 } 7110 7111 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 7112 Register in_out1, Register in_out2, Register in_out3, 7113 Register tmp1, Register tmp2, Register tmp3, 7114 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 7115 Register tmp4, Register tmp5, 7116 Register n_tmp6) { 7117 Label L_processPartitions; 7118 Label L_processPartition; 7119 Label L_exit; 7120 7121 bind(L_processPartitions); 7122 cmpl(in_out1, 3 * size); 7123 jcc(Assembler::less, L_exit); 7124 xorl(tmp1, tmp1); 7125 xorl(tmp2, tmp2); 7126 movl(tmp3, in_out2); 7127 addl(tmp3, size); 7128 7129 bind(L_processPartition); 7130 crc32(in_out3, Address(in_out2, 0), 4); 7131 crc32(tmp1, Address(in_out2, size), 4); 7132 crc32(tmp2, Address(in_out2, size*2), 4); 7133 crc32(in_out3, Address(in_out2, 0+4), 4); 7134 crc32(tmp1, Address(in_out2, size+4), 4); 7135 crc32(tmp2, Address(in_out2, size*2+4), 4); 7136 addl(in_out2, 8); 7137 cmpl(in_out2, tmp3); 7138 jcc(Assembler::less, L_processPartition); 7139 7140 push(tmp3); 7141 push(in_out1); 7142 push(in_out2); 7143 tmp4 = tmp3; 7144 tmp5 = in_out1; 7145 n_tmp6 = in_out2; 7146 7147 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 7148 w_xtmp1, w_xtmp2, w_xtmp3, 7149 tmp4, tmp5, 7150 n_tmp6); 7151 7152 pop(in_out2); 7153 pop(in_out1); 7154 pop(tmp3); 7155 7156 addl(in_out2, 2 * size); 7157 subl(in_out1, 3 * size); 7158 jmp(L_processPartitions); 7159 7160 bind(L_exit); 7161 } 7162 #endif //LP64 7163 7164 #ifdef _LP64 7165 // Algorithm 2: Pipelined usage of the CRC32 instruction. 7166 // Input: A buffer I of L bytes. 7167 // Output: the CRC32C value of the buffer. 7168 // Notations: 7169 // Write L = 24N + r, with N = floor (L/24). 7170 // r = L mod 24 (0 <= r < 24). 7171 // Consider I as the concatenation of A|B|C|R, where A, B, C, each, 7172 // N quadwords, and R consists of r bytes. 7173 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1 7174 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1 7175 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1 7176 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1 7177 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 7178 Register tmp1, Register tmp2, Register tmp3, 7179 Register tmp4, Register tmp5, Register tmp6, 7180 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 7181 bool is_pclmulqdq_supported) { 7182 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 7183 Label L_wordByWord; 7184 Label L_byteByByteProlog; 7185 Label L_byteByByte; 7186 Label L_exit; 7187 7188 if (is_pclmulqdq_supported ) { 7189 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 7190 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1); 7191 7192 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 7193 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 7194 7195 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 7196 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 7197 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\""); 7198 } else { 7199 const_or_pre_comp_const_index[0] = 1; 7200 const_or_pre_comp_const_index[1] = 0; 7201 7202 const_or_pre_comp_const_index[2] = 3; 7203 const_or_pre_comp_const_index[3] = 2; 7204 7205 const_or_pre_comp_const_index[4] = 5; 7206 const_or_pre_comp_const_index[5] = 4; 7207 } 7208 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 7209 in2, in1, in_out, 7210 tmp1, tmp2, tmp3, 7211 w_xtmp1, w_xtmp2, w_xtmp3, 7212 tmp4, tmp5, 7213 tmp6); 7214 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 7215 in2, in1, in_out, 7216 tmp1, tmp2, tmp3, 7217 w_xtmp1, w_xtmp2, w_xtmp3, 7218 tmp4, tmp5, 7219 tmp6); 7220 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 7221 in2, in1, in_out, 7222 tmp1, tmp2, tmp3, 7223 w_xtmp1, w_xtmp2, w_xtmp3, 7224 tmp4, tmp5, 7225 tmp6); 7226 movl(tmp1, in2); 7227 andl(tmp1, 0x00000007); 7228 negl(tmp1); 7229 addl(tmp1, in2); 7230 addq(tmp1, in1); 7231 7232 BIND(L_wordByWord); 7233 cmpq(in1, tmp1); 7234 jcc(Assembler::greaterEqual, L_byteByByteProlog); 7235 crc32(in_out, Address(in1, 0), 4); 7236 addq(in1, 4); 7237 jmp(L_wordByWord); 7238 7239 BIND(L_byteByByteProlog); 7240 andl(in2, 0x00000007); 7241 movl(tmp2, 1); 7242 7243 BIND(L_byteByByte); 7244 cmpl(tmp2, in2); 7245 jccb(Assembler::greater, L_exit); 7246 crc32(in_out, Address(in1, 0), 1); 7247 incq(in1); 7248 incl(tmp2); 7249 jmp(L_byteByByte); 7250 7251 BIND(L_exit); 7252 } 7253 #else 7254 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 7255 Register tmp1, Register tmp2, Register tmp3, 7256 Register tmp4, Register tmp5, Register tmp6, 7257 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 7258 bool is_pclmulqdq_supported) { 7259 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 7260 Label L_wordByWord; 7261 Label L_byteByByteProlog; 7262 Label L_byteByByte; 7263 Label L_exit; 7264 7265 if (is_pclmulqdq_supported) { 7266 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 7267 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1); 7268 7269 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 7270 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 7271 7272 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 7273 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 7274 } else { 7275 const_or_pre_comp_const_index[0] = 1; 7276 const_or_pre_comp_const_index[1] = 0; 7277 7278 const_or_pre_comp_const_index[2] = 3; 7279 const_or_pre_comp_const_index[3] = 2; 7280 7281 const_or_pre_comp_const_index[4] = 5; 7282 const_or_pre_comp_const_index[5] = 4; 7283 } 7284 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 7285 in2, in1, in_out, 7286 tmp1, tmp2, tmp3, 7287 w_xtmp1, w_xtmp2, w_xtmp3, 7288 tmp4, tmp5, 7289 tmp6); 7290 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 7291 in2, in1, in_out, 7292 tmp1, tmp2, tmp3, 7293 w_xtmp1, w_xtmp2, w_xtmp3, 7294 tmp4, tmp5, 7295 tmp6); 7296 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 7297 in2, in1, in_out, 7298 tmp1, tmp2, tmp3, 7299 w_xtmp1, w_xtmp2, w_xtmp3, 7300 tmp4, tmp5, 7301 tmp6); 7302 movl(tmp1, in2); 7303 andl(tmp1, 0x00000007); 7304 negl(tmp1); 7305 addl(tmp1, in2); 7306 addl(tmp1, in1); 7307 7308 BIND(L_wordByWord); 7309 cmpl(in1, tmp1); 7310 jcc(Assembler::greaterEqual, L_byteByByteProlog); 7311 crc32(in_out, Address(in1,0), 4); 7312 addl(in1, 4); 7313 jmp(L_wordByWord); 7314 7315 BIND(L_byteByByteProlog); 7316 andl(in2, 0x00000007); 7317 movl(tmp2, 1); 7318 7319 BIND(L_byteByByte); 7320 cmpl(tmp2, in2); 7321 jccb(Assembler::greater, L_exit); 7322 movb(tmp1, Address(in1, 0)); 7323 crc32(in_out, tmp1, 1); 7324 incl(in1); 7325 incl(tmp2); 7326 jmp(L_byteByByte); 7327 7328 BIND(L_exit); 7329 } 7330 #endif // LP64 7331 #undef BIND 7332 #undef BLOCK_COMMENT 7333 7334 // Compress char[] array to byte[]. 7335 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java 7336 // @HotSpotIntrinsicCandidate 7337 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) { 7338 // for (int i = 0; i < len; i++) { 7339 // int c = src[srcOff++]; 7340 // if (c >>> 8 != 0) { 7341 // return 0; 7342 // } 7343 // dst[dstOff++] = (byte)c; 7344 // } 7345 // return len; 7346 // } 7347 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 7348 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 7349 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 7350 Register tmp5, Register result) { 7351 Label copy_chars_loop, return_length, return_zero, done; 7352 7353 // rsi: src 7354 // rdi: dst 7355 // rdx: len 7356 // rcx: tmp5 7357 // rax: result 7358 7359 // rsi holds start addr of source char[] to be compressed 7360 // rdi holds start addr of destination byte[] 7361 // rdx holds length 7362 7363 assert(len != result, ""); 7364 7365 // save length for return 7366 push(len); 7367 7368 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512 7369 VM_Version::supports_avx512vlbw() && 7370 VM_Version::supports_bmi2()) { 7371 7372 Label copy_32_loop, copy_loop_tail, below_threshold; 7373 7374 // alignment 7375 Label post_alignment; 7376 7377 // if length of the string is less than 16, handle it in an old fashioned way 7378 testl(len, -32); 7379 jcc(Assembler::zero, below_threshold); 7380 7381 // First check whether a character is compressable ( <= 0xFF). 7382 // Create mask to test for Unicode chars inside zmm vector 7383 movl(result, 0x00FF); 7384 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit); 7385 7386 testl(len, -64); 7387 jcc(Assembler::zero, post_alignment); 7388 7389 movl(tmp5, dst); 7390 andl(tmp5, (32 - 1)); 7391 negl(tmp5); 7392 andl(tmp5, (32 - 1)); 7393 7394 // bail out when there is nothing to be done 7395 testl(tmp5, 0xFFFFFFFF); 7396 jcc(Assembler::zero, post_alignment); 7397 7398 // ~(~0 << len), where len is the # of remaining elements to process 7399 movl(result, 0xFFFFFFFF); 7400 shlxl(result, result, tmp5); 7401 notl(result); 7402 kmovdl(k3, result); 7403 7404 evmovdquw(tmp1Reg, k3, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit); 7405 evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 7406 ktestd(k2, k3); 7407 jcc(Assembler::carryClear, return_zero); 7408 7409 evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit); 7410 7411 addptr(src, tmp5); 7412 addptr(src, tmp5); 7413 addptr(dst, tmp5); 7414 subl(len, tmp5); 7415 7416 bind(post_alignment); 7417 // end of alignment 7418 7419 movl(tmp5, len); 7420 andl(tmp5, (32 - 1)); // tail count (in chars) 7421 andl(len, ~(32 - 1)); // vector count (in chars) 7422 jcc(Assembler::zero, copy_loop_tail); 7423 7424 lea(src, Address(src, len, Address::times_2)); 7425 lea(dst, Address(dst, len, Address::times_1)); 7426 negptr(len); 7427 7428 bind(copy_32_loop); 7429 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), /*merge*/ false, Assembler::AVX_512bit); 7430 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 7431 kortestdl(k2, k2); 7432 jcc(Assembler::carryClear, return_zero); 7433 7434 // All elements in current processed chunk are valid candidates for 7435 // compression. Write a truncated byte elements to the memory. 7436 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit); 7437 addptr(len, 32); 7438 jcc(Assembler::notZero, copy_32_loop); 7439 7440 bind(copy_loop_tail); 7441 // bail out when there is nothing to be done 7442 testl(tmp5, 0xFFFFFFFF); 7443 jcc(Assembler::zero, return_length); 7444 7445 movl(len, tmp5); 7446 7447 // ~(~0 << len), where len is the # of remaining elements to process 7448 movl(result, 0xFFFFFFFF); 7449 shlxl(result, result, len); 7450 notl(result); 7451 7452 kmovdl(k3, result); 7453 7454 evmovdquw(tmp1Reg, k3, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit); 7455 evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 7456 ktestd(k2, k3); 7457 jcc(Assembler::carryClear, return_zero); 7458 7459 evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit); 7460 jmp(return_length); 7461 7462 bind(below_threshold); 7463 } 7464 7465 if (UseSSE42Intrinsics) { 7466 Label copy_32_loop, copy_16, copy_tail; 7467 7468 movl(result, len); 7469 7470 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors 7471 7472 // vectored compression 7473 andl(len, 0xfffffff0); // vector count (in chars) 7474 andl(result, 0x0000000f); // tail count (in chars) 7475 testl(len, len); 7476 jcc(Assembler::zero, copy_16); 7477 7478 // compress 16 chars per iter 7479 movdl(tmp1Reg, tmp5); 7480 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 7481 pxor(tmp4Reg, tmp4Reg); 7482 7483 lea(src, Address(src, len, Address::times_2)); 7484 lea(dst, Address(dst, len, Address::times_1)); 7485 negptr(len); 7486 7487 bind(copy_32_loop); 7488 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters 7489 por(tmp4Reg, tmp2Reg); 7490 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters 7491 por(tmp4Reg, tmp3Reg); 7492 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector 7493 jcc(Assembler::notZero, return_zero); 7494 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte 7495 movdqu(Address(dst, len, Address::times_1), tmp2Reg); 7496 addptr(len, 16); 7497 jcc(Assembler::notZero, copy_32_loop); 7498 7499 // compress next vector of 8 chars (if any) 7500 bind(copy_16); 7501 movl(len, result); 7502 andl(len, 0xfffffff8); // vector count (in chars) 7503 andl(result, 0x00000007); // tail count (in chars) 7504 testl(len, len); 7505 jccb(Assembler::zero, copy_tail); 7506 7507 movdl(tmp1Reg, tmp5); 7508 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 7509 pxor(tmp3Reg, tmp3Reg); 7510 7511 movdqu(tmp2Reg, Address(src, 0)); 7512 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 7513 jccb(Assembler::notZero, return_zero); 7514 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte 7515 movq(Address(dst, 0), tmp2Reg); 7516 addptr(src, 16); 7517 addptr(dst, 8); 7518 7519 bind(copy_tail); 7520 movl(len, result); 7521 } 7522 // compress 1 char per iter 7523 testl(len, len); 7524 jccb(Assembler::zero, return_length); 7525 lea(src, Address(src, len, Address::times_2)); 7526 lea(dst, Address(dst, len, Address::times_1)); 7527 negptr(len); 7528 7529 bind(copy_chars_loop); 7530 load_unsigned_short(result, Address(src, len, Address::times_2)); 7531 testl(result, 0xff00); // check if Unicode char 7532 jccb(Assembler::notZero, return_zero); 7533 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte 7534 increment(len); 7535 jcc(Assembler::notZero, copy_chars_loop); 7536 7537 // if compression succeeded, return length 7538 bind(return_length); 7539 pop(result); 7540 jmpb(done); 7541 7542 // if compression failed, return 0 7543 bind(return_zero); 7544 xorl(result, result); 7545 addptr(rsp, wordSize); 7546 7547 bind(done); 7548 } 7549 7550 // Inflate byte[] array to char[]. 7551 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java 7552 // @HotSpotIntrinsicCandidate 7553 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) { 7554 // for (int i = 0; i < len; i++) { 7555 // dst[dstOff++] = (char)(src[srcOff++] & 0xff); 7556 // } 7557 // } 7558 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 7559 XMMRegister tmp1, Register tmp2) { 7560 Label copy_chars_loop, done, below_threshold, avx3_threshold; 7561 // rsi: src 7562 // rdi: dst 7563 // rdx: len 7564 // rcx: tmp2 7565 7566 // rsi holds start addr of source byte[] to be inflated 7567 // rdi holds start addr of destination char[] 7568 // rdx holds length 7569 assert_different_registers(src, dst, len, tmp2); 7570 movl(tmp2, len); 7571 if ((UseAVX > 2) && // AVX512 7572 VM_Version::supports_avx512vlbw() && 7573 VM_Version::supports_bmi2()) { 7574 7575 Label copy_32_loop, copy_tail; 7576 Register tmp3_aliased = len; 7577 7578 // if length of the string is less than 16, handle it in an old fashioned way 7579 testl(len, -16); 7580 jcc(Assembler::zero, below_threshold); 7581 7582 testl(len, -1 * AVX3Threshold); 7583 jcc(Assembler::zero, avx3_threshold); 7584 7585 // In order to use only one arithmetic operation for the main loop we use 7586 // this pre-calculation 7587 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop 7588 andl(len, -32); // vector count 7589 jccb(Assembler::zero, copy_tail); 7590 7591 lea(src, Address(src, len, Address::times_1)); 7592 lea(dst, Address(dst, len, Address::times_2)); 7593 negptr(len); 7594 7595 7596 // inflate 32 chars per iter 7597 bind(copy_32_loop); 7598 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit); 7599 evmovdquw(Address(dst, len, Address::times_2), tmp1, /*merge*/ false, Assembler::AVX_512bit); 7600 addptr(len, 32); 7601 jcc(Assembler::notZero, copy_32_loop); 7602 7603 bind(copy_tail); 7604 // bail out when there is nothing to be done 7605 testl(tmp2, -1); // we don't destroy the contents of tmp2 here 7606 jcc(Assembler::zero, done); 7607 7608 // ~(~0 << length), where length is the # of remaining elements to process 7609 movl(tmp3_aliased, -1); 7610 shlxl(tmp3_aliased, tmp3_aliased, tmp2); 7611 notl(tmp3_aliased); 7612 kmovdl(k2, tmp3_aliased); 7613 evpmovzxbw(tmp1, k2, Address(src, 0), Assembler::AVX_512bit); 7614 evmovdquw(Address(dst, 0), k2, tmp1, /*merge*/ true, Assembler::AVX_512bit); 7615 7616 jmp(done); 7617 bind(avx3_threshold); 7618 } 7619 if (UseSSE42Intrinsics) { 7620 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail; 7621 7622 if (UseAVX > 1) { 7623 andl(tmp2, (16 - 1)); 7624 andl(len, -16); 7625 jccb(Assembler::zero, copy_new_tail); 7626 } else { 7627 andl(tmp2, 0x00000007); // tail count (in chars) 7628 andl(len, 0xfffffff8); // vector count (in chars) 7629 jccb(Assembler::zero, copy_tail); 7630 } 7631 7632 // vectored inflation 7633 lea(src, Address(src, len, Address::times_1)); 7634 lea(dst, Address(dst, len, Address::times_2)); 7635 negptr(len); 7636 7637 if (UseAVX > 1) { 7638 bind(copy_16_loop); 7639 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit); 7640 vmovdqu(Address(dst, len, Address::times_2), tmp1); 7641 addptr(len, 16); 7642 jcc(Assembler::notZero, copy_16_loop); 7643 7644 bind(below_threshold); 7645 bind(copy_new_tail); 7646 movl(len, tmp2); 7647 andl(tmp2, 0x00000007); 7648 andl(len, 0xFFFFFFF8); 7649 jccb(Assembler::zero, copy_tail); 7650 7651 pmovzxbw(tmp1, Address(src, 0)); 7652 movdqu(Address(dst, 0), tmp1); 7653 addptr(src, 8); 7654 addptr(dst, 2 * 8); 7655 7656 jmp(copy_tail, true); 7657 } 7658 7659 // inflate 8 chars per iter 7660 bind(copy_8_loop); 7661 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words 7662 movdqu(Address(dst, len, Address::times_2), tmp1); 7663 addptr(len, 8); 7664 jcc(Assembler::notZero, copy_8_loop); 7665 7666 bind(copy_tail); 7667 movl(len, tmp2); 7668 7669 cmpl(len, 4); 7670 jccb(Assembler::less, copy_bytes); 7671 7672 movdl(tmp1, Address(src, 0)); // load 4 byte chars 7673 pmovzxbw(tmp1, tmp1); 7674 movq(Address(dst, 0), tmp1); 7675 subptr(len, 4); 7676 addptr(src, 4); 7677 addptr(dst, 8); 7678 7679 bind(copy_bytes); 7680 } else { 7681 bind(below_threshold); 7682 } 7683 7684 testl(len, len); 7685 jccb(Assembler::zero, done); 7686 lea(src, Address(src, len, Address::times_1)); 7687 lea(dst, Address(dst, len, Address::times_2)); 7688 negptr(len); 7689 7690 // inflate 1 char per iter 7691 bind(copy_chars_loop); 7692 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char 7693 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word 7694 increment(len); 7695 jcc(Assembler::notZero, copy_chars_loop); 7696 7697 bind(done); 7698 } 7699 7700 #ifdef _LP64 7701 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) { 7702 Label done; 7703 cvttss2sil(dst, src); 7704 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 7705 cmpl(dst, 0x80000000); // float_sign_flip 7706 jccb(Assembler::notEqual, done); 7707 subptr(rsp, 8); 7708 movflt(Address(rsp, 0), src); 7709 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup()))); 7710 pop(dst); 7711 bind(done); 7712 } 7713 7714 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) { 7715 Label done; 7716 cvttsd2sil(dst, src); 7717 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 7718 cmpl(dst, 0x80000000); // float_sign_flip 7719 jccb(Assembler::notEqual, done); 7720 subptr(rsp, 8); 7721 movdbl(Address(rsp, 0), src); 7722 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup()))); 7723 pop(dst); 7724 bind(done); 7725 } 7726 7727 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) { 7728 Label done; 7729 cvttss2siq(dst, src); 7730 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip())); 7731 jccb(Assembler::notEqual, done); 7732 subptr(rsp, 8); 7733 movflt(Address(rsp, 0), src); 7734 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup()))); 7735 pop(dst); 7736 bind(done); 7737 } 7738 7739 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) { 7740 Label done; 7741 cvttsd2siq(dst, src); 7742 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip())); 7743 jccb(Assembler::notEqual, done); 7744 subptr(rsp, 8); 7745 movdbl(Address(rsp, 0), src); 7746 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup()))); 7747 pop(dst); 7748 bind(done); 7749 } 7750 7751 void MacroAssembler::cache_wb(Address line) 7752 { 7753 // 64 bit cpus always support clflush 7754 assert(VM_Version::supports_clflush(), "clflush should be available"); 7755 bool optimized = VM_Version::supports_clflushopt(); 7756 bool no_evict = VM_Version::supports_clwb(); 7757 7758 // prefer clwb (writeback without evict) otherwise 7759 // prefer clflushopt (potentially parallel writeback with evict) 7760 // otherwise fallback on clflush (serial writeback with evict) 7761 7762 if (optimized) { 7763 if (no_evict) { 7764 clwb(line); 7765 } else { 7766 clflushopt(line); 7767 } 7768 } else { 7769 // no need for fence when using CLFLUSH 7770 clflush(line); 7771 } 7772 } 7773 7774 void MacroAssembler::cache_wbsync(bool is_pre) 7775 { 7776 assert(VM_Version::supports_clflush(), "clflush should be available"); 7777 bool optimized = VM_Version::supports_clflushopt(); 7778 bool no_evict = VM_Version::supports_clwb(); 7779 7780 // pick the correct implementation 7781 7782 if (!is_pre && (optimized || no_evict)) { 7783 // need an sfence for post flush when using clflushopt or clwb 7784 // otherwise no no need for any synchroniaztion 7785 7786 sfence(); 7787 } 7788 } 7789 #endif // _LP64 7790 7791 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 7792 switch (cond) { 7793 // Note some conditions are synonyms for others 7794 case Assembler::zero: return Assembler::notZero; 7795 case Assembler::notZero: return Assembler::zero; 7796 case Assembler::less: return Assembler::greaterEqual; 7797 case Assembler::lessEqual: return Assembler::greater; 7798 case Assembler::greater: return Assembler::lessEqual; 7799 case Assembler::greaterEqual: return Assembler::less; 7800 case Assembler::below: return Assembler::aboveEqual; 7801 case Assembler::belowEqual: return Assembler::above; 7802 case Assembler::above: return Assembler::belowEqual; 7803 case Assembler::aboveEqual: return Assembler::below; 7804 case Assembler::overflow: return Assembler::noOverflow; 7805 case Assembler::noOverflow: return Assembler::overflow; 7806 case Assembler::negative: return Assembler::positive; 7807 case Assembler::positive: return Assembler::negative; 7808 case Assembler::parity: return Assembler::noParity; 7809 case Assembler::noParity: return Assembler::parity; 7810 } 7811 ShouldNotReachHere(); return Assembler::overflow; 7812 } 7813 7814 SkipIfEqual::SkipIfEqual( 7815 MacroAssembler* masm, const bool* flag_addr, bool value) { 7816 _masm = masm; 7817 _masm->cmp8(ExternalAddress((address)flag_addr), value); 7818 _masm->jcc(Assembler::equal, _label); 7819 } 7820 7821 SkipIfEqual::~SkipIfEqual() { 7822 _masm->bind(_label); 7823 } 7824 7825 // 32-bit Windows has its own fast-path implementation 7826 // of get_thread 7827 #if !defined(WIN32) || defined(_LP64) 7828 7829 // This is simply a call to Thread::current() 7830 void MacroAssembler::get_thread(Register thread) { 7831 if (thread != rax) { 7832 push(rax); 7833 } 7834 LP64_ONLY(push(rdi);) 7835 LP64_ONLY(push(rsi);) 7836 push(rdx); 7837 push(rcx); 7838 #ifdef _LP64 7839 push(r8); 7840 push(r9); 7841 push(r10); 7842 push(r11); 7843 #endif 7844 7845 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0); 7846 7847 #ifdef _LP64 7848 pop(r11); 7849 pop(r10); 7850 pop(r9); 7851 pop(r8); 7852 #endif 7853 pop(rcx); 7854 pop(rdx); 7855 LP64_ONLY(pop(rsi);) 7856 LP64_ONLY(pop(rdi);) 7857 if (thread != rax) { 7858 mov(thread, rax); 7859 pop(rax); 7860 } 7861 } 7862 7863 #endif // !WIN32 || _LP64