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src/hotspot/cpu/x86/x86_32.ad
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rev 60518 : Fix 32 bit build issue after cleanup.
@@ -3320,21 +3320,21 @@
format %{ %}
interface(CONST_INTER);
%}
// Constant for test vs zero
-operand immI0() %{
+operand immI_0() %{
predicate(n->get_int() == 0);
match(ConI);
op_cost(0);
format %{ %}
interface(CONST_INTER);
%}
// Constant for increment
-operand immI1() %{
+operand immI_1() %{
predicate(n->get_int() == 1);
match(ConI);
op_cost(0);
format %{ %}
@@ -3367,10 +3367,20 @@
op_cost(5);
format %{ %}
interface(CONST_INTER);
%}
+operand immU8()
+%{
+ predicate((0 <= n->get_int()) && (n->get_int() <= 255));
+ match(ConI);
+
+ op_cost(5);
+ format %{ %}
+ interface(CONST_INTER);
+%}
+
operand immI16() %{
predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
match(ConI);
op_cost(10);
@@ -3415,30 +3425,41 @@
format %{ %}
interface(CONST_INTER);
%}
-operand immI_1() %{
- predicate( n->get_int() == 1 );
+operand immI_2() %{
+ predicate( n->get_int() == 2 );
match(ConI);
op_cost(0);
format %{ %}
interface(CONST_INTER);
%}
-operand immI_2() %{
- predicate( n->get_int() == 2 );
+operand immI_3() %{
+ predicate( n->get_int() == 3 );
match(ConI);
op_cost(0);
format %{ %}
interface(CONST_INTER);
%}
-operand immI_3() %{
- predicate( n->get_int() == 3 );
+operand immI_4()
+%{
+ predicate(n->get_int() == 4);
+ match(ConI);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+%}
+
+operand immI_8()
+%{
+ predicate(n->get_int() == 8);
match(ConI);
op_cost(0);
format %{ %}
interface(CONST_INTER);
@@ -3811,10 +3832,22 @@
format %{ %}
interface(REG_INTER);
%}
+operand rRegP() %{
+ constraint(ALLOC_IN_RC(int_reg));
+ match(RegP);
+ match(eAXRegP);
+ match(eBXRegP);
+ match(eCXRegP);
+ match(eDIRegP);
+
+ format %{ %}
+ interface(REG_INTER);
+%}
+
// On windows95, EBP is not safe to use for implicit null tests.
operand eRegP_no_EBP() %{
constraint(ALLOC_IN_RC(int_reg_no_ebp));
match(RegP);
match(eAXRegP);
@@ -3944,10 +3977,19 @@
format %{ "EAX" %}
interface(REG_INTER);
%}
// Flags register, used as output of compare instructions
+operand rFlagsReg() %{
+ constraint(ALLOC_IN_RC(int_flags));
+ match(RegFlags);
+
+ format %{ "EFLAGS" %}
+ interface(REG_INTER);
+%}
+
+// Flags register, used as output of compare instructions
operand eFlagsReg() %{
constraint(ALLOC_IN_RC(int_flags));
match(RegFlags);
format %{ "EFLAGS" %}
@@ -4073,10 +4115,18 @@
match(RegF);
format %{ %}
interface(REG_INTER);
%}
+operand legRegF() %{
+ predicate( UseSSE>=1 );
+ constraint(ALLOC_IN_RC(float_reg_legacy));
+ match(RegF);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
// Float register operands
operand vlRegF() %{
constraint(ALLOC_IN_RC(float_reg_vl));
match(RegF);
@@ -4092,10 +4142,18 @@
format %{ %}
interface(REG_INTER);
%}
// Double register operands
+operand legRegD() %{
+ predicate( UseSSE>=2 );
+ constraint(ALLOC_IN_RC(double_reg_legacy));
+ match(RegD);
+ format %{ %}
+ interface(REG_INTER);
+%}
+
operand vlRegD() %{
constraint(ALLOC_IN_RC(double_reg_vl));
match(RegD);
format %{ %}
@@ -5842,10 +5900,50 @@
opcode(0x8B);
ins_encode( OpcP, RegMem(dst,mem));
ins_pipe( ialu_reg_mem );
%}
+// Load Float
+instruct MoveF2LEG(legRegF dst, regF src) %{
+ match(Set dst src);
+ format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
+ ins_encode %{
+ __ movflt($dst$$XMMRegister, $src$$XMMRegister);
+ %}
+ ins_pipe( fpu_reg_reg );
+%}
+
+// Load Float
+instruct MoveLEG2F(regF dst, legRegF src) %{
+ match(Set dst src);
+ format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
+ ins_encode %{
+ __ movflt($dst$$XMMRegister, $src$$XMMRegister);
+ %}
+ ins_pipe( fpu_reg_reg );
+%}
+
+// Load Double
+instruct MoveD2LEG(legRegD dst, regD src) %{
+ match(Set dst src);
+ format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
+ ins_encode %{
+ __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
+ %}
+ ins_pipe( fpu_reg_reg );
+%}
+
+// Load Double
+instruct MoveLEG2D(regD dst, legRegD src) %{
+ match(Set dst src);
+ format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
+ ins_encode %{
+ __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
+ %}
+ ins_pipe( fpu_reg_reg );
+%}
+
// Load Double
instruct loadDPR(regDPR dst, memory mem) %{
predicate(UseSSE<=1);
match(Set dst (LoadD mem));
@@ -5967,11 +6065,11 @@
ins_encode( LdImmI(dst, src) );
ins_pipe( ialu_reg_fat );
%}
// Load Constant zero
-instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
+instruct loadConI0(rRegI dst, immI_0 src, eFlagsReg cr) %{
match(Set dst src);
effect(KILL cr);
ins_cost(50);
format %{ "XOR $dst,$dst" %}
@@ -7079,11 +7177,11 @@
opcode(0x81, 0x00); /* /0 id */
ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
ins_pipe( ialu_reg );
%}
-instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
+instruct incI_eReg(rRegI dst, immI_1 src, eFlagsReg cr) %{
predicate(UseIncDec);
match(Set dst (AddI dst src));
effect(KILL cr);
size(1);
@@ -7179,11 +7277,11 @@
opcode(0x81); /* Opcode 81 /0 id */
ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
ins_pipe( ialu_mem_imm );
%}
-instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
+instruct incI_mem(memory dst, immI_1 src, eFlagsReg cr) %{
match(Set dst (StoreI dst (AddI (LoadI dst) src)));
effect(KILL cr);
ins_cost(125);
format %{ "INC $dst" %}
@@ -7557,22 +7655,22 @@
ins_encode( OpcP, RegMem( src, dst ) );
ins_pipe( ialu_mem_reg );
%}
// Subtract from a pointer
-instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
+instruct subP_eReg(eRegP dst, rRegI src, immI_0 zero, eFlagsReg cr) %{
match(Set dst (AddP dst (SubI zero src)));
effect(KILL cr);
size(2);
format %{ "SUB $dst,$src" %}
opcode(0x2B);
ins_encode( OpcP, RegReg( dst, src) );
ins_pipe( ialu_reg_reg );
%}
-instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
+instruct negI_eReg(rRegI dst, immI_0 zero, eFlagsReg cr) %{
match(Set dst (SubI zero dst));
effect(KILL cr);
size(2);
format %{ "NEG $dst" %}
@@ -8022,11 +8120,11 @@
ins_pipe( pipe_slow );
%}
// Integer Shift Instructions
// Shift Left by one
-instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
+instruct shlI_eReg_1(rRegI dst, immI_1 shift, eFlagsReg cr) %{
match(Set dst (LShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SHL $dst,$shift" %}
@@ -8058,11 +8156,11 @@
ins_encode( OpcP, RegOpc( dst ) );
ins_pipe( ialu_reg_reg );
%}
// Arithmetic shift right by one
-instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
+instruct sarI_eReg_1(rRegI dst, immI_1 shift, eFlagsReg cr) %{
match(Set dst (RShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SAR $dst,$shift" %}
@@ -8070,11 +8168,11 @@
ins_encode( OpcP, RegOpc( dst ) );
ins_pipe( ialu_reg );
%}
// Arithmetic shift right by one
-instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
+instruct sarI_mem_1(memory dst, immI_1 shift, eFlagsReg cr) %{
match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
effect(KILL cr);
format %{ "SAR $dst,$shift" %}
opcode(0xD1, 0x7); /* D1 /7 */
ins_encode( OpcP, RMopc_Mem(secondary,dst) );
@@ -8115,11 +8213,11 @@
ins_encode( OpcP, RegOpc( dst ) );
ins_pipe( ialu_reg_reg );
%}
// Logical shift right by one
-instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
+instruct shrI_eReg_1(rRegI dst, immI_1 shift, eFlagsReg cr) %{
match(Set dst (URShiftI dst shift));
effect(KILL cr);
size(2);
format %{ "SHR $dst,$shift" %}
@@ -8271,11 +8369,11 @@
__ andnl($dst$$Register, $src1$$Register, $src2$$Address);
%}
ins_pipe(ialu_reg_mem);
%}
-instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{
+instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, eFlagsReg cr) %{
match(Set dst (AndI (SubI imm_zero src) src));
predicate(UseBMI1Instructions);
effect(KILL cr);
format %{ "BLSIL $dst, $src" %}
@@ -8284,11 +8382,11 @@
__ blsil($dst$$Register, $src$$Register);
%}
ins_pipe(ialu_reg);
%}
-instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{
+instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, eFlagsReg cr) %{
match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
predicate(UseBMI1Instructions);
effect(KILL cr);
ins_cost(125);
@@ -8436,11 +8534,11 @@
ins_pipe( ialu_mem_imm );
%}
// ROL/ROR
// ROL expand
-instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
+instruct rolI_eReg_imm1(rRegI dst, immI_1 shift, eFlagsReg cr) %{
effect(USE_DEF dst, USE shift, KILL cr);
format %{ "ROL $dst, $shift" %}
opcode(0xD1, 0x0); /* Opcode D1 /0 */
ins_encode( OpcP, RegOpc( dst ));
@@ -8465,11 +8563,11 @@
ins_pipe( ialu_reg_reg );
%}
// end of ROL expand
// ROL 32bit by one once
-instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
+instruct rolI_eReg_i1(rRegI dst, immI_1 lshift, immI_M1 rshift, eFlagsReg cr) %{
match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
expand %{
rolI_eReg_imm1(dst, lshift, cr);
%}
@@ -8484,11 +8582,11 @@
rolI_eReg_imm8(dst, lshift, cr);
%}
%}
// ROL 32bit var by var once
-instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
+instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI_0 zero, eFlagsReg cr) %{
match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
expand %{
rolI_eReg_CL(dst, shift, cr);
%}
@@ -8502,11 +8600,11 @@
rolI_eReg_CL(dst, shift, cr);
%}
%}
// ROR expand
-instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
+instruct rorI_eReg_imm1(rRegI dst, immI_1 shift, eFlagsReg cr) %{
effect(USE_DEF dst, USE shift, KILL cr);
format %{ "ROR $dst, $shift" %}
opcode(0xD1,0x1); /* Opcode D1 /1 */
ins_encode( OpcP, RegOpc( dst ) );
@@ -8531,11 +8629,11 @@
ins_pipe( ialu_reg_reg );
%}
// end of ROR expand
// ROR right once
-instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
+instruct rorI_eReg_i1(rRegI dst, immI_1 rshift, immI_M1 lshift, eFlagsReg cr) %{
match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
expand %{
rorI_eReg_imm1(dst, rshift, cr);
%}
@@ -8550,11 +8648,11 @@
rorI_eReg_imm8(dst, rshift, cr);
%}
%}
// ROR 32bit var by var once
-instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
+instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI_0 zero, eFlagsReg cr) %{
match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
expand %{
rorI_eReg_CL(dst, shift, cr);
%}
@@ -8718,11 +8816,11 @@
%}
ins_pipe(pipe_slow);
%}
-instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
+instruct cmpLTMask0(rRegI dst, immI_0 zero, eFlagsReg cr) %{
match(Set dst (CmpLTMask dst zero));
effect(DEF dst, KILL cr);
ins_cost(100);
format %{ "SAR $dst,31\t# cmpLTMask0" %}
@@ -8832,11 +8930,11 @@
__ cmpl($op1$$Register, $op2$$constant);
%}
ins_pipe(ialu_reg_reg);
%}
-instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2)
+instruct overflowNegI_rReg(eFlagsReg cr, immI_0 zero, eAXRegI op2)
%{
match(Set cr (OverflowSubI zero op2));
effect(DEF cr, USE_KILL op2);
format %{ "NEG $op2\t# overflow check int" %}
@@ -11970,30 +12068,30 @@
opcode(0x3B); /* Opcode 3B /r */
ins_encode( OpcP, RegMem( op1, op2) );
ins_pipe( ialu_cr_reg_mem );
%}
-instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
+instruct testI_reg( eFlagsReg cr, rRegI src, immI_0 zero ) %{
match(Set cr (CmpI src zero));
effect( DEF cr, USE src );
format %{ "TEST $src,$src" %}
opcode(0x85);
ins_encode( OpcP, RegReg( src, src ) );
ins_pipe( ialu_cr_reg_imm );
%}
-instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
+instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI_0 zero ) %{
match(Set cr (CmpI (AndI src con) zero));
format %{ "TEST $src,$con" %}
opcode(0xF7,0x00);
ins_encode( OpcP, RegOpc(src), Con32(con) );
ins_pipe( ialu_cr_reg_imm );
%}
-instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
+instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI_0 zero ) %{
match(Set cr (CmpI (AndI src mem) zero));
format %{ "TEST $src,$mem" %}
opcode(0x85);
ins_encode( OpcP, RegMem( src, mem ) );
@@ -12039,11 +12137,11 @@
// ins_cost(500);
// opcode(0x39); /* Opcode 39 /r */
// ins_encode( OpcP, RegMem( op1, op2) );
//%}
-instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
+instruct testU_reg( eFlagsRegU cr, rRegI src, immI_0 zero ) %{
match(Set cr (CmpU src zero));
format %{ "TESTu $src,$src" %}
opcode(0x85);
ins_encode( OpcP, RegReg( src, src ) );
@@ -12116,11 +12214,11 @@
%}
// Cisc-spilled version of testP_reg
// This will generate a signed flags result. This should be ok
// since any compare to a zero should be eq/neq.
-instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
+instruct testP_Reg_mem( eFlagsReg cr, memory op, immI_0 zero ) %{
match(Set cr (CmpP (LoadP op) zero));
format %{ "TEST $op,0xFFFFFFFF" %}
ins_cost(500);
opcode(0xF7); /* Opcode F7 /0 */
@@ -13487,11 +13585,11 @@
// // pertinent parts of existing instructions in architecture description
// instruct movI(rRegI dst, rRegI src) %{
// match(Set dst (CopyI src));
// %}
//
-// instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
+// instruct incI_eReg(rRegI dst, immI_1 src, eFlagsReg cr) %{
// match(Set dst (AddI dst src));
// effect(KILL cr);
// %}
//
// // Change (inc mov) to lea
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