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src/hotspot/cpu/x86/x86_64.ad
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rev 60516 : manual merge with default
*** 2876,2897 ****
format %{ %}
interface(CONST_INTER);
%}
// Constant for test vs zero
! operand immI0()
%{
predicate(n->get_int() == 0);
match(ConI);
op_cost(0);
format %{ %}
interface(CONST_INTER);
%}
// Constant for increment
! operand immI1()
%{
predicate(n->get_int() == 1);
match(ConI);
op_cost(0);
--- 2876,2897 ----
format %{ %}
interface(CONST_INTER);
%}
// Constant for test vs zero
! operand immI_0()
%{
predicate(n->get_int() == 0);
match(ConI);
op_cost(0);
format %{ %}
interface(CONST_INTER);
%}
// Constant for increment
! operand immI_1()
%{
predicate(n->get_int() == 1);
match(ConI);
op_cost(0);
*** 2908,2917 ****
--- 2908,2947 ----
op_cost(0);
format %{ %}
interface(CONST_INTER);
%}
+ operand immI_2()
+ %{
+ predicate(n->get_int() == 2);
+ match(ConI);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+ %}
+
+ operand immI_4()
+ %{
+ predicate(n->get_int() == 4);
+ match(ConI);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+ %}
+
+ operand immI_8()
+ %{
+ predicate(n->get_int() == 8);
+ match(ConI);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+ %}
+
// Valid scale values for addressing modes
operand immI2()
%{
predicate(0 <= n->get_int() && (n->get_int() <= 3));
match(ConI);
*** 5265,5287 ****
instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
predicate(UseAVX > 0 && !n->is_reduction());
match(Set dst (MaxF a b));
effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
format %{
! "blendvps $btmp,$b,$a,$b \n\t"
! "blendvps $atmp,$a,$b,$b \n\t"
"vmaxss $tmp,$atmp,$btmp \n\t"
! "cmpps.unordered $btmp,$atmp,$atmp \n\t"
! "blendvps $dst,$tmp,$atmp,$btmp \n\t"
%}
ins_encode %{
int vector_len = Assembler::AVX_128bit;
! __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
! __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
__ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
! __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
! __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
%}
ins_pipe( pipe_slow );
%}
instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
--- 5295,5317 ----
instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
predicate(UseAVX > 0 && !n->is_reduction());
match(Set dst (MaxF a b));
effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
format %{
! "vblendvps $btmp,$b,$a,$b \n\t"
! "vblendvps $atmp,$a,$b,$b \n\t"
"vmaxss $tmp,$atmp,$btmp \n\t"
! "vcmpps.unordered $btmp,$atmp,$atmp \n\t"
! "vblendvps $dst,$tmp,$atmp,$btmp \n\t"
%}
ins_encode %{
int vector_len = Assembler::AVX_128bit;
! __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
! __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
__ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
! __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
! __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
%}
ins_pipe( pipe_slow );
%}
instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
*** 5301,5323 ****
instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
predicate(UseAVX > 0 && !n->is_reduction());
match(Set dst (MaxD a b));
effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
format %{
! "blendvpd $btmp,$b,$a,$b \n\t"
! "blendvpd $atmp,$a,$b,$b \n\t"
"vmaxsd $tmp,$atmp,$btmp \n\t"
! "cmppd.unordered $btmp,$atmp,$atmp \n\t"
! "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
%}
ins_encode %{
int vector_len = Assembler::AVX_128bit;
! __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
! __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
__ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
! __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
! __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
%}
ins_pipe( pipe_slow );
%}
instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
--- 5331,5353 ----
instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
predicate(UseAVX > 0 && !n->is_reduction());
match(Set dst (MaxD a b));
effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
format %{
! "vblendvpd $btmp,$b,$a,$b \n\t"
! "vblendvpd $atmp,$a,$b,$b \n\t"
"vmaxsd $tmp,$atmp,$btmp \n\t"
! "vcmppd.unordered $btmp,$atmp,$atmp \n\t"
! "vblendvpd $dst,$tmp,$atmp,$btmp \n\t"
%}
ins_encode %{
int vector_len = Assembler::AVX_128bit;
! __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
! __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
__ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
! __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
! __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
%}
ins_pipe( pipe_slow );
%}
instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
*** 5337,5359 ****
instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
predicate(UseAVX > 0 && !n->is_reduction());
match(Set dst (MinF a b));
effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
format %{
! "blendvps $atmp,$a,$b,$a \n\t"
! "blendvps $btmp,$b,$a,$a \n\t"
"vminss $tmp,$atmp,$btmp \n\t"
! "cmpps.unordered $btmp,$atmp,$atmp \n\t"
! "blendvps $dst,$tmp,$atmp,$btmp \n\t"
%}
ins_encode %{
int vector_len = Assembler::AVX_128bit;
! __ blendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
! __ blendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
__ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
! __ cmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
! __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
%}
ins_pipe( pipe_slow );
%}
instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
--- 5367,5389 ----
instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
predicate(UseAVX > 0 && !n->is_reduction());
match(Set dst (MinF a b));
effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
format %{
! "vblendvps $atmp,$a,$b,$a \n\t"
! "vblendvps $btmp,$b,$a,$a \n\t"
"vminss $tmp,$atmp,$btmp \n\t"
! "vcmpps.unordered $btmp,$atmp,$atmp \n\t"
! "vblendvps $dst,$tmp,$atmp,$btmp \n\t"
%}
ins_encode %{
int vector_len = Assembler::AVX_128bit;
! __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
! __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
__ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
! __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
! __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
%}
ins_pipe( pipe_slow );
%}
instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
*** 5373,5395 ****
instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
predicate(UseAVX > 0 && !n->is_reduction());
match(Set dst (MinD a b));
effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
format %{
! "blendvpd $atmp,$a,$b,$a \n\t"
! "blendvpd $btmp,$b,$a,$a \n\t"
"vminsd $tmp,$atmp,$btmp \n\t"
! "cmppd.unordered $btmp,$atmp,$atmp \n\t"
! "blendvpd $dst,$tmp,$atmp,$btmp \n\t"
%}
ins_encode %{
int vector_len = Assembler::AVX_128bit;
! __ blendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
! __ blendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
__ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
! __ cmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
! __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
%}
ins_pipe( pipe_slow );
%}
instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
--- 5403,5425 ----
instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
predicate(UseAVX > 0 && !n->is_reduction());
match(Set dst (MinD a b));
effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
format %{
! "vblendvpd $atmp,$a,$b,$a \n\t"
! "vblendvpd $btmp,$b,$a,$a \n\t"
"vminsd $tmp,$atmp,$btmp \n\t"
! "vcmppd.unordered $btmp,$atmp,$atmp \n\t"
! "vblendvpd $dst,$tmp,$atmp,$btmp \n\t"
%}
ins_encode %{
int vector_len = Assembler::AVX_128bit;
! __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
! __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
__ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
! __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
! __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
%}
ins_pipe( pipe_slow );
%}
instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
*** 5609,5619 ****
format %{ "movl $dst, $src\t# int" %}
ins_encode(load_immI(dst, src));
ins_pipe(ialu_reg_fat); // XXX
%}
! instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
%{
match(Set dst src);
effect(KILL cr);
ins_cost(50);
--- 5639,5649 ----
format %{ "movl $dst, $src\t# int" %}
ins_encode(load_immI(dst, src));
ins_pipe(ialu_reg_fat); // XXX
%}
! instruct loadConI0(rRegI dst, immI_0 src, rFlagsReg cr)
%{
match(Set dst src);
effect(KILL cr);
ins_cost(50);
*** 6045,6055 ****
%}
ins_pipe(ialu_mem_imm);
%}
// Store Integer Immediate
! instruct storeImmI0(memory mem, immI0 zero)
%{
predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
match(Set mem (StoreI mem zero));
ins_cost(125); // XXX
--- 6075,6085 ----
%}
ins_pipe(ialu_mem_imm);
%}
// Store Integer Immediate
! instruct storeImmI0(memory mem, immI_0 zero)
%{
predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
match(Set mem (StoreI mem zero));
ins_cost(125); // XXX
*** 6095,6105 ****
ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
ins_pipe(ialu_mem_imm);
%}
// Store Short/Char Immediate
! instruct storeImmC0(memory mem, immI0 zero)
%{
predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
match(Set mem (StoreC mem zero));
ins_cost(125); // XXX
--- 6125,6135 ----
ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
ins_pipe(ialu_mem_imm);
%}
// Store Short/Char Immediate
! instruct storeImmC0(memory mem, immI_0 zero)
%{
predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
match(Set mem (StoreC mem zero));
ins_cost(125); // XXX
*** 6121,6131 ****
ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
ins_pipe(ialu_mem_imm);
%}
// Store Byte Immediate
! instruct storeImmB0(memory mem, immI0 zero)
%{
predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
match(Set mem (StoreB mem zero));
ins_cost(125); // XXX
--- 6151,6161 ----
ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
ins_pipe(ialu_mem_imm);
%}
// Store Byte Immediate
! instruct storeImmB0(memory mem, immI_0 zero)
%{
predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
match(Set mem (StoreB mem zero));
ins_cost(125); // XXX
*** 6146,6156 ****
ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
ins_pipe(ialu_mem_imm);
%}
// Store CMS card-mark Immediate
! instruct storeImmCM0_reg(memory mem, immI0 zero)
%{
predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
match(Set mem (StoreCM mem zero));
ins_cost(125); // XXX
--- 6176,6186 ----
ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
ins_pipe(ialu_mem_imm);
%}
// Store CMS card-mark Immediate
! instruct storeImmCM0_reg(memory mem, immI_0 zero)
%{
predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
match(Set mem (StoreCM mem zero));
ins_cost(125); // XXX
*** 6159,6169 ****
__ movb($mem$$Address, r12);
%}
ins_pipe(ialu_mem_reg);
%}
! instruct storeImmCM0(memory mem, immI0 src)
%{
match(Set mem (StoreCM mem src));
ins_cost(150); // XXX
format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
--- 6189,6199 ----
__ movb($mem$$Address, r12);
%}
ins_pipe(ialu_mem_reg);
%}
! instruct storeImmCM0(memory mem, immI_0 src)
%{
match(Set mem (StoreCM mem src));
ins_cost(150); // XXX
format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
*** 7251,7261 ****
opcode(0x81); /* Opcode 81 /0 id */
ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
ins_pipe(ialu_mem_imm);
%}
! instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
%{
predicate(UseIncDec);
match(Set dst (AddI dst src));
effect(KILL cr);
--- 7281,7291 ----
opcode(0x81); /* Opcode 81 /0 id */
ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
ins_pipe(ialu_mem_imm);
%}
! instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
%{
predicate(UseIncDec);
match(Set dst (AddI dst src));
effect(KILL cr);
*** 7263,7273 ****
opcode(0xFF, 0x00); // FF /0
ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
! instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
%{
predicate(UseIncDec);
match(Set dst (StoreI dst (AddI (LoadI dst) src)));
effect(KILL cr);
--- 7293,7303 ----
opcode(0xFF, 0x00); // FF /0
ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
! instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr)
%{
predicate(UseIncDec);
match(Set dst (StoreI dst (AddI (LoadI dst) src)));
effect(KILL cr);
*** 8157,8189 ****
ins_pipe(ialu_mem_imm);
%}
// Subtract from a pointer
// XXX hmpf???
! instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
%{
match(Set dst (AddP dst (SubI zero src)));
effect(KILL cr);
format %{ "subq $dst, $src\t# ptr - int" %}
opcode(0x2B);
ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
ins_pipe(ialu_reg_reg);
%}
! instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
%{
match(Set dst (SubI zero dst));
effect(KILL cr);
format %{ "negl $dst\t# int" %}
opcode(0xF7, 0x03); // Opcode F7 /3
ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
! instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
%{
match(Set dst (StoreI dst (SubI zero (LoadI dst))));
effect(KILL cr);
format %{ "negl $dst\t# int" %}
--- 8187,8231 ----
ins_pipe(ialu_mem_imm);
%}
// Subtract from a pointer
// XXX hmpf???
! instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
%{
match(Set dst (AddP dst (SubI zero src)));
effect(KILL cr);
format %{ "subq $dst, $src\t# ptr - int" %}
opcode(0x2B);
ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
ins_pipe(ialu_reg_reg);
%}
! instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr)
%{
match(Set dst (SubI zero dst));
effect(KILL cr);
format %{ "negl $dst\t# int" %}
opcode(0xF7, 0x03); // Opcode F7 /3
ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
! instruct negI_rReg_2(rRegI dst, rFlagsReg cr)
! %{
! match(Set dst (NegI dst));
! effect(KILL cr);
!
! format %{ "negl $dst\t# int" %}
! ins_encode %{
! __ negl($dst$$Register);
! %}
! ins_pipe(ialu_reg);
! %}
!
! instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr)
%{
match(Set dst (StoreI dst (SubI zero (LoadI dst))));
effect(KILL cr);
format %{ "negl $dst\t# int" %}
*** 8201,8210 ****
--- 8243,8264 ----
opcode(0xF7, 0x03); // Opcode F7 /3
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
+ instruct negL_rReg_2(rRegL dst, rFlagsReg cr)
+ %{
+ match(Set dst (NegL dst));
+ effect(KILL cr);
+
+ format %{ "negq $dst\t# int" %}
+ ins_encode %{
+ __ negq($dst$$Register);
+ %}
+ ins_pipe(ialu_reg);
+ %}
+
instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
%{
match(Set dst (StoreL dst (SubL zero (LoadL dst))));
effect(KILL cr);
*** 8526,8536 ****
ins_pipe(ialu_reg_reg_alu0);
%}
// Integer Shift Instructions
// Shift Left by one
! instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
%{
match(Set dst (LShiftI dst shift));
effect(KILL cr);
format %{ "sall $dst, $shift" %}
--- 8580,8590 ----
ins_pipe(ialu_reg_reg_alu0);
%}
// Integer Shift Instructions
// Shift Left by one
! instruct salI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (LShiftI dst shift));
effect(KILL cr);
format %{ "sall $dst, $shift" %}
*** 8538,8548 ****
ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
// Shift Left by one
! instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
%{
match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
effect(KILL cr);
format %{ "sall $dst, $shift\t" %}
--- 8592,8602 ----
ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
// Shift Left by one
! instruct salI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
effect(KILL cr);
format %{ "sall $dst, $shift\t" %}
*** 8598,8608 ****
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
ins_pipe(ialu_mem_reg);
%}
// Arithmetic shift right by one
! instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
%{
match(Set dst (RShiftI dst shift));
effect(KILL cr);
format %{ "sarl $dst, $shift" %}
--- 8652,8662 ----
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
ins_pipe(ialu_mem_reg);
%}
// Arithmetic shift right by one
! instruct sarI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (RShiftI dst shift));
effect(KILL cr);
format %{ "sarl $dst, $shift" %}
*** 8610,8620 ****
ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
// Arithmetic shift right by one
! instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
%{
match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
effect(KILL cr);
format %{ "sarl $dst, $shift" %}
--- 8664,8674 ----
ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
// Arithmetic shift right by one
! instruct sarI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
effect(KILL cr);
format %{ "sarl $dst, $shift" %}
*** 8670,8680 ****
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
ins_pipe(ialu_mem_reg);
%}
// Logical shift right by one
! instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
%{
match(Set dst (URShiftI dst shift));
effect(KILL cr);
format %{ "shrl $dst, $shift" %}
--- 8724,8734 ----
ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
ins_pipe(ialu_mem_reg);
%}
// Logical shift right by one
! instruct shrI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (URShiftI dst shift));
effect(KILL cr);
format %{ "shrl $dst, $shift" %}
*** 8682,8692 ****
ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
// Logical shift right by one
! instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
%{
match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
effect(KILL cr);
format %{ "shrl $dst, $shift" %}
--- 8736,8746 ----
ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
// Logical shift right by one
! instruct shrI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
effect(KILL cr);
format %{ "shrl $dst, $shift" %}
*** 8743,8753 ****
ins_pipe(ialu_mem_reg);
%}
// Long Shift Instructions
// Shift Left by one
! instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
%{
match(Set dst (LShiftL dst shift));
effect(KILL cr);
format %{ "salq $dst, $shift" %}
--- 8797,8807 ----
ins_pipe(ialu_mem_reg);
%}
// Long Shift Instructions
// Shift Left by one
! instruct salL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (LShiftL dst shift));
effect(KILL cr);
format %{ "salq $dst, $shift" %}
*** 8755,8765 ****
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
// Shift Left by one
! instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
%{
match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
effect(KILL cr);
format %{ "salq $dst, $shift" %}
--- 8809,8819 ----
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
// Shift Left by one
! instruct salL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
effect(KILL cr);
format %{ "salq $dst, $shift" %}
*** 8816,8826 ****
ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
ins_pipe(ialu_mem_reg);
%}
// Arithmetic shift right by one
! instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
%{
match(Set dst (RShiftL dst shift));
effect(KILL cr);
format %{ "sarq $dst, $shift" %}
--- 8870,8880 ----
ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
ins_pipe(ialu_mem_reg);
%}
// Arithmetic shift right by one
! instruct sarL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (RShiftL dst shift));
effect(KILL cr);
format %{ "sarq $dst, $shift" %}
*** 8828,8838 ****
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
// Arithmetic shift right by one
! instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
%{
match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
effect(KILL cr);
format %{ "sarq $dst, $shift" %}
--- 8882,8892 ----
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
ins_pipe(ialu_reg);
%}
// Arithmetic shift right by one
! instruct sarL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
effect(KILL cr);
format %{ "sarq $dst, $shift" %}
*** 8889,8899 ****
ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
ins_pipe(ialu_mem_reg);
%}
// Logical shift right by one
! instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
%{
match(Set dst (URShiftL dst shift));
effect(KILL cr);
format %{ "shrq $dst, $shift" %}
--- 8943,8953 ----
ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
ins_pipe(ialu_mem_reg);
%}
// Logical shift right by one
! instruct shrL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (URShiftL dst shift));
effect(KILL cr);
format %{ "shrq $dst, $shift" %}
*** 8901,8911 ****
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
ins_pipe(ialu_reg);
%}
// Logical shift right by one
! instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
%{
match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
effect(KILL cr);
format %{ "shrq $dst, $shift" %}
--- 8955,8965 ----
ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
ins_pipe(ialu_reg);
%}
// Logical shift right by one
! instruct shrL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
%{
match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
effect(KILL cr);
format %{ "shrq $dst, $shift" %}
*** 9019,9029 ****
ins_pipe(ialu_reg_reg);
%}
// end of ROL expand
// Rotate Left by one
! instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
%{
match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
expand %{
rolI_rReg_imm1(dst, cr);
--- 9073,9083 ----
ins_pipe(ialu_reg_reg);
%}
// end of ROL expand
// Rotate Left by one
! instruct rolI_rReg_i1(rRegI dst, immI_1 lshift, immI_M1 rshift, rFlagsReg cr)
%{
match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
expand %{
rolI_rReg_imm1(dst, cr);
*** 9040,9050 ****
rolI_rReg_imm8(dst, lshift, cr);
%}
%}
// Rotate Left by variable
! instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
%{
match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
expand %{
rolI_rReg_CL(dst, shift, cr);
--- 9094,9104 ----
rolI_rReg_imm8(dst, lshift, cr);
%}
%}
// Rotate Left by variable
! instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
%{
match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
expand %{
rolI_rReg_CL(dst, shift, cr);
*** 9092,9102 ****
ins_pipe(ialu_reg_reg);
%}
// end of ROR expand
// Rotate Right by one
! instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
%{
match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
expand %{
rorI_rReg_imm1(dst, cr);
--- 9146,9156 ----
ins_pipe(ialu_reg_reg);
%}
// end of ROR expand
// Rotate Right by one
! instruct rorI_rReg_i1(rRegI dst, immI_1 rshift, immI_M1 lshift, rFlagsReg cr)
%{
match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
expand %{
rorI_rReg_imm1(dst, cr);
*** 9113,9123 ****
rorI_rReg_imm8(dst, rshift, cr);
%}
%}
// Rotate Right by variable
! instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
%{
match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
expand %{
rorI_rReg_CL(dst, shift, cr);
--- 9167,9177 ----
rorI_rReg_imm8(dst, rshift, cr);
%}
%}
// Rotate Right by variable
! instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
%{
match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
expand %{
rorI_rReg_CL(dst, shift, cr);
*** 9164,9174 ****
ins_pipe(ialu_reg_reg);
%}
// end of ROL expand
// Rotate Left by one
! instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
%{
match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
expand %{
rolL_rReg_imm1(dst, cr);
--- 9218,9228 ----
ins_pipe(ialu_reg_reg);
%}
// end of ROL expand
// Rotate Left by one
! instruct rolL_rReg_i1(rRegL dst, immI_1 lshift, immI_M1 rshift, rFlagsReg cr)
%{
match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
expand %{
rolL_rReg_imm1(dst, cr);
*** 9185,9195 ****
rolL_rReg_imm8(dst, lshift, cr);
%}
%}
// Rotate Left by variable
! instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
%{
match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
expand %{
rolL_rReg_CL(dst, shift, cr);
--- 9239,9249 ----
rolL_rReg_imm8(dst, lshift, cr);
%}
%}
// Rotate Left by variable
! instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
%{
match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
expand %{
rolL_rReg_CL(dst, shift, cr);
*** 9237,9247 ****
ins_pipe(ialu_reg_reg);
%}
// end of ROR expand
// Rotate Right by one
! instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
%{
match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
expand %{
rorL_rReg_imm1(dst, cr);
--- 9291,9301 ----
ins_pipe(ialu_reg_reg);
%}
// end of ROR expand
// Rotate Right by one
! instruct rorL_rReg_i1(rRegL dst, immI_1 rshift, immI_M1 lshift, rFlagsReg cr)
%{
match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
expand %{
rorL_rReg_imm1(dst, cr);
*** 9258,9268 ****
rorL_rReg_imm8(dst, rshift, cr);
%}
%}
// Rotate Right by variable
! instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
%{
match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
expand %{
rorL_rReg_CL(dst, shift, cr);
--- 9312,9322 ----
rorL_rReg_imm8(dst, rshift, cr);
%}
%}
// Rotate Right by variable
! instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
%{
match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
expand %{
rorL_rReg_CL(dst, shift, cr);
*** 9430,9440 ****
__ andnl($dst$$Register, $src1$$Register, $src2$$Register);
%}
ins_pipe(ialu_reg);
%}
! instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
match(Set dst (AndI (SubI imm_zero src) src));
predicate(UseBMI1Instructions);
effect(KILL cr);
format %{ "blsil $dst, $src" %}
--- 9484,9494 ----
__ andnl($dst$$Register, $src1$$Register, $src2$$Register);
%}
ins_pipe(ialu_reg);
%}
! instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
match(Set dst (AndI (SubI imm_zero src) src));
predicate(UseBMI1Instructions);
effect(KILL cr);
format %{ "blsil $dst, $src" %}
*** 9443,9453 ****
__ blsil($dst$$Register, $src$$Register);
%}
ins_pipe(ialu_reg);
%}
! instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
predicate(UseBMI1Instructions);
effect(KILL cr);
ins_cost(125);
--- 9497,9507 ----
__ blsil($dst$$Register, $src$$Register);
%}
ins_pipe(ialu_reg);
%}
! instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
predicate(UseBMI1Instructions);
effect(KILL cr);
ins_cost(125);
*** 10126,10136 ****
Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
neg_reg(dst));
ins_pipe(pipe_slow);
%}
! instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
%{
match(Set dst (CmpLTMask dst zero));
effect(KILL cr);
ins_cost(100);
--- 10180,10190 ----
Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
neg_reg(dst));
ins_pipe(pipe_slow);
%}
! instruct cmpLTMask0(rRegI dst, immI_0 zero, rFlagsReg cr)
%{
match(Set dst (CmpLTMask dst zero));
effect(KILL cr);
ins_cost(100);
*** 11459,11469 ****
__ cmpq($op1$$Register, $op2$$constant);
%}
ins_pipe(ialu_reg_reg);
%}
! instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
%{
match(Set cr (OverflowSubI zero op2));
effect(DEF cr, USE_KILL op2);
format %{ "negl $op2\t# overflow check int" %}
--- 11513,11523 ----
__ cmpq($op1$$Register, $op2$$constant);
%}
ins_pipe(ialu_reg_reg);
%}
! instruct overflowNegI_rReg(rFlagsReg cr, immI_0 zero, rax_RegI op2)
%{
match(Set cr (OverflowSubI zero op2));
effect(DEF cr, USE_KILL op2);
format %{ "negl $op2\t# overflow check int" %}
*** 11568,11598 ****
opcode(0x3B); /* Opcode 3B /r */
ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
ins_pipe(ialu_cr_reg_mem);
%}
! instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
%{
match(Set cr (CmpI src zero));
format %{ "testl $src, $src" %}
opcode(0x85);
ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
ins_pipe(ialu_cr_reg_imm);
%}
! instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
%{
match(Set cr (CmpI (AndI src con) zero));
format %{ "testl $src, $con" %}
opcode(0xF7, 0x00);
ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
ins_pipe(ialu_cr_reg_imm);
%}
! instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
%{
match(Set cr (CmpI (AndI src (LoadI mem)) zero));
format %{ "testl $src, $mem" %}
opcode(0x85);
--- 11622,11652 ----
opcode(0x3B); /* Opcode 3B /r */
ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
ins_pipe(ialu_cr_reg_mem);
%}
! instruct testI_reg(rFlagsReg cr, rRegI src, immI_0 zero)
%{
match(Set cr (CmpI src zero));
format %{ "testl $src, $src" %}
opcode(0x85);
ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
ins_pipe(ialu_cr_reg_imm);
%}
! instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI_0 zero)
%{
match(Set cr (CmpI (AndI src con) zero));
format %{ "testl $src, $con" %}
opcode(0xF7, 0x00);
ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
ins_pipe(ialu_cr_reg_imm);
%}
! instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI_0 zero)
%{
match(Set cr (CmpI (AndI src (LoadI mem)) zero));
format %{ "testl $src, $mem" %}
opcode(0x85);
*** 11642,11652 ****
// // ins_cost(500);
// // opcode(0x39); /* Opcode 39 /r */
// // ins_encode( OpcP, reg_mem( op1, op2) );
// //%}
! instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
%{
match(Set cr (CmpU src zero));
format %{ "testl $src, $src\t# unsigned" %}
opcode(0x85);
--- 11696,11706 ----
// // ins_cost(500);
// // opcode(0x39); /* Opcode 39 /r */
// // ins_encode( OpcP, reg_mem( op1, op2) );
// //%}
! instruct testU_reg(rFlagsRegU cr, rRegI src, immI_0 zero)
%{
match(Set cr (CmpU src zero));
format %{ "testl $src, $src\t# unsigned" %}
opcode(0x85);
*** 11981,12001 ****
format %{ "cmpb $mem, $imm" %}
ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
ins_pipe(ialu_cr_reg_mem);
%}
! instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI0 zero)
%{
match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
ins_cost(125);
format %{ "testb $mem, $imm\t# ubyte" %}
ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
ins_pipe(ialu_cr_reg_mem);
%}
! instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI0 zero)
%{
match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
ins_cost(125);
format %{ "testb $mem, $imm\t# byte" %}
--- 12035,12055 ----
format %{ "cmpb $mem, $imm" %}
ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
ins_pipe(ialu_cr_reg_mem);
%}
! instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI_0 zero)
%{
match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
ins_cost(125);
format %{ "testb $mem, $imm\t# ubyte" %}
ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
ins_pipe(ialu_cr_reg_mem);
%}
! instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero)
%{
match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
ins_cost(125);
format %{ "testb $mem, $imm\t# byte" %}
*** 12714,12724 ****
// instruct movI(rRegI dst, rRegI src)
// %{
// match(Set dst (CopyI src));
// %}
//
! // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
// %{
// match(Set dst (AddI dst src));
// effect(KILL cr);
// %}
//
--- 12768,12778 ----
// instruct movI(rRegI dst, rRegI src)
// %{
// match(Set dst (CopyI src));
// %}
//
! // instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
// %{
// match(Set dst (AddI dst src));
// effect(KILL cr);
// %}
//
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