1 //
2 // Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer/long registers
173 reg_class all_reg(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all int registers
191 reg_class all_int_reg(RAX
192 RDX,
193 RBP,
194 RDI,
195 RSI,
196 RCX,
197 RBX,
198 R8,
199 R9,
200 R10,
201 R11,
202 R12,
203 R13,
204 R14);
205
206 // Class for all pointer registers
207 reg_class any_reg %{
208 return _ANY_REG_mask;
209 %}
210
211 // Class for all pointer registers (excluding RSP)
212 reg_class ptr_reg %{
213 return _PTR_REG_mask;
214 %}
215
216 // Class for all pointer registers (excluding RSP and RBP)
217 reg_class ptr_reg_no_rbp %{
218 return _PTR_REG_NO_RBP_mask;
219 %}
220
221 // Class for all pointer registers (excluding RAX and RSP)
222 reg_class ptr_no_rax_reg %{
223 return _PTR_NO_RAX_REG_mask;
224 %}
225
226 // Class for all pointer registers (excluding RAX, RBX, and RSP)
227 reg_class ptr_no_rax_rbx_reg %{
228 return _PTR_NO_RAX_RBX_REG_mask;
229 %}
230
231 // Class for all long registers (excluding RSP)
232 reg_class long_reg %{
233 return _LONG_REG_mask;
234 %}
235
236 // Class for all long registers (excluding RAX, RDX and RSP)
237 reg_class long_no_rax_rdx_reg %{
238 return _LONG_NO_RAX_RDX_REG_mask;
239 %}
240
241 // Class for all long registers (excluding RCX and RSP)
242 reg_class long_no_rcx_reg %{
243 return _LONG_NO_RCX_REG_mask;
244 %}
245
246 // Class for all int registers (excluding RSP)
247 reg_class int_reg %{
248 return _INT_REG_mask;
249 %}
250
251 // Class for all int registers (excluding RAX, RDX, and RSP)
252 reg_class int_no_rax_rdx_reg %{
253 return _INT_NO_RAX_RDX_REG_mask;
254 %}
255
256 // Class for all int registers (excluding RCX and RSP)
257 reg_class int_no_rcx_reg %{
258 return _INT_NO_RCX_REG_mask;
259 %}
260
261 // Singleton class for RAX pointer register
262 reg_class ptr_rax_reg(RAX, RAX_H);
263
264 // Singleton class for RBX pointer register
265 reg_class ptr_rbx_reg(RBX, RBX_H);
266
267 // Singleton class for RSI pointer register
268 reg_class ptr_rsi_reg(RSI, RSI_H);
269
270 // Singleton class for RBP pointer register
271 reg_class ptr_rbp_reg(RBP, RBP_H);
272
273 // Singleton class for RDI pointer register
274 reg_class ptr_rdi_reg(RDI, RDI_H);
275
276 // Singleton class for stack pointer
277 reg_class ptr_rsp_reg(RSP, RSP_H);
278
279 // Singleton class for TLS pointer
280 reg_class ptr_r15_reg(R15, R15_H);
281
282 // Singleton class for RAX long register
283 reg_class long_rax_reg(RAX, RAX_H);
284
285 // Singleton class for RCX long register
286 reg_class long_rcx_reg(RCX, RCX_H);
287
288 // Singleton class for RDX long register
289 reg_class long_rdx_reg(RDX, RDX_H);
290
291 // Singleton class for RAX int register
292 reg_class int_rax_reg(RAX);
293
294 // Singleton class for RBX int register
295 reg_class int_rbx_reg(RBX);
296
297 // Singleton class for RCX int register
298 reg_class int_rcx_reg(RCX);
299
300 // Singleton class for RCX int register
301 reg_class int_rdx_reg(RDX);
302
303 // Singleton class for RCX int register
304 reg_class int_rdi_reg(RDI);
305
306 // Singleton class for instruction pointer
307 // reg_class ip_reg(RIP);
308
309 %}
310
311 //----------SOURCE BLOCK-------------------------------------------------------
312 // This is a block of C++ code which provides values, functions, and
313 // definitions necessary in the rest of the architecture description
314 source_hpp %{
315
316 extern RegMask _ANY_REG_mask;
317 extern RegMask _PTR_REG_mask;
318 extern RegMask _PTR_REG_NO_RBP_mask;
319 extern RegMask _PTR_NO_RAX_REG_mask;
320 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
321 extern RegMask _LONG_REG_mask;
322 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
323 extern RegMask _LONG_NO_RCX_REG_mask;
324 extern RegMask _INT_REG_mask;
325 extern RegMask _INT_NO_RAX_RDX_REG_mask;
326 extern RegMask _INT_NO_RCX_REG_mask;
327
328 extern RegMask _STACK_OR_PTR_REG_mask;
329 extern RegMask _STACK_OR_LONG_REG_mask;
330 extern RegMask _STACK_OR_INT_REG_mask;
331
332 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
333 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
334 inline const RegMask& STACK_OR_INT_REG_mask() { return _STACK_OR_INT_REG_mask; }
335
336 %}
337
338 source %{
339 #define RELOC_IMM64 Assembler::imm_operand
340 #define RELOC_DISP32 Assembler::disp32_operand
341
342 #define __ _masm.
343
344 RegMask _ANY_REG_mask;
345 RegMask _PTR_REG_mask;
346 RegMask _PTR_REG_NO_RBP_mask;
347 RegMask _PTR_NO_RAX_REG_mask;
348 RegMask _PTR_NO_RAX_RBX_REG_mask;
349 RegMask _LONG_REG_mask;
350 RegMask _LONG_NO_RAX_RDX_REG_mask;
351 RegMask _LONG_NO_RCX_REG_mask;
352 RegMask _INT_REG_mask;
353 RegMask _INT_NO_RAX_RDX_REG_mask;
354 RegMask _INT_NO_RCX_REG_mask;
355 RegMask _STACK_OR_PTR_REG_mask;
356 RegMask _STACK_OR_LONG_REG_mask;
357 RegMask _STACK_OR_INT_REG_mask;
358
359 static bool need_r12_heapbase() {
360 return UseCompressedOops || UseCompressedClassPointers;
361 }
362
363 void reg_mask_init() {
364 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
365 // We derive a number of subsets from it.
366 _ANY_REG_mask = _ALL_REG_mask;
367
368 if (PreserveFramePointer) {
369 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
370 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
371 }
372 if (need_r12_heapbase()) {
373 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
374 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
375 }
376
377 _PTR_REG_mask = _ANY_REG_mask;
378 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
379 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
380 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
381 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
382
383 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
384 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
385
386 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
387 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
388 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
389
390 _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
391 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
392 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
393
394 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
395 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
396 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
397
398 _LONG_REG_mask = _PTR_REG_mask;
399 _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
400 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
401
402 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
403 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
404 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
405 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
406 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
407
408 _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
409 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
410 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
411
412 _INT_REG_mask = _ALL_INT_REG_mask;
413 if (PreserveFramePointer) {
414 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
415 }
416 if (need_r12_heapbase()) {
417 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
418 }
419
420 _STACK_OR_INT_REG_mask = _INT_REG_mask;
421 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
422
423 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
424 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
425 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
426
427 _INT_NO_RCX_REG_mask = _INT_REG_mask;
428 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
429 }
430
431 static bool generate_vzeroupper(Compile* C) {
432 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
433 }
434
435 static int clear_avx_size() {
436 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
437 }
438
439 // !!!!! Special hack to get all types of calls to specify the byte offset
440 // from the start of the call to the point where the return address
441 // will point.
442 int MachCallStaticJavaNode::ret_addr_offset()
443 {
444 int offset = 5; // 5 bytes from start of call to where return address points
445 offset += clear_avx_size();
446 return offset;
447 }
448
449 int MachCallDynamicJavaNode::ret_addr_offset()
450 {
451 int offset = 15; // 15 bytes from start of call to where return address points
452 offset += clear_avx_size();
453 return offset;
454 }
455
456 int MachCallRuntimeNode::ret_addr_offset() {
457 int offset = 13; // movq r10,#addr; callq (r10)
458 offset += clear_avx_size();
459 return offset;
460 }
461
462 //
463 // Compute padding required for nodes which need alignment
464 //
465
466 // The address of the call instruction needs to be 4-byte aligned to
467 // ensure that it does not span a cache line so that it can be patched.
468 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
469 {
470 current_offset += clear_avx_size(); // skip vzeroupper
471 current_offset += 1; // skip call opcode byte
472 return align_up(current_offset, alignment_required()) - current_offset;
473 }
474
475 // The address of the call instruction needs to be 4-byte aligned to
476 // ensure that it does not span a cache line so that it can be patched.
477 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
478 {
479 current_offset += clear_avx_size(); // skip vzeroupper
480 current_offset += 11; // skip movq instruction + call opcode byte
481 return align_up(current_offset, alignment_required()) - current_offset;
482 }
483
484 // EMIT_RM()
485 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
486 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
487 cbuf.insts()->emit_int8(c);
488 }
489
490 // EMIT_CC()
491 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
492 unsigned char c = (unsigned char) (f1 | f2);
493 cbuf.insts()->emit_int8(c);
494 }
495
496 // EMIT_OPCODE()
497 void emit_opcode(CodeBuffer &cbuf, int code) {
498 cbuf.insts()->emit_int8((unsigned char) code);
499 }
500
501 // EMIT_OPCODE() w/ relocation information
502 void emit_opcode(CodeBuffer &cbuf,
503 int code, relocInfo::relocType reloc, int offset, int format)
504 {
505 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
506 emit_opcode(cbuf, code);
507 }
508
509 // EMIT_D8()
510 void emit_d8(CodeBuffer &cbuf, int d8) {
511 cbuf.insts()->emit_int8((unsigned char) d8);
512 }
513
514 // EMIT_D16()
515 void emit_d16(CodeBuffer &cbuf, int d16) {
516 cbuf.insts()->emit_int16(d16);
517 }
518
519 // EMIT_D32()
520 void emit_d32(CodeBuffer &cbuf, int d32) {
521 cbuf.insts()->emit_int32(d32);
522 }
523
524 // EMIT_D64()
525 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
526 cbuf.insts()->emit_int64(d64);
527 }
528
529 // emit 32 bit value and construct relocation entry from relocInfo::relocType
530 void emit_d32_reloc(CodeBuffer& cbuf,
531 int d32,
532 relocInfo::relocType reloc,
533 int format)
534 {
535 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
536 cbuf.relocate(cbuf.insts_mark(), reloc, format);
537 cbuf.insts()->emit_int32(d32);
538 }
539
540 // emit 32 bit value and construct relocation entry from RelocationHolder
541 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
542 #ifdef ASSERT
543 if (rspec.reloc()->type() == relocInfo::oop_type &&
544 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
545 assert(Universe::heap()->is_in((address)(intptr_t)d32), "should be real oop");
546 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)), "cannot embed broken oops in code");
547 }
548 #endif
549 cbuf.relocate(cbuf.insts_mark(), rspec, format);
550 cbuf.insts()->emit_int32(d32);
551 }
552
553 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
554 address next_ip = cbuf.insts_end() + 4;
555 emit_d32_reloc(cbuf, (int) (addr - next_ip),
556 external_word_Relocation::spec(addr),
557 RELOC_DISP32);
558 }
559
560
561 // emit 64 bit value and construct relocation entry from relocInfo::relocType
562 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
563 cbuf.relocate(cbuf.insts_mark(), reloc, format);
564 cbuf.insts()->emit_int64(d64);
565 }
566
567 // emit 64 bit value and construct relocation entry from RelocationHolder
568 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
569 #ifdef ASSERT
570 if (rspec.reloc()->type() == relocInfo::oop_type &&
571 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
572 assert(Universe::heap()->is_in((address)d64), "should be real oop");
573 assert(oopDesc::is_oop(cast_to_oop(d64)), "cannot embed broken oops in code");
574 }
575 #endif
576 cbuf.relocate(cbuf.insts_mark(), rspec, format);
577 cbuf.insts()->emit_int64(d64);
578 }
579
580 // Access stack slot for load or store
581 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
582 {
583 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
584 if (-0x80 <= disp && disp < 0x80) {
585 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
586 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
587 emit_d8(cbuf, disp); // Displacement // R/M byte
588 } else {
589 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
590 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
591 emit_d32(cbuf, disp); // Displacement // R/M byte
592 }
593 }
594
595 // rRegI ereg, memory mem) %{ // emit_reg_mem
596 void encode_RegMem(CodeBuffer &cbuf,
597 int reg,
598 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
599 {
600 assert(disp_reloc == relocInfo::none, "cannot have disp");
601 int regenc = reg & 7;
602 int baseenc = base & 7;
603 int indexenc = index & 7;
604
605 // There is no index & no scale, use form without SIB byte
606 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
607 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
608 if (disp == 0 && base != RBP_enc && base != R13_enc) {
609 emit_rm(cbuf, 0x0, regenc, baseenc); // *
610 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
611 // If 8-bit displacement, mode 0x1
612 emit_rm(cbuf, 0x1, regenc, baseenc); // *
613 emit_d8(cbuf, disp);
614 } else {
615 // If 32-bit displacement
616 if (base == -1) { // Special flag for absolute address
617 emit_rm(cbuf, 0x0, regenc, 0x5); // *
618 if (disp_reloc != relocInfo::none) {
619 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
620 } else {
621 emit_d32(cbuf, disp);
622 }
623 } else {
624 // Normal base + offset
625 emit_rm(cbuf, 0x2, regenc, baseenc); // *
626 if (disp_reloc != relocInfo::none) {
627 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
628 } else {
629 emit_d32(cbuf, disp);
630 }
631 }
632 }
633 } else {
634 // Else, encode with the SIB byte
635 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
636 if (disp == 0 && base != RBP_enc && base != R13_enc) {
637 // If no displacement
638 emit_rm(cbuf, 0x0, regenc, 0x4); // *
639 emit_rm(cbuf, scale, indexenc, baseenc);
640 } else {
641 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
642 // If 8-bit displacement, mode 0x1
643 emit_rm(cbuf, 0x1, regenc, 0x4); // *
644 emit_rm(cbuf, scale, indexenc, baseenc);
645 emit_d8(cbuf, disp);
646 } else {
647 // If 32-bit displacement
648 if (base == 0x04 ) {
649 emit_rm(cbuf, 0x2, regenc, 0x4);
650 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
651 } else {
652 emit_rm(cbuf, 0x2, regenc, 0x4);
653 emit_rm(cbuf, scale, indexenc, baseenc); // *
654 }
655 if (disp_reloc != relocInfo::none) {
656 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
657 } else {
658 emit_d32(cbuf, disp);
659 }
660 }
661 }
662 }
663 }
664
665 // This could be in MacroAssembler but it's fairly C2 specific
666 void emit_cmpfp_fixup(MacroAssembler& _masm) {
667 Label exit;
668 __ jccb(Assembler::noParity, exit);
669 __ pushf();
670 //
671 // comiss/ucomiss instructions set ZF,PF,CF flags and
672 // zero OF,AF,SF for NaN values.
673 // Fixup flags by zeroing ZF,PF so that compare of NaN
674 // values returns 'less than' result (CF is set).
675 // Leave the rest of flags unchanged.
676 //
677 // 7 6 5 4 3 2 1 0
678 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
679 // 0 0 1 0 1 0 1 1 (0x2B)
680 //
681 __ andq(Address(rsp, 0), 0xffffff2b);
682 __ popf();
683 __ bind(exit);
684 }
685
686 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
687 Label done;
688 __ movl(dst, -1);
689 __ jcc(Assembler::parity, done);
690 __ jcc(Assembler::below, done);
691 __ setb(Assembler::notEqual, dst);
692 __ movzbl(dst, dst);
693 __ bind(done);
694 }
695
696 // Math.min() # Math.max()
697 // --------------------------
698 // ucomis[s/d] #
699 // ja -> b # a
700 // jp -> NaN # NaN
701 // jb -> a # b
702 // je #
703 // |-jz -> a | b # a & b
704 // | -> a #
705 void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst,
706 XMMRegister a, XMMRegister b,
707 XMMRegister xmmt, Register rt,
708 bool min, bool single) {
709
710 Label nan, zero, below, above, done;
711
712 if (single)
713 __ ucomiss(a, b);
714 else
715 __ ucomisd(a, b);
716
717 if (dst->encoding() != (min ? b : a)->encoding())
718 __ jccb(Assembler::above, above); // CF=0 & ZF=0
719 else
720 __ jccb(Assembler::above, done);
721
722 __ jccb(Assembler::parity, nan); // PF=1
723 __ jccb(Assembler::below, below); // CF=1
724
725 // equal
726 __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
727 if (single) {
728 __ ucomiss(a, xmmt);
729 __ jccb(Assembler::equal, zero);
730
731 __ movflt(dst, a);
732 __ jmp(done);
733 }
734 else {
735 __ ucomisd(a, xmmt);
736 __ jccb(Assembler::equal, zero);
737
738 __ movdbl(dst, a);
739 __ jmp(done);
740 }
741
742 __ bind(zero);
743 if (min)
744 __ vpor(dst, a, b, Assembler::AVX_128bit);
745 else
746 __ vpand(dst, a, b, Assembler::AVX_128bit);
747
748 __ jmp(done);
749
750 __ bind(above);
751 if (single)
752 __ movflt(dst, min ? b : a);
753 else
754 __ movdbl(dst, min ? b : a);
755
756 __ jmp(done);
757
758 __ bind(nan);
759 if (single) {
760 __ movl(rt, 0x7fc00000); // Float.NaN
761 __ movdl(dst, rt);
762 }
763 else {
764 __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
765 __ movdq(dst, rt);
766 }
767 __ jmp(done);
768
769 __ bind(below);
770 if (single)
771 __ movflt(dst, min ? a : b);
772 else
773 __ movdbl(dst, min ? a : b);
774
775 __ bind(done);
776 }
777
778 //=============================================================================
779 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
780
781 int ConstantTable::calculate_table_base_offset() const {
782 return 0; // absolute addressing, no offset
783 }
784
785 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
786 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
787 ShouldNotReachHere();
788 }
789
790 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
791 // Empty encoding
792 }
793
794 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
795 return 0;
796 }
797
798 #ifndef PRODUCT
799 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
800 st->print("# MachConstantBaseNode (empty encoding)");
801 }
802 #endif
803
804
805 //=============================================================================
806 #ifndef PRODUCT
807 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
808 Compile* C = ra_->C;
809
810 int framesize = C->output()->frame_size_in_bytes();
811 int bangsize = C->output()->bang_size_in_bytes();
812 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
813 // Remove wordSize for return addr which is already pushed.
814 framesize -= wordSize;
815
816 if (C->output()->need_stack_bang(bangsize)) {
817 framesize -= wordSize;
818 st->print("# stack bang (%d bytes)", bangsize);
819 st->print("\n\t");
820 st->print("pushq rbp\t# Save rbp");
821 if (PreserveFramePointer) {
822 st->print("\n\t");
823 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
824 }
825 if (framesize) {
826 st->print("\n\t");
827 st->print("subq rsp, #%d\t# Create frame",framesize);
828 }
829 } else {
830 st->print("subq rsp, #%d\t# Create frame",framesize);
831 st->print("\n\t");
832 framesize -= wordSize;
833 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
834 if (PreserveFramePointer) {
835 st->print("\n\t");
836 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
837 if (framesize > 0) {
838 st->print("\n\t");
839 st->print("addq rbp, #%d", framesize);
840 }
841 }
842 }
843
844 if (VerifyStackAtCalls) {
845 st->print("\n\t");
846 framesize -= wordSize;
847 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
848 #ifdef ASSERT
849 st->print("\n\t");
850 st->print("# stack alignment check");
851 #endif
852 }
853 if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
854 st->print("\n\t");
855 st->print("cmpl [r15_thread + #disarmed_offset], #disarmed_value\t");
856 st->print("\n\t");
857 st->print("je fast_entry\t");
858 st->print("\n\t");
859 st->print("call #nmethod_entry_barrier_stub\t");
860 st->print("\n\tfast_entry:");
861 }
862 st->cr();
863 }
864 #endif
865
866 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
867 Compile* C = ra_->C;
868 MacroAssembler _masm(&cbuf);
869
870 int framesize = C->output()->frame_size_in_bytes();
871 int bangsize = C->output()->bang_size_in_bytes();
872
873 if (C->clinit_barrier_on_entry()) {
874 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
875 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
876
877 Label L_skip_barrier;
878 Register klass = rscratch1;
879
880 __ mov_metadata(klass, C->method()->holder()->constant_encoding());
881 __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
882
883 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
884
885 __ bind(L_skip_barrier);
886 }
887
888 __ verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL);
889
890 C->output()->set_frame_complete(cbuf.insts_size());
891
892 if (C->has_mach_constant_base_node()) {
893 // NOTE: We set the table base offset here because users might be
894 // emitted before MachConstantBaseNode.
895 ConstantTable& constant_table = C->output()->constant_table();
896 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
897 }
898 }
899
900 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
901 {
902 return MachNode::size(ra_); // too many variables; just compute it
903 // the hard way
904 }
905
906 int MachPrologNode::reloc() const
907 {
908 return 0; // a large enough number
909 }
910
911 //=============================================================================
912 #ifndef PRODUCT
913 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
914 {
915 Compile* C = ra_->C;
916 if (generate_vzeroupper(C)) {
917 st->print("vzeroupper");
918 st->cr(); st->print("\t");
919 }
920
921 int framesize = C->output()->frame_size_in_bytes();
922 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
923 // Remove word for return adr already pushed
924 // and RBP
925 framesize -= 2*wordSize;
926
927 if (framesize) {
928 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
929 st->print("\t");
930 }
931
932 st->print_cr("popq rbp");
933 if (do_polling() && C->is_method_compilation()) {
934 st->print("\t");
935 st->print_cr("movq rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
936 "testl rax, [rscratch1]\t"
937 "# Safepoint: poll for GC");
938 }
939 }
940 #endif
941
942 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
943 {
944 Compile* C = ra_->C;
945 MacroAssembler _masm(&cbuf);
946
947 if (generate_vzeroupper(C)) {
948 // Clear upper bits of YMM registers when current compiled code uses
949 // wide vectors to avoid AVX <-> SSE transition penalty during call.
950 __ vzeroupper();
951 }
952
953 int framesize = C->output()->frame_size_in_bytes();
954 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
955 // Remove word for return adr already pushed
956 // and RBP
957 framesize -= 2*wordSize;
958
959 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
960
961 if (framesize) {
962 emit_opcode(cbuf, Assembler::REX_W);
963 if (framesize < 0x80) {
964 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
965 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
966 emit_d8(cbuf, framesize);
967 } else {
968 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
969 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
970 emit_d32(cbuf, framesize);
971 }
972 }
973
974 // popq rbp
975 emit_opcode(cbuf, 0x58 | RBP_enc);
976
977 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
978 __ reserved_stack_check();
979 }
980
981 if (do_polling() && C->is_method_compilation()) {
982 MacroAssembler _masm(&cbuf);
983 __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
984 __ relocate(relocInfo::poll_return_type);
985 __ testl(rax, Address(rscratch1, 0));
986 }
987 }
988
989 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
990 {
991 return MachNode::size(ra_); // too many variables; just compute it
992 // the hard way
993 }
994
995 int MachEpilogNode::reloc() const
996 {
997 return 2; // a large enough number
998 }
999
1000 const Pipeline* MachEpilogNode::pipeline() const
1001 {
1002 return MachNode::pipeline_class();
1003 }
1004
1005 //=============================================================================
1006
1007 enum RC {
1008 rc_bad,
1009 rc_int,
1010 rc_float,
1011 rc_stack
1012 };
1013
1014 static enum RC rc_class(OptoReg::Name reg)
1015 {
1016 if( !OptoReg::is_valid(reg) ) return rc_bad;
1017
1018 if (OptoReg::is_stack(reg)) return rc_stack;
1019
1020 VMReg r = OptoReg::as_VMReg(reg);
1021
1022 if (r->is_Register()) return rc_int;
1023
1024 assert(r->is_XMMRegister(), "must be");
1025 return rc_float;
1026 }
1027
1028 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1029 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1030 int src_hi, int dst_hi, uint ireg, outputStream* st);
1031
1032 int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1033 int stack_offset, int reg, uint ireg, outputStream* st);
1034
1035 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1036 int dst_offset, uint ireg, outputStream* st) {
1037 if (cbuf) {
1038 MacroAssembler _masm(cbuf);
1039 switch (ireg) {
1040 case Op_VecS:
1041 __ movq(Address(rsp, -8), rax);
1042 __ movl(rax, Address(rsp, src_offset));
1043 __ movl(Address(rsp, dst_offset), rax);
1044 __ movq(rax, Address(rsp, -8));
1045 break;
1046 case Op_VecD:
1047 __ pushq(Address(rsp, src_offset));
1048 __ popq (Address(rsp, dst_offset));
1049 break;
1050 case Op_VecX:
1051 __ pushq(Address(rsp, src_offset));
1052 __ popq (Address(rsp, dst_offset));
1053 __ pushq(Address(rsp, src_offset+8));
1054 __ popq (Address(rsp, dst_offset+8));
1055 break;
1056 case Op_VecY:
1057 __ vmovdqu(Address(rsp, -32), xmm0);
1058 __ vmovdqu(xmm0, Address(rsp, src_offset));
1059 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1060 __ vmovdqu(xmm0, Address(rsp, -32));
1061 break;
1062 case Op_VecZ:
1063 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1064 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1065 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1066 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1067 break;
1068 default:
1069 ShouldNotReachHere();
1070 }
1071 #ifndef PRODUCT
1072 } else {
1073 switch (ireg) {
1074 case Op_VecS:
1075 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1076 "movl rax, [rsp + #%d]\n\t"
1077 "movl [rsp + #%d], rax\n\t"
1078 "movq rax, [rsp - #8]",
1079 src_offset, dst_offset);
1080 break;
1081 case Op_VecD:
1082 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1083 "popq [rsp + #%d]",
1084 src_offset, dst_offset);
1085 break;
1086 case Op_VecX:
1087 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1088 "popq [rsp + #%d]\n\t"
1089 "pushq [rsp + #%d]\n\t"
1090 "popq [rsp + #%d]",
1091 src_offset, dst_offset, src_offset+8, dst_offset+8);
1092 break;
1093 case Op_VecY:
1094 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1095 "vmovdqu xmm0, [rsp + #%d]\n\t"
1096 "vmovdqu [rsp + #%d], xmm0\n\t"
1097 "vmovdqu xmm0, [rsp - #32]",
1098 src_offset, dst_offset);
1099 break;
1100 case Op_VecZ:
1101 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1102 "vmovdqu xmm0, [rsp + #%d]\n\t"
1103 "vmovdqu [rsp + #%d], xmm0\n\t"
1104 "vmovdqu xmm0, [rsp - #64]",
1105 src_offset, dst_offset);
1106 break;
1107 default:
1108 ShouldNotReachHere();
1109 }
1110 #endif
1111 }
1112 }
1113
1114 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1115 PhaseRegAlloc* ra_,
1116 bool do_size,
1117 outputStream* st) const {
1118 assert(cbuf != NULL || st != NULL, "sanity");
1119 // Get registers to move
1120 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1121 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1122 OptoReg::Name dst_second = ra_->get_reg_second(this);
1123 OptoReg::Name dst_first = ra_->get_reg_first(this);
1124
1125 enum RC src_second_rc = rc_class(src_second);
1126 enum RC src_first_rc = rc_class(src_first);
1127 enum RC dst_second_rc = rc_class(dst_second);
1128 enum RC dst_first_rc = rc_class(dst_first);
1129
1130 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1131 "must move at least 1 register" );
1132
1133 if (src_first == dst_first && src_second == dst_second) {
1134 // Self copy, no move
1135 return 0;
1136 }
1137 if (bottom_type()->isa_vect() != NULL) {
1138 uint ireg = ideal_reg();
1139 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1140 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1141 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1142 // mem -> mem
1143 int src_offset = ra_->reg2offset(src_first);
1144 int dst_offset = ra_->reg2offset(dst_first);
1145 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1146 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1147 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1148 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1149 int stack_offset = ra_->reg2offset(dst_first);
1150 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1151 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1152 int stack_offset = ra_->reg2offset(src_first);
1153 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1154 } else {
1155 ShouldNotReachHere();
1156 }
1157 return 0;
1158 }
1159 if (src_first_rc == rc_stack) {
1160 // mem ->
1161 if (dst_first_rc == rc_stack) {
1162 // mem -> mem
1163 assert(src_second != dst_first, "overlap");
1164 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1165 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1166 // 64-bit
1167 int src_offset = ra_->reg2offset(src_first);
1168 int dst_offset = ra_->reg2offset(dst_first);
1169 if (cbuf) {
1170 MacroAssembler _masm(cbuf);
1171 __ pushq(Address(rsp, src_offset));
1172 __ popq (Address(rsp, dst_offset));
1173 #ifndef PRODUCT
1174 } else {
1175 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1176 "popq [rsp + #%d]",
1177 src_offset, dst_offset);
1178 #endif
1179 }
1180 } else {
1181 // 32-bit
1182 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1183 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1184 // No pushl/popl, so:
1185 int src_offset = ra_->reg2offset(src_first);
1186 int dst_offset = ra_->reg2offset(dst_first);
1187 if (cbuf) {
1188 MacroAssembler _masm(cbuf);
1189 __ movq(Address(rsp, -8), rax);
1190 __ movl(rax, Address(rsp, src_offset));
1191 __ movl(Address(rsp, dst_offset), rax);
1192 __ movq(rax, Address(rsp, -8));
1193 #ifndef PRODUCT
1194 } else {
1195 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1196 "movl rax, [rsp + #%d]\n\t"
1197 "movl [rsp + #%d], rax\n\t"
1198 "movq rax, [rsp - #8]",
1199 src_offset, dst_offset);
1200 #endif
1201 }
1202 }
1203 return 0;
1204 } else if (dst_first_rc == rc_int) {
1205 // mem -> gpr
1206 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1207 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1208 // 64-bit
1209 int offset = ra_->reg2offset(src_first);
1210 if (cbuf) {
1211 MacroAssembler _masm(cbuf);
1212 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1213 #ifndef PRODUCT
1214 } else {
1215 st->print("movq %s, [rsp + #%d]\t# spill",
1216 Matcher::regName[dst_first],
1217 offset);
1218 #endif
1219 }
1220 } else {
1221 // 32-bit
1222 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1223 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1224 int offset = ra_->reg2offset(src_first);
1225 if (cbuf) {
1226 MacroAssembler _masm(cbuf);
1227 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1228 #ifndef PRODUCT
1229 } else {
1230 st->print("movl %s, [rsp + #%d]\t# spill",
1231 Matcher::regName[dst_first],
1232 offset);
1233 #endif
1234 }
1235 }
1236 return 0;
1237 } else if (dst_first_rc == rc_float) {
1238 // mem-> xmm
1239 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1240 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1241 // 64-bit
1242 int offset = ra_->reg2offset(src_first);
1243 if (cbuf) {
1244 MacroAssembler _masm(cbuf);
1245 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1246 #ifndef PRODUCT
1247 } else {
1248 st->print("%s %s, [rsp + #%d]\t# spill",
1249 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1250 Matcher::regName[dst_first],
1251 offset);
1252 #endif
1253 }
1254 } else {
1255 // 32-bit
1256 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1257 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1258 int offset = ra_->reg2offset(src_first);
1259 if (cbuf) {
1260 MacroAssembler _masm(cbuf);
1261 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1262 #ifndef PRODUCT
1263 } else {
1264 st->print("movss %s, [rsp + #%d]\t# spill",
1265 Matcher::regName[dst_first],
1266 offset);
1267 #endif
1268 }
1269 }
1270 return 0;
1271 }
1272 } else if (src_first_rc == rc_int) {
1273 // gpr ->
1274 if (dst_first_rc == rc_stack) {
1275 // gpr -> mem
1276 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1277 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1278 // 64-bit
1279 int offset = ra_->reg2offset(dst_first);
1280 if (cbuf) {
1281 MacroAssembler _masm(cbuf);
1282 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1283 #ifndef PRODUCT
1284 } else {
1285 st->print("movq [rsp + #%d], %s\t# spill",
1286 offset,
1287 Matcher::regName[src_first]);
1288 #endif
1289 }
1290 } else {
1291 // 32-bit
1292 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1293 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1294 int offset = ra_->reg2offset(dst_first);
1295 if (cbuf) {
1296 MacroAssembler _masm(cbuf);
1297 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1298 #ifndef PRODUCT
1299 } else {
1300 st->print("movl [rsp + #%d], %s\t# spill",
1301 offset,
1302 Matcher::regName[src_first]);
1303 #endif
1304 }
1305 }
1306 return 0;
1307 } else if (dst_first_rc == rc_int) {
1308 // gpr -> gpr
1309 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1310 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1311 // 64-bit
1312 if (cbuf) {
1313 MacroAssembler _masm(cbuf);
1314 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1315 as_Register(Matcher::_regEncode[src_first]));
1316 #ifndef PRODUCT
1317 } else {
1318 st->print("movq %s, %s\t# spill",
1319 Matcher::regName[dst_first],
1320 Matcher::regName[src_first]);
1321 #endif
1322 }
1323 return 0;
1324 } else {
1325 // 32-bit
1326 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1327 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1328 if (cbuf) {
1329 MacroAssembler _masm(cbuf);
1330 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1331 as_Register(Matcher::_regEncode[src_first]));
1332 #ifndef PRODUCT
1333 } else {
1334 st->print("movl %s, %s\t# spill",
1335 Matcher::regName[dst_first],
1336 Matcher::regName[src_first]);
1337 #endif
1338 }
1339 return 0;
1340 }
1341 } else if (dst_first_rc == rc_float) {
1342 // gpr -> xmm
1343 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1344 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1345 // 64-bit
1346 if (cbuf) {
1347 MacroAssembler _masm(cbuf);
1348 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1349 #ifndef PRODUCT
1350 } else {
1351 st->print("movdq %s, %s\t# spill",
1352 Matcher::regName[dst_first],
1353 Matcher::regName[src_first]);
1354 #endif
1355 }
1356 } else {
1357 // 32-bit
1358 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1359 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1360 if (cbuf) {
1361 MacroAssembler _masm(cbuf);
1362 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1363 #ifndef PRODUCT
1364 } else {
1365 st->print("movdl %s, %s\t# spill",
1366 Matcher::regName[dst_first],
1367 Matcher::regName[src_first]);
1368 #endif
1369 }
1370 }
1371 return 0;
1372 }
1373 } else if (src_first_rc == rc_float) {
1374 // xmm ->
1375 if (dst_first_rc == rc_stack) {
1376 // xmm -> mem
1377 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1378 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1379 // 64-bit
1380 int offset = ra_->reg2offset(dst_first);
1381 if (cbuf) {
1382 MacroAssembler _masm(cbuf);
1383 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1384 #ifndef PRODUCT
1385 } else {
1386 st->print("movsd [rsp + #%d], %s\t# spill",
1387 offset,
1388 Matcher::regName[src_first]);
1389 #endif
1390 }
1391 } else {
1392 // 32-bit
1393 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1394 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1395 int offset = ra_->reg2offset(dst_first);
1396 if (cbuf) {
1397 MacroAssembler _masm(cbuf);
1398 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1399 #ifndef PRODUCT
1400 } else {
1401 st->print("movss [rsp + #%d], %s\t# spill",
1402 offset,
1403 Matcher::regName[src_first]);
1404 #endif
1405 }
1406 }
1407 return 0;
1408 } else if (dst_first_rc == rc_int) {
1409 // xmm -> gpr
1410 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1411 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1412 // 64-bit
1413 if (cbuf) {
1414 MacroAssembler _masm(cbuf);
1415 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1416 #ifndef PRODUCT
1417 } else {
1418 st->print("movdq %s, %s\t# spill",
1419 Matcher::regName[dst_first],
1420 Matcher::regName[src_first]);
1421 #endif
1422 }
1423 } else {
1424 // 32-bit
1425 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1426 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1427 if (cbuf) {
1428 MacroAssembler _masm(cbuf);
1429 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1430 #ifndef PRODUCT
1431 } else {
1432 st->print("movdl %s, %s\t# spill",
1433 Matcher::regName[dst_first],
1434 Matcher::regName[src_first]);
1435 #endif
1436 }
1437 }
1438 return 0;
1439 } else if (dst_first_rc == rc_float) {
1440 // xmm -> xmm
1441 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1442 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1443 // 64-bit
1444 if (cbuf) {
1445 MacroAssembler _masm(cbuf);
1446 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1447 #ifndef PRODUCT
1448 } else {
1449 st->print("%s %s, %s\t# spill",
1450 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1451 Matcher::regName[dst_first],
1452 Matcher::regName[src_first]);
1453 #endif
1454 }
1455 } else {
1456 // 32-bit
1457 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1458 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1459 if (cbuf) {
1460 MacroAssembler _masm(cbuf);
1461 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1462 #ifndef PRODUCT
1463 } else {
1464 st->print("%s %s, %s\t# spill",
1465 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1466 Matcher::regName[dst_first],
1467 Matcher::regName[src_first]);
1468 #endif
1469 }
1470 }
1471 return 0;
1472 }
1473 }
1474
1475 assert(0," foo ");
1476 Unimplemented();
1477 return 0;
1478 }
1479
1480 #ifndef PRODUCT
1481 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1482 implementation(NULL, ra_, false, st);
1483 }
1484 #endif
1485
1486 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1487 implementation(&cbuf, ra_, false, NULL);
1488 }
1489
1490 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1491 return MachNode::size(ra_);
1492 }
1493
1494 //=============================================================================
1495 #ifndef PRODUCT
1496 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1497 {
1498 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1499 int reg = ra_->get_reg_first(this);
1500 st->print("leaq %s, [rsp + #%d]\t# box lock",
1501 Matcher::regName[reg], offset);
1502 }
1503 #endif
1504
1505 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1506 {
1507 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1508 int reg = ra_->get_encode(this);
1509 if (offset >= 0x80) {
1510 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1511 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1512 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1513 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1514 emit_d32(cbuf, offset);
1515 } else {
1516 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1517 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1518 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1519 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1520 emit_d8(cbuf, offset);
1521 }
1522 }
1523
1524 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1525 {
1526 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1527 return (offset < 0x80) ? 5 : 8; // REX
1528 }
1529
1530 //=============================================================================
1531 #ifndef PRODUCT
1532 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1533 {
1534 if (UseCompressedClassPointers) {
1535 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1536 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1537 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1538 } else {
1539 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1540 "# Inline cache check");
1541 }
1542 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1543 st->print_cr("\tnop\t# nops to align entry point");
1544 }
1545 #endif
1546
1547 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1548 {
1549 MacroAssembler masm(&cbuf);
1550 uint insts_size = cbuf.insts_size();
1551 if (UseCompressedClassPointers) {
1552 masm.load_klass(rscratch1, j_rarg0);
1553 masm.cmpptr(rax, rscratch1);
1554 } else {
1555 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1556 }
1557
1558 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1559
1560 /* WARNING these NOPs are critical so that verified entry point is properly
1561 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1562 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1563 if (OptoBreakpoint) {
1564 // Leave space for int3
1565 nops_cnt -= 1;
1566 }
1567 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1568 if (nops_cnt > 0)
1569 masm.nop(nops_cnt);
1570 }
1571
1572 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1573 {
1574 return MachNode::size(ra_); // too many variables; just compute it
1575 // the hard way
1576 }
1577
1578
1579 //=============================================================================
1580
1581 int Matcher::regnum_to_fpu_offset(int regnum)
1582 {
1583 return regnum - 32; // The FP registers are in the second chunk
1584 }
1585
1586 // This is UltraSparc specific, true just means we have fast l2f conversion
1587 const bool Matcher::convL2FSupported(void) {
1588 return true;
1589 }
1590
1591 // Is this branch offset short enough that a short branch can be used?
1592 //
1593 // NOTE: If the platform does not provide any short branch variants, then
1594 // this method should return false for offset 0.
1595 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1596 // The passed offset is relative to address of the branch.
1597 // On 86 a branch displacement is calculated relative to address
1598 // of a next instruction.
1599 offset -= br_size;
1600
1601 // the short version of jmpConUCF2 contains multiple branches,
1602 // making the reach slightly less
1603 if (rule == jmpConUCF2_rule)
1604 return (-126 <= offset && offset <= 125);
1605 return (-128 <= offset && offset <= 127);
1606 }
1607
1608 const bool Matcher::isSimpleConstant64(jlong value) {
1609 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1610 //return value == (int) value; // Cf. storeImmL and immL32.
1611
1612 // Probably always true, even if a temp register is required.
1613 return true;
1614 }
1615
1616 // The ecx parameter to rep stosq for the ClearArray node is in words.
1617 const bool Matcher::init_array_count_is_in_bytes = false;
1618
1619 // No additional cost for CMOVL.
1620 const int Matcher::long_cmove_cost() { return 0; }
1621
1622 // No CMOVF/CMOVD with SSE2
1623 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1624
1625 // Does the CPU require late expand (see block.cpp for description of late expand)?
1626 const bool Matcher::require_postalloc_expand = false;
1627
1628 // Do we need to mask the count passed to shift instructions or does
1629 // the cpu only look at the lower 5/6 bits anyway?
1630 const bool Matcher::need_masked_shift_count = false;
1631
1632 bool Matcher::narrow_oop_use_complex_address() {
1633 assert(UseCompressedOops, "only for compressed oops code");
1634 return (LogMinObjAlignmentInBytes <= 3);
1635 }
1636
1637 bool Matcher::narrow_klass_use_complex_address() {
1638 assert(UseCompressedClassPointers, "only for compressed klass code");
1639 return (LogKlassAlignmentInBytes <= 3);
1640 }
1641
1642 bool Matcher::const_oop_prefer_decode() {
1643 // Prefer ConN+DecodeN over ConP.
1644 return true;
1645 }
1646
1647 bool Matcher::const_klass_prefer_decode() {
1648 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1649 // or condisider the following:
1650 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1651 //return CompressedKlassPointers::base() == NULL;
1652 return true;
1653 }
1654
1655 // Is it better to copy float constants, or load them directly from
1656 // memory? Intel can load a float constant from a direct address,
1657 // requiring no extra registers. Most RISCs will have to materialize
1658 // an address into a register first, so they would do better to copy
1659 // the constant from stack.
1660 const bool Matcher::rematerialize_float_constants = true; // XXX
1661
1662 // If CPU can load and store mis-aligned doubles directly then no
1663 // fixup is needed. Else we split the double into 2 integer pieces
1664 // and move it piece-by-piece. Only happens when passing doubles into
1665 // C code as the Java calling convention forces doubles to be aligned.
1666 const bool Matcher::misaligned_doubles_ok = true;
1667
1668 // No-op on amd64
1669 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1670
1671 // Advertise here if the CPU requires explicit rounding operations to implement strictfp mode.
1672 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1673
1674 // Are floats conerted to double when stored to stack during deoptimization?
1675 // On x64 it is stored without convertion so we can use normal access.
1676 bool Matcher::float_in_double() { return false; }
1677
1678 // Do ints take an entire long register or just half?
1679 const bool Matcher::int_in_long = true;
1680
1681 // Return whether or not this register is ever used as an argument.
1682 // This function is used on startup to build the trampoline stubs in
1683 // generateOptoStub. Registers not mentioned will be killed by the VM
1684 // call in the trampoline, and arguments in those registers not be
1685 // available to the callee.
1686 bool Matcher::can_be_java_arg(int reg)
1687 {
1688 return
1689 reg == RDI_num || reg == RDI_H_num ||
1690 reg == RSI_num || reg == RSI_H_num ||
1691 reg == RDX_num || reg == RDX_H_num ||
1692 reg == RCX_num || reg == RCX_H_num ||
1693 reg == R8_num || reg == R8_H_num ||
1694 reg == R9_num || reg == R9_H_num ||
1695 reg == R12_num || reg == R12_H_num ||
1696 reg == XMM0_num || reg == XMM0b_num ||
1697 reg == XMM1_num || reg == XMM1b_num ||
1698 reg == XMM2_num || reg == XMM2b_num ||
1699 reg == XMM3_num || reg == XMM3b_num ||
1700 reg == XMM4_num || reg == XMM4b_num ||
1701 reg == XMM5_num || reg == XMM5b_num ||
1702 reg == XMM6_num || reg == XMM6b_num ||
1703 reg == XMM7_num || reg == XMM7b_num;
1704 }
1705
1706 bool Matcher::is_spillable_arg(int reg)
1707 {
1708 return can_be_java_arg(reg);
1709 }
1710
1711 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1712 // In 64 bit mode a code which use multiply when
1713 // devisor is constant is faster than hardware
1714 // DIV instruction (it uses MulHiL).
1715 return false;
1716 }
1717
1718 // Register for DIVI projection of divmodI
1719 RegMask Matcher::divI_proj_mask() {
1720 return INT_RAX_REG_mask();
1721 }
1722
1723 // Register for MODI projection of divmodI
1724 RegMask Matcher::modI_proj_mask() {
1725 return INT_RDX_REG_mask();
1726 }
1727
1728 // Register for DIVL projection of divmodL
1729 RegMask Matcher::divL_proj_mask() {
1730 return LONG_RAX_REG_mask();
1731 }
1732
1733 // Register for MODL projection of divmodL
1734 RegMask Matcher::modL_proj_mask() {
1735 return LONG_RDX_REG_mask();
1736 }
1737
1738 // Register for saving SP into on method handle invokes. Not used on x86_64.
1739 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1740 return NO_REG_mask();
1741 }
1742
1743 %}
1744
1745 //----------ENCODING BLOCK-----------------------------------------------------
1746 // This block specifies the encoding classes used by the compiler to
1747 // output byte streams. Encoding classes are parameterized macros
1748 // used by Machine Instruction Nodes in order to generate the bit
1749 // encoding of the instruction. Operands specify their base encoding
1750 // interface with the interface keyword. There are currently
1751 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1752 // COND_INTER. REG_INTER causes an operand to generate a function
1753 // which returns its register number when queried. CONST_INTER causes
1754 // an operand to generate a function which returns the value of the
1755 // constant when queried. MEMORY_INTER causes an operand to generate
1756 // four functions which return the Base Register, the Index Register,
1757 // the Scale Value, and the Offset Value of the operand when queried.
1758 // COND_INTER causes an operand to generate six functions which return
1759 // the encoding code (ie - encoding bits for the instruction)
1760 // associated with each basic boolean condition for a conditional
1761 // instruction.
1762 //
1763 // Instructions specify two basic values for encoding. Again, a
1764 // function is available to check if the constant displacement is an
1765 // oop. They use the ins_encode keyword to specify their encoding
1766 // classes (which must be a sequence of enc_class names, and their
1767 // parameters, specified in the encoding block), and they use the
1768 // opcode keyword to specify, in order, their primary, secondary, and
1769 // tertiary opcode. Only the opcode sections which a particular
1770 // instruction needs for encoding need to be specified.
1771 encode %{
1772 // Build emit functions for each basic byte or larger field in the
1773 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1774 // from C++ code in the enc_class source block. Emit functions will
1775 // live in the main source block for now. In future, we can
1776 // generalize this by adding a syntax that specifies the sizes of
1777 // fields in an order, so that the adlc can build the emit functions
1778 // automagically
1779
1780 // Emit primary opcode
1781 enc_class OpcP
1782 %{
1783 emit_opcode(cbuf, $primary);
1784 %}
1785
1786 // Emit secondary opcode
1787 enc_class OpcS
1788 %{
1789 emit_opcode(cbuf, $secondary);
1790 %}
1791
1792 // Emit tertiary opcode
1793 enc_class OpcT
1794 %{
1795 emit_opcode(cbuf, $tertiary);
1796 %}
1797
1798 // Emit opcode directly
1799 enc_class Opcode(immI d8)
1800 %{
1801 emit_opcode(cbuf, $d8$$constant);
1802 %}
1803
1804 // Emit size prefix
1805 enc_class SizePrefix
1806 %{
1807 emit_opcode(cbuf, 0x66);
1808 %}
1809
1810 enc_class reg(rRegI reg)
1811 %{
1812 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1813 %}
1814
1815 enc_class reg_reg(rRegI dst, rRegI src)
1816 %{
1817 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1818 %}
1819
1820 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1821 %{
1822 emit_opcode(cbuf, $opcode$$constant);
1823 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1824 %}
1825
1826 enc_class cdql_enc(no_rax_rdx_RegI div)
1827 %{
1828 // Full implementation of Java idiv and irem; checks for
1829 // special case as described in JVM spec., p.243 & p.271.
1830 //
1831 // normal case special case
1832 //
1833 // input : rax: dividend min_int
1834 // reg: divisor -1
1835 //
1836 // output: rax: quotient (= rax idiv reg) min_int
1837 // rdx: remainder (= rax irem reg) 0
1838 //
1839 // Code sequnce:
1840 //
1841 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1842 // 5: 75 07/08 jne e <normal>
1843 // 7: 33 d2 xor %edx,%edx
1844 // [div >= 8 -> offset + 1]
1845 // [REX_B]
1846 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1847 // c: 74 03/04 je 11 <done>
1848 // 000000000000000e <normal>:
1849 // e: 99 cltd
1850 // [div >= 8 -> offset + 1]
1851 // [REX_B]
1852 // f: f7 f9 idiv $div
1853 // 0000000000000011 <done>:
1854
1855 // cmp $0x80000000,%eax
1856 emit_opcode(cbuf, 0x3d);
1857 emit_d8(cbuf, 0x00);
1858 emit_d8(cbuf, 0x00);
1859 emit_d8(cbuf, 0x00);
1860 emit_d8(cbuf, 0x80);
1861
1862 // jne e <normal>
1863 emit_opcode(cbuf, 0x75);
1864 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1865
1866 // xor %edx,%edx
1867 emit_opcode(cbuf, 0x33);
1868 emit_d8(cbuf, 0xD2);
1869
1870 // cmp $0xffffffffffffffff,%ecx
1871 if ($div$$reg >= 8) {
1872 emit_opcode(cbuf, Assembler::REX_B);
1873 }
1874 emit_opcode(cbuf, 0x83);
1875 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1876 emit_d8(cbuf, 0xFF);
1877
1878 // je 11 <done>
1879 emit_opcode(cbuf, 0x74);
1880 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1881
1882 // <normal>
1883 // cltd
1884 emit_opcode(cbuf, 0x99);
1885
1886 // idivl (note: must be emitted by the user of this rule)
1887 // <done>
1888 %}
1889
1890 enc_class cdqq_enc(no_rax_rdx_RegL div)
1891 %{
1892 // Full implementation of Java ldiv and lrem; checks for
1893 // special case as described in JVM spec., p.243 & p.271.
1894 //
1895 // normal case special case
1896 //
1897 // input : rax: dividend min_long
1898 // reg: divisor -1
1899 //
1900 // output: rax: quotient (= rax idiv reg) min_long
1901 // rdx: remainder (= rax irem reg) 0
1902 //
1903 // Code sequnce:
1904 //
1905 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1906 // 7: 00 00 80
1907 // a: 48 39 d0 cmp %rdx,%rax
1908 // d: 75 08 jne 17 <normal>
1909 // f: 33 d2 xor %edx,%edx
1910 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1911 // 15: 74 05 je 1c <done>
1912 // 0000000000000017 <normal>:
1913 // 17: 48 99 cqto
1914 // 19: 48 f7 f9 idiv $div
1915 // 000000000000001c <done>:
1916
1917 // mov $0x8000000000000000,%rdx
1918 emit_opcode(cbuf, Assembler::REX_W);
1919 emit_opcode(cbuf, 0xBA);
1920 emit_d8(cbuf, 0x00);
1921 emit_d8(cbuf, 0x00);
1922 emit_d8(cbuf, 0x00);
1923 emit_d8(cbuf, 0x00);
1924 emit_d8(cbuf, 0x00);
1925 emit_d8(cbuf, 0x00);
1926 emit_d8(cbuf, 0x00);
1927 emit_d8(cbuf, 0x80);
1928
1929 // cmp %rdx,%rax
1930 emit_opcode(cbuf, Assembler::REX_W);
1931 emit_opcode(cbuf, 0x39);
1932 emit_d8(cbuf, 0xD0);
1933
1934 // jne 17 <normal>
1935 emit_opcode(cbuf, 0x75);
1936 emit_d8(cbuf, 0x08);
1937
1938 // xor %edx,%edx
1939 emit_opcode(cbuf, 0x33);
1940 emit_d8(cbuf, 0xD2);
1941
1942 // cmp $0xffffffffffffffff,$div
1943 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1944 emit_opcode(cbuf, 0x83);
1945 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1946 emit_d8(cbuf, 0xFF);
1947
1948 // je 1e <done>
1949 emit_opcode(cbuf, 0x74);
1950 emit_d8(cbuf, 0x05);
1951
1952 // <normal>
1953 // cqto
1954 emit_opcode(cbuf, Assembler::REX_W);
1955 emit_opcode(cbuf, 0x99);
1956
1957 // idivq (note: must be emitted by the user of this rule)
1958 // <done>
1959 %}
1960
1961 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1962 enc_class OpcSE(immI imm)
1963 %{
1964 // Emit primary opcode and set sign-extend bit
1965 // Check for 8-bit immediate, and set sign extend bit in opcode
1966 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1967 emit_opcode(cbuf, $primary | 0x02);
1968 } else {
1969 // 32-bit immediate
1970 emit_opcode(cbuf, $primary);
1971 }
1972 %}
1973
1974 enc_class OpcSErm(rRegI dst, immI imm)
1975 %{
1976 // OpcSEr/m
1977 int dstenc = $dst$$reg;
1978 if (dstenc >= 8) {
1979 emit_opcode(cbuf, Assembler::REX_B);
1980 dstenc -= 8;
1981 }
1982 // Emit primary opcode and set sign-extend bit
1983 // Check for 8-bit immediate, and set sign extend bit in opcode
1984 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1985 emit_opcode(cbuf, $primary | 0x02);
1986 } else {
1987 // 32-bit immediate
1988 emit_opcode(cbuf, $primary);
1989 }
1990 // Emit r/m byte with secondary opcode, after primary opcode.
1991 emit_rm(cbuf, 0x3, $secondary, dstenc);
1992 %}
1993
1994 enc_class OpcSErm_wide(rRegL dst, immI imm)
1995 %{
1996 // OpcSEr/m
1997 int dstenc = $dst$$reg;
1998 if (dstenc < 8) {
1999 emit_opcode(cbuf, Assembler::REX_W);
2000 } else {
2001 emit_opcode(cbuf, Assembler::REX_WB);
2002 dstenc -= 8;
2003 }
2004 // Emit primary opcode and set sign-extend bit
2005 // Check for 8-bit immediate, and set sign extend bit in opcode
2006 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2007 emit_opcode(cbuf, $primary | 0x02);
2008 } else {
2009 // 32-bit immediate
2010 emit_opcode(cbuf, $primary);
2011 }
2012 // Emit r/m byte with secondary opcode, after primary opcode.
2013 emit_rm(cbuf, 0x3, $secondary, dstenc);
2014 %}
2015
2016 enc_class Con8or32(immI imm)
2017 %{
2018 // Check for 8-bit immediate, and set sign extend bit in opcode
2019 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2020 $$$emit8$imm$$constant;
2021 } else {
2022 // 32-bit immediate
2023 $$$emit32$imm$$constant;
2024 }
2025 %}
2026
2027 enc_class opc2_reg(rRegI dst)
2028 %{
2029 // BSWAP
2030 emit_cc(cbuf, $secondary, $dst$$reg);
2031 %}
2032
2033 enc_class opc3_reg(rRegI dst)
2034 %{
2035 // BSWAP
2036 emit_cc(cbuf, $tertiary, $dst$$reg);
2037 %}
2038
2039 enc_class reg_opc(rRegI div)
2040 %{
2041 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2042 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2043 %}
2044
2045 enc_class enc_cmov(cmpOp cop)
2046 %{
2047 // CMOV
2048 $$$emit8$primary;
2049 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2050 %}
2051
2052 enc_class enc_PartialSubtypeCheck()
2053 %{
2054 Register Rrdi = as_Register(RDI_enc); // result register
2055 Register Rrax = as_Register(RAX_enc); // super class
2056 Register Rrcx = as_Register(RCX_enc); // killed
2057 Register Rrsi = as_Register(RSI_enc); // sub class
2058 Label miss;
2059 const bool set_cond_codes = true;
2060
2061 MacroAssembler _masm(&cbuf);
2062 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2063 NULL, &miss,
2064 /*set_cond_codes:*/ true);
2065 if ($primary) {
2066 __ xorptr(Rrdi, Rrdi);
2067 }
2068 __ bind(miss);
2069 %}
2070
2071 enc_class clear_avx %{
2072 debug_only(int off0 = cbuf.insts_size());
2073 if (generate_vzeroupper(Compile::current())) {
2074 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2075 // Clear upper bits of YMM registers when current compiled code uses
2076 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2077 MacroAssembler _masm(&cbuf);
2078 __ vzeroupper();
2079 }
2080 debug_only(int off1 = cbuf.insts_size());
2081 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2082 %}
2083
2084 enc_class Java_To_Runtime(method meth) %{
2085 // No relocation needed
2086 MacroAssembler _masm(&cbuf);
2087 __ mov64(r10, (int64_t) $meth$$method);
2088 __ call(r10);
2089 %}
2090
2091 enc_class Java_To_Interpreter(method meth)
2092 %{
2093 // CALL Java_To_Interpreter
2094 // This is the instruction starting address for relocation info.
2095 cbuf.set_insts_mark();
2096 $$$emit8$primary;
2097 // CALL directly to the runtime
2098 emit_d32_reloc(cbuf,
2099 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2100 runtime_call_Relocation::spec(),
2101 RELOC_DISP32);
2102 %}
2103
2104 enc_class Java_Static_Call(method meth)
2105 %{
2106 // JAVA STATIC CALL
2107 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2108 // determine who we intended to call.
2109 cbuf.set_insts_mark();
2110 $$$emit8$primary;
2111
2112 if (!_method) {
2113 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2114 runtime_call_Relocation::spec(),
2115 RELOC_DISP32);
2116 } else {
2117 int method_index = resolved_method_index(cbuf);
2118 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2119 : static_call_Relocation::spec(method_index);
2120 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2121 rspec, RELOC_DISP32);
2122 // Emit stubs for static call.
2123 address mark = cbuf.insts_mark();
2124 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2125 if (stub == NULL) {
2126 ciEnv::current()->record_failure("CodeCache is full");
2127 return;
2128 }
2129 #if INCLUDE_AOT
2130 CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2131 #endif
2132 }
2133 %}
2134
2135 enc_class Java_Dynamic_Call(method meth) %{
2136 MacroAssembler _masm(&cbuf);
2137 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2138 %}
2139
2140 enc_class Java_Compiled_Call(method meth)
2141 %{
2142 // JAVA COMPILED CALL
2143 int disp = in_bytes(Method:: from_compiled_offset());
2144
2145 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2146 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2147
2148 // callq *disp(%rax)
2149 cbuf.set_insts_mark();
2150 $$$emit8$primary;
2151 if (disp < 0x80) {
2152 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2153 emit_d8(cbuf, disp); // Displacement
2154 } else {
2155 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2156 emit_d32(cbuf, disp); // Displacement
2157 }
2158 %}
2159
2160 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2161 %{
2162 // SAL, SAR, SHR
2163 int dstenc = $dst$$reg;
2164 if (dstenc >= 8) {
2165 emit_opcode(cbuf, Assembler::REX_B);
2166 dstenc -= 8;
2167 }
2168 $$$emit8$primary;
2169 emit_rm(cbuf, 0x3, $secondary, dstenc);
2170 $$$emit8$shift$$constant;
2171 %}
2172
2173 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2174 %{
2175 // SAL, SAR, SHR
2176 int dstenc = $dst$$reg;
2177 if (dstenc < 8) {
2178 emit_opcode(cbuf, Assembler::REX_W);
2179 } else {
2180 emit_opcode(cbuf, Assembler::REX_WB);
2181 dstenc -= 8;
2182 }
2183 $$$emit8$primary;
2184 emit_rm(cbuf, 0x3, $secondary, dstenc);
2185 $$$emit8$shift$$constant;
2186 %}
2187
2188 enc_class load_immI(rRegI dst, immI src)
2189 %{
2190 int dstenc = $dst$$reg;
2191 if (dstenc >= 8) {
2192 emit_opcode(cbuf, Assembler::REX_B);
2193 dstenc -= 8;
2194 }
2195 emit_opcode(cbuf, 0xB8 | dstenc);
2196 $$$emit32$src$$constant;
2197 %}
2198
2199 enc_class load_immL(rRegL dst, immL src)
2200 %{
2201 int dstenc = $dst$$reg;
2202 if (dstenc < 8) {
2203 emit_opcode(cbuf, Assembler::REX_W);
2204 } else {
2205 emit_opcode(cbuf, Assembler::REX_WB);
2206 dstenc -= 8;
2207 }
2208 emit_opcode(cbuf, 0xB8 | dstenc);
2209 emit_d64(cbuf, $src$$constant);
2210 %}
2211
2212 enc_class load_immUL32(rRegL dst, immUL32 src)
2213 %{
2214 // same as load_immI, but this time we care about zeroes in the high word
2215 int dstenc = $dst$$reg;
2216 if (dstenc >= 8) {
2217 emit_opcode(cbuf, Assembler::REX_B);
2218 dstenc -= 8;
2219 }
2220 emit_opcode(cbuf, 0xB8 | dstenc);
2221 $$$emit32$src$$constant;
2222 %}
2223
2224 enc_class load_immL32(rRegL dst, immL32 src)
2225 %{
2226 int dstenc = $dst$$reg;
2227 if (dstenc < 8) {
2228 emit_opcode(cbuf, Assembler::REX_W);
2229 } else {
2230 emit_opcode(cbuf, Assembler::REX_WB);
2231 dstenc -= 8;
2232 }
2233 emit_opcode(cbuf, 0xC7);
2234 emit_rm(cbuf, 0x03, 0x00, dstenc);
2235 $$$emit32$src$$constant;
2236 %}
2237
2238 enc_class load_immP31(rRegP dst, immP32 src)
2239 %{
2240 // same as load_immI, but this time we care about zeroes in the high word
2241 int dstenc = $dst$$reg;
2242 if (dstenc >= 8) {
2243 emit_opcode(cbuf, Assembler::REX_B);
2244 dstenc -= 8;
2245 }
2246 emit_opcode(cbuf, 0xB8 | dstenc);
2247 $$$emit32$src$$constant;
2248 %}
2249
2250 enc_class load_immP(rRegP dst, immP src)
2251 %{
2252 int dstenc = $dst$$reg;
2253 if (dstenc < 8) {
2254 emit_opcode(cbuf, Assembler::REX_W);
2255 } else {
2256 emit_opcode(cbuf, Assembler::REX_WB);
2257 dstenc -= 8;
2258 }
2259 emit_opcode(cbuf, 0xB8 | dstenc);
2260 // This next line should be generated from ADLC
2261 if ($src->constant_reloc() != relocInfo::none) {
2262 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2263 } else {
2264 emit_d64(cbuf, $src$$constant);
2265 }
2266 %}
2267
2268 enc_class Con32(immI src)
2269 %{
2270 // Output immediate
2271 $$$emit32$src$$constant;
2272 %}
2273
2274 enc_class Con32F_as_bits(immF src)
2275 %{
2276 // Output Float immediate bits
2277 jfloat jf = $src$$constant;
2278 jint jf_as_bits = jint_cast(jf);
2279 emit_d32(cbuf, jf_as_bits);
2280 %}
2281
2282 enc_class Con16(immI src)
2283 %{
2284 // Output immediate
2285 $$$emit16$src$$constant;
2286 %}
2287
2288 // How is this different from Con32??? XXX
2289 enc_class Con_d32(immI src)
2290 %{
2291 emit_d32(cbuf,$src$$constant);
2292 %}
2293
2294 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2295 // Output immediate memory reference
2296 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2297 emit_d32(cbuf, 0x00);
2298 %}
2299
2300 enc_class lock_prefix()
2301 %{
2302 emit_opcode(cbuf, 0xF0); // lock
2303 %}
2304
2305 enc_class REX_mem(memory mem)
2306 %{
2307 if ($mem$$base >= 8) {
2308 if ($mem$$index < 8) {
2309 emit_opcode(cbuf, Assembler::REX_B);
2310 } else {
2311 emit_opcode(cbuf, Assembler::REX_XB);
2312 }
2313 } else {
2314 if ($mem$$index >= 8) {
2315 emit_opcode(cbuf, Assembler::REX_X);
2316 }
2317 }
2318 %}
2319
2320 enc_class REX_mem_wide(memory mem)
2321 %{
2322 if ($mem$$base >= 8) {
2323 if ($mem$$index < 8) {
2324 emit_opcode(cbuf, Assembler::REX_WB);
2325 } else {
2326 emit_opcode(cbuf, Assembler::REX_WXB);
2327 }
2328 } else {
2329 if ($mem$$index < 8) {
2330 emit_opcode(cbuf, Assembler::REX_W);
2331 } else {
2332 emit_opcode(cbuf, Assembler::REX_WX);
2333 }
2334 }
2335 %}
2336
2337 // for byte regs
2338 enc_class REX_breg(rRegI reg)
2339 %{
2340 if ($reg$$reg >= 4) {
2341 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2342 }
2343 %}
2344
2345 // for byte regs
2346 enc_class REX_reg_breg(rRegI dst, rRegI src)
2347 %{
2348 if ($dst$$reg < 8) {
2349 if ($src$$reg >= 4) {
2350 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2351 }
2352 } else {
2353 if ($src$$reg < 8) {
2354 emit_opcode(cbuf, Assembler::REX_R);
2355 } else {
2356 emit_opcode(cbuf, Assembler::REX_RB);
2357 }
2358 }
2359 %}
2360
2361 // for byte regs
2362 enc_class REX_breg_mem(rRegI reg, memory mem)
2363 %{
2364 if ($reg$$reg < 8) {
2365 if ($mem$$base < 8) {
2366 if ($mem$$index >= 8) {
2367 emit_opcode(cbuf, Assembler::REX_X);
2368 } else if ($reg$$reg >= 4) {
2369 emit_opcode(cbuf, Assembler::REX);
2370 }
2371 } else {
2372 if ($mem$$index < 8) {
2373 emit_opcode(cbuf, Assembler::REX_B);
2374 } else {
2375 emit_opcode(cbuf, Assembler::REX_XB);
2376 }
2377 }
2378 } else {
2379 if ($mem$$base < 8) {
2380 if ($mem$$index < 8) {
2381 emit_opcode(cbuf, Assembler::REX_R);
2382 } else {
2383 emit_opcode(cbuf, Assembler::REX_RX);
2384 }
2385 } else {
2386 if ($mem$$index < 8) {
2387 emit_opcode(cbuf, Assembler::REX_RB);
2388 } else {
2389 emit_opcode(cbuf, Assembler::REX_RXB);
2390 }
2391 }
2392 }
2393 %}
2394
2395 enc_class REX_reg(rRegI reg)
2396 %{
2397 if ($reg$$reg >= 8) {
2398 emit_opcode(cbuf, Assembler::REX_B);
2399 }
2400 %}
2401
2402 enc_class REX_reg_wide(rRegI reg)
2403 %{
2404 if ($reg$$reg < 8) {
2405 emit_opcode(cbuf, Assembler::REX_W);
2406 } else {
2407 emit_opcode(cbuf, Assembler::REX_WB);
2408 }
2409 %}
2410
2411 enc_class REX_reg_reg(rRegI dst, rRegI src)
2412 %{
2413 if ($dst$$reg < 8) {
2414 if ($src$$reg >= 8) {
2415 emit_opcode(cbuf, Assembler::REX_B);
2416 }
2417 } else {
2418 if ($src$$reg < 8) {
2419 emit_opcode(cbuf, Assembler::REX_R);
2420 } else {
2421 emit_opcode(cbuf, Assembler::REX_RB);
2422 }
2423 }
2424 %}
2425
2426 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2427 %{
2428 if ($dst$$reg < 8) {
2429 if ($src$$reg < 8) {
2430 emit_opcode(cbuf, Assembler::REX_W);
2431 } else {
2432 emit_opcode(cbuf, Assembler::REX_WB);
2433 }
2434 } else {
2435 if ($src$$reg < 8) {
2436 emit_opcode(cbuf, Assembler::REX_WR);
2437 } else {
2438 emit_opcode(cbuf, Assembler::REX_WRB);
2439 }
2440 }
2441 %}
2442
2443 enc_class REX_reg_mem(rRegI reg, memory mem)
2444 %{
2445 if ($reg$$reg < 8) {
2446 if ($mem$$base < 8) {
2447 if ($mem$$index >= 8) {
2448 emit_opcode(cbuf, Assembler::REX_X);
2449 }
2450 } else {
2451 if ($mem$$index < 8) {
2452 emit_opcode(cbuf, Assembler::REX_B);
2453 } else {
2454 emit_opcode(cbuf, Assembler::REX_XB);
2455 }
2456 }
2457 } else {
2458 if ($mem$$base < 8) {
2459 if ($mem$$index < 8) {
2460 emit_opcode(cbuf, Assembler::REX_R);
2461 } else {
2462 emit_opcode(cbuf, Assembler::REX_RX);
2463 }
2464 } else {
2465 if ($mem$$index < 8) {
2466 emit_opcode(cbuf, Assembler::REX_RB);
2467 } else {
2468 emit_opcode(cbuf, Assembler::REX_RXB);
2469 }
2470 }
2471 }
2472 %}
2473
2474 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2475 %{
2476 if ($reg$$reg < 8) {
2477 if ($mem$$base < 8) {
2478 if ($mem$$index < 8) {
2479 emit_opcode(cbuf, Assembler::REX_W);
2480 } else {
2481 emit_opcode(cbuf, Assembler::REX_WX);
2482 }
2483 } else {
2484 if ($mem$$index < 8) {
2485 emit_opcode(cbuf, Assembler::REX_WB);
2486 } else {
2487 emit_opcode(cbuf, Assembler::REX_WXB);
2488 }
2489 }
2490 } else {
2491 if ($mem$$base < 8) {
2492 if ($mem$$index < 8) {
2493 emit_opcode(cbuf, Assembler::REX_WR);
2494 } else {
2495 emit_opcode(cbuf, Assembler::REX_WRX);
2496 }
2497 } else {
2498 if ($mem$$index < 8) {
2499 emit_opcode(cbuf, Assembler::REX_WRB);
2500 } else {
2501 emit_opcode(cbuf, Assembler::REX_WRXB);
2502 }
2503 }
2504 }
2505 %}
2506
2507 enc_class reg_mem(rRegI ereg, memory mem)
2508 %{
2509 // High registers handle in encode_RegMem
2510 int reg = $ereg$$reg;
2511 int base = $mem$$base;
2512 int index = $mem$$index;
2513 int scale = $mem$$scale;
2514 int disp = $mem$$disp;
2515 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2516
2517 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2518 %}
2519
2520 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2521 %{
2522 int rm_byte_opcode = $rm_opcode$$constant;
2523
2524 // High registers handle in encode_RegMem
2525 int base = $mem$$base;
2526 int index = $mem$$index;
2527 int scale = $mem$$scale;
2528 int displace = $mem$$disp;
2529
2530 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2531 // working with static
2532 // globals
2533 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2534 disp_reloc);
2535 %}
2536
2537 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2538 %{
2539 int reg_encoding = $dst$$reg;
2540 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2541 int index = 0x04; // 0x04 indicates no index
2542 int scale = 0x00; // 0x00 indicates no scale
2543 int displace = $src1$$constant; // 0x00 indicates no displacement
2544 relocInfo::relocType disp_reloc = relocInfo::none;
2545 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2546 disp_reloc);
2547 %}
2548
2549 enc_class neg_reg(rRegI dst)
2550 %{
2551 int dstenc = $dst$$reg;
2552 if (dstenc >= 8) {
2553 emit_opcode(cbuf, Assembler::REX_B);
2554 dstenc -= 8;
2555 }
2556 // NEG $dst
2557 emit_opcode(cbuf, 0xF7);
2558 emit_rm(cbuf, 0x3, 0x03, dstenc);
2559 %}
2560
2561 enc_class neg_reg_wide(rRegI dst)
2562 %{
2563 int dstenc = $dst$$reg;
2564 if (dstenc < 8) {
2565 emit_opcode(cbuf, Assembler::REX_W);
2566 } else {
2567 emit_opcode(cbuf, Assembler::REX_WB);
2568 dstenc -= 8;
2569 }
2570 // NEG $dst
2571 emit_opcode(cbuf, 0xF7);
2572 emit_rm(cbuf, 0x3, 0x03, dstenc);
2573 %}
2574
2575 enc_class setLT_reg(rRegI dst)
2576 %{
2577 int dstenc = $dst$$reg;
2578 if (dstenc >= 8) {
2579 emit_opcode(cbuf, Assembler::REX_B);
2580 dstenc -= 8;
2581 } else if (dstenc >= 4) {
2582 emit_opcode(cbuf, Assembler::REX);
2583 }
2584 // SETLT $dst
2585 emit_opcode(cbuf, 0x0F);
2586 emit_opcode(cbuf, 0x9C);
2587 emit_rm(cbuf, 0x3, 0x0, dstenc);
2588 %}
2589
2590 enc_class setNZ_reg(rRegI dst)
2591 %{
2592 int dstenc = $dst$$reg;
2593 if (dstenc >= 8) {
2594 emit_opcode(cbuf, Assembler::REX_B);
2595 dstenc -= 8;
2596 } else if (dstenc >= 4) {
2597 emit_opcode(cbuf, Assembler::REX);
2598 }
2599 // SETNZ $dst
2600 emit_opcode(cbuf, 0x0F);
2601 emit_opcode(cbuf, 0x95);
2602 emit_rm(cbuf, 0x3, 0x0, dstenc);
2603 %}
2604
2605
2606 // Compare the lonogs and set -1, 0, or 1 into dst
2607 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2608 %{
2609 int src1enc = $src1$$reg;
2610 int src2enc = $src2$$reg;
2611 int dstenc = $dst$$reg;
2612
2613 // cmpq $src1, $src2
2614 if (src1enc < 8) {
2615 if (src2enc < 8) {
2616 emit_opcode(cbuf, Assembler::REX_W);
2617 } else {
2618 emit_opcode(cbuf, Assembler::REX_WB);
2619 }
2620 } else {
2621 if (src2enc < 8) {
2622 emit_opcode(cbuf, Assembler::REX_WR);
2623 } else {
2624 emit_opcode(cbuf, Assembler::REX_WRB);
2625 }
2626 }
2627 emit_opcode(cbuf, 0x3B);
2628 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2629
2630 // movl $dst, -1
2631 if (dstenc >= 8) {
2632 emit_opcode(cbuf, Assembler::REX_B);
2633 }
2634 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2635 emit_d32(cbuf, -1);
2636
2637 // jl,s done
2638 emit_opcode(cbuf, 0x7C);
2639 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2640
2641 // setne $dst
2642 if (dstenc >= 4) {
2643 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2644 }
2645 emit_opcode(cbuf, 0x0F);
2646 emit_opcode(cbuf, 0x95);
2647 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2648
2649 // movzbl $dst, $dst
2650 if (dstenc >= 4) {
2651 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2652 }
2653 emit_opcode(cbuf, 0x0F);
2654 emit_opcode(cbuf, 0xB6);
2655 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2656 %}
2657
2658 enc_class Push_ResultXD(regD dst) %{
2659 MacroAssembler _masm(&cbuf);
2660 __ fstp_d(Address(rsp, 0));
2661 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2662 __ addptr(rsp, 8);
2663 %}
2664
2665 enc_class Push_SrcXD(regD src) %{
2666 MacroAssembler _masm(&cbuf);
2667 __ subptr(rsp, 8);
2668 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2669 __ fld_d(Address(rsp, 0));
2670 %}
2671
2672
2673 enc_class enc_rethrow()
2674 %{
2675 cbuf.set_insts_mark();
2676 emit_opcode(cbuf, 0xE9); // jmp entry
2677 emit_d32_reloc(cbuf,
2678 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2679 runtime_call_Relocation::spec(),
2680 RELOC_DISP32);
2681 %}
2682
2683 %}
2684
2685
2686
2687 //----------FRAME--------------------------------------------------------------
2688 // Definition of frame structure and management information.
2689 //
2690 // S T A C K L A Y O U T Allocators stack-slot number
2691 // | (to get allocators register number
2692 // G Owned by | | v add OptoReg::stack0())
2693 // r CALLER | |
2694 // o | +--------+ pad to even-align allocators stack-slot
2695 // w V | pad0 | numbers; owned by CALLER
2696 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2697 // h ^ | in | 5
2698 // | | args | 4 Holes in incoming args owned by SELF
2699 // | | | | 3
2700 // | | +--------+
2701 // V | | old out| Empty on Intel, window on Sparc
2702 // | old |preserve| Must be even aligned.
2703 // | SP-+--------+----> Matcher::_old_SP, even aligned
2704 // | | in | 3 area for Intel ret address
2705 // Owned by |preserve| Empty on Sparc.
2706 // SELF +--------+
2707 // | | pad2 | 2 pad to align old SP
2708 // | +--------+ 1
2709 // | | locks | 0
2710 // | +--------+----> OptoReg::stack0(), even aligned
2711 // | | pad1 | 11 pad to align new SP
2712 // | +--------+
2713 // | | | 10
2714 // | | spills | 9 spills
2715 // V | | 8 (pad0 slot for callee)
2716 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2717 // ^ | out | 7
2718 // | | args | 6 Holes in outgoing args owned by CALLEE
2719 // Owned by +--------+
2720 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2721 // | new |preserve| Must be even-aligned.
2722 // | SP-+--------+----> Matcher::_new_SP, even aligned
2723 // | | |
2724 //
2725 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2726 // known from SELF's arguments and the Java calling convention.
2727 // Region 6-7 is determined per call site.
2728 // Note 2: If the calling convention leaves holes in the incoming argument
2729 // area, those holes are owned by SELF. Holes in the outgoing area
2730 // are owned by the CALLEE. Holes should not be nessecary in the
2731 // incoming area, as the Java calling convention is completely under
2732 // the control of the AD file. Doubles can be sorted and packed to
2733 // avoid holes. Holes in the outgoing arguments may be nessecary for
2734 // varargs C calling conventions.
2735 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2736 // even aligned with pad0 as needed.
2737 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2738 // region 6-11 is even aligned; it may be padded out more so that
2739 // the region from SP to FP meets the minimum stack alignment.
2740 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2741 // alignment. Region 11, pad1, may be dynamically extended so that
2742 // SP meets the minimum alignment.
2743
2744 frame
2745 %{
2746 // What direction does stack grow in (assumed to be same for C & Java)
2747 stack_direction(TOWARDS_LOW);
2748
2749 // These three registers define part of the calling convention
2750 // between compiled code and the interpreter.
2751 inline_cache_reg(RAX); // Inline Cache Register
2752 interpreter_method_oop_reg(RBX); // Method Oop Register when
2753 // calling interpreter
2754
2755 // Optional: name the operand used by cisc-spilling to access
2756 // [stack_pointer + offset]
2757 cisc_spilling_operand_name(indOffset32);
2758
2759 // Number of stack slots consumed by locking an object
2760 sync_stack_slots(2);
2761
2762 // Compiled code's Frame Pointer
2763 frame_pointer(RSP);
2764
2765 // Interpreter stores its frame pointer in a register which is
2766 // stored to the stack by I2CAdaptors.
2767 // I2CAdaptors convert from interpreted java to compiled java.
2768 interpreter_frame_pointer(RBP);
2769
2770 // Stack alignment requirement
2771 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2772
2773 // Number of stack slots between incoming argument block and the start of
2774 // a new frame. The PROLOG must add this many slots to the stack. The
2775 // EPILOG must remove this many slots. amd64 needs two slots for
2776 // return address.
2777 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2778
2779 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2780 // for calls to C. Supports the var-args backing area for register parms.
2781 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2782
2783 // The after-PROLOG location of the return address. Location of
2784 // return address specifies a type (REG or STACK) and a number
2785 // representing the register number (i.e. - use a register name) or
2786 // stack slot.
2787 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2788 // Otherwise, it is above the locks and verification slot and alignment word
2789 return_addr(STACK - 2 +
2790 align_up((Compile::current()->in_preserve_stack_slots() +
2791 Compile::current()->fixed_slots()),
2792 stack_alignment_in_slots()));
2793
2794 // Body of function which returns an integer array locating
2795 // arguments either in registers or in stack slots. Passed an array
2796 // of ideal registers called "sig" and a "length" count. Stack-slot
2797 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2798 // arguments for a CALLEE. Incoming stack arguments are
2799 // automatically biased by the preserve_stack_slots field above.
2800
2801 calling_convention
2802 %{
2803 // No difference between ingoing/outgoing just pass false
2804 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2805 %}
2806
2807 c_calling_convention
2808 %{
2809 // This is obviously always outgoing
2810 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2811 %}
2812
2813 // Location of compiled Java return values. Same as C for now.
2814 return_value
2815 %{
2816 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2817 "only return normal values");
2818
2819 static const int lo[Op_RegL + 1] = {
2820 0,
2821 0,
2822 RAX_num, // Op_RegN
2823 RAX_num, // Op_RegI
2824 RAX_num, // Op_RegP
2825 XMM0_num, // Op_RegF
2826 XMM0_num, // Op_RegD
2827 RAX_num // Op_RegL
2828 };
2829 static const int hi[Op_RegL + 1] = {
2830 0,
2831 0,
2832 OptoReg::Bad, // Op_RegN
2833 OptoReg::Bad, // Op_RegI
2834 RAX_H_num, // Op_RegP
2835 OptoReg::Bad, // Op_RegF
2836 XMM0b_num, // Op_RegD
2837 RAX_H_num // Op_RegL
2838 };
2839 // Excluded flags and vector registers.
2840 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2841 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2842 %}
2843 %}
2844
2845 //----------ATTRIBUTES---------------------------------------------------------
2846 //----------Operand Attributes-------------------------------------------------
2847 op_attrib op_cost(0); // Required cost attribute
2848
2849 //----------Instruction Attributes---------------------------------------------
2850 ins_attrib ins_cost(100); // Required cost attribute
2851 ins_attrib ins_size(8); // Required size attribute (in bits)
2852 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2853 // a non-matching short branch variant
2854 // of some long branch?
2855 ins_attrib ins_alignment(1); // Required alignment attribute (must
2856 // be a power of 2) specifies the
2857 // alignment that some part of the
2858 // instruction (not necessarily the
2859 // start) requires. If > 1, a
2860 // compute_padding() function must be
2861 // provided for the instruction
2862
2863 //----------OPERANDS-----------------------------------------------------------
2864 // Operand definitions must precede instruction definitions for correct parsing
2865 // in the ADLC because operands constitute user defined types which are used in
2866 // instruction definitions.
2867
2868 //----------Simple Operands----------------------------------------------------
2869 // Immediate Operands
2870 // Integer Immediate
2871 operand immI()
2872 %{
2873 match(ConI);
2874
2875 op_cost(10);
2876 format %{ %}
2877 interface(CONST_INTER);
2878 %}
2879
2880 // Constant for test vs zero
2881 operand immI_0()
2882 %{
2883 predicate(n->get_int() == 0);
2884 match(ConI);
2885
2886 op_cost(0);
2887 format %{ %}
2888 interface(CONST_INTER);
2889 %}
2890
2891 // Constant for increment
2892 operand immI_1()
2893 %{
2894 predicate(n->get_int() == 1);
2895 match(ConI);
2896
2897 op_cost(0);
2898 format %{ %}
2899 interface(CONST_INTER);
2900 %}
2901
2902 // Constant for decrement
2903 operand immI_M1()
2904 %{
2905 predicate(n->get_int() == -1);
2906 match(ConI);
2907
2908 op_cost(0);
2909 format %{ %}
2910 interface(CONST_INTER);
2911 %}
2912
2913 operand immI_2()
2914 %{
2915 predicate(n->get_int() == 2);
2916 match(ConI);
2917
2918 op_cost(0);
2919 format %{ %}
2920 interface(CONST_INTER);
2921 %}
2922
2923 operand immI_4()
2924 %{
2925 predicate(n->get_int() == 4);
2926 match(ConI);
2927
2928 op_cost(0);
2929 format %{ %}
2930 interface(CONST_INTER);
2931 %}
2932
2933 operand immI_8()
2934 %{
2935 predicate(n->get_int() == 8);
2936 match(ConI);
2937
2938 op_cost(0);
2939 format %{ %}
2940 interface(CONST_INTER);
2941 %}
2942
2943 // Valid scale values for addressing modes
2944 operand immI2()
2945 %{
2946 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2947 match(ConI);
2948
2949 format %{ %}
2950 interface(CONST_INTER);
2951 %}
2952
2953 operand immI8()
2954 %{
2955 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2956 match(ConI);
2957
2958 op_cost(5);
2959 format %{ %}
2960 interface(CONST_INTER);
2961 %}
2962
2963 operand immU8()
2964 %{
2965 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2966 match(ConI);
2967
2968 op_cost(5);
2969 format %{ %}
2970 interface(CONST_INTER);
2971 %}
2972
2973 operand immI16()
2974 %{
2975 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2976 match(ConI);
2977
2978 op_cost(10);
2979 format %{ %}
2980 interface(CONST_INTER);
2981 %}
2982
2983 // Int Immediate non-negative
2984 operand immU31()
2985 %{
2986 predicate(n->get_int() >= 0);
2987 match(ConI);
2988
2989 op_cost(0);
2990 format %{ %}
2991 interface(CONST_INTER);
2992 %}
2993
2994 // Constant for long shifts
2995 operand immI_32()
2996 %{
2997 predicate( n->get_int() == 32 );
2998 match(ConI);
2999
3000 op_cost(0);
3001 format %{ %}
3002 interface(CONST_INTER);
3003 %}
3004
3005 // Constant for long shifts
3006 operand immI_64()
3007 %{
3008 predicate( n->get_int() == 64 );
3009 match(ConI);
3010
3011 op_cost(0);
3012 format %{ %}
3013 interface(CONST_INTER);
3014 %}
3015
3016 // Pointer Immediate
3017 operand immP()
3018 %{
3019 match(ConP);
3020
3021 op_cost(10);
3022 format %{ %}
3023 interface(CONST_INTER);
3024 %}
3025
3026 // NULL Pointer Immediate
3027 operand immP0()
3028 %{
3029 predicate(n->get_ptr() == 0);
3030 match(ConP);
3031
3032 op_cost(5);
3033 format %{ %}
3034 interface(CONST_INTER);
3035 %}
3036
3037 // Pointer Immediate
3038 operand immN() %{
3039 match(ConN);
3040
3041 op_cost(10);
3042 format %{ %}
3043 interface(CONST_INTER);
3044 %}
3045
3046 operand immNKlass() %{
3047 match(ConNKlass);
3048
3049 op_cost(10);
3050 format %{ %}
3051 interface(CONST_INTER);
3052 %}
3053
3054 // NULL Pointer Immediate
3055 operand immN0() %{
3056 predicate(n->get_narrowcon() == 0);
3057 match(ConN);
3058
3059 op_cost(5);
3060 format %{ %}
3061 interface(CONST_INTER);
3062 %}
3063
3064 operand immP31()
3065 %{
3066 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3067 && (n->get_ptr() >> 31) == 0);
3068 match(ConP);
3069
3070 op_cost(5);
3071 format %{ %}
3072 interface(CONST_INTER);
3073 %}
3074
3075
3076 // Long Immediate
3077 operand immL()
3078 %{
3079 match(ConL);
3080
3081 op_cost(20);
3082 format %{ %}
3083 interface(CONST_INTER);
3084 %}
3085
3086 // Long Immediate 8-bit
3087 operand immL8()
3088 %{
3089 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3090 match(ConL);
3091
3092 op_cost(5);
3093 format %{ %}
3094 interface(CONST_INTER);
3095 %}
3096
3097 // Long Immediate 32-bit unsigned
3098 operand immUL32()
3099 %{
3100 predicate(n->get_long() == (unsigned int) (n->get_long()));
3101 match(ConL);
3102
3103 op_cost(10);
3104 format %{ %}
3105 interface(CONST_INTER);
3106 %}
3107
3108 // Long Immediate 32-bit signed
3109 operand immL32()
3110 %{
3111 predicate(n->get_long() == (int) (n->get_long()));
3112 match(ConL);
3113
3114 op_cost(15);
3115 format %{ %}
3116 interface(CONST_INTER);
3117 %}
3118
3119 operand immL_Pow2()
3120 %{
3121 predicate(is_power_of_2((julong)n->get_long()));
3122 match(ConL);
3123
3124 op_cost(15);
3125 format %{ %}
3126 interface(CONST_INTER);
3127 %}
3128
3129 operand immL_NotPow2()
3130 %{
3131 predicate(is_power_of_2((julong)~n->get_long()));
3132 match(ConL);
3133
3134 op_cost(15);
3135 format %{ %}
3136 interface(CONST_INTER);
3137 %}
3138
3139 // Long Immediate zero
3140 operand immL0()
3141 %{
3142 predicate(n->get_long() == 0L);
3143 match(ConL);
3144
3145 op_cost(10);
3146 format %{ %}
3147 interface(CONST_INTER);
3148 %}
3149
3150 // Constant for increment
3151 operand immL1()
3152 %{
3153 predicate(n->get_long() == 1);
3154 match(ConL);
3155
3156 format %{ %}
3157 interface(CONST_INTER);
3158 %}
3159
3160 // Constant for decrement
3161 operand immL_M1()
3162 %{
3163 predicate(n->get_long() == -1);
3164 match(ConL);
3165
3166 format %{ %}
3167 interface(CONST_INTER);
3168 %}
3169
3170 // Long Immediate: the value 10
3171 operand immL10()
3172 %{
3173 predicate(n->get_long() == 10);
3174 match(ConL);
3175
3176 format %{ %}
3177 interface(CONST_INTER);
3178 %}
3179
3180 // Long immediate from 0 to 127.
3181 // Used for a shorter form of long mul by 10.
3182 operand immL_127()
3183 %{
3184 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3185 match(ConL);
3186
3187 op_cost(10);
3188 format %{ %}
3189 interface(CONST_INTER);
3190 %}
3191
3192 // Long Immediate: low 32-bit mask
3193 operand immL_32bits()
3194 %{
3195 predicate(n->get_long() == 0xFFFFFFFFL);
3196 match(ConL);
3197 op_cost(20);
3198
3199 format %{ %}
3200 interface(CONST_INTER);
3201 %}
3202
3203 // Float Immediate zero
3204 operand immF0()
3205 %{
3206 predicate(jint_cast(n->getf()) == 0);
3207 match(ConF);
3208
3209 op_cost(5);
3210 format %{ %}
3211 interface(CONST_INTER);
3212 %}
3213
3214 // Float Immediate
3215 operand immF()
3216 %{
3217 match(ConF);
3218
3219 op_cost(15);
3220 format %{ %}
3221 interface(CONST_INTER);
3222 %}
3223
3224 // Double Immediate zero
3225 operand immD0()
3226 %{
3227 predicate(jlong_cast(n->getd()) == 0);
3228 match(ConD);
3229
3230 op_cost(5);
3231 format %{ %}
3232 interface(CONST_INTER);
3233 %}
3234
3235 // Double Immediate
3236 operand immD()
3237 %{
3238 match(ConD);
3239
3240 op_cost(15);
3241 format %{ %}
3242 interface(CONST_INTER);
3243 %}
3244
3245 // Immediates for special shifts (sign extend)
3246
3247 // Constants for increment
3248 operand immI_16()
3249 %{
3250 predicate(n->get_int() == 16);
3251 match(ConI);
3252
3253 format %{ %}
3254 interface(CONST_INTER);
3255 %}
3256
3257 operand immI_24()
3258 %{
3259 predicate(n->get_int() == 24);
3260 match(ConI);
3261
3262 format %{ %}
3263 interface(CONST_INTER);
3264 %}
3265
3266 // Constant for byte-wide masking
3267 operand immI_255()
3268 %{
3269 predicate(n->get_int() == 255);
3270 match(ConI);
3271
3272 format %{ %}
3273 interface(CONST_INTER);
3274 %}
3275
3276 // Constant for short-wide masking
3277 operand immI_65535()
3278 %{
3279 predicate(n->get_int() == 65535);
3280 match(ConI);
3281
3282 format %{ %}
3283 interface(CONST_INTER);
3284 %}
3285
3286 // Constant for byte-wide masking
3287 operand immL_255()
3288 %{
3289 predicate(n->get_long() == 255);
3290 match(ConL);
3291
3292 format %{ %}
3293 interface(CONST_INTER);
3294 %}
3295
3296 // Constant for short-wide masking
3297 operand immL_65535()
3298 %{
3299 predicate(n->get_long() == 65535);
3300 match(ConL);
3301
3302 format %{ %}
3303 interface(CONST_INTER);
3304 %}
3305
3306 // Register Operands
3307 // Integer Register
3308 operand rRegI()
3309 %{
3310 constraint(ALLOC_IN_RC(int_reg));
3311 match(RegI);
3312
3313 match(rax_RegI);
3314 match(rbx_RegI);
3315 match(rcx_RegI);
3316 match(rdx_RegI);
3317 match(rdi_RegI);
3318
3319 format %{ %}
3320 interface(REG_INTER);
3321 %}
3322
3323 // Special Registers
3324 operand rax_RegI()
3325 %{
3326 constraint(ALLOC_IN_RC(int_rax_reg));
3327 match(RegI);
3328 match(rRegI);
3329
3330 format %{ "RAX" %}
3331 interface(REG_INTER);
3332 %}
3333
3334 // Special Registers
3335 operand rbx_RegI()
3336 %{
3337 constraint(ALLOC_IN_RC(int_rbx_reg));
3338 match(RegI);
3339 match(rRegI);
3340
3341 format %{ "RBX" %}
3342 interface(REG_INTER);
3343 %}
3344
3345 operand rcx_RegI()
3346 %{
3347 constraint(ALLOC_IN_RC(int_rcx_reg));
3348 match(RegI);
3349 match(rRegI);
3350
3351 format %{ "RCX" %}
3352 interface(REG_INTER);
3353 %}
3354
3355 operand rdx_RegI()
3356 %{
3357 constraint(ALLOC_IN_RC(int_rdx_reg));
3358 match(RegI);
3359 match(rRegI);
3360
3361 format %{ "RDX" %}
3362 interface(REG_INTER);
3363 %}
3364
3365 operand rdi_RegI()
3366 %{
3367 constraint(ALLOC_IN_RC(int_rdi_reg));
3368 match(RegI);
3369 match(rRegI);
3370
3371 format %{ "RDI" %}
3372 interface(REG_INTER);
3373 %}
3374
3375 operand no_rcx_RegI()
3376 %{
3377 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3378 match(RegI);
3379 match(rax_RegI);
3380 match(rbx_RegI);
3381 match(rdx_RegI);
3382 match(rdi_RegI);
3383
3384 format %{ %}
3385 interface(REG_INTER);
3386 %}
3387
3388 operand no_rax_rdx_RegI()
3389 %{
3390 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3391 match(RegI);
3392 match(rbx_RegI);
3393 match(rcx_RegI);
3394 match(rdi_RegI);
3395
3396 format %{ %}
3397 interface(REG_INTER);
3398 %}
3399
3400 // Pointer Register
3401 operand any_RegP()
3402 %{
3403 constraint(ALLOC_IN_RC(any_reg));
3404 match(RegP);
3405 match(rax_RegP);
3406 match(rbx_RegP);
3407 match(rdi_RegP);
3408 match(rsi_RegP);
3409 match(rbp_RegP);
3410 match(r15_RegP);
3411 match(rRegP);
3412
3413 format %{ %}
3414 interface(REG_INTER);
3415 %}
3416
3417 operand rRegP()
3418 %{
3419 constraint(ALLOC_IN_RC(ptr_reg));
3420 match(RegP);
3421 match(rax_RegP);
3422 match(rbx_RegP);
3423 match(rdi_RegP);
3424 match(rsi_RegP);
3425 match(rbp_RegP); // See Q&A below about
3426 match(r15_RegP); // r15_RegP and rbp_RegP.
3427
3428 format %{ %}
3429 interface(REG_INTER);
3430 %}
3431
3432 operand rRegN() %{
3433 constraint(ALLOC_IN_RC(int_reg));
3434 match(RegN);
3435
3436 format %{ %}
3437 interface(REG_INTER);
3438 %}
3439
3440 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3441 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3442 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3443 // The output of an instruction is controlled by the allocator, which respects
3444 // register class masks, not match rules. Unless an instruction mentions
3445 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3446 // by the allocator as an input.
3447 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3448 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3449 // result, RBP is not included in the output of the instruction either.
3450
3451 operand no_rax_RegP()
3452 %{
3453 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3454 match(RegP);
3455 match(rbx_RegP);
3456 match(rsi_RegP);
3457 match(rdi_RegP);
3458
3459 format %{ %}
3460 interface(REG_INTER);
3461 %}
3462
3463 // This operand is not allowed to use RBP even if
3464 // RBP is not used to hold the frame pointer.
3465 operand no_rbp_RegP()
3466 %{
3467 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3468 match(RegP);
3469 match(rbx_RegP);
3470 match(rsi_RegP);
3471 match(rdi_RegP);
3472
3473 format %{ %}
3474 interface(REG_INTER);
3475 %}
3476
3477 operand no_rax_rbx_RegP()
3478 %{
3479 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3480 match(RegP);
3481 match(rsi_RegP);
3482 match(rdi_RegP);
3483
3484 format %{ %}
3485 interface(REG_INTER);
3486 %}
3487
3488 // Special Registers
3489 // Return a pointer value
3490 operand rax_RegP()
3491 %{
3492 constraint(ALLOC_IN_RC(ptr_rax_reg));
3493 match(RegP);
3494 match(rRegP);
3495
3496 format %{ %}
3497 interface(REG_INTER);
3498 %}
3499
3500 // Special Registers
3501 // Return a compressed pointer value
3502 operand rax_RegN()
3503 %{
3504 constraint(ALLOC_IN_RC(int_rax_reg));
3505 match(RegN);
3506 match(rRegN);
3507
3508 format %{ %}
3509 interface(REG_INTER);
3510 %}
3511
3512 // Used in AtomicAdd
3513 operand rbx_RegP()
3514 %{
3515 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3516 match(RegP);
3517 match(rRegP);
3518
3519 format %{ %}
3520 interface(REG_INTER);
3521 %}
3522
3523 operand rsi_RegP()
3524 %{
3525 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3526 match(RegP);
3527 match(rRegP);
3528
3529 format %{ %}
3530 interface(REG_INTER);
3531 %}
3532
3533 operand rbp_RegP()
3534 %{
3535 constraint(ALLOC_IN_RC(ptr_rbp_reg));
3536 match(RegP);
3537 match(rRegP);
3538
3539 format %{ %}
3540 interface(REG_INTER);
3541 %}
3542
3543 // Used in rep stosq
3544 operand rdi_RegP()
3545 %{
3546 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3547 match(RegP);
3548 match(rRegP);
3549
3550 format %{ %}
3551 interface(REG_INTER);
3552 %}
3553
3554 operand r15_RegP()
3555 %{
3556 constraint(ALLOC_IN_RC(ptr_r15_reg));
3557 match(RegP);
3558 match(rRegP);
3559
3560 format %{ %}
3561 interface(REG_INTER);
3562 %}
3563
3564 operand rRegL()
3565 %{
3566 constraint(ALLOC_IN_RC(long_reg));
3567 match(RegL);
3568 match(rax_RegL);
3569 match(rdx_RegL);
3570
3571 format %{ %}
3572 interface(REG_INTER);
3573 %}
3574
3575 // Special Registers
3576 operand no_rax_rdx_RegL()
3577 %{
3578 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3579 match(RegL);
3580 match(rRegL);
3581
3582 format %{ %}
3583 interface(REG_INTER);
3584 %}
3585
3586 operand no_rax_RegL()
3587 %{
3588 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3589 match(RegL);
3590 match(rRegL);
3591 match(rdx_RegL);
3592
3593 format %{ %}
3594 interface(REG_INTER);
3595 %}
3596
3597 operand no_rcx_RegL()
3598 %{
3599 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3600 match(RegL);
3601 match(rRegL);
3602
3603 format %{ %}
3604 interface(REG_INTER);
3605 %}
3606
3607 operand rax_RegL()
3608 %{
3609 constraint(ALLOC_IN_RC(long_rax_reg));
3610 match(RegL);
3611 match(rRegL);
3612
3613 format %{ "RAX" %}
3614 interface(REG_INTER);
3615 %}
3616
3617 operand rcx_RegL()
3618 %{
3619 constraint(ALLOC_IN_RC(long_rcx_reg));
3620 match(RegL);
3621 match(rRegL);
3622
3623 format %{ %}
3624 interface(REG_INTER);
3625 %}
3626
3627 operand rdx_RegL()
3628 %{
3629 constraint(ALLOC_IN_RC(long_rdx_reg));
3630 match(RegL);
3631 match(rRegL);
3632
3633 format %{ %}
3634 interface(REG_INTER);
3635 %}
3636
3637 // Flags register, used as output of compare instructions
3638 operand rFlagsReg()
3639 %{
3640 constraint(ALLOC_IN_RC(int_flags));
3641 match(RegFlags);
3642
3643 format %{ "RFLAGS" %}
3644 interface(REG_INTER);
3645 %}
3646
3647 // Flags register, used as output of FLOATING POINT compare instructions
3648 operand rFlagsRegU()
3649 %{
3650 constraint(ALLOC_IN_RC(int_flags));
3651 match(RegFlags);
3652
3653 format %{ "RFLAGS_U" %}
3654 interface(REG_INTER);
3655 %}
3656
3657 operand rFlagsRegUCF() %{
3658 constraint(ALLOC_IN_RC(int_flags));
3659 match(RegFlags);
3660 predicate(false);
3661
3662 format %{ "RFLAGS_U_CF" %}
3663 interface(REG_INTER);
3664 %}
3665
3666 // Float register operands
3667 operand regF() %{
3668 constraint(ALLOC_IN_RC(float_reg));
3669 match(RegF);
3670
3671 format %{ %}
3672 interface(REG_INTER);
3673 %}
3674
3675 // Float register operands
3676 operand legRegF() %{
3677 constraint(ALLOC_IN_RC(float_reg_legacy));
3678 match(RegF);
3679
3680 format %{ %}
3681 interface(REG_INTER);
3682 %}
3683
3684 // Float register operands
3685 operand vlRegF() %{
3686 constraint(ALLOC_IN_RC(float_reg_vl));
3687 match(RegF);
3688
3689 format %{ %}
3690 interface(REG_INTER);
3691 %}
3692
3693 // Double register operands
3694 operand regD() %{
3695 constraint(ALLOC_IN_RC(double_reg));
3696 match(RegD);
3697
3698 format %{ %}
3699 interface(REG_INTER);
3700 %}
3701
3702 // Double register operands
3703 operand legRegD() %{
3704 constraint(ALLOC_IN_RC(double_reg_legacy));
3705 match(RegD);
3706
3707 format %{ %}
3708 interface(REG_INTER);
3709 %}
3710
3711 // Double register operands
3712 operand vlRegD() %{
3713 constraint(ALLOC_IN_RC(double_reg_vl));
3714 match(RegD);
3715
3716 format %{ %}
3717 interface(REG_INTER);
3718 %}
3719
3720 //----------Memory Operands----------------------------------------------------
3721 // Direct Memory Operand
3722 // operand direct(immP addr)
3723 // %{
3724 // match(addr);
3725
3726 // format %{ "[$addr]" %}
3727 // interface(MEMORY_INTER) %{
3728 // base(0xFFFFFFFF);
3729 // index(0x4);
3730 // scale(0x0);
3731 // disp($addr);
3732 // %}
3733 // %}
3734
3735 // Indirect Memory Operand
3736 operand indirect(any_RegP reg)
3737 %{
3738 constraint(ALLOC_IN_RC(ptr_reg));
3739 match(reg);
3740
3741 format %{ "[$reg]" %}
3742 interface(MEMORY_INTER) %{
3743 base($reg);
3744 index(0x4);
3745 scale(0x0);
3746 disp(0x0);
3747 %}
3748 %}
3749
3750 // Indirect Memory Plus Short Offset Operand
3751 operand indOffset8(any_RegP reg, immL8 off)
3752 %{
3753 constraint(ALLOC_IN_RC(ptr_reg));
3754 match(AddP reg off);
3755
3756 format %{ "[$reg + $off (8-bit)]" %}
3757 interface(MEMORY_INTER) %{
3758 base($reg);
3759 index(0x4);
3760 scale(0x0);
3761 disp($off);
3762 %}
3763 %}
3764
3765 // Indirect Memory Plus Long Offset Operand
3766 operand indOffset32(any_RegP reg, immL32 off)
3767 %{
3768 constraint(ALLOC_IN_RC(ptr_reg));
3769 match(AddP reg off);
3770
3771 format %{ "[$reg + $off (32-bit)]" %}
3772 interface(MEMORY_INTER) %{
3773 base($reg);
3774 index(0x4);
3775 scale(0x0);
3776 disp($off);
3777 %}
3778 %}
3779
3780 // Indirect Memory Plus Index Register Plus Offset Operand
3781 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3782 %{
3783 constraint(ALLOC_IN_RC(ptr_reg));
3784 match(AddP (AddP reg lreg) off);
3785
3786 op_cost(10);
3787 format %{"[$reg + $off + $lreg]" %}
3788 interface(MEMORY_INTER) %{
3789 base($reg);
3790 index($lreg);
3791 scale(0x0);
3792 disp($off);
3793 %}
3794 %}
3795
3796 // Indirect Memory Plus Index Register Plus Offset Operand
3797 operand indIndex(any_RegP reg, rRegL lreg)
3798 %{
3799 constraint(ALLOC_IN_RC(ptr_reg));
3800 match(AddP reg lreg);
3801
3802 op_cost(10);
3803 format %{"[$reg + $lreg]" %}
3804 interface(MEMORY_INTER) %{
3805 base($reg);
3806 index($lreg);
3807 scale(0x0);
3808 disp(0x0);
3809 %}
3810 %}
3811
3812 // Indirect Memory Times Scale Plus Index Register
3813 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3814 %{
3815 constraint(ALLOC_IN_RC(ptr_reg));
3816 match(AddP reg (LShiftL lreg scale));
3817
3818 op_cost(10);
3819 format %{"[$reg + $lreg << $scale]" %}
3820 interface(MEMORY_INTER) %{
3821 base($reg);
3822 index($lreg);
3823 scale($scale);
3824 disp(0x0);
3825 %}
3826 %}
3827
3828 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3829 %{
3830 constraint(ALLOC_IN_RC(ptr_reg));
3831 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3832 match(AddP reg (LShiftL (ConvI2L idx) scale));
3833
3834 op_cost(10);
3835 format %{"[$reg + pos $idx << $scale]" %}
3836 interface(MEMORY_INTER) %{
3837 base($reg);
3838 index($idx);
3839 scale($scale);
3840 disp(0x0);
3841 %}
3842 %}
3843
3844 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3845 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3846 %{
3847 constraint(ALLOC_IN_RC(ptr_reg));
3848 match(AddP (AddP reg (LShiftL lreg scale)) off);
3849
3850 op_cost(10);
3851 format %{"[$reg + $off + $lreg << $scale]" %}
3852 interface(MEMORY_INTER) %{
3853 base($reg);
3854 index($lreg);
3855 scale($scale);
3856 disp($off);
3857 %}
3858 %}
3859
3860 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3861 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3862 %{
3863 constraint(ALLOC_IN_RC(ptr_reg));
3864 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3865 match(AddP (AddP reg (ConvI2L idx)) off);
3866
3867 op_cost(10);
3868 format %{"[$reg + $off + $idx]" %}
3869 interface(MEMORY_INTER) %{
3870 base($reg);
3871 index($idx);
3872 scale(0x0);
3873 disp($off);
3874 %}
3875 %}
3876
3877 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3878 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3879 %{
3880 constraint(ALLOC_IN_RC(ptr_reg));
3881 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3882 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3883
3884 op_cost(10);
3885 format %{"[$reg + $off + $idx << $scale]" %}
3886 interface(MEMORY_INTER) %{
3887 base($reg);
3888 index($idx);
3889 scale($scale);
3890 disp($off);
3891 %}
3892 %}
3893
3894 // Indirect Narrow Oop Plus Offset Operand
3895 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3896 // we can't free r12 even with CompressedOops::base() == NULL.
3897 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3898 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3899 constraint(ALLOC_IN_RC(ptr_reg));
3900 match(AddP (DecodeN reg) off);
3901
3902 op_cost(10);
3903 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3904 interface(MEMORY_INTER) %{
3905 base(0xc); // R12
3906 index($reg);
3907 scale(0x3);
3908 disp($off);
3909 %}
3910 %}
3911
3912 // Indirect Memory Operand
3913 operand indirectNarrow(rRegN reg)
3914 %{
3915 predicate(CompressedOops::shift() == 0);
3916 constraint(ALLOC_IN_RC(ptr_reg));
3917 match(DecodeN reg);
3918
3919 format %{ "[$reg]" %}
3920 interface(MEMORY_INTER) %{
3921 base($reg);
3922 index(0x4);
3923 scale(0x0);
3924 disp(0x0);
3925 %}
3926 %}
3927
3928 // Indirect Memory Plus Short Offset Operand
3929 operand indOffset8Narrow(rRegN reg, immL8 off)
3930 %{
3931 predicate(CompressedOops::shift() == 0);
3932 constraint(ALLOC_IN_RC(ptr_reg));
3933 match(AddP (DecodeN reg) off);
3934
3935 format %{ "[$reg + $off (8-bit)]" %}
3936 interface(MEMORY_INTER) %{
3937 base($reg);
3938 index(0x4);
3939 scale(0x0);
3940 disp($off);
3941 %}
3942 %}
3943
3944 // Indirect Memory Plus Long Offset Operand
3945 operand indOffset32Narrow(rRegN reg, immL32 off)
3946 %{
3947 predicate(CompressedOops::shift() == 0);
3948 constraint(ALLOC_IN_RC(ptr_reg));
3949 match(AddP (DecodeN reg) off);
3950
3951 format %{ "[$reg + $off (32-bit)]" %}
3952 interface(MEMORY_INTER) %{
3953 base($reg);
3954 index(0x4);
3955 scale(0x0);
3956 disp($off);
3957 %}
3958 %}
3959
3960 // Indirect Memory Plus Index Register Plus Offset Operand
3961 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3962 %{
3963 predicate(CompressedOops::shift() == 0);
3964 constraint(ALLOC_IN_RC(ptr_reg));
3965 match(AddP (AddP (DecodeN reg) lreg) off);
3966
3967 op_cost(10);
3968 format %{"[$reg + $off + $lreg]" %}
3969 interface(MEMORY_INTER) %{
3970 base($reg);
3971 index($lreg);
3972 scale(0x0);
3973 disp($off);
3974 %}
3975 %}
3976
3977 // Indirect Memory Plus Index Register Plus Offset Operand
3978 operand indIndexNarrow(rRegN reg, rRegL lreg)
3979 %{
3980 predicate(CompressedOops::shift() == 0);
3981 constraint(ALLOC_IN_RC(ptr_reg));
3982 match(AddP (DecodeN reg) lreg);
3983
3984 op_cost(10);
3985 format %{"[$reg + $lreg]" %}
3986 interface(MEMORY_INTER) %{
3987 base($reg);
3988 index($lreg);
3989 scale(0x0);
3990 disp(0x0);
3991 %}
3992 %}
3993
3994 // Indirect Memory Times Scale Plus Index Register
3995 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3996 %{
3997 predicate(CompressedOops::shift() == 0);
3998 constraint(ALLOC_IN_RC(ptr_reg));
3999 match(AddP (DecodeN reg) (LShiftL lreg scale));
4000
4001 op_cost(10);
4002 format %{"[$reg + $lreg << $scale]" %}
4003 interface(MEMORY_INTER) %{
4004 base($reg);
4005 index($lreg);
4006 scale($scale);
4007 disp(0x0);
4008 %}
4009 %}
4010
4011 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4012 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4013 %{
4014 predicate(CompressedOops::shift() == 0);
4015 constraint(ALLOC_IN_RC(ptr_reg));
4016 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4017
4018 op_cost(10);
4019 format %{"[$reg + $off + $lreg << $scale]" %}
4020 interface(MEMORY_INTER) %{
4021 base($reg);
4022 index($lreg);
4023 scale($scale);
4024 disp($off);
4025 %}
4026 %}
4027
4028 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4029 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4030 %{
4031 constraint(ALLOC_IN_RC(ptr_reg));
4032 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4033 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4034
4035 op_cost(10);
4036 format %{"[$reg + $off + $idx]" %}
4037 interface(MEMORY_INTER) %{
4038 base($reg);
4039 index($idx);
4040 scale(0x0);
4041 disp($off);
4042 %}
4043 %}
4044
4045 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4046 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4047 %{
4048 constraint(ALLOC_IN_RC(ptr_reg));
4049 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4050 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4051
4052 op_cost(10);
4053 format %{"[$reg + $off + $idx << $scale]" %}
4054 interface(MEMORY_INTER) %{
4055 base($reg);
4056 index($idx);
4057 scale($scale);
4058 disp($off);
4059 %}
4060 %}
4061
4062 //----------Special Memory Operands--------------------------------------------
4063 // Stack Slot Operand - This operand is used for loading and storing temporary
4064 // values on the stack where a match requires a value to
4065 // flow through memory.
4066 operand stackSlotP(sRegP reg)
4067 %{
4068 constraint(ALLOC_IN_RC(stack_slots));
4069 // No match rule because this operand is only generated in matching
4070
4071 format %{ "[$reg]" %}
4072 interface(MEMORY_INTER) %{
4073 base(0x4); // RSP
4074 index(0x4); // No Index
4075 scale(0x0); // No Scale
4076 disp($reg); // Stack Offset
4077 %}
4078 %}
4079
4080 operand stackSlotI(sRegI reg)
4081 %{
4082 constraint(ALLOC_IN_RC(stack_slots));
4083 // No match rule because this operand is only generated in matching
4084
4085 format %{ "[$reg]" %}
4086 interface(MEMORY_INTER) %{
4087 base(0x4); // RSP
4088 index(0x4); // No Index
4089 scale(0x0); // No Scale
4090 disp($reg); // Stack Offset
4091 %}
4092 %}
4093
4094 operand stackSlotF(sRegF reg)
4095 %{
4096 constraint(ALLOC_IN_RC(stack_slots));
4097 // No match rule because this operand is only generated in matching
4098
4099 format %{ "[$reg]" %}
4100 interface(MEMORY_INTER) %{
4101 base(0x4); // RSP
4102 index(0x4); // No Index
4103 scale(0x0); // No Scale
4104 disp($reg); // Stack Offset
4105 %}
4106 %}
4107
4108 operand stackSlotD(sRegD reg)
4109 %{
4110 constraint(ALLOC_IN_RC(stack_slots));
4111 // No match rule because this operand is only generated in matching
4112
4113 format %{ "[$reg]" %}
4114 interface(MEMORY_INTER) %{
4115 base(0x4); // RSP
4116 index(0x4); // No Index
4117 scale(0x0); // No Scale
4118 disp($reg); // Stack Offset
4119 %}
4120 %}
4121 operand stackSlotL(sRegL reg)
4122 %{
4123 constraint(ALLOC_IN_RC(stack_slots));
4124 // No match rule because this operand is only generated in matching
4125
4126 format %{ "[$reg]" %}
4127 interface(MEMORY_INTER) %{
4128 base(0x4); // RSP
4129 index(0x4); // No Index
4130 scale(0x0); // No Scale
4131 disp($reg); // Stack Offset
4132 %}
4133 %}
4134
4135 //----------Conditional Branch Operands----------------------------------------
4136 // Comparison Op - This is the operation of the comparison, and is limited to
4137 // the following set of codes:
4138 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4139 //
4140 // Other attributes of the comparison, such as unsignedness, are specified
4141 // by the comparison instruction that sets a condition code flags register.
4142 // That result is represented by a flags operand whose subtype is appropriate
4143 // to the unsignedness (etc.) of the comparison.
4144 //
4145 // Later, the instruction which matches both the Comparison Op (a Bool) and
4146 // the flags (produced by the Cmp) specifies the coding of the comparison op
4147 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4148
4149 // Comparision Code
4150 operand cmpOp()
4151 %{
4152 match(Bool);
4153
4154 format %{ "" %}
4155 interface(COND_INTER) %{
4156 equal(0x4, "e");
4157 not_equal(0x5, "ne");
4158 less(0xC, "l");
4159 greater_equal(0xD, "ge");
4160 less_equal(0xE, "le");
4161 greater(0xF, "g");
4162 overflow(0x0, "o");
4163 no_overflow(0x1, "no");
4164 %}
4165 %}
4166
4167 // Comparison Code, unsigned compare. Used by FP also, with
4168 // C2 (unordered) turned into GT or LT already. The other bits
4169 // C0 and C3 are turned into Carry & Zero flags.
4170 operand cmpOpU()
4171 %{
4172 match(Bool);
4173
4174 format %{ "" %}
4175 interface(COND_INTER) %{
4176 equal(0x4, "e");
4177 not_equal(0x5, "ne");
4178 less(0x2, "b");
4179 greater_equal(0x3, "nb");
4180 less_equal(0x6, "be");
4181 greater(0x7, "nbe");
4182 overflow(0x0, "o");
4183 no_overflow(0x1, "no");
4184 %}
4185 %}
4186
4187
4188 // Floating comparisons that don't require any fixup for the unordered case
4189 operand cmpOpUCF() %{
4190 match(Bool);
4191 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4192 n->as_Bool()->_test._test == BoolTest::ge ||
4193 n->as_Bool()->_test._test == BoolTest::le ||
4194 n->as_Bool()->_test._test == BoolTest::gt);
4195 format %{ "" %}
4196 interface(COND_INTER) %{
4197 equal(0x4, "e");
4198 not_equal(0x5, "ne");
4199 less(0x2, "b");
4200 greater_equal(0x3, "nb");
4201 less_equal(0x6, "be");
4202 greater(0x7, "nbe");
4203 overflow(0x0, "o");
4204 no_overflow(0x1, "no");
4205 %}
4206 %}
4207
4208
4209 // Floating comparisons that can be fixed up with extra conditional jumps
4210 operand cmpOpUCF2() %{
4211 match(Bool);
4212 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4213 n->as_Bool()->_test._test == BoolTest::eq);
4214 format %{ "" %}
4215 interface(COND_INTER) %{
4216 equal(0x4, "e");
4217 not_equal(0x5, "ne");
4218 less(0x2, "b");
4219 greater_equal(0x3, "nb");
4220 less_equal(0x6, "be");
4221 greater(0x7, "nbe");
4222 overflow(0x0, "o");
4223 no_overflow(0x1, "no");
4224 %}
4225 %}
4226
4227 //----------OPERAND CLASSES----------------------------------------------------
4228 // Operand Classes are groups of operands that are used as to simplify
4229 // instruction definitions by not requiring the AD writer to specify separate
4230 // instructions for every form of operand when the instruction accepts
4231 // multiple operand types with the same basic encoding and format. The classic
4232 // case of this is memory operands.
4233
4234 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4235 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4236 indCompressedOopOffset,
4237 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4238 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4239 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4240
4241 //----------PIPELINE-----------------------------------------------------------
4242 // Rules which define the behavior of the target architectures pipeline.
4243 pipeline %{
4244
4245 //----------ATTRIBUTES---------------------------------------------------------
4246 attributes %{
4247 variable_size_instructions; // Fixed size instructions
4248 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4249 instruction_unit_size = 1; // An instruction is 1 bytes long
4250 instruction_fetch_unit_size = 16; // The processor fetches one line
4251 instruction_fetch_units = 1; // of 16 bytes
4252
4253 // List of nop instructions
4254 nops( MachNop );
4255 %}
4256
4257 //----------RESOURCES----------------------------------------------------------
4258 // Resources are the functional units available to the machine
4259
4260 // Generic P2/P3 pipeline
4261 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4262 // 3 instructions decoded per cycle.
4263 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4264 // 3 ALU op, only ALU0 handles mul instructions.
4265 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4266 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4267 BR, FPU,
4268 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4269
4270 //----------PIPELINE DESCRIPTION-----------------------------------------------
4271 // Pipeline Description specifies the stages in the machine's pipeline
4272
4273 // Generic P2/P3 pipeline
4274 pipe_desc(S0, S1, S2, S3, S4, S5);
4275
4276 //----------PIPELINE CLASSES---------------------------------------------------
4277 // Pipeline Classes describe the stages in which input and output are
4278 // referenced by the hardware pipeline.
4279
4280 // Naming convention: ialu or fpu
4281 // Then: _reg
4282 // Then: _reg if there is a 2nd register
4283 // Then: _long if it's a pair of instructions implementing a long
4284 // Then: _fat if it requires the big decoder
4285 // Or: _mem if it requires the big decoder and a memory unit.
4286
4287 // Integer ALU reg operation
4288 pipe_class ialu_reg(rRegI dst)
4289 %{
4290 single_instruction;
4291 dst : S4(write);
4292 dst : S3(read);
4293 DECODE : S0; // any decoder
4294 ALU : S3; // any alu
4295 %}
4296
4297 // Long ALU reg operation
4298 pipe_class ialu_reg_long(rRegL dst)
4299 %{
4300 instruction_count(2);
4301 dst : S4(write);
4302 dst : S3(read);
4303 DECODE : S0(2); // any 2 decoders
4304 ALU : S3(2); // both alus
4305 %}
4306
4307 // Integer ALU reg operation using big decoder
4308 pipe_class ialu_reg_fat(rRegI dst)
4309 %{
4310 single_instruction;
4311 dst : S4(write);
4312 dst : S3(read);
4313 D0 : S0; // big decoder only
4314 ALU : S3; // any alu
4315 %}
4316
4317 // Long ALU reg operation using big decoder
4318 pipe_class ialu_reg_long_fat(rRegL dst)
4319 %{
4320 instruction_count(2);
4321 dst : S4(write);
4322 dst : S3(read);
4323 D0 : S0(2); // big decoder only; twice
4324 ALU : S3(2); // any 2 alus
4325 %}
4326
4327 // Integer ALU reg-reg operation
4328 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4329 %{
4330 single_instruction;
4331 dst : S4(write);
4332 src : S3(read);
4333 DECODE : S0; // any decoder
4334 ALU : S3; // any alu
4335 %}
4336
4337 // Long ALU reg-reg operation
4338 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4339 %{
4340 instruction_count(2);
4341 dst : S4(write);
4342 src : S3(read);
4343 DECODE : S0(2); // any 2 decoders
4344 ALU : S3(2); // both alus
4345 %}
4346
4347 // Integer ALU reg-reg operation
4348 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4349 %{
4350 single_instruction;
4351 dst : S4(write);
4352 src : S3(read);
4353 D0 : S0; // big decoder only
4354 ALU : S3; // any alu
4355 %}
4356
4357 // Long ALU reg-reg operation
4358 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4359 %{
4360 instruction_count(2);
4361 dst : S4(write);
4362 src : S3(read);
4363 D0 : S0(2); // big decoder only; twice
4364 ALU : S3(2); // both alus
4365 %}
4366
4367 // Integer ALU reg-mem operation
4368 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4369 %{
4370 single_instruction;
4371 dst : S5(write);
4372 mem : S3(read);
4373 D0 : S0; // big decoder only
4374 ALU : S4; // any alu
4375 MEM : S3; // any mem
4376 %}
4377
4378 // Integer mem operation (prefetch)
4379 pipe_class ialu_mem(memory mem)
4380 %{
4381 single_instruction;
4382 mem : S3(read);
4383 D0 : S0; // big decoder only
4384 MEM : S3; // any mem
4385 %}
4386
4387 // Integer Store to Memory
4388 pipe_class ialu_mem_reg(memory mem, rRegI src)
4389 %{
4390 single_instruction;
4391 mem : S3(read);
4392 src : S5(read);
4393 D0 : S0; // big decoder only
4394 ALU : S4; // any alu
4395 MEM : S3;
4396 %}
4397
4398 // // Long Store to Memory
4399 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4400 // %{
4401 // instruction_count(2);
4402 // mem : S3(read);
4403 // src : S5(read);
4404 // D0 : S0(2); // big decoder only; twice
4405 // ALU : S4(2); // any 2 alus
4406 // MEM : S3(2); // Both mems
4407 // %}
4408
4409 // Integer Store to Memory
4410 pipe_class ialu_mem_imm(memory mem)
4411 %{
4412 single_instruction;
4413 mem : S3(read);
4414 D0 : S0; // big decoder only
4415 ALU : S4; // any alu
4416 MEM : S3;
4417 %}
4418
4419 // Integer ALU0 reg-reg operation
4420 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4421 %{
4422 single_instruction;
4423 dst : S4(write);
4424 src : S3(read);
4425 D0 : S0; // Big decoder only
4426 ALU0 : S3; // only alu0
4427 %}
4428
4429 // Integer ALU0 reg-mem operation
4430 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4431 %{
4432 single_instruction;
4433 dst : S5(write);
4434 mem : S3(read);
4435 D0 : S0; // big decoder only
4436 ALU0 : S4; // ALU0 only
4437 MEM : S3; // any mem
4438 %}
4439
4440 // Integer ALU reg-reg operation
4441 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4442 %{
4443 single_instruction;
4444 cr : S4(write);
4445 src1 : S3(read);
4446 src2 : S3(read);
4447 DECODE : S0; // any decoder
4448 ALU : S3; // any alu
4449 %}
4450
4451 // Integer ALU reg-imm operation
4452 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4453 %{
4454 single_instruction;
4455 cr : S4(write);
4456 src1 : S3(read);
4457 DECODE : S0; // any decoder
4458 ALU : S3; // any alu
4459 %}
4460
4461 // Integer ALU reg-mem operation
4462 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4463 %{
4464 single_instruction;
4465 cr : S4(write);
4466 src1 : S3(read);
4467 src2 : S3(read);
4468 D0 : S0; // big decoder only
4469 ALU : S4; // any alu
4470 MEM : S3;
4471 %}
4472
4473 // Conditional move reg-reg
4474 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4475 %{
4476 instruction_count(4);
4477 y : S4(read);
4478 q : S3(read);
4479 p : S3(read);
4480 DECODE : S0(4); // any decoder
4481 %}
4482
4483 // Conditional move reg-reg
4484 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4485 %{
4486 single_instruction;
4487 dst : S4(write);
4488 src : S3(read);
4489 cr : S3(read);
4490 DECODE : S0; // any decoder
4491 %}
4492
4493 // Conditional move reg-mem
4494 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4495 %{
4496 single_instruction;
4497 dst : S4(write);
4498 src : S3(read);
4499 cr : S3(read);
4500 DECODE : S0; // any decoder
4501 MEM : S3;
4502 %}
4503
4504 // Conditional move reg-reg long
4505 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4506 %{
4507 single_instruction;
4508 dst : S4(write);
4509 src : S3(read);
4510 cr : S3(read);
4511 DECODE : S0(2); // any 2 decoders
4512 %}
4513
4514 // XXX
4515 // // Conditional move double reg-reg
4516 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4517 // %{
4518 // single_instruction;
4519 // dst : S4(write);
4520 // src : S3(read);
4521 // cr : S3(read);
4522 // DECODE : S0; // any decoder
4523 // %}
4524
4525 // Float reg-reg operation
4526 pipe_class fpu_reg(regD dst)
4527 %{
4528 instruction_count(2);
4529 dst : S3(read);
4530 DECODE : S0(2); // any 2 decoders
4531 FPU : S3;
4532 %}
4533
4534 // Float reg-reg operation
4535 pipe_class fpu_reg_reg(regD dst, regD src)
4536 %{
4537 instruction_count(2);
4538 dst : S4(write);
4539 src : S3(read);
4540 DECODE : S0(2); // any 2 decoders
4541 FPU : S3;
4542 %}
4543
4544 // Float reg-reg operation
4545 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4546 %{
4547 instruction_count(3);
4548 dst : S4(write);
4549 src1 : S3(read);
4550 src2 : S3(read);
4551 DECODE : S0(3); // any 3 decoders
4552 FPU : S3(2);
4553 %}
4554
4555 // Float reg-reg operation
4556 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4557 %{
4558 instruction_count(4);
4559 dst : S4(write);
4560 src1 : S3(read);
4561 src2 : S3(read);
4562 src3 : S3(read);
4563 DECODE : S0(4); // any 3 decoders
4564 FPU : S3(2);
4565 %}
4566
4567 // Float reg-reg operation
4568 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4569 %{
4570 instruction_count(4);
4571 dst : S4(write);
4572 src1 : S3(read);
4573 src2 : S3(read);
4574 src3 : S3(read);
4575 DECODE : S1(3); // any 3 decoders
4576 D0 : S0; // Big decoder only
4577 FPU : S3(2);
4578 MEM : S3;
4579 %}
4580
4581 // Float reg-mem operation
4582 pipe_class fpu_reg_mem(regD dst, memory mem)
4583 %{
4584 instruction_count(2);
4585 dst : S5(write);
4586 mem : S3(read);
4587 D0 : S0; // big decoder only
4588 DECODE : S1; // any decoder for FPU POP
4589 FPU : S4;
4590 MEM : S3; // any mem
4591 %}
4592
4593 // Float reg-mem operation
4594 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4595 %{
4596 instruction_count(3);
4597 dst : S5(write);
4598 src1 : S3(read);
4599 mem : S3(read);
4600 D0 : S0; // big decoder only
4601 DECODE : S1(2); // any decoder for FPU POP
4602 FPU : S4;
4603 MEM : S3; // any mem
4604 %}
4605
4606 // Float mem-reg operation
4607 pipe_class fpu_mem_reg(memory mem, regD src)
4608 %{
4609 instruction_count(2);
4610 src : S5(read);
4611 mem : S3(read);
4612 DECODE : S0; // any decoder for FPU PUSH
4613 D0 : S1; // big decoder only
4614 FPU : S4;
4615 MEM : S3; // any mem
4616 %}
4617
4618 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4619 %{
4620 instruction_count(3);
4621 src1 : S3(read);
4622 src2 : S3(read);
4623 mem : S3(read);
4624 DECODE : S0(2); // any decoder for FPU PUSH
4625 D0 : S1; // big decoder only
4626 FPU : S4;
4627 MEM : S3; // any mem
4628 %}
4629
4630 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4631 %{
4632 instruction_count(3);
4633 src1 : S3(read);
4634 src2 : S3(read);
4635 mem : S4(read);
4636 DECODE : S0; // any decoder for FPU PUSH
4637 D0 : S0(2); // big decoder only
4638 FPU : S4;
4639 MEM : S3(2); // any mem
4640 %}
4641
4642 pipe_class fpu_mem_mem(memory dst, memory src1)
4643 %{
4644 instruction_count(2);
4645 src1 : S3(read);
4646 dst : S4(read);
4647 D0 : S0(2); // big decoder only
4648 MEM : S3(2); // any mem
4649 %}
4650
4651 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4652 %{
4653 instruction_count(3);
4654 src1 : S3(read);
4655 src2 : S3(read);
4656 dst : S4(read);
4657 D0 : S0(3); // big decoder only
4658 FPU : S4;
4659 MEM : S3(3); // any mem
4660 %}
4661
4662 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4663 %{
4664 instruction_count(3);
4665 src1 : S4(read);
4666 mem : S4(read);
4667 DECODE : S0; // any decoder for FPU PUSH
4668 D0 : S0(2); // big decoder only
4669 FPU : S4;
4670 MEM : S3(2); // any mem
4671 %}
4672
4673 // Float load constant
4674 pipe_class fpu_reg_con(regD dst)
4675 %{
4676 instruction_count(2);
4677 dst : S5(write);
4678 D0 : S0; // big decoder only for the load
4679 DECODE : S1; // any decoder for FPU POP
4680 FPU : S4;
4681 MEM : S3; // any mem
4682 %}
4683
4684 // Float load constant
4685 pipe_class fpu_reg_reg_con(regD dst, regD src)
4686 %{
4687 instruction_count(3);
4688 dst : S5(write);
4689 src : S3(read);
4690 D0 : S0; // big decoder only for the load
4691 DECODE : S1(2); // any decoder for FPU POP
4692 FPU : S4;
4693 MEM : S3; // any mem
4694 %}
4695
4696 // UnConditional branch
4697 pipe_class pipe_jmp(label labl)
4698 %{
4699 single_instruction;
4700 BR : S3;
4701 %}
4702
4703 // Conditional branch
4704 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4705 %{
4706 single_instruction;
4707 cr : S1(read);
4708 BR : S3;
4709 %}
4710
4711 // Allocation idiom
4712 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4713 %{
4714 instruction_count(1); force_serialization;
4715 fixed_latency(6);
4716 heap_ptr : S3(read);
4717 DECODE : S0(3);
4718 D0 : S2;
4719 MEM : S3;
4720 ALU : S3(2);
4721 dst : S5(write);
4722 BR : S5;
4723 %}
4724
4725 // Generic big/slow expanded idiom
4726 pipe_class pipe_slow()
4727 %{
4728 instruction_count(10); multiple_bundles; force_serialization;
4729 fixed_latency(100);
4730 D0 : S0(2);
4731 MEM : S3(2);
4732 %}
4733
4734 // The real do-nothing guy
4735 pipe_class empty()
4736 %{
4737 instruction_count(0);
4738 %}
4739
4740 // Define the class for the Nop node
4741 define
4742 %{
4743 MachNop = empty;
4744 %}
4745
4746 %}
4747
4748 //----------INSTRUCTIONS-------------------------------------------------------
4749 //
4750 // match -- States which machine-independent subtree may be replaced
4751 // by this instruction.
4752 // ins_cost -- The estimated cost of this instruction is used by instruction
4753 // selection to identify a minimum cost tree of machine
4754 // instructions that matches a tree of machine-independent
4755 // instructions.
4756 // format -- A string providing the disassembly for this instruction.
4757 // The value of an instruction's operand may be inserted
4758 // by referring to it with a '$' prefix.
4759 // opcode -- Three instruction opcodes may be provided. These are referred
4760 // to within an encode class as $primary, $secondary, and $tertiary
4761 // rrspectively. The primary opcode is commonly used to
4762 // indicate the type of machine instruction, while secondary
4763 // and tertiary are often used for prefix options or addressing
4764 // modes.
4765 // ins_encode -- A list of encode classes with parameters. The encode class
4766 // name must have been defined in an 'enc_class' specification
4767 // in the encode section of the architecture description.
4768
4769
4770 //----------Load/Store/Move Instructions---------------------------------------
4771 //----------Load Instructions--------------------------------------------------
4772
4773 // Load Byte (8 bit signed)
4774 instruct loadB(rRegI dst, memory mem)
4775 %{
4776 match(Set dst (LoadB mem));
4777
4778 ins_cost(125);
4779 format %{ "movsbl $dst, $mem\t# byte" %}
4780
4781 ins_encode %{
4782 __ movsbl($dst$$Register, $mem$$Address);
4783 %}
4784
4785 ins_pipe(ialu_reg_mem);
4786 %}
4787
4788 // Load Byte (8 bit signed) into Long Register
4789 instruct loadB2L(rRegL dst, memory mem)
4790 %{
4791 match(Set dst (ConvI2L (LoadB mem)));
4792
4793 ins_cost(125);
4794 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4795
4796 ins_encode %{
4797 __ movsbq($dst$$Register, $mem$$Address);
4798 %}
4799
4800 ins_pipe(ialu_reg_mem);
4801 %}
4802
4803 // Load Unsigned Byte (8 bit UNsigned)
4804 instruct loadUB(rRegI dst, memory mem)
4805 %{
4806 match(Set dst (LoadUB mem));
4807
4808 ins_cost(125);
4809 format %{ "movzbl $dst, $mem\t# ubyte" %}
4810
4811 ins_encode %{
4812 __ movzbl($dst$$Register, $mem$$Address);
4813 %}
4814
4815 ins_pipe(ialu_reg_mem);
4816 %}
4817
4818 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4819 instruct loadUB2L(rRegL dst, memory mem)
4820 %{
4821 match(Set dst (ConvI2L (LoadUB mem)));
4822
4823 ins_cost(125);
4824 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4825
4826 ins_encode %{
4827 __ movzbq($dst$$Register, $mem$$Address);
4828 %}
4829
4830 ins_pipe(ialu_reg_mem);
4831 %}
4832
4833 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4834 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4835 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4836 effect(KILL cr);
4837
4838 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4839 "andl $dst, right_n_bits($mask, 8)" %}
4840 ins_encode %{
4841 Register Rdst = $dst$$Register;
4842 __ movzbq(Rdst, $mem$$Address);
4843 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4844 %}
4845 ins_pipe(ialu_reg_mem);
4846 %}
4847
4848 // Load Short (16 bit signed)
4849 instruct loadS(rRegI dst, memory mem)
4850 %{
4851 match(Set dst (LoadS mem));
4852
4853 ins_cost(125);
4854 format %{ "movswl $dst, $mem\t# short" %}
4855
4856 ins_encode %{
4857 __ movswl($dst$$Register, $mem$$Address);
4858 %}
4859
4860 ins_pipe(ialu_reg_mem);
4861 %}
4862
4863 // Load Short (16 bit signed) to Byte (8 bit signed)
4864 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4865 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4866
4867 ins_cost(125);
4868 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4869 ins_encode %{
4870 __ movsbl($dst$$Register, $mem$$Address);
4871 %}
4872 ins_pipe(ialu_reg_mem);
4873 %}
4874
4875 // Load Short (16 bit signed) into Long Register
4876 instruct loadS2L(rRegL dst, memory mem)
4877 %{
4878 match(Set dst (ConvI2L (LoadS mem)));
4879
4880 ins_cost(125);
4881 format %{ "movswq $dst, $mem\t# short -> long" %}
4882
4883 ins_encode %{
4884 __ movswq($dst$$Register, $mem$$Address);
4885 %}
4886
4887 ins_pipe(ialu_reg_mem);
4888 %}
4889
4890 // Load Unsigned Short/Char (16 bit UNsigned)
4891 instruct loadUS(rRegI dst, memory mem)
4892 %{
4893 match(Set dst (LoadUS mem));
4894
4895 ins_cost(125);
4896 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4897
4898 ins_encode %{
4899 __ movzwl($dst$$Register, $mem$$Address);
4900 %}
4901
4902 ins_pipe(ialu_reg_mem);
4903 %}
4904
4905 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4906 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4907 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4908
4909 ins_cost(125);
4910 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4911 ins_encode %{
4912 __ movsbl($dst$$Register, $mem$$Address);
4913 %}
4914 ins_pipe(ialu_reg_mem);
4915 %}
4916
4917 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4918 instruct loadUS2L(rRegL dst, memory mem)
4919 %{
4920 match(Set dst (ConvI2L (LoadUS mem)));
4921
4922 ins_cost(125);
4923 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4924
4925 ins_encode %{
4926 __ movzwq($dst$$Register, $mem$$Address);
4927 %}
4928
4929 ins_pipe(ialu_reg_mem);
4930 %}
4931
4932 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4933 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4934 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4935
4936 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4937 ins_encode %{
4938 __ movzbq($dst$$Register, $mem$$Address);
4939 %}
4940 ins_pipe(ialu_reg_mem);
4941 %}
4942
4943 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4944 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4945 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4946 effect(KILL cr);
4947
4948 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4949 "andl $dst, right_n_bits($mask, 16)" %}
4950 ins_encode %{
4951 Register Rdst = $dst$$Register;
4952 __ movzwq(Rdst, $mem$$Address);
4953 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4954 %}
4955 ins_pipe(ialu_reg_mem);
4956 %}
4957
4958 // Load Integer
4959 instruct loadI(rRegI dst, memory mem)
4960 %{
4961 match(Set dst (LoadI mem));
4962
4963 ins_cost(125);
4964 format %{ "movl $dst, $mem\t# int" %}
4965
4966 ins_encode %{
4967 __ movl($dst$$Register, $mem$$Address);
4968 %}
4969
4970 ins_pipe(ialu_reg_mem);
4971 %}
4972
4973 // Load Integer (32 bit signed) to Byte (8 bit signed)
4974 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4975 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4976
4977 ins_cost(125);
4978 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4979 ins_encode %{
4980 __ movsbl($dst$$Register, $mem$$Address);
4981 %}
4982 ins_pipe(ialu_reg_mem);
4983 %}
4984
4985 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4986 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4987 match(Set dst (AndI (LoadI mem) mask));
4988
4989 ins_cost(125);
4990 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4991 ins_encode %{
4992 __ movzbl($dst$$Register, $mem$$Address);
4993 %}
4994 ins_pipe(ialu_reg_mem);
4995 %}
4996
4997 // Load Integer (32 bit signed) to Short (16 bit signed)
4998 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4999 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5000
5001 ins_cost(125);
5002 format %{ "movswl $dst, $mem\t# int -> short" %}
5003 ins_encode %{
5004 __ movswl($dst$$Register, $mem$$Address);
5005 %}
5006 ins_pipe(ialu_reg_mem);
5007 %}
5008
5009 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5010 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5011 match(Set dst (AndI (LoadI mem) mask));
5012
5013 ins_cost(125);
5014 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5015 ins_encode %{
5016 __ movzwl($dst$$Register, $mem$$Address);
5017 %}
5018 ins_pipe(ialu_reg_mem);
5019 %}
5020
5021 // Load Integer into Long Register
5022 instruct loadI2L(rRegL dst, memory mem)
5023 %{
5024 match(Set dst (ConvI2L (LoadI mem)));
5025
5026 ins_cost(125);
5027 format %{ "movslq $dst, $mem\t# int -> long" %}
5028
5029 ins_encode %{
5030 __ movslq($dst$$Register, $mem$$Address);
5031 %}
5032
5033 ins_pipe(ialu_reg_mem);
5034 %}
5035
5036 // Load Integer with mask 0xFF into Long Register
5037 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5038 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5039
5040 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5041 ins_encode %{
5042 __ movzbq($dst$$Register, $mem$$Address);
5043 %}
5044 ins_pipe(ialu_reg_mem);
5045 %}
5046
5047 // Load Integer with mask 0xFFFF into Long Register
5048 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5049 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5050
5051 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5052 ins_encode %{
5053 __ movzwq($dst$$Register, $mem$$Address);
5054 %}
5055 ins_pipe(ialu_reg_mem);
5056 %}
5057
5058 // Load Integer with a 31-bit mask into Long Register
5059 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5060 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5061 effect(KILL cr);
5062
5063 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5064 "andl $dst, $mask" %}
5065 ins_encode %{
5066 Register Rdst = $dst$$Register;
5067 __ movl(Rdst, $mem$$Address);
5068 __ andl(Rdst, $mask$$constant);
5069 %}
5070 ins_pipe(ialu_reg_mem);
5071 %}
5072
5073 // Load Unsigned Integer into Long Register
5074 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5075 %{
5076 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5077
5078 ins_cost(125);
5079 format %{ "movl $dst, $mem\t# uint -> long" %}
5080
5081 ins_encode %{
5082 __ movl($dst$$Register, $mem$$Address);
5083 %}
5084
5085 ins_pipe(ialu_reg_mem);
5086 %}
5087
5088 // Load Long
5089 instruct loadL(rRegL dst, memory mem)
5090 %{
5091 match(Set dst (LoadL mem));
5092
5093 ins_cost(125);
5094 format %{ "movq $dst, $mem\t# long" %}
5095
5096 ins_encode %{
5097 __ movq($dst$$Register, $mem$$Address);
5098 %}
5099
5100 ins_pipe(ialu_reg_mem); // XXX
5101 %}
5102
5103 // Load Range
5104 instruct loadRange(rRegI dst, memory mem)
5105 %{
5106 match(Set dst (LoadRange mem));
5107
5108 ins_cost(125); // XXX
5109 format %{ "movl $dst, $mem\t# range" %}
5110 opcode(0x8B);
5111 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5112 ins_pipe(ialu_reg_mem);
5113 %}
5114
5115 // Load Pointer
5116 instruct loadP(rRegP dst, memory mem)
5117 %{
5118 match(Set dst (LoadP mem));
5119 predicate(n->as_Load()->barrier_data() == 0);
5120
5121 ins_cost(125); // XXX
5122 format %{ "movq $dst, $mem\t# ptr" %}
5123 opcode(0x8B);
5124 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5125 ins_pipe(ialu_reg_mem); // XXX
5126 %}
5127
5128 // Load Compressed Pointer
5129 instruct loadN(rRegN dst, memory mem)
5130 %{
5131 match(Set dst (LoadN mem));
5132
5133 ins_cost(125); // XXX
5134 format %{ "movl $dst, $mem\t# compressed ptr" %}
5135 ins_encode %{
5136 __ movl($dst$$Register, $mem$$Address);
5137 %}
5138 ins_pipe(ialu_reg_mem); // XXX
5139 %}
5140
5141
5142 // Load Klass Pointer
5143 instruct loadKlass(rRegP dst, memory mem)
5144 %{
5145 match(Set dst (LoadKlass mem));
5146
5147 ins_cost(125); // XXX
5148 format %{ "movq $dst, $mem\t# class" %}
5149 opcode(0x8B);
5150 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5151 ins_pipe(ialu_reg_mem); // XXX
5152 %}
5153
5154 // Load narrow Klass Pointer
5155 instruct loadNKlass(rRegN dst, memory mem)
5156 %{
5157 match(Set dst (LoadNKlass mem));
5158
5159 ins_cost(125); // XXX
5160 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5161 ins_encode %{
5162 __ movl($dst$$Register, $mem$$Address);
5163 %}
5164 ins_pipe(ialu_reg_mem); // XXX
5165 %}
5166
5167 // Load Float
5168 instruct loadF(regF dst, memory mem)
5169 %{
5170 match(Set dst (LoadF mem));
5171
5172 ins_cost(145); // XXX
5173 format %{ "movss $dst, $mem\t# float" %}
5174 ins_encode %{
5175 __ movflt($dst$$XMMRegister, $mem$$Address);
5176 %}
5177 ins_pipe(pipe_slow); // XXX
5178 %}
5179
5180 // Load Float
5181 instruct MoveF2VL(vlRegF dst, regF src) %{
5182 match(Set dst src);
5183 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5184 ins_encode %{
5185 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5186 %}
5187 ins_pipe( fpu_reg_reg );
5188 %}
5189
5190 // Load Float
5191 instruct MoveF2LEG(legRegF dst, regF src) %{
5192 match(Set dst src);
5193 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5194 ins_encode %{
5195 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5196 %}
5197 ins_pipe( fpu_reg_reg );
5198 %}
5199
5200 // Load Float
5201 instruct MoveVL2F(regF dst, vlRegF src) %{
5202 match(Set dst src);
5203 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5204 ins_encode %{
5205 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5206 %}
5207 ins_pipe( fpu_reg_reg );
5208 %}
5209
5210 // Load Float
5211 instruct MoveLEG2F(regF dst, legRegF src) %{
5212 match(Set dst src);
5213 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5214 ins_encode %{
5215 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5216 %}
5217 ins_pipe( fpu_reg_reg );
5218 %}
5219
5220 // Load Double
5221 instruct loadD_partial(regD dst, memory mem)
5222 %{
5223 predicate(!UseXmmLoadAndClearUpper);
5224 match(Set dst (LoadD mem));
5225
5226 ins_cost(145); // XXX
5227 format %{ "movlpd $dst, $mem\t# double" %}
5228 ins_encode %{
5229 __ movdbl($dst$$XMMRegister, $mem$$Address);
5230 %}
5231 ins_pipe(pipe_slow); // XXX
5232 %}
5233
5234 instruct loadD(regD dst, memory mem)
5235 %{
5236 predicate(UseXmmLoadAndClearUpper);
5237 match(Set dst (LoadD mem));
5238
5239 ins_cost(145); // XXX
5240 format %{ "movsd $dst, $mem\t# double" %}
5241 ins_encode %{
5242 __ movdbl($dst$$XMMRegister, $mem$$Address);
5243 %}
5244 ins_pipe(pipe_slow); // XXX
5245 %}
5246
5247 // Load Double
5248 instruct MoveD2VL(vlRegD dst, regD src) %{
5249 match(Set dst src);
5250 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5251 ins_encode %{
5252 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5253 %}
5254 ins_pipe( fpu_reg_reg );
5255 %}
5256
5257 // Load Double
5258 instruct MoveD2LEG(legRegD dst, regD src) %{
5259 match(Set dst src);
5260 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5261 ins_encode %{
5262 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5263 %}
5264 ins_pipe( fpu_reg_reg );
5265 %}
5266
5267 // Load Double
5268 instruct MoveVL2D(regD dst, vlRegD src) %{
5269 match(Set dst src);
5270 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5271 ins_encode %{
5272 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5273 %}
5274 ins_pipe( fpu_reg_reg );
5275 %}
5276
5277 // Load Double
5278 instruct MoveLEG2D(regD dst, legRegD src) %{
5279 match(Set dst src);
5280 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5281 ins_encode %{
5282 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5283 %}
5284 ins_pipe( fpu_reg_reg );
5285 %}
5286
5287 // Following pseudo code describes the algorithm for max[FD]:
5288 // Min algorithm is on similar lines
5289 // btmp = (b < +0.0) ? a : b
5290 // atmp = (b < +0.0) ? b : a
5291 // Tmp = Max_Float(atmp , btmp)
5292 // Res = (atmp == NaN) ? atmp : Tmp
5293
5294 // max = java.lang.Math.max(float a, float b)
5295 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5296 predicate(UseAVX > 0 && !n->is_reduction());
5297 match(Set dst (MaxF a b));
5298 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5299 format %{
5300 "vblendvps $btmp,$b,$a,$b \n\t"
5301 "vblendvps $atmp,$a,$b,$b \n\t"
5302 "vmaxss $tmp,$atmp,$btmp \n\t"
5303 "vcmpps.unordered $btmp,$atmp,$atmp \n\t"
5304 "vblendvps $dst,$tmp,$atmp,$btmp \n\t"
5305 %}
5306 ins_encode %{
5307 int vector_len = Assembler::AVX_128bit;
5308 __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5309 __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5310 __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5311 __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5312 __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5313 %}
5314 ins_pipe( pipe_slow );
5315 %}
5316
5317 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
5318 predicate(UseAVX > 0 && n->is_reduction());
5319 match(Set dst (MaxF a b));
5320 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5321
5322 format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
5323 ins_encode %{
5324 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5325 false /*min*/, true /*single*/);
5326 %}
5327 ins_pipe( pipe_slow );
5328 %}
5329
5330 // max = java.lang.Math.max(double a, double b)
5331 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5332 predicate(UseAVX > 0 && !n->is_reduction());
5333 match(Set dst (MaxD a b));
5334 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
5335 format %{
5336 "vblendvpd $btmp,$b,$a,$b \n\t"
5337 "vblendvpd $atmp,$a,$b,$b \n\t"
5338 "vmaxsd $tmp,$atmp,$btmp \n\t"
5339 "vcmppd.unordered $btmp,$atmp,$atmp \n\t"
5340 "vblendvpd $dst,$tmp,$atmp,$btmp \n\t"
5341 %}
5342 ins_encode %{
5343 int vector_len = Assembler::AVX_128bit;
5344 __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5345 __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5346 __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5347 __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5348 __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5349 %}
5350 ins_pipe( pipe_slow );
5351 %}
5352
5353 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
5354 predicate(UseAVX > 0 && n->is_reduction());
5355 match(Set dst (MaxD a b));
5356 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5357
5358 format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
5359 ins_encode %{
5360 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5361 false /*min*/, false /*single*/);
5362 %}
5363 ins_pipe( pipe_slow );
5364 %}
5365
5366 // min = java.lang.Math.min(float a, float b)
5367 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5368 predicate(UseAVX > 0 && !n->is_reduction());
5369 match(Set dst (MinF a b));
5370 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5371 format %{
5372 "vblendvps $atmp,$a,$b,$a \n\t"
5373 "vblendvps $btmp,$b,$a,$a \n\t"
5374 "vminss $tmp,$atmp,$btmp \n\t"
5375 "vcmpps.unordered $btmp,$atmp,$atmp \n\t"
5376 "vblendvps $dst,$tmp,$atmp,$btmp \n\t"
5377 %}
5378 ins_encode %{
5379 int vector_len = Assembler::AVX_128bit;
5380 __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5381 __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5382 __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5383 __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5384 __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5385 %}
5386 ins_pipe( pipe_slow );
5387 %}
5388
5389 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
5390 predicate(UseAVX > 0 && n->is_reduction());
5391 match(Set dst (MinF a b));
5392 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5393
5394 format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
5395 ins_encode %{
5396 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5397 true /*min*/, true /*single*/);
5398 %}
5399 ins_pipe( pipe_slow );
5400 %}
5401
5402 // min = java.lang.Math.min(double a, double b)
5403 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5404 predicate(UseAVX > 0 && !n->is_reduction());
5405 match(Set dst (MinD a b));
5406 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5407 format %{
5408 "vblendvpd $atmp,$a,$b,$a \n\t"
5409 "vblendvpd $btmp,$b,$a,$a \n\t"
5410 "vminsd $tmp,$atmp,$btmp \n\t"
5411 "vcmppd.unordered $btmp,$atmp,$atmp \n\t"
5412 "vblendvpd $dst,$tmp,$atmp,$btmp \n\t"
5413 %}
5414 ins_encode %{
5415 int vector_len = Assembler::AVX_128bit;
5416 __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5417 __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5418 __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5419 __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5420 __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5421 %}
5422 ins_pipe( pipe_slow );
5423 %}
5424
5425 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
5426 predicate(UseAVX > 0 && n->is_reduction());
5427 match(Set dst (MinD a b));
5428 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5429
5430 format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
5431 ins_encode %{
5432 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5433 true /*min*/, false /*single*/);
5434 %}
5435 ins_pipe( pipe_slow );
5436 %}
5437
5438 // Load Effective Address
5439 instruct leaP8(rRegP dst, indOffset8 mem)
5440 %{
5441 match(Set dst mem);
5442
5443 ins_cost(110); // XXX
5444 format %{ "leaq $dst, $mem\t# ptr 8" %}
5445 opcode(0x8D);
5446 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5447 ins_pipe(ialu_reg_reg_fat);
5448 %}
5449
5450 instruct leaP32(rRegP dst, indOffset32 mem)
5451 %{
5452 match(Set dst mem);
5453
5454 ins_cost(110);
5455 format %{ "leaq $dst, $mem\t# ptr 32" %}
5456 opcode(0x8D);
5457 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5458 ins_pipe(ialu_reg_reg_fat);
5459 %}
5460
5461 // instruct leaPIdx(rRegP dst, indIndex mem)
5462 // %{
5463 // match(Set dst mem);
5464
5465 // ins_cost(110);
5466 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5467 // opcode(0x8D);
5468 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5469 // ins_pipe(ialu_reg_reg_fat);
5470 // %}
5471
5472 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5473 %{
5474 match(Set dst mem);
5475
5476 ins_cost(110);
5477 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5478 opcode(0x8D);
5479 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5480 ins_pipe(ialu_reg_reg_fat);
5481 %}
5482
5483 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5484 %{
5485 match(Set dst mem);
5486
5487 ins_cost(110);
5488 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5489 opcode(0x8D);
5490 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5491 ins_pipe(ialu_reg_reg_fat);
5492 %}
5493
5494 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5495 %{
5496 match(Set dst mem);
5497
5498 ins_cost(110);
5499 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5500 opcode(0x8D);
5501 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5502 ins_pipe(ialu_reg_reg_fat);
5503 %}
5504
5505 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5506 %{
5507 match(Set dst mem);
5508
5509 ins_cost(110);
5510 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5511 opcode(0x8D);
5512 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5513 ins_pipe(ialu_reg_reg_fat);
5514 %}
5515
5516 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5517 %{
5518 match(Set dst mem);
5519
5520 ins_cost(110);
5521 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5522 opcode(0x8D);
5523 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5524 ins_pipe(ialu_reg_reg_fat);
5525 %}
5526
5527 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5528 %{
5529 match(Set dst mem);
5530
5531 ins_cost(110);
5532 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5533 opcode(0x8D);
5534 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5535 ins_pipe(ialu_reg_reg_fat);
5536 %}
5537
5538 // Load Effective Address which uses Narrow (32-bits) oop
5539 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5540 %{
5541 predicate(UseCompressedOops && (CompressedOops::shift() != 0));
5542 match(Set dst mem);
5543
5544 ins_cost(110);
5545 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5546 opcode(0x8D);
5547 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5548 ins_pipe(ialu_reg_reg_fat);
5549 %}
5550
5551 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5552 %{
5553 predicate(CompressedOops::shift() == 0);
5554 match(Set dst mem);
5555
5556 ins_cost(110); // XXX
5557 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5558 opcode(0x8D);
5559 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5560 ins_pipe(ialu_reg_reg_fat);
5561 %}
5562
5563 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5564 %{
5565 predicate(CompressedOops::shift() == 0);
5566 match(Set dst mem);
5567
5568 ins_cost(110);
5569 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5570 opcode(0x8D);
5571 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5572 ins_pipe(ialu_reg_reg_fat);
5573 %}
5574
5575 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5576 %{
5577 predicate(CompressedOops::shift() == 0);
5578 match(Set dst mem);
5579
5580 ins_cost(110);
5581 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5582 opcode(0x8D);
5583 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5584 ins_pipe(ialu_reg_reg_fat);
5585 %}
5586
5587 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5588 %{
5589 predicate(CompressedOops::shift() == 0);
5590 match(Set dst mem);
5591
5592 ins_cost(110);
5593 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5594 opcode(0x8D);
5595 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5596 ins_pipe(ialu_reg_reg_fat);
5597 %}
5598
5599 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5600 %{
5601 predicate(CompressedOops::shift() == 0);
5602 match(Set dst mem);
5603
5604 ins_cost(110);
5605 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5606 opcode(0x8D);
5607 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5608 ins_pipe(ialu_reg_reg_fat);
5609 %}
5610
5611 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5612 %{
5613 predicate(CompressedOops::shift() == 0);
5614 match(Set dst mem);
5615
5616 ins_cost(110);
5617 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5618 opcode(0x8D);
5619 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5620 ins_pipe(ialu_reg_reg_fat);
5621 %}
5622
5623 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5624 %{
5625 predicate(CompressedOops::shift() == 0);
5626 match(Set dst mem);
5627
5628 ins_cost(110);
5629 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5630 opcode(0x8D);
5631 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5632 ins_pipe(ialu_reg_reg_fat);
5633 %}
5634
5635 instruct loadConI(rRegI dst, immI src)
5636 %{
5637 match(Set dst src);
5638
5639 format %{ "movl $dst, $src\t# int" %}
5640 ins_encode(load_immI(dst, src));
5641 ins_pipe(ialu_reg_fat); // XXX
5642 %}
5643
5644 instruct loadConI0(rRegI dst, immI_0 src, rFlagsReg cr)
5645 %{
5646 match(Set dst src);
5647 effect(KILL cr);
5648
5649 ins_cost(50);
5650 format %{ "xorl $dst, $dst\t# int" %}
5651 opcode(0x33); /* + rd */
5652 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5653 ins_pipe(ialu_reg);
5654 %}
5655
5656 instruct loadConL(rRegL dst, immL src)
5657 %{
5658 match(Set dst src);
5659
5660 ins_cost(150);
5661 format %{ "movq $dst, $src\t# long" %}
5662 ins_encode(load_immL(dst, src));
5663 ins_pipe(ialu_reg);
5664 %}
5665
5666 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5667 %{
5668 match(Set dst src);
5669 effect(KILL cr);
5670
5671 ins_cost(50);
5672 format %{ "xorl $dst, $dst\t# long" %}
5673 opcode(0x33); /* + rd */
5674 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5675 ins_pipe(ialu_reg); // XXX
5676 %}
5677
5678 instruct loadConUL32(rRegL dst, immUL32 src)
5679 %{
5680 match(Set dst src);
5681
5682 ins_cost(60);
5683 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5684 ins_encode(load_immUL32(dst, src));
5685 ins_pipe(ialu_reg);
5686 %}
5687
5688 instruct loadConL32(rRegL dst, immL32 src)
5689 %{
5690 match(Set dst src);
5691
5692 ins_cost(70);
5693 format %{ "movq $dst, $src\t# long (32-bit)" %}
5694 ins_encode(load_immL32(dst, src));
5695 ins_pipe(ialu_reg);
5696 %}
5697
5698 instruct loadConP(rRegP dst, immP con) %{
5699 match(Set dst con);
5700
5701 format %{ "movq $dst, $con\t# ptr" %}
5702 ins_encode(load_immP(dst, con));
5703 ins_pipe(ialu_reg_fat); // XXX
5704 %}
5705
5706 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5707 %{
5708 match(Set dst src);
5709 effect(KILL cr);
5710
5711 ins_cost(50);
5712 format %{ "xorl $dst, $dst\t# ptr" %}
5713 opcode(0x33); /* + rd */
5714 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5715 ins_pipe(ialu_reg);
5716 %}
5717
5718 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5719 %{
5720 match(Set dst src);
5721 effect(KILL cr);
5722
5723 ins_cost(60);
5724 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5725 ins_encode(load_immP31(dst, src));
5726 ins_pipe(ialu_reg);
5727 %}
5728
5729 instruct loadConF(regF dst, immF con) %{
5730 match(Set dst con);
5731 ins_cost(125);
5732 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5733 ins_encode %{
5734 __ movflt($dst$$XMMRegister, $constantaddress($con));
5735 %}
5736 ins_pipe(pipe_slow);
5737 %}
5738
5739 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5740 match(Set dst src);
5741 effect(KILL cr);
5742 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5743 ins_encode %{
5744 __ xorq($dst$$Register, $dst$$Register);
5745 %}
5746 ins_pipe(ialu_reg);
5747 %}
5748
5749 instruct loadConN(rRegN dst, immN src) %{
5750 match(Set dst src);
5751
5752 ins_cost(125);
5753 format %{ "movl $dst, $src\t# compressed ptr" %}
5754 ins_encode %{
5755 address con = (address)$src$$constant;
5756 if (con == NULL) {
5757 ShouldNotReachHere();
5758 } else {
5759 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5760 }
5761 %}
5762 ins_pipe(ialu_reg_fat); // XXX
5763 %}
5764
5765 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5766 match(Set dst src);
5767
5768 ins_cost(125);
5769 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5770 ins_encode %{
5771 address con = (address)$src$$constant;
5772 if (con == NULL) {
5773 ShouldNotReachHere();
5774 } else {
5775 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5776 }
5777 %}
5778 ins_pipe(ialu_reg_fat); // XXX
5779 %}
5780
5781 instruct loadConF0(regF dst, immF0 src)
5782 %{
5783 match(Set dst src);
5784 ins_cost(100);
5785
5786 format %{ "xorps $dst, $dst\t# float 0.0" %}
5787 ins_encode %{
5788 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5789 %}
5790 ins_pipe(pipe_slow);
5791 %}
5792
5793 // Use the same format since predicate() can not be used here.
5794 instruct loadConD(regD dst, immD con) %{
5795 match(Set dst con);
5796 ins_cost(125);
5797 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5798 ins_encode %{
5799 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5800 %}
5801 ins_pipe(pipe_slow);
5802 %}
5803
5804 instruct loadConD0(regD dst, immD0 src)
5805 %{
5806 match(Set dst src);
5807 ins_cost(100);
5808
5809 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5810 ins_encode %{
5811 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5812 %}
5813 ins_pipe(pipe_slow);
5814 %}
5815
5816 instruct loadSSI(rRegI dst, stackSlotI src)
5817 %{
5818 match(Set dst src);
5819
5820 ins_cost(125);
5821 format %{ "movl $dst, $src\t# int stk" %}
5822 opcode(0x8B);
5823 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5824 ins_pipe(ialu_reg_mem);
5825 %}
5826
5827 instruct loadSSL(rRegL dst, stackSlotL src)
5828 %{
5829 match(Set dst src);
5830
5831 ins_cost(125);
5832 format %{ "movq $dst, $src\t# long stk" %}
5833 opcode(0x8B);
5834 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5835 ins_pipe(ialu_reg_mem);
5836 %}
5837
5838 instruct loadSSP(rRegP dst, stackSlotP src)
5839 %{
5840 match(Set dst src);
5841
5842 ins_cost(125);
5843 format %{ "movq $dst, $src\t# ptr stk" %}
5844 opcode(0x8B);
5845 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5846 ins_pipe(ialu_reg_mem);
5847 %}
5848
5849 instruct loadSSF(regF dst, stackSlotF src)
5850 %{
5851 match(Set dst src);
5852
5853 ins_cost(125);
5854 format %{ "movss $dst, $src\t# float stk" %}
5855 ins_encode %{
5856 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5857 %}
5858 ins_pipe(pipe_slow); // XXX
5859 %}
5860
5861 // Use the same format since predicate() can not be used here.
5862 instruct loadSSD(regD dst, stackSlotD src)
5863 %{
5864 match(Set dst src);
5865
5866 ins_cost(125);
5867 format %{ "movsd $dst, $src\t# double stk" %}
5868 ins_encode %{
5869 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5870 %}
5871 ins_pipe(pipe_slow); // XXX
5872 %}
5873
5874 // Prefetch instructions for allocation.
5875 // Must be safe to execute with invalid address (cannot fault).
5876
5877 instruct prefetchAlloc( memory mem ) %{
5878 predicate(AllocatePrefetchInstr==3);
5879 match(PrefetchAllocation mem);
5880 ins_cost(125);
5881
5882 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5883 ins_encode %{
5884 __ prefetchw($mem$$Address);
5885 %}
5886 ins_pipe(ialu_mem);
5887 %}
5888
5889 instruct prefetchAllocNTA( memory mem ) %{
5890 predicate(AllocatePrefetchInstr==0);
5891 match(PrefetchAllocation mem);
5892 ins_cost(125);
5893
5894 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5895 ins_encode %{
5896 __ prefetchnta($mem$$Address);
5897 %}
5898 ins_pipe(ialu_mem);
5899 %}
5900
5901 instruct prefetchAllocT0( memory mem ) %{
5902 predicate(AllocatePrefetchInstr==1);
5903 match(PrefetchAllocation mem);
5904 ins_cost(125);
5905
5906 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5907 ins_encode %{
5908 __ prefetcht0($mem$$Address);
5909 %}
5910 ins_pipe(ialu_mem);
5911 %}
5912
5913 instruct prefetchAllocT2( memory mem ) %{
5914 predicate(AllocatePrefetchInstr==2);
5915 match(PrefetchAllocation mem);
5916 ins_cost(125);
5917
5918 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5919 ins_encode %{
5920 __ prefetcht2($mem$$Address);
5921 %}
5922 ins_pipe(ialu_mem);
5923 %}
5924
5925 //----------Store Instructions-------------------------------------------------
5926
5927 // Store Byte
5928 instruct storeB(memory mem, rRegI src)
5929 %{
5930 match(Set mem (StoreB mem src));
5931
5932 ins_cost(125); // XXX
5933 format %{ "movb $mem, $src\t# byte" %}
5934 opcode(0x88);
5935 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5936 ins_pipe(ialu_mem_reg);
5937 %}
5938
5939 // Store Char/Short
5940 instruct storeC(memory mem, rRegI src)
5941 %{
5942 match(Set mem (StoreC mem src));
5943
5944 ins_cost(125); // XXX
5945 format %{ "movw $mem, $src\t# char/short" %}
5946 opcode(0x89);
5947 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5948 ins_pipe(ialu_mem_reg);
5949 %}
5950
5951 // Store Integer
5952 instruct storeI(memory mem, rRegI src)
5953 %{
5954 match(Set mem (StoreI mem src));
5955
5956 ins_cost(125); // XXX
5957 format %{ "movl $mem, $src\t# int" %}
5958 opcode(0x89);
5959 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5960 ins_pipe(ialu_mem_reg);
5961 %}
5962
5963 // Store Long
5964 instruct storeL(memory mem, rRegL src)
5965 %{
5966 match(Set mem (StoreL mem src));
5967
5968 ins_cost(125); // XXX
5969 format %{ "movq $mem, $src\t# long" %}
5970 opcode(0x89);
5971 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5972 ins_pipe(ialu_mem_reg); // XXX
5973 %}
5974
5975 // Store Pointer
5976 instruct storeP(memory mem, any_RegP src)
5977 %{
5978 match(Set mem (StoreP mem src));
5979
5980 ins_cost(125); // XXX
5981 format %{ "movq $mem, $src\t# ptr" %}
5982 opcode(0x89);
5983 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5984 ins_pipe(ialu_mem_reg);
5985 %}
5986
5987 instruct storeImmP0(memory mem, immP0 zero)
5988 %{
5989 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
5990 match(Set mem (StoreP mem zero));
5991
5992 ins_cost(125); // XXX
5993 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5994 ins_encode %{
5995 __ movq($mem$$Address, r12);
5996 %}
5997 ins_pipe(ialu_mem_reg);
5998 %}
5999
6000 // Store NULL Pointer, mark word, or other simple pointer constant.
6001 instruct storeImmP(memory mem, immP31 src)
6002 %{
6003 match(Set mem (StoreP mem src));
6004
6005 ins_cost(150); // XXX
6006 format %{ "movq $mem, $src\t# ptr" %}
6007 opcode(0xC7); /* C7 /0 */
6008 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6009 ins_pipe(ialu_mem_imm);
6010 %}
6011
6012 // Store Compressed Pointer
6013 instruct storeN(memory mem, rRegN src)
6014 %{
6015 match(Set mem (StoreN mem src));
6016
6017 ins_cost(125); // XXX
6018 format %{ "movl $mem, $src\t# compressed ptr" %}
6019 ins_encode %{
6020 __ movl($mem$$Address, $src$$Register);
6021 %}
6022 ins_pipe(ialu_mem_reg);
6023 %}
6024
6025 instruct storeNKlass(memory mem, rRegN src)
6026 %{
6027 match(Set mem (StoreNKlass mem src));
6028
6029 ins_cost(125); // XXX
6030 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6031 ins_encode %{
6032 __ movl($mem$$Address, $src$$Register);
6033 %}
6034 ins_pipe(ialu_mem_reg);
6035 %}
6036
6037 instruct storeImmN0(memory mem, immN0 zero)
6038 %{
6039 predicate(CompressedOops::base() == NULL && CompressedKlassPointers::base() == NULL);
6040 match(Set mem (StoreN mem zero));
6041
6042 ins_cost(125); // XXX
6043 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6044 ins_encode %{
6045 __ movl($mem$$Address, r12);
6046 %}
6047 ins_pipe(ialu_mem_reg);
6048 %}
6049
6050 instruct storeImmN(memory mem, immN src)
6051 %{
6052 match(Set mem (StoreN mem src));
6053
6054 ins_cost(150); // XXX
6055 format %{ "movl $mem, $src\t# compressed ptr" %}
6056 ins_encode %{
6057 address con = (address)$src$$constant;
6058 if (con == NULL) {
6059 __ movl($mem$$Address, (int32_t)0);
6060 } else {
6061 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6062 }
6063 %}
6064 ins_pipe(ialu_mem_imm);
6065 %}
6066
6067 instruct storeImmNKlass(memory mem, immNKlass src)
6068 %{
6069 match(Set mem (StoreNKlass mem src));
6070
6071 ins_cost(150); // XXX
6072 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6073 ins_encode %{
6074 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6075 %}
6076 ins_pipe(ialu_mem_imm);
6077 %}
6078
6079 // Store Integer Immediate
6080 instruct storeImmI0(memory mem, immI_0 zero)
6081 %{
6082 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6083 match(Set mem (StoreI mem zero));
6084
6085 ins_cost(125); // XXX
6086 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6087 ins_encode %{
6088 __ movl($mem$$Address, r12);
6089 %}
6090 ins_pipe(ialu_mem_reg);
6091 %}
6092
6093 instruct storeImmI(memory mem, immI src)
6094 %{
6095 match(Set mem (StoreI mem src));
6096
6097 ins_cost(150);
6098 format %{ "movl $mem, $src\t# int" %}
6099 opcode(0xC7); /* C7 /0 */
6100 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6101 ins_pipe(ialu_mem_imm);
6102 %}
6103
6104 // Store Long Immediate
6105 instruct storeImmL0(memory mem, immL0 zero)
6106 %{
6107 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6108 match(Set mem (StoreL mem zero));
6109
6110 ins_cost(125); // XXX
6111 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6112 ins_encode %{
6113 __ movq($mem$$Address, r12);
6114 %}
6115 ins_pipe(ialu_mem_reg);
6116 %}
6117
6118 instruct storeImmL(memory mem, immL32 src)
6119 %{
6120 match(Set mem (StoreL mem src));
6121
6122 ins_cost(150);
6123 format %{ "movq $mem, $src\t# long" %}
6124 opcode(0xC7); /* C7 /0 */
6125 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6126 ins_pipe(ialu_mem_imm);
6127 %}
6128
6129 // Store Short/Char Immediate
6130 instruct storeImmC0(memory mem, immI_0 zero)
6131 %{
6132 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6133 match(Set mem (StoreC mem zero));
6134
6135 ins_cost(125); // XXX
6136 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6137 ins_encode %{
6138 __ movw($mem$$Address, r12);
6139 %}
6140 ins_pipe(ialu_mem_reg);
6141 %}
6142
6143 instruct storeImmI16(memory mem, immI16 src)
6144 %{
6145 predicate(UseStoreImmI16);
6146 match(Set mem (StoreC mem src));
6147
6148 ins_cost(150);
6149 format %{ "movw $mem, $src\t# short/char" %}
6150 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6151 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6152 ins_pipe(ialu_mem_imm);
6153 %}
6154
6155 // Store Byte Immediate
6156 instruct storeImmB0(memory mem, immI_0 zero)
6157 %{
6158 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6159 match(Set mem (StoreB mem zero));
6160
6161 ins_cost(125); // XXX
6162 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6163 ins_encode %{
6164 __ movb($mem$$Address, r12);
6165 %}
6166 ins_pipe(ialu_mem_reg);
6167 %}
6168
6169 instruct storeImmB(memory mem, immI8 src)
6170 %{
6171 match(Set mem (StoreB mem src));
6172
6173 ins_cost(150); // XXX
6174 format %{ "movb $mem, $src\t# byte" %}
6175 opcode(0xC6); /* C6 /0 */
6176 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6177 ins_pipe(ialu_mem_imm);
6178 %}
6179
6180 // Store CMS card-mark Immediate
6181 instruct storeImmCM0_reg(memory mem, immI_0 zero)
6182 %{
6183 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6184 match(Set mem (StoreCM mem zero));
6185
6186 ins_cost(125); // XXX
6187 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6188 ins_encode %{
6189 __ movb($mem$$Address, r12);
6190 %}
6191 ins_pipe(ialu_mem_reg);
6192 %}
6193
6194 instruct storeImmCM0(memory mem, immI_0 src)
6195 %{
6196 match(Set mem (StoreCM mem src));
6197
6198 ins_cost(150); // XXX
6199 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6200 opcode(0xC6); /* C6 /0 */
6201 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6202 ins_pipe(ialu_mem_imm);
6203 %}
6204
6205 // Store Float
6206 instruct storeF(memory mem, regF src)
6207 %{
6208 match(Set mem (StoreF mem src));
6209
6210 ins_cost(95); // XXX
6211 format %{ "movss $mem, $src\t# float" %}
6212 ins_encode %{
6213 __ movflt($mem$$Address, $src$$XMMRegister);
6214 %}
6215 ins_pipe(pipe_slow); // XXX
6216 %}
6217
6218 // Store immediate Float value (it is faster than store from XMM register)
6219 instruct storeF0(memory mem, immF0 zero)
6220 %{
6221 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6222 match(Set mem (StoreF mem zero));
6223
6224 ins_cost(25); // XXX
6225 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
6226 ins_encode %{
6227 __ movl($mem$$Address, r12);
6228 %}
6229 ins_pipe(ialu_mem_reg);
6230 %}
6231
6232 instruct storeF_imm(memory mem, immF src)
6233 %{
6234 match(Set mem (StoreF mem src));
6235
6236 ins_cost(50);
6237 format %{ "movl $mem, $src\t# float" %}
6238 opcode(0xC7); /* C7 /0 */
6239 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6240 ins_pipe(ialu_mem_imm);
6241 %}
6242
6243 // Store Double
6244 instruct storeD(memory mem, regD src)
6245 %{
6246 match(Set mem (StoreD mem src));
6247
6248 ins_cost(95); // XXX
6249 format %{ "movsd $mem, $src\t# double" %}
6250 ins_encode %{
6251 __ movdbl($mem$$Address, $src$$XMMRegister);
6252 %}
6253 ins_pipe(pipe_slow); // XXX
6254 %}
6255
6256 // Store immediate double 0.0 (it is faster than store from XMM register)
6257 instruct storeD0_imm(memory mem, immD0 src)
6258 %{
6259 predicate(!UseCompressedOops || (CompressedOops::base() != NULL));
6260 match(Set mem (StoreD mem src));
6261
6262 ins_cost(50);
6263 format %{ "movq $mem, $src\t# double 0." %}
6264 opcode(0xC7); /* C7 /0 */
6265 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6266 ins_pipe(ialu_mem_imm);
6267 %}
6268
6269 instruct storeD0(memory mem, immD0 zero)
6270 %{
6271 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL));
6272 match(Set mem (StoreD mem zero));
6273
6274 ins_cost(25); // XXX
6275 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6276 ins_encode %{
6277 __ movq($mem$$Address, r12);
6278 %}
6279 ins_pipe(ialu_mem_reg);
6280 %}
6281
6282 instruct storeSSI(stackSlotI dst, rRegI src)
6283 %{
6284 match(Set dst src);
6285
6286 ins_cost(100);
6287 format %{ "movl $dst, $src\t# int stk" %}
6288 opcode(0x89);
6289 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6290 ins_pipe( ialu_mem_reg );
6291 %}
6292
6293 instruct storeSSL(stackSlotL dst, rRegL src)
6294 %{
6295 match(Set dst src);
6296
6297 ins_cost(100);
6298 format %{ "movq $dst, $src\t# long stk" %}
6299 opcode(0x89);
6300 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6301 ins_pipe(ialu_mem_reg);
6302 %}
6303
6304 instruct storeSSP(stackSlotP dst, rRegP src)
6305 %{
6306 match(Set dst src);
6307
6308 ins_cost(100);
6309 format %{ "movq $dst, $src\t# ptr stk" %}
6310 opcode(0x89);
6311 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6312 ins_pipe(ialu_mem_reg);
6313 %}
6314
6315 instruct storeSSF(stackSlotF dst, regF src)
6316 %{
6317 match(Set dst src);
6318
6319 ins_cost(95); // XXX
6320 format %{ "movss $dst, $src\t# float stk" %}
6321 ins_encode %{
6322 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6323 %}
6324 ins_pipe(pipe_slow); // XXX
6325 %}
6326
6327 instruct storeSSD(stackSlotD dst, regD src)
6328 %{
6329 match(Set dst src);
6330
6331 ins_cost(95); // XXX
6332 format %{ "movsd $dst, $src\t# double stk" %}
6333 ins_encode %{
6334 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6335 %}
6336 ins_pipe(pipe_slow); // XXX
6337 %}
6338
6339 instruct cacheWB(indirect addr)
6340 %{
6341 predicate(VM_Version::supports_data_cache_line_flush());
6342 match(CacheWB addr);
6343
6344 ins_cost(100);
6345 format %{"cache wb $addr" %}
6346 ins_encode %{
6347 assert($addr->index_position() < 0, "should be");
6348 assert($addr$$disp == 0, "should be");
6349 __ cache_wb(Address($addr$$base$$Register, 0));
6350 %}
6351 ins_pipe(pipe_slow); // XXX
6352 %}
6353
6354 instruct cacheWBPreSync()
6355 %{
6356 predicate(VM_Version::supports_data_cache_line_flush());
6357 match(CacheWBPreSync);
6358
6359 ins_cost(100);
6360 format %{"cache wb presync" %}
6361 ins_encode %{
6362 __ cache_wbsync(true);
6363 %}
6364 ins_pipe(pipe_slow); // XXX
6365 %}
6366
6367 instruct cacheWBPostSync()
6368 %{
6369 predicate(VM_Version::supports_data_cache_line_flush());
6370 match(CacheWBPostSync);
6371
6372 ins_cost(100);
6373 format %{"cache wb postsync" %}
6374 ins_encode %{
6375 __ cache_wbsync(false);
6376 %}
6377 ins_pipe(pipe_slow); // XXX
6378 %}
6379
6380 //----------BSWAP Instructions-------------------------------------------------
6381 instruct bytes_reverse_int(rRegI dst) %{
6382 match(Set dst (ReverseBytesI dst));
6383
6384 format %{ "bswapl $dst" %}
6385 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6386 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6387 ins_pipe( ialu_reg );
6388 %}
6389
6390 instruct bytes_reverse_long(rRegL dst) %{
6391 match(Set dst (ReverseBytesL dst));
6392
6393 format %{ "bswapq $dst" %}
6394 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6395 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6396 ins_pipe( ialu_reg);
6397 %}
6398
6399 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6400 match(Set dst (ReverseBytesUS dst));
6401 effect(KILL cr);
6402
6403 format %{ "bswapl $dst\n\t"
6404 "shrl $dst,16\n\t" %}
6405 ins_encode %{
6406 __ bswapl($dst$$Register);
6407 __ shrl($dst$$Register, 16);
6408 %}
6409 ins_pipe( ialu_reg );
6410 %}
6411
6412 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6413 match(Set dst (ReverseBytesS dst));
6414 effect(KILL cr);
6415
6416 format %{ "bswapl $dst\n\t"
6417 "sar $dst,16\n\t" %}
6418 ins_encode %{
6419 __ bswapl($dst$$Register);
6420 __ sarl($dst$$Register, 16);
6421 %}
6422 ins_pipe( ialu_reg );
6423 %}
6424
6425 //---------- Zeros Count Instructions ------------------------------------------
6426
6427 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6428 predicate(UseCountLeadingZerosInstruction);
6429 match(Set dst (CountLeadingZerosI src));
6430 effect(KILL cr);
6431
6432 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6433 ins_encode %{
6434 __ lzcntl($dst$$Register, $src$$Register);
6435 %}
6436 ins_pipe(ialu_reg);
6437 %}
6438
6439 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6440 predicate(!UseCountLeadingZerosInstruction);
6441 match(Set dst (CountLeadingZerosI src));
6442 effect(KILL cr);
6443
6444 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6445 "jnz skip\n\t"
6446 "movl $dst, -1\n"
6447 "skip:\n\t"
6448 "negl $dst\n\t"
6449 "addl $dst, 31" %}
6450 ins_encode %{
6451 Register Rdst = $dst$$Register;
6452 Register Rsrc = $src$$Register;
6453 Label skip;
6454 __ bsrl(Rdst, Rsrc);
6455 __ jccb(Assembler::notZero, skip);
6456 __ movl(Rdst, -1);
6457 __ bind(skip);
6458 __ negl(Rdst);
6459 __ addl(Rdst, BitsPerInt - 1);
6460 %}
6461 ins_pipe(ialu_reg);
6462 %}
6463
6464 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6465 predicate(UseCountLeadingZerosInstruction);
6466 match(Set dst (CountLeadingZerosL src));
6467 effect(KILL cr);
6468
6469 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6470 ins_encode %{
6471 __ lzcntq($dst$$Register, $src$$Register);
6472 %}
6473 ins_pipe(ialu_reg);
6474 %}
6475
6476 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6477 predicate(!UseCountLeadingZerosInstruction);
6478 match(Set dst (CountLeadingZerosL src));
6479 effect(KILL cr);
6480
6481 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6482 "jnz skip\n\t"
6483 "movl $dst, -1\n"
6484 "skip:\n\t"
6485 "negl $dst\n\t"
6486 "addl $dst, 63" %}
6487 ins_encode %{
6488 Register Rdst = $dst$$Register;
6489 Register Rsrc = $src$$Register;
6490 Label skip;
6491 __ bsrq(Rdst, Rsrc);
6492 __ jccb(Assembler::notZero, skip);
6493 __ movl(Rdst, -1);
6494 __ bind(skip);
6495 __ negl(Rdst);
6496 __ addl(Rdst, BitsPerLong - 1);
6497 %}
6498 ins_pipe(ialu_reg);
6499 %}
6500
6501 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6502 predicate(UseCountTrailingZerosInstruction);
6503 match(Set dst (CountTrailingZerosI src));
6504 effect(KILL cr);
6505
6506 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6507 ins_encode %{
6508 __ tzcntl($dst$$Register, $src$$Register);
6509 %}
6510 ins_pipe(ialu_reg);
6511 %}
6512
6513 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6514 predicate(!UseCountTrailingZerosInstruction);
6515 match(Set dst (CountTrailingZerosI src));
6516 effect(KILL cr);
6517
6518 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6519 "jnz done\n\t"
6520 "movl $dst, 32\n"
6521 "done:" %}
6522 ins_encode %{
6523 Register Rdst = $dst$$Register;
6524 Label done;
6525 __ bsfl(Rdst, $src$$Register);
6526 __ jccb(Assembler::notZero, done);
6527 __ movl(Rdst, BitsPerInt);
6528 __ bind(done);
6529 %}
6530 ins_pipe(ialu_reg);
6531 %}
6532
6533 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6534 predicate(UseCountTrailingZerosInstruction);
6535 match(Set dst (CountTrailingZerosL src));
6536 effect(KILL cr);
6537
6538 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6539 ins_encode %{
6540 __ tzcntq($dst$$Register, $src$$Register);
6541 %}
6542 ins_pipe(ialu_reg);
6543 %}
6544
6545 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6546 predicate(!UseCountTrailingZerosInstruction);
6547 match(Set dst (CountTrailingZerosL src));
6548 effect(KILL cr);
6549
6550 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6551 "jnz done\n\t"
6552 "movl $dst, 64\n"
6553 "done:" %}
6554 ins_encode %{
6555 Register Rdst = $dst$$Register;
6556 Label done;
6557 __ bsfq(Rdst, $src$$Register);
6558 __ jccb(Assembler::notZero, done);
6559 __ movl(Rdst, BitsPerLong);
6560 __ bind(done);
6561 %}
6562 ins_pipe(ialu_reg);
6563 %}
6564
6565
6566 //---------- Population Count Instructions -------------------------------------
6567
6568 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6569 predicate(UsePopCountInstruction);
6570 match(Set dst (PopCountI src));
6571 effect(KILL cr);
6572
6573 format %{ "popcnt $dst, $src" %}
6574 ins_encode %{
6575 __ popcntl($dst$$Register, $src$$Register);
6576 %}
6577 ins_pipe(ialu_reg);
6578 %}
6579
6580 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6581 predicate(UsePopCountInstruction);
6582 match(Set dst (PopCountI (LoadI mem)));
6583 effect(KILL cr);
6584
6585 format %{ "popcnt $dst, $mem" %}
6586 ins_encode %{
6587 __ popcntl($dst$$Register, $mem$$Address);
6588 %}
6589 ins_pipe(ialu_reg);
6590 %}
6591
6592 // Note: Long.bitCount(long) returns an int.
6593 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6594 predicate(UsePopCountInstruction);
6595 match(Set dst (PopCountL src));
6596 effect(KILL cr);
6597
6598 format %{ "popcnt $dst, $src" %}
6599 ins_encode %{
6600 __ popcntq($dst$$Register, $src$$Register);
6601 %}
6602 ins_pipe(ialu_reg);
6603 %}
6604
6605 // Note: Long.bitCount(long) returns an int.
6606 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6607 predicate(UsePopCountInstruction);
6608 match(Set dst (PopCountL (LoadL mem)));
6609 effect(KILL cr);
6610
6611 format %{ "popcnt $dst, $mem" %}
6612 ins_encode %{
6613 __ popcntq($dst$$Register, $mem$$Address);
6614 %}
6615 ins_pipe(ialu_reg);
6616 %}
6617
6618
6619 //----------MemBar Instructions-----------------------------------------------
6620 // Memory barrier flavors
6621
6622 instruct membar_acquire()
6623 %{
6624 match(MemBarAcquire);
6625 match(LoadFence);
6626 ins_cost(0);
6627
6628 size(0);
6629 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6630 ins_encode();
6631 ins_pipe(empty);
6632 %}
6633
6634 instruct membar_acquire_lock()
6635 %{
6636 match(MemBarAcquireLock);
6637 ins_cost(0);
6638
6639 size(0);
6640 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6641 ins_encode();
6642 ins_pipe(empty);
6643 %}
6644
6645 instruct membar_release()
6646 %{
6647 match(MemBarRelease);
6648 match(StoreFence);
6649 ins_cost(0);
6650
6651 size(0);
6652 format %{ "MEMBAR-release ! (empty encoding)" %}
6653 ins_encode();
6654 ins_pipe(empty);
6655 %}
6656
6657 instruct membar_release_lock()
6658 %{
6659 match(MemBarReleaseLock);
6660 ins_cost(0);
6661
6662 size(0);
6663 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6664 ins_encode();
6665 ins_pipe(empty);
6666 %}
6667
6668 instruct membar_volatile(rFlagsReg cr) %{
6669 match(MemBarVolatile);
6670 effect(KILL cr);
6671 ins_cost(400);
6672
6673 format %{
6674 $$template
6675 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6676 %}
6677 ins_encode %{
6678 __ membar(Assembler::StoreLoad);
6679 %}
6680 ins_pipe(pipe_slow);
6681 %}
6682
6683 instruct unnecessary_membar_volatile()
6684 %{
6685 match(MemBarVolatile);
6686 predicate(Matcher::post_store_load_barrier(n));
6687 ins_cost(0);
6688
6689 size(0);
6690 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6691 ins_encode();
6692 ins_pipe(empty);
6693 %}
6694
6695 instruct membar_storestore() %{
6696 match(MemBarStoreStore);
6697 ins_cost(0);
6698
6699 size(0);
6700 format %{ "MEMBAR-storestore (empty encoding)" %}
6701 ins_encode( );
6702 ins_pipe(empty);
6703 %}
6704
6705 //----------Move Instructions--------------------------------------------------
6706
6707 instruct castX2P(rRegP dst, rRegL src)
6708 %{
6709 match(Set dst (CastX2P src));
6710
6711 format %{ "movq $dst, $src\t# long->ptr" %}
6712 ins_encode %{
6713 if ($dst$$reg != $src$$reg) {
6714 __ movptr($dst$$Register, $src$$Register);
6715 }
6716 %}
6717 ins_pipe(ialu_reg_reg); // XXX
6718 %}
6719
6720 instruct castP2X(rRegL dst, rRegP src)
6721 %{
6722 match(Set dst (CastP2X src));
6723
6724 format %{ "movq $dst, $src\t# ptr -> long" %}
6725 ins_encode %{
6726 if ($dst$$reg != $src$$reg) {
6727 __ movptr($dst$$Register, $src$$Register);
6728 }
6729 %}
6730 ins_pipe(ialu_reg_reg); // XXX
6731 %}
6732
6733 // Convert oop into int for vectors alignment masking
6734 instruct convP2I(rRegI dst, rRegP src)
6735 %{
6736 match(Set dst (ConvL2I (CastP2X src)));
6737
6738 format %{ "movl $dst, $src\t# ptr -> int" %}
6739 ins_encode %{
6740 __ movl($dst$$Register, $src$$Register);
6741 %}
6742 ins_pipe(ialu_reg_reg); // XXX
6743 %}
6744
6745 // Convert compressed oop into int for vectors alignment masking
6746 // in case of 32bit oops (heap < 4Gb).
6747 instruct convN2I(rRegI dst, rRegN src)
6748 %{
6749 predicate(CompressedOops::shift() == 0);
6750 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6751
6752 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6753 ins_encode %{
6754 __ movl($dst$$Register, $src$$Register);
6755 %}
6756 ins_pipe(ialu_reg_reg); // XXX
6757 %}
6758
6759 // Convert oop pointer into compressed form
6760 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6761 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6762 match(Set dst (EncodeP src));
6763 effect(KILL cr);
6764 format %{ "encode_heap_oop $dst,$src" %}
6765 ins_encode %{
6766 Register s = $src$$Register;
6767 Register d = $dst$$Register;
6768 if (s != d) {
6769 __ movq(d, s);
6770 }
6771 __ encode_heap_oop(d);
6772 %}
6773 ins_pipe(ialu_reg_long);
6774 %}
6775
6776 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6777 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6778 match(Set dst (EncodeP src));
6779 effect(KILL cr);
6780 format %{ "encode_heap_oop_not_null $dst,$src" %}
6781 ins_encode %{
6782 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6783 %}
6784 ins_pipe(ialu_reg_long);
6785 %}
6786
6787 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6788 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6789 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6790 match(Set dst (DecodeN src));
6791 effect(KILL cr);
6792 format %{ "decode_heap_oop $dst,$src" %}
6793 ins_encode %{
6794 Register s = $src$$Register;
6795 Register d = $dst$$Register;
6796 if (s != d) {
6797 __ movq(d, s);
6798 }
6799 __ decode_heap_oop(d);
6800 %}
6801 ins_pipe(ialu_reg_long);
6802 %}
6803
6804 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6805 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6806 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6807 match(Set dst (DecodeN src));
6808 effect(KILL cr);
6809 format %{ "decode_heap_oop_not_null $dst,$src" %}
6810 ins_encode %{
6811 Register s = $src$$Register;
6812 Register d = $dst$$Register;
6813 if (s != d) {
6814 __ decode_heap_oop_not_null(d, s);
6815 } else {
6816 __ decode_heap_oop_not_null(d);
6817 }
6818 %}
6819 ins_pipe(ialu_reg_long);
6820 %}
6821
6822 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6823 match(Set dst (EncodePKlass src));
6824 effect(KILL cr);
6825 format %{ "encode_klass_not_null $dst,$src" %}
6826 ins_encode %{
6827 __ encode_klass_not_null($dst$$Register, $src$$Register);
6828 %}
6829 ins_pipe(ialu_reg_long);
6830 %}
6831
6832 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6833 match(Set dst (DecodeNKlass src));
6834 effect(KILL cr);
6835 format %{ "decode_klass_not_null $dst,$src" %}
6836 ins_encode %{
6837 Register s = $src$$Register;
6838 Register d = $dst$$Register;
6839 if (s != d) {
6840 __ decode_klass_not_null(d, s);
6841 } else {
6842 __ decode_klass_not_null(d);
6843 }
6844 %}
6845 ins_pipe(ialu_reg_long);
6846 %}
6847
6848
6849 //----------Conditional Move---------------------------------------------------
6850 // Jump
6851 // dummy instruction for generating temp registers
6852 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6853 match(Jump (LShiftL switch_val shift));
6854 ins_cost(350);
6855 predicate(false);
6856 effect(TEMP dest);
6857
6858 format %{ "leaq $dest, [$constantaddress]\n\t"
6859 "jmp [$dest + $switch_val << $shift]\n\t" %}
6860 ins_encode %{
6861 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6862 // to do that and the compiler is using that register as one it can allocate.
6863 // So we build it all by hand.
6864 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6865 // ArrayAddress dispatch(table, index);
6866 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6867 __ lea($dest$$Register, $constantaddress);
6868 __ jmp(dispatch);
6869 %}
6870 ins_pipe(pipe_jmp);
6871 %}
6872
6873 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6874 match(Jump (AddL (LShiftL switch_val shift) offset));
6875 ins_cost(350);
6876 effect(TEMP dest);
6877
6878 format %{ "leaq $dest, [$constantaddress]\n\t"
6879 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6880 ins_encode %{
6881 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6882 // to do that and the compiler is using that register as one it can allocate.
6883 // So we build it all by hand.
6884 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6885 // ArrayAddress dispatch(table, index);
6886 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6887 __ lea($dest$$Register, $constantaddress);
6888 __ jmp(dispatch);
6889 %}
6890 ins_pipe(pipe_jmp);
6891 %}
6892
6893 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6894 match(Jump switch_val);
6895 ins_cost(350);
6896 effect(TEMP dest);
6897
6898 format %{ "leaq $dest, [$constantaddress]\n\t"
6899 "jmp [$dest + $switch_val]\n\t" %}
6900 ins_encode %{
6901 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6902 // to do that and the compiler is using that register as one it can allocate.
6903 // So we build it all by hand.
6904 // Address index(noreg, switch_reg, Address::times_1);
6905 // ArrayAddress dispatch(table, index);
6906 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6907 __ lea($dest$$Register, $constantaddress);
6908 __ jmp(dispatch);
6909 %}
6910 ins_pipe(pipe_jmp);
6911 %}
6912
6913 // Conditional move
6914 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6915 %{
6916 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6917
6918 ins_cost(200); // XXX
6919 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6920 opcode(0x0F, 0x40);
6921 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6922 ins_pipe(pipe_cmov_reg);
6923 %}
6924
6925 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6926 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6927
6928 ins_cost(200); // XXX
6929 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6930 opcode(0x0F, 0x40);
6931 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6932 ins_pipe(pipe_cmov_reg);
6933 %}
6934
6935 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6936 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6937 ins_cost(200);
6938 expand %{
6939 cmovI_regU(cop, cr, dst, src);
6940 %}
6941 %}
6942
6943 // Conditional move
6944 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6945 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6946
6947 ins_cost(250); // XXX
6948 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6949 opcode(0x0F, 0x40);
6950 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6951 ins_pipe(pipe_cmov_mem);
6952 %}
6953
6954 // Conditional move
6955 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6956 %{
6957 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6958
6959 ins_cost(250); // XXX
6960 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6961 opcode(0x0F, 0x40);
6962 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6963 ins_pipe(pipe_cmov_mem);
6964 %}
6965
6966 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6967 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6968 ins_cost(250);
6969 expand %{
6970 cmovI_memU(cop, cr, dst, src);
6971 %}
6972 %}
6973
6974 // Conditional move
6975 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6976 %{
6977 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6978
6979 ins_cost(200); // XXX
6980 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6981 opcode(0x0F, 0x40);
6982 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6983 ins_pipe(pipe_cmov_reg);
6984 %}
6985
6986 // Conditional move
6987 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6988 %{
6989 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6990
6991 ins_cost(200); // XXX
6992 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6993 opcode(0x0F, 0x40);
6994 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6995 ins_pipe(pipe_cmov_reg);
6996 %}
6997
6998 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6999 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7000 ins_cost(200);
7001 expand %{
7002 cmovN_regU(cop, cr, dst, src);
7003 %}
7004 %}
7005
7006 // Conditional move
7007 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7008 %{
7009 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7010
7011 ins_cost(200); // XXX
7012 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7013 opcode(0x0F, 0x40);
7014 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7015 ins_pipe(pipe_cmov_reg); // XXX
7016 %}
7017
7018 // Conditional move
7019 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7020 %{
7021 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7022
7023 ins_cost(200); // XXX
7024 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7025 opcode(0x0F, 0x40);
7026 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7027 ins_pipe(pipe_cmov_reg); // XXX
7028 %}
7029
7030 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7031 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7032 ins_cost(200);
7033 expand %{
7034 cmovP_regU(cop, cr, dst, src);
7035 %}
7036 %}
7037
7038 // DISABLED: Requires the ADLC to emit a bottom_type call that
7039 // correctly meets the two pointer arguments; one is an incoming
7040 // register but the other is a memory operand. ALSO appears to
7041 // be buggy with implicit null checks.
7042 //
7043 //// Conditional move
7044 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7045 //%{
7046 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7047 // ins_cost(250);
7048 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7049 // opcode(0x0F,0x40);
7050 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7051 // ins_pipe( pipe_cmov_mem );
7052 //%}
7053 //
7054 //// Conditional move
7055 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7056 //%{
7057 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7058 // ins_cost(250);
7059 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7060 // opcode(0x0F,0x40);
7061 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7062 // ins_pipe( pipe_cmov_mem );
7063 //%}
7064
7065 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7066 %{
7067 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7068
7069 ins_cost(200); // XXX
7070 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7071 opcode(0x0F, 0x40);
7072 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7073 ins_pipe(pipe_cmov_reg); // XXX
7074 %}
7075
7076 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7077 %{
7078 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7079
7080 ins_cost(200); // XXX
7081 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7082 opcode(0x0F, 0x40);
7083 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7084 ins_pipe(pipe_cmov_mem); // XXX
7085 %}
7086
7087 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7088 %{
7089 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7090
7091 ins_cost(200); // XXX
7092 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7093 opcode(0x0F, 0x40);
7094 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7095 ins_pipe(pipe_cmov_reg); // XXX
7096 %}
7097
7098 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7099 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7100 ins_cost(200);
7101 expand %{
7102 cmovL_regU(cop, cr, dst, src);
7103 %}
7104 %}
7105
7106 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7107 %{
7108 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7109
7110 ins_cost(200); // XXX
7111 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7112 opcode(0x0F, 0x40);
7113 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7114 ins_pipe(pipe_cmov_mem); // XXX
7115 %}
7116
7117 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7118 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7119 ins_cost(200);
7120 expand %{
7121 cmovL_memU(cop, cr, dst, src);
7122 %}
7123 %}
7124
7125 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7126 %{
7127 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7128
7129 ins_cost(200); // XXX
7130 format %{ "jn$cop skip\t# signed cmove float\n\t"
7131 "movss $dst, $src\n"
7132 "skip:" %}
7133 ins_encode %{
7134 Label Lskip;
7135 // Invert sense of branch from sense of CMOV
7136 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7137 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7138 __ bind(Lskip);
7139 %}
7140 ins_pipe(pipe_slow);
7141 %}
7142
7143 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7144 // %{
7145 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7146
7147 // ins_cost(200); // XXX
7148 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7149 // "movss $dst, $src\n"
7150 // "skip:" %}
7151 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7152 // ins_pipe(pipe_slow);
7153 // %}
7154
7155 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7156 %{
7157 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7158
7159 ins_cost(200); // XXX
7160 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7161 "movss $dst, $src\n"
7162 "skip:" %}
7163 ins_encode %{
7164 Label Lskip;
7165 // Invert sense of branch from sense of CMOV
7166 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7167 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7168 __ bind(Lskip);
7169 %}
7170 ins_pipe(pipe_slow);
7171 %}
7172
7173 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7174 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7175 ins_cost(200);
7176 expand %{
7177 cmovF_regU(cop, cr, dst, src);
7178 %}
7179 %}
7180
7181 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7182 %{
7183 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7184
7185 ins_cost(200); // XXX
7186 format %{ "jn$cop skip\t# signed cmove double\n\t"
7187 "movsd $dst, $src\n"
7188 "skip:" %}
7189 ins_encode %{
7190 Label Lskip;
7191 // Invert sense of branch from sense of CMOV
7192 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7193 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7194 __ bind(Lskip);
7195 %}
7196 ins_pipe(pipe_slow);
7197 %}
7198
7199 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7200 %{
7201 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7202
7203 ins_cost(200); // XXX
7204 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7205 "movsd $dst, $src\n"
7206 "skip:" %}
7207 ins_encode %{
7208 Label Lskip;
7209 // Invert sense of branch from sense of CMOV
7210 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7211 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7212 __ bind(Lskip);
7213 %}
7214 ins_pipe(pipe_slow);
7215 %}
7216
7217 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7218 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7219 ins_cost(200);
7220 expand %{
7221 cmovD_regU(cop, cr, dst, src);
7222 %}
7223 %}
7224
7225 //----------Arithmetic Instructions--------------------------------------------
7226 //----------Addition Instructions----------------------------------------------
7227
7228 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7229 %{
7230 match(Set dst (AddI dst src));
7231 effect(KILL cr);
7232
7233 format %{ "addl $dst, $src\t# int" %}
7234 opcode(0x03);
7235 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7236 ins_pipe(ialu_reg_reg);
7237 %}
7238
7239 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7240 %{
7241 match(Set dst (AddI dst src));
7242 effect(KILL cr);
7243
7244 format %{ "addl $dst, $src\t# int" %}
7245 opcode(0x81, 0x00); /* /0 id */
7246 ins_encode(OpcSErm(dst, src), Con8or32(src));
7247 ins_pipe( ialu_reg );
7248 %}
7249
7250 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7251 %{
7252 match(Set dst (AddI dst (LoadI src)));
7253 effect(KILL cr);
7254
7255 ins_cost(125); // XXX
7256 format %{ "addl $dst, $src\t# int" %}
7257 opcode(0x03);
7258 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7259 ins_pipe(ialu_reg_mem);
7260 %}
7261
7262 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7263 %{
7264 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7265 effect(KILL cr);
7266
7267 ins_cost(150); // XXX
7268 format %{ "addl $dst, $src\t# int" %}
7269 opcode(0x01); /* Opcode 01 /r */
7270 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7271 ins_pipe(ialu_mem_reg);
7272 %}
7273
7274 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7275 %{
7276 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7277 effect(KILL cr);
7278
7279 ins_cost(125); // XXX
7280 format %{ "addl $dst, $src\t# int" %}
7281 opcode(0x81); /* Opcode 81 /0 id */
7282 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7283 ins_pipe(ialu_mem_imm);
7284 %}
7285
7286 instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
7287 %{
7288 predicate(UseIncDec);
7289 match(Set dst (AddI dst src));
7290 effect(KILL cr);
7291
7292 format %{ "incl $dst\t# int" %}
7293 opcode(0xFF, 0x00); // FF /0
7294 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7295 ins_pipe(ialu_reg);
7296 %}
7297
7298 instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr)
7299 %{
7300 predicate(UseIncDec);
7301 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7302 effect(KILL cr);
7303
7304 ins_cost(125); // XXX
7305 format %{ "incl $dst\t# int" %}
7306 opcode(0xFF); /* Opcode FF /0 */
7307 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7308 ins_pipe(ialu_mem_imm);
7309 %}
7310
7311 // XXX why does that use AddI
7312 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7313 %{
7314 predicate(UseIncDec);
7315 match(Set dst (AddI dst src));
7316 effect(KILL cr);
7317
7318 format %{ "decl $dst\t# int" %}
7319 opcode(0xFF, 0x01); // FF /1
7320 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7321 ins_pipe(ialu_reg);
7322 %}
7323
7324 // XXX why does that use AddI
7325 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7326 %{
7327 predicate(UseIncDec);
7328 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7329 effect(KILL cr);
7330
7331 ins_cost(125); // XXX
7332 format %{ "decl $dst\t# int" %}
7333 opcode(0xFF); /* Opcode FF /1 */
7334 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7335 ins_pipe(ialu_mem_imm);
7336 %}
7337
7338 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7339 %{
7340 match(Set dst (AddI src0 src1));
7341
7342 ins_cost(110);
7343 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7344 opcode(0x8D); /* 0x8D /r */
7345 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7346 ins_pipe(ialu_reg_reg);
7347 %}
7348
7349 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7350 %{
7351 match(Set dst (AddL dst src));
7352 effect(KILL cr);
7353
7354 format %{ "addq $dst, $src\t# long" %}
7355 opcode(0x03);
7356 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7357 ins_pipe(ialu_reg_reg);
7358 %}
7359
7360 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7361 %{
7362 match(Set dst (AddL dst src));
7363 effect(KILL cr);
7364
7365 format %{ "addq $dst, $src\t# long" %}
7366 opcode(0x81, 0x00); /* /0 id */
7367 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7368 ins_pipe( ialu_reg );
7369 %}
7370
7371 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7372 %{
7373 match(Set dst (AddL dst (LoadL src)));
7374 effect(KILL cr);
7375
7376 ins_cost(125); // XXX
7377 format %{ "addq $dst, $src\t# long" %}
7378 opcode(0x03);
7379 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7380 ins_pipe(ialu_reg_mem);
7381 %}
7382
7383 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7384 %{
7385 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7386 effect(KILL cr);
7387
7388 ins_cost(150); // XXX
7389 format %{ "addq $dst, $src\t# long" %}
7390 opcode(0x01); /* Opcode 01 /r */
7391 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7392 ins_pipe(ialu_mem_reg);
7393 %}
7394
7395 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7396 %{
7397 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7398 effect(KILL cr);
7399
7400 ins_cost(125); // XXX
7401 format %{ "addq $dst, $src\t# long" %}
7402 opcode(0x81); /* Opcode 81 /0 id */
7403 ins_encode(REX_mem_wide(dst),
7404 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7405 ins_pipe(ialu_mem_imm);
7406 %}
7407
7408 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7409 %{
7410 predicate(UseIncDec);
7411 match(Set dst (AddL dst src));
7412 effect(KILL cr);
7413
7414 format %{ "incq $dst\t# long" %}
7415 opcode(0xFF, 0x00); // FF /0
7416 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7417 ins_pipe(ialu_reg);
7418 %}
7419
7420 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7421 %{
7422 predicate(UseIncDec);
7423 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7424 effect(KILL cr);
7425
7426 ins_cost(125); // XXX
7427 format %{ "incq $dst\t# long" %}
7428 opcode(0xFF); /* Opcode FF /0 */
7429 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7430 ins_pipe(ialu_mem_imm);
7431 %}
7432
7433 // XXX why does that use AddL
7434 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7435 %{
7436 predicate(UseIncDec);
7437 match(Set dst (AddL dst src));
7438 effect(KILL cr);
7439
7440 format %{ "decq $dst\t# long" %}
7441 opcode(0xFF, 0x01); // FF /1
7442 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7443 ins_pipe(ialu_reg);
7444 %}
7445
7446 // XXX why does that use AddL
7447 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7448 %{
7449 predicate(UseIncDec);
7450 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7451 effect(KILL cr);
7452
7453 ins_cost(125); // XXX
7454 format %{ "decq $dst\t# long" %}
7455 opcode(0xFF); /* Opcode FF /1 */
7456 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7457 ins_pipe(ialu_mem_imm);
7458 %}
7459
7460 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7461 %{
7462 match(Set dst (AddL src0 src1));
7463
7464 ins_cost(110);
7465 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7466 opcode(0x8D); /* 0x8D /r */
7467 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7468 ins_pipe(ialu_reg_reg);
7469 %}
7470
7471 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7472 %{
7473 match(Set dst (AddP dst src));
7474 effect(KILL cr);
7475
7476 format %{ "addq $dst, $src\t# ptr" %}
7477 opcode(0x03);
7478 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7479 ins_pipe(ialu_reg_reg);
7480 %}
7481
7482 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7483 %{
7484 match(Set dst (AddP dst src));
7485 effect(KILL cr);
7486
7487 format %{ "addq $dst, $src\t# ptr" %}
7488 opcode(0x81, 0x00); /* /0 id */
7489 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7490 ins_pipe( ialu_reg );
7491 %}
7492
7493 // XXX addP mem ops ????
7494
7495 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7496 %{
7497 match(Set dst (AddP src0 src1));
7498
7499 ins_cost(110);
7500 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7501 opcode(0x8D); /* 0x8D /r */
7502 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7503 ins_pipe(ialu_reg_reg);
7504 %}
7505
7506 instruct checkCastPP(rRegP dst)
7507 %{
7508 match(Set dst (CheckCastPP dst));
7509
7510 size(0);
7511 format %{ "# checkcastPP of $dst" %}
7512 ins_encode(/* empty encoding */);
7513 ins_pipe(empty);
7514 %}
7515
7516 instruct castPP(rRegP dst)
7517 %{
7518 match(Set dst (CastPP dst));
7519
7520 size(0);
7521 format %{ "# castPP of $dst" %}
7522 ins_encode(/* empty encoding */);
7523 ins_pipe(empty);
7524 %}
7525
7526 instruct castII(rRegI dst)
7527 %{
7528 match(Set dst (CastII dst));
7529
7530 size(0);
7531 format %{ "# castII of $dst" %}
7532 ins_encode(/* empty encoding */);
7533 ins_cost(0);
7534 ins_pipe(empty);
7535 %}
7536
7537 instruct castLL(rRegL dst)
7538 %{
7539 match(Set dst (CastLL dst));
7540
7541 size(0);
7542 format %{ "# castLL of $dst" %}
7543 ins_encode(/* empty encoding */);
7544 ins_cost(0);
7545 ins_pipe(empty);
7546 %}
7547
7548 // LoadP-locked same as a regular LoadP when used with compare-swap
7549 instruct loadPLocked(rRegP dst, memory mem)
7550 %{
7551 match(Set dst (LoadPLocked mem));
7552
7553 ins_cost(125); // XXX
7554 format %{ "movq $dst, $mem\t# ptr locked" %}
7555 opcode(0x8B);
7556 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7557 ins_pipe(ialu_reg_mem); // XXX
7558 %}
7559
7560 // Conditional-store of the updated heap-top.
7561 // Used during allocation of the shared heap.
7562 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7563
7564 instruct storePConditional(memory heap_top_ptr,
7565 rax_RegP oldval, rRegP newval,
7566 rFlagsReg cr)
7567 %{
7568 predicate(n->as_LoadStore()->barrier_data() == 0);
7569 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7570
7571 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7572 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7573 opcode(0x0F, 0xB1);
7574 ins_encode(lock_prefix,
7575 REX_reg_mem_wide(newval, heap_top_ptr),
7576 OpcP, OpcS,
7577 reg_mem(newval, heap_top_ptr));
7578 ins_pipe(pipe_cmpxchg);
7579 %}
7580
7581 // Conditional-store of an int value.
7582 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7583 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7584 %{
7585 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7586 effect(KILL oldval);
7587
7588 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7589 opcode(0x0F, 0xB1);
7590 ins_encode(lock_prefix,
7591 REX_reg_mem(newval, mem),
7592 OpcP, OpcS,
7593 reg_mem(newval, mem));
7594 ins_pipe(pipe_cmpxchg);
7595 %}
7596
7597 // Conditional-store of a long value.
7598 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7599 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7600 %{
7601 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7602 effect(KILL oldval);
7603
7604 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7605 opcode(0x0F, 0xB1);
7606 ins_encode(lock_prefix,
7607 REX_reg_mem_wide(newval, mem),
7608 OpcP, OpcS,
7609 reg_mem(newval, mem));
7610 ins_pipe(pipe_cmpxchg);
7611 %}
7612
7613
7614 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7615 instruct compareAndSwapP(rRegI res,
7616 memory mem_ptr,
7617 rax_RegP oldval, rRegP newval,
7618 rFlagsReg cr)
7619 %{
7620 predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0);
7621 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7622 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7623 effect(KILL cr, KILL oldval);
7624
7625 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7626 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7627 "sete $res\n\t"
7628 "movzbl $res, $res" %}
7629 opcode(0x0F, 0xB1);
7630 ins_encode(lock_prefix,
7631 REX_reg_mem_wide(newval, mem_ptr),
7632 OpcP, OpcS,
7633 reg_mem(newval, mem_ptr),
7634 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7635 REX_reg_breg(res, res), // movzbl
7636 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7637 ins_pipe( pipe_cmpxchg );
7638 %}
7639
7640 instruct compareAndSwapL(rRegI res,
7641 memory mem_ptr,
7642 rax_RegL oldval, rRegL newval,
7643 rFlagsReg cr)
7644 %{
7645 predicate(VM_Version::supports_cx8());
7646 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7647 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7648 effect(KILL cr, KILL oldval);
7649
7650 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7651 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7652 "sete $res\n\t"
7653 "movzbl $res, $res" %}
7654 opcode(0x0F, 0xB1);
7655 ins_encode(lock_prefix,
7656 REX_reg_mem_wide(newval, mem_ptr),
7657 OpcP, OpcS,
7658 reg_mem(newval, mem_ptr),
7659 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7660 REX_reg_breg(res, res), // movzbl
7661 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7662 ins_pipe( pipe_cmpxchg );
7663 %}
7664
7665 instruct compareAndSwapI(rRegI res,
7666 memory mem_ptr,
7667 rax_RegI oldval, rRegI newval,
7668 rFlagsReg cr)
7669 %{
7670 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7671 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7672 effect(KILL cr, KILL oldval);
7673
7674 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7675 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7676 "sete $res\n\t"
7677 "movzbl $res, $res" %}
7678 opcode(0x0F, 0xB1);
7679 ins_encode(lock_prefix,
7680 REX_reg_mem(newval, mem_ptr),
7681 OpcP, OpcS,
7682 reg_mem(newval, mem_ptr),
7683 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7684 REX_reg_breg(res, res), // movzbl
7685 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7686 ins_pipe( pipe_cmpxchg );
7687 %}
7688
7689 instruct compareAndSwapB(rRegI res,
7690 memory mem_ptr,
7691 rax_RegI oldval, rRegI newval,
7692 rFlagsReg cr)
7693 %{
7694 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7695 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7696 effect(KILL cr, KILL oldval);
7697
7698 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7699 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7700 "sete $res\n\t"
7701 "movzbl $res, $res" %}
7702 opcode(0x0F, 0xB0);
7703 ins_encode(lock_prefix,
7704 REX_breg_mem(newval, mem_ptr),
7705 OpcP, OpcS,
7706 reg_mem(newval, mem_ptr),
7707 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7708 REX_reg_breg(res, res), // movzbl
7709 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7710 ins_pipe( pipe_cmpxchg );
7711 %}
7712
7713 instruct compareAndSwapS(rRegI res,
7714 memory mem_ptr,
7715 rax_RegI oldval, rRegI newval,
7716 rFlagsReg cr)
7717 %{
7718 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7719 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7720 effect(KILL cr, KILL oldval);
7721
7722 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7723 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7724 "sete $res\n\t"
7725 "movzbl $res, $res" %}
7726 opcode(0x0F, 0xB1);
7727 ins_encode(lock_prefix,
7728 SizePrefix,
7729 REX_reg_mem(newval, mem_ptr),
7730 OpcP, OpcS,
7731 reg_mem(newval, mem_ptr),
7732 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7733 REX_reg_breg(res, res), // movzbl
7734 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7735 ins_pipe( pipe_cmpxchg );
7736 %}
7737
7738 instruct compareAndSwapN(rRegI res,
7739 memory mem_ptr,
7740 rax_RegN oldval, rRegN newval,
7741 rFlagsReg cr) %{
7742 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7743 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7744 effect(KILL cr, KILL oldval);
7745
7746 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7747 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7748 "sete $res\n\t"
7749 "movzbl $res, $res" %}
7750 opcode(0x0F, 0xB1);
7751 ins_encode(lock_prefix,
7752 REX_reg_mem(newval, mem_ptr),
7753 OpcP, OpcS,
7754 reg_mem(newval, mem_ptr),
7755 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7756 REX_reg_breg(res, res), // movzbl
7757 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7758 ins_pipe( pipe_cmpxchg );
7759 %}
7760
7761 instruct compareAndExchangeB(
7762 memory mem_ptr,
7763 rax_RegI oldval, rRegI newval,
7764 rFlagsReg cr)
7765 %{
7766 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7767 effect(KILL cr);
7768
7769 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7770 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7771 opcode(0x0F, 0xB0);
7772 ins_encode(lock_prefix,
7773 REX_breg_mem(newval, mem_ptr),
7774 OpcP, OpcS,
7775 reg_mem(newval, mem_ptr) // lock cmpxchg
7776 );
7777 ins_pipe( pipe_cmpxchg );
7778 %}
7779
7780 instruct compareAndExchangeS(
7781 memory mem_ptr,
7782 rax_RegI oldval, rRegI newval,
7783 rFlagsReg cr)
7784 %{
7785 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7786 effect(KILL cr);
7787
7788 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7789 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7790 opcode(0x0F, 0xB1);
7791 ins_encode(lock_prefix,
7792 SizePrefix,
7793 REX_reg_mem(newval, mem_ptr),
7794 OpcP, OpcS,
7795 reg_mem(newval, mem_ptr) // lock cmpxchg
7796 );
7797 ins_pipe( pipe_cmpxchg );
7798 %}
7799
7800 instruct compareAndExchangeI(
7801 memory mem_ptr,
7802 rax_RegI oldval, rRegI newval,
7803 rFlagsReg cr)
7804 %{
7805 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7806 effect(KILL cr);
7807
7808 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7809 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7810 opcode(0x0F, 0xB1);
7811 ins_encode(lock_prefix,
7812 REX_reg_mem(newval, mem_ptr),
7813 OpcP, OpcS,
7814 reg_mem(newval, mem_ptr) // lock cmpxchg
7815 );
7816 ins_pipe( pipe_cmpxchg );
7817 %}
7818
7819 instruct compareAndExchangeL(
7820 memory mem_ptr,
7821 rax_RegL oldval, rRegL newval,
7822 rFlagsReg cr)
7823 %{
7824 predicate(VM_Version::supports_cx8());
7825 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7826 effect(KILL cr);
7827
7828 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7829 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7830 opcode(0x0F, 0xB1);
7831 ins_encode(lock_prefix,
7832 REX_reg_mem_wide(newval, mem_ptr),
7833 OpcP, OpcS,
7834 reg_mem(newval, mem_ptr) // lock cmpxchg
7835 );
7836 ins_pipe( pipe_cmpxchg );
7837 %}
7838
7839 instruct compareAndExchangeN(
7840 memory mem_ptr,
7841 rax_RegN oldval, rRegN newval,
7842 rFlagsReg cr) %{
7843 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7844 effect(KILL cr);
7845
7846 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7847 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7848 opcode(0x0F, 0xB1);
7849 ins_encode(lock_prefix,
7850 REX_reg_mem(newval, mem_ptr),
7851 OpcP, OpcS,
7852 reg_mem(newval, mem_ptr) // lock cmpxchg
7853 );
7854 ins_pipe( pipe_cmpxchg );
7855 %}
7856
7857 instruct compareAndExchangeP(
7858 memory mem_ptr,
7859 rax_RegP oldval, rRegP newval,
7860 rFlagsReg cr)
7861 %{
7862 predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0);
7863 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7864 effect(KILL cr);
7865
7866 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7867 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7868 opcode(0x0F, 0xB1);
7869 ins_encode(lock_prefix,
7870 REX_reg_mem_wide(newval, mem_ptr),
7871 OpcP, OpcS,
7872 reg_mem(newval, mem_ptr) // lock cmpxchg
7873 );
7874 ins_pipe( pipe_cmpxchg );
7875 %}
7876
7877 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7878 predicate(n->as_LoadStore()->result_not_used());
7879 match(Set dummy (GetAndAddB mem add));
7880 effect(KILL cr);
7881 format %{ "ADDB [$mem],$add" %}
7882 ins_encode %{
7883 __ lock();
7884 __ addb($mem$$Address, $add$$constant);
7885 %}
7886 ins_pipe( pipe_cmpxchg );
7887 %}
7888
7889 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7890 match(Set newval (GetAndAddB mem newval));
7891 effect(KILL cr);
7892 format %{ "XADDB [$mem],$newval" %}
7893 ins_encode %{
7894 __ lock();
7895 __ xaddb($mem$$Address, $newval$$Register);
7896 %}
7897 ins_pipe( pipe_cmpxchg );
7898 %}
7899
7900 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7901 predicate(n->as_LoadStore()->result_not_used());
7902 match(Set dummy (GetAndAddS mem add));
7903 effect(KILL cr);
7904 format %{ "ADDW [$mem],$add" %}
7905 ins_encode %{
7906 __ lock();
7907 __ addw($mem$$Address, $add$$constant);
7908 %}
7909 ins_pipe( pipe_cmpxchg );
7910 %}
7911
7912 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
7913 match(Set newval (GetAndAddS mem newval));
7914 effect(KILL cr);
7915 format %{ "XADDW [$mem],$newval" %}
7916 ins_encode %{
7917 __ lock();
7918 __ xaddw($mem$$Address, $newval$$Register);
7919 %}
7920 ins_pipe( pipe_cmpxchg );
7921 %}
7922
7923 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7924 predicate(n->as_LoadStore()->result_not_used());
7925 match(Set dummy (GetAndAddI mem add));
7926 effect(KILL cr);
7927 format %{ "ADDL [$mem],$add" %}
7928 ins_encode %{
7929 __ lock();
7930 __ addl($mem$$Address, $add$$constant);
7931 %}
7932 ins_pipe( pipe_cmpxchg );
7933 %}
7934
7935 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7936 match(Set newval (GetAndAddI mem newval));
7937 effect(KILL cr);
7938 format %{ "XADDL [$mem],$newval" %}
7939 ins_encode %{
7940 __ lock();
7941 __ xaddl($mem$$Address, $newval$$Register);
7942 %}
7943 ins_pipe( pipe_cmpxchg );
7944 %}
7945
7946 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7947 predicate(n->as_LoadStore()->result_not_used());
7948 match(Set dummy (GetAndAddL mem add));
7949 effect(KILL cr);
7950 format %{ "ADDQ [$mem],$add" %}
7951 ins_encode %{
7952 __ lock();
7953 __ addq($mem$$Address, $add$$constant);
7954 %}
7955 ins_pipe( pipe_cmpxchg );
7956 %}
7957
7958 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7959 match(Set newval (GetAndAddL mem newval));
7960 effect(KILL cr);
7961 format %{ "XADDQ [$mem],$newval" %}
7962 ins_encode %{
7963 __ lock();
7964 __ xaddq($mem$$Address, $newval$$Register);
7965 %}
7966 ins_pipe( pipe_cmpxchg );
7967 %}
7968
7969 instruct xchgB( memory mem, rRegI newval) %{
7970 match(Set newval (GetAndSetB mem newval));
7971 format %{ "XCHGB $newval,[$mem]" %}
7972 ins_encode %{
7973 __ xchgb($newval$$Register, $mem$$Address);
7974 %}
7975 ins_pipe( pipe_cmpxchg );
7976 %}
7977
7978 instruct xchgS( memory mem, rRegI newval) %{
7979 match(Set newval (GetAndSetS mem newval));
7980 format %{ "XCHGW $newval,[$mem]" %}
7981 ins_encode %{
7982 __ xchgw($newval$$Register, $mem$$Address);
7983 %}
7984 ins_pipe( pipe_cmpxchg );
7985 %}
7986
7987 instruct xchgI( memory mem, rRegI newval) %{
7988 match(Set newval (GetAndSetI mem newval));
7989 format %{ "XCHGL $newval,[$mem]" %}
7990 ins_encode %{
7991 __ xchgl($newval$$Register, $mem$$Address);
7992 %}
7993 ins_pipe( pipe_cmpxchg );
7994 %}
7995
7996 instruct xchgL( memory mem, rRegL newval) %{
7997 match(Set newval (GetAndSetL mem newval));
7998 format %{ "XCHGL $newval,[$mem]" %}
7999 ins_encode %{
8000 __ xchgq($newval$$Register, $mem$$Address);
8001 %}
8002 ins_pipe( pipe_cmpxchg );
8003 %}
8004
8005 instruct xchgP( memory mem, rRegP newval) %{
8006 match(Set newval (GetAndSetP mem newval));
8007 predicate(n->as_LoadStore()->barrier_data() == 0);
8008 format %{ "XCHGQ $newval,[$mem]" %}
8009 ins_encode %{
8010 __ xchgq($newval$$Register, $mem$$Address);
8011 %}
8012 ins_pipe( pipe_cmpxchg );
8013 %}
8014
8015 instruct xchgN( memory mem, rRegN newval) %{
8016 match(Set newval (GetAndSetN mem newval));
8017 format %{ "XCHGL $newval,$mem]" %}
8018 ins_encode %{
8019 __ xchgl($newval$$Register, $mem$$Address);
8020 %}
8021 ins_pipe( pipe_cmpxchg );
8022 %}
8023
8024 //----------Abs Instructions-------------------------------------------
8025
8026 // Integer Absolute Instructions
8027 instruct absI_rReg(rRegI dst, rRegI src, rRegI tmp, rFlagsReg cr)
8028 %{
8029 match(Set dst (AbsI src));
8030 effect(TEMP dst, TEMP tmp, KILL cr);
8031 format %{ "movl $tmp, $src\n\t"
8032 "sarl $tmp, 31\n\t"
8033 "movl $dst, $src\n\t"
8034 "xorl $dst, $tmp\n\t"
8035 "subl $dst, $tmp\n"
8036 %}
8037 ins_encode %{
8038 __ movl($tmp$$Register, $src$$Register);
8039 __ sarl($tmp$$Register, 31);
8040 __ movl($dst$$Register, $src$$Register);
8041 __ xorl($dst$$Register, $tmp$$Register);
8042 __ subl($dst$$Register, $tmp$$Register);
8043 %}
8044
8045 ins_pipe(ialu_reg_reg);
8046 %}
8047
8048 // Long Absolute Instructions
8049 instruct absL_rReg(rRegL dst, rRegL src, rRegL tmp, rFlagsReg cr)
8050 %{
8051 match(Set dst (AbsL src));
8052 effect(TEMP dst, TEMP tmp, KILL cr);
8053 format %{ "movq $tmp, $src\n\t"
8054 "sarq $tmp, 63\n\t"
8055 "movq $dst, $src\n\t"
8056 "xorq $dst, $tmp\n\t"
8057 "subq $dst, $tmp\n"
8058 %}
8059 ins_encode %{
8060 __ movq($tmp$$Register, $src$$Register);
8061 __ sarq($tmp$$Register, 63);
8062 __ movq($dst$$Register, $src$$Register);
8063 __ xorq($dst$$Register, $tmp$$Register);
8064 __ subq($dst$$Register, $tmp$$Register);
8065 %}
8066
8067 ins_pipe(ialu_reg_reg);
8068 %}
8069
8070 //----------Subtraction Instructions-------------------------------------------
8071
8072 // Integer Subtraction Instructions
8073 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8074 %{
8075 match(Set dst (SubI dst src));
8076 effect(KILL cr);
8077
8078 format %{ "subl $dst, $src\t# int" %}
8079 opcode(0x2B);
8080 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8081 ins_pipe(ialu_reg_reg);
8082 %}
8083
8084 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8085 %{
8086 match(Set dst (SubI dst src));
8087 effect(KILL cr);
8088
8089 format %{ "subl $dst, $src\t# int" %}
8090 opcode(0x81, 0x05); /* Opcode 81 /5 */
8091 ins_encode(OpcSErm(dst, src), Con8or32(src));
8092 ins_pipe(ialu_reg);
8093 %}
8094
8095 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8096 %{
8097 match(Set dst (SubI dst (LoadI src)));
8098 effect(KILL cr);
8099
8100 ins_cost(125);
8101 format %{ "subl $dst, $src\t# int" %}
8102 opcode(0x2B);
8103 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8104 ins_pipe(ialu_reg_mem);
8105 %}
8106
8107 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8108 %{
8109 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8110 effect(KILL cr);
8111
8112 ins_cost(150);
8113 format %{ "subl $dst, $src\t# int" %}
8114 opcode(0x29); /* Opcode 29 /r */
8115 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8116 ins_pipe(ialu_mem_reg);
8117 %}
8118
8119 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8120 %{
8121 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8122 effect(KILL cr);
8123
8124 ins_cost(125); // XXX
8125 format %{ "subl $dst, $src\t# int" %}
8126 opcode(0x81); /* Opcode 81 /5 id */
8127 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8128 ins_pipe(ialu_mem_imm);
8129 %}
8130
8131 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8132 %{
8133 match(Set dst (SubL dst src));
8134 effect(KILL cr);
8135
8136 format %{ "subq $dst, $src\t# long" %}
8137 opcode(0x2B);
8138 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8139 ins_pipe(ialu_reg_reg);
8140 %}
8141
8142 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8143 %{
8144 match(Set dst (SubL dst src));
8145 effect(KILL cr);
8146
8147 format %{ "subq $dst, $src\t# long" %}
8148 opcode(0x81, 0x05); /* Opcode 81 /5 */
8149 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8150 ins_pipe(ialu_reg);
8151 %}
8152
8153 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8154 %{
8155 match(Set dst (SubL dst (LoadL src)));
8156 effect(KILL cr);
8157
8158 ins_cost(125);
8159 format %{ "subq $dst, $src\t# long" %}
8160 opcode(0x2B);
8161 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8162 ins_pipe(ialu_reg_mem);
8163 %}
8164
8165 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8166 %{
8167 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8168 effect(KILL cr);
8169
8170 ins_cost(150);
8171 format %{ "subq $dst, $src\t# long" %}
8172 opcode(0x29); /* Opcode 29 /r */
8173 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8174 ins_pipe(ialu_mem_reg);
8175 %}
8176
8177 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8178 %{
8179 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8180 effect(KILL cr);
8181
8182 ins_cost(125); // XXX
8183 format %{ "subq $dst, $src\t# long" %}
8184 opcode(0x81); /* Opcode 81 /5 id */
8185 ins_encode(REX_mem_wide(dst),
8186 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8187 ins_pipe(ialu_mem_imm);
8188 %}
8189
8190 // Subtract from a pointer
8191 // XXX hmpf???
8192 instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
8193 %{
8194 match(Set dst (AddP dst (SubI zero src)));
8195 effect(KILL cr);
8196
8197 format %{ "subq $dst, $src\t# ptr - int" %}
8198 opcode(0x2B);
8199 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8200 ins_pipe(ialu_reg_reg);
8201 %}
8202
8203 instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr)
8204 %{
8205 match(Set dst (SubI zero dst));
8206 effect(KILL cr);
8207
8208 format %{ "negl $dst\t# int" %}
8209 opcode(0xF7, 0x03); // Opcode F7 /3
8210 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8211 ins_pipe(ialu_reg);
8212 %}
8213
8214 instruct negI_rReg_2(rRegI dst, rFlagsReg cr)
8215 %{
8216 match(Set dst (NegI dst));
8217 effect(KILL cr);
8218
8219 format %{ "negl $dst\t# int" %}
8220 ins_encode %{
8221 __ negl($dst$$Register);
8222 %}
8223 ins_pipe(ialu_reg);
8224 %}
8225
8226 instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr)
8227 %{
8228 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8229 effect(KILL cr);
8230
8231 format %{ "negl $dst\t# int" %}
8232 opcode(0xF7, 0x03); // Opcode F7 /3
8233 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8234 ins_pipe(ialu_reg);
8235 %}
8236
8237 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8238 %{
8239 match(Set dst (SubL zero dst));
8240 effect(KILL cr);
8241
8242 format %{ "negq $dst\t# long" %}
8243 opcode(0xF7, 0x03); // Opcode F7 /3
8244 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8245 ins_pipe(ialu_reg);
8246 %}
8247
8248 instruct negL_rReg_2(rRegL dst, rFlagsReg cr)
8249 %{
8250 match(Set dst (NegL dst));
8251 effect(KILL cr);
8252
8253 format %{ "negq $dst\t# int" %}
8254 ins_encode %{
8255 __ negq($dst$$Register);
8256 %}
8257 ins_pipe(ialu_reg);
8258 %}
8259
8260 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8261 %{
8262 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8263 effect(KILL cr);
8264
8265 format %{ "negq $dst\t# long" %}
8266 opcode(0xF7, 0x03); // Opcode F7 /3
8267 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8268 ins_pipe(ialu_reg);
8269 %}
8270
8271 //----------Multiplication/Division Instructions-------------------------------
8272 // Integer Multiplication Instructions
8273 // Multiply Register
8274
8275 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8276 %{
8277 match(Set dst (MulI dst src));
8278 effect(KILL cr);
8279
8280 ins_cost(300);
8281 format %{ "imull $dst, $src\t# int" %}
8282 opcode(0x0F, 0xAF);
8283 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8284 ins_pipe(ialu_reg_reg_alu0);
8285 %}
8286
8287 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8288 %{
8289 match(Set dst (MulI src imm));
8290 effect(KILL cr);
8291
8292 ins_cost(300);
8293 format %{ "imull $dst, $src, $imm\t# int" %}
8294 opcode(0x69); /* 69 /r id */
8295 ins_encode(REX_reg_reg(dst, src),
8296 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8297 ins_pipe(ialu_reg_reg_alu0);
8298 %}
8299
8300 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8301 %{
8302 match(Set dst (MulI dst (LoadI src)));
8303 effect(KILL cr);
8304
8305 ins_cost(350);
8306 format %{ "imull $dst, $src\t# int" %}
8307 opcode(0x0F, 0xAF);
8308 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8309 ins_pipe(ialu_reg_mem_alu0);
8310 %}
8311
8312 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8313 %{
8314 match(Set dst (MulI (LoadI src) imm));
8315 effect(KILL cr);
8316
8317 ins_cost(300);
8318 format %{ "imull $dst, $src, $imm\t# int" %}
8319 opcode(0x69); /* 69 /r id */
8320 ins_encode(REX_reg_mem(dst, src),
8321 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8322 ins_pipe(ialu_reg_mem_alu0);
8323 %}
8324
8325 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
8326 %{
8327 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
8328 effect(KILL cr, KILL src2);
8329
8330 expand %{ mulI_rReg(dst, src1, cr);
8331 mulI_rReg(src2, src3, cr);
8332 addI_rReg(dst, src2, cr); %}
8333 %}
8334
8335 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8336 %{
8337 match(Set dst (MulL dst src));
8338 effect(KILL cr);
8339
8340 ins_cost(300);
8341 format %{ "imulq $dst, $src\t# long" %}
8342 opcode(0x0F, 0xAF);
8343 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8344 ins_pipe(ialu_reg_reg_alu0);
8345 %}
8346
8347 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8348 %{
8349 match(Set dst (MulL src imm));
8350 effect(KILL cr);
8351
8352 ins_cost(300);
8353 format %{ "imulq $dst, $src, $imm\t# long" %}
8354 opcode(0x69); /* 69 /r id */
8355 ins_encode(REX_reg_reg_wide(dst, src),
8356 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8357 ins_pipe(ialu_reg_reg_alu0);
8358 %}
8359
8360 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8361 %{
8362 match(Set dst (MulL dst (LoadL src)));
8363 effect(KILL cr);
8364
8365 ins_cost(350);
8366 format %{ "imulq $dst, $src\t# long" %}
8367 opcode(0x0F, 0xAF);
8368 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8369 ins_pipe(ialu_reg_mem_alu0);
8370 %}
8371
8372 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8373 %{
8374 match(Set dst (MulL (LoadL src) imm));
8375 effect(KILL cr);
8376
8377 ins_cost(300);
8378 format %{ "imulq $dst, $src, $imm\t# long" %}
8379 opcode(0x69); /* 69 /r id */
8380 ins_encode(REX_reg_mem_wide(dst, src),
8381 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8382 ins_pipe(ialu_reg_mem_alu0);
8383 %}
8384
8385 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8386 %{
8387 match(Set dst (MulHiL src rax));
8388 effect(USE_KILL rax, KILL cr);
8389
8390 ins_cost(300);
8391 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8392 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8393 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8394 ins_pipe(ialu_reg_reg_alu0);
8395 %}
8396
8397 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8398 rFlagsReg cr)
8399 %{
8400 match(Set rax (DivI rax div));
8401 effect(KILL rdx, KILL cr);
8402
8403 ins_cost(30*100+10*100); // XXX
8404 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8405 "jne,s normal\n\t"
8406 "xorl rdx, rdx\n\t"
8407 "cmpl $div, -1\n\t"
8408 "je,s done\n"
8409 "normal: cdql\n\t"
8410 "idivl $div\n"
8411 "done:" %}
8412 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8413 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8414 ins_pipe(ialu_reg_reg_alu0);
8415 %}
8416
8417 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8418 rFlagsReg cr)
8419 %{
8420 match(Set rax (DivL rax div));
8421 effect(KILL rdx, KILL cr);
8422
8423 ins_cost(30*100+10*100); // XXX
8424 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8425 "cmpq rax, rdx\n\t"
8426 "jne,s normal\n\t"
8427 "xorl rdx, rdx\n\t"
8428 "cmpq $div, -1\n\t"
8429 "je,s done\n"
8430 "normal: cdqq\n\t"
8431 "idivq $div\n"
8432 "done:" %}
8433 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8434 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8435 ins_pipe(ialu_reg_reg_alu0);
8436 %}
8437
8438 // Integer DIVMOD with Register, both quotient and mod results
8439 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8440 rFlagsReg cr)
8441 %{
8442 match(DivModI rax div);
8443 effect(KILL cr);
8444
8445 ins_cost(30*100+10*100); // XXX
8446 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8447 "jne,s normal\n\t"
8448 "xorl rdx, rdx\n\t"
8449 "cmpl $div, -1\n\t"
8450 "je,s done\n"
8451 "normal: cdql\n\t"
8452 "idivl $div\n"
8453 "done:" %}
8454 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8455 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8456 ins_pipe(pipe_slow);
8457 %}
8458
8459 // Long DIVMOD with Register, both quotient and mod results
8460 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8461 rFlagsReg cr)
8462 %{
8463 match(DivModL rax div);
8464 effect(KILL cr);
8465
8466 ins_cost(30*100+10*100); // XXX
8467 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8468 "cmpq rax, rdx\n\t"
8469 "jne,s normal\n\t"
8470 "xorl rdx, rdx\n\t"
8471 "cmpq $div, -1\n\t"
8472 "je,s done\n"
8473 "normal: cdqq\n\t"
8474 "idivq $div\n"
8475 "done:" %}
8476 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8477 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8478 ins_pipe(pipe_slow);
8479 %}
8480
8481 //----------- DivL-By-Constant-Expansions--------------------------------------
8482 // DivI cases are handled by the compiler
8483
8484 // Magic constant, reciprocal of 10
8485 instruct loadConL_0x6666666666666667(rRegL dst)
8486 %{
8487 effect(DEF dst);
8488
8489 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8490 ins_encode(load_immL(dst, 0x6666666666666667));
8491 ins_pipe(ialu_reg);
8492 %}
8493
8494 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8495 %{
8496 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8497
8498 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8499 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8500 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8501 ins_pipe(ialu_reg_reg_alu0);
8502 %}
8503
8504 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8505 %{
8506 effect(USE_DEF dst, KILL cr);
8507
8508 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8509 opcode(0xC1, 0x7); /* C1 /7 ib */
8510 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8511 ins_pipe(ialu_reg);
8512 %}
8513
8514 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8515 %{
8516 effect(USE_DEF dst, KILL cr);
8517
8518 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8519 opcode(0xC1, 0x7); /* C1 /7 ib */
8520 ins_encode(reg_opc_imm_wide(dst, 0x2));
8521 ins_pipe(ialu_reg);
8522 %}
8523
8524 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8525 %{
8526 match(Set dst (DivL src div));
8527
8528 ins_cost((5+8)*100);
8529 expand %{
8530 rax_RegL rax; // Killed temp
8531 rFlagsReg cr; // Killed
8532 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8533 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8534 sarL_rReg_63(src, cr); // sarq src, 63
8535 sarL_rReg_2(dst, cr); // sarq rdx, 2
8536 subL_rReg(dst, src, cr); // subl rdx, src
8537 %}
8538 %}
8539
8540 //-----------------------------------------------------------------------------
8541
8542 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8543 rFlagsReg cr)
8544 %{
8545 match(Set rdx (ModI rax div));
8546 effect(KILL rax, KILL cr);
8547
8548 ins_cost(300); // XXX
8549 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8550 "jne,s normal\n\t"
8551 "xorl rdx, rdx\n\t"
8552 "cmpl $div, -1\n\t"
8553 "je,s done\n"
8554 "normal: cdql\n\t"
8555 "idivl $div\n"
8556 "done:" %}
8557 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8558 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8559 ins_pipe(ialu_reg_reg_alu0);
8560 %}
8561
8562 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8563 rFlagsReg cr)
8564 %{
8565 match(Set rdx (ModL rax div));
8566 effect(KILL rax, KILL cr);
8567
8568 ins_cost(300); // XXX
8569 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8570 "cmpq rax, rdx\n\t"
8571 "jne,s normal\n\t"
8572 "xorl rdx, rdx\n\t"
8573 "cmpq $div, -1\n\t"
8574 "je,s done\n"
8575 "normal: cdqq\n\t"
8576 "idivq $div\n"
8577 "done:" %}
8578 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8579 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8580 ins_pipe(ialu_reg_reg_alu0);
8581 %}
8582
8583 // Integer Shift Instructions
8584 // Shift Left by one
8585 instruct salI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8586 %{
8587 match(Set dst (LShiftI dst shift));
8588 effect(KILL cr);
8589
8590 format %{ "sall $dst, $shift" %}
8591 opcode(0xD1, 0x4); /* D1 /4 */
8592 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8593 ins_pipe(ialu_reg);
8594 %}
8595
8596 // Shift Left by one
8597 instruct salI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8598 %{
8599 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8600 effect(KILL cr);
8601
8602 format %{ "sall $dst, $shift\t" %}
8603 opcode(0xD1, 0x4); /* D1 /4 */
8604 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8605 ins_pipe(ialu_mem_imm);
8606 %}
8607
8608 // Shift Left by 8-bit immediate
8609 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8610 %{
8611 match(Set dst (LShiftI dst shift));
8612 effect(KILL cr);
8613
8614 format %{ "sall $dst, $shift" %}
8615 opcode(0xC1, 0x4); /* C1 /4 ib */
8616 ins_encode(reg_opc_imm(dst, shift));
8617 ins_pipe(ialu_reg);
8618 %}
8619
8620 // Shift Left by 8-bit immediate
8621 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8622 %{
8623 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8624 effect(KILL cr);
8625
8626 format %{ "sall $dst, $shift" %}
8627 opcode(0xC1, 0x4); /* C1 /4 ib */
8628 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8629 ins_pipe(ialu_mem_imm);
8630 %}
8631
8632 // Shift Left by variable
8633 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8634 %{
8635 match(Set dst (LShiftI dst shift));
8636 effect(KILL cr);
8637
8638 format %{ "sall $dst, $shift" %}
8639 opcode(0xD3, 0x4); /* D3 /4 */
8640 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8641 ins_pipe(ialu_reg_reg);
8642 %}
8643
8644 // Shift Left by variable
8645 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8646 %{
8647 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8648 effect(KILL cr);
8649
8650 format %{ "sall $dst, $shift" %}
8651 opcode(0xD3, 0x4); /* D3 /4 */
8652 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8653 ins_pipe(ialu_mem_reg);
8654 %}
8655
8656 // Arithmetic shift right by one
8657 instruct sarI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8658 %{
8659 match(Set dst (RShiftI dst shift));
8660 effect(KILL cr);
8661
8662 format %{ "sarl $dst, $shift" %}
8663 opcode(0xD1, 0x7); /* D1 /7 */
8664 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8665 ins_pipe(ialu_reg);
8666 %}
8667
8668 // Arithmetic shift right by one
8669 instruct sarI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8670 %{
8671 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8672 effect(KILL cr);
8673
8674 format %{ "sarl $dst, $shift" %}
8675 opcode(0xD1, 0x7); /* D1 /7 */
8676 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8677 ins_pipe(ialu_mem_imm);
8678 %}
8679
8680 // Arithmetic Shift Right by 8-bit immediate
8681 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8682 %{
8683 match(Set dst (RShiftI dst shift));
8684 effect(KILL cr);
8685
8686 format %{ "sarl $dst, $shift" %}
8687 opcode(0xC1, 0x7); /* C1 /7 ib */
8688 ins_encode(reg_opc_imm(dst, shift));
8689 ins_pipe(ialu_mem_imm);
8690 %}
8691
8692 // Arithmetic Shift Right by 8-bit immediate
8693 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8694 %{
8695 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8696 effect(KILL cr);
8697
8698 format %{ "sarl $dst, $shift" %}
8699 opcode(0xC1, 0x7); /* C1 /7 ib */
8700 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8701 ins_pipe(ialu_mem_imm);
8702 %}
8703
8704 // Arithmetic Shift Right by variable
8705 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8706 %{
8707 match(Set dst (RShiftI dst shift));
8708 effect(KILL cr);
8709
8710 format %{ "sarl $dst, $shift" %}
8711 opcode(0xD3, 0x7); /* D3 /7 */
8712 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8713 ins_pipe(ialu_reg_reg);
8714 %}
8715
8716 // Arithmetic Shift Right by variable
8717 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8718 %{
8719 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8720 effect(KILL cr);
8721
8722 format %{ "sarl $dst, $shift" %}
8723 opcode(0xD3, 0x7); /* D3 /7 */
8724 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8725 ins_pipe(ialu_mem_reg);
8726 %}
8727
8728 // Logical shift right by one
8729 instruct shrI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8730 %{
8731 match(Set dst (URShiftI dst shift));
8732 effect(KILL cr);
8733
8734 format %{ "shrl $dst, $shift" %}
8735 opcode(0xD1, 0x5); /* D1 /5 */
8736 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8737 ins_pipe(ialu_reg);
8738 %}
8739
8740 // Logical shift right by one
8741 instruct shrI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8742 %{
8743 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8744 effect(KILL cr);
8745
8746 format %{ "shrl $dst, $shift" %}
8747 opcode(0xD1, 0x5); /* D1 /5 */
8748 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8749 ins_pipe(ialu_mem_imm);
8750 %}
8751
8752 // Logical Shift Right by 8-bit immediate
8753 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8754 %{
8755 match(Set dst (URShiftI dst shift));
8756 effect(KILL cr);
8757
8758 format %{ "shrl $dst, $shift" %}
8759 opcode(0xC1, 0x5); /* C1 /5 ib */
8760 ins_encode(reg_opc_imm(dst, shift));
8761 ins_pipe(ialu_reg);
8762 %}
8763
8764 // Logical Shift Right by 8-bit immediate
8765 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8766 %{
8767 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8768 effect(KILL cr);
8769
8770 format %{ "shrl $dst, $shift" %}
8771 opcode(0xC1, 0x5); /* C1 /5 ib */
8772 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8773 ins_pipe(ialu_mem_imm);
8774 %}
8775
8776 // Logical Shift Right by variable
8777 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8778 %{
8779 match(Set dst (URShiftI dst shift));
8780 effect(KILL cr);
8781
8782 format %{ "shrl $dst, $shift" %}
8783 opcode(0xD3, 0x5); /* D3 /5 */
8784 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8785 ins_pipe(ialu_reg_reg);
8786 %}
8787
8788 // Logical Shift Right by variable
8789 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8790 %{
8791 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8792 effect(KILL cr);
8793
8794 format %{ "shrl $dst, $shift" %}
8795 opcode(0xD3, 0x5); /* D3 /5 */
8796 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8797 ins_pipe(ialu_mem_reg);
8798 %}
8799
8800 // Long Shift Instructions
8801 // Shift Left by one
8802 instruct salL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
8803 %{
8804 match(Set dst (LShiftL dst shift));
8805 effect(KILL cr);
8806
8807 format %{ "salq $dst, $shift" %}
8808 opcode(0xD1, 0x4); /* D1 /4 */
8809 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8810 ins_pipe(ialu_reg);
8811 %}
8812
8813 // Shift Left by one
8814 instruct salL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8815 %{
8816 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8817 effect(KILL cr);
8818
8819 format %{ "salq $dst, $shift" %}
8820 opcode(0xD1, 0x4); /* D1 /4 */
8821 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8822 ins_pipe(ialu_mem_imm);
8823 %}
8824
8825 // Shift Left by 8-bit immediate
8826 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8827 %{
8828 match(Set dst (LShiftL dst shift));
8829 effect(KILL cr);
8830
8831 format %{ "salq $dst, $shift" %}
8832 opcode(0xC1, 0x4); /* C1 /4 ib */
8833 ins_encode(reg_opc_imm_wide(dst, shift));
8834 ins_pipe(ialu_reg);
8835 %}
8836
8837 // Shift Left by 8-bit immediate
8838 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8839 %{
8840 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8841 effect(KILL cr);
8842
8843 format %{ "salq $dst, $shift" %}
8844 opcode(0xC1, 0x4); /* C1 /4 ib */
8845 ins_encode(REX_mem_wide(dst), OpcP,
8846 RM_opc_mem(secondary, dst), Con8or32(shift));
8847 ins_pipe(ialu_mem_imm);
8848 %}
8849
8850 // Shift Left by variable
8851 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8852 %{
8853 match(Set dst (LShiftL dst shift));
8854 effect(KILL cr);
8855
8856 format %{ "salq $dst, $shift" %}
8857 opcode(0xD3, 0x4); /* D3 /4 */
8858 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8859 ins_pipe(ialu_reg_reg);
8860 %}
8861
8862 // Shift Left by variable
8863 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8864 %{
8865 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8866 effect(KILL cr);
8867
8868 format %{ "salq $dst, $shift" %}
8869 opcode(0xD3, 0x4); /* D3 /4 */
8870 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8871 ins_pipe(ialu_mem_reg);
8872 %}
8873
8874 // Arithmetic shift right by one
8875 instruct sarL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
8876 %{
8877 match(Set dst (RShiftL dst shift));
8878 effect(KILL cr);
8879
8880 format %{ "sarq $dst, $shift" %}
8881 opcode(0xD1, 0x7); /* D1 /7 */
8882 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8883 ins_pipe(ialu_reg);
8884 %}
8885
8886 // Arithmetic shift right by one
8887 instruct sarL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8888 %{
8889 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8890 effect(KILL cr);
8891
8892 format %{ "sarq $dst, $shift" %}
8893 opcode(0xD1, 0x7); /* D1 /7 */
8894 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8895 ins_pipe(ialu_mem_imm);
8896 %}
8897
8898 // Arithmetic Shift Right by 8-bit immediate
8899 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8900 %{
8901 match(Set dst (RShiftL dst shift));
8902 effect(KILL cr);
8903
8904 format %{ "sarq $dst, $shift" %}
8905 opcode(0xC1, 0x7); /* C1 /7 ib */
8906 ins_encode(reg_opc_imm_wide(dst, shift));
8907 ins_pipe(ialu_mem_imm);
8908 %}
8909
8910 // Arithmetic Shift Right by 8-bit immediate
8911 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8912 %{
8913 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8914 effect(KILL cr);
8915
8916 format %{ "sarq $dst, $shift" %}
8917 opcode(0xC1, 0x7); /* C1 /7 ib */
8918 ins_encode(REX_mem_wide(dst), OpcP,
8919 RM_opc_mem(secondary, dst), Con8or32(shift));
8920 ins_pipe(ialu_mem_imm);
8921 %}
8922
8923 // Arithmetic Shift Right by variable
8924 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8925 %{
8926 match(Set dst (RShiftL dst shift));
8927 effect(KILL cr);
8928
8929 format %{ "sarq $dst, $shift" %}
8930 opcode(0xD3, 0x7); /* D3 /7 */
8931 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8932 ins_pipe(ialu_reg_reg);
8933 %}
8934
8935 // Arithmetic Shift Right by variable
8936 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8937 %{
8938 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8939 effect(KILL cr);
8940
8941 format %{ "sarq $dst, $shift" %}
8942 opcode(0xD3, 0x7); /* D3 /7 */
8943 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8944 ins_pipe(ialu_mem_reg);
8945 %}
8946
8947 // Logical shift right by one
8948 instruct shrL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
8949 %{
8950 match(Set dst (URShiftL dst shift));
8951 effect(KILL cr);
8952
8953 format %{ "shrq $dst, $shift" %}
8954 opcode(0xD1, 0x5); /* D1 /5 */
8955 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8956 ins_pipe(ialu_reg);
8957 %}
8958
8959 // Logical shift right by one
8960 instruct shrL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8961 %{
8962 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8963 effect(KILL cr);
8964
8965 format %{ "shrq $dst, $shift" %}
8966 opcode(0xD1, 0x5); /* D1 /5 */
8967 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8968 ins_pipe(ialu_mem_imm);
8969 %}
8970
8971 // Logical Shift Right by 8-bit immediate
8972 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8973 %{
8974 match(Set dst (URShiftL dst shift));
8975 effect(KILL cr);
8976
8977 format %{ "shrq $dst, $shift" %}
8978 opcode(0xC1, 0x5); /* C1 /5 ib */
8979 ins_encode(reg_opc_imm_wide(dst, shift));
8980 ins_pipe(ialu_reg);
8981 %}
8982
8983
8984 // Logical Shift Right by 8-bit immediate
8985 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8986 %{
8987 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8988 effect(KILL cr);
8989
8990 format %{ "shrq $dst, $shift" %}
8991 opcode(0xC1, 0x5); /* C1 /5 ib */
8992 ins_encode(REX_mem_wide(dst), OpcP,
8993 RM_opc_mem(secondary, dst), Con8or32(shift));
8994 ins_pipe(ialu_mem_imm);
8995 %}
8996
8997 // Logical Shift Right by variable
8998 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8999 %{
9000 match(Set dst (URShiftL dst shift));
9001 effect(KILL cr);
9002
9003 format %{ "shrq $dst, $shift" %}
9004 opcode(0xD3, 0x5); /* D3 /5 */
9005 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9006 ins_pipe(ialu_reg_reg);
9007 %}
9008
9009 // Logical Shift Right by variable
9010 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9011 %{
9012 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9013 effect(KILL cr);
9014
9015 format %{ "shrq $dst, $shift" %}
9016 opcode(0xD3, 0x5); /* D3 /5 */
9017 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9018 ins_pipe(ialu_mem_reg);
9019 %}
9020
9021 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9022 // This idiom is used by the compiler for the i2b bytecode.
9023 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9024 %{
9025 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9026
9027 format %{ "movsbl $dst, $src\t# i2b" %}
9028 opcode(0x0F, 0xBE);
9029 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9030 ins_pipe(ialu_reg_reg);
9031 %}
9032
9033 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9034 // This idiom is used by the compiler the i2s bytecode.
9035 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9036 %{
9037 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9038
9039 format %{ "movswl $dst, $src\t# i2s" %}
9040 opcode(0x0F, 0xBF);
9041 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9042 ins_pipe(ialu_reg_reg);
9043 %}
9044
9045 // ROL/ROR instructions
9046
9047 // ROL expand
9048 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
9049 effect(KILL cr, USE_DEF dst);
9050
9051 format %{ "roll $dst" %}
9052 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9053 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9054 ins_pipe(ialu_reg);
9055 %}
9056
9057 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
9058 effect(USE_DEF dst, USE shift, KILL cr);
9059
9060 format %{ "roll $dst, $shift" %}
9061 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9062 ins_encode( reg_opc_imm(dst, shift) );
9063 ins_pipe(ialu_reg);
9064 %}
9065
9066 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9067 %{
9068 effect(USE_DEF dst, USE shift, KILL cr);
9069
9070 format %{ "roll $dst, $shift" %}
9071 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9072 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9073 ins_pipe(ialu_reg_reg);
9074 %}
9075 // end of ROL expand
9076
9077 // Rotate Left by one
9078 instruct rolI_rReg_i1(rRegI dst, immI_1 lshift, immI_M1 rshift, rFlagsReg cr)
9079 %{
9080 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9081
9082 expand %{
9083 rolI_rReg_imm1(dst, cr);
9084 %}
9085 %}
9086
9087 // Rotate Left by 8-bit immediate
9088 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9089 %{
9090 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9091 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9092
9093 expand %{
9094 rolI_rReg_imm8(dst, lshift, cr);
9095 %}
9096 %}
9097
9098 // Rotate Left by variable
9099 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
9100 %{
9101 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9102
9103 expand %{
9104 rolI_rReg_CL(dst, shift, cr);
9105 %}
9106 %}
9107
9108 // Rotate Left by variable
9109 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9110 %{
9111 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9112
9113 expand %{
9114 rolI_rReg_CL(dst, shift, cr);
9115 %}
9116 %}
9117
9118 // ROR expand
9119 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9120 %{
9121 effect(USE_DEF dst, KILL cr);
9122
9123 format %{ "rorl $dst" %}
9124 opcode(0xD1, 0x1); /* D1 /1 */
9125 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9126 ins_pipe(ialu_reg);
9127 %}
9128
9129 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
9130 %{
9131 effect(USE_DEF dst, USE shift, KILL cr);
9132
9133 format %{ "rorl $dst, $shift" %}
9134 opcode(0xC1, 0x1); /* C1 /1 ib */
9135 ins_encode(reg_opc_imm(dst, shift));
9136 ins_pipe(ialu_reg);
9137 %}
9138
9139 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9140 %{
9141 effect(USE_DEF dst, USE shift, KILL cr);
9142
9143 format %{ "rorl $dst, $shift" %}
9144 opcode(0xD3, 0x1); /* D3 /1 */
9145 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9146 ins_pipe(ialu_reg_reg);
9147 %}
9148 // end of ROR expand
9149
9150 // Rotate Right by one
9151 instruct rorI_rReg_i1(rRegI dst, immI_1 rshift, immI_M1 lshift, rFlagsReg cr)
9152 %{
9153 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9154
9155 expand %{
9156 rorI_rReg_imm1(dst, cr);
9157 %}
9158 %}
9159
9160 // Rotate Right by 8-bit immediate
9161 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9162 %{
9163 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9164 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9165
9166 expand %{
9167 rorI_rReg_imm8(dst, rshift, cr);
9168 %}
9169 %}
9170
9171 // Rotate Right by variable
9172 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
9173 %{
9174 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9175
9176 expand %{
9177 rorI_rReg_CL(dst, shift, cr);
9178 %}
9179 %}
9180
9181 // Rotate Right by variable
9182 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9183 %{
9184 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9185
9186 expand %{
9187 rorI_rReg_CL(dst, shift, cr);
9188 %}
9189 %}
9190
9191 // for long rotate
9192 // ROL expand
9193 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9194 effect(USE_DEF dst, KILL cr);
9195
9196 format %{ "rolq $dst" %}
9197 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9198 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9199 ins_pipe(ialu_reg);
9200 %}
9201
9202 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9203 effect(USE_DEF dst, USE shift, KILL cr);
9204
9205 format %{ "rolq $dst, $shift" %}
9206 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9207 ins_encode( reg_opc_imm_wide(dst, shift) );
9208 ins_pipe(ialu_reg);
9209 %}
9210
9211 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9212 %{
9213 effect(USE_DEF dst, USE shift, KILL cr);
9214
9215 format %{ "rolq $dst, $shift" %}
9216 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9217 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9218 ins_pipe(ialu_reg_reg);
9219 %}
9220 // end of ROL expand
9221
9222 // Rotate Left by one
9223 instruct rolL_rReg_i1(rRegL dst, immI_1 lshift, immI_M1 rshift, rFlagsReg cr)
9224 %{
9225 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9226
9227 expand %{
9228 rolL_rReg_imm1(dst, cr);
9229 %}
9230 %}
9231
9232 // Rotate Left by 8-bit immediate
9233 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9234 %{
9235 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9236 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9237
9238 expand %{
9239 rolL_rReg_imm8(dst, lshift, cr);
9240 %}
9241 %}
9242
9243 // Rotate Left by variable
9244 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
9245 %{
9246 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9247
9248 expand %{
9249 rolL_rReg_CL(dst, shift, cr);
9250 %}
9251 %}
9252
9253 // Rotate Left by variable
9254 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9255 %{
9256 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9257
9258 expand %{
9259 rolL_rReg_CL(dst, shift, cr);
9260 %}
9261 %}
9262
9263 // ROR expand
9264 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9265 %{
9266 effect(USE_DEF dst, KILL cr);
9267
9268 format %{ "rorq $dst" %}
9269 opcode(0xD1, 0x1); /* D1 /1 */
9270 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9271 ins_pipe(ialu_reg);
9272 %}
9273
9274 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9275 %{
9276 effect(USE_DEF dst, USE shift, KILL cr);
9277
9278 format %{ "rorq $dst, $shift" %}
9279 opcode(0xC1, 0x1); /* C1 /1 ib */
9280 ins_encode(reg_opc_imm_wide(dst, shift));
9281 ins_pipe(ialu_reg);
9282 %}
9283
9284 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9285 %{
9286 effect(USE_DEF dst, USE shift, KILL cr);
9287
9288 format %{ "rorq $dst, $shift" %}
9289 opcode(0xD3, 0x1); /* D3 /1 */
9290 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9291 ins_pipe(ialu_reg_reg);
9292 %}
9293 // end of ROR expand
9294
9295 // Rotate Right by one
9296 instruct rorL_rReg_i1(rRegL dst, immI_1 rshift, immI_M1 lshift, rFlagsReg cr)
9297 %{
9298 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9299
9300 expand %{
9301 rorL_rReg_imm1(dst, cr);
9302 %}
9303 %}
9304
9305 // Rotate Right by 8-bit immediate
9306 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9307 %{
9308 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9309 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9310
9311 expand %{
9312 rorL_rReg_imm8(dst, rshift, cr);
9313 %}
9314 %}
9315
9316 // Rotate Right by variable
9317 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
9318 %{
9319 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9320
9321 expand %{
9322 rorL_rReg_CL(dst, shift, cr);
9323 %}
9324 %}
9325
9326 // Rotate Right by variable
9327 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9328 %{
9329 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9330
9331 expand %{
9332 rorL_rReg_CL(dst, shift, cr);
9333 %}
9334 %}
9335
9336 // Logical Instructions
9337
9338 // Integer Logical Instructions
9339
9340 // And Instructions
9341 // And Register with Register
9342 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9343 %{
9344 match(Set dst (AndI dst src));
9345 effect(KILL cr);
9346
9347 format %{ "andl $dst, $src\t# int" %}
9348 opcode(0x23);
9349 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9350 ins_pipe(ialu_reg_reg);
9351 %}
9352
9353 // And Register with Immediate 255
9354 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9355 %{
9356 match(Set dst (AndI dst src));
9357
9358 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9359 opcode(0x0F, 0xB6);
9360 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9361 ins_pipe(ialu_reg);
9362 %}
9363
9364 // And Register with Immediate 255 and promote to long
9365 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9366 %{
9367 match(Set dst (ConvI2L (AndI src mask)));
9368
9369 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9370 opcode(0x0F, 0xB6);
9371 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9372 ins_pipe(ialu_reg);
9373 %}
9374
9375 // And Register with Immediate 65535
9376 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9377 %{
9378 match(Set dst (AndI dst src));
9379
9380 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9381 opcode(0x0F, 0xB7);
9382 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9383 ins_pipe(ialu_reg);
9384 %}
9385
9386 // And Register with Immediate 65535 and promote to long
9387 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9388 %{
9389 match(Set dst (ConvI2L (AndI src mask)));
9390
9391 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9392 opcode(0x0F, 0xB7);
9393 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9394 ins_pipe(ialu_reg);
9395 %}
9396
9397 // And Register with Immediate
9398 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9399 %{
9400 match(Set dst (AndI dst src));
9401 effect(KILL cr);
9402
9403 format %{ "andl $dst, $src\t# int" %}
9404 opcode(0x81, 0x04); /* Opcode 81 /4 */
9405 ins_encode(OpcSErm(dst, src), Con8or32(src));
9406 ins_pipe(ialu_reg);
9407 %}
9408
9409 // And Register with Memory
9410 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9411 %{
9412 match(Set dst (AndI dst (LoadI src)));
9413 effect(KILL cr);
9414
9415 ins_cost(125);
9416 format %{ "andl $dst, $src\t# int" %}
9417 opcode(0x23);
9418 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9419 ins_pipe(ialu_reg_mem);
9420 %}
9421
9422 // And Memory with Register
9423 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9424 %{
9425 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
9426 effect(KILL cr);
9427
9428 ins_cost(150);
9429 format %{ "andb $dst, $src\t# byte" %}
9430 opcode(0x20);
9431 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9432 ins_pipe(ialu_mem_reg);
9433 %}
9434
9435 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9436 %{
9437 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9438 effect(KILL cr);
9439
9440 ins_cost(150);
9441 format %{ "andl $dst, $src\t# int" %}
9442 opcode(0x21); /* Opcode 21 /r */
9443 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9444 ins_pipe(ialu_mem_reg);
9445 %}
9446
9447 // And Memory with Immediate
9448 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9449 %{
9450 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9451 effect(KILL cr);
9452
9453 ins_cost(125);
9454 format %{ "andl $dst, $src\t# int" %}
9455 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9456 ins_encode(REX_mem(dst), OpcSE(src),
9457 RM_opc_mem(secondary, dst), Con8or32(src));
9458 ins_pipe(ialu_mem_imm);
9459 %}
9460
9461 // BMI1 instructions
9462 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9463 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9464 predicate(UseBMI1Instructions);
9465 effect(KILL cr);
9466
9467 ins_cost(125);
9468 format %{ "andnl $dst, $src1, $src2" %}
9469
9470 ins_encode %{
9471 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9472 %}
9473 ins_pipe(ialu_reg_mem);
9474 %}
9475
9476 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9477 match(Set dst (AndI (XorI src1 minus_1) src2));
9478 predicate(UseBMI1Instructions);
9479 effect(KILL cr);
9480
9481 format %{ "andnl $dst, $src1, $src2" %}
9482
9483 ins_encode %{
9484 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9485 %}
9486 ins_pipe(ialu_reg);
9487 %}
9488
9489 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
9490 match(Set dst (AndI (SubI imm_zero src) src));
9491 predicate(UseBMI1Instructions);
9492 effect(KILL cr);
9493
9494 format %{ "blsil $dst, $src" %}
9495
9496 ins_encode %{
9497 __ blsil($dst$$Register, $src$$Register);
9498 %}
9499 ins_pipe(ialu_reg);
9500 %}
9501
9502 instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
9503 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9504 predicate(UseBMI1Instructions);
9505 effect(KILL cr);
9506
9507 ins_cost(125);
9508 format %{ "blsil $dst, $src" %}
9509
9510 ins_encode %{
9511 __ blsil($dst$$Register, $src$$Address);
9512 %}
9513 ins_pipe(ialu_reg_mem);
9514 %}
9515
9516 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9517 %{
9518 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9519 predicate(UseBMI1Instructions);
9520 effect(KILL cr);
9521
9522 ins_cost(125);
9523 format %{ "blsmskl $dst, $src" %}
9524
9525 ins_encode %{
9526 __ blsmskl($dst$$Register, $src$$Address);
9527 %}
9528 ins_pipe(ialu_reg_mem);
9529 %}
9530
9531 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9532 %{
9533 match(Set dst (XorI (AddI src minus_1) src));
9534 predicate(UseBMI1Instructions);
9535 effect(KILL cr);
9536
9537 format %{ "blsmskl $dst, $src" %}
9538
9539 ins_encode %{
9540 __ blsmskl($dst$$Register, $src$$Register);
9541 %}
9542
9543 ins_pipe(ialu_reg);
9544 %}
9545
9546 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9547 %{
9548 match(Set dst (AndI (AddI src minus_1) src) );
9549 predicate(UseBMI1Instructions);
9550 effect(KILL cr);
9551
9552 format %{ "blsrl $dst, $src" %}
9553
9554 ins_encode %{
9555 __ blsrl($dst$$Register, $src$$Register);
9556 %}
9557
9558 ins_pipe(ialu_reg_mem);
9559 %}
9560
9561 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9562 %{
9563 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9564 predicate(UseBMI1Instructions);
9565 effect(KILL cr);
9566
9567 ins_cost(125);
9568 format %{ "blsrl $dst, $src" %}
9569
9570 ins_encode %{
9571 __ blsrl($dst$$Register, $src$$Address);
9572 %}
9573
9574 ins_pipe(ialu_reg);
9575 %}
9576
9577 // Or Instructions
9578 // Or Register with Register
9579 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9580 %{
9581 match(Set dst (OrI dst src));
9582 effect(KILL cr);
9583
9584 format %{ "orl $dst, $src\t# int" %}
9585 opcode(0x0B);
9586 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9587 ins_pipe(ialu_reg_reg);
9588 %}
9589
9590 // Or Register with Immediate
9591 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9592 %{
9593 match(Set dst (OrI dst src));
9594 effect(KILL cr);
9595
9596 format %{ "orl $dst, $src\t# int" %}
9597 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9598 ins_encode(OpcSErm(dst, src), Con8or32(src));
9599 ins_pipe(ialu_reg);
9600 %}
9601
9602 // Or Register with Memory
9603 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9604 %{
9605 match(Set dst (OrI dst (LoadI src)));
9606 effect(KILL cr);
9607
9608 ins_cost(125);
9609 format %{ "orl $dst, $src\t# int" %}
9610 opcode(0x0B);
9611 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9612 ins_pipe(ialu_reg_mem);
9613 %}
9614
9615 // Or Memory with Register
9616 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9617 %{
9618 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
9619 effect(KILL cr);
9620
9621 ins_cost(150);
9622 format %{ "orb $dst, $src\t# byte" %}
9623 opcode(0x08);
9624 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9625 ins_pipe(ialu_mem_reg);
9626 %}
9627
9628 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9629 %{
9630 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9631 effect(KILL cr);
9632
9633 ins_cost(150);
9634 format %{ "orl $dst, $src\t# int" %}
9635 opcode(0x09); /* Opcode 09 /r */
9636 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9637 ins_pipe(ialu_mem_reg);
9638 %}
9639
9640 // Or Memory with Immediate
9641 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9642 %{
9643 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9644 effect(KILL cr);
9645
9646 ins_cost(125);
9647 format %{ "orl $dst, $src\t# int" %}
9648 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9649 ins_encode(REX_mem(dst), OpcSE(src),
9650 RM_opc_mem(secondary, dst), Con8or32(src));
9651 ins_pipe(ialu_mem_imm);
9652 %}
9653
9654 // Xor Instructions
9655 // Xor Register with Register
9656 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9657 %{
9658 match(Set dst (XorI dst src));
9659 effect(KILL cr);
9660
9661 format %{ "xorl $dst, $src\t# int" %}
9662 opcode(0x33);
9663 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9664 ins_pipe(ialu_reg_reg);
9665 %}
9666
9667 // Xor Register with Immediate -1
9668 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9669 match(Set dst (XorI dst imm));
9670
9671 format %{ "not $dst" %}
9672 ins_encode %{
9673 __ notl($dst$$Register);
9674 %}
9675 ins_pipe(ialu_reg);
9676 %}
9677
9678 // Xor Register with Immediate
9679 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9680 %{
9681 match(Set dst (XorI dst src));
9682 effect(KILL cr);
9683
9684 format %{ "xorl $dst, $src\t# int" %}
9685 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9686 ins_encode(OpcSErm(dst, src), Con8or32(src));
9687 ins_pipe(ialu_reg);
9688 %}
9689
9690 // Xor Register with Memory
9691 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9692 %{
9693 match(Set dst (XorI dst (LoadI src)));
9694 effect(KILL cr);
9695
9696 ins_cost(125);
9697 format %{ "xorl $dst, $src\t# int" %}
9698 opcode(0x33);
9699 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9700 ins_pipe(ialu_reg_mem);
9701 %}
9702
9703 // Xor Memory with Register
9704 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9705 %{
9706 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
9707 effect(KILL cr);
9708
9709 ins_cost(150);
9710 format %{ "xorb $dst, $src\t# byte" %}
9711 opcode(0x30);
9712 ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9713 ins_pipe(ialu_mem_reg);
9714 %}
9715
9716 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9717 %{
9718 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9719 effect(KILL cr);
9720
9721 ins_cost(150);
9722 format %{ "xorl $dst, $src\t# int" %}
9723 opcode(0x31); /* Opcode 31 /r */
9724 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9725 ins_pipe(ialu_mem_reg);
9726 %}
9727
9728 // Xor Memory with Immediate
9729 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9730 %{
9731 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9732 effect(KILL cr);
9733
9734 ins_cost(125);
9735 format %{ "xorl $dst, $src\t# int" %}
9736 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9737 ins_encode(REX_mem(dst), OpcSE(src),
9738 RM_opc_mem(secondary, dst), Con8or32(src));
9739 ins_pipe(ialu_mem_imm);
9740 %}
9741
9742
9743 // Long Logical Instructions
9744
9745 // And Instructions
9746 // And Register with Register
9747 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9748 %{
9749 match(Set dst (AndL dst src));
9750 effect(KILL cr);
9751
9752 format %{ "andq $dst, $src\t# long" %}
9753 opcode(0x23);
9754 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9755 ins_pipe(ialu_reg_reg);
9756 %}
9757
9758 // And Register with Immediate 255
9759 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9760 %{
9761 match(Set dst (AndL dst src));
9762
9763 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9764 opcode(0x0F, 0xB6);
9765 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9766 ins_pipe(ialu_reg);
9767 %}
9768
9769 // And Register with Immediate 65535
9770 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9771 %{
9772 match(Set dst (AndL dst src));
9773
9774 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9775 opcode(0x0F, 0xB7);
9776 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9777 ins_pipe(ialu_reg);
9778 %}
9779
9780 // And Register with Immediate
9781 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9782 %{
9783 match(Set dst (AndL dst src));
9784 effect(KILL cr);
9785
9786 format %{ "andq $dst, $src\t# long" %}
9787 opcode(0x81, 0x04); /* Opcode 81 /4 */
9788 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9789 ins_pipe(ialu_reg);
9790 %}
9791
9792 // And Register with Memory
9793 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9794 %{
9795 match(Set dst (AndL dst (LoadL src)));
9796 effect(KILL cr);
9797
9798 ins_cost(125);
9799 format %{ "andq $dst, $src\t# long" %}
9800 opcode(0x23);
9801 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9802 ins_pipe(ialu_reg_mem);
9803 %}
9804
9805 // And Memory with Register
9806 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9807 %{
9808 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9809 effect(KILL cr);
9810
9811 ins_cost(150);
9812 format %{ "andq $dst, $src\t# long" %}
9813 opcode(0x21); /* Opcode 21 /r */
9814 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9815 ins_pipe(ialu_mem_reg);
9816 %}
9817
9818 // And Memory with Immediate
9819 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9820 %{
9821 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9822 effect(KILL cr);
9823
9824 ins_cost(125);
9825 format %{ "andq $dst, $src\t# long" %}
9826 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9827 ins_encode(REX_mem_wide(dst), OpcSE(src),
9828 RM_opc_mem(secondary, dst), Con8or32(src));
9829 ins_pipe(ialu_mem_imm);
9830 %}
9831
9832 instruct btrL_mem_imm(memory dst, immL_NotPow2 con, rFlagsReg cr)
9833 %{
9834 // con should be a pure 64-bit immediate given that not(con) is a power of 2
9835 // because AND/OR works well enough for 8/32-bit values.
9836 predicate(log2_long(~n->in(3)->in(2)->get_long()) > 30);
9837
9838 match(Set dst (StoreL dst (AndL (LoadL dst) con)));
9839 effect(KILL cr);
9840
9841 ins_cost(125);
9842 format %{ "btrq $dst, log2(not($con))\t# long" %}
9843 ins_encode %{
9844 __ btrq($dst$$Address, log2_long(~$con$$constant));
9845 %}
9846 ins_pipe(ialu_mem_imm);
9847 %}
9848
9849 // BMI1 instructions
9850 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9851 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9852 predicate(UseBMI1Instructions);
9853 effect(KILL cr);
9854
9855 ins_cost(125);
9856 format %{ "andnq $dst, $src1, $src2" %}
9857
9858 ins_encode %{
9859 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9860 %}
9861 ins_pipe(ialu_reg_mem);
9862 %}
9863
9864 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9865 match(Set dst (AndL (XorL src1 minus_1) src2));
9866 predicate(UseBMI1Instructions);
9867 effect(KILL cr);
9868
9869 format %{ "andnq $dst, $src1, $src2" %}
9870
9871 ins_encode %{
9872 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9873 %}
9874 ins_pipe(ialu_reg_mem);
9875 %}
9876
9877 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9878 match(Set dst (AndL (SubL imm_zero src) src));
9879 predicate(UseBMI1Instructions);
9880 effect(KILL cr);
9881
9882 format %{ "blsiq $dst, $src" %}
9883
9884 ins_encode %{
9885 __ blsiq($dst$$Register, $src$$Register);
9886 %}
9887 ins_pipe(ialu_reg);
9888 %}
9889
9890 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9891 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9892 predicate(UseBMI1Instructions);
9893 effect(KILL cr);
9894
9895 ins_cost(125);
9896 format %{ "blsiq $dst, $src" %}
9897
9898 ins_encode %{
9899 __ blsiq($dst$$Register, $src$$Address);
9900 %}
9901 ins_pipe(ialu_reg_mem);
9902 %}
9903
9904 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9905 %{
9906 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9907 predicate(UseBMI1Instructions);
9908 effect(KILL cr);
9909
9910 ins_cost(125);
9911 format %{ "blsmskq $dst, $src" %}
9912
9913 ins_encode %{
9914 __ blsmskq($dst$$Register, $src$$Address);
9915 %}
9916 ins_pipe(ialu_reg_mem);
9917 %}
9918
9919 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9920 %{
9921 match(Set dst (XorL (AddL src minus_1) src));
9922 predicate(UseBMI1Instructions);
9923 effect(KILL cr);
9924
9925 format %{ "blsmskq $dst, $src" %}
9926
9927 ins_encode %{
9928 __ blsmskq($dst$$Register, $src$$Register);
9929 %}
9930
9931 ins_pipe(ialu_reg);
9932 %}
9933
9934 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9935 %{
9936 match(Set dst (AndL (AddL src minus_1) src) );
9937 predicate(UseBMI1Instructions);
9938 effect(KILL cr);
9939
9940 format %{ "blsrq $dst, $src" %}
9941
9942 ins_encode %{
9943 __ blsrq($dst$$Register, $src$$Register);
9944 %}
9945
9946 ins_pipe(ialu_reg);
9947 %}
9948
9949 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9950 %{
9951 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9952 predicate(UseBMI1Instructions);
9953 effect(KILL cr);
9954
9955 ins_cost(125);
9956 format %{ "blsrq $dst, $src" %}
9957
9958 ins_encode %{
9959 __ blsrq($dst$$Register, $src$$Address);
9960 %}
9961
9962 ins_pipe(ialu_reg);
9963 %}
9964
9965 // Or Instructions
9966 // Or Register with Register
9967 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9968 %{
9969 match(Set dst (OrL dst src));
9970 effect(KILL cr);
9971
9972 format %{ "orq $dst, $src\t# long" %}
9973 opcode(0x0B);
9974 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9975 ins_pipe(ialu_reg_reg);
9976 %}
9977
9978 // Use any_RegP to match R15 (TLS register) without spilling.
9979 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9980 match(Set dst (OrL dst (CastP2X src)));
9981 effect(KILL cr);
9982
9983 format %{ "orq $dst, $src\t# long" %}
9984 opcode(0x0B);
9985 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9986 ins_pipe(ialu_reg_reg);
9987 %}
9988
9989
9990 // Or Register with Immediate
9991 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9992 %{
9993 match(Set dst (OrL dst src));
9994 effect(KILL cr);
9995
9996 format %{ "orq $dst, $src\t# long" %}
9997 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9998 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9999 ins_pipe(ialu_reg);
10000 %}
10001
10002 // Or Register with Memory
10003 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10004 %{
10005 match(Set dst (OrL dst (LoadL src)));
10006 effect(KILL cr);
10007
10008 ins_cost(125);
10009 format %{ "orq $dst, $src\t# long" %}
10010 opcode(0x0B);
10011 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10012 ins_pipe(ialu_reg_mem);
10013 %}
10014
10015 // Or Memory with Register
10016 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10017 %{
10018 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10019 effect(KILL cr);
10020
10021 ins_cost(150);
10022 format %{ "orq $dst, $src\t# long" %}
10023 opcode(0x09); /* Opcode 09 /r */
10024 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10025 ins_pipe(ialu_mem_reg);
10026 %}
10027
10028 // Or Memory with Immediate
10029 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10030 %{
10031 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10032 effect(KILL cr);
10033
10034 ins_cost(125);
10035 format %{ "orq $dst, $src\t# long" %}
10036 opcode(0x81, 0x1); /* Opcode 81 /1 id */
10037 ins_encode(REX_mem_wide(dst), OpcSE(src),
10038 RM_opc_mem(secondary, dst), Con8or32(src));
10039 ins_pipe(ialu_mem_imm);
10040 %}
10041
10042 instruct btsL_mem_imm(memory dst, immL_Pow2 con, rFlagsReg cr)
10043 %{
10044 // con should be a pure 64-bit power of 2 immediate
10045 // because AND/OR works well enough for 8/32-bit values.
10046 predicate(log2_long(n->in(3)->in(2)->get_long()) > 31);
10047
10048 match(Set dst (StoreL dst (OrL (LoadL dst) con)));
10049 effect(KILL cr);
10050
10051 ins_cost(125);
10052 format %{ "btsq $dst, log2($con)\t# long" %}
10053 ins_encode %{
10054 __ btsq($dst$$Address, log2_long((julong)$con$$constant));
10055 %}
10056 ins_pipe(ialu_mem_imm);
10057 %}
10058
10059 // Xor Instructions
10060 // Xor Register with Register
10061 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10062 %{
10063 match(Set dst (XorL dst src));
10064 effect(KILL cr);
10065
10066 format %{ "xorq $dst, $src\t# long" %}
10067 opcode(0x33);
10068 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10069 ins_pipe(ialu_reg_reg);
10070 %}
10071
10072 // Xor Register with Immediate -1
10073 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10074 match(Set dst (XorL dst imm));
10075
10076 format %{ "notq $dst" %}
10077 ins_encode %{
10078 __ notq($dst$$Register);
10079 %}
10080 ins_pipe(ialu_reg);
10081 %}
10082
10083 // Xor Register with Immediate
10084 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10085 %{
10086 match(Set dst (XorL dst src));
10087 effect(KILL cr);
10088
10089 format %{ "xorq $dst, $src\t# long" %}
10090 opcode(0x81, 0x06); /* Opcode 81 /6 id */
10091 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10092 ins_pipe(ialu_reg);
10093 %}
10094
10095 // Xor Register with Memory
10096 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10097 %{
10098 match(Set dst (XorL dst (LoadL src)));
10099 effect(KILL cr);
10100
10101 ins_cost(125);
10102 format %{ "xorq $dst, $src\t# long" %}
10103 opcode(0x33);
10104 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10105 ins_pipe(ialu_reg_mem);
10106 %}
10107
10108 // Xor Memory with Register
10109 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10110 %{
10111 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10112 effect(KILL cr);
10113
10114 ins_cost(150);
10115 format %{ "xorq $dst, $src\t# long" %}
10116 opcode(0x31); /* Opcode 31 /r */
10117 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10118 ins_pipe(ialu_mem_reg);
10119 %}
10120
10121 // Xor Memory with Immediate
10122 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10123 %{
10124 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10125 effect(KILL cr);
10126
10127 ins_cost(125);
10128 format %{ "xorq $dst, $src\t# long" %}
10129 opcode(0x81, 0x6); /* Opcode 81 /6 id */
10130 ins_encode(REX_mem_wide(dst), OpcSE(src),
10131 RM_opc_mem(secondary, dst), Con8or32(src));
10132 ins_pipe(ialu_mem_imm);
10133 %}
10134
10135 // Convert Int to Boolean
10136 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10137 %{
10138 match(Set dst (Conv2B src));
10139 effect(KILL cr);
10140
10141 format %{ "testl $src, $src\t# ci2b\n\t"
10142 "setnz $dst\n\t"
10143 "movzbl $dst, $dst" %}
10144 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
10145 setNZ_reg(dst),
10146 REX_reg_breg(dst, dst), // movzbl
10147 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10148 ins_pipe(pipe_slow); // XXX
10149 %}
10150
10151 // Convert Pointer to Boolean
10152 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10153 %{
10154 match(Set dst (Conv2B src));
10155 effect(KILL cr);
10156
10157 format %{ "testq $src, $src\t# cp2b\n\t"
10158 "setnz $dst\n\t"
10159 "movzbl $dst, $dst" %}
10160 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
10161 setNZ_reg(dst),
10162 REX_reg_breg(dst, dst), // movzbl
10163 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10164 ins_pipe(pipe_slow); // XXX
10165 %}
10166
10167 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10168 %{
10169 match(Set dst (CmpLTMask p q));
10170 effect(KILL cr);
10171
10172 ins_cost(400);
10173 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10174 "setlt $dst\n\t"
10175 "movzbl $dst, $dst\n\t"
10176 "negl $dst" %}
10177 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10178 setLT_reg(dst),
10179 REX_reg_breg(dst, dst), // movzbl
10180 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10181 neg_reg(dst));
10182 ins_pipe(pipe_slow);
10183 %}
10184
10185 instruct cmpLTMask0(rRegI dst, immI_0 zero, rFlagsReg cr)
10186 %{
10187 match(Set dst (CmpLTMask dst zero));
10188 effect(KILL cr);
10189
10190 ins_cost(100);
10191 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10192 ins_encode %{
10193 __ sarl($dst$$Register, 31);
10194 %}
10195 ins_pipe(ialu_reg);
10196 %}
10197
10198 /* Better to save a register than avoid a branch */
10199 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10200 %{
10201 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10202 effect(KILL cr);
10203 ins_cost(300);
10204 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
10205 "jge done\n\t"
10206 "addl $p,$y\n"
10207 "done: " %}
10208 ins_encode %{
10209 Register Rp = $p$$Register;
10210 Register Rq = $q$$Register;
10211 Register Ry = $y$$Register;
10212 Label done;
10213 __ subl(Rp, Rq);
10214 __ jccb(Assembler::greaterEqual, done);
10215 __ addl(Rp, Ry);
10216 __ bind(done);
10217 %}
10218 ins_pipe(pipe_cmplt);
10219 %}
10220
10221 /* Better to save a register than avoid a branch */
10222 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10223 %{
10224 match(Set y (AndI (CmpLTMask p q) y));
10225 effect(KILL cr);
10226
10227 ins_cost(300);
10228
10229 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
10230 "jlt done\n\t"
10231 "xorl $y, $y\n"
10232 "done: " %}
10233 ins_encode %{
10234 Register Rp = $p$$Register;
10235 Register Rq = $q$$Register;
10236 Register Ry = $y$$Register;
10237 Label done;
10238 __ cmpl(Rp, Rq);
10239 __ jccb(Assembler::less, done);
10240 __ xorl(Ry, Ry);
10241 __ bind(done);
10242 %}
10243 ins_pipe(pipe_cmplt);
10244 %}
10245
10246
10247 //---------- FP Instructions------------------------------------------------
10248
10249 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10250 %{
10251 match(Set cr (CmpF src1 src2));
10252
10253 ins_cost(145);
10254 format %{ "ucomiss $src1, $src2\n\t"
10255 "jnp,s exit\n\t"
10256 "pushfq\t# saw NaN, set CF\n\t"
10257 "andq [rsp], #0xffffff2b\n\t"
10258 "popfq\n"
10259 "exit:" %}
10260 ins_encode %{
10261 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10262 emit_cmpfp_fixup(_masm);
10263 %}
10264 ins_pipe(pipe_slow);
10265 %}
10266
10267 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10268 match(Set cr (CmpF src1 src2));
10269
10270 ins_cost(100);
10271 format %{ "ucomiss $src1, $src2" %}
10272 ins_encode %{
10273 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10274 %}
10275 ins_pipe(pipe_slow);
10276 %}
10277
10278 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10279 %{
10280 match(Set cr (CmpF src1 (LoadF src2)));
10281
10282 ins_cost(145);
10283 format %{ "ucomiss $src1, $src2\n\t"
10284 "jnp,s exit\n\t"
10285 "pushfq\t# saw NaN, set CF\n\t"
10286 "andq [rsp], #0xffffff2b\n\t"
10287 "popfq\n"
10288 "exit:" %}
10289 ins_encode %{
10290 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10291 emit_cmpfp_fixup(_masm);
10292 %}
10293 ins_pipe(pipe_slow);
10294 %}
10295
10296 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10297 match(Set cr (CmpF src1 (LoadF src2)));
10298
10299 ins_cost(100);
10300 format %{ "ucomiss $src1, $src2" %}
10301 ins_encode %{
10302 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10303 %}
10304 ins_pipe(pipe_slow);
10305 %}
10306
10307 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10308 match(Set cr (CmpF src con));
10309
10310 ins_cost(145);
10311 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10312 "jnp,s exit\n\t"
10313 "pushfq\t# saw NaN, set CF\n\t"
10314 "andq [rsp], #0xffffff2b\n\t"
10315 "popfq\n"
10316 "exit:" %}
10317 ins_encode %{
10318 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10319 emit_cmpfp_fixup(_masm);
10320 %}
10321 ins_pipe(pipe_slow);
10322 %}
10323
10324 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10325 match(Set cr (CmpF src con));
10326 ins_cost(100);
10327 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10328 ins_encode %{
10329 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10330 %}
10331 ins_pipe(pipe_slow);
10332 %}
10333
10334 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10335 %{
10336 match(Set cr (CmpD src1 src2));
10337
10338 ins_cost(145);
10339 format %{ "ucomisd $src1, $src2\n\t"
10340 "jnp,s exit\n\t"
10341 "pushfq\t# saw NaN, set CF\n\t"
10342 "andq [rsp], #0xffffff2b\n\t"
10343 "popfq\n"
10344 "exit:" %}
10345 ins_encode %{
10346 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10347 emit_cmpfp_fixup(_masm);
10348 %}
10349 ins_pipe(pipe_slow);
10350 %}
10351
10352 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10353 match(Set cr (CmpD src1 src2));
10354
10355 ins_cost(100);
10356 format %{ "ucomisd $src1, $src2 test" %}
10357 ins_encode %{
10358 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10359 %}
10360 ins_pipe(pipe_slow);
10361 %}
10362
10363 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10364 %{
10365 match(Set cr (CmpD src1 (LoadD src2)));
10366
10367 ins_cost(145);
10368 format %{ "ucomisd $src1, $src2\n\t"
10369 "jnp,s exit\n\t"
10370 "pushfq\t# saw NaN, set CF\n\t"
10371 "andq [rsp], #0xffffff2b\n\t"
10372 "popfq\n"
10373 "exit:" %}
10374 ins_encode %{
10375 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10376 emit_cmpfp_fixup(_masm);
10377 %}
10378 ins_pipe(pipe_slow);
10379 %}
10380
10381 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10382 match(Set cr (CmpD src1 (LoadD src2)));
10383
10384 ins_cost(100);
10385 format %{ "ucomisd $src1, $src2" %}
10386 ins_encode %{
10387 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10388 %}
10389 ins_pipe(pipe_slow);
10390 %}
10391
10392 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10393 match(Set cr (CmpD src con));
10394
10395 ins_cost(145);
10396 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10397 "jnp,s exit\n\t"
10398 "pushfq\t# saw NaN, set CF\n\t"
10399 "andq [rsp], #0xffffff2b\n\t"
10400 "popfq\n"
10401 "exit:" %}
10402 ins_encode %{
10403 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10404 emit_cmpfp_fixup(_masm);
10405 %}
10406 ins_pipe(pipe_slow);
10407 %}
10408
10409 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10410 match(Set cr (CmpD src con));
10411 ins_cost(100);
10412 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10413 ins_encode %{
10414 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10415 %}
10416 ins_pipe(pipe_slow);
10417 %}
10418
10419 // Compare into -1,0,1
10420 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10421 %{
10422 match(Set dst (CmpF3 src1 src2));
10423 effect(KILL cr);
10424
10425 ins_cost(275);
10426 format %{ "ucomiss $src1, $src2\n\t"
10427 "movl $dst, #-1\n\t"
10428 "jp,s done\n\t"
10429 "jb,s done\n\t"
10430 "setne $dst\n\t"
10431 "movzbl $dst, $dst\n"
10432 "done:" %}
10433 ins_encode %{
10434 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10435 emit_cmpfp3(_masm, $dst$$Register);
10436 %}
10437 ins_pipe(pipe_slow);
10438 %}
10439
10440 // Compare into -1,0,1
10441 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10442 %{
10443 match(Set dst (CmpF3 src1 (LoadF src2)));
10444 effect(KILL cr);
10445
10446 ins_cost(275);
10447 format %{ "ucomiss $src1, $src2\n\t"
10448 "movl $dst, #-1\n\t"
10449 "jp,s done\n\t"
10450 "jb,s done\n\t"
10451 "setne $dst\n\t"
10452 "movzbl $dst, $dst\n"
10453 "done:" %}
10454 ins_encode %{
10455 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10456 emit_cmpfp3(_masm, $dst$$Register);
10457 %}
10458 ins_pipe(pipe_slow);
10459 %}
10460
10461 // Compare into -1,0,1
10462 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10463 match(Set dst (CmpF3 src con));
10464 effect(KILL cr);
10465
10466 ins_cost(275);
10467 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10468 "movl $dst, #-1\n\t"
10469 "jp,s done\n\t"
10470 "jb,s done\n\t"
10471 "setne $dst\n\t"
10472 "movzbl $dst, $dst\n"
10473 "done:" %}
10474 ins_encode %{
10475 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10476 emit_cmpfp3(_masm, $dst$$Register);
10477 %}
10478 ins_pipe(pipe_slow);
10479 %}
10480
10481 // Compare into -1,0,1
10482 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10483 %{
10484 match(Set dst (CmpD3 src1 src2));
10485 effect(KILL cr);
10486
10487 ins_cost(275);
10488 format %{ "ucomisd $src1, $src2\n\t"
10489 "movl $dst, #-1\n\t"
10490 "jp,s done\n\t"
10491 "jb,s done\n\t"
10492 "setne $dst\n\t"
10493 "movzbl $dst, $dst\n"
10494 "done:" %}
10495 ins_encode %{
10496 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10497 emit_cmpfp3(_masm, $dst$$Register);
10498 %}
10499 ins_pipe(pipe_slow);
10500 %}
10501
10502 // Compare into -1,0,1
10503 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10504 %{
10505 match(Set dst (CmpD3 src1 (LoadD src2)));
10506 effect(KILL cr);
10507
10508 ins_cost(275);
10509 format %{ "ucomisd $src1, $src2\n\t"
10510 "movl $dst, #-1\n\t"
10511 "jp,s done\n\t"
10512 "jb,s done\n\t"
10513 "setne $dst\n\t"
10514 "movzbl $dst, $dst\n"
10515 "done:" %}
10516 ins_encode %{
10517 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10518 emit_cmpfp3(_masm, $dst$$Register);
10519 %}
10520 ins_pipe(pipe_slow);
10521 %}
10522
10523 // Compare into -1,0,1
10524 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10525 match(Set dst (CmpD3 src con));
10526 effect(KILL cr);
10527
10528 ins_cost(275);
10529 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10530 "movl $dst, #-1\n\t"
10531 "jp,s done\n\t"
10532 "jb,s done\n\t"
10533 "setne $dst\n\t"
10534 "movzbl $dst, $dst\n"
10535 "done:" %}
10536 ins_encode %{
10537 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10538 emit_cmpfp3(_masm, $dst$$Register);
10539 %}
10540 ins_pipe(pipe_slow);
10541 %}
10542
10543 //----------Arithmetic Conversion Instructions---------------------------------
10544
10545 instruct convF2D_reg_reg(regD dst, regF src)
10546 %{
10547 match(Set dst (ConvF2D src));
10548
10549 format %{ "cvtss2sd $dst, $src" %}
10550 ins_encode %{
10551 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10552 %}
10553 ins_pipe(pipe_slow); // XXX
10554 %}
10555
10556 instruct convF2D_reg_mem(regD dst, memory src)
10557 %{
10558 match(Set dst (ConvF2D (LoadF src)));
10559
10560 format %{ "cvtss2sd $dst, $src" %}
10561 ins_encode %{
10562 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10563 %}
10564 ins_pipe(pipe_slow); // XXX
10565 %}
10566
10567 instruct convD2F_reg_reg(regF dst, regD src)
10568 %{
10569 match(Set dst (ConvD2F src));
10570
10571 format %{ "cvtsd2ss $dst, $src" %}
10572 ins_encode %{
10573 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10574 %}
10575 ins_pipe(pipe_slow); // XXX
10576 %}
10577
10578 instruct convD2F_reg_mem(regF dst, memory src)
10579 %{
10580 match(Set dst (ConvD2F (LoadD src)));
10581
10582 format %{ "cvtsd2ss $dst, $src" %}
10583 ins_encode %{
10584 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10585 %}
10586 ins_pipe(pipe_slow); // XXX
10587 %}
10588
10589 // XXX do mem variants
10590 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10591 %{
10592 match(Set dst (ConvF2I src));
10593 effect(KILL cr);
10594 format %{ "convert_f2i $dst,$src" %}
10595 ins_encode %{
10596 __ convert_f2i($dst$$Register, $src$$XMMRegister);
10597 %}
10598 ins_pipe(pipe_slow);
10599 %}
10600
10601 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10602 %{
10603 match(Set dst (ConvF2L src));
10604 effect(KILL cr);
10605 format %{ "convert_f2l $dst,$src"%}
10606 ins_encode %{
10607 __ convert_f2l($dst$$Register, $src$$XMMRegister);
10608 %}
10609 ins_pipe(pipe_slow);
10610 %}
10611
10612 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10613 %{
10614 match(Set dst (ConvD2I src));
10615 effect(KILL cr);
10616 format %{ "convert_d2i $dst,$src"%}
10617 ins_encode %{
10618 __ convert_d2i($dst$$Register, $src$$XMMRegister);
10619 %}
10620 ins_pipe(pipe_slow);
10621 %}
10622
10623 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10624 %{
10625 match(Set dst (ConvD2L src));
10626 effect(KILL cr);
10627 format %{ "convert_d2l $dst,$src"%}
10628 ins_encode %{
10629 __ convert_d2l($dst$$Register, $src$$XMMRegister);
10630 %}
10631 ins_pipe(pipe_slow);
10632 %}
10633
10634 instruct convI2F_reg_reg(regF dst, rRegI src)
10635 %{
10636 predicate(!UseXmmI2F);
10637 match(Set dst (ConvI2F src));
10638
10639 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10640 ins_encode %{
10641 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10642 %}
10643 ins_pipe(pipe_slow); // XXX
10644 %}
10645
10646 instruct convI2F_reg_mem(regF dst, memory src)
10647 %{
10648 match(Set dst (ConvI2F (LoadI src)));
10649
10650 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10651 ins_encode %{
10652 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10653 %}
10654 ins_pipe(pipe_slow); // XXX
10655 %}
10656
10657 instruct convI2D_reg_reg(regD dst, rRegI src)
10658 %{
10659 predicate(!UseXmmI2D);
10660 match(Set dst (ConvI2D src));
10661
10662 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10663 ins_encode %{
10664 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10665 %}
10666 ins_pipe(pipe_slow); // XXX
10667 %}
10668
10669 instruct convI2D_reg_mem(regD dst, memory src)
10670 %{
10671 match(Set dst (ConvI2D (LoadI src)));
10672
10673 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10674 ins_encode %{
10675 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10676 %}
10677 ins_pipe(pipe_slow); // XXX
10678 %}
10679
10680 instruct convXI2F_reg(regF dst, rRegI src)
10681 %{
10682 predicate(UseXmmI2F);
10683 match(Set dst (ConvI2F src));
10684
10685 format %{ "movdl $dst, $src\n\t"
10686 "cvtdq2psl $dst, $dst\t# i2f" %}
10687 ins_encode %{
10688 __ movdl($dst$$XMMRegister, $src$$Register);
10689 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10690 %}
10691 ins_pipe(pipe_slow); // XXX
10692 %}
10693
10694 instruct convXI2D_reg(regD dst, rRegI src)
10695 %{
10696 predicate(UseXmmI2D);
10697 match(Set dst (ConvI2D src));
10698
10699 format %{ "movdl $dst, $src\n\t"
10700 "cvtdq2pdl $dst, $dst\t# i2d" %}
10701 ins_encode %{
10702 __ movdl($dst$$XMMRegister, $src$$Register);
10703 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10704 %}
10705 ins_pipe(pipe_slow); // XXX
10706 %}
10707
10708 instruct convL2F_reg_reg(regF dst, rRegL src)
10709 %{
10710 match(Set dst (ConvL2F src));
10711
10712 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10713 ins_encode %{
10714 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10715 %}
10716 ins_pipe(pipe_slow); // XXX
10717 %}
10718
10719 instruct convL2F_reg_mem(regF dst, memory src)
10720 %{
10721 match(Set dst (ConvL2F (LoadL src)));
10722
10723 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10724 ins_encode %{
10725 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10726 %}
10727 ins_pipe(pipe_slow); // XXX
10728 %}
10729
10730 instruct convL2D_reg_reg(regD dst, rRegL src)
10731 %{
10732 match(Set dst (ConvL2D src));
10733
10734 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10735 ins_encode %{
10736 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10737 %}
10738 ins_pipe(pipe_slow); // XXX
10739 %}
10740
10741 instruct convL2D_reg_mem(regD dst, memory src)
10742 %{
10743 match(Set dst (ConvL2D (LoadL src)));
10744
10745 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10746 ins_encode %{
10747 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10748 %}
10749 ins_pipe(pipe_slow); // XXX
10750 %}
10751
10752 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10753 %{
10754 match(Set dst (ConvI2L src));
10755
10756 ins_cost(125);
10757 format %{ "movslq $dst, $src\t# i2l" %}
10758 ins_encode %{
10759 __ movslq($dst$$Register, $src$$Register);
10760 %}
10761 ins_pipe(ialu_reg_reg);
10762 %}
10763
10764 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10765 // %{
10766 // match(Set dst (ConvI2L src));
10767 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10768 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10769 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10770 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10771 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10772 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10773
10774 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10775 // ins_encode(enc_copy(dst, src));
10776 // // opcode(0x63); // needs REX.W
10777 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10778 // ins_pipe(ialu_reg_reg);
10779 // %}
10780
10781 // Zero-extend convert int to long
10782 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10783 %{
10784 match(Set dst (AndL (ConvI2L src) mask));
10785
10786 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10787 ins_encode %{
10788 if ($dst$$reg != $src$$reg) {
10789 __ movl($dst$$Register, $src$$Register);
10790 }
10791 %}
10792 ins_pipe(ialu_reg_reg);
10793 %}
10794
10795 // Zero-extend convert int to long
10796 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10797 %{
10798 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10799
10800 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10801 ins_encode %{
10802 __ movl($dst$$Register, $src$$Address);
10803 %}
10804 ins_pipe(ialu_reg_mem);
10805 %}
10806
10807 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10808 %{
10809 match(Set dst (AndL src mask));
10810
10811 format %{ "movl $dst, $src\t# zero-extend long" %}
10812 ins_encode %{
10813 __ movl($dst$$Register, $src$$Register);
10814 %}
10815 ins_pipe(ialu_reg_reg);
10816 %}
10817
10818 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10819 %{
10820 match(Set dst (ConvL2I src));
10821
10822 format %{ "movl $dst, $src\t# l2i" %}
10823 ins_encode %{
10824 __ movl($dst$$Register, $src$$Register);
10825 %}
10826 ins_pipe(ialu_reg_reg);
10827 %}
10828
10829
10830 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10831 match(Set dst (MoveF2I src));
10832 effect(DEF dst, USE src);
10833
10834 ins_cost(125);
10835 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10836 ins_encode %{
10837 __ movl($dst$$Register, Address(rsp, $src$$disp));
10838 %}
10839 ins_pipe(ialu_reg_mem);
10840 %}
10841
10842 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10843 match(Set dst (MoveI2F src));
10844 effect(DEF dst, USE src);
10845
10846 ins_cost(125);
10847 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10848 ins_encode %{
10849 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10850 %}
10851 ins_pipe(pipe_slow);
10852 %}
10853
10854 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10855 match(Set dst (MoveD2L src));
10856 effect(DEF dst, USE src);
10857
10858 ins_cost(125);
10859 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10860 ins_encode %{
10861 __ movq($dst$$Register, Address(rsp, $src$$disp));
10862 %}
10863 ins_pipe(ialu_reg_mem);
10864 %}
10865
10866 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10867 predicate(!UseXmmLoadAndClearUpper);
10868 match(Set dst (MoveL2D src));
10869 effect(DEF dst, USE src);
10870
10871 ins_cost(125);
10872 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10873 ins_encode %{
10874 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10875 %}
10876 ins_pipe(pipe_slow);
10877 %}
10878
10879 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10880 predicate(UseXmmLoadAndClearUpper);
10881 match(Set dst (MoveL2D src));
10882 effect(DEF dst, USE src);
10883
10884 ins_cost(125);
10885 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10886 ins_encode %{
10887 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10888 %}
10889 ins_pipe(pipe_slow);
10890 %}
10891
10892
10893 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10894 match(Set dst (MoveF2I src));
10895 effect(DEF dst, USE src);
10896
10897 ins_cost(95); // XXX
10898 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10899 ins_encode %{
10900 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10901 %}
10902 ins_pipe(pipe_slow);
10903 %}
10904
10905 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10906 match(Set dst (MoveI2F src));
10907 effect(DEF dst, USE src);
10908
10909 ins_cost(100);
10910 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10911 ins_encode %{
10912 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10913 %}
10914 ins_pipe( ialu_mem_reg );
10915 %}
10916
10917 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10918 match(Set dst (MoveD2L src));
10919 effect(DEF dst, USE src);
10920
10921 ins_cost(95); // XXX
10922 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10923 ins_encode %{
10924 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10925 %}
10926 ins_pipe(pipe_slow);
10927 %}
10928
10929 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10930 match(Set dst (MoveL2D src));
10931 effect(DEF dst, USE src);
10932
10933 ins_cost(100);
10934 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10935 ins_encode %{
10936 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10937 %}
10938 ins_pipe(ialu_mem_reg);
10939 %}
10940
10941 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10942 match(Set dst (MoveF2I src));
10943 effect(DEF dst, USE src);
10944 ins_cost(85);
10945 format %{ "movd $dst,$src\t# MoveF2I" %}
10946 ins_encode %{
10947 __ movdl($dst$$Register, $src$$XMMRegister);
10948 %}
10949 ins_pipe( pipe_slow );
10950 %}
10951
10952 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10953 match(Set dst (MoveD2L src));
10954 effect(DEF dst, USE src);
10955 ins_cost(85);
10956 format %{ "movd $dst,$src\t# MoveD2L" %}
10957 ins_encode %{
10958 __ movdq($dst$$Register, $src$$XMMRegister);
10959 %}
10960 ins_pipe( pipe_slow );
10961 %}
10962
10963 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10964 match(Set dst (MoveI2F src));
10965 effect(DEF dst, USE src);
10966 ins_cost(100);
10967 format %{ "movd $dst,$src\t# MoveI2F" %}
10968 ins_encode %{
10969 __ movdl($dst$$XMMRegister, $src$$Register);
10970 %}
10971 ins_pipe( pipe_slow );
10972 %}
10973
10974 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10975 match(Set dst (MoveL2D src));
10976 effect(DEF dst, USE src);
10977 ins_cost(100);
10978 format %{ "movd $dst,$src\t# MoveL2D" %}
10979 ins_encode %{
10980 __ movdq($dst$$XMMRegister, $src$$Register);
10981 %}
10982 ins_pipe( pipe_slow );
10983 %}
10984
10985
10986 // =======================================================================
10987 // fast clearing of an array
10988 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
10989 Universe dummy, rFlagsReg cr)
10990 %{
10991 predicate(!((ClearArrayNode*)n)->is_large());
10992 match(Set dummy (ClearArray cnt base));
10993 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
10994
10995 format %{ $$template
10996 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10997 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
10998 $$emit$$"jg LARGE\n\t"
10999 $$emit$$"dec rcx\n\t"
11000 $$emit$$"js DONE\t# Zero length\n\t"
11001 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
11002 $$emit$$"dec rcx\n\t"
11003 $$emit$$"jge LOOP\n\t"
11004 $$emit$$"jmp DONE\n\t"
11005 $$emit$$"# LARGE:\n\t"
11006 if (UseFastStosb) {
11007 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11008 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
11009 } else if (UseXMMForObjInit) {
11010 $$emit$$"mov rdi,rax\n\t"
11011 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11012 $$emit$$"jmpq L_zero_64_bytes\n\t"
11013 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11014 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11015 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11016 $$emit$$"add 0x40,rax\n\t"
11017 $$emit$$"# L_zero_64_bytes:\n\t"
11018 $$emit$$"sub 0x8,rcx\n\t"
11019 $$emit$$"jge L_loop\n\t"
11020 $$emit$$"add 0x4,rcx\n\t"
11021 $$emit$$"jl L_tail\n\t"
11022 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11023 $$emit$$"add 0x20,rax\n\t"
11024 $$emit$$"sub 0x4,rcx\n\t"
11025 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11026 $$emit$$"add 0x4,rcx\n\t"
11027 $$emit$$"jle L_end\n\t"
11028 $$emit$$"dec rcx\n\t"
11029 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11030 $$emit$$"vmovq xmm0,(rax)\n\t"
11031 $$emit$$"add 0x8,rax\n\t"
11032 $$emit$$"dec rcx\n\t"
11033 $$emit$$"jge L_sloop\n\t"
11034 $$emit$$"# L_end:\n\t"
11035 } else {
11036 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
11037 }
11038 $$emit$$"# DONE"
11039 %}
11040 ins_encode %{
11041 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11042 $tmp$$XMMRegister, false);
11043 %}
11044 ins_pipe(pipe_slow);
11045 %}
11046
11047 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11048 Universe dummy, rFlagsReg cr)
11049 %{
11050 predicate(((ClearArrayNode*)n)->is_large());
11051 match(Set dummy (ClearArray cnt base));
11052 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11053
11054 format %{ $$template
11055 if (UseFastStosb) {
11056 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11057 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11058 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
11059 } else if (UseXMMForObjInit) {
11060 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
11061 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11062 $$emit$$"jmpq L_zero_64_bytes\n\t"
11063 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11064 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11065 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11066 $$emit$$"add 0x40,rax\n\t"
11067 $$emit$$"# L_zero_64_bytes:\n\t"
11068 $$emit$$"sub 0x8,rcx\n\t"
11069 $$emit$$"jge L_loop\n\t"
11070 $$emit$$"add 0x4,rcx\n\t"
11071 $$emit$$"jl L_tail\n\t"
11072 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11073 $$emit$$"add 0x20,rax\n\t"
11074 $$emit$$"sub 0x4,rcx\n\t"
11075 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11076 $$emit$$"add 0x4,rcx\n\t"
11077 $$emit$$"jle L_end\n\t"
11078 $$emit$$"dec rcx\n\t"
11079 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11080 $$emit$$"vmovq xmm0,(rax)\n\t"
11081 $$emit$$"add 0x8,rax\n\t"
11082 $$emit$$"dec rcx\n\t"
11083 $$emit$$"jge L_sloop\n\t"
11084 $$emit$$"# L_end:\n\t"
11085 } else {
11086 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11087 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
11088 }
11089 %}
11090 ins_encode %{
11091 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11092 $tmp$$XMMRegister, true);
11093 %}
11094 ins_pipe(pipe_slow);
11095 %}
11096
11097 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11098 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11099 %{
11100 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11101 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11102 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11103
11104 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11105 ins_encode %{
11106 __ string_compare($str1$$Register, $str2$$Register,
11107 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11108 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
11109 %}
11110 ins_pipe( pipe_slow );
11111 %}
11112
11113 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11114 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11115 %{
11116 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11117 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11118 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11119
11120 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11121 ins_encode %{
11122 __ string_compare($str1$$Register, $str2$$Register,
11123 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11124 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
11125 %}
11126 ins_pipe( pipe_slow );
11127 %}
11128
11129 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11130 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11131 %{
11132 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11133 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11134 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11135
11136 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11137 ins_encode %{
11138 __ string_compare($str1$$Register, $str2$$Register,
11139 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11140 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
11141 %}
11142 ins_pipe( pipe_slow );
11143 %}
11144
11145 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11146 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11147 %{
11148 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11149 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11150 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11151
11152 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11153 ins_encode %{
11154 __ string_compare($str2$$Register, $str1$$Register,
11155 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11156 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
11157 %}
11158 ins_pipe( pipe_slow );
11159 %}
11160
11161 // fast search of substring with known size.
11162 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11163 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11164 %{
11165 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11166 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11167 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11168
11169 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11170 ins_encode %{
11171 int icnt2 = (int)$int_cnt2$$constant;
11172 if (icnt2 >= 16) {
11173 // IndexOf for constant substrings with size >= 16 elements
11174 // which don't need to be loaded through stack.
11175 __ string_indexofC8($str1$$Register, $str2$$Register,
11176 $cnt1$$Register, $cnt2$$Register,
11177 icnt2, $result$$Register,
11178 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11179 } else {
11180 // Small strings are loaded through stack if they cross page boundary.
11181 __ string_indexof($str1$$Register, $str2$$Register,
11182 $cnt1$$Register, $cnt2$$Register,
11183 icnt2, $result$$Register,
11184 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11185 }
11186 %}
11187 ins_pipe( pipe_slow );
11188 %}
11189
11190 // fast search of substring with known size.
11191 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11192 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11193 %{
11194 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11195 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11196 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11197
11198 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11199 ins_encode %{
11200 int icnt2 = (int)$int_cnt2$$constant;
11201 if (icnt2 >= 8) {
11202 // IndexOf for constant substrings with size >= 8 elements
11203 // which don't need to be loaded through stack.
11204 __ string_indexofC8($str1$$Register, $str2$$Register,
11205 $cnt1$$Register, $cnt2$$Register,
11206 icnt2, $result$$Register,
11207 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11208 } else {
11209 // Small strings are loaded through stack if they cross page boundary.
11210 __ string_indexof($str1$$Register, $str2$$Register,
11211 $cnt1$$Register, $cnt2$$Register,
11212 icnt2, $result$$Register,
11213 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11214 }
11215 %}
11216 ins_pipe( pipe_slow );
11217 %}
11218
11219 // fast search of substring with known size.
11220 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11221 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11222 %{
11223 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11224 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11225 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11226
11227 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11228 ins_encode %{
11229 int icnt2 = (int)$int_cnt2$$constant;
11230 if (icnt2 >= 8) {
11231 // IndexOf for constant substrings with size >= 8 elements
11232 // which don't need to be loaded through stack.
11233 __ string_indexofC8($str1$$Register, $str2$$Register,
11234 $cnt1$$Register, $cnt2$$Register,
11235 icnt2, $result$$Register,
11236 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11237 } else {
11238 // Small strings are loaded through stack if they cross page boundary.
11239 __ string_indexof($str1$$Register, $str2$$Register,
11240 $cnt1$$Register, $cnt2$$Register,
11241 icnt2, $result$$Register,
11242 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11243 }
11244 %}
11245 ins_pipe( pipe_slow );
11246 %}
11247
11248 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11249 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11250 %{
11251 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11252 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11253 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11254
11255 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11256 ins_encode %{
11257 __ string_indexof($str1$$Register, $str2$$Register,
11258 $cnt1$$Register, $cnt2$$Register,
11259 (-1), $result$$Register,
11260 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11261 %}
11262 ins_pipe( pipe_slow );
11263 %}
11264
11265 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11266 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11267 %{
11268 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11269 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11270 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11271
11272 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11273 ins_encode %{
11274 __ string_indexof($str1$$Register, $str2$$Register,
11275 $cnt1$$Register, $cnt2$$Register,
11276 (-1), $result$$Register,
11277 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11278 %}
11279 ins_pipe( pipe_slow );
11280 %}
11281
11282 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11283 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11284 %{
11285 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11286 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11287 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11288
11289 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11290 ins_encode %{
11291 __ string_indexof($str1$$Register, $str2$$Register,
11292 $cnt1$$Register, $cnt2$$Register,
11293 (-1), $result$$Register,
11294 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11295 %}
11296 ins_pipe( pipe_slow );
11297 %}
11298
11299 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11300 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
11301 %{
11302 predicate(UseSSE42Intrinsics);
11303 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11304 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11305 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11306 ins_encode %{
11307 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11308 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
11309 %}
11310 ins_pipe( pipe_slow );
11311 %}
11312
11313 // fast string equals
11314 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11315 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr)
11316 %{
11317 match(Set result (StrEquals (Binary str1 str2) cnt));
11318 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11319
11320 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11321 ins_encode %{
11322 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11323 $cnt$$Register, $result$$Register, $tmp3$$Register,
11324 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11325 %}
11326 ins_pipe( pipe_slow );
11327 %}
11328
11329 // fast array equals
11330 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11331 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11332 %{
11333 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11334 match(Set result (AryEq ary1 ary2));
11335 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11336
11337 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11338 ins_encode %{
11339 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11340 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11341 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11342 %}
11343 ins_pipe( pipe_slow );
11344 %}
11345
11346 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11347 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11348 %{
11349 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11350 match(Set result (AryEq ary1 ary2));
11351 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11352
11353 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11354 ins_encode %{
11355 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11356 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11357 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
11358 %}
11359 ins_pipe( pipe_slow );
11360 %}
11361
11362 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11363 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr)
11364 %{
11365 match(Set result (HasNegatives ary1 len));
11366 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11367
11368 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11369 ins_encode %{
11370 __ has_negatives($ary1$$Register, $len$$Register,
11371 $result$$Register, $tmp3$$Register,
11372 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11373 %}
11374 ins_pipe( pipe_slow );
11375 %}
11376
11377 // fast char[] to byte[] compression
11378 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
11379 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11380 match(Set result (StrCompressedCopy src (Binary dst len)));
11381 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11382
11383 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11384 ins_encode %{
11385 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11386 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11387 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11388 %}
11389 ins_pipe( pipe_slow );
11390 %}
11391
11392 // fast byte[] to char[] inflation
11393 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11394 legRegD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11395 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11396 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11397
11398 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11399 ins_encode %{
11400 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11401 $tmp1$$XMMRegister, $tmp2$$Register);
11402 %}
11403 ins_pipe( pipe_slow );
11404 %}
11405
11406 // encode char[] to byte[] in ISO_8859_1
11407 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11408 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
11409 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11410 match(Set result (EncodeISOArray src (Binary dst len)));
11411 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11412
11413 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11414 ins_encode %{
11415 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11416 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11417 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11418 %}
11419 ins_pipe( pipe_slow );
11420 %}
11421
11422 //----------Overflow Math Instructions-----------------------------------------
11423
11424 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11425 %{
11426 match(Set cr (OverflowAddI op1 op2));
11427 effect(DEF cr, USE_KILL op1, USE op2);
11428
11429 format %{ "addl $op1, $op2\t# overflow check int" %}
11430
11431 ins_encode %{
11432 __ addl($op1$$Register, $op2$$Register);
11433 %}
11434 ins_pipe(ialu_reg_reg);
11435 %}
11436
11437 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11438 %{
11439 match(Set cr (OverflowAddI op1 op2));
11440 effect(DEF cr, USE_KILL op1, USE op2);
11441
11442 format %{ "addl $op1, $op2\t# overflow check int" %}
11443
11444 ins_encode %{
11445 __ addl($op1$$Register, $op2$$constant);
11446 %}
11447 ins_pipe(ialu_reg_reg);
11448 %}
11449
11450 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11451 %{
11452 match(Set cr (OverflowAddL op1 op2));
11453 effect(DEF cr, USE_KILL op1, USE op2);
11454
11455 format %{ "addq $op1, $op2\t# overflow check long" %}
11456 ins_encode %{
11457 __ addq($op1$$Register, $op2$$Register);
11458 %}
11459 ins_pipe(ialu_reg_reg);
11460 %}
11461
11462 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11463 %{
11464 match(Set cr (OverflowAddL op1 op2));
11465 effect(DEF cr, USE_KILL op1, USE op2);
11466
11467 format %{ "addq $op1, $op2\t# overflow check long" %}
11468 ins_encode %{
11469 __ addq($op1$$Register, $op2$$constant);
11470 %}
11471 ins_pipe(ialu_reg_reg);
11472 %}
11473
11474 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11475 %{
11476 match(Set cr (OverflowSubI op1 op2));
11477
11478 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11479 ins_encode %{
11480 __ cmpl($op1$$Register, $op2$$Register);
11481 %}
11482 ins_pipe(ialu_reg_reg);
11483 %}
11484
11485 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11486 %{
11487 match(Set cr (OverflowSubI op1 op2));
11488
11489 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11490 ins_encode %{
11491 __ cmpl($op1$$Register, $op2$$constant);
11492 %}
11493 ins_pipe(ialu_reg_reg);
11494 %}
11495
11496 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11497 %{
11498 match(Set cr (OverflowSubL op1 op2));
11499
11500 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11501 ins_encode %{
11502 __ cmpq($op1$$Register, $op2$$Register);
11503 %}
11504 ins_pipe(ialu_reg_reg);
11505 %}
11506
11507 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11508 %{
11509 match(Set cr (OverflowSubL op1 op2));
11510
11511 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11512 ins_encode %{
11513 __ cmpq($op1$$Register, $op2$$constant);
11514 %}
11515 ins_pipe(ialu_reg_reg);
11516 %}
11517
11518 instruct overflowNegI_rReg(rFlagsReg cr, immI_0 zero, rax_RegI op2)
11519 %{
11520 match(Set cr (OverflowSubI zero op2));
11521 effect(DEF cr, USE_KILL op2);
11522
11523 format %{ "negl $op2\t# overflow check int" %}
11524 ins_encode %{
11525 __ negl($op2$$Register);
11526 %}
11527 ins_pipe(ialu_reg_reg);
11528 %}
11529
11530 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11531 %{
11532 match(Set cr (OverflowSubL zero op2));
11533 effect(DEF cr, USE_KILL op2);
11534
11535 format %{ "negq $op2\t# overflow check long" %}
11536 ins_encode %{
11537 __ negq($op2$$Register);
11538 %}
11539 ins_pipe(ialu_reg_reg);
11540 %}
11541
11542 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11543 %{
11544 match(Set cr (OverflowMulI op1 op2));
11545 effect(DEF cr, USE_KILL op1, USE op2);
11546
11547 format %{ "imull $op1, $op2\t# overflow check int" %}
11548 ins_encode %{
11549 __ imull($op1$$Register, $op2$$Register);
11550 %}
11551 ins_pipe(ialu_reg_reg_alu0);
11552 %}
11553
11554 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11555 %{
11556 match(Set cr (OverflowMulI op1 op2));
11557 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11558
11559 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11560 ins_encode %{
11561 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11562 %}
11563 ins_pipe(ialu_reg_reg_alu0);
11564 %}
11565
11566 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11567 %{
11568 match(Set cr (OverflowMulL op1 op2));
11569 effect(DEF cr, USE_KILL op1, USE op2);
11570
11571 format %{ "imulq $op1, $op2\t# overflow check long" %}
11572 ins_encode %{
11573 __ imulq($op1$$Register, $op2$$Register);
11574 %}
11575 ins_pipe(ialu_reg_reg_alu0);
11576 %}
11577
11578 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11579 %{
11580 match(Set cr (OverflowMulL op1 op2));
11581 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11582
11583 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11584 ins_encode %{
11585 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11586 %}
11587 ins_pipe(ialu_reg_reg_alu0);
11588 %}
11589
11590
11591 //----------Control Flow Instructions------------------------------------------
11592 // Signed compare Instructions
11593
11594 // XXX more variants!!
11595 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11596 %{
11597 match(Set cr (CmpI op1 op2));
11598 effect(DEF cr, USE op1, USE op2);
11599
11600 format %{ "cmpl $op1, $op2" %}
11601 opcode(0x3B); /* Opcode 3B /r */
11602 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11603 ins_pipe(ialu_cr_reg_reg);
11604 %}
11605
11606 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11607 %{
11608 match(Set cr (CmpI op1 op2));
11609
11610 format %{ "cmpl $op1, $op2" %}
11611 opcode(0x81, 0x07); /* Opcode 81 /7 */
11612 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11613 ins_pipe(ialu_cr_reg_imm);
11614 %}
11615
11616 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11617 %{
11618 match(Set cr (CmpI op1 (LoadI op2)));
11619
11620 ins_cost(500); // XXX
11621 format %{ "cmpl $op1, $op2" %}
11622 opcode(0x3B); /* Opcode 3B /r */
11623 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11624 ins_pipe(ialu_cr_reg_mem);
11625 %}
11626
11627 instruct testI_reg(rFlagsReg cr, rRegI src, immI_0 zero)
11628 %{
11629 match(Set cr (CmpI src zero));
11630
11631 format %{ "testl $src, $src" %}
11632 opcode(0x85);
11633 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11634 ins_pipe(ialu_cr_reg_imm);
11635 %}
11636
11637 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI_0 zero)
11638 %{
11639 match(Set cr (CmpI (AndI src con) zero));
11640
11641 format %{ "testl $src, $con" %}
11642 opcode(0xF7, 0x00);
11643 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11644 ins_pipe(ialu_cr_reg_imm);
11645 %}
11646
11647 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI_0 zero)
11648 %{
11649 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11650
11651 format %{ "testl $src, $mem" %}
11652 opcode(0x85);
11653 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11654 ins_pipe(ialu_cr_reg_mem);
11655 %}
11656
11657 // Unsigned compare Instructions; really, same as signed except they
11658 // produce an rFlagsRegU instead of rFlagsReg.
11659 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11660 %{
11661 match(Set cr (CmpU op1 op2));
11662
11663 format %{ "cmpl $op1, $op2\t# unsigned" %}
11664 opcode(0x3B); /* Opcode 3B /r */
11665 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11666 ins_pipe(ialu_cr_reg_reg);
11667 %}
11668
11669 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11670 %{
11671 match(Set cr (CmpU op1 op2));
11672
11673 format %{ "cmpl $op1, $op2\t# unsigned" %}
11674 opcode(0x81,0x07); /* Opcode 81 /7 */
11675 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11676 ins_pipe(ialu_cr_reg_imm);
11677 %}
11678
11679 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11680 %{
11681 match(Set cr (CmpU op1 (LoadI op2)));
11682
11683 ins_cost(500); // XXX
11684 format %{ "cmpl $op1, $op2\t# unsigned" %}
11685 opcode(0x3B); /* Opcode 3B /r */
11686 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11687 ins_pipe(ialu_cr_reg_mem);
11688 %}
11689
11690 // // // Cisc-spilled version of cmpU_rReg
11691 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11692 // //%{
11693 // // match(Set cr (CmpU (LoadI op1) op2));
11694 // //
11695 // // format %{ "CMPu $op1,$op2" %}
11696 // // ins_cost(500);
11697 // // opcode(0x39); /* Opcode 39 /r */
11698 // // ins_encode( OpcP, reg_mem( op1, op2) );
11699 // //%}
11700
11701 instruct testU_reg(rFlagsRegU cr, rRegI src, immI_0 zero)
11702 %{
11703 match(Set cr (CmpU src zero));
11704
11705 format %{ "testl $src, $src\t# unsigned" %}
11706 opcode(0x85);
11707 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11708 ins_pipe(ialu_cr_reg_imm);
11709 %}
11710
11711 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11712 %{
11713 match(Set cr (CmpP op1 op2));
11714
11715 format %{ "cmpq $op1, $op2\t# ptr" %}
11716 opcode(0x3B); /* Opcode 3B /r */
11717 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11718 ins_pipe(ialu_cr_reg_reg);
11719 %}
11720
11721 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11722 %{
11723 match(Set cr (CmpP op1 (LoadP op2)));
11724 predicate(n->in(2)->as_Load()->barrier_data() == 0);
11725
11726 ins_cost(500); // XXX
11727 format %{ "cmpq $op1, $op2\t# ptr" %}
11728 opcode(0x3B); /* Opcode 3B /r */
11729 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11730 ins_pipe(ialu_cr_reg_mem);
11731 %}
11732
11733 // // // Cisc-spilled version of cmpP_rReg
11734 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11735 // //%{
11736 // // match(Set cr (CmpP (LoadP op1) op2));
11737 // //
11738 // // format %{ "CMPu $op1,$op2" %}
11739 // // ins_cost(500);
11740 // // opcode(0x39); /* Opcode 39 /r */
11741 // // ins_encode( OpcP, reg_mem( op1, op2) );
11742 // //%}
11743
11744 // XXX this is generalized by compP_rReg_mem???
11745 // Compare raw pointer (used in out-of-heap check).
11746 // Only works because non-oop pointers must be raw pointers
11747 // and raw pointers have no anti-dependencies.
11748 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11749 %{
11750 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none &&
11751 n->in(2)->as_Load()->barrier_data() == 0);
11752 match(Set cr (CmpP op1 (LoadP op2)));
11753
11754 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11755 opcode(0x3B); /* Opcode 3B /r */
11756 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11757 ins_pipe(ialu_cr_reg_mem);
11758 %}
11759
11760 // This will generate a signed flags result. This should be OK since
11761 // any compare to a zero should be eq/neq.
11762 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11763 %{
11764 match(Set cr (CmpP src zero));
11765
11766 format %{ "testq $src, $src\t# ptr" %}
11767 opcode(0x85);
11768 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11769 ins_pipe(ialu_cr_reg_imm);
11770 %}
11771
11772 // This will generate a signed flags result. This should be OK since
11773 // any compare to a zero should be eq/neq.
11774 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11775 %{
11776 predicate((!UseCompressedOops || (CompressedOops::base() != NULL)) &&
11777 n->in(1)->as_Load()->barrier_data() == 0);
11778 match(Set cr (CmpP (LoadP op) zero));
11779
11780 ins_cost(500); // XXX
11781 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11782 opcode(0xF7); /* Opcode F7 /0 */
11783 ins_encode(REX_mem_wide(op),
11784 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11785 ins_pipe(ialu_cr_reg_imm);
11786 %}
11787
11788 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11789 %{
11790 predicate(UseCompressedOops && (CompressedOops::base() == NULL) &&
11791 (CompressedKlassPointers::base() == NULL) &&
11792 n->in(1)->as_Load()->barrier_data() == 0);
11793 match(Set cr (CmpP (LoadP mem) zero));
11794
11795 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11796 ins_encode %{
11797 __ cmpq(r12, $mem$$Address);
11798 %}
11799 ins_pipe(ialu_cr_reg_mem);
11800 %}
11801
11802 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11803 %{
11804 match(Set cr (CmpN op1 op2));
11805
11806 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11807 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11808 ins_pipe(ialu_cr_reg_reg);
11809 %}
11810
11811 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11812 %{
11813 match(Set cr (CmpN src (LoadN mem)));
11814
11815 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11816 ins_encode %{
11817 __ cmpl($src$$Register, $mem$$Address);
11818 %}
11819 ins_pipe(ialu_cr_reg_mem);
11820 %}
11821
11822 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11823 match(Set cr (CmpN op1 op2));
11824
11825 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11826 ins_encode %{
11827 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11828 %}
11829 ins_pipe(ialu_cr_reg_imm);
11830 %}
11831
11832 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11833 %{
11834 match(Set cr (CmpN src (LoadN mem)));
11835
11836 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11837 ins_encode %{
11838 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11839 %}
11840 ins_pipe(ialu_cr_reg_mem);
11841 %}
11842
11843 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11844 match(Set cr (CmpN op1 op2));
11845
11846 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11847 ins_encode %{
11848 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11849 %}
11850 ins_pipe(ialu_cr_reg_imm);
11851 %}
11852
11853 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11854 %{
11855 match(Set cr (CmpN src (LoadNKlass mem)));
11856
11857 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11858 ins_encode %{
11859 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11860 %}
11861 ins_pipe(ialu_cr_reg_mem);
11862 %}
11863
11864 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11865 match(Set cr (CmpN src zero));
11866
11867 format %{ "testl $src, $src\t# compressed ptr" %}
11868 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11869 ins_pipe(ialu_cr_reg_imm);
11870 %}
11871
11872 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11873 %{
11874 predicate(CompressedOops::base() != NULL);
11875 match(Set cr (CmpN (LoadN mem) zero));
11876
11877 ins_cost(500); // XXX
11878 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11879 ins_encode %{
11880 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11881 %}
11882 ins_pipe(ialu_cr_reg_mem);
11883 %}
11884
11885 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11886 %{
11887 predicate(CompressedOops::base() == NULL && (CompressedKlassPointers::base() == NULL));
11888 match(Set cr (CmpN (LoadN mem) zero));
11889
11890 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11891 ins_encode %{
11892 __ cmpl(r12, $mem$$Address);
11893 %}
11894 ins_pipe(ialu_cr_reg_mem);
11895 %}
11896
11897 // Yanked all unsigned pointer compare operations.
11898 // Pointer compares are done with CmpP which is already unsigned.
11899
11900 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11901 %{
11902 match(Set cr (CmpL op1 op2));
11903
11904 format %{ "cmpq $op1, $op2" %}
11905 opcode(0x3B); /* Opcode 3B /r */
11906 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11907 ins_pipe(ialu_cr_reg_reg);
11908 %}
11909
11910 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11911 %{
11912 match(Set cr (CmpL op1 op2));
11913
11914 format %{ "cmpq $op1, $op2" %}
11915 opcode(0x81, 0x07); /* Opcode 81 /7 */
11916 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11917 ins_pipe(ialu_cr_reg_imm);
11918 %}
11919
11920 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11921 %{
11922 match(Set cr (CmpL op1 (LoadL op2)));
11923
11924 format %{ "cmpq $op1, $op2" %}
11925 opcode(0x3B); /* Opcode 3B /r */
11926 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11927 ins_pipe(ialu_cr_reg_mem);
11928 %}
11929
11930 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11931 %{
11932 match(Set cr (CmpL src zero));
11933
11934 format %{ "testq $src, $src" %}
11935 opcode(0x85);
11936 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11937 ins_pipe(ialu_cr_reg_imm);
11938 %}
11939
11940 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11941 %{
11942 match(Set cr (CmpL (AndL src con) zero));
11943
11944 format %{ "testq $src, $con\t# long" %}
11945 opcode(0xF7, 0x00);
11946 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11947 ins_pipe(ialu_cr_reg_imm);
11948 %}
11949
11950 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11951 %{
11952 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11953
11954 format %{ "testq $src, $mem" %}
11955 opcode(0x85);
11956 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11957 ins_pipe(ialu_cr_reg_mem);
11958 %}
11959
11960 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
11961 %{
11962 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
11963
11964 format %{ "testq $src, $mem" %}
11965 opcode(0x85);
11966 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11967 ins_pipe(ialu_cr_reg_mem);
11968 %}
11969
11970 // Manifest a CmpL result in an integer register. Very painful.
11971 // This is the test to avoid.
11972 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11973 %{
11974 match(Set dst (CmpL3 src1 src2));
11975 effect(KILL flags);
11976
11977 ins_cost(275); // XXX
11978 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11979 "movl $dst, -1\n\t"
11980 "jl,s done\n\t"
11981 "setne $dst\n\t"
11982 "movzbl $dst, $dst\n\t"
11983 "done:" %}
11984 ins_encode(cmpl3_flag(src1, src2, dst));
11985 ins_pipe(pipe_slow);
11986 %}
11987
11988 // Unsigned long compare Instructions; really, same as signed long except they
11989 // produce an rFlagsRegU instead of rFlagsReg.
11990 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
11991 %{
11992 match(Set cr (CmpUL op1 op2));
11993
11994 format %{ "cmpq $op1, $op2\t# unsigned" %}
11995 opcode(0x3B); /* Opcode 3B /r */
11996 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11997 ins_pipe(ialu_cr_reg_reg);
11998 %}
11999
12000 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
12001 %{
12002 match(Set cr (CmpUL op1 op2));
12003
12004 format %{ "cmpq $op1, $op2\t# unsigned" %}
12005 opcode(0x81, 0x07); /* Opcode 81 /7 */
12006 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
12007 ins_pipe(ialu_cr_reg_imm);
12008 %}
12009
12010 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
12011 %{
12012 match(Set cr (CmpUL op1 (LoadL op2)));
12013
12014 format %{ "cmpq $op1, $op2\t# unsigned" %}
12015 opcode(0x3B); /* Opcode 3B /r */
12016 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
12017 ins_pipe(ialu_cr_reg_mem);
12018 %}
12019
12020 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
12021 %{
12022 match(Set cr (CmpUL src zero));
12023
12024 format %{ "testq $src, $src\t# unsigned" %}
12025 opcode(0x85);
12026 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12027 ins_pipe(ialu_cr_reg_imm);
12028 %}
12029
12030 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12031 %{
12032 match(Set cr (CmpI (LoadB mem) imm));
12033
12034 ins_cost(125);
12035 format %{ "cmpb $mem, $imm" %}
12036 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12037 ins_pipe(ialu_cr_reg_mem);
12038 %}
12039
12040 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI_0 zero)
12041 %{
12042 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12043
12044 ins_cost(125);
12045 format %{ "testb $mem, $imm\t# ubyte" %}
12046 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12047 ins_pipe(ialu_cr_reg_mem);
12048 %}
12049
12050 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero)
12051 %{
12052 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12053
12054 ins_cost(125);
12055 format %{ "testb $mem, $imm\t# byte" %}
12056 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12057 ins_pipe(ialu_cr_reg_mem);
12058 %}
12059
12060 //----------Max and Min--------------------------------------------------------
12061 // Min Instructions
12062
12063 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12064 %{
12065 effect(USE_DEF dst, USE src, USE cr);
12066
12067 format %{ "cmovlgt $dst, $src\t# min" %}
12068 opcode(0x0F, 0x4F);
12069 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12070 ins_pipe(pipe_cmov_reg);
12071 %}
12072
12073
12074 instruct minI_rReg(rRegI dst, rRegI src)
12075 %{
12076 match(Set dst (MinI dst src));
12077
12078 ins_cost(200);
12079 expand %{
12080 rFlagsReg cr;
12081 compI_rReg(cr, dst, src);
12082 cmovI_reg_g(dst, src, cr);
12083 %}
12084 %}
12085
12086 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12087 %{
12088 effect(USE_DEF dst, USE src, USE cr);
12089
12090 format %{ "cmovllt $dst, $src\t# max" %}
12091 opcode(0x0F, 0x4C);
12092 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12093 ins_pipe(pipe_cmov_reg);
12094 %}
12095
12096
12097 instruct maxI_rReg(rRegI dst, rRegI src)
12098 %{
12099 match(Set dst (MaxI dst src));
12100
12101 ins_cost(200);
12102 expand %{
12103 rFlagsReg cr;
12104 compI_rReg(cr, dst, src);
12105 cmovI_reg_l(dst, src, cr);
12106 %}
12107 %}
12108
12109 // ============================================================================
12110 // Branch Instructions
12111
12112 // Jump Direct - Label defines a relative address from JMP+1
12113 instruct jmpDir(label labl)
12114 %{
12115 match(Goto);
12116 effect(USE labl);
12117
12118 ins_cost(300);
12119 format %{ "jmp $labl" %}
12120 size(5);
12121 ins_encode %{
12122 Label* L = $labl$$label;
12123 __ jmp(*L, false); // Always long jump
12124 %}
12125 ins_pipe(pipe_jmp);
12126 %}
12127
12128 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12129 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12130 %{
12131 match(If cop cr);
12132 effect(USE labl);
12133
12134 ins_cost(300);
12135 format %{ "j$cop $labl" %}
12136 size(6);
12137 ins_encode %{
12138 Label* L = $labl$$label;
12139 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12140 %}
12141 ins_pipe(pipe_jcc);
12142 %}
12143
12144 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12145 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12146 %{
12147 predicate(!n->has_vector_mask_set());
12148 match(CountedLoopEnd cop cr);
12149 effect(USE labl);
12150
12151 ins_cost(300);
12152 format %{ "j$cop $labl\t# loop end" %}
12153 size(6);
12154 ins_encode %{
12155 Label* L = $labl$$label;
12156 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12157 %}
12158 ins_pipe(pipe_jcc);
12159 %}
12160
12161 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12162 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12163 predicate(!n->has_vector_mask_set());
12164 match(CountedLoopEnd cop cmp);
12165 effect(USE labl);
12166
12167 ins_cost(300);
12168 format %{ "j$cop,u $labl\t# loop end" %}
12169 size(6);
12170 ins_encode %{
12171 Label* L = $labl$$label;
12172 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12173 %}
12174 ins_pipe(pipe_jcc);
12175 %}
12176
12177 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12178 predicate(!n->has_vector_mask_set());
12179 match(CountedLoopEnd cop cmp);
12180 effect(USE labl);
12181
12182 ins_cost(200);
12183 format %{ "j$cop,u $labl\t# loop end" %}
12184 size(6);
12185 ins_encode %{
12186 Label* L = $labl$$label;
12187 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12188 %}
12189 ins_pipe(pipe_jcc);
12190 %}
12191
12192 // mask version
12193 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12194 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
12195 %{
12196 predicate(n->has_vector_mask_set());
12197 match(CountedLoopEnd cop cr);
12198 effect(USE labl);
12199
12200 ins_cost(400);
12201 format %{ "j$cop $labl\t# loop end\n\t"
12202 "restorevectmask \t# vector mask restore for loops" %}
12203 size(10);
12204 ins_encode %{
12205 Label* L = $labl$$label;
12206 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12207 __ restorevectmask();
12208 %}
12209 ins_pipe(pipe_jcc);
12210 %}
12211
12212 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12213 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12214 predicate(n->has_vector_mask_set());
12215 match(CountedLoopEnd cop cmp);
12216 effect(USE labl);
12217
12218 ins_cost(400);
12219 format %{ "j$cop,u $labl\t# loop end\n\t"
12220 "restorevectmask \t# vector mask restore for loops" %}
12221 size(10);
12222 ins_encode %{
12223 Label* L = $labl$$label;
12224 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12225 __ restorevectmask();
12226 %}
12227 ins_pipe(pipe_jcc);
12228 %}
12229
12230 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12231 predicate(n->has_vector_mask_set());
12232 match(CountedLoopEnd cop cmp);
12233 effect(USE labl);
12234
12235 ins_cost(300);
12236 format %{ "j$cop,u $labl\t# loop end\n\t"
12237 "restorevectmask \t# vector mask restore for loops" %}
12238 size(10);
12239 ins_encode %{
12240 Label* L = $labl$$label;
12241 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12242 __ restorevectmask();
12243 %}
12244 ins_pipe(pipe_jcc);
12245 %}
12246
12247 // Jump Direct Conditional - using unsigned comparison
12248 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12249 match(If cop cmp);
12250 effect(USE labl);
12251
12252 ins_cost(300);
12253 format %{ "j$cop,u $labl" %}
12254 size(6);
12255 ins_encode %{
12256 Label* L = $labl$$label;
12257 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12258 %}
12259 ins_pipe(pipe_jcc);
12260 %}
12261
12262 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12263 match(If cop cmp);
12264 effect(USE labl);
12265
12266 ins_cost(200);
12267 format %{ "j$cop,u $labl" %}
12268 size(6);
12269 ins_encode %{
12270 Label* L = $labl$$label;
12271 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12272 %}
12273 ins_pipe(pipe_jcc);
12274 %}
12275
12276 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12277 match(If cop cmp);
12278 effect(USE labl);
12279
12280 ins_cost(200);
12281 format %{ $$template
12282 if ($cop$$cmpcode == Assembler::notEqual) {
12283 $$emit$$"jp,u $labl\n\t"
12284 $$emit$$"j$cop,u $labl"
12285 } else {
12286 $$emit$$"jp,u done\n\t"
12287 $$emit$$"j$cop,u $labl\n\t"
12288 $$emit$$"done:"
12289 }
12290 %}
12291 ins_encode %{
12292 Label* l = $labl$$label;
12293 if ($cop$$cmpcode == Assembler::notEqual) {
12294 __ jcc(Assembler::parity, *l, false);
12295 __ jcc(Assembler::notEqual, *l, false);
12296 } else if ($cop$$cmpcode == Assembler::equal) {
12297 Label done;
12298 __ jccb(Assembler::parity, done);
12299 __ jcc(Assembler::equal, *l, false);
12300 __ bind(done);
12301 } else {
12302 ShouldNotReachHere();
12303 }
12304 %}
12305 ins_pipe(pipe_jcc);
12306 %}
12307
12308 // ============================================================================
12309 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12310 // superklass array for an instance of the superklass. Set a hidden
12311 // internal cache on a hit (cache is checked with exposed code in
12312 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12313 // encoding ALSO sets flags.
12314
12315 instruct partialSubtypeCheck(rdi_RegP result,
12316 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12317 rFlagsReg cr)
12318 %{
12319 match(Set result (PartialSubtypeCheck sub super));
12320 effect(KILL rcx, KILL cr);
12321
12322 ins_cost(1100); // slightly larger than the next version
12323 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12324 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12325 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12326 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12327 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12328 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12329 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12330 "miss:\t" %}
12331
12332 opcode(0x1); // Force a XOR of RDI
12333 ins_encode(enc_PartialSubtypeCheck());
12334 ins_pipe(pipe_slow);
12335 %}
12336
12337 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12338 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12339 immP0 zero,
12340 rdi_RegP result)
12341 %{
12342 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12343 effect(KILL rcx, KILL result);
12344
12345 ins_cost(1000);
12346 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12347 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12348 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12349 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12350 "jne,s miss\t\t# Missed: flags nz\n\t"
12351 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12352 "miss:\t" %}
12353
12354 opcode(0x0); // No need to XOR RDI
12355 ins_encode(enc_PartialSubtypeCheck());
12356 ins_pipe(pipe_slow);
12357 %}
12358
12359 // ============================================================================
12360 // Branch Instructions -- short offset versions
12361 //
12362 // These instructions are used to replace jumps of a long offset (the default
12363 // match) with jumps of a shorter offset. These instructions are all tagged
12364 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12365 // match rules in general matching. Instead, the ADLC generates a conversion
12366 // method in the MachNode which can be used to do in-place replacement of the
12367 // long variant with the shorter variant. The compiler will determine if a
12368 // branch can be taken by the is_short_branch_offset() predicate in the machine
12369 // specific code section of the file.
12370
12371 // Jump Direct - Label defines a relative address from JMP+1
12372 instruct jmpDir_short(label labl) %{
12373 match(Goto);
12374 effect(USE labl);
12375
12376 ins_cost(300);
12377 format %{ "jmp,s $labl" %}
12378 size(2);
12379 ins_encode %{
12380 Label* L = $labl$$label;
12381 __ jmpb(*L);
12382 %}
12383 ins_pipe(pipe_jmp);
12384 ins_short_branch(1);
12385 %}
12386
12387 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12388 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12389 match(If cop cr);
12390 effect(USE labl);
12391
12392 ins_cost(300);
12393 format %{ "j$cop,s $labl" %}
12394 size(2);
12395 ins_encode %{
12396 Label* L = $labl$$label;
12397 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12398 %}
12399 ins_pipe(pipe_jcc);
12400 ins_short_branch(1);
12401 %}
12402
12403 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12404 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12405 match(CountedLoopEnd cop cr);
12406 effect(USE labl);
12407
12408 ins_cost(300);
12409 format %{ "j$cop,s $labl\t# loop end" %}
12410 size(2);
12411 ins_encode %{
12412 Label* L = $labl$$label;
12413 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12414 %}
12415 ins_pipe(pipe_jcc);
12416 ins_short_branch(1);
12417 %}
12418
12419 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12420 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12421 match(CountedLoopEnd cop cmp);
12422 effect(USE labl);
12423
12424 ins_cost(300);
12425 format %{ "j$cop,us $labl\t# loop end" %}
12426 size(2);
12427 ins_encode %{
12428 Label* L = $labl$$label;
12429 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12430 %}
12431 ins_pipe(pipe_jcc);
12432 ins_short_branch(1);
12433 %}
12434
12435 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12436 match(CountedLoopEnd cop cmp);
12437 effect(USE labl);
12438
12439 ins_cost(300);
12440 format %{ "j$cop,us $labl\t# loop end" %}
12441 size(2);
12442 ins_encode %{
12443 Label* L = $labl$$label;
12444 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12445 %}
12446 ins_pipe(pipe_jcc);
12447 ins_short_branch(1);
12448 %}
12449
12450 // Jump Direct Conditional - using unsigned comparison
12451 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12452 match(If cop cmp);
12453 effect(USE labl);
12454
12455 ins_cost(300);
12456 format %{ "j$cop,us $labl" %}
12457 size(2);
12458 ins_encode %{
12459 Label* L = $labl$$label;
12460 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12461 %}
12462 ins_pipe(pipe_jcc);
12463 ins_short_branch(1);
12464 %}
12465
12466 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12467 match(If cop cmp);
12468 effect(USE labl);
12469
12470 ins_cost(300);
12471 format %{ "j$cop,us $labl" %}
12472 size(2);
12473 ins_encode %{
12474 Label* L = $labl$$label;
12475 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12476 %}
12477 ins_pipe(pipe_jcc);
12478 ins_short_branch(1);
12479 %}
12480
12481 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12482 match(If cop cmp);
12483 effect(USE labl);
12484
12485 ins_cost(300);
12486 format %{ $$template
12487 if ($cop$$cmpcode == Assembler::notEqual) {
12488 $$emit$$"jp,u,s $labl\n\t"
12489 $$emit$$"j$cop,u,s $labl"
12490 } else {
12491 $$emit$$"jp,u,s done\n\t"
12492 $$emit$$"j$cop,u,s $labl\n\t"
12493 $$emit$$"done:"
12494 }
12495 %}
12496 size(4);
12497 ins_encode %{
12498 Label* l = $labl$$label;
12499 if ($cop$$cmpcode == Assembler::notEqual) {
12500 __ jccb(Assembler::parity, *l);
12501 __ jccb(Assembler::notEqual, *l);
12502 } else if ($cop$$cmpcode == Assembler::equal) {
12503 Label done;
12504 __ jccb(Assembler::parity, done);
12505 __ jccb(Assembler::equal, *l);
12506 __ bind(done);
12507 } else {
12508 ShouldNotReachHere();
12509 }
12510 %}
12511 ins_pipe(pipe_jcc);
12512 ins_short_branch(1);
12513 %}
12514
12515 // ============================================================================
12516 // inlined locking and unlocking
12517
12518 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12519 predicate(Compile::current()->use_rtm());
12520 match(Set cr (FastLock object box));
12521 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12522 ins_cost(300);
12523 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12524 ins_encode %{
12525 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12526 $scr$$Register, $cx1$$Register, $cx2$$Register,
12527 _counters, _rtm_counters, _stack_rtm_counters,
12528 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12529 true, ra_->C->profile_rtm());
12530 %}
12531 ins_pipe(pipe_slow);
12532 %}
12533
12534 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12535 predicate(!Compile::current()->use_rtm());
12536 match(Set cr (FastLock object box));
12537 effect(TEMP tmp, TEMP scr, USE_KILL box);
12538 ins_cost(300);
12539 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12540 ins_encode %{
12541 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12542 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12543 %}
12544 ins_pipe(pipe_slow);
12545 %}
12546
12547 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12548 match(Set cr (FastUnlock object box));
12549 effect(TEMP tmp, USE_KILL box);
12550 ins_cost(300);
12551 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12552 ins_encode %{
12553 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12554 %}
12555 ins_pipe(pipe_slow);
12556 %}
12557
12558
12559 // ============================================================================
12560 // Safepoint Instructions
12561 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12562 %{
12563 match(SafePoint poll);
12564 effect(KILL cr, USE poll);
12565
12566 format %{ "testl rax, [$poll]\t"
12567 "# Safepoint: poll for GC" %}
12568 ins_cost(125);
12569 size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12570 ins_encode %{
12571 __ relocate(relocInfo::poll_type);
12572 address pre_pc = __ pc();
12573 __ testl(rax, Address($poll$$Register, 0));
12574 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
12575 %}
12576 ins_pipe(ialu_reg_mem);
12577 %}
12578
12579 // ============================================================================
12580 // Procedure Call/Return Instructions
12581 // Call Java Static Instruction
12582 // Note: If this code changes, the corresponding ret_addr_offset() and
12583 // compute_padding() functions will have to be adjusted.
12584 instruct CallStaticJavaDirect(method meth) %{
12585 match(CallStaticJava);
12586 effect(USE meth);
12587
12588 ins_cost(300);
12589 format %{ "call,static " %}
12590 opcode(0xE8); /* E8 cd */
12591 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12592 ins_pipe(pipe_slow);
12593 ins_alignment(4);
12594 %}
12595
12596 // Call Java Dynamic Instruction
12597 // Note: If this code changes, the corresponding ret_addr_offset() and
12598 // compute_padding() functions will have to be adjusted.
12599 instruct CallDynamicJavaDirect(method meth)
12600 %{
12601 match(CallDynamicJava);
12602 effect(USE meth);
12603
12604 ins_cost(300);
12605 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12606 "call,dynamic " %}
12607 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12608 ins_pipe(pipe_slow);
12609 ins_alignment(4);
12610 %}
12611
12612 // Call Runtime Instruction
12613 instruct CallRuntimeDirect(method meth)
12614 %{
12615 match(CallRuntime);
12616 effect(USE meth);
12617
12618 ins_cost(300);
12619 format %{ "call,runtime " %}
12620 ins_encode(clear_avx, Java_To_Runtime(meth));
12621 ins_pipe(pipe_slow);
12622 %}
12623
12624 // Call runtime without safepoint
12625 instruct CallLeafDirect(method meth)
12626 %{
12627 match(CallLeaf);
12628 effect(USE meth);
12629
12630 ins_cost(300);
12631 format %{ "call_leaf,runtime " %}
12632 ins_encode(clear_avx, Java_To_Runtime(meth));
12633 ins_pipe(pipe_slow);
12634 %}
12635
12636 // Call runtime without safepoint
12637 instruct CallLeafNoFPDirect(method meth)
12638 %{
12639 match(CallLeafNoFP);
12640 effect(USE meth);
12641
12642 ins_cost(300);
12643 format %{ "call_leaf_nofp,runtime " %}
12644 ins_encode(clear_avx, Java_To_Runtime(meth));
12645 ins_pipe(pipe_slow);
12646 %}
12647
12648 // Return Instruction
12649 // Remove the return address & jump to it.
12650 // Notice: We always emit a nop after a ret to make sure there is room
12651 // for safepoint patching
12652 instruct Ret()
12653 %{
12654 match(Return);
12655
12656 format %{ "ret" %}
12657 opcode(0xC3);
12658 ins_encode(OpcP);
12659 ins_pipe(pipe_jmp);
12660 %}
12661
12662 // Tail Call; Jump from runtime stub to Java code.
12663 // Also known as an 'interprocedural jump'.
12664 // Target of jump will eventually return to caller.
12665 // TailJump below removes the return address.
12666 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12667 %{
12668 match(TailCall jump_target method_oop);
12669
12670 ins_cost(300);
12671 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12672 opcode(0xFF, 0x4); /* Opcode FF /4 */
12673 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12674 ins_pipe(pipe_jmp);
12675 %}
12676
12677 // Tail Jump; remove the return address; jump to target.
12678 // TailCall above leaves the return address around.
12679 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12680 %{
12681 match(TailJump jump_target ex_oop);
12682
12683 ins_cost(300);
12684 format %{ "popq rdx\t# pop return address\n\t"
12685 "jmp $jump_target" %}
12686 opcode(0xFF, 0x4); /* Opcode FF /4 */
12687 ins_encode(Opcode(0x5a), // popq rdx
12688 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12689 ins_pipe(pipe_jmp);
12690 %}
12691
12692 // Create exception oop: created by stack-crawling runtime code.
12693 // Created exception is now available to this handler, and is setup
12694 // just prior to jumping to this handler. No code emitted.
12695 instruct CreateException(rax_RegP ex_oop)
12696 %{
12697 match(Set ex_oop (CreateEx));
12698
12699 size(0);
12700 // use the following format syntax
12701 format %{ "# exception oop is in rax; no code emitted" %}
12702 ins_encode();
12703 ins_pipe(empty);
12704 %}
12705
12706 // Rethrow exception:
12707 // The exception oop will come in the first argument position.
12708 // Then JUMP (not call) to the rethrow stub code.
12709 instruct RethrowException()
12710 %{
12711 match(Rethrow);
12712
12713 // use the following format syntax
12714 format %{ "jmp rethrow_stub" %}
12715 ins_encode(enc_rethrow);
12716 ins_pipe(pipe_jmp);
12717 %}
12718
12719 // ============================================================================
12720 // This name is KNOWN by the ADLC and cannot be changed.
12721 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12722 // for this guy.
12723 instruct tlsLoadP(r15_RegP dst) %{
12724 match(Set dst (ThreadLocal));
12725 effect(DEF dst);
12726
12727 size(0);
12728 format %{ "# TLS is in R15" %}
12729 ins_encode( /*empty encoding*/ );
12730 ins_pipe(ialu_reg_reg);
12731 %}
12732
12733
12734 //----------PEEPHOLE RULES-----------------------------------------------------
12735 // These must follow all instruction definitions as they use the names
12736 // defined in the instructions definitions.
12737 //
12738 // peepmatch ( root_instr_name [preceding_instruction]* );
12739 //
12740 // peepconstraint %{
12741 // (instruction_number.operand_name relational_op instruction_number.operand_name
12742 // [, ...] );
12743 // // instruction numbers are zero-based using left to right order in peepmatch
12744 //
12745 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12746 // // provide an instruction_number.operand_name for each operand that appears
12747 // // in the replacement instruction's match rule
12748 //
12749 // ---------VM FLAGS---------------------------------------------------------
12750 //
12751 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12752 //
12753 // Each peephole rule is given an identifying number starting with zero and
12754 // increasing by one in the order seen by the parser. An individual peephole
12755 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12756 // on the command-line.
12757 //
12758 // ---------CURRENT LIMITATIONS----------------------------------------------
12759 //
12760 // Only match adjacent instructions in same basic block
12761 // Only equality constraints
12762 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12763 // Only one replacement instruction
12764 //
12765 // ---------EXAMPLE----------------------------------------------------------
12766 //
12767 // // pertinent parts of existing instructions in architecture description
12768 // instruct movI(rRegI dst, rRegI src)
12769 // %{
12770 // match(Set dst (CopyI src));
12771 // %}
12772 //
12773 // instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
12774 // %{
12775 // match(Set dst (AddI dst src));
12776 // effect(KILL cr);
12777 // %}
12778 //
12779 // // Change (inc mov) to lea
12780 // peephole %{
12781 // // increment preceeded by register-register move
12782 // peepmatch ( incI_rReg movI );
12783 // // require that the destination register of the increment
12784 // // match the destination register of the move
12785 // peepconstraint ( 0.dst == 1.dst );
12786 // // construct a replacement instruction that sets
12787 // // the destination to ( move's source register + one )
12788 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12789 // %}
12790 //
12791
12792 // Implementation no longer uses movX instructions since
12793 // machine-independent system no longer uses CopyX nodes.
12794 //
12795 // peephole
12796 // %{
12797 // peepmatch (incI_rReg movI);
12798 // peepconstraint (0.dst == 1.dst);
12799 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12800 // %}
12801
12802 // peephole
12803 // %{
12804 // peepmatch (decI_rReg movI);
12805 // peepconstraint (0.dst == 1.dst);
12806 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12807 // %}
12808
12809 // peephole
12810 // %{
12811 // peepmatch (addI_rReg_imm movI);
12812 // peepconstraint (0.dst == 1.dst);
12813 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12814 // %}
12815
12816 // peephole
12817 // %{
12818 // peepmatch (incL_rReg movL);
12819 // peepconstraint (0.dst == 1.dst);
12820 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12821 // %}
12822
12823 // peephole
12824 // %{
12825 // peepmatch (decL_rReg movL);
12826 // peepconstraint (0.dst == 1.dst);
12827 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12828 // %}
12829
12830 // peephole
12831 // %{
12832 // peepmatch (addL_rReg_imm movL);
12833 // peepconstraint (0.dst == 1.dst);
12834 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12835 // %}
12836
12837 // peephole
12838 // %{
12839 // peepmatch (addP_rReg_imm movP);
12840 // peepconstraint (0.dst == 1.dst);
12841 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12842 // %}
12843
12844 // // Change load of spilled value to only a spill
12845 // instruct storeI(memory mem, rRegI src)
12846 // %{
12847 // match(Set mem (StoreI mem src));
12848 // %}
12849 //
12850 // instruct loadI(rRegI dst, memory mem)
12851 // %{
12852 // match(Set dst (LoadI mem));
12853 // %}
12854 //
12855
12856 peephole
12857 %{
12858 peepmatch (loadI storeI);
12859 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12860 peepreplace (storeI(1.mem 1.mem 1.src));
12861 %}
12862
12863 peephole
12864 %{
12865 peepmatch (loadL storeL);
12866 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12867 peepreplace (storeL(1.mem 1.mem 1.src));
12868 %}
12869
12870 //----------SMARTSPILL RULES---------------------------------------------------
12871 // These must follow all instruction definitions as they use the names
12872 // defined in the instructions definitions.