1 //
   2 // Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
   3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4 //
   5 // This code is free software; you can redistribute it and/or modify it
   6 // under the terms of the GNU General Public License version 2 only, as
   7 // published by the Free Software Foundation.
   8 //
   9 // This code is distributed in the hope that it will be useful, but WITHOUT
  10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12 // version 2 for more details (a copy is included in the LICENSE file that
  13 // accompanied this code).
  14 //
  15 // You should have received a copy of the GNU General Public License version
  16 // 2 along with this work; if not, write to the Free Software Foundation,
  17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18 //
  19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20 // or visit www.oracle.com if you need additional information or have any
  21 // questions.
  22 //
  23 //
  24 
  25 // AMD64 Architecture Description File
  26 
  27 //----------REGISTER DEFINITION BLOCK------------------------------------------
  28 // This information is used by the matcher and the register allocator to
  29 // describe individual registers and classes of registers within the target
  30 // archtecture.
  31 
  32 register %{
  33 //----------Architecture Description Register Definitions----------------------
  34 // General Registers
  35 // "reg_def"  name ( register save type, C convention save type,
  36 //                   ideal register type, encoding );
  37 // Register Save Types:
  38 //
  39 // NS  = No-Save:       The register allocator assumes that these registers
  40 //                      can be used without saving upon entry to the method, &
  41 //                      that they do not need to be saved at call sites.
  42 //
  43 // SOC = Save-On-Call:  The register allocator assumes that these registers
  44 //                      can be used without saving upon entry to the method,
  45 //                      but that they must be saved at call sites.
  46 //
  47 // SOE = Save-On-Entry: The register allocator assumes that these registers
  48 //                      must be saved before using them upon entry to the
  49 //                      method, but they do not need to be saved at call
  50 //                      sites.
  51 //
  52 // AS  = Always-Save:   The register allocator assumes that these registers
  53 //                      must be saved before using them upon entry to the
  54 //                      method, & that they must be saved at call sites.
  55 //
  56 // Ideal Register Type is used to determine how to save & restore a
  57 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  58 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
  59 //
  60 // The encoding number is the actual bit-pattern placed into the opcodes.
  61 
  62 // General Registers
  63 // R8-R15 must be encoded with REX.  (RSP, RBP, RSI, RDI need REX when
  64 // used as byte registers)
  65 
  66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
  67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
  68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
  69 
  70 reg_def RAX  (SOC, SOC, Op_RegI,  0, rax->as_VMReg());
  71 reg_def RAX_H(SOC, SOC, Op_RegI,  0, rax->as_VMReg()->next());
  72 
  73 reg_def RCX  (SOC, SOC, Op_RegI,  1, rcx->as_VMReg());
  74 reg_def RCX_H(SOC, SOC, Op_RegI,  1, rcx->as_VMReg()->next());
  75 
  76 reg_def RDX  (SOC, SOC, Op_RegI,  2, rdx->as_VMReg());
  77 reg_def RDX_H(SOC, SOC, Op_RegI,  2, rdx->as_VMReg()->next());
  78 
  79 reg_def RBX  (SOC, SOE, Op_RegI,  3, rbx->as_VMReg());
  80 reg_def RBX_H(SOC, SOE, Op_RegI,  3, rbx->as_VMReg()->next());
  81 
  82 reg_def RSP  (NS,  NS,  Op_RegI,  4, rsp->as_VMReg());
  83 reg_def RSP_H(NS,  NS,  Op_RegI,  4, rsp->as_VMReg()->next());
  84 
  85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
  86 reg_def RBP  (NS, SOE, Op_RegI,  5, rbp->as_VMReg());
  87 reg_def RBP_H(NS, SOE, Op_RegI,  5, rbp->as_VMReg()->next());
  88 
  89 #ifdef _WIN64
  90 
  91 reg_def RSI  (SOC, SOE, Op_RegI,  6, rsi->as_VMReg());
  92 reg_def RSI_H(SOC, SOE, Op_RegI,  6, rsi->as_VMReg()->next());
  93 
  94 reg_def RDI  (SOC, SOE, Op_RegI,  7, rdi->as_VMReg());
  95 reg_def RDI_H(SOC, SOE, Op_RegI,  7, rdi->as_VMReg()->next());
  96 
  97 #else
  98 
  99 reg_def RSI  (SOC, SOC, Op_RegI,  6, rsi->as_VMReg());
 100 reg_def RSI_H(SOC, SOC, Op_RegI,  6, rsi->as_VMReg()->next());
 101 
 102 reg_def RDI  (SOC, SOC, Op_RegI,  7, rdi->as_VMReg());
 103 reg_def RDI_H(SOC, SOC, Op_RegI,  7, rdi->as_VMReg()->next());
 104 
 105 #endif
 106 
 107 reg_def R8   (SOC, SOC, Op_RegI,  8, r8->as_VMReg());
 108 reg_def R8_H (SOC, SOC, Op_RegI,  8, r8->as_VMReg()->next());
 109 
 110 reg_def R9   (SOC, SOC, Op_RegI,  9, r9->as_VMReg());
 111 reg_def R9_H (SOC, SOC, Op_RegI,  9, r9->as_VMReg()->next());
 112 
 113 reg_def R10  (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
 115 
 116 reg_def R11  (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
 118 
 119 reg_def R12  (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
 121 
 122 reg_def R13  (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
 124 
 125 reg_def R14  (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
 127 
 128 reg_def R15  (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
 130 
 131 
 132 // Floating Point Registers
 133 
 134 // Specify priority of register selection within phases of register
 135 // allocation.  Highest priority is first.  A useful heuristic is to
 136 // give registers a low priority when they are required by machine
 137 // instructions, like EAX and EDX on I486, and choose no-save registers
 138 // before save-on-call, & save-on-call before save-on-entry.  Registers
 139 // which participate in fixed calling sequences should come last.
 140 // Registers which are used as pairs must fall on an even boundary.
 141 
 142 alloc_class chunk0(R10,         R10_H,
 143                    R11,         R11_H,
 144                    R8,          R8_H,
 145                    R9,          R9_H,
 146                    R12,         R12_H,
 147                    RCX,         RCX_H,
 148                    RBX,         RBX_H,
 149                    RDI,         RDI_H,
 150                    RDX,         RDX_H,
 151                    RSI,         RSI_H,
 152                    RAX,         RAX_H,
 153                    RBP,         RBP_H,
 154                    R13,         R13_H,
 155                    R14,         R14_H,
 156                    R15,         R15_H,
 157                    RSP,         RSP_H);
 158 
 159 
 160 //----------Architecture Description Register Classes--------------------------
 161 // Several register classes are automatically defined based upon information in
 162 // this architecture description.
 163 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
 164 // 2) reg_class compiler_method_oop_reg    ( /* as def'd in frame section */ )
 165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
 166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 167 //
 168 
 169 // Empty register class.
 170 reg_class no_reg();
 171 
 172 // Class for all pointer/long registers
 173 reg_class all_reg(RAX, RAX_H,
 174                   RDX, RDX_H,
 175                   RBP, RBP_H,
 176                   RDI, RDI_H,
 177                   RSI, RSI_H,
 178                   RCX, RCX_H,
 179                   RBX, RBX_H,
 180                   RSP, RSP_H,
 181                   R8,  R8_H,
 182                   R9,  R9_H,
 183                   R10, R10_H,
 184                   R11, R11_H,
 185                   R12, R12_H,
 186                   R13, R13_H,
 187                   R14, R14_H,
 188                   R15, R15_H);
 189 
 190 // Class for all int registers
 191 reg_class all_int_reg(RAX
 192                       RDX,
 193                       RBP,
 194                       RDI,
 195                       RSI,
 196                       RCX,
 197                       RBX,
 198                       R8,
 199                       R9,
 200                       R10,
 201                       R11,
 202                       R12,
 203                       R13,
 204                       R14);
 205 
 206 // Class for all pointer registers
 207 reg_class any_reg %{
 208   return _ANY_REG_mask;
 209 %}
 210 
 211 // Class for all pointer registers (excluding RSP)
 212 reg_class ptr_reg %{
 213   return _PTR_REG_mask;
 214 %}
 215 
 216 // Class for all pointer registers (excluding RSP and RBP)
 217 reg_class ptr_reg_no_rbp %{
 218   return _PTR_REG_NO_RBP_mask;
 219 %}
 220 
 221 // Class for all pointer registers (excluding RAX and RSP)
 222 reg_class ptr_no_rax_reg %{
 223   return _PTR_NO_RAX_REG_mask;
 224 %}
 225 
 226 // Class for all pointer registers (excluding RAX, RBX, and RSP)
 227 reg_class ptr_no_rax_rbx_reg %{
 228   return _PTR_NO_RAX_RBX_REG_mask;
 229 %}
 230 
 231 // Class for all long registers (excluding RSP)
 232 reg_class long_reg %{
 233   return _LONG_REG_mask;
 234 %}
 235 
 236 // Class for all long registers (excluding RAX, RDX and RSP)
 237 reg_class long_no_rax_rdx_reg %{
 238   return _LONG_NO_RAX_RDX_REG_mask;
 239 %}
 240 
 241 // Class for all long registers (excluding RCX and RSP)
 242 reg_class long_no_rcx_reg %{
 243   return _LONG_NO_RCX_REG_mask;
 244 %}
 245 
 246 // Class for all int registers (excluding RSP)
 247 reg_class int_reg %{
 248   return _INT_REG_mask;
 249 %}
 250 
 251 // Class for all int registers (excluding RAX, RDX, and RSP)
 252 reg_class int_no_rax_rdx_reg %{
 253   return _INT_NO_RAX_RDX_REG_mask;
 254 %}
 255 
 256 // Class for all int registers (excluding RCX and RSP)
 257 reg_class int_no_rcx_reg %{
 258   return _INT_NO_RCX_REG_mask;
 259 %}
 260 
 261 // Singleton class for RAX pointer register
 262 reg_class ptr_rax_reg(RAX, RAX_H);
 263 
 264 // Singleton class for RBX pointer register
 265 reg_class ptr_rbx_reg(RBX, RBX_H);
 266 
 267 // Singleton class for RSI pointer register
 268 reg_class ptr_rsi_reg(RSI, RSI_H);
 269 
 270 // Singleton class for RBP pointer register
 271 reg_class ptr_rbp_reg(RBP, RBP_H);
 272 
 273 // Singleton class for RDI pointer register
 274 reg_class ptr_rdi_reg(RDI, RDI_H);
 275 
 276 // Singleton class for stack pointer
 277 reg_class ptr_rsp_reg(RSP, RSP_H);
 278 
 279 // Singleton class for TLS pointer
 280 reg_class ptr_r15_reg(R15, R15_H);
 281 
 282 // Singleton class for RAX long register
 283 reg_class long_rax_reg(RAX, RAX_H);
 284 
 285 // Singleton class for RCX long register
 286 reg_class long_rcx_reg(RCX, RCX_H);
 287 
 288 // Singleton class for RDX long register
 289 reg_class long_rdx_reg(RDX, RDX_H);
 290 
 291 // Singleton class for RAX int register
 292 reg_class int_rax_reg(RAX);
 293 
 294 // Singleton class for RBX int register
 295 reg_class int_rbx_reg(RBX);
 296 
 297 // Singleton class for RCX int register
 298 reg_class int_rcx_reg(RCX);
 299 
 300 // Singleton class for RCX int register
 301 reg_class int_rdx_reg(RDX);
 302 
 303 // Singleton class for RCX int register
 304 reg_class int_rdi_reg(RDI);
 305 
 306 // Singleton class for instruction pointer
 307 // reg_class ip_reg(RIP);
 308 
 309 %}
 310 
 311 //----------SOURCE BLOCK-------------------------------------------------------
 312 // This is a block of C++ code which provides values, functions, and
 313 // definitions necessary in the rest of the architecture description
 314 source_hpp %{
 315 
 316 extern RegMask _ANY_REG_mask;
 317 extern RegMask _PTR_REG_mask;
 318 extern RegMask _PTR_REG_NO_RBP_mask;
 319 extern RegMask _PTR_NO_RAX_REG_mask;
 320 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
 321 extern RegMask _LONG_REG_mask;
 322 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
 323 extern RegMask _LONG_NO_RCX_REG_mask;
 324 extern RegMask _INT_REG_mask;
 325 extern RegMask _INT_NO_RAX_RDX_REG_mask;
 326 extern RegMask _INT_NO_RCX_REG_mask;
 327 
 328 extern RegMask _STACK_OR_PTR_REG_mask;
 329 extern RegMask _STACK_OR_LONG_REG_mask;
 330 extern RegMask _STACK_OR_INT_REG_mask;
 331 
 332 inline const RegMask& STACK_OR_PTR_REG_mask()  { return _STACK_OR_PTR_REG_mask;  }
 333 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
 334 inline const RegMask& STACK_OR_INT_REG_mask()  { return _STACK_OR_INT_REG_mask;  }
 335 
 336 %}
 337 
 338 source %{
 339 #define   RELOC_IMM64    Assembler::imm_operand
 340 #define   RELOC_DISP32   Assembler::disp32_operand
 341 
 342 #define __ _masm.
 343 
 344 RegMask _ANY_REG_mask;
 345 RegMask _PTR_REG_mask;
 346 RegMask _PTR_REG_NO_RBP_mask;
 347 RegMask _PTR_NO_RAX_REG_mask;
 348 RegMask _PTR_NO_RAX_RBX_REG_mask;
 349 RegMask _LONG_REG_mask;
 350 RegMask _LONG_NO_RAX_RDX_REG_mask;
 351 RegMask _LONG_NO_RCX_REG_mask;
 352 RegMask _INT_REG_mask;
 353 RegMask _INT_NO_RAX_RDX_REG_mask;
 354 RegMask _INT_NO_RCX_REG_mask;
 355 RegMask _STACK_OR_PTR_REG_mask;
 356 RegMask _STACK_OR_LONG_REG_mask;
 357 RegMask _STACK_OR_INT_REG_mask;
 358 
 359 static bool need_r12_heapbase() {
 360   return UseCompressedOops;
 361 }
 362 
 363 void reg_mask_init() {
 364   // _ALL_REG_mask is generated by adlc from the all_reg register class below.
 365   // We derive a number of subsets from it.
 366   _ANY_REG_mask = _ALL_REG_mask;
 367 
 368   if (PreserveFramePointer) {
 369     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
 370     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
 371   }
 372   if (need_r12_heapbase()) {
 373     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
 374     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
 375   }
 376 
 377   _PTR_REG_mask = _ANY_REG_mask;
 378   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
 379   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
 380   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
 381   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
 382 
 383   _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
 384   _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
 385 
 386   _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
 387   _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
 388   _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
 389 
 390   _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
 391   _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
 392   _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
 393 
 394   _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
 395   _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
 396   _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
 397 
 398   _LONG_REG_mask = _PTR_REG_mask;
 399   _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
 400   _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
 401 
 402   _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
 403   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
 404   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
 405   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
 406   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
 407 
 408   _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
 409   _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
 410   _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
 411 
 412   _INT_REG_mask = _ALL_INT_REG_mask;
 413   if (PreserveFramePointer) {
 414     _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
 415   }
 416   if (need_r12_heapbase()) {
 417     _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
 418   }
 419 
 420   _STACK_OR_INT_REG_mask = _INT_REG_mask;
 421   _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
 422 
 423   _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
 424   _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
 425   _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
 426 
 427   _INT_NO_RCX_REG_mask = _INT_REG_mask;
 428   _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
 429 }
 430 
 431 static bool generate_vzeroupper(Compile* C) {
 432   return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false;  // Generate vzeroupper
 433 }
 434 
 435 static int clear_avx_size() {
 436   return generate_vzeroupper(Compile::current()) ? 3: 0;  // vzeroupper
 437 }
 438 
 439 // !!!!! Special hack to get all types of calls to specify the byte offset
 440 //       from the start of the call to the point where the return address
 441 //       will point.
 442 int MachCallStaticJavaNode::ret_addr_offset()
 443 {
 444   int offset = 5; // 5 bytes from start of call to where return address points
 445   offset += clear_avx_size();
 446   return offset;
 447 }
 448 
 449 int MachCallDynamicJavaNode::ret_addr_offset()
 450 {
 451   int offset = 15; // 15 bytes from start of call to where return address points
 452   offset += clear_avx_size();
 453   return offset;
 454 }
 455 
 456 int MachCallRuntimeNode::ret_addr_offset() {
 457   int offset = 13; // movq r10,#addr; callq (r10)
 458   offset += clear_avx_size();
 459   return offset;
 460 }
 461 
 462 //
 463 // Compute padding required for nodes which need alignment
 464 //
 465 
 466 // The address of the call instruction needs to be 4-byte aligned to
 467 // ensure that it does not span a cache line so that it can be patched.
 468 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
 469 {
 470   current_offset += clear_avx_size(); // skip vzeroupper
 471   current_offset += 1; // skip call opcode byte
 472   return align_up(current_offset, alignment_required()) - current_offset;
 473 }
 474 
 475 // The address of the call instruction needs to be 4-byte aligned to
 476 // ensure that it does not span a cache line so that it can be patched.
 477 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
 478 {
 479   current_offset += clear_avx_size(); // skip vzeroupper
 480   current_offset += 11; // skip movq instruction + call opcode byte
 481   return align_up(current_offset, alignment_required()) - current_offset;
 482 }
 483 
 484 // EMIT_RM()
 485 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
 486   unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
 487   cbuf.insts()->emit_int8(c);
 488 }
 489 
 490 // EMIT_CC()
 491 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
 492   unsigned char c = (unsigned char) (f1 | f2);
 493   cbuf.insts()->emit_int8(c);
 494 }
 495 
 496 // EMIT_OPCODE()
 497 void emit_opcode(CodeBuffer &cbuf, int code) {
 498   cbuf.insts()->emit_int8((unsigned char) code);
 499 }
 500 
 501 // EMIT_OPCODE() w/ relocation information
 502 void emit_opcode(CodeBuffer &cbuf,
 503                  int code, relocInfo::relocType reloc, int offset, int format)
 504 {
 505   cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
 506   emit_opcode(cbuf, code);
 507 }
 508 
 509 // EMIT_D8()
 510 void emit_d8(CodeBuffer &cbuf, int d8) {
 511   cbuf.insts()->emit_int8((unsigned char) d8);
 512 }
 513 
 514 // EMIT_D16()
 515 void emit_d16(CodeBuffer &cbuf, int d16) {
 516   cbuf.insts()->emit_int16(d16);
 517 }
 518 
 519 // EMIT_D32()
 520 void emit_d32(CodeBuffer &cbuf, int d32) {
 521   cbuf.insts()->emit_int32(d32);
 522 }
 523 
 524 // EMIT_D64()
 525 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
 526   cbuf.insts()->emit_int64(d64);
 527 }
 528 
 529 // emit 32 bit value and construct relocation entry from relocInfo::relocType
 530 void emit_d32_reloc(CodeBuffer& cbuf,
 531                     int d32,
 532                     relocInfo::relocType reloc,
 533                     int format)
 534 {
 535   assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
 536   cbuf.relocate(cbuf.insts_mark(), reloc, format);
 537   cbuf.insts()->emit_int32(d32);
 538 }
 539 
 540 // emit 32 bit value and construct relocation entry from RelocationHolder
 541 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
 542 #ifdef ASSERT
 543   if (rspec.reloc()->type() == relocInfo::oop_type &&
 544       d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
 545     assert(Universe::heap()->is_in((address)(intptr_t)d32), "should be real oop");
 546     assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)), "cannot embed broken oops in code");
 547   }
 548 #endif
 549   cbuf.relocate(cbuf.insts_mark(), rspec, format);
 550   cbuf.insts()->emit_int32(d32);
 551 }
 552 
 553 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
 554   address next_ip = cbuf.insts_end() + 4;
 555   emit_d32_reloc(cbuf, (int) (addr - next_ip),
 556                  external_word_Relocation::spec(addr),
 557                  RELOC_DISP32);
 558 }
 559 
 560 
 561 // emit 64 bit value and construct relocation entry from relocInfo::relocType
 562 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
 563   cbuf.relocate(cbuf.insts_mark(), reloc, format);
 564   cbuf.insts()->emit_int64(d64);
 565 }
 566 
 567 // emit 64 bit value and construct relocation entry from RelocationHolder
 568 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
 569 #ifdef ASSERT
 570   if (rspec.reloc()->type() == relocInfo::oop_type &&
 571       d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
 572     assert(Universe::heap()->is_in((address)d64), "should be real oop");
 573     assert(oopDesc::is_oop(cast_to_oop(d64)), "cannot embed broken oops in code");
 574   }
 575 #endif
 576   cbuf.relocate(cbuf.insts_mark(), rspec, format);
 577   cbuf.insts()->emit_int64(d64);
 578 }
 579 
 580 // Access stack slot for load or store
 581 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
 582 {
 583   emit_opcode(cbuf, opcode);                  // (e.g., FILD   [RSP+src])
 584   if (-0x80 <= disp && disp < 0x80) {
 585     emit_rm(cbuf, 0x01, rm_field, RSP_enc);   // R/M byte
 586     emit_rm(cbuf, 0x00, RSP_enc, RSP_enc);    // SIB byte
 587     emit_d8(cbuf, disp);     // Displacement  // R/M byte
 588   } else {
 589     emit_rm(cbuf, 0x02, rm_field, RSP_enc);   // R/M byte
 590     emit_rm(cbuf, 0x00, RSP_enc, RSP_enc);    // SIB byte
 591     emit_d32(cbuf, disp);     // Displacement // R/M byte
 592   }
 593 }
 594 
 595    // rRegI ereg, memory mem) %{    // emit_reg_mem
 596 void encode_RegMem(CodeBuffer &cbuf,
 597                    int reg,
 598                    int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
 599 {
 600   assert(disp_reloc == relocInfo::none, "cannot have disp");
 601   int regenc = reg & 7;
 602   int baseenc = base & 7;
 603   int indexenc = index & 7;
 604 
 605   // There is no index & no scale, use form without SIB byte
 606   if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
 607     // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
 608     if (disp == 0 && base != RBP_enc && base != R13_enc) {
 609       emit_rm(cbuf, 0x0, regenc, baseenc); // *
 610     } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
 611       // If 8-bit displacement, mode 0x1
 612       emit_rm(cbuf, 0x1, regenc, baseenc); // *
 613       emit_d8(cbuf, disp);
 614     } else {
 615       // If 32-bit displacement
 616       if (base == -1) { // Special flag for absolute address
 617         emit_rm(cbuf, 0x0, regenc, 0x5); // *
 618         if (disp_reloc != relocInfo::none) {
 619           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
 620         } else {
 621           emit_d32(cbuf, disp);
 622         }
 623       } else {
 624         // Normal base + offset
 625         emit_rm(cbuf, 0x2, regenc, baseenc); // *
 626         if (disp_reloc != relocInfo::none) {
 627           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
 628         } else {
 629           emit_d32(cbuf, disp);
 630         }
 631       }
 632     }
 633   } else {
 634     // Else, encode with the SIB byte
 635     // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
 636     if (disp == 0 && base != RBP_enc && base != R13_enc) {
 637       // If no displacement
 638       emit_rm(cbuf, 0x0, regenc, 0x4); // *
 639       emit_rm(cbuf, scale, indexenc, baseenc);
 640     } else {
 641       if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
 642         // If 8-bit displacement, mode 0x1
 643         emit_rm(cbuf, 0x1, regenc, 0x4); // *
 644         emit_rm(cbuf, scale, indexenc, baseenc);
 645         emit_d8(cbuf, disp);
 646       } else {
 647         // If 32-bit displacement
 648         if (base == 0x04 ) {
 649           emit_rm(cbuf, 0x2, regenc, 0x4);
 650           emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
 651         } else {
 652           emit_rm(cbuf, 0x2, regenc, 0x4);
 653           emit_rm(cbuf, scale, indexenc, baseenc); // *
 654         }
 655         if (disp_reloc != relocInfo::none) {
 656           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
 657         } else {
 658           emit_d32(cbuf, disp);
 659         }
 660       }
 661     }
 662   }
 663 }
 664 
 665 // This could be in MacroAssembler but it's fairly C2 specific
 666 void emit_cmpfp_fixup(MacroAssembler& _masm) {
 667   Label exit;
 668   __ jccb(Assembler::noParity, exit);
 669   __ pushf();
 670   //
 671   // comiss/ucomiss instructions set ZF,PF,CF flags and
 672   // zero OF,AF,SF for NaN values.
 673   // Fixup flags by zeroing ZF,PF so that compare of NaN
 674   // values returns 'less than' result (CF is set).
 675   // Leave the rest of flags unchanged.
 676   //
 677   //    7 6 5 4 3 2 1 0
 678   //   |S|Z|r|A|r|P|r|C|  (r - reserved bit)
 679   //    0 0 1 0 1 0 1 1   (0x2B)
 680   //
 681   __ andq(Address(rsp, 0), 0xffffff2b);
 682   __ popf();
 683   __ bind(exit);
 684 }
 685 
 686 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
 687   Label done;
 688   __ movl(dst, -1);
 689   __ jcc(Assembler::parity, done);
 690   __ jcc(Assembler::below, done);
 691   __ setb(Assembler::notEqual, dst);
 692   __ movzbl(dst, dst);
 693   __ bind(done);
 694 }
 695 
 696 // Math.min()    # Math.max()
 697 // --------------------------
 698 // ucomis[s/d]   #
 699 // ja   -> b     # a
 700 // jp   -> NaN   # NaN
 701 // jb   -> a     # b
 702 // je            #
 703 // |-jz -> a | b # a & b
 704 // |    -> a     #
 705 void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst,
 706                      XMMRegister a, XMMRegister b,
 707                      XMMRegister xmmt, Register rt,
 708                      bool min, bool single) {
 709 
 710   Label nan, zero, below, above, done;
 711 
 712   if (single)
 713     __ ucomiss(a, b);
 714   else
 715     __ ucomisd(a, b);
 716 
 717   if (dst->encoding() != (min ? b : a)->encoding())
 718     __ jccb(Assembler::above, above); // CF=0 & ZF=0
 719   else
 720     __ jccb(Assembler::above, done);
 721 
 722   __ jccb(Assembler::parity, nan);  // PF=1
 723   __ jccb(Assembler::below, below); // CF=1
 724 
 725   // equal
 726   __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
 727   if (single) {
 728     __ ucomiss(a, xmmt);
 729     __ jccb(Assembler::equal, zero);
 730 
 731     __ movflt(dst, a);
 732     __ jmp(done);
 733   }
 734   else {
 735     __ ucomisd(a, xmmt);
 736     __ jccb(Assembler::equal, zero);
 737 
 738     __ movdbl(dst, a);
 739     __ jmp(done);
 740   }
 741 
 742   __ bind(zero);
 743   if (min)
 744     __ vpor(dst, a, b, Assembler::AVX_128bit);
 745   else
 746     __ vpand(dst, a, b, Assembler::AVX_128bit);
 747 
 748   __ jmp(done);
 749 
 750   __ bind(above);
 751   if (single)
 752     __ movflt(dst, min ? b : a);
 753   else
 754     __ movdbl(dst, min ? b : a);
 755 
 756   __ jmp(done);
 757 
 758   __ bind(nan);
 759   if (single) {
 760     __ movl(rt, 0x7fc00000); // Float.NaN
 761     __ movdl(dst, rt);
 762   }
 763   else {
 764     __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
 765     __ movdq(dst, rt);
 766   }
 767   __ jmp(done);
 768 
 769   __ bind(below);
 770   if (single)
 771     __ movflt(dst, min ? a : b);
 772   else
 773     __ movdbl(dst, min ? a : b);
 774 
 775   __ bind(done);
 776 }
 777 
 778 //=============================================================================
 779 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
 780 
 781 int ConstantTable::calculate_table_base_offset() const {
 782   return 0;  // absolute addressing, no offset
 783 }
 784 
 785 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
 786 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
 787   ShouldNotReachHere();
 788 }
 789 
 790 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
 791   // Empty encoding
 792 }
 793 
 794 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
 795   return 0;
 796 }
 797 
 798 #ifndef PRODUCT
 799 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 800   st->print("# MachConstantBaseNode (empty encoding)");
 801 }
 802 #endif
 803 
 804 
 805 //=============================================================================
 806 #ifndef PRODUCT
 807 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 808   Compile* C = ra_->C;
 809 
 810   int framesize = C->output()->frame_size_in_bytes();
 811   int bangsize = C->output()->bang_size_in_bytes();
 812   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 813   // Remove wordSize for return addr which is already pushed.
 814   framesize -= wordSize;
 815 
 816   if (C->output()->need_stack_bang(bangsize)) {
 817     framesize -= wordSize;
 818     st->print("# stack bang (%d bytes)", bangsize);
 819     st->print("\n\t");
 820     st->print("pushq   rbp\t# Save rbp");
 821     if (PreserveFramePointer) {
 822         st->print("\n\t");
 823         st->print("movq    rbp, rsp\t# Save the caller's SP into rbp");
 824     }
 825     if (framesize) {
 826       st->print("\n\t");
 827       st->print("subq    rsp, #%d\t# Create frame",framesize);
 828     }
 829   } else {
 830     st->print("subq    rsp, #%d\t# Create frame",framesize);
 831     st->print("\n\t");
 832     framesize -= wordSize;
 833     st->print("movq    [rsp + #%d], rbp\t# Save rbp",framesize);
 834     if (PreserveFramePointer) {
 835       st->print("\n\t");
 836       st->print("movq    rbp, rsp\t# Save the caller's SP into rbp");
 837       if (framesize > 0) {
 838         st->print("\n\t");
 839         st->print("addq    rbp, #%d", framesize);
 840       }
 841     }
 842   }
 843 
 844   if (VerifyStackAtCalls) {
 845     st->print("\n\t");
 846     framesize -= wordSize;
 847     st->print("movq    [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
 848 #ifdef ASSERT
 849     st->print("\n\t");
 850     st->print("# stack alignment check");
 851 #endif
 852   }
 853   if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
 854     st->print("\n\t");
 855     st->print("cmpl    [r15_thread + #disarmed_offset], #disarmed_value\t");
 856     st->print("\n\t");
 857     st->print("je      fast_entry\t");
 858     st->print("\n\t");
 859     st->print("call    #nmethod_entry_barrier_stub\t");
 860     st->print("\n\tfast_entry:");
 861   }
 862   st->cr();
 863 }
 864 #endif
 865 
 866 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 867   Compile* C = ra_->C;
 868   MacroAssembler _masm(&cbuf);
 869 
 870   int framesize = C->output()->frame_size_in_bytes();
 871   int bangsize = C->output()->bang_size_in_bytes();
 872 
 873   if (C->clinit_barrier_on_entry()) {
 874     assert(VM_Version::supports_fast_class_init_checks(), "sanity");
 875     assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
 876 
 877     Label L_skip_barrier;
 878     Register klass = rscratch1;
 879 
 880     __ mov_metadata(klass, C->method()->holder()->constant_encoding());
 881     __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
 882 
 883     __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
 884 
 885     __ bind(L_skip_barrier);
 886   }
 887 
 888   __ verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL);
 889 
 890   C->output()->set_frame_complete(cbuf.insts_size());
 891 
 892   if (C->has_mach_constant_base_node()) {
 893     // NOTE: We set the table base offset here because users might be
 894     // emitted before MachConstantBaseNode.
 895     ConstantTable& constant_table = C->output()->constant_table();
 896     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
 897   }
 898 }
 899 
 900 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
 901 {
 902   return MachNode::size(ra_); // too many variables; just compute it
 903                               // the hard way
 904 }
 905 
 906 int MachPrologNode::reloc() const
 907 {
 908   return 0; // a large enough number
 909 }
 910 
 911 //=============================================================================
 912 #ifndef PRODUCT
 913 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 914 {
 915   Compile* C = ra_->C;
 916   if (generate_vzeroupper(C)) {
 917     st->print("vzeroupper");
 918     st->cr(); st->print("\t");
 919   }
 920 
 921   int framesize = C->output()->frame_size_in_bytes();
 922   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 923   // Remove word for return adr already pushed
 924   // and RBP
 925   framesize -= 2*wordSize;
 926 
 927   if (framesize) {
 928     st->print_cr("addq    rsp, %d\t# Destroy frame", framesize);
 929     st->print("\t");
 930   }
 931 
 932   st->print_cr("popq    rbp");
 933   if (do_polling() && C->is_method_compilation()) {
 934     st->print("\t");
 935     st->print_cr("movq    rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
 936                  "testl   rax, [rscratch1]\t"
 937                  "# Safepoint: poll for GC");
 938   }
 939 }
 940 #endif
 941 
 942 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
 943 {
 944   Compile* C = ra_->C;
 945   MacroAssembler _masm(&cbuf);
 946 
 947   if (generate_vzeroupper(C)) {
 948     // Clear upper bits of YMM registers when current compiled code uses
 949     // wide vectors to avoid AVX <-> SSE transition penalty during call.
 950     __ vzeroupper();
 951   }
 952 
 953   int framesize = C->output()->frame_size_in_bytes();
 954   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 955   // Remove word for return adr already pushed
 956   // and RBP
 957   framesize -= 2*wordSize;
 958 
 959   // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
 960 
 961   if (framesize) {
 962     emit_opcode(cbuf, Assembler::REX_W);
 963     if (framesize < 0x80) {
 964       emit_opcode(cbuf, 0x83); // addq rsp, #framesize
 965       emit_rm(cbuf, 0x3, 0x00, RSP_enc);
 966       emit_d8(cbuf, framesize);
 967     } else {
 968       emit_opcode(cbuf, 0x81); // addq rsp, #framesize
 969       emit_rm(cbuf, 0x3, 0x00, RSP_enc);
 970       emit_d32(cbuf, framesize);
 971     }
 972   }
 973 
 974   // popq rbp
 975   emit_opcode(cbuf, 0x58 | RBP_enc);
 976 
 977   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
 978     __ reserved_stack_check();
 979   }
 980 
 981   if (do_polling() && C->is_method_compilation()) {
 982     MacroAssembler _masm(&cbuf);
 983     __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
 984     __ relocate(relocInfo::poll_return_type);
 985     __ testl(rax, Address(rscratch1, 0));
 986   }
 987 }
 988 
 989 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
 990 {
 991   return MachNode::size(ra_); // too many variables; just compute it
 992                               // the hard way
 993 }
 994 
 995 int MachEpilogNode::reloc() const
 996 {
 997   return 2; // a large enough number
 998 }
 999 
1000 const Pipeline* MachEpilogNode::pipeline() const
1001 {
1002   return MachNode::pipeline_class();
1003 }
1004 
1005 //=============================================================================
1006 
1007 enum RC {
1008   rc_bad,
1009   rc_int,
1010   rc_float,
1011   rc_stack
1012 };
1013 
1014 static enum RC rc_class(OptoReg::Name reg)
1015 {
1016   if( !OptoReg::is_valid(reg)  ) return rc_bad;
1017 
1018   if (OptoReg::is_stack(reg)) return rc_stack;
1019 
1020   VMReg r = OptoReg::as_VMReg(reg);
1021 
1022   if (r->is_Register()) return rc_int;
1023 
1024   assert(r->is_XMMRegister(), "must be");
1025   return rc_float;
1026 }
1027 
1028 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1029 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1030                           int src_hi, int dst_hi, uint ireg, outputStream* st);
1031 
1032 int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1033                      int stack_offset, int reg, uint ireg, outputStream* st);
1034 
1035 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1036                                       int dst_offset, uint ireg, outputStream* st) {
1037   if (cbuf) {
1038     MacroAssembler _masm(cbuf);
1039     switch (ireg) {
1040     case Op_VecS:
1041       __ movq(Address(rsp, -8), rax);
1042       __ movl(rax, Address(rsp, src_offset));
1043       __ movl(Address(rsp, dst_offset), rax);
1044       __ movq(rax, Address(rsp, -8));
1045       break;
1046     case Op_VecD:
1047       __ pushq(Address(rsp, src_offset));
1048       __ popq (Address(rsp, dst_offset));
1049       break;
1050     case Op_VecX:
1051       __ pushq(Address(rsp, src_offset));
1052       __ popq (Address(rsp, dst_offset));
1053       __ pushq(Address(rsp, src_offset+8));
1054       __ popq (Address(rsp, dst_offset+8));
1055       break;
1056     case Op_VecY:
1057       __ vmovdqu(Address(rsp, -32), xmm0);
1058       __ vmovdqu(xmm0, Address(rsp, src_offset));
1059       __ vmovdqu(Address(rsp, dst_offset), xmm0);
1060       __ vmovdqu(xmm0, Address(rsp, -32));
1061       break;
1062     case Op_VecZ:
1063       __ evmovdquq(Address(rsp, -64), xmm0, 2);
1064       __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1065       __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1066       __ evmovdquq(xmm0, Address(rsp, -64), 2);
1067       break;
1068     default:
1069       ShouldNotReachHere();
1070     }
1071 #ifndef PRODUCT
1072   } else {
1073     switch (ireg) {
1074     case Op_VecS:
1075       st->print("movq    [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1076                 "movl    rax, [rsp + #%d]\n\t"
1077                 "movl    [rsp + #%d], rax\n\t"
1078                 "movq    rax, [rsp - #8]",
1079                 src_offset, dst_offset);
1080       break;
1081     case Op_VecD:
1082       st->print("pushq   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1083                 "popq    [rsp + #%d]",
1084                 src_offset, dst_offset);
1085       break;
1086      case Op_VecX:
1087       st->print("pushq   [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1088                 "popq    [rsp + #%d]\n\t"
1089                 "pushq   [rsp + #%d]\n\t"
1090                 "popq    [rsp + #%d]",
1091                 src_offset, dst_offset, src_offset+8, dst_offset+8);
1092       break;
1093     case Op_VecY:
1094       st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1095                 "vmovdqu xmm0, [rsp + #%d]\n\t"
1096                 "vmovdqu [rsp + #%d], xmm0\n\t"
1097                 "vmovdqu xmm0, [rsp - #32]",
1098                 src_offset, dst_offset);
1099       break;
1100     case Op_VecZ:
1101       st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1102                 "vmovdqu xmm0, [rsp + #%d]\n\t"
1103                 "vmovdqu [rsp + #%d], xmm0\n\t"
1104                 "vmovdqu xmm0, [rsp - #64]",
1105                 src_offset, dst_offset);
1106       break;
1107     default:
1108       ShouldNotReachHere();
1109     }
1110 #endif
1111   }
1112 }
1113 
1114 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1115                                        PhaseRegAlloc* ra_,
1116                                        bool do_size,
1117                                        outputStream* st) const {
1118   assert(cbuf != NULL || st  != NULL, "sanity");
1119   // Get registers to move
1120   OptoReg::Name src_second = ra_->get_reg_second(in(1));
1121   OptoReg::Name src_first = ra_->get_reg_first(in(1));
1122   OptoReg::Name dst_second = ra_->get_reg_second(this);
1123   OptoReg::Name dst_first = ra_->get_reg_first(this);
1124 
1125   enum RC src_second_rc = rc_class(src_second);
1126   enum RC src_first_rc = rc_class(src_first);
1127   enum RC dst_second_rc = rc_class(dst_second);
1128   enum RC dst_first_rc = rc_class(dst_first);
1129 
1130   assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1131          "must move at least 1 register" );
1132 
1133   if (src_first == dst_first && src_second == dst_second) {
1134     // Self copy, no move
1135     return 0;
1136   }
1137   if (bottom_type()->isa_vect() != NULL) {
1138     uint ireg = ideal_reg();
1139     assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1140     assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1141     if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1142       // mem -> mem
1143       int src_offset = ra_->reg2offset(src_first);
1144       int dst_offset = ra_->reg2offset(dst_first);
1145       vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1146     } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1147       vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1148     } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1149       int stack_offset = ra_->reg2offset(dst_first);
1150       vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1151     } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1152       int stack_offset = ra_->reg2offset(src_first);
1153       vec_spill_helper(cbuf, false, true,  stack_offset, dst_first, ireg, st);
1154     } else {
1155       ShouldNotReachHere();
1156     }
1157     return 0;
1158   }
1159   if (src_first_rc == rc_stack) {
1160     // mem ->
1161     if (dst_first_rc == rc_stack) {
1162       // mem -> mem
1163       assert(src_second != dst_first, "overlap");
1164       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1165           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1166         // 64-bit
1167         int src_offset = ra_->reg2offset(src_first);
1168         int dst_offset = ra_->reg2offset(dst_first);
1169         if (cbuf) {
1170           MacroAssembler _masm(cbuf);
1171           __ pushq(Address(rsp, src_offset));
1172           __ popq (Address(rsp, dst_offset));
1173 #ifndef PRODUCT
1174         } else {
1175           st->print("pushq   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1176                     "popq    [rsp + #%d]",
1177                      src_offset, dst_offset);
1178 #endif
1179         }
1180       } else {
1181         // 32-bit
1182         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1183         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1184         // No pushl/popl, so:
1185         int src_offset = ra_->reg2offset(src_first);
1186         int dst_offset = ra_->reg2offset(dst_first);
1187         if (cbuf) {
1188           MacroAssembler _masm(cbuf);
1189           __ movq(Address(rsp, -8), rax);
1190           __ movl(rax, Address(rsp, src_offset));
1191           __ movl(Address(rsp, dst_offset), rax);
1192           __ movq(rax, Address(rsp, -8));
1193 #ifndef PRODUCT
1194         } else {
1195           st->print("movq    [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1196                     "movl    rax, [rsp + #%d]\n\t"
1197                     "movl    [rsp + #%d], rax\n\t"
1198                     "movq    rax, [rsp - #8]",
1199                      src_offset, dst_offset);
1200 #endif
1201         }
1202       }
1203       return 0;
1204     } else if (dst_first_rc == rc_int) {
1205       // mem -> gpr
1206       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1207           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1208         // 64-bit
1209         int offset = ra_->reg2offset(src_first);
1210         if (cbuf) {
1211           MacroAssembler _masm(cbuf);
1212           __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1213 #ifndef PRODUCT
1214         } else {
1215           st->print("movq    %s, [rsp + #%d]\t# spill",
1216                      Matcher::regName[dst_first],
1217                      offset);
1218 #endif
1219         }
1220       } else {
1221         // 32-bit
1222         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1223         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1224         int offset = ra_->reg2offset(src_first);
1225         if (cbuf) {
1226           MacroAssembler _masm(cbuf);
1227           __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1228 #ifndef PRODUCT
1229         } else {
1230           st->print("movl    %s, [rsp + #%d]\t# spill",
1231                      Matcher::regName[dst_first],
1232                      offset);
1233 #endif
1234         }
1235       }
1236       return 0;
1237     } else if (dst_first_rc == rc_float) {
1238       // mem-> xmm
1239       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1240           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1241         // 64-bit
1242         int offset = ra_->reg2offset(src_first);
1243         if (cbuf) {
1244           MacroAssembler _masm(cbuf);
1245           __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1246 #ifndef PRODUCT
1247         } else {
1248           st->print("%s  %s, [rsp + #%d]\t# spill",
1249                      UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1250                      Matcher::regName[dst_first],
1251                      offset);
1252 #endif
1253         }
1254       } else {
1255         // 32-bit
1256         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1257         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1258         int offset = ra_->reg2offset(src_first);
1259         if (cbuf) {
1260           MacroAssembler _masm(cbuf);
1261           __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1262 #ifndef PRODUCT
1263         } else {
1264           st->print("movss   %s, [rsp + #%d]\t# spill",
1265                      Matcher::regName[dst_first],
1266                      offset);
1267 #endif
1268         }
1269       }
1270       return 0;
1271     }
1272   } else if (src_first_rc == rc_int) {
1273     // gpr ->
1274     if (dst_first_rc == rc_stack) {
1275       // gpr -> mem
1276       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1277           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1278         // 64-bit
1279         int offset = ra_->reg2offset(dst_first);
1280         if (cbuf) {
1281           MacroAssembler _masm(cbuf);
1282           __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1283 #ifndef PRODUCT
1284         } else {
1285           st->print("movq    [rsp + #%d], %s\t# spill",
1286                      offset,
1287                      Matcher::regName[src_first]);
1288 #endif
1289         }
1290       } else {
1291         // 32-bit
1292         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1293         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1294         int offset = ra_->reg2offset(dst_first);
1295         if (cbuf) {
1296           MacroAssembler _masm(cbuf);
1297           __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1298 #ifndef PRODUCT
1299         } else {
1300           st->print("movl    [rsp + #%d], %s\t# spill",
1301                      offset,
1302                      Matcher::regName[src_first]);
1303 #endif
1304         }
1305       }
1306       return 0;
1307     } else if (dst_first_rc == rc_int) {
1308       // gpr -> gpr
1309       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1310           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1311         // 64-bit
1312         if (cbuf) {
1313           MacroAssembler _masm(cbuf);
1314           __ movq(as_Register(Matcher::_regEncode[dst_first]),
1315                   as_Register(Matcher::_regEncode[src_first]));
1316 #ifndef PRODUCT
1317         } else {
1318           st->print("movq    %s, %s\t# spill",
1319                      Matcher::regName[dst_first],
1320                      Matcher::regName[src_first]);
1321 #endif
1322         }
1323         return 0;
1324       } else {
1325         // 32-bit
1326         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1327         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1328         if (cbuf) {
1329           MacroAssembler _masm(cbuf);
1330           __ movl(as_Register(Matcher::_regEncode[dst_first]),
1331                   as_Register(Matcher::_regEncode[src_first]));
1332 #ifndef PRODUCT
1333         } else {
1334           st->print("movl    %s, %s\t# spill",
1335                      Matcher::regName[dst_first],
1336                      Matcher::regName[src_first]);
1337 #endif
1338         }
1339         return 0;
1340       }
1341     } else if (dst_first_rc == rc_float) {
1342       // gpr -> xmm
1343       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1344           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1345         // 64-bit
1346         if (cbuf) {
1347           MacroAssembler _masm(cbuf);
1348           __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1349 #ifndef PRODUCT
1350         } else {
1351           st->print("movdq   %s, %s\t# spill",
1352                      Matcher::regName[dst_first],
1353                      Matcher::regName[src_first]);
1354 #endif
1355         }
1356       } else {
1357         // 32-bit
1358         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1359         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1360         if (cbuf) {
1361           MacroAssembler _masm(cbuf);
1362           __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1363 #ifndef PRODUCT
1364         } else {
1365           st->print("movdl   %s, %s\t# spill",
1366                      Matcher::regName[dst_first],
1367                      Matcher::regName[src_first]);
1368 #endif
1369         }
1370       }
1371       return 0;
1372     }
1373   } else if (src_first_rc == rc_float) {
1374     // xmm ->
1375     if (dst_first_rc == rc_stack) {
1376       // xmm -> mem
1377       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1378           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1379         // 64-bit
1380         int offset = ra_->reg2offset(dst_first);
1381         if (cbuf) {
1382           MacroAssembler _masm(cbuf);
1383           __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1384 #ifndef PRODUCT
1385         } else {
1386           st->print("movsd   [rsp + #%d], %s\t# spill",
1387                      offset,
1388                      Matcher::regName[src_first]);
1389 #endif
1390         }
1391       } else {
1392         // 32-bit
1393         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1394         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1395         int offset = ra_->reg2offset(dst_first);
1396         if (cbuf) {
1397           MacroAssembler _masm(cbuf);
1398           __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1399 #ifndef PRODUCT
1400         } else {
1401           st->print("movss   [rsp + #%d], %s\t# spill",
1402                      offset,
1403                      Matcher::regName[src_first]);
1404 #endif
1405         }
1406       }
1407       return 0;
1408     } else if (dst_first_rc == rc_int) {
1409       // xmm -> gpr
1410       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1411           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1412         // 64-bit
1413         if (cbuf) {
1414           MacroAssembler _masm(cbuf);
1415           __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1416 #ifndef PRODUCT
1417         } else {
1418           st->print("movdq   %s, %s\t# spill",
1419                      Matcher::regName[dst_first],
1420                      Matcher::regName[src_first]);
1421 #endif
1422         }
1423       } else {
1424         // 32-bit
1425         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1426         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1427         if (cbuf) {
1428           MacroAssembler _masm(cbuf);
1429           __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1430 #ifndef PRODUCT
1431         } else {
1432           st->print("movdl   %s, %s\t# spill",
1433                      Matcher::regName[dst_first],
1434                      Matcher::regName[src_first]);
1435 #endif
1436         }
1437       }
1438       return 0;
1439     } else if (dst_first_rc == rc_float) {
1440       // xmm -> xmm
1441       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1442           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1443         // 64-bit
1444         if (cbuf) {
1445           MacroAssembler _masm(cbuf);
1446           __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1447 #ifndef PRODUCT
1448         } else {
1449           st->print("%s  %s, %s\t# spill",
1450                      UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1451                      Matcher::regName[dst_first],
1452                      Matcher::regName[src_first]);
1453 #endif
1454         }
1455       } else {
1456         // 32-bit
1457         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1458         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1459         if (cbuf) {
1460           MacroAssembler _masm(cbuf);
1461           __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1462 #ifndef PRODUCT
1463         } else {
1464           st->print("%s  %s, %s\t# spill",
1465                      UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1466                      Matcher::regName[dst_first],
1467                      Matcher::regName[src_first]);
1468 #endif
1469         }
1470       }
1471       return 0;
1472     }
1473   }
1474 
1475   assert(0," foo ");
1476   Unimplemented();
1477   return 0;
1478 }
1479 
1480 #ifndef PRODUCT
1481 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1482   implementation(NULL, ra_, false, st);
1483 }
1484 #endif
1485 
1486 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1487   implementation(&cbuf, ra_, false, NULL);
1488 }
1489 
1490 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1491   return MachNode::size(ra_);
1492 }
1493 
1494 //=============================================================================
1495 #ifndef PRODUCT
1496 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1497 {
1498   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1499   int reg = ra_->get_reg_first(this);
1500   st->print("leaq    %s, [rsp + #%d]\t# box lock",
1501             Matcher::regName[reg], offset);
1502 }
1503 #endif
1504 
1505 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1506 {
1507   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1508   int reg = ra_->get_encode(this);
1509   if (offset >= 0x80) {
1510     emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1511     emit_opcode(cbuf, 0x8D); // LEA  reg,[SP+offset]
1512     emit_rm(cbuf, 0x2, reg & 7, 0x04);
1513     emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1514     emit_d32(cbuf, offset);
1515   } else {
1516     emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1517     emit_opcode(cbuf, 0x8D); // LEA  reg,[SP+offset]
1518     emit_rm(cbuf, 0x1, reg & 7, 0x04);
1519     emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1520     emit_d8(cbuf, offset);
1521   }
1522 }
1523 
1524 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1525 {
1526   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1527   return (offset < 0x80) ? 5 : 8; // REX
1528 }
1529 
1530 //=============================================================================
1531 #ifndef PRODUCT
1532 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1533 {
1534   if (UseCompressedClassPointers) {
1535     st->print_cr("movl    rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1536     st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1537     st->print_cr("\tcmpq    rax, rscratch1\t # Inline cache check");
1538   } else {
1539     st->print_cr("\tcmpq    rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1540                  "# Inline cache check");
1541   }
1542   st->print_cr("\tjne     SharedRuntime::_ic_miss_stub");
1543   st->print_cr("\tnop\t# nops to align entry point");
1544 }
1545 #endif
1546 
1547 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1548 {
1549   MacroAssembler masm(&cbuf);
1550   uint insts_size = cbuf.insts_size();
1551   if (UseCompressedClassPointers) {
1552     masm.load_klass(rscratch1, j_rarg0, rscratch2);
1553     masm.cmpptr(rax, rscratch1);
1554   } else {
1555     masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1556   }
1557 
1558   masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1559 
1560   /* WARNING these NOPs are critical so that verified entry point is properly
1561      4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1562   int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1563   if (OptoBreakpoint) {
1564     // Leave space for int3
1565     nops_cnt -= 1;
1566   }
1567   nops_cnt &= 0x3; // Do not add nops if code is aligned.
1568   if (nops_cnt > 0)
1569     masm.nop(nops_cnt);
1570 }
1571 
1572 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1573 {
1574   return MachNode::size(ra_); // too many variables; just compute it
1575                               // the hard way
1576 }
1577 
1578 
1579 //=============================================================================
1580 
1581 int Matcher::regnum_to_fpu_offset(int regnum)
1582 {
1583   return regnum - 32; // The FP registers are in the second chunk
1584 }
1585 
1586 // This is UltraSparc specific, true just means we have fast l2f conversion
1587 const bool Matcher::convL2FSupported(void) {
1588   return true;
1589 }
1590 
1591 // Is this branch offset short enough that a short branch can be used?
1592 //
1593 // NOTE: If the platform does not provide any short branch variants, then
1594 //       this method should return false for offset 0.
1595 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1596   // The passed offset is relative to address of the branch.
1597   // On 86 a branch displacement is calculated relative to address
1598   // of a next instruction.
1599   offset -= br_size;
1600 
1601   // the short version of jmpConUCF2 contains multiple branches,
1602   // making the reach slightly less
1603   if (rule == jmpConUCF2_rule)
1604     return (-126 <= offset && offset <= 125);
1605   return (-128 <= offset && offset <= 127);
1606 }
1607 
1608 const bool Matcher::isSimpleConstant64(jlong value) {
1609   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1610   //return value == (int) value;  // Cf. storeImmL and immL32.
1611 
1612   // Probably always true, even if a temp register is required.
1613   return true;
1614 }
1615 
1616 // The ecx parameter to rep stosq for the ClearArray node is in words.
1617 const bool Matcher::init_array_count_is_in_bytes = false;
1618 
1619 // No additional cost for CMOVL.
1620 const int Matcher::long_cmove_cost() { return 0; }
1621 
1622 // No CMOVF/CMOVD with SSE2
1623 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1624 
1625 // Does the CPU require late expand (see block.cpp for description of late expand)?
1626 const bool Matcher::require_postalloc_expand = false;
1627 
1628 // Do we need to mask the count passed to shift instructions or does
1629 // the cpu only look at the lower 5/6 bits anyway?
1630 const bool Matcher::need_masked_shift_count = false;
1631 
1632 bool Matcher::narrow_oop_use_complex_address() {
1633   assert(UseCompressedOops, "only for compressed oops code");
1634   return (LogMinObjAlignmentInBytes <= 3);
1635 }
1636 
1637 bool Matcher::narrow_klass_use_complex_address() {
1638   assert(UseCompressedClassPointers, "only for compressed klass code");
1639   return (LogKlassAlignmentInBytes <= 3);
1640 }
1641 
1642 bool Matcher::const_oop_prefer_decode() {
1643   // Prefer ConN+DecodeN over ConP.
1644   return true;
1645 }
1646 
1647 bool Matcher::const_klass_prefer_decode() {
1648   // Prefer ConP over ConNKlass+DecodeNKlass.
1649   return true;
1650 }
1651 
1652 // Is it better to copy float constants, or load them directly from
1653 // memory?  Intel can load a float constant from a direct address,
1654 // requiring no extra registers.  Most RISCs will have to materialize
1655 // an address into a register first, so they would do better to copy
1656 // the constant from stack.
1657 const bool Matcher::rematerialize_float_constants = true; // XXX
1658 
1659 // If CPU can load and store mis-aligned doubles directly then no
1660 // fixup is needed.  Else we split the double into 2 integer pieces
1661 // and move it piece-by-piece.  Only happens when passing doubles into
1662 // C code as the Java calling convention forces doubles to be aligned.
1663 const bool Matcher::misaligned_doubles_ok = true;
1664 
1665 // No-op on amd64
1666 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1667 
1668 // Advertise here if the CPU requires explicit rounding operations to implement strictfp mode.
1669 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1670 
1671 // Are floats conerted to double when stored to stack during deoptimization?
1672 // On x64 it is stored without convertion so we can use normal access.
1673 bool Matcher::float_in_double() { return false; }
1674 
1675 // Do ints take an entire long register or just half?
1676 const bool Matcher::int_in_long = true;
1677 
1678 // Return whether or not this register is ever used as an argument.
1679 // This function is used on startup to build the trampoline stubs in
1680 // generateOptoStub.  Registers not mentioned will be killed by the VM
1681 // call in the trampoline, and arguments in those registers not be
1682 // available to the callee.
1683 bool Matcher::can_be_java_arg(int reg)
1684 {
1685   return
1686     reg ==  RDI_num || reg == RDI_H_num ||
1687     reg ==  RSI_num || reg == RSI_H_num ||
1688     reg ==  RDX_num || reg == RDX_H_num ||
1689     reg ==  RCX_num || reg == RCX_H_num ||
1690     reg ==   R8_num || reg ==  R8_H_num ||
1691     reg ==   R9_num || reg ==  R9_H_num ||
1692     reg ==  R12_num || reg == R12_H_num ||
1693     reg == XMM0_num || reg == XMM0b_num ||
1694     reg == XMM1_num || reg == XMM1b_num ||
1695     reg == XMM2_num || reg == XMM2b_num ||
1696     reg == XMM3_num || reg == XMM3b_num ||
1697     reg == XMM4_num || reg == XMM4b_num ||
1698     reg == XMM5_num || reg == XMM5b_num ||
1699     reg == XMM6_num || reg == XMM6b_num ||
1700     reg == XMM7_num || reg == XMM7b_num;
1701 }
1702 
1703 bool Matcher::is_spillable_arg(int reg)
1704 {
1705   return can_be_java_arg(reg);
1706 }
1707 
1708 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1709   // In 64 bit mode a code which use multiply when
1710   // devisor is constant is faster than hardware
1711   // DIV instruction (it uses MulHiL).
1712   return false;
1713 }
1714 
1715 // Register for DIVI projection of divmodI
1716 RegMask Matcher::divI_proj_mask() {
1717   return INT_RAX_REG_mask();
1718 }
1719 
1720 // Register for MODI projection of divmodI
1721 RegMask Matcher::modI_proj_mask() {
1722   return INT_RDX_REG_mask();
1723 }
1724 
1725 // Register for DIVL projection of divmodL
1726 RegMask Matcher::divL_proj_mask() {
1727   return LONG_RAX_REG_mask();
1728 }
1729 
1730 // Register for MODL projection of divmodL
1731 RegMask Matcher::modL_proj_mask() {
1732   return LONG_RDX_REG_mask();
1733 }
1734 
1735 // Register for saving SP into on method handle invokes. Not used on x86_64.
1736 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1737     return NO_REG_mask();
1738 }
1739 
1740 %}
1741 
1742 //----------ENCODING BLOCK-----------------------------------------------------
1743 // This block specifies the encoding classes used by the compiler to
1744 // output byte streams.  Encoding classes are parameterized macros
1745 // used by Machine Instruction Nodes in order to generate the bit
1746 // encoding of the instruction.  Operands specify their base encoding
1747 // interface with the interface keyword.  There are currently
1748 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1749 // COND_INTER.  REG_INTER causes an operand to generate a function
1750 // which returns its register number when queried.  CONST_INTER causes
1751 // an operand to generate a function which returns the value of the
1752 // constant when queried.  MEMORY_INTER causes an operand to generate
1753 // four functions which return the Base Register, the Index Register,
1754 // the Scale Value, and the Offset Value of the operand when queried.
1755 // COND_INTER causes an operand to generate six functions which return
1756 // the encoding code (ie - encoding bits for the instruction)
1757 // associated with each basic boolean condition for a conditional
1758 // instruction.
1759 //
1760 // Instructions specify two basic values for encoding.  Again, a
1761 // function is available to check if the constant displacement is an
1762 // oop. They use the ins_encode keyword to specify their encoding
1763 // classes (which must be a sequence of enc_class names, and their
1764 // parameters, specified in the encoding block), and they use the
1765 // opcode keyword to specify, in order, their primary, secondary, and
1766 // tertiary opcode.  Only the opcode sections which a particular
1767 // instruction needs for encoding need to be specified.
1768 encode %{
1769   // Build emit functions for each basic byte or larger field in the
1770   // intel encoding scheme (opcode, rm, sib, immediate), and call them
1771   // from C++ code in the enc_class source block.  Emit functions will
1772   // live in the main source block for now.  In future, we can
1773   // generalize this by adding a syntax that specifies the sizes of
1774   // fields in an order, so that the adlc can build the emit functions
1775   // automagically
1776 
1777   // Emit primary opcode
1778   enc_class OpcP
1779   %{
1780     emit_opcode(cbuf, $primary);
1781   %}
1782 
1783   // Emit secondary opcode
1784   enc_class OpcS
1785   %{
1786     emit_opcode(cbuf, $secondary);
1787   %}
1788 
1789   // Emit tertiary opcode
1790   enc_class OpcT
1791   %{
1792     emit_opcode(cbuf, $tertiary);
1793   %}
1794 
1795   // Emit opcode directly
1796   enc_class Opcode(immI d8)
1797   %{
1798     emit_opcode(cbuf, $d8$$constant);
1799   %}
1800 
1801   // Emit size prefix
1802   enc_class SizePrefix
1803   %{
1804     emit_opcode(cbuf, 0x66);
1805   %}
1806 
1807   enc_class reg(rRegI reg)
1808   %{
1809     emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1810   %}
1811 
1812   enc_class reg_reg(rRegI dst, rRegI src)
1813   %{
1814     emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1815   %}
1816 
1817   enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1818   %{
1819     emit_opcode(cbuf, $opcode$$constant);
1820     emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1821   %}
1822 
1823   enc_class cdql_enc(no_rax_rdx_RegI div)
1824   %{
1825     // Full implementation of Java idiv and irem; checks for
1826     // special case as described in JVM spec., p.243 & p.271.
1827     //
1828     //         normal case                           special case
1829     //
1830     // input : rax: dividend                         min_int
1831     //         reg: divisor                          -1
1832     //
1833     // output: rax: quotient  (= rax idiv reg)       min_int
1834     //         rdx: remainder (= rax irem reg)       0
1835     //
1836     //  Code sequnce:
1837     //
1838     //    0:   3d 00 00 00 80          cmp    $0x80000000,%eax
1839     //    5:   75 07/08                jne    e <normal>
1840     //    7:   33 d2                   xor    %edx,%edx
1841     //  [div >= 8 -> offset + 1]
1842     //  [REX_B]
1843     //    9:   83 f9 ff                cmp    $0xffffffffffffffff,$div
1844     //    c:   74 03/04                je     11 <done>
1845     // 000000000000000e <normal>:
1846     //    e:   99                      cltd
1847     //  [div >= 8 -> offset + 1]
1848     //  [REX_B]
1849     //    f:   f7 f9                   idiv   $div
1850     // 0000000000000011 <done>:
1851 
1852     // cmp    $0x80000000,%eax
1853     emit_opcode(cbuf, 0x3d);
1854     emit_d8(cbuf, 0x00);
1855     emit_d8(cbuf, 0x00);
1856     emit_d8(cbuf, 0x00);
1857     emit_d8(cbuf, 0x80);
1858 
1859     // jne    e <normal>
1860     emit_opcode(cbuf, 0x75);
1861     emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1862 
1863     // xor    %edx,%edx
1864     emit_opcode(cbuf, 0x33);
1865     emit_d8(cbuf, 0xD2);
1866 
1867     // cmp    $0xffffffffffffffff,%ecx
1868     if ($div$$reg >= 8) {
1869       emit_opcode(cbuf, Assembler::REX_B);
1870     }
1871     emit_opcode(cbuf, 0x83);
1872     emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1873     emit_d8(cbuf, 0xFF);
1874 
1875     // je     11 <done>
1876     emit_opcode(cbuf, 0x74);
1877     emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1878 
1879     // <normal>
1880     // cltd
1881     emit_opcode(cbuf, 0x99);
1882 
1883     // idivl (note: must be emitted by the user of this rule)
1884     // <done>
1885   %}
1886 
1887   enc_class cdqq_enc(no_rax_rdx_RegL div)
1888   %{
1889     // Full implementation of Java ldiv and lrem; checks for
1890     // special case as described in JVM spec., p.243 & p.271.
1891     //
1892     //         normal case                           special case
1893     //
1894     // input : rax: dividend                         min_long
1895     //         reg: divisor                          -1
1896     //
1897     // output: rax: quotient  (= rax idiv reg)       min_long
1898     //         rdx: remainder (= rax irem reg)       0
1899     //
1900     //  Code sequnce:
1901     //
1902     //    0:   48 ba 00 00 00 00 00    mov    $0x8000000000000000,%rdx
1903     //    7:   00 00 80
1904     //    a:   48 39 d0                cmp    %rdx,%rax
1905     //    d:   75 08                   jne    17 <normal>
1906     //    f:   33 d2                   xor    %edx,%edx
1907     //   11:   48 83 f9 ff             cmp    $0xffffffffffffffff,$div
1908     //   15:   74 05                   je     1c <done>
1909     // 0000000000000017 <normal>:
1910     //   17:   48 99                   cqto
1911     //   19:   48 f7 f9                idiv   $div
1912     // 000000000000001c <done>:
1913 
1914     // mov    $0x8000000000000000,%rdx
1915     emit_opcode(cbuf, Assembler::REX_W);
1916     emit_opcode(cbuf, 0xBA);
1917     emit_d8(cbuf, 0x00);
1918     emit_d8(cbuf, 0x00);
1919     emit_d8(cbuf, 0x00);
1920     emit_d8(cbuf, 0x00);
1921     emit_d8(cbuf, 0x00);
1922     emit_d8(cbuf, 0x00);
1923     emit_d8(cbuf, 0x00);
1924     emit_d8(cbuf, 0x80);
1925 
1926     // cmp    %rdx,%rax
1927     emit_opcode(cbuf, Assembler::REX_W);
1928     emit_opcode(cbuf, 0x39);
1929     emit_d8(cbuf, 0xD0);
1930 
1931     // jne    17 <normal>
1932     emit_opcode(cbuf, 0x75);
1933     emit_d8(cbuf, 0x08);
1934 
1935     // xor    %edx,%edx
1936     emit_opcode(cbuf, 0x33);
1937     emit_d8(cbuf, 0xD2);
1938 
1939     // cmp    $0xffffffffffffffff,$div
1940     emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1941     emit_opcode(cbuf, 0x83);
1942     emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1943     emit_d8(cbuf, 0xFF);
1944 
1945     // je     1e <done>
1946     emit_opcode(cbuf, 0x74);
1947     emit_d8(cbuf, 0x05);
1948 
1949     // <normal>
1950     // cqto
1951     emit_opcode(cbuf, Assembler::REX_W);
1952     emit_opcode(cbuf, 0x99);
1953 
1954     // idivq (note: must be emitted by the user of this rule)
1955     // <done>
1956   %}
1957 
1958   // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1959   enc_class OpcSE(immI imm)
1960   %{
1961     // Emit primary opcode and set sign-extend bit
1962     // Check for 8-bit immediate, and set sign extend bit in opcode
1963     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1964       emit_opcode(cbuf, $primary | 0x02);
1965     } else {
1966       // 32-bit immediate
1967       emit_opcode(cbuf, $primary);
1968     }
1969   %}
1970 
1971   enc_class OpcSErm(rRegI dst, immI imm)
1972   %{
1973     // OpcSEr/m
1974     int dstenc = $dst$$reg;
1975     if (dstenc >= 8) {
1976       emit_opcode(cbuf, Assembler::REX_B);
1977       dstenc -= 8;
1978     }
1979     // Emit primary opcode and set sign-extend bit
1980     // Check for 8-bit immediate, and set sign extend bit in opcode
1981     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1982       emit_opcode(cbuf, $primary | 0x02);
1983     } else {
1984       // 32-bit immediate
1985       emit_opcode(cbuf, $primary);
1986     }
1987     // Emit r/m byte with secondary opcode, after primary opcode.
1988     emit_rm(cbuf, 0x3, $secondary, dstenc);
1989   %}
1990 
1991   enc_class OpcSErm_wide(rRegL dst, immI imm)
1992   %{
1993     // OpcSEr/m
1994     int dstenc = $dst$$reg;
1995     if (dstenc < 8) {
1996       emit_opcode(cbuf, Assembler::REX_W);
1997     } else {
1998       emit_opcode(cbuf, Assembler::REX_WB);
1999       dstenc -= 8;
2000     }
2001     // Emit primary opcode and set sign-extend bit
2002     // Check for 8-bit immediate, and set sign extend bit in opcode
2003     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2004       emit_opcode(cbuf, $primary | 0x02);
2005     } else {
2006       // 32-bit immediate
2007       emit_opcode(cbuf, $primary);
2008     }
2009     // Emit r/m byte with secondary opcode, after primary opcode.
2010     emit_rm(cbuf, 0x3, $secondary, dstenc);
2011   %}
2012 
2013   enc_class Con8or32(immI imm)
2014   %{
2015     // Check for 8-bit immediate, and set sign extend bit in opcode
2016     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2017       $$$emit8$imm$$constant;
2018     } else {
2019       // 32-bit immediate
2020       $$$emit32$imm$$constant;
2021     }
2022   %}
2023 
2024   enc_class opc2_reg(rRegI dst)
2025   %{
2026     // BSWAP
2027     emit_cc(cbuf, $secondary, $dst$$reg);
2028   %}
2029 
2030   enc_class opc3_reg(rRegI dst)
2031   %{
2032     // BSWAP
2033     emit_cc(cbuf, $tertiary, $dst$$reg);
2034   %}
2035 
2036   enc_class reg_opc(rRegI div)
2037   %{
2038     // INC, DEC, IDIV, IMOD, JMP indirect, ...
2039     emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2040   %}
2041 
2042   enc_class enc_cmov(cmpOp cop)
2043   %{
2044     // CMOV
2045     $$$emit8$primary;
2046     emit_cc(cbuf, $secondary, $cop$$cmpcode);
2047   %}
2048 
2049   enc_class enc_PartialSubtypeCheck()
2050   %{
2051     Register Rrdi = as_Register(RDI_enc); // result register
2052     Register Rrax = as_Register(RAX_enc); // super class
2053     Register Rrcx = as_Register(RCX_enc); // killed
2054     Register Rrsi = as_Register(RSI_enc); // sub class
2055     Label miss;
2056     const bool set_cond_codes = true;
2057 
2058     MacroAssembler _masm(&cbuf);
2059     __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2060                                      NULL, &miss,
2061                                      /*set_cond_codes:*/ true);
2062     if ($primary) {
2063       __ xorptr(Rrdi, Rrdi);
2064     }
2065     __ bind(miss);
2066   %}
2067 
2068   enc_class clear_avx %{
2069     debug_only(int off0 = cbuf.insts_size());
2070     if (generate_vzeroupper(Compile::current())) {
2071       // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2072       // Clear upper bits of YMM registers when current compiled code uses
2073       // wide vectors to avoid AVX <-> SSE transition penalty during call.
2074       MacroAssembler _masm(&cbuf);
2075       __ vzeroupper();
2076     }
2077     debug_only(int off1 = cbuf.insts_size());
2078     assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2079   %}
2080 
2081   enc_class Java_To_Runtime(method meth) %{
2082     // No relocation needed
2083     MacroAssembler _masm(&cbuf);
2084     __ mov64(r10, (int64_t) $meth$$method);
2085     __ call(r10);
2086   %}
2087 
2088   enc_class Java_To_Interpreter(method meth)
2089   %{
2090     // CALL Java_To_Interpreter
2091     // This is the instruction starting address for relocation info.
2092     cbuf.set_insts_mark();
2093     $$$emit8$primary;
2094     // CALL directly to the runtime
2095     emit_d32_reloc(cbuf,
2096                    (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2097                    runtime_call_Relocation::spec(),
2098                    RELOC_DISP32);
2099   %}
2100 
2101   enc_class Java_Static_Call(method meth)
2102   %{
2103     // JAVA STATIC CALL
2104     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to
2105     // determine who we intended to call.
2106     cbuf.set_insts_mark();
2107     $$$emit8$primary;
2108 
2109     if (!_method) {
2110       emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2111                      runtime_call_Relocation::spec(),
2112                      RELOC_DISP32);
2113     } else {
2114       int method_index = resolved_method_index(cbuf);
2115       RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2116                                                   : static_call_Relocation::spec(method_index);
2117       emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2118                      rspec, RELOC_DISP32);
2119       // Emit stubs for static call.
2120       address mark = cbuf.insts_mark();
2121       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2122       if (stub == NULL) {
2123         ciEnv::current()->record_failure("CodeCache is full");
2124         return;
2125       }
2126 #if INCLUDE_AOT
2127       CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2128 #endif
2129     }
2130   %}
2131 
2132   enc_class Java_Dynamic_Call(method meth) %{
2133     MacroAssembler _masm(&cbuf);
2134     __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2135   %}
2136 
2137   enc_class Java_Compiled_Call(method meth)
2138   %{
2139     // JAVA COMPILED CALL
2140     int disp = in_bytes(Method:: from_compiled_offset());
2141 
2142     // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2143     // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2144 
2145     // callq *disp(%rax)
2146     cbuf.set_insts_mark();
2147     $$$emit8$primary;
2148     if (disp < 0x80) {
2149       emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2150       emit_d8(cbuf, disp); // Displacement
2151     } else {
2152       emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2153       emit_d32(cbuf, disp); // Displacement
2154     }
2155   %}
2156 
2157   enc_class reg_opc_imm(rRegI dst, immI8 shift)
2158   %{
2159     // SAL, SAR, SHR
2160     int dstenc = $dst$$reg;
2161     if (dstenc >= 8) {
2162       emit_opcode(cbuf, Assembler::REX_B);
2163       dstenc -= 8;
2164     }
2165     $$$emit8$primary;
2166     emit_rm(cbuf, 0x3, $secondary, dstenc);
2167     $$$emit8$shift$$constant;
2168   %}
2169 
2170   enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2171   %{
2172     // SAL, SAR, SHR
2173     int dstenc = $dst$$reg;
2174     if (dstenc < 8) {
2175       emit_opcode(cbuf, Assembler::REX_W);
2176     } else {
2177       emit_opcode(cbuf, Assembler::REX_WB);
2178       dstenc -= 8;
2179     }
2180     $$$emit8$primary;
2181     emit_rm(cbuf, 0x3, $secondary, dstenc);
2182     $$$emit8$shift$$constant;
2183   %}
2184 
2185   enc_class load_immI(rRegI dst, immI src)
2186   %{
2187     int dstenc = $dst$$reg;
2188     if (dstenc >= 8) {
2189       emit_opcode(cbuf, Assembler::REX_B);
2190       dstenc -= 8;
2191     }
2192     emit_opcode(cbuf, 0xB8 | dstenc);
2193     $$$emit32$src$$constant;
2194   %}
2195 
2196   enc_class load_immL(rRegL dst, immL src)
2197   %{
2198     int dstenc = $dst$$reg;
2199     if (dstenc < 8) {
2200       emit_opcode(cbuf, Assembler::REX_W);
2201     } else {
2202       emit_opcode(cbuf, Assembler::REX_WB);
2203       dstenc -= 8;
2204     }
2205     emit_opcode(cbuf, 0xB8 | dstenc);
2206     emit_d64(cbuf, $src$$constant);
2207   %}
2208 
2209   enc_class load_immUL32(rRegL dst, immUL32 src)
2210   %{
2211     // same as load_immI, but this time we care about zeroes in the high word
2212     int dstenc = $dst$$reg;
2213     if (dstenc >= 8) {
2214       emit_opcode(cbuf, Assembler::REX_B);
2215       dstenc -= 8;
2216     }
2217     emit_opcode(cbuf, 0xB8 | dstenc);
2218     $$$emit32$src$$constant;
2219   %}
2220 
2221   enc_class load_immL32(rRegL dst, immL32 src)
2222   %{
2223     int dstenc = $dst$$reg;
2224     if (dstenc < 8) {
2225       emit_opcode(cbuf, Assembler::REX_W);
2226     } else {
2227       emit_opcode(cbuf, Assembler::REX_WB);
2228       dstenc -= 8;
2229     }
2230     emit_opcode(cbuf, 0xC7);
2231     emit_rm(cbuf, 0x03, 0x00, dstenc);
2232     $$$emit32$src$$constant;
2233   %}
2234 
2235   enc_class load_immP31(rRegP dst, immP32 src)
2236   %{
2237     // same as load_immI, but this time we care about zeroes in the high word
2238     int dstenc = $dst$$reg;
2239     if (dstenc >= 8) {
2240       emit_opcode(cbuf, Assembler::REX_B);
2241       dstenc -= 8;
2242     }
2243     emit_opcode(cbuf, 0xB8 | dstenc);
2244     $$$emit32$src$$constant;
2245   %}
2246 
2247   enc_class load_immP(rRegP dst, immP src)
2248   %{
2249     int dstenc = $dst$$reg;
2250     if (dstenc < 8) {
2251       emit_opcode(cbuf, Assembler::REX_W);
2252     } else {
2253       emit_opcode(cbuf, Assembler::REX_WB);
2254       dstenc -= 8;
2255     }
2256     emit_opcode(cbuf, 0xB8 | dstenc);
2257     // This next line should be generated from ADLC
2258     if ($src->constant_reloc() != relocInfo::none) {
2259       emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2260     } else {
2261       emit_d64(cbuf, $src$$constant);
2262     }
2263   %}
2264 
2265   enc_class Con32(immI src)
2266   %{
2267     // Output immediate
2268     $$$emit32$src$$constant;
2269   %}
2270 
2271   enc_class Con32F_as_bits(immF src)
2272   %{
2273     // Output Float immediate bits
2274     jfloat jf = $src$$constant;
2275     jint jf_as_bits = jint_cast(jf);
2276     emit_d32(cbuf, jf_as_bits);
2277   %}
2278 
2279   enc_class Con16(immI src)
2280   %{
2281     // Output immediate
2282     $$$emit16$src$$constant;
2283   %}
2284 
2285   // How is this different from Con32??? XXX
2286   enc_class Con_d32(immI src)
2287   %{
2288     emit_d32(cbuf,$src$$constant);
2289   %}
2290 
2291   enc_class conmemref (rRegP t1) %{    // Con32(storeImmI)
2292     // Output immediate memory reference
2293     emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2294     emit_d32(cbuf, 0x00);
2295   %}
2296 
2297   enc_class lock_prefix()
2298   %{
2299     emit_opcode(cbuf, 0xF0); // lock
2300   %}
2301 
2302   enc_class REX_mem(memory mem)
2303   %{
2304     if ($mem$$base >= 8) {
2305       if ($mem$$index < 8) {
2306         emit_opcode(cbuf, Assembler::REX_B);
2307       } else {
2308         emit_opcode(cbuf, Assembler::REX_XB);
2309       }
2310     } else {
2311       if ($mem$$index >= 8) {
2312         emit_opcode(cbuf, Assembler::REX_X);
2313       }
2314     }
2315   %}
2316 
2317   enc_class REX_mem_wide(memory mem)
2318   %{
2319     if ($mem$$base >= 8) {
2320       if ($mem$$index < 8) {
2321         emit_opcode(cbuf, Assembler::REX_WB);
2322       } else {
2323         emit_opcode(cbuf, Assembler::REX_WXB);
2324       }
2325     } else {
2326       if ($mem$$index < 8) {
2327         emit_opcode(cbuf, Assembler::REX_W);
2328       } else {
2329         emit_opcode(cbuf, Assembler::REX_WX);
2330       }
2331     }
2332   %}
2333 
2334   // for byte regs
2335   enc_class REX_breg(rRegI reg)
2336   %{
2337     if ($reg$$reg >= 4) {
2338       emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2339     }
2340   %}
2341 
2342   // for byte regs
2343   enc_class REX_reg_breg(rRegI dst, rRegI src)
2344   %{
2345     if ($dst$$reg < 8) {
2346       if ($src$$reg >= 4) {
2347         emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2348       }
2349     } else {
2350       if ($src$$reg < 8) {
2351         emit_opcode(cbuf, Assembler::REX_R);
2352       } else {
2353         emit_opcode(cbuf, Assembler::REX_RB);
2354       }
2355     }
2356   %}
2357 
2358   // for byte regs
2359   enc_class REX_breg_mem(rRegI reg, memory mem)
2360   %{
2361     if ($reg$$reg < 8) {
2362       if ($mem$$base < 8) {
2363         if ($mem$$index >= 8) {
2364           emit_opcode(cbuf, Assembler::REX_X);
2365         } else if ($reg$$reg >= 4) {
2366           emit_opcode(cbuf, Assembler::REX);
2367         }
2368       } else {
2369         if ($mem$$index < 8) {
2370           emit_opcode(cbuf, Assembler::REX_B);
2371         } else {
2372           emit_opcode(cbuf, Assembler::REX_XB);
2373         }
2374       }
2375     } else {
2376       if ($mem$$base < 8) {
2377         if ($mem$$index < 8) {
2378           emit_opcode(cbuf, Assembler::REX_R);
2379         } else {
2380           emit_opcode(cbuf, Assembler::REX_RX);
2381         }
2382       } else {
2383         if ($mem$$index < 8) {
2384           emit_opcode(cbuf, Assembler::REX_RB);
2385         } else {
2386           emit_opcode(cbuf, Assembler::REX_RXB);
2387         }
2388       }
2389     }
2390   %}
2391 
2392   enc_class REX_reg(rRegI reg)
2393   %{
2394     if ($reg$$reg >= 8) {
2395       emit_opcode(cbuf, Assembler::REX_B);
2396     }
2397   %}
2398 
2399   enc_class REX_reg_wide(rRegI reg)
2400   %{
2401     if ($reg$$reg < 8) {
2402       emit_opcode(cbuf, Assembler::REX_W);
2403     } else {
2404       emit_opcode(cbuf, Assembler::REX_WB);
2405     }
2406   %}
2407 
2408   enc_class REX_reg_reg(rRegI dst, rRegI src)
2409   %{
2410     if ($dst$$reg < 8) {
2411       if ($src$$reg >= 8) {
2412         emit_opcode(cbuf, Assembler::REX_B);
2413       }
2414     } else {
2415       if ($src$$reg < 8) {
2416         emit_opcode(cbuf, Assembler::REX_R);
2417       } else {
2418         emit_opcode(cbuf, Assembler::REX_RB);
2419       }
2420     }
2421   %}
2422 
2423   enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2424   %{
2425     if ($dst$$reg < 8) {
2426       if ($src$$reg < 8) {
2427         emit_opcode(cbuf, Assembler::REX_W);
2428       } else {
2429         emit_opcode(cbuf, Assembler::REX_WB);
2430       }
2431     } else {
2432       if ($src$$reg < 8) {
2433         emit_opcode(cbuf, Assembler::REX_WR);
2434       } else {
2435         emit_opcode(cbuf, Assembler::REX_WRB);
2436       }
2437     }
2438   %}
2439 
2440   enc_class REX_reg_mem(rRegI reg, memory mem)
2441   %{
2442     if ($reg$$reg < 8) {
2443       if ($mem$$base < 8) {
2444         if ($mem$$index >= 8) {
2445           emit_opcode(cbuf, Assembler::REX_X);
2446         }
2447       } else {
2448         if ($mem$$index < 8) {
2449           emit_opcode(cbuf, Assembler::REX_B);
2450         } else {
2451           emit_opcode(cbuf, Assembler::REX_XB);
2452         }
2453       }
2454     } else {
2455       if ($mem$$base < 8) {
2456         if ($mem$$index < 8) {
2457           emit_opcode(cbuf, Assembler::REX_R);
2458         } else {
2459           emit_opcode(cbuf, Assembler::REX_RX);
2460         }
2461       } else {
2462         if ($mem$$index < 8) {
2463           emit_opcode(cbuf, Assembler::REX_RB);
2464         } else {
2465           emit_opcode(cbuf, Assembler::REX_RXB);
2466         }
2467       }
2468     }
2469   %}
2470 
2471   enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2472   %{
2473     if ($reg$$reg < 8) {
2474       if ($mem$$base < 8) {
2475         if ($mem$$index < 8) {
2476           emit_opcode(cbuf, Assembler::REX_W);
2477         } else {
2478           emit_opcode(cbuf, Assembler::REX_WX);
2479         }
2480       } else {
2481         if ($mem$$index < 8) {
2482           emit_opcode(cbuf, Assembler::REX_WB);
2483         } else {
2484           emit_opcode(cbuf, Assembler::REX_WXB);
2485         }
2486       }
2487     } else {
2488       if ($mem$$base < 8) {
2489         if ($mem$$index < 8) {
2490           emit_opcode(cbuf, Assembler::REX_WR);
2491         } else {
2492           emit_opcode(cbuf, Assembler::REX_WRX);
2493         }
2494       } else {
2495         if ($mem$$index < 8) {
2496           emit_opcode(cbuf, Assembler::REX_WRB);
2497         } else {
2498           emit_opcode(cbuf, Assembler::REX_WRXB);
2499         }
2500       }
2501     }
2502   %}
2503 
2504   enc_class reg_mem(rRegI ereg, memory mem)
2505   %{
2506     // High registers handle in encode_RegMem
2507     int reg = $ereg$$reg;
2508     int base = $mem$$base;
2509     int index = $mem$$index;
2510     int scale = $mem$$scale;
2511     int disp = $mem$$disp;
2512     relocInfo::relocType disp_reloc = $mem->disp_reloc();
2513 
2514     encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2515   %}
2516 
2517   enc_class RM_opc_mem(immI rm_opcode, memory mem)
2518   %{
2519     int rm_byte_opcode = $rm_opcode$$constant;
2520 
2521     // High registers handle in encode_RegMem
2522     int base = $mem$$base;
2523     int index = $mem$$index;
2524     int scale = $mem$$scale;
2525     int displace = $mem$$disp;
2526 
2527     relocInfo::relocType disp_reloc = $mem->disp_reloc();       // disp-as-oop when
2528                                             // working with static
2529                                             // globals
2530     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2531                   disp_reloc);
2532   %}
2533 
2534   enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2535   %{
2536     int reg_encoding = $dst$$reg;
2537     int base         = $src0$$reg;      // 0xFFFFFFFF indicates no base
2538     int index        = 0x04;            // 0x04 indicates no index
2539     int scale        = 0x00;            // 0x00 indicates no scale
2540     int displace     = $src1$$constant; // 0x00 indicates no displacement
2541     relocInfo::relocType disp_reloc = relocInfo::none;
2542     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2543                   disp_reloc);
2544   %}
2545 
2546   enc_class neg_reg(rRegI dst)
2547   %{
2548     int dstenc = $dst$$reg;
2549     if (dstenc >= 8) {
2550       emit_opcode(cbuf, Assembler::REX_B);
2551       dstenc -= 8;
2552     }
2553     // NEG $dst
2554     emit_opcode(cbuf, 0xF7);
2555     emit_rm(cbuf, 0x3, 0x03, dstenc);
2556   %}
2557 
2558   enc_class neg_reg_wide(rRegI dst)
2559   %{
2560     int dstenc = $dst$$reg;
2561     if (dstenc < 8) {
2562       emit_opcode(cbuf, Assembler::REX_W);
2563     } else {
2564       emit_opcode(cbuf, Assembler::REX_WB);
2565       dstenc -= 8;
2566     }
2567     // NEG $dst
2568     emit_opcode(cbuf, 0xF7);
2569     emit_rm(cbuf, 0x3, 0x03, dstenc);
2570   %}
2571 
2572   enc_class setLT_reg(rRegI dst)
2573   %{
2574     int dstenc = $dst$$reg;
2575     if (dstenc >= 8) {
2576       emit_opcode(cbuf, Assembler::REX_B);
2577       dstenc -= 8;
2578     } else if (dstenc >= 4) {
2579       emit_opcode(cbuf, Assembler::REX);
2580     }
2581     // SETLT $dst
2582     emit_opcode(cbuf, 0x0F);
2583     emit_opcode(cbuf, 0x9C);
2584     emit_rm(cbuf, 0x3, 0x0, dstenc);
2585   %}
2586 
2587   enc_class setNZ_reg(rRegI dst)
2588   %{
2589     int dstenc = $dst$$reg;
2590     if (dstenc >= 8) {
2591       emit_opcode(cbuf, Assembler::REX_B);
2592       dstenc -= 8;
2593     } else if (dstenc >= 4) {
2594       emit_opcode(cbuf, Assembler::REX);
2595     }
2596     // SETNZ $dst
2597     emit_opcode(cbuf, 0x0F);
2598     emit_opcode(cbuf, 0x95);
2599     emit_rm(cbuf, 0x3, 0x0, dstenc);
2600   %}
2601 
2602 
2603   // Compare the lonogs and set -1, 0, or 1 into dst
2604   enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2605   %{
2606     int src1enc = $src1$$reg;
2607     int src2enc = $src2$$reg;
2608     int dstenc = $dst$$reg;
2609 
2610     // cmpq $src1, $src2
2611     if (src1enc < 8) {
2612       if (src2enc < 8) {
2613         emit_opcode(cbuf, Assembler::REX_W);
2614       } else {
2615         emit_opcode(cbuf, Assembler::REX_WB);
2616       }
2617     } else {
2618       if (src2enc < 8) {
2619         emit_opcode(cbuf, Assembler::REX_WR);
2620       } else {
2621         emit_opcode(cbuf, Assembler::REX_WRB);
2622       }
2623     }
2624     emit_opcode(cbuf, 0x3B);
2625     emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2626 
2627     // movl $dst, -1
2628     if (dstenc >= 8) {
2629       emit_opcode(cbuf, Assembler::REX_B);
2630     }
2631     emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2632     emit_d32(cbuf, -1);
2633 
2634     // jl,s done
2635     emit_opcode(cbuf, 0x7C);
2636     emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2637 
2638     // setne $dst
2639     if (dstenc >= 4) {
2640       emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2641     }
2642     emit_opcode(cbuf, 0x0F);
2643     emit_opcode(cbuf, 0x95);
2644     emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2645 
2646     // movzbl $dst, $dst
2647     if (dstenc >= 4) {
2648       emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2649     }
2650     emit_opcode(cbuf, 0x0F);
2651     emit_opcode(cbuf, 0xB6);
2652     emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2653   %}
2654 
2655   enc_class Push_ResultXD(regD dst) %{
2656     MacroAssembler _masm(&cbuf);
2657     __ fstp_d(Address(rsp, 0));
2658     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2659     __ addptr(rsp, 8);
2660   %}
2661 
2662   enc_class Push_SrcXD(regD src) %{
2663     MacroAssembler _masm(&cbuf);
2664     __ subptr(rsp, 8);
2665     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2666     __ fld_d(Address(rsp, 0));
2667   %}
2668 
2669 
2670   enc_class enc_rethrow()
2671   %{
2672     cbuf.set_insts_mark();
2673     emit_opcode(cbuf, 0xE9); // jmp entry
2674     emit_d32_reloc(cbuf,
2675                    (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2676                    runtime_call_Relocation::spec(),
2677                    RELOC_DISP32);
2678   %}
2679 
2680 %}
2681 
2682 
2683 
2684 //----------FRAME--------------------------------------------------------------
2685 // Definition of frame structure and management information.
2686 //
2687 //  S T A C K   L A Y O U T    Allocators stack-slot number
2688 //                             |   (to get allocators register number
2689 //  G  Owned by    |        |  v    add OptoReg::stack0())
2690 //  r   CALLER     |        |
2691 //  o     |        +--------+      pad to even-align allocators stack-slot
2692 //  w     V        |  pad0  |        numbers; owned by CALLER
2693 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
2694 //  h     ^        |   in   |  5
2695 //        |        |  args  |  4   Holes in incoming args owned by SELF
2696 //  |     |        |        |  3
2697 //  |     |        +--------+
2698 //  V     |        | old out|      Empty on Intel, window on Sparc
2699 //        |    old |preserve|      Must be even aligned.
2700 //        |     SP-+--------+----> Matcher::_old_SP, even aligned
2701 //        |        |   in   |  3   area for Intel ret address
2702 //     Owned by    |preserve|      Empty on Sparc.
2703 //       SELF      +--------+
2704 //        |        |  pad2  |  2   pad to align old SP
2705 //        |        +--------+  1
2706 //        |        | locks  |  0
2707 //        |        +--------+----> OptoReg::stack0(), even aligned
2708 //        |        |  pad1  | 11   pad to align new SP
2709 //        |        +--------+
2710 //        |        |        | 10
2711 //        |        | spills |  9   spills
2712 //        V        |        |  8   (pad0 slot for callee)
2713 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
2714 //        ^        |  out   |  7
2715 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
2716 //     Owned by    +--------+
2717 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
2718 //        |    new |preserve|      Must be even-aligned.
2719 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
2720 //        |        |        |
2721 //
2722 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
2723 //         known from SELF's arguments and the Java calling convention.
2724 //         Region 6-7 is determined per call site.
2725 // Note 2: If the calling convention leaves holes in the incoming argument
2726 //         area, those holes are owned by SELF.  Holes in the outgoing area
2727 //         are owned by the CALLEE.  Holes should not be nessecary in the
2728 //         incoming area, as the Java calling convention is completely under
2729 //         the control of the AD file.  Doubles can be sorted and packed to
2730 //         avoid holes.  Holes in the outgoing arguments may be nessecary for
2731 //         varargs C calling conventions.
2732 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
2733 //         even aligned with pad0 as needed.
2734 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
2735 //         region 6-11 is even aligned; it may be padded out more so that
2736 //         the region from SP to FP meets the minimum stack alignment.
2737 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2738 //         alignment.  Region 11, pad1, may be dynamically extended so that
2739 //         SP meets the minimum alignment.
2740 
2741 frame
2742 %{
2743   // What direction does stack grow in (assumed to be same for C & Java)
2744   stack_direction(TOWARDS_LOW);
2745 
2746   // These three registers define part of the calling convention
2747   // between compiled code and the interpreter.
2748   inline_cache_reg(RAX);                // Inline Cache Register
2749   interpreter_method_oop_reg(RBX);      // Method Oop Register when
2750                                         // calling interpreter
2751 
2752   // Optional: name the operand used by cisc-spilling to access
2753   // [stack_pointer + offset]
2754   cisc_spilling_operand_name(indOffset32);
2755 
2756   // Number of stack slots consumed by locking an object
2757   sync_stack_slots(2);
2758 
2759   // Compiled code's Frame Pointer
2760   frame_pointer(RSP);
2761 
2762   // Interpreter stores its frame pointer in a register which is
2763   // stored to the stack by I2CAdaptors.
2764   // I2CAdaptors convert from interpreted java to compiled java.
2765   interpreter_frame_pointer(RBP);
2766 
2767   // Stack alignment requirement
2768   stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2769 
2770   // Number of stack slots between incoming argument block and the start of
2771   // a new frame.  The PROLOG must add this many slots to the stack.  The
2772   // EPILOG must remove this many slots.  amd64 needs two slots for
2773   // return address.
2774   in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2775 
2776   // Number of outgoing stack slots killed above the out_preserve_stack_slots
2777   // for calls to C.  Supports the var-args backing area for register parms.
2778   varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2779 
2780   // The after-PROLOG location of the return address.  Location of
2781   // return address specifies a type (REG or STACK) and a number
2782   // representing the register number (i.e. - use a register name) or
2783   // stack slot.
2784   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2785   // Otherwise, it is above the locks and verification slot and alignment word
2786   return_addr(STACK - 2 +
2787               align_up((Compile::current()->in_preserve_stack_slots() +
2788                         Compile::current()->fixed_slots()),
2789                        stack_alignment_in_slots()));
2790 
2791   // Body of function which returns an integer array locating
2792   // arguments either in registers or in stack slots.  Passed an array
2793   // of ideal registers called "sig" and a "length" count.  Stack-slot
2794   // offsets are based on outgoing arguments, i.e. a CALLER setting up
2795   // arguments for a CALLEE.  Incoming stack arguments are
2796   // automatically biased by the preserve_stack_slots field above.
2797 
2798   calling_convention
2799   %{
2800     // No difference between ingoing/outgoing just pass false
2801     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2802   %}
2803 
2804   c_calling_convention
2805   %{
2806     // This is obviously always outgoing
2807     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2808   %}
2809 
2810   // Location of compiled Java return values.  Same as C for now.
2811   return_value
2812   %{
2813     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2814            "only return normal values");
2815 
2816     static const int lo[Op_RegL + 1] = {
2817       0,
2818       0,
2819       RAX_num,  // Op_RegN
2820       RAX_num,  // Op_RegI
2821       RAX_num,  // Op_RegP
2822       XMM0_num, // Op_RegF
2823       XMM0_num, // Op_RegD
2824       RAX_num   // Op_RegL
2825     };
2826     static const int hi[Op_RegL + 1] = {
2827       0,
2828       0,
2829       OptoReg::Bad, // Op_RegN
2830       OptoReg::Bad, // Op_RegI
2831       RAX_H_num,    // Op_RegP
2832       OptoReg::Bad, // Op_RegF
2833       XMM0b_num,    // Op_RegD
2834       RAX_H_num     // Op_RegL
2835     };
2836     // Excluded flags and vector registers.
2837     assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2838     return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2839   %}
2840 %}
2841 
2842 //----------ATTRIBUTES---------------------------------------------------------
2843 //----------Operand Attributes-------------------------------------------------
2844 op_attrib op_cost(0);        // Required cost attribute
2845 
2846 //----------Instruction Attributes---------------------------------------------
2847 ins_attrib ins_cost(100);       // Required cost attribute
2848 ins_attrib ins_size(8);         // Required size attribute (in bits)
2849 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2850                                 // a non-matching short branch variant
2851                                 // of some long branch?
2852 ins_attrib ins_alignment(1);    // Required alignment attribute (must
2853                                 // be a power of 2) specifies the
2854                                 // alignment that some part of the
2855                                 // instruction (not necessarily the
2856                                 // start) requires.  If > 1, a
2857                                 // compute_padding() function must be
2858                                 // provided for the instruction
2859 
2860 //----------OPERANDS-----------------------------------------------------------
2861 // Operand definitions must precede instruction definitions for correct parsing
2862 // in the ADLC because operands constitute user defined types which are used in
2863 // instruction definitions.
2864 
2865 //----------Simple Operands----------------------------------------------------
2866 // Immediate Operands
2867 // Integer Immediate
2868 operand immI()
2869 %{
2870   match(ConI);
2871 
2872   op_cost(10);
2873   format %{ %}
2874   interface(CONST_INTER);
2875 %}
2876 
2877 // Constant for test vs zero
2878 operand immI_0()
2879 %{
2880   predicate(n->get_int() == 0);
2881   match(ConI);
2882 
2883   op_cost(0);
2884   format %{ %}
2885   interface(CONST_INTER);
2886 %}
2887 
2888 // Constant for increment
2889 operand immI_1()
2890 %{
2891   predicate(n->get_int() == 1);
2892   match(ConI);
2893 
2894   op_cost(0);
2895   format %{ %}
2896   interface(CONST_INTER);
2897 %}
2898 
2899 // Constant for decrement
2900 operand immI_M1()
2901 %{
2902   predicate(n->get_int() == -1);
2903   match(ConI);
2904 
2905   op_cost(0);
2906   format %{ %}
2907   interface(CONST_INTER);
2908 %}
2909 
2910 operand immI_2()
2911 %{
2912   predicate(n->get_int() == 2);
2913   match(ConI);
2914 
2915   op_cost(0);
2916   format %{ %}
2917   interface(CONST_INTER);
2918 %}
2919 
2920 operand immI_4()
2921 %{
2922   predicate(n->get_int() == 4);
2923   match(ConI);
2924 
2925   op_cost(0);
2926   format %{ %}
2927   interface(CONST_INTER);
2928 %}
2929 
2930 operand immI_8()
2931 %{
2932   predicate(n->get_int() == 8);
2933   match(ConI);
2934 
2935   op_cost(0);
2936   format %{ %}
2937   interface(CONST_INTER);
2938 %}
2939 
2940 // Valid scale values for addressing modes
2941 operand immI2()
2942 %{
2943   predicate(0 <= n->get_int() && (n->get_int() <= 3));
2944   match(ConI);
2945 
2946   format %{ %}
2947   interface(CONST_INTER);
2948 %}
2949 
2950 operand immI8()
2951 %{
2952   predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2953   match(ConI);
2954 
2955   op_cost(5);
2956   format %{ %}
2957   interface(CONST_INTER);
2958 %}
2959 
2960 operand immU8()
2961 %{
2962   predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2963   match(ConI);
2964 
2965   op_cost(5);
2966   format %{ %}
2967   interface(CONST_INTER);
2968 %}
2969 
2970 operand immI16()
2971 %{
2972   predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2973   match(ConI);
2974 
2975   op_cost(10);
2976   format %{ %}
2977   interface(CONST_INTER);
2978 %}
2979 
2980 // Int Immediate non-negative
2981 operand immU31()
2982 %{
2983   predicate(n->get_int() >= 0);
2984   match(ConI);
2985 
2986   op_cost(0);
2987   format %{ %}
2988   interface(CONST_INTER);
2989 %}
2990 
2991 // Constant for long shifts
2992 operand immI_32()
2993 %{
2994   predicate( n->get_int() == 32 );
2995   match(ConI);
2996 
2997   op_cost(0);
2998   format %{ %}
2999   interface(CONST_INTER);
3000 %}
3001 
3002 // Constant for long shifts
3003 operand immI_64()
3004 %{
3005   predicate( n->get_int() == 64 );
3006   match(ConI);
3007 
3008   op_cost(0);
3009   format %{ %}
3010   interface(CONST_INTER);
3011 %}
3012 
3013 // Pointer Immediate
3014 operand immP()
3015 %{
3016   match(ConP);
3017 
3018   op_cost(10);
3019   format %{ %}
3020   interface(CONST_INTER);
3021 %}
3022 
3023 // NULL Pointer Immediate
3024 operand immP0()
3025 %{
3026   predicate(n->get_ptr() == 0);
3027   match(ConP);
3028 
3029   op_cost(5);
3030   format %{ %}
3031   interface(CONST_INTER);
3032 %}
3033 
3034 // Pointer Immediate
3035 operand immN() %{
3036   match(ConN);
3037 
3038   op_cost(10);
3039   format %{ %}
3040   interface(CONST_INTER);
3041 %}
3042 
3043 operand immNKlass() %{
3044   match(ConNKlass);
3045 
3046   op_cost(10);
3047   format %{ %}
3048   interface(CONST_INTER);
3049 %}
3050 
3051 // NULL Pointer Immediate
3052 operand immN0() %{
3053   predicate(n->get_narrowcon() == 0);
3054   match(ConN);
3055 
3056   op_cost(5);
3057   format %{ %}
3058   interface(CONST_INTER);
3059 %}
3060 
3061 operand immP31()
3062 %{
3063   predicate(n->as_Type()->type()->reloc() == relocInfo::none
3064             && (n->get_ptr() >> 31) == 0);
3065   match(ConP);
3066 
3067   op_cost(5);
3068   format %{ %}
3069   interface(CONST_INTER);
3070 %}
3071 
3072 
3073 // Long Immediate
3074 operand immL()
3075 %{
3076   match(ConL);
3077 
3078   op_cost(20);
3079   format %{ %}
3080   interface(CONST_INTER);
3081 %}
3082 
3083 // Long Immediate 8-bit
3084 operand immL8()
3085 %{
3086   predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3087   match(ConL);
3088 
3089   op_cost(5);
3090   format %{ %}
3091   interface(CONST_INTER);
3092 %}
3093 
3094 // Long Immediate 32-bit unsigned
3095 operand immUL32()
3096 %{
3097   predicate(n->get_long() == (unsigned int) (n->get_long()));
3098   match(ConL);
3099 
3100   op_cost(10);
3101   format %{ %}
3102   interface(CONST_INTER);
3103 %}
3104 
3105 // Long Immediate 32-bit signed
3106 operand immL32()
3107 %{
3108   predicate(n->get_long() == (int) (n->get_long()));
3109   match(ConL);
3110 
3111   op_cost(15);
3112   format %{ %}
3113   interface(CONST_INTER);
3114 %}
3115 
3116 operand immL_Pow2()
3117 %{
3118   predicate(is_power_of_2((julong)n->get_long()));
3119   match(ConL);
3120 
3121   op_cost(15);
3122   format %{ %}
3123   interface(CONST_INTER);
3124 %}
3125 
3126 operand immL_NotPow2()
3127 %{
3128   predicate(is_power_of_2((julong)~n->get_long()));
3129   match(ConL);
3130 
3131   op_cost(15);
3132   format %{ %}
3133   interface(CONST_INTER);
3134 %}
3135 
3136 // Long Immediate zero
3137 operand immL0()
3138 %{
3139   predicate(n->get_long() == 0L);
3140   match(ConL);
3141 
3142   op_cost(10);
3143   format %{ %}
3144   interface(CONST_INTER);
3145 %}
3146 
3147 // Constant for increment
3148 operand immL1()
3149 %{
3150   predicate(n->get_long() == 1);
3151   match(ConL);
3152 
3153   format %{ %}
3154   interface(CONST_INTER);
3155 %}
3156 
3157 // Constant for decrement
3158 operand immL_M1()
3159 %{
3160   predicate(n->get_long() == -1);
3161   match(ConL);
3162 
3163   format %{ %}
3164   interface(CONST_INTER);
3165 %}
3166 
3167 // Long Immediate: the value 10
3168 operand immL10()
3169 %{
3170   predicate(n->get_long() == 10);
3171   match(ConL);
3172 
3173   format %{ %}
3174   interface(CONST_INTER);
3175 %}
3176 
3177 // Long immediate from 0 to 127.
3178 // Used for a shorter form of long mul by 10.
3179 operand immL_127()
3180 %{
3181   predicate(0 <= n->get_long() && n->get_long() < 0x80);
3182   match(ConL);
3183 
3184   op_cost(10);
3185   format %{ %}
3186   interface(CONST_INTER);
3187 %}
3188 
3189 // Long Immediate: low 32-bit mask
3190 operand immL_32bits()
3191 %{
3192   predicate(n->get_long() == 0xFFFFFFFFL);
3193   match(ConL);
3194   op_cost(20);
3195 
3196   format %{ %}
3197   interface(CONST_INTER);
3198 %}
3199 
3200 // Float Immediate zero
3201 operand immF0()
3202 %{
3203   predicate(jint_cast(n->getf()) == 0);
3204   match(ConF);
3205 
3206   op_cost(5);
3207   format %{ %}
3208   interface(CONST_INTER);
3209 %}
3210 
3211 // Float Immediate
3212 operand immF()
3213 %{
3214   match(ConF);
3215 
3216   op_cost(15);
3217   format %{ %}
3218   interface(CONST_INTER);
3219 %}
3220 
3221 // Double Immediate zero
3222 operand immD0()
3223 %{
3224   predicate(jlong_cast(n->getd()) == 0);
3225   match(ConD);
3226 
3227   op_cost(5);
3228   format %{ %}
3229   interface(CONST_INTER);
3230 %}
3231 
3232 // Double Immediate
3233 operand immD()
3234 %{
3235   match(ConD);
3236 
3237   op_cost(15);
3238   format %{ %}
3239   interface(CONST_INTER);
3240 %}
3241 
3242 // Immediates for special shifts (sign extend)
3243 
3244 // Constants for increment
3245 operand immI_16()
3246 %{
3247   predicate(n->get_int() == 16);
3248   match(ConI);
3249 
3250   format %{ %}
3251   interface(CONST_INTER);
3252 %}
3253 
3254 operand immI_24()
3255 %{
3256   predicate(n->get_int() == 24);
3257   match(ConI);
3258 
3259   format %{ %}
3260   interface(CONST_INTER);
3261 %}
3262 
3263 // Constant for byte-wide masking
3264 operand immI_255()
3265 %{
3266   predicate(n->get_int() == 255);
3267   match(ConI);
3268 
3269   format %{ %}
3270   interface(CONST_INTER);
3271 %}
3272 
3273 // Constant for short-wide masking
3274 operand immI_65535()
3275 %{
3276   predicate(n->get_int() == 65535);
3277   match(ConI);
3278 
3279   format %{ %}
3280   interface(CONST_INTER);
3281 %}
3282 
3283 // Constant for byte-wide masking
3284 operand immL_255()
3285 %{
3286   predicate(n->get_long() == 255);
3287   match(ConL);
3288 
3289   format %{ %}
3290   interface(CONST_INTER);
3291 %}
3292 
3293 // Constant for short-wide masking
3294 operand immL_65535()
3295 %{
3296   predicate(n->get_long() == 65535);
3297   match(ConL);
3298 
3299   format %{ %}
3300   interface(CONST_INTER);
3301 %}
3302 
3303 // Register Operands
3304 // Integer Register
3305 operand rRegI()
3306 %{
3307   constraint(ALLOC_IN_RC(int_reg));
3308   match(RegI);
3309 
3310   match(rax_RegI);
3311   match(rbx_RegI);
3312   match(rcx_RegI);
3313   match(rdx_RegI);
3314   match(rdi_RegI);
3315 
3316   format %{ %}
3317   interface(REG_INTER);
3318 %}
3319 
3320 // Special Registers
3321 operand rax_RegI()
3322 %{
3323   constraint(ALLOC_IN_RC(int_rax_reg));
3324   match(RegI);
3325   match(rRegI);
3326 
3327   format %{ "RAX" %}
3328   interface(REG_INTER);
3329 %}
3330 
3331 // Special Registers
3332 operand rbx_RegI()
3333 %{
3334   constraint(ALLOC_IN_RC(int_rbx_reg));
3335   match(RegI);
3336   match(rRegI);
3337 
3338   format %{ "RBX" %}
3339   interface(REG_INTER);
3340 %}
3341 
3342 operand rcx_RegI()
3343 %{
3344   constraint(ALLOC_IN_RC(int_rcx_reg));
3345   match(RegI);
3346   match(rRegI);
3347 
3348   format %{ "RCX" %}
3349   interface(REG_INTER);
3350 %}
3351 
3352 operand rdx_RegI()
3353 %{
3354   constraint(ALLOC_IN_RC(int_rdx_reg));
3355   match(RegI);
3356   match(rRegI);
3357 
3358   format %{ "RDX" %}
3359   interface(REG_INTER);
3360 %}
3361 
3362 operand rdi_RegI()
3363 %{
3364   constraint(ALLOC_IN_RC(int_rdi_reg));
3365   match(RegI);
3366   match(rRegI);
3367 
3368   format %{ "RDI" %}
3369   interface(REG_INTER);
3370 %}
3371 
3372 operand no_rcx_RegI()
3373 %{
3374   constraint(ALLOC_IN_RC(int_no_rcx_reg));
3375   match(RegI);
3376   match(rax_RegI);
3377   match(rbx_RegI);
3378   match(rdx_RegI);
3379   match(rdi_RegI);
3380 
3381   format %{ %}
3382   interface(REG_INTER);
3383 %}
3384 
3385 operand no_rax_rdx_RegI()
3386 %{
3387   constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3388   match(RegI);
3389   match(rbx_RegI);
3390   match(rcx_RegI);
3391   match(rdi_RegI);
3392 
3393   format %{ %}
3394   interface(REG_INTER);
3395 %}
3396 
3397 // Pointer Register
3398 operand any_RegP()
3399 %{
3400   constraint(ALLOC_IN_RC(any_reg));
3401   match(RegP);
3402   match(rax_RegP);
3403   match(rbx_RegP);
3404   match(rdi_RegP);
3405   match(rsi_RegP);
3406   match(rbp_RegP);
3407   match(r15_RegP);
3408   match(rRegP);
3409 
3410   format %{ %}
3411   interface(REG_INTER);
3412 %}
3413 
3414 operand rRegP()
3415 %{
3416   constraint(ALLOC_IN_RC(ptr_reg));
3417   match(RegP);
3418   match(rax_RegP);
3419   match(rbx_RegP);
3420   match(rdi_RegP);
3421   match(rsi_RegP);
3422   match(rbp_RegP);  // See Q&A below about
3423   match(r15_RegP);  // r15_RegP and rbp_RegP.
3424 
3425   format %{ %}
3426   interface(REG_INTER);
3427 %}
3428 
3429 operand rRegN() %{
3430   constraint(ALLOC_IN_RC(int_reg));
3431   match(RegN);
3432 
3433   format %{ %}
3434   interface(REG_INTER);
3435 %}
3436 
3437 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3438 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3439 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3440 // The output of an instruction is controlled by the allocator, which respects
3441 // register class masks, not match rules.  Unless an instruction mentions
3442 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3443 // by the allocator as an input.
3444 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3445 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3446 // result, RBP is not included in the output of the instruction either.
3447 
3448 operand no_rax_RegP()
3449 %{
3450   constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3451   match(RegP);
3452   match(rbx_RegP);
3453   match(rsi_RegP);
3454   match(rdi_RegP);
3455 
3456   format %{ %}
3457   interface(REG_INTER);
3458 %}
3459 
3460 // This operand is not allowed to use RBP even if
3461 // RBP is not used to hold the frame pointer.
3462 operand no_rbp_RegP()
3463 %{
3464   constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3465   match(RegP);
3466   match(rbx_RegP);
3467   match(rsi_RegP);
3468   match(rdi_RegP);
3469 
3470   format %{ %}
3471   interface(REG_INTER);
3472 %}
3473 
3474 operand no_rax_rbx_RegP()
3475 %{
3476   constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3477   match(RegP);
3478   match(rsi_RegP);
3479   match(rdi_RegP);
3480 
3481   format %{ %}
3482   interface(REG_INTER);
3483 %}
3484 
3485 // Special Registers
3486 // Return a pointer value
3487 operand rax_RegP()
3488 %{
3489   constraint(ALLOC_IN_RC(ptr_rax_reg));
3490   match(RegP);
3491   match(rRegP);
3492 
3493   format %{ %}
3494   interface(REG_INTER);
3495 %}
3496 
3497 // Special Registers
3498 // Return a compressed pointer value
3499 operand rax_RegN()
3500 %{
3501   constraint(ALLOC_IN_RC(int_rax_reg));
3502   match(RegN);
3503   match(rRegN);
3504 
3505   format %{ %}
3506   interface(REG_INTER);
3507 %}
3508 
3509 // Used in AtomicAdd
3510 operand rbx_RegP()
3511 %{
3512   constraint(ALLOC_IN_RC(ptr_rbx_reg));
3513   match(RegP);
3514   match(rRegP);
3515 
3516   format %{ %}
3517   interface(REG_INTER);
3518 %}
3519 
3520 operand rsi_RegP()
3521 %{
3522   constraint(ALLOC_IN_RC(ptr_rsi_reg));
3523   match(RegP);
3524   match(rRegP);
3525 
3526   format %{ %}
3527   interface(REG_INTER);
3528 %}
3529 
3530 operand rbp_RegP()
3531 %{
3532   constraint(ALLOC_IN_RC(ptr_rbp_reg));
3533   match(RegP);
3534   match(rRegP);
3535 
3536   format %{ %}
3537   interface(REG_INTER);
3538 %}
3539 
3540 // Used in rep stosq
3541 operand rdi_RegP()
3542 %{
3543   constraint(ALLOC_IN_RC(ptr_rdi_reg));
3544   match(RegP);
3545   match(rRegP);
3546 
3547   format %{ %}
3548   interface(REG_INTER);
3549 %}
3550 
3551 operand r15_RegP()
3552 %{
3553   constraint(ALLOC_IN_RC(ptr_r15_reg));
3554   match(RegP);
3555   match(rRegP);
3556 
3557   format %{ %}
3558   interface(REG_INTER);
3559 %}
3560 
3561 operand rRegL()
3562 %{
3563   constraint(ALLOC_IN_RC(long_reg));
3564   match(RegL);
3565   match(rax_RegL);
3566   match(rdx_RegL);
3567 
3568   format %{ %}
3569   interface(REG_INTER);
3570 %}
3571 
3572 // Special Registers
3573 operand no_rax_rdx_RegL()
3574 %{
3575   constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3576   match(RegL);
3577   match(rRegL);
3578 
3579   format %{ %}
3580   interface(REG_INTER);
3581 %}
3582 
3583 operand no_rax_RegL()
3584 %{
3585   constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3586   match(RegL);
3587   match(rRegL);
3588   match(rdx_RegL);
3589 
3590   format %{ %}
3591   interface(REG_INTER);
3592 %}
3593 
3594 operand no_rcx_RegL()
3595 %{
3596   constraint(ALLOC_IN_RC(long_no_rcx_reg));
3597   match(RegL);
3598   match(rRegL);
3599 
3600   format %{ %}
3601   interface(REG_INTER);
3602 %}
3603 
3604 operand rax_RegL()
3605 %{
3606   constraint(ALLOC_IN_RC(long_rax_reg));
3607   match(RegL);
3608   match(rRegL);
3609 
3610   format %{ "RAX" %}
3611   interface(REG_INTER);
3612 %}
3613 
3614 operand rcx_RegL()
3615 %{
3616   constraint(ALLOC_IN_RC(long_rcx_reg));
3617   match(RegL);
3618   match(rRegL);
3619 
3620   format %{ %}
3621   interface(REG_INTER);
3622 %}
3623 
3624 operand rdx_RegL()
3625 %{
3626   constraint(ALLOC_IN_RC(long_rdx_reg));
3627   match(RegL);
3628   match(rRegL);
3629 
3630   format %{ %}
3631   interface(REG_INTER);
3632 %}
3633 
3634 // Flags register, used as output of compare instructions
3635 operand rFlagsReg()
3636 %{
3637   constraint(ALLOC_IN_RC(int_flags));
3638   match(RegFlags);
3639 
3640   format %{ "RFLAGS" %}
3641   interface(REG_INTER);
3642 %}
3643 
3644 // Flags register, used as output of FLOATING POINT compare instructions
3645 operand rFlagsRegU()
3646 %{
3647   constraint(ALLOC_IN_RC(int_flags));
3648   match(RegFlags);
3649 
3650   format %{ "RFLAGS_U" %}
3651   interface(REG_INTER);
3652 %}
3653 
3654 operand rFlagsRegUCF() %{
3655   constraint(ALLOC_IN_RC(int_flags));
3656   match(RegFlags);
3657   predicate(false);
3658 
3659   format %{ "RFLAGS_U_CF" %}
3660   interface(REG_INTER);
3661 %}
3662 
3663 // Float register operands
3664 operand regF() %{
3665    constraint(ALLOC_IN_RC(float_reg));
3666    match(RegF);
3667 
3668    format %{ %}
3669    interface(REG_INTER);
3670 %}
3671 
3672 // Float register operands
3673 operand legRegF() %{
3674    constraint(ALLOC_IN_RC(float_reg_legacy));
3675    match(RegF);
3676 
3677    format %{ %}
3678    interface(REG_INTER);
3679 %}
3680 
3681 // Float register operands
3682 operand vlRegF() %{
3683    constraint(ALLOC_IN_RC(float_reg_vl));
3684    match(RegF);
3685 
3686    format %{ %}
3687    interface(REG_INTER);
3688 %}
3689 
3690 // Double register operands
3691 operand regD() %{
3692    constraint(ALLOC_IN_RC(double_reg));
3693    match(RegD);
3694 
3695    format %{ %}
3696    interface(REG_INTER);
3697 %}
3698 
3699 // Double register operands
3700 operand legRegD() %{
3701    constraint(ALLOC_IN_RC(double_reg_legacy));
3702    match(RegD);
3703 
3704    format %{ %}
3705    interface(REG_INTER);
3706 %}
3707 
3708 // Double register operands
3709 operand vlRegD() %{
3710    constraint(ALLOC_IN_RC(double_reg_vl));
3711    match(RegD);
3712 
3713    format %{ %}
3714    interface(REG_INTER);
3715 %}
3716 
3717 //----------Memory Operands----------------------------------------------------
3718 // Direct Memory Operand
3719 // operand direct(immP addr)
3720 // %{
3721 //   match(addr);
3722 
3723 //   format %{ "[$addr]" %}
3724 //   interface(MEMORY_INTER) %{
3725 //     base(0xFFFFFFFF);
3726 //     index(0x4);
3727 //     scale(0x0);
3728 //     disp($addr);
3729 //   %}
3730 // %}
3731 
3732 // Indirect Memory Operand
3733 operand indirect(any_RegP reg)
3734 %{
3735   constraint(ALLOC_IN_RC(ptr_reg));
3736   match(reg);
3737 
3738   format %{ "[$reg]" %}
3739   interface(MEMORY_INTER) %{
3740     base($reg);
3741     index(0x4);
3742     scale(0x0);
3743     disp(0x0);
3744   %}
3745 %}
3746 
3747 // Indirect Memory Plus Short Offset Operand
3748 operand indOffset8(any_RegP reg, immL8 off)
3749 %{
3750   constraint(ALLOC_IN_RC(ptr_reg));
3751   match(AddP reg off);
3752 
3753   format %{ "[$reg + $off (8-bit)]" %}
3754   interface(MEMORY_INTER) %{
3755     base($reg);
3756     index(0x4);
3757     scale(0x0);
3758     disp($off);
3759   %}
3760 %}
3761 
3762 // Indirect Memory Plus Long Offset Operand
3763 operand indOffset32(any_RegP reg, immL32 off)
3764 %{
3765   constraint(ALLOC_IN_RC(ptr_reg));
3766   match(AddP reg off);
3767 
3768   format %{ "[$reg + $off (32-bit)]" %}
3769   interface(MEMORY_INTER) %{
3770     base($reg);
3771     index(0x4);
3772     scale(0x0);
3773     disp($off);
3774   %}
3775 %}
3776 
3777 // Indirect Memory Plus Index Register Plus Offset Operand
3778 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3779 %{
3780   constraint(ALLOC_IN_RC(ptr_reg));
3781   match(AddP (AddP reg lreg) off);
3782 
3783   op_cost(10);
3784   format %{"[$reg + $off + $lreg]" %}
3785   interface(MEMORY_INTER) %{
3786     base($reg);
3787     index($lreg);
3788     scale(0x0);
3789     disp($off);
3790   %}
3791 %}
3792 
3793 // Indirect Memory Plus Index Register Plus Offset Operand
3794 operand indIndex(any_RegP reg, rRegL lreg)
3795 %{
3796   constraint(ALLOC_IN_RC(ptr_reg));
3797   match(AddP reg lreg);
3798 
3799   op_cost(10);
3800   format %{"[$reg + $lreg]" %}
3801   interface(MEMORY_INTER) %{
3802     base($reg);
3803     index($lreg);
3804     scale(0x0);
3805     disp(0x0);
3806   %}
3807 %}
3808 
3809 // Indirect Memory Times Scale Plus Index Register
3810 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3811 %{
3812   constraint(ALLOC_IN_RC(ptr_reg));
3813   match(AddP reg (LShiftL lreg scale));
3814 
3815   op_cost(10);
3816   format %{"[$reg + $lreg << $scale]" %}
3817   interface(MEMORY_INTER) %{
3818     base($reg);
3819     index($lreg);
3820     scale($scale);
3821     disp(0x0);
3822   %}
3823 %}
3824 
3825 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3826 %{
3827   constraint(ALLOC_IN_RC(ptr_reg));
3828   predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3829   match(AddP reg (LShiftL (ConvI2L idx) scale));
3830 
3831   op_cost(10);
3832   format %{"[$reg + pos $idx << $scale]" %}
3833   interface(MEMORY_INTER) %{
3834     base($reg);
3835     index($idx);
3836     scale($scale);
3837     disp(0x0);
3838   %}
3839 %}
3840 
3841 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3842 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3843 %{
3844   constraint(ALLOC_IN_RC(ptr_reg));
3845   match(AddP (AddP reg (LShiftL lreg scale)) off);
3846 
3847   op_cost(10);
3848   format %{"[$reg + $off + $lreg << $scale]" %}
3849   interface(MEMORY_INTER) %{
3850     base($reg);
3851     index($lreg);
3852     scale($scale);
3853     disp($off);
3854   %}
3855 %}
3856 
3857 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3858 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3859 %{
3860   constraint(ALLOC_IN_RC(ptr_reg));
3861   predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3862   match(AddP (AddP reg (ConvI2L idx)) off);
3863 
3864   op_cost(10);
3865   format %{"[$reg + $off + $idx]" %}
3866   interface(MEMORY_INTER) %{
3867     base($reg);
3868     index($idx);
3869     scale(0x0);
3870     disp($off);
3871   %}
3872 %}
3873 
3874 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3875 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3876 %{
3877   constraint(ALLOC_IN_RC(ptr_reg));
3878   predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3879   match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3880 
3881   op_cost(10);
3882   format %{"[$reg + $off + $idx << $scale]" %}
3883   interface(MEMORY_INTER) %{
3884     base($reg);
3885     index($idx);
3886     scale($scale);
3887     disp($off);
3888   %}
3889 %}
3890 
3891 // Indirect Narrow Oop Plus Offset Operand
3892 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3893 // we can't free r12 even with CompressedOops::base() == NULL.
3894 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3895   predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3896   constraint(ALLOC_IN_RC(ptr_reg));
3897   match(AddP (DecodeN reg) off);
3898 
3899   op_cost(10);
3900   format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3901   interface(MEMORY_INTER) %{
3902     base(0xc); // R12
3903     index($reg);
3904     scale(0x3);
3905     disp($off);
3906   %}
3907 %}
3908 
3909 // Indirect Memory Operand
3910 operand indirectNarrow(rRegN reg)
3911 %{
3912   predicate(CompressedOops::shift() == 0);
3913   constraint(ALLOC_IN_RC(ptr_reg));
3914   match(DecodeN reg);
3915 
3916   format %{ "[$reg]" %}
3917   interface(MEMORY_INTER) %{
3918     base($reg);
3919     index(0x4);
3920     scale(0x0);
3921     disp(0x0);
3922   %}
3923 %}
3924 
3925 // Indirect Memory Plus Short Offset Operand
3926 operand indOffset8Narrow(rRegN reg, immL8 off)
3927 %{
3928   predicate(CompressedOops::shift() == 0);
3929   constraint(ALLOC_IN_RC(ptr_reg));
3930   match(AddP (DecodeN reg) off);
3931 
3932   format %{ "[$reg + $off (8-bit)]" %}
3933   interface(MEMORY_INTER) %{
3934     base($reg);
3935     index(0x4);
3936     scale(0x0);
3937     disp($off);
3938   %}
3939 %}
3940 
3941 // Indirect Memory Plus Long Offset Operand
3942 operand indOffset32Narrow(rRegN reg, immL32 off)
3943 %{
3944   predicate(CompressedOops::shift() == 0);
3945   constraint(ALLOC_IN_RC(ptr_reg));
3946   match(AddP (DecodeN reg) off);
3947 
3948   format %{ "[$reg + $off (32-bit)]" %}
3949   interface(MEMORY_INTER) %{
3950     base($reg);
3951     index(0x4);
3952     scale(0x0);
3953     disp($off);
3954   %}
3955 %}
3956 
3957 // Indirect Memory Plus Index Register Plus Offset Operand
3958 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3959 %{
3960   predicate(CompressedOops::shift() == 0);
3961   constraint(ALLOC_IN_RC(ptr_reg));
3962   match(AddP (AddP (DecodeN reg) lreg) off);
3963 
3964   op_cost(10);
3965   format %{"[$reg + $off + $lreg]" %}
3966   interface(MEMORY_INTER) %{
3967     base($reg);
3968     index($lreg);
3969     scale(0x0);
3970     disp($off);
3971   %}
3972 %}
3973 
3974 // Indirect Memory Plus Index Register Plus Offset Operand
3975 operand indIndexNarrow(rRegN reg, rRegL lreg)
3976 %{
3977   predicate(CompressedOops::shift() == 0);
3978   constraint(ALLOC_IN_RC(ptr_reg));
3979   match(AddP (DecodeN reg) lreg);
3980 
3981   op_cost(10);
3982   format %{"[$reg + $lreg]" %}
3983   interface(MEMORY_INTER) %{
3984     base($reg);
3985     index($lreg);
3986     scale(0x0);
3987     disp(0x0);
3988   %}
3989 %}
3990 
3991 // Indirect Memory Times Scale Plus Index Register
3992 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3993 %{
3994   predicate(CompressedOops::shift() == 0);
3995   constraint(ALLOC_IN_RC(ptr_reg));
3996   match(AddP (DecodeN reg) (LShiftL lreg scale));
3997 
3998   op_cost(10);
3999   format %{"[$reg + $lreg << $scale]" %}
4000   interface(MEMORY_INTER) %{
4001     base($reg);
4002     index($lreg);
4003     scale($scale);
4004     disp(0x0);
4005   %}
4006 %}
4007 
4008 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4009 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4010 %{
4011   predicate(CompressedOops::shift() == 0);
4012   constraint(ALLOC_IN_RC(ptr_reg));
4013   match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4014 
4015   op_cost(10);
4016   format %{"[$reg + $off + $lreg << $scale]" %}
4017   interface(MEMORY_INTER) %{
4018     base($reg);
4019     index($lreg);
4020     scale($scale);
4021     disp($off);
4022   %}
4023 %}
4024 
4025 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4026 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4027 %{
4028   constraint(ALLOC_IN_RC(ptr_reg));
4029   predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4030   match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4031 
4032   op_cost(10);
4033   format %{"[$reg + $off + $idx]" %}
4034   interface(MEMORY_INTER) %{
4035     base($reg);
4036     index($idx);
4037     scale(0x0);
4038     disp($off);
4039   %}
4040 %}
4041 
4042 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4043 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4044 %{
4045   constraint(ALLOC_IN_RC(ptr_reg));
4046   predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4047   match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4048 
4049   op_cost(10);
4050   format %{"[$reg + $off + $idx << $scale]" %}
4051   interface(MEMORY_INTER) %{
4052     base($reg);
4053     index($idx);
4054     scale($scale);
4055     disp($off);
4056   %}
4057 %}
4058 
4059 //----------Special Memory Operands--------------------------------------------
4060 // Stack Slot Operand - This operand is used for loading and storing temporary
4061 //                      values on the stack where a match requires a value to
4062 //                      flow through memory.
4063 operand stackSlotP(sRegP reg)
4064 %{
4065   constraint(ALLOC_IN_RC(stack_slots));
4066   // No match rule because this operand is only generated in matching
4067 
4068   format %{ "[$reg]" %}
4069   interface(MEMORY_INTER) %{
4070     base(0x4);   // RSP
4071     index(0x4);  // No Index
4072     scale(0x0);  // No Scale
4073     disp($reg);  // Stack Offset
4074   %}
4075 %}
4076 
4077 operand stackSlotI(sRegI reg)
4078 %{
4079   constraint(ALLOC_IN_RC(stack_slots));
4080   // No match rule because this operand is only generated in matching
4081 
4082   format %{ "[$reg]" %}
4083   interface(MEMORY_INTER) %{
4084     base(0x4);   // RSP
4085     index(0x4);  // No Index
4086     scale(0x0);  // No Scale
4087     disp($reg);  // Stack Offset
4088   %}
4089 %}
4090 
4091 operand stackSlotF(sRegF reg)
4092 %{
4093   constraint(ALLOC_IN_RC(stack_slots));
4094   // No match rule because this operand is only generated in matching
4095 
4096   format %{ "[$reg]" %}
4097   interface(MEMORY_INTER) %{
4098     base(0x4);   // RSP
4099     index(0x4);  // No Index
4100     scale(0x0);  // No Scale
4101     disp($reg);  // Stack Offset
4102   %}
4103 %}
4104 
4105 operand stackSlotD(sRegD reg)
4106 %{
4107   constraint(ALLOC_IN_RC(stack_slots));
4108   // No match rule because this operand is only generated in matching
4109 
4110   format %{ "[$reg]" %}
4111   interface(MEMORY_INTER) %{
4112     base(0x4);   // RSP
4113     index(0x4);  // No Index
4114     scale(0x0);  // No Scale
4115     disp($reg);  // Stack Offset
4116   %}
4117 %}
4118 operand stackSlotL(sRegL reg)
4119 %{
4120   constraint(ALLOC_IN_RC(stack_slots));
4121   // No match rule because this operand is only generated in matching
4122 
4123   format %{ "[$reg]" %}
4124   interface(MEMORY_INTER) %{
4125     base(0x4);   // RSP
4126     index(0x4);  // No Index
4127     scale(0x0);  // No Scale
4128     disp($reg);  // Stack Offset
4129   %}
4130 %}
4131 
4132 //----------Conditional Branch Operands----------------------------------------
4133 // Comparison Op  - This is the operation of the comparison, and is limited to
4134 //                  the following set of codes:
4135 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4136 //
4137 // Other attributes of the comparison, such as unsignedness, are specified
4138 // by the comparison instruction that sets a condition code flags register.
4139 // That result is represented by a flags operand whose subtype is appropriate
4140 // to the unsignedness (etc.) of the comparison.
4141 //
4142 // Later, the instruction which matches both the Comparison Op (a Bool) and
4143 // the flags (produced by the Cmp) specifies the coding of the comparison op
4144 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4145 
4146 // Comparision Code
4147 operand cmpOp()
4148 %{
4149   match(Bool);
4150 
4151   format %{ "" %}
4152   interface(COND_INTER) %{
4153     equal(0x4, "e");
4154     not_equal(0x5, "ne");
4155     less(0xC, "l");
4156     greater_equal(0xD, "ge");
4157     less_equal(0xE, "le");
4158     greater(0xF, "g");
4159     overflow(0x0, "o");
4160     no_overflow(0x1, "no");
4161   %}
4162 %}
4163 
4164 // Comparison Code, unsigned compare.  Used by FP also, with
4165 // C2 (unordered) turned into GT or LT already.  The other bits
4166 // C0 and C3 are turned into Carry & Zero flags.
4167 operand cmpOpU()
4168 %{
4169   match(Bool);
4170 
4171   format %{ "" %}
4172   interface(COND_INTER) %{
4173     equal(0x4, "e");
4174     not_equal(0x5, "ne");
4175     less(0x2, "b");
4176     greater_equal(0x3, "nb");
4177     less_equal(0x6, "be");
4178     greater(0x7, "nbe");
4179     overflow(0x0, "o");
4180     no_overflow(0x1, "no");
4181   %}
4182 %}
4183 
4184 
4185 // Floating comparisons that don't require any fixup for the unordered case
4186 operand cmpOpUCF() %{
4187   match(Bool);
4188   predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4189             n->as_Bool()->_test._test == BoolTest::ge ||
4190             n->as_Bool()->_test._test == BoolTest::le ||
4191             n->as_Bool()->_test._test == BoolTest::gt);
4192   format %{ "" %}
4193   interface(COND_INTER) %{
4194     equal(0x4, "e");
4195     not_equal(0x5, "ne");
4196     less(0x2, "b");
4197     greater_equal(0x3, "nb");
4198     less_equal(0x6, "be");
4199     greater(0x7, "nbe");
4200     overflow(0x0, "o");
4201     no_overflow(0x1, "no");
4202   %}
4203 %}
4204 
4205 
4206 // Floating comparisons that can be fixed up with extra conditional jumps
4207 operand cmpOpUCF2() %{
4208   match(Bool);
4209   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4210             n->as_Bool()->_test._test == BoolTest::eq);
4211   format %{ "" %}
4212   interface(COND_INTER) %{
4213     equal(0x4, "e");
4214     not_equal(0x5, "ne");
4215     less(0x2, "b");
4216     greater_equal(0x3, "nb");
4217     less_equal(0x6, "be");
4218     greater(0x7, "nbe");
4219     overflow(0x0, "o");
4220     no_overflow(0x1, "no");
4221   %}
4222 %}
4223 
4224 //----------OPERAND CLASSES----------------------------------------------------
4225 // Operand Classes are groups of operands that are used as to simplify
4226 // instruction definitions by not requiring the AD writer to specify separate
4227 // instructions for every form of operand when the instruction accepts
4228 // multiple operand types with the same basic encoding and format.  The classic
4229 // case of this is memory operands.
4230 
4231 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4232                indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4233                indCompressedOopOffset,
4234                indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4235                indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4236                indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4237 
4238 //----------PIPELINE-----------------------------------------------------------
4239 // Rules which define the behavior of the target architectures pipeline.
4240 pipeline %{
4241 
4242 //----------ATTRIBUTES---------------------------------------------------------
4243 attributes %{
4244   variable_size_instructions;        // Fixed size instructions
4245   max_instructions_per_bundle = 3;   // Up to 3 instructions per bundle
4246   instruction_unit_size = 1;         // An instruction is 1 bytes long
4247   instruction_fetch_unit_size = 16;  // The processor fetches one line
4248   instruction_fetch_units = 1;       // of 16 bytes
4249 
4250   // List of nop instructions
4251   nops( MachNop );
4252 %}
4253 
4254 //----------RESOURCES----------------------------------------------------------
4255 // Resources are the functional units available to the machine
4256 
4257 // Generic P2/P3 pipeline
4258 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4259 // 3 instructions decoded per cycle.
4260 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4261 // 3 ALU op, only ALU0 handles mul instructions.
4262 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4263            MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4264            BR, FPU,
4265            ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4266 
4267 //----------PIPELINE DESCRIPTION-----------------------------------------------
4268 // Pipeline Description specifies the stages in the machine's pipeline
4269 
4270 // Generic P2/P3 pipeline
4271 pipe_desc(S0, S1, S2, S3, S4, S5);
4272 
4273 //----------PIPELINE CLASSES---------------------------------------------------
4274 // Pipeline Classes describe the stages in which input and output are
4275 // referenced by the hardware pipeline.
4276 
4277 // Naming convention: ialu or fpu
4278 // Then: _reg
4279 // Then: _reg if there is a 2nd register
4280 // Then: _long if it's a pair of instructions implementing a long
4281 // Then: _fat if it requires the big decoder
4282 //   Or: _mem if it requires the big decoder and a memory unit.
4283 
4284 // Integer ALU reg operation
4285 pipe_class ialu_reg(rRegI dst)
4286 %{
4287     single_instruction;
4288     dst    : S4(write);
4289     dst    : S3(read);
4290     DECODE : S0;        // any decoder
4291     ALU    : S3;        // any alu
4292 %}
4293 
4294 // Long ALU reg operation
4295 pipe_class ialu_reg_long(rRegL dst)
4296 %{
4297     instruction_count(2);
4298     dst    : S4(write);
4299     dst    : S3(read);
4300     DECODE : S0(2);     // any 2 decoders
4301     ALU    : S3(2);     // both alus
4302 %}
4303 
4304 // Integer ALU reg operation using big decoder
4305 pipe_class ialu_reg_fat(rRegI dst)
4306 %{
4307     single_instruction;
4308     dst    : S4(write);
4309     dst    : S3(read);
4310     D0     : S0;        // big decoder only
4311     ALU    : S3;        // any alu
4312 %}
4313 
4314 // Long ALU reg operation using big decoder
4315 pipe_class ialu_reg_long_fat(rRegL dst)
4316 %{
4317     instruction_count(2);
4318     dst    : S4(write);
4319     dst    : S3(read);
4320     D0     : S0(2);     // big decoder only; twice
4321     ALU    : S3(2);     // any 2 alus
4322 %}
4323 
4324 // Integer ALU reg-reg operation
4325 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4326 %{
4327     single_instruction;
4328     dst    : S4(write);
4329     src    : S3(read);
4330     DECODE : S0;        // any decoder
4331     ALU    : S3;        // any alu
4332 %}
4333 
4334 // Long ALU reg-reg operation
4335 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4336 %{
4337     instruction_count(2);
4338     dst    : S4(write);
4339     src    : S3(read);
4340     DECODE : S0(2);     // any 2 decoders
4341     ALU    : S3(2);     // both alus
4342 %}
4343 
4344 // Integer ALU reg-reg operation
4345 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4346 %{
4347     single_instruction;
4348     dst    : S4(write);
4349     src    : S3(read);
4350     D0     : S0;        // big decoder only
4351     ALU    : S3;        // any alu
4352 %}
4353 
4354 // Long ALU reg-reg operation
4355 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4356 %{
4357     instruction_count(2);
4358     dst    : S4(write);
4359     src    : S3(read);
4360     D0     : S0(2);     // big decoder only; twice
4361     ALU    : S3(2);     // both alus
4362 %}
4363 
4364 // Integer ALU reg-mem operation
4365 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4366 %{
4367     single_instruction;
4368     dst    : S5(write);
4369     mem    : S3(read);
4370     D0     : S0;        // big decoder only
4371     ALU    : S4;        // any alu
4372     MEM    : S3;        // any mem
4373 %}
4374 
4375 // Integer mem operation (prefetch)
4376 pipe_class ialu_mem(memory mem)
4377 %{
4378     single_instruction;
4379     mem    : S3(read);
4380     D0     : S0;        // big decoder only
4381     MEM    : S3;        // any mem
4382 %}
4383 
4384 // Integer Store to Memory
4385 pipe_class ialu_mem_reg(memory mem, rRegI src)
4386 %{
4387     single_instruction;
4388     mem    : S3(read);
4389     src    : S5(read);
4390     D0     : S0;        // big decoder only
4391     ALU    : S4;        // any alu
4392     MEM    : S3;
4393 %}
4394 
4395 // // Long Store to Memory
4396 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4397 // %{
4398 //     instruction_count(2);
4399 //     mem    : S3(read);
4400 //     src    : S5(read);
4401 //     D0     : S0(2);          // big decoder only; twice
4402 //     ALU    : S4(2);     // any 2 alus
4403 //     MEM    : S3(2);  // Both mems
4404 // %}
4405 
4406 // Integer Store to Memory
4407 pipe_class ialu_mem_imm(memory mem)
4408 %{
4409     single_instruction;
4410     mem    : S3(read);
4411     D0     : S0;        // big decoder only
4412     ALU    : S4;        // any alu
4413     MEM    : S3;
4414 %}
4415 
4416 // Integer ALU0 reg-reg operation
4417 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4418 %{
4419     single_instruction;
4420     dst    : S4(write);
4421     src    : S3(read);
4422     D0     : S0;        // Big decoder only
4423     ALU0   : S3;        // only alu0
4424 %}
4425 
4426 // Integer ALU0 reg-mem operation
4427 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4428 %{
4429     single_instruction;
4430     dst    : S5(write);
4431     mem    : S3(read);
4432     D0     : S0;        // big decoder only
4433     ALU0   : S4;        // ALU0 only
4434     MEM    : S3;        // any mem
4435 %}
4436 
4437 // Integer ALU reg-reg operation
4438 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4439 %{
4440     single_instruction;
4441     cr     : S4(write);
4442     src1   : S3(read);
4443     src2   : S3(read);
4444     DECODE : S0;        // any decoder
4445     ALU    : S3;        // any alu
4446 %}
4447 
4448 // Integer ALU reg-imm operation
4449 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4450 %{
4451     single_instruction;
4452     cr     : S4(write);
4453     src1   : S3(read);
4454     DECODE : S0;        // any decoder
4455     ALU    : S3;        // any alu
4456 %}
4457 
4458 // Integer ALU reg-mem operation
4459 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4460 %{
4461     single_instruction;
4462     cr     : S4(write);
4463     src1   : S3(read);
4464     src2   : S3(read);
4465     D0     : S0;        // big decoder only
4466     ALU    : S4;        // any alu
4467     MEM    : S3;
4468 %}
4469 
4470 // Conditional move reg-reg
4471 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4472 %{
4473     instruction_count(4);
4474     y      : S4(read);
4475     q      : S3(read);
4476     p      : S3(read);
4477     DECODE : S0(4);     // any decoder
4478 %}
4479 
4480 // Conditional move reg-reg
4481 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4482 %{
4483     single_instruction;
4484     dst    : S4(write);
4485     src    : S3(read);
4486     cr     : S3(read);
4487     DECODE : S0;        // any decoder
4488 %}
4489 
4490 // Conditional move reg-mem
4491 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4492 %{
4493     single_instruction;
4494     dst    : S4(write);
4495     src    : S3(read);
4496     cr     : S3(read);
4497     DECODE : S0;        // any decoder
4498     MEM    : S3;
4499 %}
4500 
4501 // Conditional move reg-reg long
4502 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4503 %{
4504     single_instruction;
4505     dst    : S4(write);
4506     src    : S3(read);
4507     cr     : S3(read);
4508     DECODE : S0(2);     // any 2 decoders
4509 %}
4510 
4511 // XXX
4512 // // Conditional move double reg-reg
4513 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4514 // %{
4515 //     single_instruction;
4516 //     dst    : S4(write);
4517 //     src    : S3(read);
4518 //     cr     : S3(read);
4519 //     DECODE : S0;     // any decoder
4520 // %}
4521 
4522 // Float reg-reg operation
4523 pipe_class fpu_reg(regD dst)
4524 %{
4525     instruction_count(2);
4526     dst    : S3(read);
4527     DECODE : S0(2);     // any 2 decoders
4528     FPU    : S3;
4529 %}
4530 
4531 // Float reg-reg operation
4532 pipe_class fpu_reg_reg(regD dst, regD src)
4533 %{
4534     instruction_count(2);
4535     dst    : S4(write);
4536     src    : S3(read);
4537     DECODE : S0(2);     // any 2 decoders
4538     FPU    : S3;
4539 %}
4540 
4541 // Float reg-reg operation
4542 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4543 %{
4544     instruction_count(3);
4545     dst    : S4(write);
4546     src1   : S3(read);
4547     src2   : S3(read);
4548     DECODE : S0(3);     // any 3 decoders
4549     FPU    : S3(2);
4550 %}
4551 
4552 // Float reg-reg operation
4553 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4554 %{
4555     instruction_count(4);
4556     dst    : S4(write);
4557     src1   : S3(read);
4558     src2   : S3(read);
4559     src3   : S3(read);
4560     DECODE : S0(4);     // any 3 decoders
4561     FPU    : S3(2);
4562 %}
4563 
4564 // Float reg-reg operation
4565 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4566 %{
4567     instruction_count(4);
4568     dst    : S4(write);
4569     src1   : S3(read);
4570     src2   : S3(read);
4571     src3   : S3(read);
4572     DECODE : S1(3);     // any 3 decoders
4573     D0     : S0;        // Big decoder only
4574     FPU    : S3(2);
4575     MEM    : S3;
4576 %}
4577 
4578 // Float reg-mem operation
4579 pipe_class fpu_reg_mem(regD dst, memory mem)
4580 %{
4581     instruction_count(2);
4582     dst    : S5(write);
4583     mem    : S3(read);
4584     D0     : S0;        // big decoder only
4585     DECODE : S1;        // any decoder for FPU POP
4586     FPU    : S4;
4587     MEM    : S3;        // any mem
4588 %}
4589 
4590 // Float reg-mem operation
4591 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4592 %{
4593     instruction_count(3);
4594     dst    : S5(write);
4595     src1   : S3(read);
4596     mem    : S3(read);
4597     D0     : S0;        // big decoder only
4598     DECODE : S1(2);     // any decoder for FPU POP
4599     FPU    : S4;
4600     MEM    : S3;        // any mem
4601 %}
4602 
4603 // Float mem-reg operation
4604 pipe_class fpu_mem_reg(memory mem, regD src)
4605 %{
4606     instruction_count(2);
4607     src    : S5(read);
4608     mem    : S3(read);
4609     DECODE : S0;        // any decoder for FPU PUSH
4610     D0     : S1;        // big decoder only
4611     FPU    : S4;
4612     MEM    : S3;        // any mem
4613 %}
4614 
4615 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4616 %{
4617     instruction_count(3);
4618     src1   : S3(read);
4619     src2   : S3(read);
4620     mem    : S3(read);
4621     DECODE : S0(2);     // any decoder for FPU PUSH
4622     D0     : S1;        // big decoder only
4623     FPU    : S4;
4624     MEM    : S3;        // any mem
4625 %}
4626 
4627 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4628 %{
4629     instruction_count(3);
4630     src1   : S3(read);
4631     src2   : S3(read);
4632     mem    : S4(read);
4633     DECODE : S0;        // any decoder for FPU PUSH
4634     D0     : S0(2);     // big decoder only
4635     FPU    : S4;
4636     MEM    : S3(2);     // any mem
4637 %}
4638 
4639 pipe_class fpu_mem_mem(memory dst, memory src1)
4640 %{
4641     instruction_count(2);
4642     src1   : S3(read);
4643     dst    : S4(read);
4644     D0     : S0(2);     // big decoder only
4645     MEM    : S3(2);     // any mem
4646 %}
4647 
4648 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4649 %{
4650     instruction_count(3);
4651     src1   : S3(read);
4652     src2   : S3(read);
4653     dst    : S4(read);
4654     D0     : S0(3);     // big decoder only
4655     FPU    : S4;
4656     MEM    : S3(3);     // any mem
4657 %}
4658 
4659 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4660 %{
4661     instruction_count(3);
4662     src1   : S4(read);
4663     mem    : S4(read);
4664     DECODE : S0;        // any decoder for FPU PUSH
4665     D0     : S0(2);     // big decoder only
4666     FPU    : S4;
4667     MEM    : S3(2);     // any mem
4668 %}
4669 
4670 // Float load constant
4671 pipe_class fpu_reg_con(regD dst)
4672 %{
4673     instruction_count(2);
4674     dst    : S5(write);
4675     D0     : S0;        // big decoder only for the load
4676     DECODE : S1;        // any decoder for FPU POP
4677     FPU    : S4;
4678     MEM    : S3;        // any mem
4679 %}
4680 
4681 // Float load constant
4682 pipe_class fpu_reg_reg_con(regD dst, regD src)
4683 %{
4684     instruction_count(3);
4685     dst    : S5(write);
4686     src    : S3(read);
4687     D0     : S0;        // big decoder only for the load
4688     DECODE : S1(2);     // any decoder for FPU POP
4689     FPU    : S4;
4690     MEM    : S3;        // any mem
4691 %}
4692 
4693 // UnConditional branch
4694 pipe_class pipe_jmp(label labl)
4695 %{
4696     single_instruction;
4697     BR   : S3;
4698 %}
4699 
4700 // Conditional branch
4701 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4702 %{
4703     single_instruction;
4704     cr    : S1(read);
4705     BR    : S3;
4706 %}
4707 
4708 // Allocation idiom
4709 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4710 %{
4711     instruction_count(1); force_serialization;
4712     fixed_latency(6);
4713     heap_ptr : S3(read);
4714     DECODE   : S0(3);
4715     D0       : S2;
4716     MEM      : S3;
4717     ALU      : S3(2);
4718     dst      : S5(write);
4719     BR       : S5;
4720 %}
4721 
4722 // Generic big/slow expanded idiom
4723 pipe_class pipe_slow()
4724 %{
4725     instruction_count(10); multiple_bundles; force_serialization;
4726     fixed_latency(100);
4727     D0  : S0(2);
4728     MEM : S3(2);
4729 %}
4730 
4731 // The real do-nothing guy
4732 pipe_class empty()
4733 %{
4734     instruction_count(0);
4735 %}
4736 
4737 // Define the class for the Nop node
4738 define
4739 %{
4740    MachNop = empty;
4741 %}
4742 
4743 %}
4744 
4745 //----------INSTRUCTIONS-------------------------------------------------------
4746 //
4747 // match      -- States which machine-independent subtree may be replaced
4748 //               by this instruction.
4749 // ins_cost   -- The estimated cost of this instruction is used by instruction
4750 //               selection to identify a minimum cost tree of machine
4751 //               instructions that matches a tree of machine-independent
4752 //               instructions.
4753 // format     -- A string providing the disassembly for this instruction.
4754 //               The value of an instruction's operand may be inserted
4755 //               by referring to it with a '$' prefix.
4756 // opcode     -- Three instruction opcodes may be provided.  These are referred
4757 //               to within an encode class as $primary, $secondary, and $tertiary
4758 //               rrspectively.  The primary opcode is commonly used to
4759 //               indicate the type of machine instruction, while secondary
4760 //               and tertiary are often used for prefix options or addressing
4761 //               modes.
4762 // ins_encode -- A list of encode classes with parameters. The encode class
4763 //               name must have been defined in an 'enc_class' specification
4764 //               in the encode section of the architecture description.
4765 
4766 
4767 //----------Load/Store/Move Instructions---------------------------------------
4768 //----------Load Instructions--------------------------------------------------
4769 
4770 // Load Byte (8 bit signed)
4771 instruct loadB(rRegI dst, memory mem)
4772 %{
4773   match(Set dst (LoadB mem));
4774 
4775   ins_cost(125);
4776   format %{ "movsbl  $dst, $mem\t# byte" %}
4777 
4778   ins_encode %{
4779     __ movsbl($dst$$Register, $mem$$Address);
4780   %}
4781 
4782   ins_pipe(ialu_reg_mem);
4783 %}
4784 
4785 // Load Byte (8 bit signed) into Long Register
4786 instruct loadB2L(rRegL dst, memory mem)
4787 %{
4788   match(Set dst (ConvI2L (LoadB mem)));
4789 
4790   ins_cost(125);
4791   format %{ "movsbq  $dst, $mem\t# byte -> long" %}
4792 
4793   ins_encode %{
4794     __ movsbq($dst$$Register, $mem$$Address);
4795   %}
4796 
4797   ins_pipe(ialu_reg_mem);
4798 %}
4799 
4800 // Load Unsigned Byte (8 bit UNsigned)
4801 instruct loadUB(rRegI dst, memory mem)
4802 %{
4803   match(Set dst (LoadUB mem));
4804 
4805   ins_cost(125);
4806   format %{ "movzbl  $dst, $mem\t# ubyte" %}
4807 
4808   ins_encode %{
4809     __ movzbl($dst$$Register, $mem$$Address);
4810   %}
4811 
4812   ins_pipe(ialu_reg_mem);
4813 %}
4814 
4815 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4816 instruct loadUB2L(rRegL dst, memory mem)
4817 %{
4818   match(Set dst (ConvI2L (LoadUB mem)));
4819 
4820   ins_cost(125);
4821   format %{ "movzbq  $dst, $mem\t# ubyte -> long" %}
4822 
4823   ins_encode %{
4824     __ movzbq($dst$$Register, $mem$$Address);
4825   %}
4826 
4827   ins_pipe(ialu_reg_mem);
4828 %}
4829 
4830 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4831 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4832   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4833   effect(KILL cr);
4834 
4835   format %{ "movzbq  $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4836             "andl    $dst, right_n_bits($mask, 8)" %}
4837   ins_encode %{
4838     Register Rdst = $dst$$Register;
4839     __ movzbq(Rdst, $mem$$Address);
4840     __ andl(Rdst, $mask$$constant & right_n_bits(8));
4841   %}
4842   ins_pipe(ialu_reg_mem);
4843 %}
4844 
4845 // Load Short (16 bit signed)
4846 instruct loadS(rRegI dst, memory mem)
4847 %{
4848   match(Set dst (LoadS mem));
4849 
4850   ins_cost(125);
4851   format %{ "movswl $dst, $mem\t# short" %}
4852 
4853   ins_encode %{
4854     __ movswl($dst$$Register, $mem$$Address);
4855   %}
4856 
4857   ins_pipe(ialu_reg_mem);
4858 %}
4859 
4860 // Load Short (16 bit signed) to Byte (8 bit signed)
4861 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4862   match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4863 
4864   ins_cost(125);
4865   format %{ "movsbl $dst, $mem\t# short -> byte" %}
4866   ins_encode %{
4867     __ movsbl($dst$$Register, $mem$$Address);
4868   %}
4869   ins_pipe(ialu_reg_mem);
4870 %}
4871 
4872 // Load Short (16 bit signed) into Long Register
4873 instruct loadS2L(rRegL dst, memory mem)
4874 %{
4875   match(Set dst (ConvI2L (LoadS mem)));
4876 
4877   ins_cost(125);
4878   format %{ "movswq $dst, $mem\t# short -> long" %}
4879 
4880   ins_encode %{
4881     __ movswq($dst$$Register, $mem$$Address);
4882   %}
4883 
4884   ins_pipe(ialu_reg_mem);
4885 %}
4886 
4887 // Load Unsigned Short/Char (16 bit UNsigned)
4888 instruct loadUS(rRegI dst, memory mem)
4889 %{
4890   match(Set dst (LoadUS mem));
4891 
4892   ins_cost(125);
4893   format %{ "movzwl  $dst, $mem\t# ushort/char" %}
4894 
4895   ins_encode %{
4896     __ movzwl($dst$$Register, $mem$$Address);
4897   %}
4898 
4899   ins_pipe(ialu_reg_mem);
4900 %}
4901 
4902 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4903 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4904   match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4905 
4906   ins_cost(125);
4907   format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4908   ins_encode %{
4909     __ movsbl($dst$$Register, $mem$$Address);
4910   %}
4911   ins_pipe(ialu_reg_mem);
4912 %}
4913 
4914 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4915 instruct loadUS2L(rRegL dst, memory mem)
4916 %{
4917   match(Set dst (ConvI2L (LoadUS mem)));
4918 
4919   ins_cost(125);
4920   format %{ "movzwq  $dst, $mem\t# ushort/char -> long" %}
4921 
4922   ins_encode %{
4923     __ movzwq($dst$$Register, $mem$$Address);
4924   %}
4925 
4926   ins_pipe(ialu_reg_mem);
4927 %}
4928 
4929 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4930 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4931   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4932 
4933   format %{ "movzbq  $dst, $mem\t# ushort/char & 0xFF -> long" %}
4934   ins_encode %{
4935     __ movzbq($dst$$Register, $mem$$Address);
4936   %}
4937   ins_pipe(ialu_reg_mem);
4938 %}
4939 
4940 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4941 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4942   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4943   effect(KILL cr);
4944 
4945   format %{ "movzwq  $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4946             "andl    $dst, right_n_bits($mask, 16)" %}
4947   ins_encode %{
4948     Register Rdst = $dst$$Register;
4949     __ movzwq(Rdst, $mem$$Address);
4950     __ andl(Rdst, $mask$$constant & right_n_bits(16));
4951   %}
4952   ins_pipe(ialu_reg_mem);
4953 %}
4954 
4955 // Load Integer
4956 instruct loadI(rRegI dst, memory mem)
4957 %{
4958   match(Set dst (LoadI mem));
4959 
4960   ins_cost(125);
4961   format %{ "movl    $dst, $mem\t# int" %}
4962 
4963   ins_encode %{
4964     __ movl($dst$$Register, $mem$$Address);
4965   %}
4966 
4967   ins_pipe(ialu_reg_mem);
4968 %}
4969 
4970 // Load Integer (32 bit signed) to Byte (8 bit signed)
4971 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4972   match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4973 
4974   ins_cost(125);
4975   format %{ "movsbl  $dst, $mem\t# int -> byte" %}
4976   ins_encode %{
4977     __ movsbl($dst$$Register, $mem$$Address);
4978   %}
4979   ins_pipe(ialu_reg_mem);
4980 %}
4981 
4982 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4983 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4984   match(Set dst (AndI (LoadI mem) mask));
4985 
4986   ins_cost(125);
4987   format %{ "movzbl  $dst, $mem\t# int -> ubyte" %}
4988   ins_encode %{
4989     __ movzbl($dst$$Register, $mem$$Address);
4990   %}
4991   ins_pipe(ialu_reg_mem);
4992 %}
4993 
4994 // Load Integer (32 bit signed) to Short (16 bit signed)
4995 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4996   match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4997 
4998   ins_cost(125);
4999   format %{ "movswl  $dst, $mem\t# int -> short" %}
5000   ins_encode %{
5001     __ movswl($dst$$Register, $mem$$Address);
5002   %}
5003   ins_pipe(ialu_reg_mem);
5004 %}
5005 
5006 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5007 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5008   match(Set dst (AndI (LoadI mem) mask));
5009 
5010   ins_cost(125);
5011   format %{ "movzwl  $dst, $mem\t# int -> ushort/char" %}
5012   ins_encode %{
5013     __ movzwl($dst$$Register, $mem$$Address);
5014   %}
5015   ins_pipe(ialu_reg_mem);
5016 %}
5017 
5018 // Load Integer into Long Register
5019 instruct loadI2L(rRegL dst, memory mem)
5020 %{
5021   match(Set dst (ConvI2L (LoadI mem)));
5022 
5023   ins_cost(125);
5024   format %{ "movslq  $dst, $mem\t# int -> long" %}
5025 
5026   ins_encode %{
5027     __ movslq($dst$$Register, $mem$$Address);
5028   %}
5029 
5030   ins_pipe(ialu_reg_mem);
5031 %}
5032 
5033 // Load Integer with mask 0xFF into Long Register
5034 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5035   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5036 
5037   format %{ "movzbq  $dst, $mem\t# int & 0xFF -> long" %}
5038   ins_encode %{
5039     __ movzbq($dst$$Register, $mem$$Address);
5040   %}
5041   ins_pipe(ialu_reg_mem);
5042 %}
5043 
5044 // Load Integer with mask 0xFFFF into Long Register
5045 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5046   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5047 
5048   format %{ "movzwq  $dst, $mem\t# int & 0xFFFF -> long" %}
5049   ins_encode %{
5050     __ movzwq($dst$$Register, $mem$$Address);
5051   %}
5052   ins_pipe(ialu_reg_mem);
5053 %}
5054 
5055 // Load Integer with a 31-bit mask into Long Register
5056 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5057   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5058   effect(KILL cr);
5059 
5060   format %{ "movl    $dst, $mem\t# int & 31-bit mask -> long\n\t"
5061             "andl    $dst, $mask" %}
5062   ins_encode %{
5063     Register Rdst = $dst$$Register;
5064     __ movl(Rdst, $mem$$Address);
5065     __ andl(Rdst, $mask$$constant);
5066   %}
5067   ins_pipe(ialu_reg_mem);
5068 %}
5069 
5070 // Load Unsigned Integer into Long Register
5071 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5072 %{
5073   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5074 
5075   ins_cost(125);
5076   format %{ "movl    $dst, $mem\t# uint -> long" %}
5077 
5078   ins_encode %{
5079     __ movl($dst$$Register, $mem$$Address);
5080   %}
5081 
5082   ins_pipe(ialu_reg_mem);
5083 %}
5084 
5085 // Load Long
5086 instruct loadL(rRegL dst, memory mem)
5087 %{
5088   match(Set dst (LoadL mem));
5089 
5090   ins_cost(125);
5091   format %{ "movq    $dst, $mem\t# long" %}
5092 
5093   ins_encode %{
5094     __ movq($dst$$Register, $mem$$Address);
5095   %}
5096 
5097   ins_pipe(ialu_reg_mem); // XXX
5098 %}
5099 
5100 // Load Range
5101 instruct loadRange(rRegI dst, memory mem)
5102 %{
5103   match(Set dst (LoadRange mem));
5104 
5105   ins_cost(125); // XXX
5106   format %{ "movl    $dst, $mem\t# range" %}
5107   opcode(0x8B);
5108   ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5109   ins_pipe(ialu_reg_mem);
5110 %}
5111 
5112 // Load Pointer
5113 instruct loadP(rRegP dst, memory mem)
5114 %{
5115   match(Set dst (LoadP mem));
5116   predicate(n->as_Load()->barrier_data() == 0);
5117 
5118   ins_cost(125); // XXX
5119   format %{ "movq    $dst, $mem\t# ptr" %}
5120   opcode(0x8B);
5121   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5122   ins_pipe(ialu_reg_mem); // XXX
5123 %}
5124 
5125 // Load Compressed Pointer
5126 instruct loadN(rRegN dst, memory mem)
5127 %{
5128    match(Set dst (LoadN mem));
5129 
5130    ins_cost(125); // XXX
5131    format %{ "movl    $dst, $mem\t# compressed ptr" %}
5132    ins_encode %{
5133      __ movl($dst$$Register, $mem$$Address);
5134    %}
5135    ins_pipe(ialu_reg_mem); // XXX
5136 %}
5137 
5138 
5139 // Load Klass Pointer
5140 instruct loadKlass(rRegP dst, memory mem)
5141 %{
5142   match(Set dst (LoadKlass mem));
5143 
5144   ins_cost(125); // XXX
5145   format %{ "movq    $dst, $mem\t# class" %}
5146   opcode(0x8B);
5147   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5148   ins_pipe(ialu_reg_mem); // XXX
5149 %}
5150 
5151 // Load narrow Klass Pointer
5152 instruct loadNKlass(rRegN dst, memory mem)
5153 %{
5154   match(Set dst (LoadNKlass mem));
5155 
5156   ins_cost(125); // XXX
5157   format %{ "movl    $dst, $mem\t# compressed klass ptr" %}
5158   ins_encode %{
5159     __ movl($dst$$Register, $mem$$Address);
5160   %}
5161   ins_pipe(ialu_reg_mem); // XXX
5162 %}
5163 
5164 // Load Float
5165 instruct loadF(regF dst, memory mem)
5166 %{
5167   match(Set dst (LoadF mem));
5168 
5169   ins_cost(145); // XXX
5170   format %{ "movss   $dst, $mem\t# float" %}
5171   ins_encode %{
5172     __ movflt($dst$$XMMRegister, $mem$$Address);
5173   %}
5174   ins_pipe(pipe_slow); // XXX
5175 %}
5176 
5177 // Load Float
5178 instruct MoveF2VL(vlRegF dst, regF src) %{
5179   match(Set dst src);
5180   format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5181   ins_encode %{
5182     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5183   %}
5184   ins_pipe( fpu_reg_reg );
5185 %}
5186 
5187 // Load Float
5188 instruct MoveF2LEG(legRegF dst, regF src) %{
5189   match(Set dst src);
5190   format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5191   ins_encode %{
5192     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5193   %}
5194   ins_pipe( fpu_reg_reg );
5195 %}
5196 
5197 // Load Float
5198 instruct MoveVL2F(regF dst, vlRegF src) %{
5199   match(Set dst src);
5200   format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5201   ins_encode %{
5202     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5203   %}
5204   ins_pipe( fpu_reg_reg );
5205 %}
5206 
5207 // Load Float
5208 instruct MoveLEG2F(regF dst, legRegF src) %{
5209   match(Set dst src);
5210   format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
5211   ins_encode %{
5212     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5213   %}
5214   ins_pipe( fpu_reg_reg );
5215 %}
5216 
5217 // Load Double
5218 instruct loadD_partial(regD dst, memory mem)
5219 %{
5220   predicate(!UseXmmLoadAndClearUpper);
5221   match(Set dst (LoadD mem));
5222 
5223   ins_cost(145); // XXX
5224   format %{ "movlpd  $dst, $mem\t# double" %}
5225   ins_encode %{
5226     __ movdbl($dst$$XMMRegister, $mem$$Address);
5227   %}
5228   ins_pipe(pipe_slow); // XXX
5229 %}
5230 
5231 instruct loadD(regD dst, memory mem)
5232 %{
5233   predicate(UseXmmLoadAndClearUpper);
5234   match(Set dst (LoadD mem));
5235 
5236   ins_cost(145); // XXX
5237   format %{ "movsd   $dst, $mem\t# double" %}
5238   ins_encode %{
5239     __ movdbl($dst$$XMMRegister, $mem$$Address);
5240   %}
5241   ins_pipe(pipe_slow); // XXX
5242 %}
5243 
5244 // Load Double
5245 instruct MoveD2VL(vlRegD dst, regD src) %{
5246   match(Set dst src);
5247   format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5248   ins_encode %{
5249     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5250   %}
5251   ins_pipe( fpu_reg_reg );
5252 %}
5253 
5254 // Load Double
5255 instruct MoveD2LEG(legRegD dst, regD src) %{
5256   match(Set dst src);
5257   format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5258   ins_encode %{
5259     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5260   %}
5261   ins_pipe( fpu_reg_reg );
5262 %}
5263 
5264 // Load Double
5265 instruct MoveVL2D(regD dst, vlRegD src) %{
5266   match(Set dst src);
5267   format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5268   ins_encode %{
5269     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5270   %}
5271   ins_pipe( fpu_reg_reg );
5272 %}
5273 
5274 // Load Double
5275 instruct MoveLEG2D(regD dst, legRegD src) %{
5276   match(Set dst src);
5277   format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
5278   ins_encode %{
5279     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5280   %}
5281   ins_pipe( fpu_reg_reg );
5282 %}
5283 
5284 // Following pseudo code describes the algorithm for max[FD]:
5285 // Min algorithm is on similar lines
5286 //  btmp = (b < +0.0) ? a : b
5287 //  atmp = (b < +0.0) ? b : a
5288 //  Tmp  = Max_Float(atmp , btmp)
5289 //  Res  = (atmp == NaN) ? atmp : Tmp
5290 
5291 // max = java.lang.Math.max(float a, float b)
5292 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5293   predicate(UseAVX > 0 && !n->is_reduction());
5294   match(Set dst (MaxF a b));
5295   effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5296   format %{
5297      "vblendvps        $btmp,$b,$a,$b           \n\t"
5298      "vblendvps        $atmp,$a,$b,$b           \n\t"
5299      "vmaxss           $tmp,$atmp,$btmp         \n\t"
5300      "vcmpps.unordered $btmp,$atmp,$atmp        \n\t"
5301      "vblendvps        $dst,$tmp,$atmp,$btmp    \n\t"
5302   %}
5303   ins_encode %{
5304     int vector_len = Assembler::AVX_128bit;
5305     __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5306     __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5307     __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5308     __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5309     __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5310  %}
5311   ins_pipe( pipe_slow );
5312 %}
5313 
5314 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
5315   predicate(UseAVX > 0 && n->is_reduction());
5316   match(Set dst (MaxF a b));
5317   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5318 
5319   format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
5320   ins_encode %{
5321     emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5322                     false /*min*/, true /*single*/);
5323   %}
5324   ins_pipe( pipe_slow );
5325 %}
5326 
5327 // max = java.lang.Math.max(double a, double b)
5328 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5329   predicate(UseAVX > 0 && !n->is_reduction());
5330   match(Set dst (MaxD a b));
5331   effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
5332   format %{
5333      "vblendvpd        $btmp,$b,$a,$b            \n\t"
5334      "vblendvpd        $atmp,$a,$b,$b            \n\t"
5335      "vmaxsd           $tmp,$atmp,$btmp          \n\t"
5336      "vcmppd.unordered $btmp,$atmp,$atmp         \n\t"
5337      "vblendvpd        $dst,$tmp,$atmp,$btmp     \n\t"
5338   %}
5339   ins_encode %{
5340     int vector_len = Assembler::AVX_128bit;
5341     __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5342     __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5343     __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5344     __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5345     __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5346   %}
5347   ins_pipe( pipe_slow );
5348 %}
5349 
5350 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
5351   predicate(UseAVX > 0 && n->is_reduction());
5352   match(Set dst (MaxD a b));
5353   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5354 
5355   format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
5356   ins_encode %{
5357     emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5358                     false /*min*/, false /*single*/);
5359   %}
5360   ins_pipe( pipe_slow );
5361 %}
5362 
5363 // min = java.lang.Math.min(float a, float b)
5364 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5365   predicate(UseAVX > 0 && !n->is_reduction());
5366   match(Set dst (MinF a b));
5367   effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5368   format %{
5369      "vblendvps        $atmp,$a,$b,$a             \n\t"
5370      "vblendvps        $btmp,$b,$a,$a             \n\t"
5371      "vminss           $tmp,$atmp,$btmp           \n\t"
5372      "vcmpps.unordered $btmp,$atmp,$atmp          \n\t"
5373      "vblendvps        $dst,$tmp,$atmp,$btmp      \n\t"
5374   %}
5375   ins_encode %{
5376     int vector_len = Assembler::AVX_128bit;
5377     __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5378     __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5379     __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5380     __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5381     __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5382   %}
5383   ins_pipe( pipe_slow );
5384 %}
5385 
5386 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
5387   predicate(UseAVX > 0 && n->is_reduction());
5388   match(Set dst (MinF a b));
5389   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5390 
5391   format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
5392   ins_encode %{
5393     emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5394                     true /*min*/, true /*single*/);
5395   %}
5396   ins_pipe( pipe_slow );
5397 %}
5398 
5399 // min = java.lang.Math.min(double a, double b)
5400 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5401   predicate(UseAVX > 0 && !n->is_reduction());
5402   match(Set dst (MinD a b));
5403   effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5404   format %{
5405      "vblendvpd        $atmp,$a,$b,$a           \n\t"
5406      "vblendvpd        $btmp,$b,$a,$a           \n\t"
5407      "vminsd           $tmp,$atmp,$btmp         \n\t"
5408      "vcmppd.unordered $btmp,$atmp,$atmp        \n\t"
5409      "vblendvpd        $dst,$tmp,$atmp,$btmp    \n\t"
5410   %}
5411   ins_encode %{
5412     int vector_len = Assembler::AVX_128bit;
5413     __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5414     __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5415     __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5416     __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5417     __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5418   %}
5419   ins_pipe( pipe_slow );
5420 %}
5421 
5422 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
5423   predicate(UseAVX > 0 && n->is_reduction());
5424   match(Set dst (MinD a b));
5425   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5426 
5427   format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
5428   ins_encode %{
5429     emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5430                     true /*min*/, false /*single*/);
5431   %}
5432   ins_pipe( pipe_slow );
5433 %}
5434 
5435 // Load Effective Address
5436 instruct leaP8(rRegP dst, indOffset8 mem)
5437 %{
5438   match(Set dst mem);
5439 
5440   ins_cost(110); // XXX
5441   format %{ "leaq    $dst, $mem\t# ptr 8" %}
5442   opcode(0x8D);
5443   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5444   ins_pipe(ialu_reg_reg_fat);
5445 %}
5446 
5447 instruct leaP32(rRegP dst, indOffset32 mem)
5448 %{
5449   match(Set dst mem);
5450 
5451   ins_cost(110);
5452   format %{ "leaq    $dst, $mem\t# ptr 32" %}
5453   opcode(0x8D);
5454   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5455   ins_pipe(ialu_reg_reg_fat);
5456 %}
5457 
5458 // instruct leaPIdx(rRegP dst, indIndex mem)
5459 // %{
5460 //   match(Set dst mem);
5461 
5462 //   ins_cost(110);
5463 //   format %{ "leaq    $dst, $mem\t# ptr idx" %}
5464 //   opcode(0x8D);
5465 //   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5466 //   ins_pipe(ialu_reg_reg_fat);
5467 // %}
5468 
5469 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5470 %{
5471   match(Set dst mem);
5472 
5473   ins_cost(110);
5474   format %{ "leaq    $dst, $mem\t# ptr idxoff" %}
5475   opcode(0x8D);
5476   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5477   ins_pipe(ialu_reg_reg_fat);
5478 %}
5479 
5480 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5481 %{
5482   match(Set dst mem);
5483 
5484   ins_cost(110);
5485   format %{ "leaq    $dst, $mem\t# ptr idxscale" %}
5486   opcode(0x8D);
5487   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5488   ins_pipe(ialu_reg_reg_fat);
5489 %}
5490 
5491 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5492 %{
5493   match(Set dst mem);
5494 
5495   ins_cost(110);
5496   format %{ "leaq    $dst, $mem\t# ptr idxscale" %}
5497   opcode(0x8D);
5498   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5499   ins_pipe(ialu_reg_reg_fat);
5500 %}
5501 
5502 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5503 %{
5504   match(Set dst mem);
5505 
5506   ins_cost(110);
5507   format %{ "leaq    $dst, $mem\t# ptr idxscaleoff" %}
5508   opcode(0x8D);
5509   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5510   ins_pipe(ialu_reg_reg_fat);
5511 %}
5512 
5513 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5514 %{
5515   match(Set dst mem);
5516 
5517   ins_cost(110);
5518   format %{ "leaq    $dst, $mem\t# ptr posidxoff" %}
5519   opcode(0x8D);
5520   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5521   ins_pipe(ialu_reg_reg_fat);
5522 %}
5523 
5524 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5525 %{
5526   match(Set dst mem);
5527 
5528   ins_cost(110);
5529   format %{ "leaq    $dst, $mem\t# ptr posidxscaleoff" %}
5530   opcode(0x8D);
5531   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5532   ins_pipe(ialu_reg_reg_fat);
5533 %}
5534 
5535 // Load Effective Address which uses Narrow (32-bits) oop
5536 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5537 %{
5538   predicate(UseCompressedOops && (CompressedOops::shift() != 0));
5539   match(Set dst mem);
5540 
5541   ins_cost(110);
5542   format %{ "leaq    $dst, $mem\t# ptr compressedoopoff32" %}
5543   opcode(0x8D);
5544   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5545   ins_pipe(ialu_reg_reg_fat);
5546 %}
5547 
5548 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5549 %{
5550   predicate(CompressedOops::shift() == 0);
5551   match(Set dst mem);
5552 
5553   ins_cost(110); // XXX
5554   format %{ "leaq    $dst, $mem\t# ptr off8narrow" %}
5555   opcode(0x8D);
5556   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5557   ins_pipe(ialu_reg_reg_fat);
5558 %}
5559 
5560 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5561 %{
5562   predicate(CompressedOops::shift() == 0);
5563   match(Set dst mem);
5564 
5565   ins_cost(110);
5566   format %{ "leaq    $dst, $mem\t# ptr off32narrow" %}
5567   opcode(0x8D);
5568   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5569   ins_pipe(ialu_reg_reg_fat);
5570 %}
5571 
5572 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5573 %{
5574   predicate(CompressedOops::shift() == 0);
5575   match(Set dst mem);
5576 
5577   ins_cost(110);
5578   format %{ "leaq    $dst, $mem\t# ptr idxoffnarrow" %}
5579   opcode(0x8D);
5580   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5581   ins_pipe(ialu_reg_reg_fat);
5582 %}
5583 
5584 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5585 %{
5586   predicate(CompressedOops::shift() == 0);
5587   match(Set dst mem);
5588 
5589   ins_cost(110);
5590   format %{ "leaq    $dst, $mem\t# ptr idxscalenarrow" %}
5591   opcode(0x8D);
5592   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5593   ins_pipe(ialu_reg_reg_fat);
5594 %}
5595 
5596 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5597 %{
5598   predicate(CompressedOops::shift() == 0);
5599   match(Set dst mem);
5600 
5601   ins_cost(110);
5602   format %{ "leaq    $dst, $mem\t# ptr idxscaleoffnarrow" %}
5603   opcode(0x8D);
5604   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5605   ins_pipe(ialu_reg_reg_fat);
5606 %}
5607 
5608 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5609 %{
5610   predicate(CompressedOops::shift() == 0);
5611   match(Set dst mem);
5612 
5613   ins_cost(110);
5614   format %{ "leaq    $dst, $mem\t# ptr posidxoffnarrow" %}
5615   opcode(0x8D);
5616   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5617   ins_pipe(ialu_reg_reg_fat);
5618 %}
5619 
5620 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5621 %{
5622   predicate(CompressedOops::shift() == 0);
5623   match(Set dst mem);
5624 
5625   ins_cost(110);
5626   format %{ "leaq    $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5627   opcode(0x8D);
5628   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5629   ins_pipe(ialu_reg_reg_fat);
5630 %}
5631 
5632 instruct loadConI(rRegI dst, immI src)
5633 %{
5634   match(Set dst src);
5635 
5636   format %{ "movl    $dst, $src\t# int" %}
5637   ins_encode(load_immI(dst, src));
5638   ins_pipe(ialu_reg_fat); // XXX
5639 %}
5640 
5641 instruct loadConI0(rRegI dst, immI_0 src, rFlagsReg cr)
5642 %{
5643   match(Set dst src);
5644   effect(KILL cr);
5645 
5646   ins_cost(50);
5647   format %{ "xorl    $dst, $dst\t# int" %}
5648   opcode(0x33); /* + rd */
5649   ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5650   ins_pipe(ialu_reg);
5651 %}
5652 
5653 instruct loadConL(rRegL dst, immL src)
5654 %{
5655   match(Set dst src);
5656 
5657   ins_cost(150);
5658   format %{ "movq    $dst, $src\t# long" %}
5659   ins_encode(load_immL(dst, src));
5660   ins_pipe(ialu_reg);
5661 %}
5662 
5663 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5664 %{
5665   match(Set dst src);
5666   effect(KILL cr);
5667 
5668   ins_cost(50);
5669   format %{ "xorl    $dst, $dst\t# long" %}
5670   opcode(0x33); /* + rd */
5671   ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5672   ins_pipe(ialu_reg); // XXX
5673 %}
5674 
5675 instruct loadConUL32(rRegL dst, immUL32 src)
5676 %{
5677   match(Set dst src);
5678 
5679   ins_cost(60);
5680   format %{ "movl    $dst, $src\t# long (unsigned 32-bit)" %}
5681   ins_encode(load_immUL32(dst, src));
5682   ins_pipe(ialu_reg);
5683 %}
5684 
5685 instruct loadConL32(rRegL dst, immL32 src)
5686 %{
5687   match(Set dst src);
5688 
5689   ins_cost(70);
5690   format %{ "movq    $dst, $src\t# long (32-bit)" %}
5691   ins_encode(load_immL32(dst, src));
5692   ins_pipe(ialu_reg);
5693 %}
5694 
5695 instruct loadConP(rRegP dst, immP con) %{
5696   match(Set dst con);
5697 
5698   format %{ "movq    $dst, $con\t# ptr" %}
5699   ins_encode(load_immP(dst, con));
5700   ins_pipe(ialu_reg_fat); // XXX
5701 %}
5702 
5703 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5704 %{
5705   match(Set dst src);
5706   effect(KILL cr);
5707 
5708   ins_cost(50);
5709   format %{ "xorl    $dst, $dst\t# ptr" %}
5710   opcode(0x33); /* + rd */
5711   ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5712   ins_pipe(ialu_reg);
5713 %}
5714 
5715 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5716 %{
5717   match(Set dst src);
5718   effect(KILL cr);
5719 
5720   ins_cost(60);
5721   format %{ "movl    $dst, $src\t# ptr (positive 32-bit)" %}
5722   ins_encode(load_immP31(dst, src));
5723   ins_pipe(ialu_reg);
5724 %}
5725 
5726 instruct loadConF(regF dst, immF con) %{
5727   match(Set dst con);
5728   ins_cost(125);
5729   format %{ "movss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5730   ins_encode %{
5731     __ movflt($dst$$XMMRegister, $constantaddress($con));
5732   %}
5733   ins_pipe(pipe_slow);
5734 %}
5735 
5736 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5737   match(Set dst src);
5738   effect(KILL cr);
5739   format %{ "xorq    $dst, $src\t# compressed NULL ptr" %}
5740   ins_encode %{
5741     __ xorq($dst$$Register, $dst$$Register);
5742   %}
5743   ins_pipe(ialu_reg);
5744 %}
5745 
5746 instruct loadConN(rRegN dst, immN src) %{
5747   match(Set dst src);
5748 
5749   ins_cost(125);
5750   format %{ "movl    $dst, $src\t# compressed ptr" %}
5751   ins_encode %{
5752     address con = (address)$src$$constant;
5753     if (con == NULL) {
5754       ShouldNotReachHere();
5755     } else {
5756       __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5757     }
5758   %}
5759   ins_pipe(ialu_reg_fat); // XXX
5760 %}
5761 
5762 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5763   match(Set dst src);
5764 
5765   ins_cost(125);
5766   format %{ "movl    $dst, $src\t# compressed klass ptr" %}
5767   ins_encode %{
5768     address con = (address)$src$$constant;
5769     if (con == NULL) {
5770       ShouldNotReachHere();
5771     } else {
5772       __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5773     }
5774   %}
5775   ins_pipe(ialu_reg_fat); // XXX
5776 %}
5777 
5778 instruct loadConF0(regF dst, immF0 src)
5779 %{
5780   match(Set dst src);
5781   ins_cost(100);
5782 
5783   format %{ "xorps   $dst, $dst\t# float 0.0" %}
5784   ins_encode %{
5785     __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5786   %}
5787   ins_pipe(pipe_slow);
5788 %}
5789 
5790 // Use the same format since predicate() can not be used here.
5791 instruct loadConD(regD dst, immD con) %{
5792   match(Set dst con);
5793   ins_cost(125);
5794   format %{ "movsd   $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5795   ins_encode %{
5796     __ movdbl($dst$$XMMRegister, $constantaddress($con));
5797   %}
5798   ins_pipe(pipe_slow);
5799 %}
5800 
5801 instruct loadConD0(regD dst, immD0 src)
5802 %{
5803   match(Set dst src);
5804   ins_cost(100);
5805 
5806   format %{ "xorpd   $dst, $dst\t# double 0.0" %}
5807   ins_encode %{
5808     __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5809   %}
5810   ins_pipe(pipe_slow);
5811 %}
5812 
5813 instruct loadSSI(rRegI dst, stackSlotI src)
5814 %{
5815   match(Set dst src);
5816 
5817   ins_cost(125);
5818   format %{ "movl    $dst, $src\t# int stk" %}
5819   opcode(0x8B);
5820   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5821   ins_pipe(ialu_reg_mem);
5822 %}
5823 
5824 instruct loadSSL(rRegL dst, stackSlotL src)
5825 %{
5826   match(Set dst src);
5827 
5828   ins_cost(125);
5829   format %{ "movq    $dst, $src\t# long stk" %}
5830   opcode(0x8B);
5831   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5832   ins_pipe(ialu_reg_mem);
5833 %}
5834 
5835 instruct loadSSP(rRegP dst, stackSlotP src)
5836 %{
5837   match(Set dst src);
5838 
5839   ins_cost(125);
5840   format %{ "movq    $dst, $src\t# ptr stk" %}
5841   opcode(0x8B);
5842   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5843   ins_pipe(ialu_reg_mem);
5844 %}
5845 
5846 instruct loadSSF(regF dst, stackSlotF src)
5847 %{
5848   match(Set dst src);
5849 
5850   ins_cost(125);
5851   format %{ "movss   $dst, $src\t# float stk" %}
5852   ins_encode %{
5853     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5854   %}
5855   ins_pipe(pipe_slow); // XXX
5856 %}
5857 
5858 // Use the same format since predicate() can not be used here.
5859 instruct loadSSD(regD dst, stackSlotD src)
5860 %{
5861   match(Set dst src);
5862 
5863   ins_cost(125);
5864   format %{ "movsd   $dst, $src\t# double stk" %}
5865   ins_encode  %{
5866     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5867   %}
5868   ins_pipe(pipe_slow); // XXX
5869 %}
5870 
5871 // Prefetch instructions for allocation.
5872 // Must be safe to execute with invalid address (cannot fault).
5873 
5874 instruct prefetchAlloc( memory mem ) %{
5875   predicate(AllocatePrefetchInstr==3);
5876   match(PrefetchAllocation mem);
5877   ins_cost(125);
5878 
5879   format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5880   ins_encode %{
5881     __ prefetchw($mem$$Address);
5882   %}
5883   ins_pipe(ialu_mem);
5884 %}
5885 
5886 instruct prefetchAllocNTA( memory mem ) %{
5887   predicate(AllocatePrefetchInstr==0);
5888   match(PrefetchAllocation mem);
5889   ins_cost(125);
5890 
5891   format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5892   ins_encode %{
5893     __ prefetchnta($mem$$Address);
5894   %}
5895   ins_pipe(ialu_mem);
5896 %}
5897 
5898 instruct prefetchAllocT0( memory mem ) %{
5899   predicate(AllocatePrefetchInstr==1);
5900   match(PrefetchAllocation mem);
5901   ins_cost(125);
5902 
5903   format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5904   ins_encode %{
5905     __ prefetcht0($mem$$Address);
5906   %}
5907   ins_pipe(ialu_mem);
5908 %}
5909 
5910 instruct prefetchAllocT2( memory mem ) %{
5911   predicate(AllocatePrefetchInstr==2);
5912   match(PrefetchAllocation mem);
5913   ins_cost(125);
5914 
5915   format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5916   ins_encode %{
5917     __ prefetcht2($mem$$Address);
5918   %}
5919   ins_pipe(ialu_mem);
5920 %}
5921 
5922 //----------Store Instructions-------------------------------------------------
5923 
5924 // Store Byte
5925 instruct storeB(memory mem, rRegI src)
5926 %{
5927   match(Set mem (StoreB mem src));
5928 
5929   ins_cost(125); // XXX
5930   format %{ "movb    $mem, $src\t# byte" %}
5931   opcode(0x88);
5932   ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5933   ins_pipe(ialu_mem_reg);
5934 %}
5935 
5936 // Store Char/Short
5937 instruct storeC(memory mem, rRegI src)
5938 %{
5939   match(Set mem (StoreC mem src));
5940 
5941   ins_cost(125); // XXX
5942   format %{ "movw    $mem, $src\t# char/short" %}
5943   opcode(0x89);
5944   ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5945   ins_pipe(ialu_mem_reg);
5946 %}
5947 
5948 // Store Integer
5949 instruct storeI(memory mem, rRegI src)
5950 %{
5951   match(Set mem (StoreI mem src));
5952 
5953   ins_cost(125); // XXX
5954   format %{ "movl    $mem, $src\t# int" %}
5955   opcode(0x89);
5956   ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5957   ins_pipe(ialu_mem_reg);
5958 %}
5959 
5960 // Store Long
5961 instruct storeL(memory mem, rRegL src)
5962 %{
5963   match(Set mem (StoreL mem src));
5964 
5965   ins_cost(125); // XXX
5966   format %{ "movq    $mem, $src\t# long" %}
5967   opcode(0x89);
5968   ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5969   ins_pipe(ialu_mem_reg); // XXX
5970 %}
5971 
5972 // Store Pointer
5973 instruct storeP(memory mem, any_RegP src)
5974 %{
5975   match(Set mem (StoreP mem src));
5976 
5977   ins_cost(125); // XXX
5978   format %{ "movq    $mem, $src\t# ptr" %}
5979   opcode(0x89);
5980   ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5981   ins_pipe(ialu_mem_reg);
5982 %}
5983 
5984 instruct storeImmP0(memory mem, immP0 zero)
5985 %{
5986   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
5987   match(Set mem (StoreP mem zero));
5988 
5989   ins_cost(125); // XXX
5990   format %{ "movq    $mem, R12\t# ptr (R12_heapbase==0)" %}
5991   ins_encode %{
5992     __ movq($mem$$Address, r12);
5993   %}
5994   ins_pipe(ialu_mem_reg);
5995 %}
5996 
5997 // Store NULL Pointer, mark word, or other simple pointer constant.
5998 instruct storeImmP(memory mem, immP31 src)
5999 %{
6000   match(Set mem (StoreP mem src));
6001 
6002   ins_cost(150); // XXX
6003   format %{ "movq    $mem, $src\t# ptr" %}
6004   opcode(0xC7); /* C7 /0 */
6005   ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6006   ins_pipe(ialu_mem_imm);
6007 %}
6008 
6009 // Store Compressed Pointer
6010 instruct storeN(memory mem, rRegN src)
6011 %{
6012   match(Set mem (StoreN mem src));
6013 
6014   ins_cost(125); // XXX
6015   format %{ "movl    $mem, $src\t# compressed ptr" %}
6016   ins_encode %{
6017     __ movl($mem$$Address, $src$$Register);
6018   %}
6019   ins_pipe(ialu_mem_reg);
6020 %}
6021 
6022 instruct storeNKlass(memory mem, rRegN src)
6023 %{
6024   match(Set mem (StoreNKlass mem src));
6025 
6026   ins_cost(125); // XXX
6027   format %{ "movl    $mem, $src\t# compressed klass ptr" %}
6028   ins_encode %{
6029     __ movl($mem$$Address, $src$$Register);
6030   %}
6031   ins_pipe(ialu_mem_reg);
6032 %}
6033 
6034 instruct storeImmN0(memory mem, immN0 zero)
6035 %{
6036   predicate(CompressedOops::base() == NULL);
6037   match(Set mem (StoreN mem zero));
6038 
6039   ins_cost(125); // XXX
6040   format %{ "movl    $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6041   ins_encode %{
6042     __ movl($mem$$Address, r12);
6043   %}
6044   ins_pipe(ialu_mem_reg);
6045 %}
6046 
6047 instruct storeImmN(memory mem, immN src)
6048 %{
6049   match(Set mem (StoreN mem src));
6050 
6051   ins_cost(150); // XXX
6052   format %{ "movl    $mem, $src\t# compressed ptr" %}
6053   ins_encode %{
6054     address con = (address)$src$$constant;
6055     if (con == NULL) {
6056       __ movl($mem$$Address, (int32_t)0);
6057     } else {
6058       __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6059     }
6060   %}
6061   ins_pipe(ialu_mem_imm);
6062 %}
6063 
6064 instruct storeImmNKlass(memory mem, immNKlass src)
6065 %{
6066   match(Set mem (StoreNKlass mem src));
6067 
6068   ins_cost(150); // XXX
6069   format %{ "movl    $mem, $src\t# compressed klass ptr" %}
6070   ins_encode %{
6071     __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6072   %}
6073   ins_pipe(ialu_mem_imm);
6074 %}
6075 
6076 // Store Integer Immediate
6077 instruct storeImmI0(memory mem, immI_0 zero)
6078 %{
6079   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6080   match(Set mem (StoreI mem zero));
6081 
6082   ins_cost(125); // XXX
6083   format %{ "movl    $mem, R12\t# int (R12_heapbase==0)" %}
6084   ins_encode %{
6085     __ movl($mem$$Address, r12);
6086   %}
6087   ins_pipe(ialu_mem_reg);
6088 %}
6089 
6090 instruct storeImmI(memory mem, immI src)
6091 %{
6092   match(Set mem (StoreI mem src));
6093 
6094   ins_cost(150);
6095   format %{ "movl    $mem, $src\t# int" %}
6096   opcode(0xC7); /* C7 /0 */
6097   ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6098   ins_pipe(ialu_mem_imm);
6099 %}
6100 
6101 // Store Long Immediate
6102 instruct storeImmL0(memory mem, immL0 zero)
6103 %{
6104   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6105   match(Set mem (StoreL mem zero));
6106 
6107   ins_cost(125); // XXX
6108   format %{ "movq    $mem, R12\t# long (R12_heapbase==0)" %}
6109   ins_encode %{
6110     __ movq($mem$$Address, r12);
6111   %}
6112   ins_pipe(ialu_mem_reg);
6113 %}
6114 
6115 instruct storeImmL(memory mem, immL32 src)
6116 %{
6117   match(Set mem (StoreL mem src));
6118 
6119   ins_cost(150);
6120   format %{ "movq    $mem, $src\t# long" %}
6121   opcode(0xC7); /* C7 /0 */
6122   ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6123   ins_pipe(ialu_mem_imm);
6124 %}
6125 
6126 // Store Short/Char Immediate
6127 instruct storeImmC0(memory mem, immI_0 zero)
6128 %{
6129   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6130   match(Set mem (StoreC mem zero));
6131 
6132   ins_cost(125); // XXX
6133   format %{ "movw    $mem, R12\t# short/char (R12_heapbase==0)" %}
6134   ins_encode %{
6135     __ movw($mem$$Address, r12);
6136   %}
6137   ins_pipe(ialu_mem_reg);
6138 %}
6139 
6140 instruct storeImmI16(memory mem, immI16 src)
6141 %{
6142   predicate(UseStoreImmI16);
6143   match(Set mem (StoreC mem src));
6144 
6145   ins_cost(150);
6146   format %{ "movw    $mem, $src\t# short/char" %}
6147   opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6148   ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6149   ins_pipe(ialu_mem_imm);
6150 %}
6151 
6152 // Store Byte Immediate
6153 instruct storeImmB0(memory mem, immI_0 zero)
6154 %{
6155   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6156   match(Set mem (StoreB mem zero));
6157 
6158   ins_cost(125); // XXX
6159   format %{ "movb    $mem, R12\t# short/char (R12_heapbase==0)" %}
6160   ins_encode %{
6161     __ movb($mem$$Address, r12);
6162   %}
6163   ins_pipe(ialu_mem_reg);
6164 %}
6165 
6166 instruct storeImmB(memory mem, immI8 src)
6167 %{
6168   match(Set mem (StoreB mem src));
6169 
6170   ins_cost(150); // XXX
6171   format %{ "movb    $mem, $src\t# byte" %}
6172   opcode(0xC6); /* C6 /0 */
6173   ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6174   ins_pipe(ialu_mem_imm);
6175 %}
6176 
6177 // Store CMS card-mark Immediate
6178 instruct storeImmCM0_reg(memory mem, immI_0 zero)
6179 %{
6180   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6181   match(Set mem (StoreCM mem zero));
6182 
6183   ins_cost(125); // XXX
6184   format %{ "movb    $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6185   ins_encode %{
6186     __ movb($mem$$Address, r12);
6187   %}
6188   ins_pipe(ialu_mem_reg);
6189 %}
6190 
6191 instruct storeImmCM0(memory mem, immI_0 src)
6192 %{
6193   match(Set mem (StoreCM mem src));
6194 
6195   ins_cost(150); // XXX
6196   format %{ "movb    $mem, $src\t# CMS card-mark byte 0" %}
6197   opcode(0xC6); /* C6 /0 */
6198   ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6199   ins_pipe(ialu_mem_imm);
6200 %}
6201 
6202 // Store Float
6203 instruct storeF(memory mem, regF src)
6204 %{
6205   match(Set mem (StoreF mem src));
6206 
6207   ins_cost(95); // XXX
6208   format %{ "movss   $mem, $src\t# float" %}
6209   ins_encode %{
6210     __ movflt($mem$$Address, $src$$XMMRegister);
6211   %}
6212   ins_pipe(pipe_slow); // XXX
6213 %}
6214 
6215 // Store immediate Float value (it is faster than store from XMM register)
6216 instruct storeF0(memory mem, immF0 zero)
6217 %{
6218   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6219   match(Set mem (StoreF mem zero));
6220 
6221   ins_cost(25); // XXX
6222   format %{ "movl    $mem, R12\t# float 0. (R12_heapbase==0)" %}
6223   ins_encode %{
6224     __ movl($mem$$Address, r12);
6225   %}
6226   ins_pipe(ialu_mem_reg);
6227 %}
6228 
6229 instruct storeF_imm(memory mem, immF src)
6230 %{
6231   match(Set mem (StoreF mem src));
6232 
6233   ins_cost(50);
6234   format %{ "movl    $mem, $src\t# float" %}
6235   opcode(0xC7); /* C7 /0 */
6236   ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6237   ins_pipe(ialu_mem_imm);
6238 %}
6239 
6240 // Store Double
6241 instruct storeD(memory mem, regD src)
6242 %{
6243   match(Set mem (StoreD mem src));
6244 
6245   ins_cost(95); // XXX
6246   format %{ "movsd   $mem, $src\t# double" %}
6247   ins_encode %{
6248     __ movdbl($mem$$Address, $src$$XMMRegister);
6249   %}
6250   ins_pipe(pipe_slow); // XXX
6251 %}
6252 
6253 // Store immediate double 0.0 (it is faster than store from XMM register)
6254 instruct storeD0_imm(memory mem, immD0 src)
6255 %{
6256   predicate(!UseCompressedOops || (CompressedOops::base() != NULL));
6257   match(Set mem (StoreD mem src));
6258 
6259   ins_cost(50);
6260   format %{ "movq    $mem, $src\t# double 0." %}
6261   opcode(0xC7); /* C7 /0 */
6262   ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6263   ins_pipe(ialu_mem_imm);
6264 %}
6265 
6266 instruct storeD0(memory mem, immD0 zero)
6267 %{
6268   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6269   match(Set mem (StoreD mem zero));
6270 
6271   ins_cost(25); // XXX
6272   format %{ "movq    $mem, R12\t# double 0. (R12_heapbase==0)" %}
6273   ins_encode %{
6274     __ movq($mem$$Address, r12);
6275   %}
6276   ins_pipe(ialu_mem_reg);
6277 %}
6278 
6279 instruct storeSSI(stackSlotI dst, rRegI src)
6280 %{
6281   match(Set dst src);
6282 
6283   ins_cost(100);
6284   format %{ "movl    $dst, $src\t# int stk" %}
6285   opcode(0x89);
6286   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6287   ins_pipe( ialu_mem_reg );
6288 %}
6289 
6290 instruct storeSSL(stackSlotL dst, rRegL src)
6291 %{
6292   match(Set dst src);
6293 
6294   ins_cost(100);
6295   format %{ "movq    $dst, $src\t# long stk" %}
6296   opcode(0x89);
6297   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6298   ins_pipe(ialu_mem_reg);
6299 %}
6300 
6301 instruct storeSSP(stackSlotP dst, rRegP src)
6302 %{
6303   match(Set dst src);
6304 
6305   ins_cost(100);
6306   format %{ "movq    $dst, $src\t# ptr stk" %}
6307   opcode(0x89);
6308   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6309   ins_pipe(ialu_mem_reg);
6310 %}
6311 
6312 instruct storeSSF(stackSlotF dst, regF src)
6313 %{
6314   match(Set dst src);
6315 
6316   ins_cost(95); // XXX
6317   format %{ "movss   $dst, $src\t# float stk" %}
6318   ins_encode %{
6319     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6320   %}
6321   ins_pipe(pipe_slow); // XXX
6322 %}
6323 
6324 instruct storeSSD(stackSlotD dst, regD src)
6325 %{
6326   match(Set dst src);
6327 
6328   ins_cost(95); // XXX
6329   format %{ "movsd   $dst, $src\t# double stk" %}
6330   ins_encode %{
6331     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6332   %}
6333   ins_pipe(pipe_slow); // XXX
6334 %}
6335 
6336 instruct cacheWB(indirect addr)
6337 %{
6338   predicate(VM_Version::supports_data_cache_line_flush());
6339   match(CacheWB addr);
6340 
6341   ins_cost(100);
6342   format %{"cache wb $addr" %}
6343   ins_encode %{
6344     assert($addr->index_position() < 0, "should be");
6345     assert($addr$$disp == 0, "should be");
6346     __ cache_wb(Address($addr$$base$$Register, 0));
6347   %}
6348   ins_pipe(pipe_slow); // XXX
6349 %}
6350 
6351 instruct cacheWBPreSync()
6352 %{
6353   predicate(VM_Version::supports_data_cache_line_flush());
6354   match(CacheWBPreSync);
6355 
6356   ins_cost(100);
6357   format %{"cache wb presync" %}
6358   ins_encode %{
6359     __ cache_wbsync(true);
6360   %}
6361   ins_pipe(pipe_slow); // XXX
6362 %}
6363 
6364 instruct cacheWBPostSync()
6365 %{
6366   predicate(VM_Version::supports_data_cache_line_flush());
6367   match(CacheWBPostSync);
6368 
6369   ins_cost(100);
6370   format %{"cache wb postsync" %}
6371   ins_encode %{
6372     __ cache_wbsync(false);
6373   %}
6374   ins_pipe(pipe_slow); // XXX
6375 %}
6376 
6377 //----------BSWAP Instructions-------------------------------------------------
6378 instruct bytes_reverse_int(rRegI dst) %{
6379   match(Set dst (ReverseBytesI dst));
6380 
6381   format %{ "bswapl  $dst" %}
6382   opcode(0x0F, 0xC8);  /*Opcode 0F /C8 */
6383   ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6384   ins_pipe( ialu_reg );
6385 %}
6386 
6387 instruct bytes_reverse_long(rRegL dst) %{
6388   match(Set dst (ReverseBytesL dst));
6389 
6390   format %{ "bswapq  $dst" %}
6391   opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6392   ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6393   ins_pipe( ialu_reg);
6394 %}
6395 
6396 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6397   match(Set dst (ReverseBytesUS dst));
6398   effect(KILL cr);
6399 
6400   format %{ "bswapl  $dst\n\t"
6401             "shrl    $dst,16\n\t" %}
6402   ins_encode %{
6403     __ bswapl($dst$$Register);
6404     __ shrl($dst$$Register, 16);
6405   %}
6406   ins_pipe( ialu_reg );
6407 %}
6408 
6409 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6410   match(Set dst (ReverseBytesS dst));
6411   effect(KILL cr);
6412 
6413   format %{ "bswapl  $dst\n\t"
6414             "sar     $dst,16\n\t" %}
6415   ins_encode %{
6416     __ bswapl($dst$$Register);
6417     __ sarl($dst$$Register, 16);
6418   %}
6419   ins_pipe( ialu_reg );
6420 %}
6421 
6422 //---------- Zeros Count Instructions ------------------------------------------
6423 
6424 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6425   predicate(UseCountLeadingZerosInstruction);
6426   match(Set dst (CountLeadingZerosI src));
6427   effect(KILL cr);
6428 
6429   format %{ "lzcntl  $dst, $src\t# count leading zeros (int)" %}
6430   ins_encode %{
6431     __ lzcntl($dst$$Register, $src$$Register);
6432   %}
6433   ins_pipe(ialu_reg);
6434 %}
6435 
6436 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6437   predicate(!UseCountLeadingZerosInstruction);
6438   match(Set dst (CountLeadingZerosI src));
6439   effect(KILL cr);
6440 
6441   format %{ "bsrl    $dst, $src\t# count leading zeros (int)\n\t"
6442             "jnz     skip\n\t"
6443             "movl    $dst, -1\n"
6444       "skip:\n\t"
6445             "negl    $dst\n\t"
6446             "addl    $dst, 31" %}
6447   ins_encode %{
6448     Register Rdst = $dst$$Register;
6449     Register Rsrc = $src$$Register;
6450     Label skip;
6451     __ bsrl(Rdst, Rsrc);
6452     __ jccb(Assembler::notZero, skip);
6453     __ movl(Rdst, -1);
6454     __ bind(skip);
6455     __ negl(Rdst);
6456     __ addl(Rdst, BitsPerInt - 1);
6457   %}
6458   ins_pipe(ialu_reg);
6459 %}
6460 
6461 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6462   predicate(UseCountLeadingZerosInstruction);
6463   match(Set dst (CountLeadingZerosL src));
6464   effect(KILL cr);
6465 
6466   format %{ "lzcntq  $dst, $src\t# count leading zeros (long)" %}
6467   ins_encode %{
6468     __ lzcntq($dst$$Register, $src$$Register);
6469   %}
6470   ins_pipe(ialu_reg);
6471 %}
6472 
6473 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6474   predicate(!UseCountLeadingZerosInstruction);
6475   match(Set dst (CountLeadingZerosL src));
6476   effect(KILL cr);
6477 
6478   format %{ "bsrq    $dst, $src\t# count leading zeros (long)\n\t"
6479             "jnz     skip\n\t"
6480             "movl    $dst, -1\n"
6481       "skip:\n\t"
6482             "negl    $dst\n\t"
6483             "addl    $dst, 63" %}
6484   ins_encode %{
6485     Register Rdst = $dst$$Register;
6486     Register Rsrc = $src$$Register;
6487     Label skip;
6488     __ bsrq(Rdst, Rsrc);
6489     __ jccb(Assembler::notZero, skip);
6490     __ movl(Rdst, -1);
6491     __ bind(skip);
6492     __ negl(Rdst);
6493     __ addl(Rdst, BitsPerLong - 1);
6494   %}
6495   ins_pipe(ialu_reg);
6496 %}
6497 
6498 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6499   predicate(UseCountTrailingZerosInstruction);
6500   match(Set dst (CountTrailingZerosI src));
6501   effect(KILL cr);
6502 
6503   format %{ "tzcntl    $dst, $src\t# count trailing zeros (int)" %}
6504   ins_encode %{
6505     __ tzcntl($dst$$Register, $src$$Register);
6506   %}
6507   ins_pipe(ialu_reg);
6508 %}
6509 
6510 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6511   predicate(!UseCountTrailingZerosInstruction);
6512   match(Set dst (CountTrailingZerosI src));
6513   effect(KILL cr);
6514 
6515   format %{ "bsfl    $dst, $src\t# count trailing zeros (int)\n\t"
6516             "jnz     done\n\t"
6517             "movl    $dst, 32\n"
6518       "done:" %}
6519   ins_encode %{
6520     Register Rdst = $dst$$Register;
6521     Label done;
6522     __ bsfl(Rdst, $src$$Register);
6523     __ jccb(Assembler::notZero, done);
6524     __ movl(Rdst, BitsPerInt);
6525     __ bind(done);
6526   %}
6527   ins_pipe(ialu_reg);
6528 %}
6529 
6530 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6531   predicate(UseCountTrailingZerosInstruction);
6532   match(Set dst (CountTrailingZerosL src));
6533   effect(KILL cr);
6534 
6535   format %{ "tzcntq    $dst, $src\t# count trailing zeros (long)" %}
6536   ins_encode %{
6537     __ tzcntq($dst$$Register, $src$$Register);
6538   %}
6539   ins_pipe(ialu_reg);
6540 %}
6541 
6542 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6543   predicate(!UseCountTrailingZerosInstruction);
6544   match(Set dst (CountTrailingZerosL src));
6545   effect(KILL cr);
6546 
6547   format %{ "bsfq    $dst, $src\t# count trailing zeros (long)\n\t"
6548             "jnz     done\n\t"
6549             "movl    $dst, 64\n"
6550       "done:" %}
6551   ins_encode %{
6552     Register Rdst = $dst$$Register;
6553     Label done;
6554     __ bsfq(Rdst, $src$$Register);
6555     __ jccb(Assembler::notZero, done);
6556     __ movl(Rdst, BitsPerLong);
6557     __ bind(done);
6558   %}
6559   ins_pipe(ialu_reg);
6560 %}
6561 
6562 
6563 //---------- Population Count Instructions -------------------------------------
6564 
6565 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6566   predicate(UsePopCountInstruction);
6567   match(Set dst (PopCountI src));
6568   effect(KILL cr);
6569 
6570   format %{ "popcnt  $dst, $src" %}
6571   ins_encode %{
6572     __ popcntl($dst$$Register, $src$$Register);
6573   %}
6574   ins_pipe(ialu_reg);
6575 %}
6576 
6577 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6578   predicate(UsePopCountInstruction);
6579   match(Set dst (PopCountI (LoadI mem)));
6580   effect(KILL cr);
6581 
6582   format %{ "popcnt  $dst, $mem" %}
6583   ins_encode %{
6584     __ popcntl($dst$$Register, $mem$$Address);
6585   %}
6586   ins_pipe(ialu_reg);
6587 %}
6588 
6589 // Note: Long.bitCount(long) returns an int.
6590 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6591   predicate(UsePopCountInstruction);
6592   match(Set dst (PopCountL src));
6593   effect(KILL cr);
6594 
6595   format %{ "popcnt  $dst, $src" %}
6596   ins_encode %{
6597     __ popcntq($dst$$Register, $src$$Register);
6598   %}
6599   ins_pipe(ialu_reg);
6600 %}
6601 
6602 // Note: Long.bitCount(long) returns an int.
6603 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6604   predicate(UsePopCountInstruction);
6605   match(Set dst (PopCountL (LoadL mem)));
6606   effect(KILL cr);
6607 
6608   format %{ "popcnt  $dst, $mem" %}
6609   ins_encode %{
6610     __ popcntq($dst$$Register, $mem$$Address);
6611   %}
6612   ins_pipe(ialu_reg);
6613 %}
6614 
6615 
6616 //----------MemBar Instructions-----------------------------------------------
6617 // Memory barrier flavors
6618 
6619 instruct membar_acquire()
6620 %{
6621   match(MemBarAcquire);
6622   match(LoadFence);
6623   ins_cost(0);
6624 
6625   size(0);
6626   format %{ "MEMBAR-acquire ! (empty encoding)" %}
6627   ins_encode();
6628   ins_pipe(empty);
6629 %}
6630 
6631 instruct membar_acquire_lock()
6632 %{
6633   match(MemBarAcquireLock);
6634   ins_cost(0);
6635 
6636   size(0);
6637   format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6638   ins_encode();
6639   ins_pipe(empty);
6640 %}
6641 
6642 instruct membar_release()
6643 %{
6644   match(MemBarRelease);
6645   match(StoreFence);
6646   ins_cost(0);
6647 
6648   size(0);
6649   format %{ "MEMBAR-release ! (empty encoding)" %}
6650   ins_encode();
6651   ins_pipe(empty);
6652 %}
6653 
6654 instruct membar_release_lock()
6655 %{
6656   match(MemBarReleaseLock);
6657   ins_cost(0);
6658 
6659   size(0);
6660   format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6661   ins_encode();
6662   ins_pipe(empty);
6663 %}
6664 
6665 instruct membar_volatile(rFlagsReg cr) %{
6666   match(MemBarVolatile);
6667   effect(KILL cr);
6668   ins_cost(400);
6669 
6670   format %{
6671     $$template
6672     $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6673   %}
6674   ins_encode %{
6675     __ membar(Assembler::StoreLoad);
6676   %}
6677   ins_pipe(pipe_slow);
6678 %}
6679 
6680 instruct unnecessary_membar_volatile()
6681 %{
6682   match(MemBarVolatile);
6683   predicate(Matcher::post_store_load_barrier(n));
6684   ins_cost(0);
6685 
6686   size(0);
6687   format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6688   ins_encode();
6689   ins_pipe(empty);
6690 %}
6691 
6692 instruct membar_storestore() %{
6693   match(MemBarStoreStore);
6694   ins_cost(0);
6695 
6696   size(0);
6697   format %{ "MEMBAR-storestore (empty encoding)" %}
6698   ins_encode( );
6699   ins_pipe(empty);
6700 %}
6701 
6702 //----------Move Instructions--------------------------------------------------
6703 
6704 instruct castX2P(rRegP dst, rRegL src)
6705 %{
6706   match(Set dst (CastX2P src));
6707 
6708   format %{ "movq    $dst, $src\t# long->ptr" %}
6709   ins_encode %{
6710     if ($dst$$reg != $src$$reg) {
6711       __ movptr($dst$$Register, $src$$Register);
6712     }
6713   %}
6714   ins_pipe(ialu_reg_reg); // XXX
6715 %}
6716 
6717 instruct castP2X(rRegL dst, rRegP src)
6718 %{
6719   match(Set dst (CastP2X src));
6720 
6721   format %{ "movq    $dst, $src\t# ptr -> long" %}
6722   ins_encode %{
6723     if ($dst$$reg != $src$$reg) {
6724       __ movptr($dst$$Register, $src$$Register);
6725     }
6726   %}
6727   ins_pipe(ialu_reg_reg); // XXX
6728 %}
6729 
6730 // Convert oop into int for vectors alignment masking
6731 instruct convP2I(rRegI dst, rRegP src)
6732 %{
6733   match(Set dst (ConvL2I (CastP2X src)));
6734 
6735   format %{ "movl    $dst, $src\t# ptr -> int" %}
6736   ins_encode %{
6737     __ movl($dst$$Register, $src$$Register);
6738   %}
6739   ins_pipe(ialu_reg_reg); // XXX
6740 %}
6741 
6742 // Convert compressed oop into int for vectors alignment masking
6743 // in case of 32bit oops (heap < 4Gb).
6744 instruct convN2I(rRegI dst, rRegN src)
6745 %{
6746   predicate(CompressedOops::shift() == 0);
6747   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6748 
6749   format %{ "movl    $dst, $src\t# compressed ptr -> int" %}
6750   ins_encode %{
6751     __ movl($dst$$Register, $src$$Register);
6752   %}
6753   ins_pipe(ialu_reg_reg); // XXX
6754 %}
6755 
6756 // Convert oop pointer into compressed form
6757 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6758   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6759   match(Set dst (EncodeP src));
6760   effect(KILL cr);
6761   format %{ "encode_heap_oop $dst,$src" %}
6762   ins_encode %{
6763     Register s = $src$$Register;
6764     Register d = $dst$$Register;
6765     if (s != d) {
6766       __ movq(d, s);
6767     }
6768     __ encode_heap_oop(d);
6769   %}
6770   ins_pipe(ialu_reg_long);
6771 %}
6772 
6773 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6774   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6775   match(Set dst (EncodeP src));
6776   effect(KILL cr);
6777   format %{ "encode_heap_oop_not_null $dst,$src" %}
6778   ins_encode %{
6779     __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6780   %}
6781   ins_pipe(ialu_reg_long);
6782 %}
6783 
6784 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6785   predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6786             n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6787   match(Set dst (DecodeN src));
6788   effect(KILL cr);
6789   format %{ "decode_heap_oop $dst,$src" %}
6790   ins_encode %{
6791     Register s = $src$$Register;
6792     Register d = $dst$$Register;
6793     if (s != d) {
6794       __ movq(d, s);
6795     }
6796     __ decode_heap_oop(d);
6797   %}
6798   ins_pipe(ialu_reg_long);
6799 %}
6800 
6801 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6802   predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6803             n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6804   match(Set dst (DecodeN src));
6805   effect(KILL cr);
6806   format %{ "decode_heap_oop_not_null $dst,$src" %}
6807   ins_encode %{
6808     Register s = $src$$Register;
6809     Register d = $dst$$Register;
6810     if (s != d) {
6811       __ decode_heap_oop_not_null(d, s);
6812     } else {
6813       __ decode_heap_oop_not_null(d);
6814     }
6815   %}
6816   ins_pipe(ialu_reg_long);
6817 %}
6818 
6819 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6820   match(Set dst (EncodePKlass src));
6821   effect(TEMP dst, KILL cr);
6822   format %{ "encode_and_move_klass_not_null $dst,$src" %}
6823   ins_encode %{
6824     __ encode_and_move_klass_not_null($dst$$Register, $src$$Register);
6825   %}
6826   ins_pipe(ialu_reg_long);
6827 %}
6828 
6829 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6830   match(Set dst (DecodeNKlass src));
6831   effect(TEMP dst, KILL cr);
6832   format %{ "decode_and_move_klass_not_null $dst,$src" %}
6833   ins_encode %{
6834     __ decode_and_move_klass_not_null($dst$$Register, $src$$Register);
6835   %}
6836   ins_pipe(ialu_reg_long);
6837 %}
6838 
6839 //----------Conditional Move---------------------------------------------------
6840 // Jump
6841 // dummy instruction for generating temp registers
6842 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6843   match(Jump (LShiftL switch_val shift));
6844   ins_cost(350);
6845   predicate(false);
6846   effect(TEMP dest);
6847 
6848   format %{ "leaq    $dest, [$constantaddress]\n\t"
6849             "jmp     [$dest + $switch_val << $shift]\n\t" %}
6850   ins_encode %{
6851     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6852     // to do that and the compiler is using that register as one it can allocate.
6853     // So we build it all by hand.
6854     // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6855     // ArrayAddress dispatch(table, index);
6856     Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6857     __ lea($dest$$Register, $constantaddress);
6858     __ jmp(dispatch);
6859   %}
6860   ins_pipe(pipe_jmp);
6861 %}
6862 
6863 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6864   match(Jump (AddL (LShiftL switch_val shift) offset));
6865   ins_cost(350);
6866   effect(TEMP dest);
6867 
6868   format %{ "leaq    $dest, [$constantaddress]\n\t"
6869             "jmp     [$dest + $switch_val << $shift + $offset]\n\t" %}
6870   ins_encode %{
6871     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6872     // to do that and the compiler is using that register as one it can allocate.
6873     // So we build it all by hand.
6874     // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6875     // ArrayAddress dispatch(table, index);
6876     Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6877     __ lea($dest$$Register, $constantaddress);
6878     __ jmp(dispatch);
6879   %}
6880   ins_pipe(pipe_jmp);
6881 %}
6882 
6883 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6884   match(Jump switch_val);
6885   ins_cost(350);
6886   effect(TEMP dest);
6887 
6888   format %{ "leaq    $dest, [$constantaddress]\n\t"
6889             "jmp     [$dest + $switch_val]\n\t" %}
6890   ins_encode %{
6891     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6892     // to do that and the compiler is using that register as one it can allocate.
6893     // So we build it all by hand.
6894     // Address index(noreg, switch_reg, Address::times_1);
6895     // ArrayAddress dispatch(table, index);
6896     Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6897     __ lea($dest$$Register, $constantaddress);
6898     __ jmp(dispatch);
6899   %}
6900   ins_pipe(pipe_jmp);
6901 %}
6902 
6903 // Conditional move
6904 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6905 %{
6906   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6907 
6908   ins_cost(200); // XXX
6909   format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6910   opcode(0x0F, 0x40);
6911   ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6912   ins_pipe(pipe_cmov_reg);
6913 %}
6914 
6915 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6916   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6917 
6918   ins_cost(200); // XXX
6919   format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6920   opcode(0x0F, 0x40);
6921   ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6922   ins_pipe(pipe_cmov_reg);
6923 %}
6924 
6925 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6926   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6927   ins_cost(200);
6928   expand %{
6929     cmovI_regU(cop, cr, dst, src);
6930   %}
6931 %}
6932 
6933 // Conditional move
6934 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6935   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6936 
6937   ins_cost(250); // XXX
6938   format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6939   opcode(0x0F, 0x40);
6940   ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6941   ins_pipe(pipe_cmov_mem);
6942 %}
6943 
6944 // Conditional move
6945 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6946 %{
6947   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6948 
6949   ins_cost(250); // XXX
6950   format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6951   opcode(0x0F, 0x40);
6952   ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6953   ins_pipe(pipe_cmov_mem);
6954 %}
6955 
6956 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6957   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6958   ins_cost(250);
6959   expand %{
6960     cmovI_memU(cop, cr, dst, src);
6961   %}
6962 %}
6963 
6964 // Conditional move
6965 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6966 %{
6967   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6968 
6969   ins_cost(200); // XXX
6970   format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6971   opcode(0x0F, 0x40);
6972   ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6973   ins_pipe(pipe_cmov_reg);
6974 %}
6975 
6976 // Conditional move
6977 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6978 %{
6979   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6980 
6981   ins_cost(200); // XXX
6982   format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6983   opcode(0x0F, 0x40);
6984   ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6985   ins_pipe(pipe_cmov_reg);
6986 %}
6987 
6988 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6989   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6990   ins_cost(200);
6991   expand %{
6992     cmovN_regU(cop, cr, dst, src);
6993   %}
6994 %}
6995 
6996 // Conditional move
6997 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6998 %{
6999   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7000 
7001   ins_cost(200); // XXX
7002   format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7003   opcode(0x0F, 0x40);
7004   ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7005   ins_pipe(pipe_cmov_reg);  // XXX
7006 %}
7007 
7008 // Conditional move
7009 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7010 %{
7011   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7012 
7013   ins_cost(200); // XXX
7014   format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7015   opcode(0x0F, 0x40);
7016   ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7017   ins_pipe(pipe_cmov_reg); // XXX
7018 %}
7019 
7020 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7021   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7022   ins_cost(200);
7023   expand %{
7024     cmovP_regU(cop, cr, dst, src);
7025   %}
7026 %}
7027 
7028 // DISABLED: Requires the ADLC to emit a bottom_type call that
7029 // correctly meets the two pointer arguments; one is an incoming
7030 // register but the other is a memory operand.  ALSO appears to
7031 // be buggy with implicit null checks.
7032 //
7033 //// Conditional move
7034 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7035 //%{
7036 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7037 //  ins_cost(250);
7038 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
7039 //  opcode(0x0F,0x40);
7040 //  ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7041 //  ins_pipe( pipe_cmov_mem );
7042 //%}
7043 //
7044 //// Conditional move
7045 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7046 //%{
7047 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7048 //  ins_cost(250);
7049 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
7050 //  opcode(0x0F,0x40);
7051 //  ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7052 //  ins_pipe( pipe_cmov_mem );
7053 //%}
7054 
7055 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7056 %{
7057   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7058 
7059   ins_cost(200); // XXX
7060   format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7061   opcode(0x0F, 0x40);
7062   ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7063   ins_pipe(pipe_cmov_reg);  // XXX
7064 %}
7065 
7066 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7067 %{
7068   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7069 
7070   ins_cost(200); // XXX
7071   format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7072   opcode(0x0F, 0x40);
7073   ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7074   ins_pipe(pipe_cmov_mem);  // XXX
7075 %}
7076 
7077 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7078 %{
7079   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7080 
7081   ins_cost(200); // XXX
7082   format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7083   opcode(0x0F, 0x40);
7084   ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7085   ins_pipe(pipe_cmov_reg); // XXX
7086 %}
7087 
7088 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7089   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7090   ins_cost(200);
7091   expand %{
7092     cmovL_regU(cop, cr, dst, src);
7093   %}
7094 %}
7095 
7096 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7097 %{
7098   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7099 
7100   ins_cost(200); // XXX
7101   format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7102   opcode(0x0F, 0x40);
7103   ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7104   ins_pipe(pipe_cmov_mem); // XXX
7105 %}
7106 
7107 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7108   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7109   ins_cost(200);
7110   expand %{
7111     cmovL_memU(cop, cr, dst, src);
7112   %}
7113 %}
7114 
7115 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7116 %{
7117   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7118 
7119   ins_cost(200); // XXX
7120   format %{ "jn$cop    skip\t# signed cmove float\n\t"
7121             "movss     $dst, $src\n"
7122     "skip:" %}
7123   ins_encode %{
7124     Label Lskip;
7125     // Invert sense of branch from sense of CMOV
7126     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7127     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7128     __ bind(Lskip);
7129   %}
7130   ins_pipe(pipe_slow);
7131 %}
7132 
7133 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7134 // %{
7135 //   match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7136 
7137 //   ins_cost(200); // XXX
7138 //   format %{ "jn$cop    skip\t# signed cmove float\n\t"
7139 //             "movss     $dst, $src\n"
7140 //     "skip:" %}
7141 //   ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7142 //   ins_pipe(pipe_slow);
7143 // %}
7144 
7145 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7146 %{
7147   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7148 
7149   ins_cost(200); // XXX
7150   format %{ "jn$cop    skip\t# unsigned cmove float\n\t"
7151             "movss     $dst, $src\n"
7152     "skip:" %}
7153   ins_encode %{
7154     Label Lskip;
7155     // Invert sense of branch from sense of CMOV
7156     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7157     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7158     __ bind(Lskip);
7159   %}
7160   ins_pipe(pipe_slow);
7161 %}
7162 
7163 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7164   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7165   ins_cost(200);
7166   expand %{
7167     cmovF_regU(cop, cr, dst, src);
7168   %}
7169 %}
7170 
7171 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7172 %{
7173   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7174 
7175   ins_cost(200); // XXX
7176   format %{ "jn$cop    skip\t# signed cmove double\n\t"
7177             "movsd     $dst, $src\n"
7178     "skip:" %}
7179   ins_encode %{
7180     Label Lskip;
7181     // Invert sense of branch from sense of CMOV
7182     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7183     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7184     __ bind(Lskip);
7185   %}
7186   ins_pipe(pipe_slow);
7187 %}
7188 
7189 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7190 %{
7191   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7192 
7193   ins_cost(200); // XXX
7194   format %{ "jn$cop    skip\t# unsigned cmove double\n\t"
7195             "movsd     $dst, $src\n"
7196     "skip:" %}
7197   ins_encode %{
7198     Label Lskip;
7199     // Invert sense of branch from sense of CMOV
7200     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7201     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7202     __ bind(Lskip);
7203   %}
7204   ins_pipe(pipe_slow);
7205 %}
7206 
7207 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7208   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7209   ins_cost(200);
7210   expand %{
7211     cmovD_regU(cop, cr, dst, src);
7212   %}
7213 %}
7214 
7215 //----------Arithmetic Instructions--------------------------------------------
7216 //----------Addition Instructions----------------------------------------------
7217 
7218 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7219 %{
7220   match(Set dst (AddI dst src));
7221   effect(KILL cr);
7222 
7223   format %{ "addl    $dst, $src\t# int" %}
7224   opcode(0x03);
7225   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7226   ins_pipe(ialu_reg_reg);
7227 %}
7228 
7229 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7230 %{
7231   match(Set dst (AddI dst src));
7232   effect(KILL cr);
7233 
7234   format %{ "addl    $dst, $src\t# int" %}
7235   opcode(0x81, 0x00); /* /0 id */
7236   ins_encode(OpcSErm(dst, src), Con8or32(src));
7237   ins_pipe( ialu_reg );
7238 %}
7239 
7240 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7241 %{
7242   match(Set dst (AddI dst (LoadI src)));
7243   effect(KILL cr);
7244 
7245   ins_cost(125); // XXX
7246   format %{ "addl    $dst, $src\t# int" %}
7247   opcode(0x03);
7248   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7249   ins_pipe(ialu_reg_mem);
7250 %}
7251 
7252 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7253 %{
7254   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7255   effect(KILL cr);
7256 
7257   ins_cost(150); // XXX
7258   format %{ "addl    $dst, $src\t# int" %}
7259   opcode(0x01); /* Opcode 01 /r */
7260   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7261   ins_pipe(ialu_mem_reg);
7262 %}
7263 
7264 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7265 %{
7266   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7267   effect(KILL cr);
7268 
7269   ins_cost(125); // XXX
7270   format %{ "addl    $dst, $src\t# int" %}
7271   opcode(0x81); /* Opcode 81 /0 id */
7272   ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7273   ins_pipe(ialu_mem_imm);
7274 %}
7275 
7276 instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
7277 %{
7278   predicate(UseIncDec);
7279   match(Set dst (AddI dst src));
7280   effect(KILL cr);
7281 
7282   format %{ "incl    $dst\t# int" %}
7283   opcode(0xFF, 0x00); // FF /0
7284   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7285   ins_pipe(ialu_reg);
7286 %}
7287 
7288 instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr)
7289 %{
7290   predicate(UseIncDec);
7291   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7292   effect(KILL cr);
7293 
7294   ins_cost(125); // XXX
7295   format %{ "incl    $dst\t# int" %}
7296   opcode(0xFF); /* Opcode FF /0 */
7297   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7298   ins_pipe(ialu_mem_imm);
7299 %}
7300 
7301 // XXX why does that use AddI
7302 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7303 %{
7304   predicate(UseIncDec);
7305   match(Set dst (AddI dst src));
7306   effect(KILL cr);
7307 
7308   format %{ "decl    $dst\t# int" %}
7309   opcode(0xFF, 0x01); // FF /1
7310   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7311   ins_pipe(ialu_reg);
7312 %}
7313 
7314 // XXX why does that use AddI
7315 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7316 %{
7317   predicate(UseIncDec);
7318   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7319   effect(KILL cr);
7320 
7321   ins_cost(125); // XXX
7322   format %{ "decl    $dst\t# int" %}
7323   opcode(0xFF); /* Opcode FF /1 */
7324   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7325   ins_pipe(ialu_mem_imm);
7326 %}
7327 
7328 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7329 %{
7330   match(Set dst (AddI src0 src1));
7331 
7332   ins_cost(110);
7333   format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7334   opcode(0x8D); /* 0x8D /r */
7335   ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7336   ins_pipe(ialu_reg_reg);
7337 %}
7338 
7339 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7340 %{
7341   match(Set dst (AddL dst src));
7342   effect(KILL cr);
7343 
7344   format %{ "addq    $dst, $src\t# long" %}
7345   opcode(0x03);
7346   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7347   ins_pipe(ialu_reg_reg);
7348 %}
7349 
7350 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7351 %{
7352   match(Set dst (AddL dst src));
7353   effect(KILL cr);
7354 
7355   format %{ "addq    $dst, $src\t# long" %}
7356   opcode(0x81, 0x00); /* /0 id */
7357   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7358   ins_pipe( ialu_reg );
7359 %}
7360 
7361 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7362 %{
7363   match(Set dst (AddL dst (LoadL src)));
7364   effect(KILL cr);
7365 
7366   ins_cost(125); // XXX
7367   format %{ "addq    $dst, $src\t# long" %}
7368   opcode(0x03);
7369   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7370   ins_pipe(ialu_reg_mem);
7371 %}
7372 
7373 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7374 %{
7375   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7376   effect(KILL cr);
7377 
7378   ins_cost(150); // XXX
7379   format %{ "addq    $dst, $src\t# long" %}
7380   opcode(0x01); /* Opcode 01 /r */
7381   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7382   ins_pipe(ialu_mem_reg);
7383 %}
7384 
7385 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7386 %{
7387   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7388   effect(KILL cr);
7389 
7390   ins_cost(125); // XXX
7391   format %{ "addq    $dst, $src\t# long" %}
7392   opcode(0x81); /* Opcode 81 /0 id */
7393   ins_encode(REX_mem_wide(dst),
7394              OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7395   ins_pipe(ialu_mem_imm);
7396 %}
7397 
7398 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7399 %{
7400   predicate(UseIncDec);
7401   match(Set dst (AddL dst src));
7402   effect(KILL cr);
7403 
7404   format %{ "incq    $dst\t# long" %}
7405   opcode(0xFF, 0x00); // FF /0
7406   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7407   ins_pipe(ialu_reg);
7408 %}
7409 
7410 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7411 %{
7412   predicate(UseIncDec);
7413   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7414   effect(KILL cr);
7415 
7416   ins_cost(125); // XXX
7417   format %{ "incq    $dst\t# long" %}
7418   opcode(0xFF); /* Opcode FF /0 */
7419   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7420   ins_pipe(ialu_mem_imm);
7421 %}
7422 
7423 // XXX why does that use AddL
7424 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7425 %{
7426   predicate(UseIncDec);
7427   match(Set dst (AddL dst src));
7428   effect(KILL cr);
7429 
7430   format %{ "decq    $dst\t# long" %}
7431   opcode(0xFF, 0x01); // FF /1
7432   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7433   ins_pipe(ialu_reg);
7434 %}
7435 
7436 // XXX why does that use AddL
7437 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7438 %{
7439   predicate(UseIncDec);
7440   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7441   effect(KILL cr);
7442 
7443   ins_cost(125); // XXX
7444   format %{ "decq    $dst\t# long" %}
7445   opcode(0xFF); /* Opcode FF /1 */
7446   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7447   ins_pipe(ialu_mem_imm);
7448 %}
7449 
7450 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7451 %{
7452   match(Set dst (AddL src0 src1));
7453 
7454   ins_cost(110);
7455   format %{ "leaq    $dst, [$src0 + $src1]\t# long" %}
7456   opcode(0x8D); /* 0x8D /r */
7457   ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7458   ins_pipe(ialu_reg_reg);
7459 %}
7460 
7461 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7462 %{
7463   match(Set dst (AddP dst src));
7464   effect(KILL cr);
7465 
7466   format %{ "addq    $dst, $src\t# ptr" %}
7467   opcode(0x03);
7468   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7469   ins_pipe(ialu_reg_reg);
7470 %}
7471 
7472 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7473 %{
7474   match(Set dst (AddP dst src));
7475   effect(KILL cr);
7476 
7477   format %{ "addq    $dst, $src\t# ptr" %}
7478   opcode(0x81, 0x00); /* /0 id */
7479   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7480   ins_pipe( ialu_reg );
7481 %}
7482 
7483 // XXX addP mem ops ????
7484 
7485 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7486 %{
7487   match(Set dst (AddP src0 src1));
7488 
7489   ins_cost(110);
7490   format %{ "leaq    $dst, [$src0 + $src1]\t# ptr" %}
7491   opcode(0x8D); /* 0x8D /r */
7492   ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7493   ins_pipe(ialu_reg_reg);
7494 %}
7495 
7496 instruct checkCastPP(rRegP dst)
7497 %{
7498   match(Set dst (CheckCastPP dst));
7499 
7500   size(0);
7501   format %{ "# checkcastPP of $dst" %}
7502   ins_encode(/* empty encoding */);
7503   ins_pipe(empty);
7504 %}
7505 
7506 instruct castPP(rRegP dst)
7507 %{
7508   match(Set dst (CastPP dst));
7509 
7510   size(0);
7511   format %{ "# castPP of $dst" %}
7512   ins_encode(/* empty encoding */);
7513   ins_pipe(empty);
7514 %}
7515 
7516 instruct castII(rRegI dst)
7517 %{
7518   match(Set dst (CastII dst));
7519 
7520   size(0);
7521   format %{ "# castII of $dst" %}
7522   ins_encode(/* empty encoding */);
7523   ins_cost(0);
7524   ins_pipe(empty);
7525 %}
7526 
7527 // LoadP-locked same as a regular LoadP when used with compare-swap
7528 instruct loadPLocked(rRegP dst, memory mem)
7529 %{
7530   match(Set dst (LoadPLocked mem));
7531 
7532   ins_cost(125); // XXX
7533   format %{ "movq    $dst, $mem\t# ptr locked" %}
7534   opcode(0x8B);
7535   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7536   ins_pipe(ialu_reg_mem); // XXX
7537 %}
7538 
7539 // Conditional-store of the updated heap-top.
7540 // Used during allocation of the shared heap.
7541 // Sets flags (EQ) on success.  Implemented with a CMPXCHG on Intel.
7542 
7543 instruct storePConditional(memory heap_top_ptr,
7544                            rax_RegP oldval, rRegP newval,
7545                            rFlagsReg cr)
7546 %{
7547   predicate(n->as_LoadStore()->barrier_data() == 0);
7548   match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7549 
7550   format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7551             "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7552   opcode(0x0F, 0xB1);
7553   ins_encode(lock_prefix,
7554              REX_reg_mem_wide(newval, heap_top_ptr),
7555              OpcP, OpcS,
7556              reg_mem(newval, heap_top_ptr));
7557   ins_pipe(pipe_cmpxchg);
7558 %}
7559 
7560 // Conditional-store of an int value.
7561 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG.
7562 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7563 %{
7564   match(Set cr (StoreIConditional mem (Binary oldval newval)));
7565   effect(KILL oldval);
7566 
7567   format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7568   opcode(0x0F, 0xB1);
7569   ins_encode(lock_prefix,
7570              REX_reg_mem(newval, mem),
7571              OpcP, OpcS,
7572              reg_mem(newval, mem));
7573   ins_pipe(pipe_cmpxchg);
7574 %}
7575 
7576 // Conditional-store of a long value.
7577 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG.
7578 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7579 %{
7580   match(Set cr (StoreLConditional mem (Binary oldval newval)));
7581   effect(KILL oldval);
7582 
7583   format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7584   opcode(0x0F, 0xB1);
7585   ins_encode(lock_prefix,
7586              REX_reg_mem_wide(newval, mem),
7587              OpcP, OpcS,
7588              reg_mem(newval, mem));
7589   ins_pipe(pipe_cmpxchg);
7590 %}
7591 
7592 
7593 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7594 instruct compareAndSwapP(rRegI res,
7595                          memory mem_ptr,
7596                          rax_RegP oldval, rRegP newval,
7597                          rFlagsReg cr)
7598 %{
7599   predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0);
7600   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7601   match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7602   effect(KILL cr, KILL oldval);
7603 
7604   format %{ "cmpxchgq $mem_ptr,$newval\t# "
7605             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7606             "sete    $res\n\t"
7607             "movzbl  $res, $res" %}
7608   opcode(0x0F, 0xB1);
7609   ins_encode(lock_prefix,
7610              REX_reg_mem_wide(newval, mem_ptr),
7611              OpcP, OpcS,
7612              reg_mem(newval, mem_ptr),
7613              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7614              REX_reg_breg(res, res), // movzbl
7615              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7616   ins_pipe( pipe_cmpxchg );
7617 %}
7618 
7619 instruct compareAndSwapL(rRegI res,
7620                          memory mem_ptr,
7621                          rax_RegL oldval, rRegL newval,
7622                          rFlagsReg cr)
7623 %{
7624   predicate(VM_Version::supports_cx8());
7625   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7626   match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7627   effect(KILL cr, KILL oldval);
7628 
7629   format %{ "cmpxchgq $mem_ptr,$newval\t# "
7630             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7631             "sete    $res\n\t"
7632             "movzbl  $res, $res" %}
7633   opcode(0x0F, 0xB1);
7634   ins_encode(lock_prefix,
7635              REX_reg_mem_wide(newval, mem_ptr),
7636              OpcP, OpcS,
7637              reg_mem(newval, mem_ptr),
7638              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7639              REX_reg_breg(res, res), // movzbl
7640              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7641   ins_pipe( pipe_cmpxchg );
7642 %}
7643 
7644 instruct compareAndSwapI(rRegI res,
7645                          memory mem_ptr,
7646                          rax_RegI oldval, rRegI newval,
7647                          rFlagsReg cr)
7648 %{
7649   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7650   match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7651   effect(KILL cr, KILL oldval);
7652 
7653   format %{ "cmpxchgl $mem_ptr,$newval\t# "
7654             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7655             "sete    $res\n\t"
7656             "movzbl  $res, $res" %}
7657   opcode(0x0F, 0xB1);
7658   ins_encode(lock_prefix,
7659              REX_reg_mem(newval, mem_ptr),
7660              OpcP, OpcS,
7661              reg_mem(newval, mem_ptr),
7662              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7663              REX_reg_breg(res, res), // movzbl
7664              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7665   ins_pipe( pipe_cmpxchg );
7666 %}
7667 
7668 instruct compareAndSwapB(rRegI res,
7669                          memory mem_ptr,
7670                          rax_RegI oldval, rRegI newval,
7671                          rFlagsReg cr)
7672 %{
7673   match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7674   match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7675   effect(KILL cr, KILL oldval);
7676 
7677   format %{ "cmpxchgb $mem_ptr,$newval\t# "
7678             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7679             "sete    $res\n\t"
7680             "movzbl  $res, $res" %}
7681   opcode(0x0F, 0xB0);
7682   ins_encode(lock_prefix,
7683              REX_breg_mem(newval, mem_ptr),
7684              OpcP, OpcS,
7685              reg_mem(newval, mem_ptr),
7686              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7687              REX_reg_breg(res, res), // movzbl
7688              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7689   ins_pipe( pipe_cmpxchg );
7690 %}
7691 
7692 instruct compareAndSwapS(rRegI res,
7693                          memory mem_ptr,
7694                          rax_RegI oldval, rRegI newval,
7695                          rFlagsReg cr)
7696 %{
7697   match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7698   match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7699   effect(KILL cr, KILL oldval);
7700 
7701   format %{ "cmpxchgw $mem_ptr,$newval\t# "
7702             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7703             "sete    $res\n\t"
7704             "movzbl  $res, $res" %}
7705   opcode(0x0F, 0xB1);
7706   ins_encode(lock_prefix,
7707              SizePrefix,
7708              REX_reg_mem(newval, mem_ptr),
7709              OpcP, OpcS,
7710              reg_mem(newval, mem_ptr),
7711              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7712              REX_reg_breg(res, res), // movzbl
7713              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7714   ins_pipe( pipe_cmpxchg );
7715 %}
7716 
7717 instruct compareAndSwapN(rRegI res,
7718                           memory mem_ptr,
7719                           rax_RegN oldval, rRegN newval,
7720                           rFlagsReg cr) %{
7721   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7722   match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7723   effect(KILL cr, KILL oldval);
7724 
7725   format %{ "cmpxchgl $mem_ptr,$newval\t# "
7726             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7727             "sete    $res\n\t"
7728             "movzbl  $res, $res" %}
7729   opcode(0x0F, 0xB1);
7730   ins_encode(lock_prefix,
7731              REX_reg_mem(newval, mem_ptr),
7732              OpcP, OpcS,
7733              reg_mem(newval, mem_ptr),
7734              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7735              REX_reg_breg(res, res), // movzbl
7736              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7737   ins_pipe( pipe_cmpxchg );
7738 %}
7739 
7740 instruct compareAndExchangeB(
7741                          memory mem_ptr,
7742                          rax_RegI oldval, rRegI newval,
7743                          rFlagsReg cr)
7744 %{
7745   match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7746   effect(KILL cr);
7747 
7748   format %{ "cmpxchgb $mem_ptr,$newval\t# "
7749             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
7750   opcode(0x0F, 0xB0);
7751   ins_encode(lock_prefix,
7752              REX_breg_mem(newval, mem_ptr),
7753              OpcP, OpcS,
7754              reg_mem(newval, mem_ptr) // lock cmpxchg
7755              );
7756   ins_pipe( pipe_cmpxchg );
7757 %}
7758 
7759 instruct compareAndExchangeS(
7760                          memory mem_ptr,
7761                          rax_RegI oldval, rRegI newval,
7762                          rFlagsReg cr)
7763 %{
7764   match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7765   effect(KILL cr);
7766 
7767   format %{ "cmpxchgw $mem_ptr,$newval\t# "
7768             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
7769   opcode(0x0F, 0xB1);
7770   ins_encode(lock_prefix,
7771              SizePrefix,
7772              REX_reg_mem(newval, mem_ptr),
7773              OpcP, OpcS,
7774              reg_mem(newval, mem_ptr) // lock cmpxchg
7775              );
7776   ins_pipe( pipe_cmpxchg );
7777 %}
7778 
7779 instruct compareAndExchangeI(
7780                          memory mem_ptr,
7781                          rax_RegI oldval, rRegI newval,
7782                          rFlagsReg cr)
7783 %{
7784   match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7785   effect(KILL cr);
7786 
7787   format %{ "cmpxchgl $mem_ptr,$newval\t# "
7788             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
7789   opcode(0x0F, 0xB1);
7790   ins_encode(lock_prefix,
7791              REX_reg_mem(newval, mem_ptr),
7792              OpcP, OpcS,
7793              reg_mem(newval, mem_ptr) // lock cmpxchg
7794              );
7795   ins_pipe( pipe_cmpxchg );
7796 %}
7797 
7798 instruct compareAndExchangeL(
7799                          memory mem_ptr,
7800                          rax_RegL oldval, rRegL newval,
7801                          rFlagsReg cr)
7802 %{
7803   predicate(VM_Version::supports_cx8());
7804   match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7805   effect(KILL cr);
7806 
7807   format %{ "cmpxchgq $mem_ptr,$newval\t# "
7808             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
7809   opcode(0x0F, 0xB1);
7810   ins_encode(lock_prefix,
7811              REX_reg_mem_wide(newval, mem_ptr),
7812              OpcP, OpcS,
7813              reg_mem(newval, mem_ptr)  // lock cmpxchg
7814             );
7815   ins_pipe( pipe_cmpxchg );
7816 %}
7817 
7818 instruct compareAndExchangeN(
7819                           memory mem_ptr,
7820                           rax_RegN oldval, rRegN newval,
7821                           rFlagsReg cr) %{
7822   match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7823   effect(KILL cr);
7824 
7825   format %{ "cmpxchgl $mem_ptr,$newval\t# "
7826             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7827   opcode(0x0F, 0xB1);
7828   ins_encode(lock_prefix,
7829              REX_reg_mem(newval, mem_ptr),
7830              OpcP, OpcS,
7831              reg_mem(newval, mem_ptr)  // lock cmpxchg
7832           );
7833   ins_pipe( pipe_cmpxchg );
7834 %}
7835 
7836 instruct compareAndExchangeP(
7837                          memory mem_ptr,
7838                          rax_RegP oldval, rRegP newval,
7839                          rFlagsReg cr)
7840 %{
7841   predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0);
7842   match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7843   effect(KILL cr);
7844 
7845   format %{ "cmpxchgq $mem_ptr,$newval\t# "
7846             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7847   opcode(0x0F, 0xB1);
7848   ins_encode(lock_prefix,
7849              REX_reg_mem_wide(newval, mem_ptr),
7850              OpcP, OpcS,
7851              reg_mem(newval, mem_ptr)  // lock cmpxchg
7852           );
7853   ins_pipe( pipe_cmpxchg );
7854 %}
7855 
7856 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7857   predicate(n->as_LoadStore()->result_not_used());
7858   match(Set dummy (GetAndAddB mem add));
7859   effect(KILL cr);
7860   format %{ "ADDB  [$mem],$add" %}
7861   ins_encode %{
7862     __ lock();
7863     __ addb($mem$$Address, $add$$constant);
7864   %}
7865   ins_pipe( pipe_cmpxchg );
7866 %}
7867 
7868 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7869   match(Set newval (GetAndAddB mem newval));
7870   effect(KILL cr);
7871   format %{ "XADDB  [$mem],$newval" %}
7872   ins_encode %{
7873     __ lock();
7874     __ xaddb($mem$$Address, $newval$$Register);
7875   %}
7876   ins_pipe( pipe_cmpxchg );
7877 %}
7878 
7879 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7880   predicate(n->as_LoadStore()->result_not_used());
7881   match(Set dummy (GetAndAddS mem add));
7882   effect(KILL cr);
7883   format %{ "ADDW  [$mem],$add" %}
7884   ins_encode %{
7885     __ lock();
7886     __ addw($mem$$Address, $add$$constant);
7887   %}
7888   ins_pipe( pipe_cmpxchg );
7889 %}
7890 
7891 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
7892   match(Set newval (GetAndAddS mem newval));
7893   effect(KILL cr);
7894   format %{ "XADDW  [$mem],$newval" %}
7895   ins_encode %{
7896     __ lock();
7897     __ xaddw($mem$$Address, $newval$$Register);
7898   %}
7899   ins_pipe( pipe_cmpxchg );
7900 %}
7901 
7902 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7903   predicate(n->as_LoadStore()->result_not_used());
7904   match(Set dummy (GetAndAddI mem add));
7905   effect(KILL cr);
7906   format %{ "ADDL  [$mem],$add" %}
7907   ins_encode %{
7908     __ lock();
7909     __ addl($mem$$Address, $add$$constant);
7910   %}
7911   ins_pipe( pipe_cmpxchg );
7912 %}
7913 
7914 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7915   match(Set newval (GetAndAddI mem newval));
7916   effect(KILL cr);
7917   format %{ "XADDL  [$mem],$newval" %}
7918   ins_encode %{
7919     __ lock();
7920     __ xaddl($mem$$Address, $newval$$Register);
7921   %}
7922   ins_pipe( pipe_cmpxchg );
7923 %}
7924 
7925 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7926   predicate(n->as_LoadStore()->result_not_used());
7927   match(Set dummy (GetAndAddL mem add));
7928   effect(KILL cr);
7929   format %{ "ADDQ  [$mem],$add" %}
7930   ins_encode %{
7931     __ lock();
7932     __ addq($mem$$Address, $add$$constant);
7933   %}
7934   ins_pipe( pipe_cmpxchg );
7935 %}
7936 
7937 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7938   match(Set newval (GetAndAddL mem newval));
7939   effect(KILL cr);
7940   format %{ "XADDQ  [$mem],$newval" %}
7941   ins_encode %{
7942     __ lock();
7943     __ xaddq($mem$$Address, $newval$$Register);
7944   %}
7945   ins_pipe( pipe_cmpxchg );
7946 %}
7947 
7948 instruct xchgB( memory mem, rRegI newval) %{
7949   match(Set newval (GetAndSetB mem newval));
7950   format %{ "XCHGB  $newval,[$mem]" %}
7951   ins_encode %{
7952     __ xchgb($newval$$Register, $mem$$Address);
7953   %}
7954   ins_pipe( pipe_cmpxchg );
7955 %}
7956 
7957 instruct xchgS( memory mem, rRegI newval) %{
7958   match(Set newval (GetAndSetS mem newval));
7959   format %{ "XCHGW  $newval,[$mem]" %}
7960   ins_encode %{
7961     __ xchgw($newval$$Register, $mem$$Address);
7962   %}
7963   ins_pipe( pipe_cmpxchg );
7964 %}
7965 
7966 instruct xchgI( memory mem, rRegI newval) %{
7967   match(Set newval (GetAndSetI mem newval));
7968   format %{ "XCHGL  $newval,[$mem]" %}
7969   ins_encode %{
7970     __ xchgl($newval$$Register, $mem$$Address);
7971   %}
7972   ins_pipe( pipe_cmpxchg );
7973 %}
7974 
7975 instruct xchgL( memory mem, rRegL newval) %{
7976   match(Set newval (GetAndSetL mem newval));
7977   format %{ "XCHGL  $newval,[$mem]" %}
7978   ins_encode %{
7979     __ xchgq($newval$$Register, $mem$$Address);
7980   %}
7981   ins_pipe( pipe_cmpxchg );
7982 %}
7983 
7984 instruct xchgP( memory mem, rRegP newval) %{
7985   match(Set newval (GetAndSetP mem newval));
7986   predicate(n->as_LoadStore()->barrier_data() == 0);
7987   format %{ "XCHGQ  $newval,[$mem]" %}
7988   ins_encode %{
7989     __ xchgq($newval$$Register, $mem$$Address);
7990   %}
7991   ins_pipe( pipe_cmpxchg );
7992 %}
7993 
7994 instruct xchgN( memory mem, rRegN newval) %{
7995   match(Set newval (GetAndSetN mem newval));
7996   format %{ "XCHGL  $newval,$mem]" %}
7997   ins_encode %{
7998     __ xchgl($newval$$Register, $mem$$Address);
7999   %}
8000   ins_pipe( pipe_cmpxchg );
8001 %}
8002 
8003 //----------Abs Instructions-------------------------------------------
8004 
8005 // Integer Absolute Instructions
8006 instruct absI_rReg(rRegI dst, rRegI src, rRegI tmp, rFlagsReg cr)
8007 %{
8008   match(Set dst (AbsI src));
8009   effect(TEMP dst, TEMP tmp, KILL cr);
8010   format %{ "movl $tmp, $src\n\t"
8011             "sarl $tmp, 31\n\t"
8012             "movl $dst, $src\n\t"
8013             "xorl $dst, $tmp\n\t"
8014             "subl $dst, $tmp\n"
8015           %}
8016   ins_encode %{
8017     __ movl($tmp$$Register, $src$$Register);
8018     __ sarl($tmp$$Register, 31);
8019     __ movl($dst$$Register, $src$$Register);
8020     __ xorl($dst$$Register, $tmp$$Register);
8021     __ subl($dst$$Register, $tmp$$Register);
8022   %}
8023 
8024   ins_pipe(ialu_reg_reg);
8025 %}
8026 
8027 // Long Absolute Instructions
8028 instruct absL_rReg(rRegL dst, rRegL src, rRegL tmp, rFlagsReg cr)
8029 %{
8030   match(Set dst (AbsL src));
8031   effect(TEMP dst, TEMP tmp, KILL cr);
8032   format %{ "movq $tmp, $src\n\t"
8033             "sarq $tmp, 63\n\t"
8034             "movq $dst, $src\n\t"
8035             "xorq $dst, $tmp\n\t"
8036             "subq $dst, $tmp\n"
8037           %}
8038   ins_encode %{
8039     __ movq($tmp$$Register, $src$$Register);
8040     __ sarq($tmp$$Register, 63);
8041     __ movq($dst$$Register, $src$$Register);
8042     __ xorq($dst$$Register, $tmp$$Register);
8043     __ subq($dst$$Register, $tmp$$Register);
8044   %}
8045 
8046   ins_pipe(ialu_reg_reg);
8047 %}
8048 
8049 //----------Subtraction Instructions-------------------------------------------
8050 
8051 // Integer Subtraction Instructions
8052 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8053 %{
8054   match(Set dst (SubI dst src));
8055   effect(KILL cr);
8056 
8057   format %{ "subl    $dst, $src\t# int" %}
8058   opcode(0x2B);
8059   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8060   ins_pipe(ialu_reg_reg);
8061 %}
8062 
8063 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8064 %{
8065   match(Set dst (SubI dst src));
8066   effect(KILL cr);
8067 
8068   format %{ "subl    $dst, $src\t# int" %}
8069   opcode(0x81, 0x05);  /* Opcode 81 /5 */
8070   ins_encode(OpcSErm(dst, src), Con8or32(src));
8071   ins_pipe(ialu_reg);
8072 %}
8073 
8074 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8075 %{
8076   match(Set dst (SubI dst (LoadI src)));
8077   effect(KILL cr);
8078 
8079   ins_cost(125);
8080   format %{ "subl    $dst, $src\t# int" %}
8081   opcode(0x2B);
8082   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8083   ins_pipe(ialu_reg_mem);
8084 %}
8085 
8086 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8087 %{
8088   match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8089   effect(KILL cr);
8090 
8091   ins_cost(150);
8092   format %{ "subl    $dst, $src\t# int" %}
8093   opcode(0x29); /* Opcode 29 /r */
8094   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8095   ins_pipe(ialu_mem_reg);
8096 %}
8097 
8098 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8099 %{
8100   match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8101   effect(KILL cr);
8102 
8103   ins_cost(125); // XXX
8104   format %{ "subl    $dst, $src\t# int" %}
8105   opcode(0x81); /* Opcode 81 /5 id */
8106   ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8107   ins_pipe(ialu_mem_imm);
8108 %}
8109 
8110 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8111 %{
8112   match(Set dst (SubL dst src));
8113   effect(KILL cr);
8114 
8115   format %{ "subq    $dst, $src\t# long" %}
8116   opcode(0x2B);
8117   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8118   ins_pipe(ialu_reg_reg);
8119 %}
8120 
8121 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8122 %{
8123   match(Set dst (SubL dst src));
8124   effect(KILL cr);
8125 
8126   format %{ "subq    $dst, $src\t# long" %}
8127   opcode(0x81, 0x05);  /* Opcode 81 /5 */
8128   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8129   ins_pipe(ialu_reg);
8130 %}
8131 
8132 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8133 %{
8134   match(Set dst (SubL dst (LoadL src)));
8135   effect(KILL cr);
8136 
8137   ins_cost(125);
8138   format %{ "subq    $dst, $src\t# long" %}
8139   opcode(0x2B);
8140   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8141   ins_pipe(ialu_reg_mem);
8142 %}
8143 
8144 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8145 %{
8146   match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8147   effect(KILL cr);
8148 
8149   ins_cost(150);
8150   format %{ "subq    $dst, $src\t# long" %}
8151   opcode(0x29); /* Opcode 29 /r */
8152   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8153   ins_pipe(ialu_mem_reg);
8154 %}
8155 
8156 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8157 %{
8158   match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8159   effect(KILL cr);
8160 
8161   ins_cost(125); // XXX
8162   format %{ "subq    $dst, $src\t# long" %}
8163   opcode(0x81); /* Opcode 81 /5 id */
8164   ins_encode(REX_mem_wide(dst),
8165              OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8166   ins_pipe(ialu_mem_imm);
8167 %}
8168 
8169 // Subtract from a pointer
8170 // XXX hmpf???
8171 instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
8172 %{
8173   match(Set dst (AddP dst (SubI zero src)));
8174   effect(KILL cr);
8175 
8176   format %{ "subq    $dst, $src\t# ptr - int" %}
8177   opcode(0x2B);
8178   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8179   ins_pipe(ialu_reg_reg);
8180 %}
8181 
8182 instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr)
8183 %{
8184   match(Set dst (SubI zero dst));
8185   effect(KILL cr);
8186 
8187   format %{ "negl    $dst\t# int" %}
8188   opcode(0xF7, 0x03);  // Opcode F7 /3
8189   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8190   ins_pipe(ialu_reg);
8191 %}
8192 
8193 instruct negI_rReg_2(rRegI dst, rFlagsReg cr)
8194 %{
8195   match(Set dst (NegI dst));
8196   effect(KILL cr);
8197 
8198   format %{ "negl    $dst\t# int" %}
8199   ins_encode %{
8200     __ negl($dst$$Register);
8201   %}
8202   ins_pipe(ialu_reg);
8203 %}
8204 
8205 instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr)
8206 %{
8207   match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8208   effect(KILL cr);
8209 
8210   format %{ "negl    $dst\t# int" %}
8211   opcode(0xF7, 0x03);  // Opcode F7 /3
8212   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8213   ins_pipe(ialu_reg);
8214 %}
8215 
8216 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8217 %{
8218   match(Set dst (SubL zero dst));
8219   effect(KILL cr);
8220 
8221   format %{ "negq    $dst\t# long" %}
8222   opcode(0xF7, 0x03);  // Opcode F7 /3
8223   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8224   ins_pipe(ialu_reg);
8225 %}
8226 
8227 instruct negL_rReg_2(rRegL dst, rFlagsReg cr)
8228 %{
8229   match(Set dst (NegL dst));
8230   effect(KILL cr);
8231 
8232   format %{ "negq    $dst\t# int" %}
8233   ins_encode %{
8234     __ negq($dst$$Register);
8235   %}
8236   ins_pipe(ialu_reg);
8237 %}
8238 
8239 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8240 %{
8241   match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8242   effect(KILL cr);
8243 
8244   format %{ "negq    $dst\t# long" %}
8245   opcode(0xF7, 0x03);  // Opcode F7 /3
8246   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8247   ins_pipe(ialu_reg);
8248 %}
8249 
8250 //----------Multiplication/Division Instructions-------------------------------
8251 // Integer Multiplication Instructions
8252 // Multiply Register
8253 
8254 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8255 %{
8256   match(Set dst (MulI dst src));
8257   effect(KILL cr);
8258 
8259   ins_cost(300);
8260   format %{ "imull   $dst, $src\t# int" %}
8261   opcode(0x0F, 0xAF);
8262   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8263   ins_pipe(ialu_reg_reg_alu0);
8264 %}
8265 
8266 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8267 %{
8268   match(Set dst (MulI src imm));
8269   effect(KILL cr);
8270 
8271   ins_cost(300);
8272   format %{ "imull   $dst, $src, $imm\t# int" %}
8273   opcode(0x69); /* 69 /r id */
8274   ins_encode(REX_reg_reg(dst, src),
8275              OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8276   ins_pipe(ialu_reg_reg_alu0);
8277 %}
8278 
8279 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8280 %{
8281   match(Set dst (MulI dst (LoadI src)));
8282   effect(KILL cr);
8283 
8284   ins_cost(350);
8285   format %{ "imull   $dst, $src\t# int" %}
8286   opcode(0x0F, 0xAF);
8287   ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8288   ins_pipe(ialu_reg_mem_alu0);
8289 %}
8290 
8291 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8292 %{
8293   match(Set dst (MulI (LoadI src) imm));
8294   effect(KILL cr);
8295 
8296   ins_cost(300);
8297   format %{ "imull   $dst, $src, $imm\t# int" %}
8298   opcode(0x69); /* 69 /r id */
8299   ins_encode(REX_reg_mem(dst, src),
8300              OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8301   ins_pipe(ialu_reg_mem_alu0);
8302 %}
8303 
8304 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
8305 %{
8306   match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
8307   effect(KILL cr, KILL src2);
8308 
8309   expand %{ mulI_rReg(dst, src1, cr);
8310            mulI_rReg(src2, src3, cr);
8311            addI_rReg(dst, src2, cr); %}
8312 %}
8313 
8314 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8315 %{
8316   match(Set dst (MulL dst src));
8317   effect(KILL cr);
8318 
8319   ins_cost(300);
8320   format %{ "imulq   $dst, $src\t# long" %}
8321   opcode(0x0F, 0xAF);
8322   ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8323   ins_pipe(ialu_reg_reg_alu0);
8324 %}
8325 
8326 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8327 %{
8328   match(Set dst (MulL src imm));
8329   effect(KILL cr);
8330 
8331   ins_cost(300);
8332   format %{ "imulq   $dst, $src, $imm\t# long" %}
8333   opcode(0x69); /* 69 /r id */
8334   ins_encode(REX_reg_reg_wide(dst, src),
8335              OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8336   ins_pipe(ialu_reg_reg_alu0);
8337 %}
8338 
8339 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8340 %{
8341   match(Set dst (MulL dst (LoadL src)));
8342   effect(KILL cr);
8343 
8344   ins_cost(350);
8345   format %{ "imulq   $dst, $src\t# long" %}
8346   opcode(0x0F, 0xAF);
8347   ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8348   ins_pipe(ialu_reg_mem_alu0);
8349 %}
8350 
8351 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8352 %{
8353   match(Set dst (MulL (LoadL src) imm));
8354   effect(KILL cr);
8355 
8356   ins_cost(300);
8357   format %{ "imulq   $dst, $src, $imm\t# long" %}
8358   opcode(0x69); /* 69 /r id */
8359   ins_encode(REX_reg_mem_wide(dst, src),
8360              OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8361   ins_pipe(ialu_reg_mem_alu0);
8362 %}
8363 
8364 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8365 %{
8366   match(Set dst (MulHiL src rax));
8367   effect(USE_KILL rax, KILL cr);
8368 
8369   ins_cost(300);
8370   format %{ "imulq   RDX:RAX, RAX, $src\t# mulhi" %}
8371   opcode(0xF7, 0x5); /* Opcode F7 /5 */
8372   ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8373   ins_pipe(ialu_reg_reg_alu0);
8374 %}
8375 
8376 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8377                    rFlagsReg cr)
8378 %{
8379   match(Set rax (DivI rax div));
8380   effect(KILL rdx, KILL cr);
8381 
8382   ins_cost(30*100+10*100); // XXX
8383   format %{ "cmpl    rax, 0x80000000\t# idiv\n\t"
8384             "jne,s   normal\n\t"
8385             "xorl    rdx, rdx\n\t"
8386             "cmpl    $div, -1\n\t"
8387             "je,s    done\n"
8388     "normal: cdql\n\t"
8389             "idivl   $div\n"
8390     "done:"        %}
8391   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8392   ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8393   ins_pipe(ialu_reg_reg_alu0);
8394 %}
8395 
8396 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8397                    rFlagsReg cr)
8398 %{
8399   match(Set rax (DivL rax div));
8400   effect(KILL rdx, KILL cr);
8401 
8402   ins_cost(30*100+10*100); // XXX
8403   format %{ "movq    rdx, 0x8000000000000000\t# ldiv\n\t"
8404             "cmpq    rax, rdx\n\t"
8405             "jne,s   normal\n\t"
8406             "xorl    rdx, rdx\n\t"
8407             "cmpq    $div, -1\n\t"
8408             "je,s    done\n"
8409     "normal: cdqq\n\t"
8410             "idivq   $div\n"
8411     "done:"        %}
8412   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8413   ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8414   ins_pipe(ialu_reg_reg_alu0);
8415 %}
8416 
8417 // Integer DIVMOD with Register, both quotient and mod results
8418 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8419                              rFlagsReg cr)
8420 %{
8421   match(DivModI rax div);
8422   effect(KILL cr);
8423 
8424   ins_cost(30*100+10*100); // XXX
8425   format %{ "cmpl    rax, 0x80000000\t# idiv\n\t"
8426             "jne,s   normal\n\t"
8427             "xorl    rdx, rdx\n\t"
8428             "cmpl    $div, -1\n\t"
8429             "je,s    done\n"
8430     "normal: cdql\n\t"
8431             "idivl   $div\n"
8432     "done:"        %}
8433   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8434   ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8435   ins_pipe(pipe_slow);
8436 %}
8437 
8438 // Long DIVMOD with Register, both quotient and mod results
8439 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8440                              rFlagsReg cr)
8441 %{
8442   match(DivModL rax div);
8443   effect(KILL cr);
8444 
8445   ins_cost(30*100+10*100); // XXX
8446   format %{ "movq    rdx, 0x8000000000000000\t# ldiv\n\t"
8447             "cmpq    rax, rdx\n\t"
8448             "jne,s   normal\n\t"
8449             "xorl    rdx, rdx\n\t"
8450             "cmpq    $div, -1\n\t"
8451             "je,s    done\n"
8452     "normal: cdqq\n\t"
8453             "idivq   $div\n"
8454     "done:"        %}
8455   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8456   ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8457   ins_pipe(pipe_slow);
8458 %}
8459 
8460 //----------- DivL-By-Constant-Expansions--------------------------------------
8461 // DivI cases are handled by the compiler
8462 
8463 // Magic constant, reciprocal of 10
8464 instruct loadConL_0x6666666666666667(rRegL dst)
8465 %{
8466   effect(DEF dst);
8467 
8468   format %{ "movq    $dst, #0x666666666666667\t# Used in div-by-10" %}
8469   ins_encode(load_immL(dst, 0x6666666666666667));
8470   ins_pipe(ialu_reg);
8471 %}
8472 
8473 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8474 %{
8475   effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8476 
8477   format %{ "imulq   rdx:rax, rax, $src\t# Used in div-by-10" %}
8478   opcode(0xF7, 0x5); /* Opcode F7 /5 */
8479   ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8480   ins_pipe(ialu_reg_reg_alu0);
8481 %}
8482 
8483 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8484 %{
8485   effect(USE_DEF dst, KILL cr);
8486 
8487   format %{ "sarq    $dst, #63\t# Used in div-by-10" %}
8488   opcode(0xC1, 0x7); /* C1 /7 ib */
8489   ins_encode(reg_opc_imm_wide(dst, 0x3F));
8490   ins_pipe(ialu_reg);
8491 %}
8492 
8493 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8494 %{
8495   effect(USE_DEF dst, KILL cr);
8496 
8497   format %{ "sarq    $dst, #2\t# Used in div-by-10" %}
8498   opcode(0xC1, 0x7); /* C1 /7 ib */
8499   ins_encode(reg_opc_imm_wide(dst, 0x2));
8500   ins_pipe(ialu_reg);
8501 %}
8502 
8503 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8504 %{
8505   match(Set dst (DivL src div));
8506 
8507   ins_cost((5+8)*100);
8508   expand %{
8509     rax_RegL rax;                     // Killed temp
8510     rFlagsReg cr;                     // Killed
8511     loadConL_0x6666666666666667(rax); // movq  rax, 0x6666666666666667
8512     mul_hi(dst, src, rax, cr);        // mulq  rdx:rax <= rax * $src
8513     sarL_rReg_63(src, cr);            // sarq  src, 63
8514     sarL_rReg_2(dst, cr);             // sarq  rdx, 2
8515     subL_rReg(dst, src, cr);          // subl  rdx, src
8516   %}
8517 %}
8518 
8519 //-----------------------------------------------------------------------------
8520 
8521 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8522                    rFlagsReg cr)
8523 %{
8524   match(Set rdx (ModI rax div));
8525   effect(KILL rax, KILL cr);
8526 
8527   ins_cost(300); // XXX
8528   format %{ "cmpl    rax, 0x80000000\t# irem\n\t"
8529             "jne,s   normal\n\t"
8530             "xorl    rdx, rdx\n\t"
8531             "cmpl    $div, -1\n\t"
8532             "je,s    done\n"
8533     "normal: cdql\n\t"
8534             "idivl   $div\n"
8535     "done:"        %}
8536   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8537   ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8538   ins_pipe(ialu_reg_reg_alu0);
8539 %}
8540 
8541 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8542                    rFlagsReg cr)
8543 %{
8544   match(Set rdx (ModL rax div));
8545   effect(KILL rax, KILL cr);
8546 
8547   ins_cost(300); // XXX
8548   format %{ "movq    rdx, 0x8000000000000000\t# lrem\n\t"
8549             "cmpq    rax, rdx\n\t"
8550             "jne,s   normal\n\t"
8551             "xorl    rdx, rdx\n\t"
8552             "cmpq    $div, -1\n\t"
8553             "je,s    done\n"
8554     "normal: cdqq\n\t"
8555             "idivq   $div\n"
8556     "done:"        %}
8557   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8558   ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8559   ins_pipe(ialu_reg_reg_alu0);
8560 %}
8561 
8562 // Integer Shift Instructions
8563 // Shift Left by one
8564 instruct salI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8565 %{
8566   match(Set dst (LShiftI dst shift));
8567   effect(KILL cr);
8568 
8569   format %{ "sall    $dst, $shift" %}
8570   opcode(0xD1, 0x4); /* D1 /4 */
8571   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8572   ins_pipe(ialu_reg);
8573 %}
8574 
8575 // Shift Left by one
8576 instruct salI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8577 %{
8578   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8579   effect(KILL cr);
8580 
8581   format %{ "sall    $dst, $shift\t" %}
8582   opcode(0xD1, 0x4); /* D1 /4 */
8583   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8584   ins_pipe(ialu_mem_imm);
8585 %}
8586 
8587 // Shift Left by 8-bit immediate
8588 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8589 %{
8590   match(Set dst (LShiftI dst shift));
8591   effect(KILL cr);
8592 
8593   format %{ "sall    $dst, $shift" %}
8594   opcode(0xC1, 0x4); /* C1 /4 ib */
8595   ins_encode(reg_opc_imm(dst, shift));
8596   ins_pipe(ialu_reg);
8597 %}
8598 
8599 // Shift Left by 8-bit immediate
8600 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8601 %{
8602   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8603   effect(KILL cr);
8604 
8605   format %{ "sall    $dst, $shift" %}
8606   opcode(0xC1, 0x4); /* C1 /4 ib */
8607   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8608   ins_pipe(ialu_mem_imm);
8609 %}
8610 
8611 // Shift Left by variable
8612 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8613 %{
8614   match(Set dst (LShiftI dst shift));
8615   effect(KILL cr);
8616 
8617   format %{ "sall    $dst, $shift" %}
8618   opcode(0xD3, 0x4); /* D3 /4 */
8619   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8620   ins_pipe(ialu_reg_reg);
8621 %}
8622 
8623 // Shift Left by variable
8624 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8625 %{
8626   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8627   effect(KILL cr);
8628 
8629   format %{ "sall    $dst, $shift" %}
8630   opcode(0xD3, 0x4); /* D3 /4 */
8631   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8632   ins_pipe(ialu_mem_reg);
8633 %}
8634 
8635 // Arithmetic shift right by one
8636 instruct sarI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8637 %{
8638   match(Set dst (RShiftI dst shift));
8639   effect(KILL cr);
8640 
8641   format %{ "sarl    $dst, $shift" %}
8642   opcode(0xD1, 0x7); /* D1 /7 */
8643   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8644   ins_pipe(ialu_reg);
8645 %}
8646 
8647 // Arithmetic shift right by one
8648 instruct sarI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8649 %{
8650   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8651   effect(KILL cr);
8652 
8653   format %{ "sarl    $dst, $shift" %}
8654   opcode(0xD1, 0x7); /* D1 /7 */
8655   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8656   ins_pipe(ialu_mem_imm);
8657 %}
8658 
8659 // Arithmetic Shift Right by 8-bit immediate
8660 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8661 %{
8662   match(Set dst (RShiftI dst shift));
8663   effect(KILL cr);
8664 
8665   format %{ "sarl    $dst, $shift" %}
8666   opcode(0xC1, 0x7); /* C1 /7 ib */
8667   ins_encode(reg_opc_imm(dst, shift));
8668   ins_pipe(ialu_mem_imm);
8669 %}
8670 
8671 // Arithmetic Shift Right by 8-bit immediate
8672 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8673 %{
8674   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8675   effect(KILL cr);
8676 
8677   format %{ "sarl    $dst, $shift" %}
8678   opcode(0xC1, 0x7); /* C1 /7 ib */
8679   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8680   ins_pipe(ialu_mem_imm);
8681 %}
8682 
8683 // Arithmetic Shift Right by variable
8684 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8685 %{
8686   match(Set dst (RShiftI dst shift));
8687   effect(KILL cr);
8688 
8689   format %{ "sarl    $dst, $shift" %}
8690   opcode(0xD3, 0x7); /* D3 /7 */
8691   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8692   ins_pipe(ialu_reg_reg);
8693 %}
8694 
8695 // Arithmetic Shift Right by variable
8696 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8697 %{
8698   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8699   effect(KILL cr);
8700 
8701   format %{ "sarl    $dst, $shift" %}
8702   opcode(0xD3, 0x7); /* D3 /7 */
8703   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8704   ins_pipe(ialu_mem_reg);
8705 %}
8706 
8707 // Logical shift right by one
8708 instruct shrI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8709 %{
8710   match(Set dst (URShiftI dst shift));
8711   effect(KILL cr);
8712 
8713   format %{ "shrl    $dst, $shift" %}
8714   opcode(0xD1, 0x5); /* D1 /5 */
8715   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8716   ins_pipe(ialu_reg);
8717 %}
8718 
8719 // Logical shift right by one
8720 instruct shrI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8721 %{
8722   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8723   effect(KILL cr);
8724 
8725   format %{ "shrl    $dst, $shift" %}
8726   opcode(0xD1, 0x5); /* D1 /5 */
8727   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8728   ins_pipe(ialu_mem_imm);
8729 %}
8730 
8731 // Logical Shift Right by 8-bit immediate
8732 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8733 %{
8734   match(Set dst (URShiftI dst shift));
8735   effect(KILL cr);
8736 
8737   format %{ "shrl    $dst, $shift" %}
8738   opcode(0xC1, 0x5); /* C1 /5 ib */
8739   ins_encode(reg_opc_imm(dst, shift));
8740   ins_pipe(ialu_reg);
8741 %}
8742 
8743 // Logical Shift Right by 8-bit immediate
8744 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8745 %{
8746   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8747   effect(KILL cr);
8748 
8749   format %{ "shrl    $dst, $shift" %}
8750   opcode(0xC1, 0x5); /* C1 /5 ib */
8751   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8752   ins_pipe(ialu_mem_imm);
8753 %}
8754 
8755 // Logical Shift Right by variable
8756 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8757 %{
8758   match(Set dst (URShiftI dst shift));
8759   effect(KILL cr);
8760 
8761   format %{ "shrl    $dst, $shift" %}
8762   opcode(0xD3, 0x5); /* D3 /5 */
8763   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8764   ins_pipe(ialu_reg_reg);
8765 %}
8766 
8767 // Logical Shift Right by variable
8768 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8769 %{
8770   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8771   effect(KILL cr);
8772 
8773   format %{ "shrl    $dst, $shift" %}
8774   opcode(0xD3, 0x5); /* D3 /5 */
8775   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8776   ins_pipe(ialu_mem_reg);
8777 %}
8778 
8779 // Long Shift Instructions
8780 // Shift Left by one
8781 instruct salL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
8782 %{
8783   match(Set dst (LShiftL dst shift));
8784   effect(KILL cr);
8785 
8786   format %{ "salq    $dst, $shift" %}
8787   opcode(0xD1, 0x4); /* D1 /4 */
8788   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8789   ins_pipe(ialu_reg);
8790 %}
8791 
8792 // Shift Left by one
8793 instruct salL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8794 %{
8795   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8796   effect(KILL cr);
8797 
8798   format %{ "salq    $dst, $shift" %}
8799   opcode(0xD1, 0x4); /* D1 /4 */
8800   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8801   ins_pipe(ialu_mem_imm);
8802 %}
8803 
8804 // Shift Left by 8-bit immediate
8805 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8806 %{
8807   match(Set dst (LShiftL dst shift));
8808   effect(KILL cr);
8809 
8810   format %{ "salq    $dst, $shift" %}
8811   opcode(0xC1, 0x4); /* C1 /4 ib */
8812   ins_encode(reg_opc_imm_wide(dst, shift));
8813   ins_pipe(ialu_reg);
8814 %}
8815 
8816 // Shift Left by 8-bit immediate
8817 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8818 %{
8819   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8820   effect(KILL cr);
8821 
8822   format %{ "salq    $dst, $shift" %}
8823   opcode(0xC1, 0x4); /* C1 /4 ib */
8824   ins_encode(REX_mem_wide(dst), OpcP,
8825              RM_opc_mem(secondary, dst), Con8or32(shift));
8826   ins_pipe(ialu_mem_imm);
8827 %}
8828 
8829 // Shift Left by variable
8830 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8831 %{
8832   match(Set dst (LShiftL dst shift));
8833   effect(KILL cr);
8834 
8835   format %{ "salq    $dst, $shift" %}
8836   opcode(0xD3, 0x4); /* D3 /4 */
8837   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8838   ins_pipe(ialu_reg_reg);
8839 %}
8840 
8841 // Shift Left by variable
8842 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8843 %{
8844   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8845   effect(KILL cr);
8846 
8847   format %{ "salq    $dst, $shift" %}
8848   opcode(0xD3, 0x4); /* D3 /4 */
8849   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8850   ins_pipe(ialu_mem_reg);
8851 %}
8852 
8853 // Arithmetic shift right by one
8854 instruct sarL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
8855 %{
8856   match(Set dst (RShiftL dst shift));
8857   effect(KILL cr);
8858 
8859   format %{ "sarq    $dst, $shift" %}
8860   opcode(0xD1, 0x7); /* D1 /7 */
8861   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8862   ins_pipe(ialu_reg);
8863 %}
8864 
8865 // Arithmetic shift right by one
8866 instruct sarL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8867 %{
8868   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8869   effect(KILL cr);
8870 
8871   format %{ "sarq    $dst, $shift" %}
8872   opcode(0xD1, 0x7); /* D1 /7 */
8873   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8874   ins_pipe(ialu_mem_imm);
8875 %}
8876 
8877 // Arithmetic Shift Right by 8-bit immediate
8878 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8879 %{
8880   match(Set dst (RShiftL dst shift));
8881   effect(KILL cr);
8882 
8883   format %{ "sarq    $dst, $shift" %}
8884   opcode(0xC1, 0x7); /* C1 /7 ib */
8885   ins_encode(reg_opc_imm_wide(dst, shift));
8886   ins_pipe(ialu_mem_imm);
8887 %}
8888 
8889 // Arithmetic Shift Right by 8-bit immediate
8890 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8891 %{
8892   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8893   effect(KILL cr);
8894 
8895   format %{ "sarq    $dst, $shift" %}
8896   opcode(0xC1, 0x7); /* C1 /7 ib */
8897   ins_encode(REX_mem_wide(dst), OpcP,
8898              RM_opc_mem(secondary, dst), Con8or32(shift));
8899   ins_pipe(ialu_mem_imm);
8900 %}
8901 
8902 // Arithmetic Shift Right by variable
8903 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8904 %{
8905   match(Set dst (RShiftL dst shift));
8906   effect(KILL cr);
8907 
8908   format %{ "sarq    $dst, $shift" %}
8909   opcode(0xD3, 0x7); /* D3 /7 */
8910   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8911   ins_pipe(ialu_reg_reg);
8912 %}
8913 
8914 // Arithmetic Shift Right by variable
8915 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8916 %{
8917   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8918   effect(KILL cr);
8919 
8920   format %{ "sarq    $dst, $shift" %}
8921   opcode(0xD3, 0x7); /* D3 /7 */
8922   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8923   ins_pipe(ialu_mem_reg);
8924 %}
8925 
8926 // Logical shift right by one
8927 instruct shrL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
8928 %{
8929   match(Set dst (URShiftL dst shift));
8930   effect(KILL cr);
8931 
8932   format %{ "shrq    $dst, $shift" %}
8933   opcode(0xD1, 0x5); /* D1 /5 */
8934   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8935   ins_pipe(ialu_reg);
8936 %}
8937 
8938 // Logical shift right by one
8939 instruct shrL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8940 %{
8941   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8942   effect(KILL cr);
8943 
8944   format %{ "shrq    $dst, $shift" %}
8945   opcode(0xD1, 0x5); /* D1 /5 */
8946   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8947   ins_pipe(ialu_mem_imm);
8948 %}
8949 
8950 // Logical Shift Right by 8-bit immediate
8951 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8952 %{
8953   match(Set dst (URShiftL dst shift));
8954   effect(KILL cr);
8955 
8956   format %{ "shrq    $dst, $shift" %}
8957   opcode(0xC1, 0x5); /* C1 /5 ib */
8958   ins_encode(reg_opc_imm_wide(dst, shift));
8959   ins_pipe(ialu_reg);
8960 %}
8961 
8962 
8963 // Logical Shift Right by 8-bit immediate
8964 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8965 %{
8966   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8967   effect(KILL cr);
8968 
8969   format %{ "shrq    $dst, $shift" %}
8970   opcode(0xC1, 0x5); /* C1 /5 ib */
8971   ins_encode(REX_mem_wide(dst), OpcP,
8972              RM_opc_mem(secondary, dst), Con8or32(shift));
8973   ins_pipe(ialu_mem_imm);
8974 %}
8975 
8976 // Logical Shift Right by variable
8977 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8978 %{
8979   match(Set dst (URShiftL dst shift));
8980   effect(KILL cr);
8981 
8982   format %{ "shrq    $dst, $shift" %}
8983   opcode(0xD3, 0x5); /* D3 /5 */
8984   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8985   ins_pipe(ialu_reg_reg);
8986 %}
8987 
8988 // Logical Shift Right by variable
8989 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8990 %{
8991   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8992   effect(KILL cr);
8993 
8994   format %{ "shrq    $dst, $shift" %}
8995   opcode(0xD3, 0x5); /* D3 /5 */
8996   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8997   ins_pipe(ialu_mem_reg);
8998 %}
8999 
9000 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9001 // This idiom is used by the compiler for the i2b bytecode.
9002 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9003 %{
9004   match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9005 
9006   format %{ "movsbl  $dst, $src\t# i2b" %}
9007   opcode(0x0F, 0xBE);
9008   ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9009   ins_pipe(ialu_reg_reg);
9010 %}
9011 
9012 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9013 // This idiom is used by the compiler the i2s bytecode.
9014 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9015 %{
9016   match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9017 
9018   format %{ "movswl  $dst, $src\t# i2s" %}
9019   opcode(0x0F, 0xBF);
9020   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9021   ins_pipe(ialu_reg_reg);
9022 %}
9023 
9024 // ROL/ROR instructions
9025 
9026 // ROL expand
9027 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
9028   effect(KILL cr, USE_DEF dst);
9029 
9030   format %{ "roll    $dst" %}
9031   opcode(0xD1, 0x0); /* Opcode  D1 /0 */
9032   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9033   ins_pipe(ialu_reg);
9034 %}
9035 
9036 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
9037   effect(USE_DEF dst, USE shift, KILL cr);
9038 
9039   format %{ "roll    $dst, $shift" %}
9040   opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9041   ins_encode( reg_opc_imm(dst, shift) );
9042   ins_pipe(ialu_reg);
9043 %}
9044 
9045 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9046 %{
9047   effect(USE_DEF dst, USE shift, KILL cr);
9048 
9049   format %{ "roll    $dst, $shift" %}
9050   opcode(0xD3, 0x0); /* Opcode D3 /0 */
9051   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9052   ins_pipe(ialu_reg_reg);
9053 %}
9054 // end of ROL expand
9055 
9056 // Rotate Left by one
9057 instruct rolI_rReg_i1(rRegI dst, immI_1 lshift, immI_M1 rshift, rFlagsReg cr)
9058 %{
9059   match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9060 
9061   expand %{
9062     rolI_rReg_imm1(dst, cr);
9063   %}
9064 %}
9065 
9066 // Rotate Left by 8-bit immediate
9067 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9068 %{
9069   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9070   match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9071 
9072   expand %{
9073     rolI_rReg_imm8(dst, lshift, cr);
9074   %}
9075 %}
9076 
9077 // Rotate Left by variable
9078 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
9079 %{
9080   match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9081 
9082   expand %{
9083     rolI_rReg_CL(dst, shift, cr);
9084   %}
9085 %}
9086 
9087 // Rotate Left by variable
9088 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9089 %{
9090   match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9091 
9092   expand %{
9093     rolI_rReg_CL(dst, shift, cr);
9094   %}
9095 %}
9096 
9097 // ROR expand
9098 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9099 %{
9100   effect(USE_DEF dst, KILL cr);
9101 
9102   format %{ "rorl    $dst" %}
9103   opcode(0xD1, 0x1); /* D1 /1 */
9104   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9105   ins_pipe(ialu_reg);
9106 %}
9107 
9108 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
9109 %{
9110   effect(USE_DEF dst, USE shift, KILL cr);
9111 
9112   format %{ "rorl    $dst, $shift" %}
9113   opcode(0xC1, 0x1); /* C1 /1 ib */
9114   ins_encode(reg_opc_imm(dst, shift));
9115   ins_pipe(ialu_reg);
9116 %}
9117 
9118 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9119 %{
9120   effect(USE_DEF dst, USE shift, KILL cr);
9121 
9122   format %{ "rorl    $dst, $shift" %}
9123   opcode(0xD3, 0x1); /* D3 /1 */
9124   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9125   ins_pipe(ialu_reg_reg);
9126 %}
9127 // end of ROR expand
9128 
9129 // Rotate Right by one
9130 instruct rorI_rReg_i1(rRegI dst, immI_1 rshift, immI_M1 lshift, rFlagsReg cr)
9131 %{
9132   match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9133 
9134   expand %{
9135     rorI_rReg_imm1(dst, cr);
9136   %}
9137 %}
9138 
9139 // Rotate Right by 8-bit immediate
9140 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9141 %{
9142   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9143   match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9144 
9145   expand %{
9146     rorI_rReg_imm8(dst, rshift, cr);
9147   %}
9148 %}
9149 
9150 // Rotate Right by variable
9151 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
9152 %{
9153   match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9154 
9155   expand %{
9156     rorI_rReg_CL(dst, shift, cr);
9157   %}
9158 %}
9159 
9160 // Rotate Right by variable
9161 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9162 %{
9163   match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9164 
9165   expand %{
9166     rorI_rReg_CL(dst, shift, cr);
9167   %}
9168 %}
9169 
9170 // for long rotate
9171 // ROL expand
9172 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9173   effect(USE_DEF dst, KILL cr);
9174 
9175   format %{ "rolq    $dst" %}
9176   opcode(0xD1, 0x0); /* Opcode  D1 /0 */
9177   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9178   ins_pipe(ialu_reg);
9179 %}
9180 
9181 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9182   effect(USE_DEF dst, USE shift, KILL cr);
9183 
9184   format %{ "rolq    $dst, $shift" %}
9185   opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9186   ins_encode( reg_opc_imm_wide(dst, shift) );
9187   ins_pipe(ialu_reg);
9188 %}
9189 
9190 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9191 %{
9192   effect(USE_DEF dst, USE shift, KILL cr);
9193 
9194   format %{ "rolq    $dst, $shift" %}
9195   opcode(0xD3, 0x0); /* Opcode D3 /0 */
9196   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9197   ins_pipe(ialu_reg_reg);
9198 %}
9199 // end of ROL expand
9200 
9201 // Rotate Left by one
9202 instruct rolL_rReg_i1(rRegL dst, immI_1 lshift, immI_M1 rshift, rFlagsReg cr)
9203 %{
9204   match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9205 
9206   expand %{
9207     rolL_rReg_imm1(dst, cr);
9208   %}
9209 %}
9210 
9211 // Rotate Left by 8-bit immediate
9212 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9213 %{
9214   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9215   match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9216 
9217   expand %{
9218     rolL_rReg_imm8(dst, lshift, cr);
9219   %}
9220 %}
9221 
9222 // Rotate Left by variable
9223 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
9224 %{
9225   match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9226 
9227   expand %{
9228     rolL_rReg_CL(dst, shift, cr);
9229   %}
9230 %}
9231 
9232 // Rotate Left by variable
9233 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9234 %{
9235   match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9236 
9237   expand %{
9238     rolL_rReg_CL(dst, shift, cr);
9239   %}
9240 %}
9241 
9242 // ROR expand
9243 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9244 %{
9245   effect(USE_DEF dst, KILL cr);
9246 
9247   format %{ "rorq    $dst" %}
9248   opcode(0xD1, 0x1); /* D1 /1 */
9249   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9250   ins_pipe(ialu_reg);
9251 %}
9252 
9253 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9254 %{
9255   effect(USE_DEF dst, USE shift, KILL cr);
9256 
9257   format %{ "rorq    $dst, $shift" %}
9258   opcode(0xC1, 0x1); /* C1 /1 ib */
9259   ins_encode(reg_opc_imm_wide(dst, shift));
9260   ins_pipe(ialu_reg);
9261 %}
9262 
9263 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9264 %{
9265   effect(USE_DEF dst, USE shift, KILL cr);
9266 
9267   format %{ "rorq    $dst, $shift" %}
9268   opcode(0xD3, 0x1); /* D3 /1 */
9269   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9270   ins_pipe(ialu_reg_reg);
9271 %}
9272 // end of ROR expand
9273 
9274 // Rotate Right by one
9275 instruct rorL_rReg_i1(rRegL dst, immI_1 rshift, immI_M1 lshift, rFlagsReg cr)
9276 %{
9277   match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9278 
9279   expand %{
9280     rorL_rReg_imm1(dst, cr);
9281   %}
9282 %}
9283 
9284 // Rotate Right by 8-bit immediate
9285 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9286 %{
9287   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9288   match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9289 
9290   expand %{
9291     rorL_rReg_imm8(dst, rshift, cr);
9292   %}
9293 %}
9294 
9295 // Rotate Right by variable
9296 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI_0 zero, rFlagsReg cr)
9297 %{
9298   match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9299 
9300   expand %{
9301     rorL_rReg_CL(dst, shift, cr);
9302   %}
9303 %}
9304 
9305 // Rotate Right by variable
9306 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9307 %{
9308   match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9309 
9310   expand %{
9311     rorL_rReg_CL(dst, shift, cr);
9312   %}
9313 %}
9314 
9315 // Logical Instructions
9316 
9317 // Integer Logical Instructions
9318 
9319 // And Instructions
9320 // And Register with Register
9321 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9322 %{
9323   match(Set dst (AndI dst src));
9324   effect(KILL cr);
9325 
9326   format %{ "andl    $dst, $src\t# int" %}
9327   opcode(0x23);
9328   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9329   ins_pipe(ialu_reg_reg);
9330 %}
9331 
9332 // And Register with Immediate 255
9333 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9334 %{
9335   match(Set dst (AndI dst src));
9336 
9337   format %{ "movzbl  $dst, $dst\t# int & 0xFF" %}
9338   opcode(0x0F, 0xB6);
9339   ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9340   ins_pipe(ialu_reg);
9341 %}
9342 
9343 // And Register with Immediate 255 and promote to long
9344 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9345 %{
9346   match(Set dst (ConvI2L (AndI src mask)));
9347 
9348   format %{ "movzbl  $dst, $src\t# int & 0xFF -> long" %}
9349   opcode(0x0F, 0xB6);
9350   ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9351   ins_pipe(ialu_reg);
9352 %}
9353 
9354 // And Register with Immediate 65535
9355 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9356 %{
9357   match(Set dst (AndI dst src));
9358 
9359   format %{ "movzwl  $dst, $dst\t# int & 0xFFFF" %}
9360   opcode(0x0F, 0xB7);
9361   ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9362   ins_pipe(ialu_reg);
9363 %}
9364 
9365 // And Register with Immediate 65535 and promote to long
9366 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9367 %{
9368   match(Set dst (ConvI2L (AndI src mask)));
9369 
9370   format %{ "movzwl  $dst, $src\t# int & 0xFFFF -> long" %}
9371   opcode(0x0F, 0xB7);
9372   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9373   ins_pipe(ialu_reg);
9374 %}
9375 
9376 // And Register with Immediate
9377 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9378 %{
9379   match(Set dst (AndI dst src));
9380   effect(KILL cr);
9381 
9382   format %{ "andl    $dst, $src\t# int" %}
9383   opcode(0x81, 0x04); /* Opcode 81 /4 */
9384   ins_encode(OpcSErm(dst, src), Con8or32(src));
9385   ins_pipe(ialu_reg);
9386 %}
9387 
9388 // And Register with Memory
9389 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9390 %{
9391   match(Set dst (AndI dst (LoadI src)));
9392   effect(KILL cr);
9393 
9394   ins_cost(125);
9395   format %{ "andl    $dst, $src\t# int" %}
9396   opcode(0x23);
9397   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9398   ins_pipe(ialu_reg_mem);
9399 %}
9400 
9401 // And Memory with Register
9402 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9403 %{
9404   match(Set dst (StoreB dst (AndI (LoadB dst) src)));
9405   effect(KILL cr);
9406 
9407   ins_cost(150);
9408   format %{ "andb    $dst, $src\t# byte" %}
9409   opcode(0x20);
9410   ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9411   ins_pipe(ialu_mem_reg);
9412 %}
9413 
9414 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9415 %{
9416   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9417   effect(KILL cr);
9418 
9419   ins_cost(150);
9420   format %{ "andl    $dst, $src\t# int" %}
9421   opcode(0x21); /* Opcode 21 /r */
9422   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9423   ins_pipe(ialu_mem_reg);
9424 %}
9425 
9426 // And Memory with Immediate
9427 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9428 %{
9429   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9430   effect(KILL cr);
9431 
9432   ins_cost(125);
9433   format %{ "andl    $dst, $src\t# int" %}
9434   opcode(0x81, 0x4); /* Opcode 81 /4 id */
9435   ins_encode(REX_mem(dst), OpcSE(src),
9436              RM_opc_mem(secondary, dst), Con8or32(src));
9437   ins_pipe(ialu_mem_imm);
9438 %}
9439 
9440 // BMI1 instructions
9441 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9442   match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9443   predicate(UseBMI1Instructions);
9444   effect(KILL cr);
9445 
9446   ins_cost(125);
9447   format %{ "andnl  $dst, $src1, $src2" %}
9448 
9449   ins_encode %{
9450     __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9451   %}
9452   ins_pipe(ialu_reg_mem);
9453 %}
9454 
9455 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9456   match(Set dst (AndI (XorI src1 minus_1) src2));
9457   predicate(UseBMI1Instructions);
9458   effect(KILL cr);
9459 
9460   format %{ "andnl  $dst, $src1, $src2" %}
9461 
9462   ins_encode %{
9463     __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9464   %}
9465   ins_pipe(ialu_reg);
9466 %}
9467 
9468 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
9469   match(Set dst (AndI (SubI imm_zero src) src));
9470   predicate(UseBMI1Instructions);
9471   effect(KILL cr);
9472 
9473   format %{ "blsil  $dst, $src" %}
9474 
9475   ins_encode %{
9476     __ blsil($dst$$Register, $src$$Register);
9477   %}
9478   ins_pipe(ialu_reg);
9479 %}
9480 
9481 instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
9482   match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9483   predicate(UseBMI1Instructions);
9484   effect(KILL cr);
9485 
9486   ins_cost(125);
9487   format %{ "blsil  $dst, $src" %}
9488 
9489   ins_encode %{
9490     __ blsil($dst$$Register, $src$$Address);
9491   %}
9492   ins_pipe(ialu_reg_mem);
9493 %}
9494 
9495 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9496 %{
9497   match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9498   predicate(UseBMI1Instructions);
9499   effect(KILL cr);
9500 
9501   ins_cost(125);
9502   format %{ "blsmskl $dst, $src" %}
9503 
9504   ins_encode %{
9505     __ blsmskl($dst$$Register, $src$$Address);
9506   %}
9507   ins_pipe(ialu_reg_mem);
9508 %}
9509 
9510 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9511 %{
9512   match(Set dst (XorI (AddI src minus_1) src));
9513   predicate(UseBMI1Instructions);
9514   effect(KILL cr);
9515 
9516   format %{ "blsmskl $dst, $src" %}
9517 
9518   ins_encode %{
9519     __ blsmskl($dst$$Register, $src$$Register);
9520   %}
9521 
9522   ins_pipe(ialu_reg);
9523 %}
9524 
9525 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9526 %{
9527   match(Set dst (AndI (AddI src minus_1) src) );
9528   predicate(UseBMI1Instructions);
9529   effect(KILL cr);
9530 
9531   format %{ "blsrl  $dst, $src" %}
9532 
9533   ins_encode %{
9534     __ blsrl($dst$$Register, $src$$Register);
9535   %}
9536 
9537   ins_pipe(ialu_reg_mem);
9538 %}
9539 
9540 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9541 %{
9542   match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9543   predicate(UseBMI1Instructions);
9544   effect(KILL cr);
9545 
9546   ins_cost(125);
9547   format %{ "blsrl  $dst, $src" %}
9548 
9549   ins_encode %{
9550     __ blsrl($dst$$Register, $src$$Address);
9551   %}
9552 
9553   ins_pipe(ialu_reg);
9554 %}
9555 
9556 // Or Instructions
9557 // Or Register with Register
9558 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9559 %{
9560   match(Set dst (OrI dst src));
9561   effect(KILL cr);
9562 
9563   format %{ "orl     $dst, $src\t# int" %}
9564   opcode(0x0B);
9565   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9566   ins_pipe(ialu_reg_reg);
9567 %}
9568 
9569 // Or Register with Immediate
9570 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9571 %{
9572   match(Set dst (OrI dst src));
9573   effect(KILL cr);
9574 
9575   format %{ "orl     $dst, $src\t# int" %}
9576   opcode(0x81, 0x01); /* Opcode 81 /1 id */
9577   ins_encode(OpcSErm(dst, src), Con8or32(src));
9578   ins_pipe(ialu_reg);
9579 %}
9580 
9581 // Or Register with Memory
9582 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9583 %{
9584   match(Set dst (OrI dst (LoadI src)));
9585   effect(KILL cr);
9586 
9587   ins_cost(125);
9588   format %{ "orl     $dst, $src\t# int" %}
9589   opcode(0x0B);
9590   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9591   ins_pipe(ialu_reg_mem);
9592 %}
9593 
9594 // Or Memory with Register
9595 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9596 %{
9597   match(Set dst (StoreB dst (OrI (LoadB dst) src)));
9598   effect(KILL cr);
9599 
9600   ins_cost(150);
9601   format %{ "orb    $dst, $src\t# byte" %}
9602   opcode(0x08);
9603   ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9604   ins_pipe(ialu_mem_reg);
9605 %}
9606 
9607 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9608 %{
9609   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9610   effect(KILL cr);
9611 
9612   ins_cost(150);
9613   format %{ "orl     $dst, $src\t# int" %}
9614   opcode(0x09); /* Opcode 09 /r */
9615   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9616   ins_pipe(ialu_mem_reg);
9617 %}
9618 
9619 // Or Memory with Immediate
9620 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9621 %{
9622   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9623   effect(KILL cr);
9624 
9625   ins_cost(125);
9626   format %{ "orl     $dst, $src\t# int" %}
9627   opcode(0x81, 0x1); /* Opcode 81 /1 id */
9628   ins_encode(REX_mem(dst), OpcSE(src),
9629              RM_opc_mem(secondary, dst), Con8or32(src));
9630   ins_pipe(ialu_mem_imm);
9631 %}
9632 
9633 // Xor Instructions
9634 // Xor Register with Register
9635 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9636 %{
9637   match(Set dst (XorI dst src));
9638   effect(KILL cr);
9639 
9640   format %{ "xorl    $dst, $src\t# int" %}
9641   opcode(0x33);
9642   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9643   ins_pipe(ialu_reg_reg);
9644 %}
9645 
9646 // Xor Register with Immediate -1
9647 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9648   match(Set dst (XorI dst imm));
9649 
9650   format %{ "not    $dst" %}
9651   ins_encode %{
9652      __ notl($dst$$Register);
9653   %}
9654   ins_pipe(ialu_reg);
9655 %}
9656 
9657 // Xor Register with Immediate
9658 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9659 %{
9660   match(Set dst (XorI dst src));
9661   effect(KILL cr);
9662 
9663   format %{ "xorl    $dst, $src\t# int" %}
9664   opcode(0x81, 0x06); /* Opcode 81 /6 id */
9665   ins_encode(OpcSErm(dst, src), Con8or32(src));
9666   ins_pipe(ialu_reg);
9667 %}
9668 
9669 // Xor Register with Memory
9670 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9671 %{
9672   match(Set dst (XorI dst (LoadI src)));
9673   effect(KILL cr);
9674 
9675   ins_cost(125);
9676   format %{ "xorl    $dst, $src\t# int" %}
9677   opcode(0x33);
9678   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9679   ins_pipe(ialu_reg_mem);
9680 %}
9681 
9682 // Xor Memory with Register
9683 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9684 %{
9685   match(Set dst (StoreB dst (XorI (LoadB dst) src)));
9686   effect(KILL cr);
9687 
9688   ins_cost(150);
9689   format %{ "xorb    $dst, $src\t# byte" %}
9690   opcode(0x30);
9691   ins_encode(REX_breg_mem(src, dst), OpcP, reg_mem(src, dst));
9692   ins_pipe(ialu_mem_reg);
9693 %}
9694 
9695 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9696 %{
9697   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9698   effect(KILL cr);
9699 
9700   ins_cost(150);
9701   format %{ "xorl    $dst, $src\t# int" %}
9702   opcode(0x31); /* Opcode 31 /r */
9703   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9704   ins_pipe(ialu_mem_reg);
9705 %}
9706 
9707 // Xor Memory with Immediate
9708 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9709 %{
9710   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9711   effect(KILL cr);
9712 
9713   ins_cost(125);
9714   format %{ "xorl    $dst, $src\t# int" %}
9715   opcode(0x81, 0x6); /* Opcode 81 /6 id */
9716   ins_encode(REX_mem(dst), OpcSE(src),
9717              RM_opc_mem(secondary, dst), Con8or32(src));
9718   ins_pipe(ialu_mem_imm);
9719 %}
9720 
9721 
9722 // Long Logical Instructions
9723 
9724 // And Instructions
9725 // And Register with Register
9726 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9727 %{
9728   match(Set dst (AndL dst src));
9729   effect(KILL cr);
9730 
9731   format %{ "andq    $dst, $src\t# long" %}
9732   opcode(0x23);
9733   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9734   ins_pipe(ialu_reg_reg);
9735 %}
9736 
9737 // And Register with Immediate 255
9738 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9739 %{
9740   match(Set dst (AndL dst src));
9741 
9742   format %{ "movzbq  $dst, $dst\t# long & 0xFF" %}
9743   opcode(0x0F, 0xB6);
9744   ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9745   ins_pipe(ialu_reg);
9746 %}
9747 
9748 // And Register with Immediate 65535
9749 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9750 %{
9751   match(Set dst (AndL dst src));
9752 
9753   format %{ "movzwq  $dst, $dst\t# long & 0xFFFF" %}
9754   opcode(0x0F, 0xB7);
9755   ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9756   ins_pipe(ialu_reg);
9757 %}
9758 
9759 // And Register with Immediate
9760 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9761 %{
9762   match(Set dst (AndL dst src));
9763   effect(KILL cr);
9764 
9765   format %{ "andq    $dst, $src\t# long" %}
9766   opcode(0x81, 0x04); /* Opcode 81 /4 */
9767   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9768   ins_pipe(ialu_reg);
9769 %}
9770 
9771 // And Register with Memory
9772 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9773 %{
9774   match(Set dst (AndL dst (LoadL src)));
9775   effect(KILL cr);
9776 
9777   ins_cost(125);
9778   format %{ "andq    $dst, $src\t# long" %}
9779   opcode(0x23);
9780   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9781   ins_pipe(ialu_reg_mem);
9782 %}
9783 
9784 // And Memory with Register
9785 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9786 %{
9787   match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9788   effect(KILL cr);
9789 
9790   ins_cost(150);
9791   format %{ "andq    $dst, $src\t# long" %}
9792   opcode(0x21); /* Opcode 21 /r */
9793   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9794   ins_pipe(ialu_mem_reg);
9795 %}
9796 
9797 // And Memory with Immediate
9798 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9799 %{
9800   match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9801   effect(KILL cr);
9802 
9803   ins_cost(125);
9804   format %{ "andq    $dst, $src\t# long" %}
9805   opcode(0x81, 0x4); /* Opcode 81 /4 id */
9806   ins_encode(REX_mem_wide(dst), OpcSE(src),
9807              RM_opc_mem(secondary, dst), Con8or32(src));
9808   ins_pipe(ialu_mem_imm);
9809 %}
9810 
9811 instruct btrL_mem_imm(memory dst, immL_NotPow2 con, rFlagsReg cr)
9812 %{
9813   // con should be a pure 64-bit immediate given that not(con) is a power of 2
9814   // because AND/OR works well enough for 8/32-bit values.
9815   predicate(log2_long(~n->in(3)->in(2)->get_long()) > 30);
9816 
9817   match(Set dst (StoreL dst (AndL (LoadL dst) con)));
9818   effect(KILL cr);
9819 
9820   ins_cost(125);
9821   format %{ "btrq    $dst, log2(not($con))\t# long" %}
9822   ins_encode %{
9823     __ btrq($dst$$Address, log2_long(~$con$$constant));
9824   %}
9825   ins_pipe(ialu_mem_imm);
9826 %}
9827 
9828 // BMI1 instructions
9829 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9830   match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9831   predicate(UseBMI1Instructions);
9832   effect(KILL cr);
9833 
9834   ins_cost(125);
9835   format %{ "andnq  $dst, $src1, $src2" %}
9836 
9837   ins_encode %{
9838     __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9839   %}
9840   ins_pipe(ialu_reg_mem);
9841 %}
9842 
9843 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9844   match(Set dst (AndL (XorL src1 minus_1) src2));
9845   predicate(UseBMI1Instructions);
9846   effect(KILL cr);
9847 
9848   format %{ "andnq  $dst, $src1, $src2" %}
9849 
9850   ins_encode %{
9851   __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9852   %}
9853   ins_pipe(ialu_reg_mem);
9854 %}
9855 
9856 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9857   match(Set dst (AndL (SubL imm_zero src) src));
9858   predicate(UseBMI1Instructions);
9859   effect(KILL cr);
9860 
9861   format %{ "blsiq  $dst, $src" %}
9862 
9863   ins_encode %{
9864     __ blsiq($dst$$Register, $src$$Register);
9865   %}
9866   ins_pipe(ialu_reg);
9867 %}
9868 
9869 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9870   match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9871   predicate(UseBMI1Instructions);
9872   effect(KILL cr);
9873 
9874   ins_cost(125);
9875   format %{ "blsiq  $dst, $src" %}
9876 
9877   ins_encode %{
9878     __ blsiq($dst$$Register, $src$$Address);
9879   %}
9880   ins_pipe(ialu_reg_mem);
9881 %}
9882 
9883 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9884 %{
9885   match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9886   predicate(UseBMI1Instructions);
9887   effect(KILL cr);
9888 
9889   ins_cost(125);
9890   format %{ "blsmskq $dst, $src" %}
9891 
9892   ins_encode %{
9893     __ blsmskq($dst$$Register, $src$$Address);
9894   %}
9895   ins_pipe(ialu_reg_mem);
9896 %}
9897 
9898 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9899 %{
9900   match(Set dst (XorL (AddL src minus_1) src));
9901   predicate(UseBMI1Instructions);
9902   effect(KILL cr);
9903 
9904   format %{ "blsmskq $dst, $src" %}
9905 
9906   ins_encode %{
9907     __ blsmskq($dst$$Register, $src$$Register);
9908   %}
9909 
9910   ins_pipe(ialu_reg);
9911 %}
9912 
9913 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9914 %{
9915   match(Set dst (AndL (AddL src minus_1) src) );
9916   predicate(UseBMI1Instructions);
9917   effect(KILL cr);
9918 
9919   format %{ "blsrq  $dst, $src" %}
9920 
9921   ins_encode %{
9922     __ blsrq($dst$$Register, $src$$Register);
9923   %}
9924 
9925   ins_pipe(ialu_reg);
9926 %}
9927 
9928 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9929 %{
9930   match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9931   predicate(UseBMI1Instructions);
9932   effect(KILL cr);
9933 
9934   ins_cost(125);
9935   format %{ "blsrq  $dst, $src" %}
9936 
9937   ins_encode %{
9938     __ blsrq($dst$$Register, $src$$Address);
9939   %}
9940 
9941   ins_pipe(ialu_reg);
9942 %}
9943 
9944 // Or Instructions
9945 // Or Register with Register
9946 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9947 %{
9948   match(Set dst (OrL dst src));
9949   effect(KILL cr);
9950 
9951   format %{ "orq     $dst, $src\t# long" %}
9952   opcode(0x0B);
9953   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9954   ins_pipe(ialu_reg_reg);
9955 %}
9956 
9957 // Use any_RegP to match R15 (TLS register) without spilling.
9958 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9959   match(Set dst (OrL dst (CastP2X src)));
9960   effect(KILL cr);
9961 
9962   format %{ "orq     $dst, $src\t# long" %}
9963   opcode(0x0B);
9964   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9965   ins_pipe(ialu_reg_reg);
9966 %}
9967 
9968 
9969 // Or Register with Immediate
9970 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9971 %{
9972   match(Set dst (OrL dst src));
9973   effect(KILL cr);
9974 
9975   format %{ "orq     $dst, $src\t# long" %}
9976   opcode(0x81, 0x01); /* Opcode 81 /1 id */
9977   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9978   ins_pipe(ialu_reg);
9979 %}
9980 
9981 // Or Register with Memory
9982 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9983 %{
9984   match(Set dst (OrL dst (LoadL src)));
9985   effect(KILL cr);
9986 
9987   ins_cost(125);
9988   format %{ "orq     $dst, $src\t# long" %}
9989   opcode(0x0B);
9990   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9991   ins_pipe(ialu_reg_mem);
9992 %}
9993 
9994 // Or Memory with Register
9995 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9996 %{
9997   match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9998   effect(KILL cr);
9999 
10000   ins_cost(150);
10001   format %{ "orq     $dst, $src\t# long" %}
10002   opcode(0x09); /* Opcode 09 /r */
10003   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10004   ins_pipe(ialu_mem_reg);
10005 %}
10006 
10007 // Or Memory with Immediate
10008 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10009 %{
10010   match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10011   effect(KILL cr);
10012 
10013   ins_cost(125);
10014   format %{ "orq     $dst, $src\t# long" %}
10015   opcode(0x81, 0x1); /* Opcode 81 /1 id */
10016   ins_encode(REX_mem_wide(dst), OpcSE(src),
10017              RM_opc_mem(secondary, dst), Con8or32(src));
10018   ins_pipe(ialu_mem_imm);
10019 %}
10020 
10021 instruct btsL_mem_imm(memory dst, immL_Pow2 con, rFlagsReg cr)
10022 %{
10023   // con should be a pure 64-bit power of 2 immediate
10024   // because AND/OR works well enough for 8/32-bit values.
10025   predicate(log2_long(n->in(3)->in(2)->get_long()) > 31);
10026 
10027   match(Set dst (StoreL dst (OrL (LoadL dst) con)));
10028   effect(KILL cr);
10029 
10030   ins_cost(125);
10031   format %{ "btsq    $dst, log2($con)\t# long" %}
10032   ins_encode %{
10033     __ btsq($dst$$Address, log2_long((julong)$con$$constant));
10034   %}
10035   ins_pipe(ialu_mem_imm);
10036 %}
10037 
10038 // Xor Instructions
10039 // Xor Register with Register
10040 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10041 %{
10042   match(Set dst (XorL dst src));
10043   effect(KILL cr);
10044 
10045   format %{ "xorq    $dst, $src\t# long" %}
10046   opcode(0x33);
10047   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10048   ins_pipe(ialu_reg_reg);
10049 %}
10050 
10051 // Xor Register with Immediate -1
10052 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10053   match(Set dst (XorL dst imm));
10054 
10055   format %{ "notq   $dst" %}
10056   ins_encode %{
10057      __ notq($dst$$Register);
10058   %}
10059   ins_pipe(ialu_reg);
10060 %}
10061 
10062 // Xor Register with Immediate
10063 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10064 %{
10065   match(Set dst (XorL dst src));
10066   effect(KILL cr);
10067 
10068   format %{ "xorq    $dst, $src\t# long" %}
10069   opcode(0x81, 0x06); /* Opcode 81 /6 id */
10070   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10071   ins_pipe(ialu_reg);
10072 %}
10073 
10074 // Xor Register with Memory
10075 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10076 %{
10077   match(Set dst (XorL dst (LoadL src)));
10078   effect(KILL cr);
10079 
10080   ins_cost(125);
10081   format %{ "xorq    $dst, $src\t# long" %}
10082   opcode(0x33);
10083   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10084   ins_pipe(ialu_reg_mem);
10085 %}
10086 
10087 // Xor Memory with Register
10088 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10089 %{
10090   match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10091   effect(KILL cr);
10092 
10093   ins_cost(150);
10094   format %{ "xorq    $dst, $src\t# long" %}
10095   opcode(0x31); /* Opcode 31 /r */
10096   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10097   ins_pipe(ialu_mem_reg);
10098 %}
10099 
10100 // Xor Memory with Immediate
10101 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10102 %{
10103   match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10104   effect(KILL cr);
10105 
10106   ins_cost(125);
10107   format %{ "xorq    $dst, $src\t# long" %}
10108   opcode(0x81, 0x6); /* Opcode 81 /6 id */
10109   ins_encode(REX_mem_wide(dst), OpcSE(src),
10110              RM_opc_mem(secondary, dst), Con8or32(src));
10111   ins_pipe(ialu_mem_imm);
10112 %}
10113 
10114 // Convert Int to Boolean
10115 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10116 %{
10117   match(Set dst (Conv2B src));
10118   effect(KILL cr);
10119 
10120   format %{ "testl   $src, $src\t# ci2b\n\t"
10121             "setnz   $dst\n\t"
10122             "movzbl  $dst, $dst" %}
10123   ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
10124              setNZ_reg(dst),
10125              REX_reg_breg(dst, dst), // movzbl
10126              Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10127   ins_pipe(pipe_slow); // XXX
10128 %}
10129 
10130 // Convert Pointer to Boolean
10131 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10132 %{
10133   match(Set dst (Conv2B src));
10134   effect(KILL cr);
10135 
10136   format %{ "testq   $src, $src\t# cp2b\n\t"
10137             "setnz   $dst\n\t"
10138             "movzbl  $dst, $dst" %}
10139   ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
10140              setNZ_reg(dst),
10141              REX_reg_breg(dst, dst), // movzbl
10142              Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10143   ins_pipe(pipe_slow); // XXX
10144 %}
10145 
10146 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10147 %{
10148   match(Set dst (CmpLTMask p q));
10149   effect(KILL cr);
10150 
10151   ins_cost(400);
10152   format %{ "cmpl    $p, $q\t# cmpLTMask\n\t"
10153             "setlt   $dst\n\t"
10154             "movzbl  $dst, $dst\n\t"
10155             "negl    $dst" %}
10156   ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10157              setLT_reg(dst),
10158              REX_reg_breg(dst, dst), // movzbl
10159              Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10160              neg_reg(dst));
10161   ins_pipe(pipe_slow);
10162 %}
10163 
10164 instruct cmpLTMask0(rRegI dst, immI_0 zero, rFlagsReg cr)
10165 %{
10166   match(Set dst (CmpLTMask dst zero));
10167   effect(KILL cr);
10168 
10169   ins_cost(100);
10170   format %{ "sarl    $dst, #31\t# cmpLTMask0" %}
10171   ins_encode %{
10172   __ sarl($dst$$Register, 31);
10173   %}
10174   ins_pipe(ialu_reg);
10175 %}
10176 
10177 /* Better to save a register than avoid a branch */
10178 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10179 %{
10180   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10181   effect(KILL cr);
10182   ins_cost(300);
10183   format %{ "subl    $p,$q\t# cadd_cmpLTMask\n\t"
10184             "jge     done\n\t"
10185             "addl    $p,$y\n"
10186             "done:   " %}
10187   ins_encode %{
10188     Register Rp = $p$$Register;
10189     Register Rq = $q$$Register;
10190     Register Ry = $y$$Register;
10191     Label done;
10192     __ subl(Rp, Rq);
10193     __ jccb(Assembler::greaterEqual, done);
10194     __ addl(Rp, Ry);
10195     __ bind(done);
10196   %}
10197   ins_pipe(pipe_cmplt);
10198 %}
10199 
10200 /* Better to save a register than avoid a branch */
10201 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10202 %{
10203   match(Set y (AndI (CmpLTMask p q) y));
10204   effect(KILL cr);
10205 
10206   ins_cost(300);
10207 
10208   format %{ "cmpl    $p, $q\t# and_cmpLTMask\n\t"
10209             "jlt     done\n\t"
10210             "xorl    $y, $y\n"
10211             "done:   " %}
10212   ins_encode %{
10213     Register Rp = $p$$Register;
10214     Register Rq = $q$$Register;
10215     Register Ry = $y$$Register;
10216     Label done;
10217     __ cmpl(Rp, Rq);
10218     __ jccb(Assembler::less, done);
10219     __ xorl(Ry, Ry);
10220     __ bind(done);
10221   %}
10222   ins_pipe(pipe_cmplt);
10223 %}
10224 
10225 
10226 //---------- FP Instructions------------------------------------------------
10227 
10228 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10229 %{
10230   match(Set cr (CmpF src1 src2));
10231 
10232   ins_cost(145);
10233   format %{ "ucomiss $src1, $src2\n\t"
10234             "jnp,s   exit\n\t"
10235             "pushfq\t# saw NaN, set CF\n\t"
10236             "andq    [rsp], #0xffffff2b\n\t"
10237             "popfq\n"
10238     "exit:" %}
10239   ins_encode %{
10240     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10241     emit_cmpfp_fixup(_masm);
10242   %}
10243   ins_pipe(pipe_slow);
10244 %}
10245 
10246 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10247   match(Set cr (CmpF src1 src2));
10248 
10249   ins_cost(100);
10250   format %{ "ucomiss $src1, $src2" %}
10251   ins_encode %{
10252     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10253   %}
10254   ins_pipe(pipe_slow);
10255 %}
10256 
10257 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10258 %{
10259   match(Set cr (CmpF src1 (LoadF src2)));
10260 
10261   ins_cost(145);
10262   format %{ "ucomiss $src1, $src2\n\t"
10263             "jnp,s   exit\n\t"
10264             "pushfq\t# saw NaN, set CF\n\t"
10265             "andq    [rsp], #0xffffff2b\n\t"
10266             "popfq\n"
10267     "exit:" %}
10268   ins_encode %{
10269     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10270     emit_cmpfp_fixup(_masm);
10271   %}
10272   ins_pipe(pipe_slow);
10273 %}
10274 
10275 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10276   match(Set cr (CmpF src1 (LoadF src2)));
10277 
10278   ins_cost(100);
10279   format %{ "ucomiss $src1, $src2" %}
10280   ins_encode %{
10281     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10282   %}
10283   ins_pipe(pipe_slow);
10284 %}
10285 
10286 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10287   match(Set cr (CmpF src con));
10288 
10289   ins_cost(145);
10290   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10291             "jnp,s   exit\n\t"
10292             "pushfq\t# saw NaN, set CF\n\t"
10293             "andq    [rsp], #0xffffff2b\n\t"
10294             "popfq\n"
10295     "exit:" %}
10296   ins_encode %{
10297     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10298     emit_cmpfp_fixup(_masm);
10299   %}
10300   ins_pipe(pipe_slow);
10301 %}
10302 
10303 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10304   match(Set cr (CmpF src con));
10305   ins_cost(100);
10306   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10307   ins_encode %{
10308     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10309   %}
10310   ins_pipe(pipe_slow);
10311 %}
10312 
10313 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10314 %{
10315   match(Set cr (CmpD src1 src2));
10316 
10317   ins_cost(145);
10318   format %{ "ucomisd $src1, $src2\n\t"
10319             "jnp,s   exit\n\t"
10320             "pushfq\t# saw NaN, set CF\n\t"
10321             "andq    [rsp], #0xffffff2b\n\t"
10322             "popfq\n"
10323     "exit:" %}
10324   ins_encode %{
10325     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10326     emit_cmpfp_fixup(_masm);
10327   %}
10328   ins_pipe(pipe_slow);
10329 %}
10330 
10331 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10332   match(Set cr (CmpD src1 src2));
10333 
10334   ins_cost(100);
10335   format %{ "ucomisd $src1, $src2 test" %}
10336   ins_encode %{
10337     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10338   %}
10339   ins_pipe(pipe_slow);
10340 %}
10341 
10342 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10343 %{
10344   match(Set cr (CmpD src1 (LoadD src2)));
10345 
10346   ins_cost(145);
10347   format %{ "ucomisd $src1, $src2\n\t"
10348             "jnp,s   exit\n\t"
10349             "pushfq\t# saw NaN, set CF\n\t"
10350             "andq    [rsp], #0xffffff2b\n\t"
10351             "popfq\n"
10352     "exit:" %}
10353   ins_encode %{
10354     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10355     emit_cmpfp_fixup(_masm);
10356   %}
10357   ins_pipe(pipe_slow);
10358 %}
10359 
10360 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10361   match(Set cr (CmpD src1 (LoadD src2)));
10362 
10363   ins_cost(100);
10364   format %{ "ucomisd $src1, $src2" %}
10365   ins_encode %{
10366     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10367   %}
10368   ins_pipe(pipe_slow);
10369 %}
10370 
10371 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10372   match(Set cr (CmpD src con));
10373 
10374   ins_cost(145);
10375   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10376             "jnp,s   exit\n\t"
10377             "pushfq\t# saw NaN, set CF\n\t"
10378             "andq    [rsp], #0xffffff2b\n\t"
10379             "popfq\n"
10380     "exit:" %}
10381   ins_encode %{
10382     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10383     emit_cmpfp_fixup(_masm);
10384   %}
10385   ins_pipe(pipe_slow);
10386 %}
10387 
10388 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10389   match(Set cr (CmpD src con));
10390   ins_cost(100);
10391   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10392   ins_encode %{
10393     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10394   %}
10395   ins_pipe(pipe_slow);
10396 %}
10397 
10398 // Compare into -1,0,1
10399 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10400 %{
10401   match(Set dst (CmpF3 src1 src2));
10402   effect(KILL cr);
10403 
10404   ins_cost(275);
10405   format %{ "ucomiss $src1, $src2\n\t"
10406             "movl    $dst, #-1\n\t"
10407             "jp,s    done\n\t"
10408             "jb,s    done\n\t"
10409             "setne   $dst\n\t"
10410             "movzbl  $dst, $dst\n"
10411     "done:" %}
10412   ins_encode %{
10413     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10414     emit_cmpfp3(_masm, $dst$$Register);
10415   %}
10416   ins_pipe(pipe_slow);
10417 %}
10418 
10419 // Compare into -1,0,1
10420 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10421 %{
10422   match(Set dst (CmpF3 src1 (LoadF src2)));
10423   effect(KILL cr);
10424 
10425   ins_cost(275);
10426   format %{ "ucomiss $src1, $src2\n\t"
10427             "movl    $dst, #-1\n\t"
10428             "jp,s    done\n\t"
10429             "jb,s    done\n\t"
10430             "setne   $dst\n\t"
10431             "movzbl  $dst, $dst\n"
10432     "done:" %}
10433   ins_encode %{
10434     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10435     emit_cmpfp3(_masm, $dst$$Register);
10436   %}
10437   ins_pipe(pipe_slow);
10438 %}
10439 
10440 // Compare into -1,0,1
10441 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10442   match(Set dst (CmpF3 src con));
10443   effect(KILL cr);
10444 
10445   ins_cost(275);
10446   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10447             "movl    $dst, #-1\n\t"
10448             "jp,s    done\n\t"
10449             "jb,s    done\n\t"
10450             "setne   $dst\n\t"
10451             "movzbl  $dst, $dst\n"
10452     "done:" %}
10453   ins_encode %{
10454     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10455     emit_cmpfp3(_masm, $dst$$Register);
10456   %}
10457   ins_pipe(pipe_slow);
10458 %}
10459 
10460 // Compare into -1,0,1
10461 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10462 %{
10463   match(Set dst (CmpD3 src1 src2));
10464   effect(KILL cr);
10465 
10466   ins_cost(275);
10467   format %{ "ucomisd $src1, $src2\n\t"
10468             "movl    $dst, #-1\n\t"
10469             "jp,s    done\n\t"
10470             "jb,s    done\n\t"
10471             "setne   $dst\n\t"
10472             "movzbl  $dst, $dst\n"
10473     "done:" %}
10474   ins_encode %{
10475     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10476     emit_cmpfp3(_masm, $dst$$Register);
10477   %}
10478   ins_pipe(pipe_slow);
10479 %}
10480 
10481 // Compare into -1,0,1
10482 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10483 %{
10484   match(Set dst (CmpD3 src1 (LoadD src2)));
10485   effect(KILL cr);
10486 
10487   ins_cost(275);
10488   format %{ "ucomisd $src1, $src2\n\t"
10489             "movl    $dst, #-1\n\t"
10490             "jp,s    done\n\t"
10491             "jb,s    done\n\t"
10492             "setne   $dst\n\t"
10493             "movzbl  $dst, $dst\n"
10494     "done:" %}
10495   ins_encode %{
10496     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10497     emit_cmpfp3(_masm, $dst$$Register);
10498   %}
10499   ins_pipe(pipe_slow);
10500 %}
10501 
10502 // Compare into -1,0,1
10503 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10504   match(Set dst (CmpD3 src con));
10505   effect(KILL cr);
10506 
10507   ins_cost(275);
10508   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10509             "movl    $dst, #-1\n\t"
10510             "jp,s    done\n\t"
10511             "jb,s    done\n\t"
10512             "setne   $dst\n\t"
10513             "movzbl  $dst, $dst\n"
10514     "done:" %}
10515   ins_encode %{
10516     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10517     emit_cmpfp3(_masm, $dst$$Register);
10518   %}
10519   ins_pipe(pipe_slow);
10520 %}
10521 
10522 //----------Arithmetic Conversion Instructions---------------------------------
10523 
10524 instruct convF2D_reg_reg(regD dst, regF src)
10525 %{
10526   match(Set dst (ConvF2D src));
10527 
10528   format %{ "cvtss2sd $dst, $src" %}
10529   ins_encode %{
10530     __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10531   %}
10532   ins_pipe(pipe_slow); // XXX
10533 %}
10534 
10535 instruct convF2D_reg_mem(regD dst, memory src)
10536 %{
10537   match(Set dst (ConvF2D (LoadF src)));
10538 
10539   format %{ "cvtss2sd $dst, $src" %}
10540   ins_encode %{
10541     __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10542   %}
10543   ins_pipe(pipe_slow); // XXX
10544 %}
10545 
10546 instruct convD2F_reg_reg(regF dst, regD src)
10547 %{
10548   match(Set dst (ConvD2F src));
10549 
10550   format %{ "cvtsd2ss $dst, $src" %}
10551   ins_encode %{
10552     __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10553   %}
10554   ins_pipe(pipe_slow); // XXX
10555 %}
10556 
10557 instruct convD2F_reg_mem(regF dst, memory src)
10558 %{
10559   match(Set dst (ConvD2F (LoadD src)));
10560 
10561   format %{ "cvtsd2ss $dst, $src" %}
10562   ins_encode %{
10563     __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10564   %}
10565   ins_pipe(pipe_slow); // XXX
10566 %}
10567 
10568 // XXX do mem variants
10569 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10570 %{
10571   match(Set dst (ConvF2I src));
10572   effect(KILL cr);
10573   format %{ "convert_f2i $dst,$src" %}
10574   ins_encode %{
10575     __ convert_f2i($dst$$Register, $src$$XMMRegister);
10576   %}
10577   ins_pipe(pipe_slow);
10578 %}
10579 
10580 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10581 %{
10582   match(Set dst (ConvF2L src));
10583   effect(KILL cr);
10584   format %{ "convert_f2l $dst,$src"%}
10585   ins_encode %{
10586     __ convert_f2l($dst$$Register, $src$$XMMRegister);
10587   %}
10588   ins_pipe(pipe_slow);
10589 %}
10590 
10591 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10592 %{
10593   match(Set dst (ConvD2I src));
10594   effect(KILL cr);
10595   format %{ "convert_d2i $dst,$src"%}
10596   ins_encode %{
10597     __ convert_d2i($dst$$Register, $src$$XMMRegister);
10598   %}
10599   ins_pipe(pipe_slow);
10600 %}
10601 
10602 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10603 %{
10604   match(Set dst (ConvD2L src));
10605   effect(KILL cr);
10606   format %{ "convert_d2l $dst,$src"%}
10607   ins_encode %{
10608     __ convert_d2l($dst$$Register, $src$$XMMRegister);
10609   %}
10610   ins_pipe(pipe_slow);
10611 %}
10612 
10613 instruct convI2F_reg_reg(regF dst, rRegI src)
10614 %{
10615   predicate(!UseXmmI2F);
10616   match(Set dst (ConvI2F src));
10617 
10618   format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10619   ins_encode %{
10620     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10621   %}
10622   ins_pipe(pipe_slow); // XXX
10623 %}
10624 
10625 instruct convI2F_reg_mem(regF dst, memory src)
10626 %{
10627   match(Set dst (ConvI2F (LoadI src)));
10628 
10629   format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10630   ins_encode %{
10631     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10632   %}
10633   ins_pipe(pipe_slow); // XXX
10634 %}
10635 
10636 instruct convI2D_reg_reg(regD dst, rRegI src)
10637 %{
10638   predicate(!UseXmmI2D);
10639   match(Set dst (ConvI2D src));
10640 
10641   format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10642   ins_encode %{
10643     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10644   %}
10645   ins_pipe(pipe_slow); // XXX
10646 %}
10647 
10648 instruct convI2D_reg_mem(regD dst, memory src)
10649 %{
10650   match(Set dst (ConvI2D (LoadI src)));
10651 
10652   format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10653   ins_encode %{
10654     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10655   %}
10656   ins_pipe(pipe_slow); // XXX
10657 %}
10658 
10659 instruct convXI2F_reg(regF dst, rRegI src)
10660 %{
10661   predicate(UseXmmI2F);
10662   match(Set dst (ConvI2F src));
10663 
10664   format %{ "movdl $dst, $src\n\t"
10665             "cvtdq2psl $dst, $dst\t# i2f" %}
10666   ins_encode %{
10667     __ movdl($dst$$XMMRegister, $src$$Register);
10668     __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10669   %}
10670   ins_pipe(pipe_slow); // XXX
10671 %}
10672 
10673 instruct convXI2D_reg(regD dst, rRegI src)
10674 %{
10675   predicate(UseXmmI2D);
10676   match(Set dst (ConvI2D src));
10677 
10678   format %{ "movdl $dst, $src\n\t"
10679             "cvtdq2pdl $dst, $dst\t# i2d" %}
10680   ins_encode %{
10681     __ movdl($dst$$XMMRegister, $src$$Register);
10682     __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10683   %}
10684   ins_pipe(pipe_slow); // XXX
10685 %}
10686 
10687 instruct convL2F_reg_reg(regF dst, rRegL src)
10688 %{
10689   match(Set dst (ConvL2F src));
10690 
10691   format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10692   ins_encode %{
10693     __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10694   %}
10695   ins_pipe(pipe_slow); // XXX
10696 %}
10697 
10698 instruct convL2F_reg_mem(regF dst, memory src)
10699 %{
10700   match(Set dst (ConvL2F (LoadL src)));
10701 
10702   format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10703   ins_encode %{
10704     __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10705   %}
10706   ins_pipe(pipe_slow); // XXX
10707 %}
10708 
10709 instruct convL2D_reg_reg(regD dst, rRegL src)
10710 %{
10711   match(Set dst (ConvL2D src));
10712 
10713   format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10714   ins_encode %{
10715     __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10716   %}
10717   ins_pipe(pipe_slow); // XXX
10718 %}
10719 
10720 instruct convL2D_reg_mem(regD dst, memory src)
10721 %{
10722   match(Set dst (ConvL2D (LoadL src)));
10723 
10724   format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10725   ins_encode %{
10726     __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10727   %}
10728   ins_pipe(pipe_slow); // XXX
10729 %}
10730 
10731 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10732 %{
10733   match(Set dst (ConvI2L src));
10734 
10735   ins_cost(125);
10736   format %{ "movslq  $dst, $src\t# i2l" %}
10737   ins_encode %{
10738     __ movslq($dst$$Register, $src$$Register);
10739   %}
10740   ins_pipe(ialu_reg_reg);
10741 %}
10742 
10743 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10744 // %{
10745 //   match(Set dst (ConvI2L src));
10746 // //   predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10747 // //             _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10748 //   predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10749 //             (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10750 //             ((const TypeNode*) n)->type()->is_long()->_lo ==
10751 //             (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10752 
10753 //   format %{ "movl    $dst, $src\t# unsigned i2l" %}
10754 //   ins_encode(enc_copy(dst, src));
10755 // //   opcode(0x63); // needs REX.W
10756 // //   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10757 //   ins_pipe(ialu_reg_reg);
10758 // %}
10759 
10760 // Zero-extend convert int to long
10761 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10762 %{
10763   match(Set dst (AndL (ConvI2L src) mask));
10764 
10765   format %{ "movl    $dst, $src\t# i2l zero-extend\n\t" %}
10766   ins_encode %{
10767     if ($dst$$reg != $src$$reg) {
10768       __ movl($dst$$Register, $src$$Register);
10769     }
10770   %}
10771   ins_pipe(ialu_reg_reg);
10772 %}
10773 
10774 // Zero-extend convert int to long
10775 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10776 %{
10777   match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10778 
10779   format %{ "movl    $dst, $src\t# i2l zero-extend\n\t" %}
10780   ins_encode %{
10781     __ movl($dst$$Register, $src$$Address);
10782   %}
10783   ins_pipe(ialu_reg_mem);
10784 %}
10785 
10786 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10787 %{
10788   match(Set dst (AndL src mask));
10789 
10790   format %{ "movl    $dst, $src\t# zero-extend long" %}
10791   ins_encode %{
10792     __ movl($dst$$Register, $src$$Register);
10793   %}
10794   ins_pipe(ialu_reg_reg);
10795 %}
10796 
10797 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10798 %{
10799   match(Set dst (ConvL2I src));
10800 
10801   format %{ "movl    $dst, $src\t# l2i" %}
10802   ins_encode %{
10803     __ movl($dst$$Register, $src$$Register);
10804   %}
10805   ins_pipe(ialu_reg_reg);
10806 %}
10807 
10808 
10809 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10810   match(Set dst (MoveF2I src));
10811   effect(DEF dst, USE src);
10812 
10813   ins_cost(125);
10814   format %{ "movl    $dst, $src\t# MoveF2I_stack_reg" %}
10815   ins_encode %{
10816     __ movl($dst$$Register, Address(rsp, $src$$disp));
10817   %}
10818   ins_pipe(ialu_reg_mem);
10819 %}
10820 
10821 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10822   match(Set dst (MoveI2F src));
10823   effect(DEF dst, USE src);
10824 
10825   ins_cost(125);
10826   format %{ "movss   $dst, $src\t# MoveI2F_stack_reg" %}
10827   ins_encode %{
10828     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10829   %}
10830   ins_pipe(pipe_slow);
10831 %}
10832 
10833 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10834   match(Set dst (MoveD2L src));
10835   effect(DEF dst, USE src);
10836 
10837   ins_cost(125);
10838   format %{ "movq    $dst, $src\t# MoveD2L_stack_reg" %}
10839   ins_encode %{
10840     __ movq($dst$$Register, Address(rsp, $src$$disp));
10841   %}
10842   ins_pipe(ialu_reg_mem);
10843 %}
10844 
10845 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10846   predicate(!UseXmmLoadAndClearUpper);
10847   match(Set dst (MoveL2D src));
10848   effect(DEF dst, USE src);
10849 
10850   ins_cost(125);
10851   format %{ "movlpd  $dst, $src\t# MoveL2D_stack_reg" %}
10852   ins_encode %{
10853     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10854   %}
10855   ins_pipe(pipe_slow);
10856 %}
10857 
10858 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10859   predicate(UseXmmLoadAndClearUpper);
10860   match(Set dst (MoveL2D src));
10861   effect(DEF dst, USE src);
10862 
10863   ins_cost(125);
10864   format %{ "movsd   $dst, $src\t# MoveL2D_stack_reg" %}
10865   ins_encode %{
10866     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10867   %}
10868   ins_pipe(pipe_slow);
10869 %}
10870 
10871 
10872 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10873   match(Set dst (MoveF2I src));
10874   effect(DEF dst, USE src);
10875 
10876   ins_cost(95); // XXX
10877   format %{ "movss   $dst, $src\t# MoveF2I_reg_stack" %}
10878   ins_encode %{
10879     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10880   %}
10881   ins_pipe(pipe_slow);
10882 %}
10883 
10884 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10885   match(Set dst (MoveI2F src));
10886   effect(DEF dst, USE src);
10887 
10888   ins_cost(100);
10889   format %{ "movl    $dst, $src\t# MoveI2F_reg_stack" %}
10890   ins_encode %{
10891     __ movl(Address(rsp, $dst$$disp), $src$$Register);
10892   %}
10893   ins_pipe( ialu_mem_reg );
10894 %}
10895 
10896 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10897   match(Set dst (MoveD2L src));
10898   effect(DEF dst, USE src);
10899 
10900   ins_cost(95); // XXX
10901   format %{ "movsd   $dst, $src\t# MoveL2D_reg_stack" %}
10902   ins_encode %{
10903     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10904   %}
10905   ins_pipe(pipe_slow);
10906 %}
10907 
10908 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10909   match(Set dst (MoveL2D src));
10910   effect(DEF dst, USE src);
10911 
10912   ins_cost(100);
10913   format %{ "movq    $dst, $src\t# MoveL2D_reg_stack" %}
10914   ins_encode %{
10915     __ movq(Address(rsp, $dst$$disp), $src$$Register);
10916   %}
10917   ins_pipe(ialu_mem_reg);
10918 %}
10919 
10920 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10921   match(Set dst (MoveF2I src));
10922   effect(DEF dst, USE src);
10923   ins_cost(85);
10924   format %{ "movd    $dst,$src\t# MoveF2I" %}
10925   ins_encode %{
10926     __ movdl($dst$$Register, $src$$XMMRegister);
10927   %}
10928   ins_pipe( pipe_slow );
10929 %}
10930 
10931 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10932   match(Set dst (MoveD2L src));
10933   effect(DEF dst, USE src);
10934   ins_cost(85);
10935   format %{ "movd    $dst,$src\t# MoveD2L" %}
10936   ins_encode %{
10937     __ movdq($dst$$Register, $src$$XMMRegister);
10938   %}
10939   ins_pipe( pipe_slow );
10940 %}
10941 
10942 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10943   match(Set dst (MoveI2F src));
10944   effect(DEF dst, USE src);
10945   ins_cost(100);
10946   format %{ "movd    $dst,$src\t# MoveI2F" %}
10947   ins_encode %{
10948     __ movdl($dst$$XMMRegister, $src$$Register);
10949   %}
10950   ins_pipe( pipe_slow );
10951 %}
10952 
10953 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10954   match(Set dst (MoveL2D src));
10955   effect(DEF dst, USE src);
10956   ins_cost(100);
10957   format %{ "movd    $dst,$src\t# MoveL2D" %}
10958   ins_encode %{
10959      __ movdq($dst$$XMMRegister, $src$$Register);
10960   %}
10961   ins_pipe( pipe_slow );
10962 %}
10963 
10964 
10965 // =======================================================================
10966 // fast clearing of an array
10967 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
10968                   Universe dummy, rFlagsReg cr)
10969 %{
10970   predicate(!((ClearArrayNode*)n)->is_large());
10971   match(Set dummy (ClearArray cnt base));
10972   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
10973 
10974   format %{ $$template
10975     $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
10976     $$emit$$"cmp     InitArrayShortSize,rcx\n\t"
10977     $$emit$$"jg      LARGE\n\t"
10978     $$emit$$"dec     rcx\n\t"
10979     $$emit$$"js      DONE\t# Zero length\n\t"
10980     $$emit$$"mov     rax,(rdi,rcx,8)\t# LOOP\n\t"
10981     $$emit$$"dec     rcx\n\t"
10982     $$emit$$"jge     LOOP\n\t"
10983     $$emit$$"jmp     DONE\n\t"
10984     $$emit$$"# LARGE:\n\t"
10985     if (UseFastStosb) {
10986        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
10987        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--\n\t"
10988     } else if (UseXMMForObjInit) {
10989        $$emit$$"mov     rdi,rax\n\t"
10990        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
10991        $$emit$$"jmpq    L_zero_64_bytes\n\t"
10992        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10993        $$emit$$"vmovdqu ymm0,(rax)\n\t"
10994        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
10995        $$emit$$"add     0x40,rax\n\t"
10996        $$emit$$"# L_zero_64_bytes:\n\t"
10997        $$emit$$"sub     0x8,rcx\n\t"
10998        $$emit$$"jge     L_loop\n\t"
10999        $$emit$$"add     0x4,rcx\n\t"
11000        $$emit$$"jl      L_tail\n\t"
11001        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11002        $$emit$$"add     0x20,rax\n\t"
11003        $$emit$$"sub     0x4,rcx\n\t"
11004        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11005        $$emit$$"add     0x4,rcx\n\t"
11006        $$emit$$"jle     L_end\n\t"
11007        $$emit$$"dec     rcx\n\t"
11008        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11009        $$emit$$"vmovq   xmm0,(rax)\n\t"
11010        $$emit$$"add     0x8,rax\n\t"
11011        $$emit$$"dec     rcx\n\t"
11012        $$emit$$"jge     L_sloop\n\t"
11013        $$emit$$"# L_end:\n\t"
11014     } else {
11015        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--\n\t"
11016     }
11017     $$emit$$"# DONE"
11018   %}
11019   ins_encode %{
11020     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11021                  $tmp$$XMMRegister, false);
11022   %}
11023   ins_pipe(pipe_slow);
11024 %}
11025 
11026 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11027                         Universe dummy, rFlagsReg cr)
11028 %{
11029   predicate(((ClearArrayNode*)n)->is_large());
11030   match(Set dummy (ClearArray cnt base));
11031   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11032 
11033   format %{ $$template
11034     if (UseFastStosb) {
11035        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11036        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
11037        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--"
11038     } else if (UseXMMForObjInit) {
11039        $$emit$$"mov     rdi,rax\t# ClearArray:\n\t"
11040        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
11041        $$emit$$"jmpq    L_zero_64_bytes\n\t"
11042        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11043        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11044        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11045        $$emit$$"add     0x40,rax\n\t"
11046        $$emit$$"# L_zero_64_bytes:\n\t"
11047        $$emit$$"sub     0x8,rcx\n\t"
11048        $$emit$$"jge     L_loop\n\t"
11049        $$emit$$"add     0x4,rcx\n\t"
11050        $$emit$$"jl      L_tail\n\t"
11051        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11052        $$emit$$"add     0x20,rax\n\t"
11053        $$emit$$"sub     0x4,rcx\n\t"
11054        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11055        $$emit$$"add     0x4,rcx\n\t"
11056        $$emit$$"jle     L_end\n\t"
11057        $$emit$$"dec     rcx\n\t"
11058        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11059        $$emit$$"vmovq   xmm0,(rax)\n\t"
11060        $$emit$$"add     0x8,rax\n\t"
11061        $$emit$$"dec     rcx\n\t"
11062        $$emit$$"jge     L_sloop\n\t"
11063        $$emit$$"# L_end:\n\t"
11064     } else {
11065        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11066        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--"
11067     }
11068   %}
11069   ins_encode %{
11070     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11071                  $tmp$$XMMRegister, true);
11072   %}
11073   ins_pipe(pipe_slow);
11074 %}
11075 
11076 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11077                          rax_RegI result, legRegD tmp1, rFlagsReg cr)
11078 %{
11079   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11080   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11081   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11082 
11083   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11084   ins_encode %{
11085     __ string_compare($str1$$Register, $str2$$Register,
11086                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11087                       $tmp1$$XMMRegister, StrIntrinsicNode::LL);
11088   %}
11089   ins_pipe( pipe_slow );
11090 %}
11091 
11092 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11093                          rax_RegI result, legRegD tmp1, rFlagsReg cr)
11094 %{
11095   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11096   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11097   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11098 
11099   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11100   ins_encode %{
11101     __ string_compare($str1$$Register, $str2$$Register,
11102                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11103                       $tmp1$$XMMRegister, StrIntrinsicNode::UU);
11104   %}
11105   ins_pipe( pipe_slow );
11106 %}
11107 
11108 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11109                           rax_RegI result, legRegD tmp1, rFlagsReg cr)
11110 %{
11111   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11112   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11113   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11114 
11115   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11116   ins_encode %{
11117     __ string_compare($str1$$Register, $str2$$Register,
11118                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11119                       $tmp1$$XMMRegister, StrIntrinsicNode::LU);
11120   %}
11121   ins_pipe( pipe_slow );
11122 %}
11123 
11124 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11125                           rax_RegI result, legRegD tmp1, rFlagsReg cr)
11126 %{
11127   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11128   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11129   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11130 
11131   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11132   ins_encode %{
11133     __ string_compare($str2$$Register, $str1$$Register,
11134                       $cnt2$$Register, $cnt1$$Register, $result$$Register,
11135                       $tmp1$$XMMRegister, StrIntrinsicNode::UL);
11136   %}
11137   ins_pipe( pipe_slow );
11138 %}
11139 
11140 // fast search of substring with known size.
11141 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11142                              rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11143 %{
11144   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11145   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11146   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11147 
11148   format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11149   ins_encode %{
11150     int icnt2 = (int)$int_cnt2$$constant;
11151     if (icnt2 >= 16) {
11152       // IndexOf for constant substrings with size >= 16 elements
11153       // which don't need to be loaded through stack.
11154       __ string_indexofC8($str1$$Register, $str2$$Register,
11155                           $cnt1$$Register, $cnt2$$Register,
11156                           icnt2, $result$$Register,
11157                           $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11158     } else {
11159       // Small strings are loaded through stack if they cross page boundary.
11160       __ string_indexof($str1$$Register, $str2$$Register,
11161                         $cnt1$$Register, $cnt2$$Register,
11162                         icnt2, $result$$Register,
11163                         $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11164     }
11165   %}
11166   ins_pipe( pipe_slow );
11167 %}
11168 
11169 // fast search of substring with known size.
11170 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11171                              rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11172 %{
11173   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11174   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11175   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11176 
11177   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11178   ins_encode %{
11179     int icnt2 = (int)$int_cnt2$$constant;
11180     if (icnt2 >= 8) {
11181       // IndexOf for constant substrings with size >= 8 elements
11182       // which don't need to be loaded through stack.
11183       __ string_indexofC8($str1$$Register, $str2$$Register,
11184                           $cnt1$$Register, $cnt2$$Register,
11185                           icnt2, $result$$Register,
11186                           $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11187     } else {
11188       // Small strings are loaded through stack if they cross page boundary.
11189       __ string_indexof($str1$$Register, $str2$$Register,
11190                         $cnt1$$Register, $cnt2$$Register,
11191                         icnt2, $result$$Register,
11192                         $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11193     }
11194   %}
11195   ins_pipe( pipe_slow );
11196 %}
11197 
11198 // fast search of substring with known size.
11199 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11200                               rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11201 %{
11202   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11203   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11204   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11205 
11206   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11207   ins_encode %{
11208     int icnt2 = (int)$int_cnt2$$constant;
11209     if (icnt2 >= 8) {
11210       // IndexOf for constant substrings with size >= 8 elements
11211       // which don't need to be loaded through stack.
11212       __ string_indexofC8($str1$$Register, $str2$$Register,
11213                           $cnt1$$Register, $cnt2$$Register,
11214                           icnt2, $result$$Register,
11215                           $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11216     } else {
11217       // Small strings are loaded through stack if they cross page boundary.
11218       __ string_indexof($str1$$Register, $str2$$Register,
11219                         $cnt1$$Register, $cnt2$$Register,
11220                         icnt2, $result$$Register,
11221                         $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11222     }
11223   %}
11224   ins_pipe( pipe_slow );
11225 %}
11226 
11227 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11228                          rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11229 %{
11230   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11231   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11232   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11233 
11234   format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11235   ins_encode %{
11236     __ string_indexof($str1$$Register, $str2$$Register,
11237                       $cnt1$$Register, $cnt2$$Register,
11238                       (-1), $result$$Register,
11239                       $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11240   %}
11241   ins_pipe( pipe_slow );
11242 %}
11243 
11244 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11245                          rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11246 %{
11247   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11248   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11249   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11250 
11251   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11252   ins_encode %{
11253     __ string_indexof($str1$$Register, $str2$$Register,
11254                       $cnt1$$Register, $cnt2$$Register,
11255                       (-1), $result$$Register,
11256                       $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11257   %}
11258   ins_pipe( pipe_slow );
11259 %}
11260 
11261 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11262                           rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11263 %{
11264   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11265   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11266   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11267 
11268   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11269   ins_encode %{
11270     __ string_indexof($str1$$Register, $str2$$Register,
11271                       $cnt1$$Register, $cnt2$$Register,
11272                       (-1), $result$$Register,
11273                       $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11274   %}
11275   ins_pipe( pipe_slow );
11276 %}
11277 
11278 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11279                               rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
11280 %{
11281   predicate(UseSSE42Intrinsics);
11282   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11283   effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11284   format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result   // KILL all" %}
11285   ins_encode %{
11286     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11287                            $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
11288   %}
11289   ins_pipe( pipe_slow );
11290 %}
11291 
11292 // fast string equals
11293 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11294                        legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr)
11295 %{
11296   match(Set result (StrEquals (Binary str1 str2) cnt));
11297   effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11298 
11299   format %{ "String Equals $str1,$str2,$cnt -> $result    // KILL $tmp1, $tmp2, $tmp3" %}
11300   ins_encode %{
11301     __ arrays_equals(false, $str1$$Register, $str2$$Register,
11302                      $cnt$$Register, $result$$Register, $tmp3$$Register,
11303                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11304   %}
11305   ins_pipe( pipe_slow );
11306 %}
11307 
11308 // fast array equals
11309 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11310                        legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11311 %{
11312   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11313   match(Set result (AryEq ary1 ary2));
11314   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11315 
11316   format %{ "Array Equals byte[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11317   ins_encode %{
11318     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11319                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
11320                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11321   %}
11322   ins_pipe( pipe_slow );
11323 %}
11324 
11325 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11326                        legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11327 %{
11328   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11329   match(Set result (AryEq ary1 ary2));
11330   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11331 
11332   format %{ "Array Equals char[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11333   ins_encode %{
11334     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11335                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
11336                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
11337   %}
11338   ins_pipe( pipe_slow );
11339 %}
11340 
11341 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11342                        legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr)
11343 %{
11344   match(Set result (HasNegatives ary1 len));
11345   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11346 
11347   format %{ "has negatives byte[] $ary1,$len -> $result   // KILL $tmp1, $tmp2, $tmp3" %}
11348   ins_encode %{
11349     __ has_negatives($ary1$$Register, $len$$Register,
11350                      $result$$Register, $tmp3$$Register,
11351                      $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11352   %}
11353   ins_pipe( pipe_slow );
11354 %}
11355 
11356 // fast char[] to byte[] compression
11357 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
11358                          rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11359   match(Set result (StrCompressedCopy src (Binary dst len)));
11360   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11361 
11362   format %{ "String Compress $src,$dst -> $result    // KILL RAX, RCX, RDX" %}
11363   ins_encode %{
11364     __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11365                            $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11366                            $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11367   %}
11368   ins_pipe( pipe_slow );
11369 %}
11370 
11371 // fast byte[] to char[] inflation
11372 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11373                         legRegD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11374   match(Set dummy (StrInflatedCopy src (Binary dst len)));
11375   effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11376 
11377   format %{ "String Inflate $src,$dst    // KILL $tmp1, $tmp2" %}
11378   ins_encode %{
11379     __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11380                           $tmp1$$XMMRegister, $tmp2$$Register);
11381   %}
11382   ins_pipe( pipe_slow );
11383 %}
11384 
11385 // encode char[] to byte[] in ISO_8859_1
11386 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11387                           legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
11388                           rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11389   match(Set result (EncodeISOArray src (Binary dst len)));
11390   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11391 
11392   format %{ "Encode array $src,$dst,$len -> $result    // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11393   ins_encode %{
11394     __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11395                         $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11396                         $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11397   %}
11398   ins_pipe( pipe_slow );
11399 %}
11400 
11401 //----------Overflow Math Instructions-----------------------------------------
11402 
11403 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11404 %{
11405   match(Set cr (OverflowAddI op1 op2));
11406   effect(DEF cr, USE_KILL op1, USE op2);
11407 
11408   format %{ "addl    $op1, $op2\t# overflow check int" %}
11409 
11410   ins_encode %{
11411     __ addl($op1$$Register, $op2$$Register);
11412   %}
11413   ins_pipe(ialu_reg_reg);
11414 %}
11415 
11416 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11417 %{
11418   match(Set cr (OverflowAddI op1 op2));
11419   effect(DEF cr, USE_KILL op1, USE op2);
11420 
11421   format %{ "addl    $op1, $op2\t# overflow check int" %}
11422 
11423   ins_encode %{
11424     __ addl($op1$$Register, $op2$$constant);
11425   %}
11426   ins_pipe(ialu_reg_reg);
11427 %}
11428 
11429 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11430 %{
11431   match(Set cr (OverflowAddL op1 op2));
11432   effect(DEF cr, USE_KILL op1, USE op2);
11433 
11434   format %{ "addq    $op1, $op2\t# overflow check long" %}
11435   ins_encode %{
11436     __ addq($op1$$Register, $op2$$Register);
11437   %}
11438   ins_pipe(ialu_reg_reg);
11439 %}
11440 
11441 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11442 %{
11443   match(Set cr (OverflowAddL op1 op2));
11444   effect(DEF cr, USE_KILL op1, USE op2);
11445 
11446   format %{ "addq    $op1, $op2\t# overflow check long" %}
11447   ins_encode %{
11448     __ addq($op1$$Register, $op2$$constant);
11449   %}
11450   ins_pipe(ialu_reg_reg);
11451 %}
11452 
11453 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11454 %{
11455   match(Set cr (OverflowSubI op1 op2));
11456 
11457   format %{ "cmpl    $op1, $op2\t# overflow check int" %}
11458   ins_encode %{
11459     __ cmpl($op1$$Register, $op2$$Register);
11460   %}
11461   ins_pipe(ialu_reg_reg);
11462 %}
11463 
11464 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11465 %{
11466   match(Set cr (OverflowSubI op1 op2));
11467 
11468   format %{ "cmpl    $op1, $op2\t# overflow check int" %}
11469   ins_encode %{
11470     __ cmpl($op1$$Register, $op2$$constant);
11471   %}
11472   ins_pipe(ialu_reg_reg);
11473 %}
11474 
11475 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11476 %{
11477   match(Set cr (OverflowSubL op1 op2));
11478 
11479   format %{ "cmpq    $op1, $op2\t# overflow check long" %}
11480   ins_encode %{
11481     __ cmpq($op1$$Register, $op2$$Register);
11482   %}
11483   ins_pipe(ialu_reg_reg);
11484 %}
11485 
11486 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11487 %{
11488   match(Set cr (OverflowSubL op1 op2));
11489 
11490   format %{ "cmpq    $op1, $op2\t# overflow check long" %}
11491   ins_encode %{
11492     __ cmpq($op1$$Register, $op2$$constant);
11493   %}
11494   ins_pipe(ialu_reg_reg);
11495 %}
11496 
11497 instruct overflowNegI_rReg(rFlagsReg cr, immI_0 zero, rax_RegI op2)
11498 %{
11499   match(Set cr (OverflowSubI zero op2));
11500   effect(DEF cr, USE_KILL op2);
11501 
11502   format %{ "negl    $op2\t# overflow check int" %}
11503   ins_encode %{
11504     __ negl($op2$$Register);
11505   %}
11506   ins_pipe(ialu_reg_reg);
11507 %}
11508 
11509 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11510 %{
11511   match(Set cr (OverflowSubL zero op2));
11512   effect(DEF cr, USE_KILL op2);
11513 
11514   format %{ "negq    $op2\t# overflow check long" %}
11515   ins_encode %{
11516     __ negq($op2$$Register);
11517   %}
11518   ins_pipe(ialu_reg_reg);
11519 %}
11520 
11521 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11522 %{
11523   match(Set cr (OverflowMulI op1 op2));
11524   effect(DEF cr, USE_KILL op1, USE op2);
11525 
11526   format %{ "imull    $op1, $op2\t# overflow check int" %}
11527   ins_encode %{
11528     __ imull($op1$$Register, $op2$$Register);
11529   %}
11530   ins_pipe(ialu_reg_reg_alu0);
11531 %}
11532 
11533 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11534 %{
11535   match(Set cr (OverflowMulI op1 op2));
11536   effect(DEF cr, TEMP tmp, USE op1, USE op2);
11537 
11538   format %{ "imull    $tmp, $op1, $op2\t# overflow check int" %}
11539   ins_encode %{
11540     __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11541   %}
11542   ins_pipe(ialu_reg_reg_alu0);
11543 %}
11544 
11545 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11546 %{
11547   match(Set cr (OverflowMulL op1 op2));
11548   effect(DEF cr, USE_KILL op1, USE op2);
11549 
11550   format %{ "imulq    $op1, $op2\t# overflow check long" %}
11551   ins_encode %{
11552     __ imulq($op1$$Register, $op2$$Register);
11553   %}
11554   ins_pipe(ialu_reg_reg_alu0);
11555 %}
11556 
11557 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11558 %{
11559   match(Set cr (OverflowMulL op1 op2));
11560   effect(DEF cr, TEMP tmp, USE op1, USE op2);
11561 
11562   format %{ "imulq    $tmp, $op1, $op2\t# overflow check long" %}
11563   ins_encode %{
11564     __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11565   %}
11566   ins_pipe(ialu_reg_reg_alu0);
11567 %}
11568 
11569 
11570 //----------Control Flow Instructions------------------------------------------
11571 // Signed compare Instructions
11572 
11573 // XXX more variants!!
11574 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11575 %{
11576   match(Set cr (CmpI op1 op2));
11577   effect(DEF cr, USE op1, USE op2);
11578 
11579   format %{ "cmpl    $op1, $op2" %}
11580   opcode(0x3B);  /* Opcode 3B /r */
11581   ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11582   ins_pipe(ialu_cr_reg_reg);
11583 %}
11584 
11585 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11586 %{
11587   match(Set cr (CmpI op1 op2));
11588 
11589   format %{ "cmpl    $op1, $op2" %}
11590   opcode(0x81, 0x07); /* Opcode 81 /7 */
11591   ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11592   ins_pipe(ialu_cr_reg_imm);
11593 %}
11594 
11595 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11596 %{
11597   match(Set cr (CmpI op1 (LoadI op2)));
11598 
11599   ins_cost(500); // XXX
11600   format %{ "cmpl    $op1, $op2" %}
11601   opcode(0x3B); /* Opcode 3B /r */
11602   ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11603   ins_pipe(ialu_cr_reg_mem);
11604 %}
11605 
11606 instruct testI_reg(rFlagsReg cr, rRegI src, immI_0 zero)
11607 %{
11608   match(Set cr (CmpI src zero));
11609 
11610   format %{ "testl   $src, $src" %}
11611   opcode(0x85);
11612   ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11613   ins_pipe(ialu_cr_reg_imm);
11614 %}
11615 
11616 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI_0 zero)
11617 %{
11618   match(Set cr (CmpI (AndI src con) zero));
11619 
11620   format %{ "testl   $src, $con" %}
11621   opcode(0xF7, 0x00);
11622   ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11623   ins_pipe(ialu_cr_reg_imm);
11624 %}
11625 
11626 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI_0 zero)
11627 %{
11628   match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11629 
11630   format %{ "testl   $src, $mem" %}
11631   opcode(0x85);
11632   ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11633   ins_pipe(ialu_cr_reg_mem);
11634 %}
11635 
11636 // Unsigned compare Instructions; really, same as signed except they
11637 // produce an rFlagsRegU instead of rFlagsReg.
11638 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11639 %{
11640   match(Set cr (CmpU op1 op2));
11641 
11642   format %{ "cmpl    $op1, $op2\t# unsigned" %}
11643   opcode(0x3B); /* Opcode 3B /r */
11644   ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11645   ins_pipe(ialu_cr_reg_reg);
11646 %}
11647 
11648 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11649 %{
11650   match(Set cr (CmpU op1 op2));
11651 
11652   format %{ "cmpl    $op1, $op2\t# unsigned" %}
11653   opcode(0x81,0x07); /* Opcode 81 /7 */
11654   ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11655   ins_pipe(ialu_cr_reg_imm);
11656 %}
11657 
11658 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11659 %{
11660   match(Set cr (CmpU op1 (LoadI op2)));
11661 
11662   ins_cost(500); // XXX
11663   format %{ "cmpl    $op1, $op2\t# unsigned" %}
11664   opcode(0x3B); /* Opcode 3B /r */
11665   ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11666   ins_pipe(ialu_cr_reg_mem);
11667 %}
11668 
11669 // // // Cisc-spilled version of cmpU_rReg
11670 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11671 // //%{
11672 // //  match(Set cr (CmpU (LoadI op1) op2));
11673 // //
11674 // //  format %{ "CMPu   $op1,$op2" %}
11675 // //  ins_cost(500);
11676 // //  opcode(0x39);  /* Opcode 39 /r */
11677 // //  ins_encode( OpcP, reg_mem( op1, op2) );
11678 // //%}
11679 
11680 instruct testU_reg(rFlagsRegU cr, rRegI src, immI_0 zero)
11681 %{
11682   match(Set cr (CmpU src zero));
11683 
11684   format %{ "testl   $src, $src\t# unsigned" %}
11685   opcode(0x85);
11686   ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11687   ins_pipe(ialu_cr_reg_imm);
11688 %}
11689 
11690 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11691 %{
11692   match(Set cr (CmpP op1 op2));
11693 
11694   format %{ "cmpq    $op1, $op2\t# ptr" %}
11695   opcode(0x3B); /* Opcode 3B /r */
11696   ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11697   ins_pipe(ialu_cr_reg_reg);
11698 %}
11699 
11700 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11701 %{
11702   match(Set cr (CmpP op1 (LoadP op2)));
11703   predicate(n->in(2)->as_Load()->barrier_data() == 0);
11704 
11705   ins_cost(500); // XXX
11706   format %{ "cmpq    $op1, $op2\t# ptr" %}
11707   opcode(0x3B); /* Opcode 3B /r */
11708   ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11709   ins_pipe(ialu_cr_reg_mem);
11710 %}
11711 
11712 // // // Cisc-spilled version of cmpP_rReg
11713 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11714 // //%{
11715 // //  match(Set cr (CmpP (LoadP op1) op2));
11716 // //
11717 // //  format %{ "CMPu   $op1,$op2" %}
11718 // //  ins_cost(500);
11719 // //  opcode(0x39);  /* Opcode 39 /r */
11720 // //  ins_encode( OpcP, reg_mem( op1, op2) );
11721 // //%}
11722 
11723 // XXX this is generalized by compP_rReg_mem???
11724 // Compare raw pointer (used in out-of-heap check).
11725 // Only works because non-oop pointers must be raw pointers
11726 // and raw pointers have no anti-dependencies.
11727 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11728 %{
11729   predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none &&
11730             n->in(2)->as_Load()->barrier_data() == 0);
11731   match(Set cr (CmpP op1 (LoadP op2)));
11732 
11733   format %{ "cmpq    $op1, $op2\t# raw ptr" %}
11734   opcode(0x3B); /* Opcode 3B /r */
11735   ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11736   ins_pipe(ialu_cr_reg_mem);
11737 %}
11738 
11739 // This will generate a signed flags result. This should be OK since
11740 // any compare to a zero should be eq/neq.
11741 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11742 %{
11743   match(Set cr (CmpP src zero));
11744 
11745   format %{ "testq   $src, $src\t# ptr" %}
11746   opcode(0x85);
11747   ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11748   ins_pipe(ialu_cr_reg_imm);
11749 %}
11750 
11751 // This will generate a signed flags result. This should be OK since
11752 // any compare to a zero should be eq/neq.
11753 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11754 %{
11755   predicate((!UseCompressedOops || (CompressedOops::base() != NULL)) &&
11756             n->in(1)->as_Load()->barrier_data() == 0);
11757   match(Set cr (CmpP (LoadP op) zero));
11758 
11759   ins_cost(500); // XXX
11760   format %{ "testq   $op, 0xffffffffffffffff\t# ptr" %}
11761   opcode(0xF7); /* Opcode F7 /0 */
11762   ins_encode(REX_mem_wide(op),
11763              OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11764   ins_pipe(ialu_cr_reg_imm);
11765 %}
11766 
11767 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11768 %{
11769   predicate(UseCompressedOops && (CompressedOops::base() == NULL) &&
11770             n->in(1)->as_Load()->barrier_data() == 0);
11771   match(Set cr (CmpP (LoadP mem) zero));
11772 
11773   format %{ "cmpq    R12, $mem\t# ptr (R12_heapbase==0)" %}
11774   ins_encode %{
11775     __ cmpq(r12, $mem$$Address);
11776   %}
11777   ins_pipe(ialu_cr_reg_mem);
11778 %}
11779 
11780 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11781 %{
11782   match(Set cr (CmpN op1 op2));
11783 
11784   format %{ "cmpl    $op1, $op2\t# compressed ptr" %}
11785   ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11786   ins_pipe(ialu_cr_reg_reg);
11787 %}
11788 
11789 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11790 %{
11791   match(Set cr (CmpN src (LoadN mem)));
11792 
11793   format %{ "cmpl    $src, $mem\t# compressed ptr" %}
11794   ins_encode %{
11795     __ cmpl($src$$Register, $mem$$Address);
11796   %}
11797   ins_pipe(ialu_cr_reg_mem);
11798 %}
11799 
11800 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11801   match(Set cr (CmpN op1 op2));
11802 
11803   format %{ "cmpl    $op1, $op2\t# compressed ptr" %}
11804   ins_encode %{
11805     __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11806   %}
11807   ins_pipe(ialu_cr_reg_imm);
11808 %}
11809 
11810 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11811 %{
11812   match(Set cr (CmpN src (LoadN mem)));
11813 
11814   format %{ "cmpl    $mem, $src\t# compressed ptr" %}
11815   ins_encode %{
11816     __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11817   %}
11818   ins_pipe(ialu_cr_reg_mem);
11819 %}
11820 
11821 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11822   match(Set cr (CmpN op1 op2));
11823 
11824   format %{ "cmpl    $op1, $op2\t# compressed klass ptr" %}
11825   ins_encode %{
11826     __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11827   %}
11828   ins_pipe(ialu_cr_reg_imm);
11829 %}
11830 
11831 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11832 %{
11833   match(Set cr (CmpN src (LoadNKlass mem)));
11834 
11835   format %{ "cmpl    $mem, $src\t# compressed klass ptr" %}
11836   ins_encode %{
11837     __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11838   %}
11839   ins_pipe(ialu_cr_reg_mem);
11840 %}
11841 
11842 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11843   match(Set cr (CmpN src zero));
11844 
11845   format %{ "testl   $src, $src\t# compressed ptr" %}
11846   ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11847   ins_pipe(ialu_cr_reg_imm);
11848 %}
11849 
11850 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11851 %{
11852   predicate(CompressedOops::base() != NULL);
11853   match(Set cr (CmpN (LoadN mem) zero));
11854 
11855   ins_cost(500); // XXX
11856   format %{ "testl   $mem, 0xffffffff\t# compressed ptr" %}
11857   ins_encode %{
11858     __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11859   %}
11860   ins_pipe(ialu_cr_reg_mem);
11861 %}
11862 
11863 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11864 %{
11865   predicate(CompressedOops::base() == NULL);
11866   match(Set cr (CmpN (LoadN mem) zero));
11867 
11868   format %{ "cmpl    R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11869   ins_encode %{
11870     __ cmpl(r12, $mem$$Address);
11871   %}
11872   ins_pipe(ialu_cr_reg_mem);
11873 %}
11874 
11875 // Yanked all unsigned pointer compare operations.
11876 // Pointer compares are done with CmpP which is already unsigned.
11877 
11878 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11879 %{
11880   match(Set cr (CmpL op1 op2));
11881 
11882   format %{ "cmpq    $op1, $op2" %}
11883   opcode(0x3B);  /* Opcode 3B /r */
11884   ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11885   ins_pipe(ialu_cr_reg_reg);
11886 %}
11887 
11888 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11889 %{
11890   match(Set cr (CmpL op1 op2));
11891 
11892   format %{ "cmpq    $op1, $op2" %}
11893   opcode(0x81, 0x07); /* Opcode 81 /7 */
11894   ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11895   ins_pipe(ialu_cr_reg_imm);
11896 %}
11897 
11898 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11899 %{
11900   match(Set cr (CmpL op1 (LoadL op2)));
11901 
11902   format %{ "cmpq    $op1, $op2" %}
11903   opcode(0x3B); /* Opcode 3B /r */
11904   ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11905   ins_pipe(ialu_cr_reg_mem);
11906 %}
11907 
11908 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11909 %{
11910   match(Set cr (CmpL src zero));
11911 
11912   format %{ "testq   $src, $src" %}
11913   opcode(0x85);
11914   ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11915   ins_pipe(ialu_cr_reg_imm);
11916 %}
11917 
11918 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11919 %{
11920   match(Set cr (CmpL (AndL src con) zero));
11921 
11922   format %{ "testq   $src, $con\t# long" %}
11923   opcode(0xF7, 0x00);
11924   ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11925   ins_pipe(ialu_cr_reg_imm);
11926 %}
11927 
11928 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11929 %{
11930   match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11931 
11932   format %{ "testq   $src, $mem" %}
11933   opcode(0x85);
11934   ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11935   ins_pipe(ialu_cr_reg_mem);
11936 %}
11937 
11938 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
11939 %{
11940   match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
11941 
11942   format %{ "testq   $src, $mem" %}
11943   opcode(0x85);
11944   ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11945   ins_pipe(ialu_cr_reg_mem);
11946 %}
11947 
11948 // Manifest a CmpL result in an integer register.  Very painful.
11949 // This is the test to avoid.
11950 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11951 %{
11952   match(Set dst (CmpL3 src1 src2));
11953   effect(KILL flags);
11954 
11955   ins_cost(275); // XXX
11956   format %{ "cmpq    $src1, $src2\t# CmpL3\n\t"
11957             "movl    $dst, -1\n\t"
11958             "jl,s    done\n\t"
11959             "setne   $dst\n\t"
11960             "movzbl  $dst, $dst\n\t"
11961     "done:" %}
11962   ins_encode(cmpl3_flag(src1, src2, dst));
11963   ins_pipe(pipe_slow);
11964 %}
11965 
11966 // Unsigned long compare Instructions; really, same as signed long except they
11967 // produce an rFlagsRegU instead of rFlagsReg.
11968 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
11969 %{
11970   match(Set cr (CmpUL op1 op2));
11971 
11972   format %{ "cmpq    $op1, $op2\t# unsigned" %}
11973   opcode(0x3B);  /* Opcode 3B /r */
11974   ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11975   ins_pipe(ialu_cr_reg_reg);
11976 %}
11977 
11978 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
11979 %{
11980   match(Set cr (CmpUL op1 op2));
11981 
11982   format %{ "cmpq    $op1, $op2\t# unsigned" %}
11983   opcode(0x81, 0x07); /* Opcode 81 /7 */
11984   ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11985   ins_pipe(ialu_cr_reg_imm);
11986 %}
11987 
11988 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
11989 %{
11990   match(Set cr (CmpUL op1 (LoadL op2)));
11991 
11992   format %{ "cmpq    $op1, $op2\t# unsigned" %}
11993   opcode(0x3B); /* Opcode 3B /r */
11994   ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11995   ins_pipe(ialu_cr_reg_mem);
11996 %}
11997 
11998 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
11999 %{
12000   match(Set cr (CmpUL src zero));
12001 
12002   format %{ "testq   $src, $src\t# unsigned" %}
12003   opcode(0x85);
12004   ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12005   ins_pipe(ialu_cr_reg_imm);
12006 %}
12007 
12008 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12009 %{
12010   match(Set cr (CmpI (LoadB mem) imm));
12011 
12012   ins_cost(125);
12013   format %{ "cmpb    $mem, $imm" %}
12014   ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12015   ins_pipe(ialu_cr_reg_mem);
12016 %}
12017 
12018 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI_0 zero)
12019 %{
12020   match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12021 
12022   ins_cost(125);
12023   format %{ "testb   $mem, $imm\t# ubyte" %}
12024   ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12025   ins_pipe(ialu_cr_reg_mem);
12026 %}
12027 
12028 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero)
12029 %{
12030   match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12031 
12032   ins_cost(125);
12033   format %{ "testb   $mem, $imm\t# byte" %}
12034   ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12035   ins_pipe(ialu_cr_reg_mem);
12036 %}
12037 
12038 //----------Max and Min--------------------------------------------------------
12039 // Min Instructions
12040 
12041 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12042 %{
12043   effect(USE_DEF dst, USE src, USE cr);
12044 
12045   format %{ "cmovlgt $dst, $src\t# min" %}
12046   opcode(0x0F, 0x4F);
12047   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12048   ins_pipe(pipe_cmov_reg);
12049 %}
12050 
12051 
12052 instruct minI_rReg(rRegI dst, rRegI src)
12053 %{
12054   match(Set dst (MinI dst src));
12055 
12056   ins_cost(200);
12057   expand %{
12058     rFlagsReg cr;
12059     compI_rReg(cr, dst, src);
12060     cmovI_reg_g(dst, src, cr);
12061   %}
12062 %}
12063 
12064 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12065 %{
12066   effect(USE_DEF dst, USE src, USE cr);
12067 
12068   format %{ "cmovllt $dst, $src\t# max" %}
12069   opcode(0x0F, 0x4C);
12070   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12071   ins_pipe(pipe_cmov_reg);
12072 %}
12073 
12074 
12075 instruct maxI_rReg(rRegI dst, rRegI src)
12076 %{
12077   match(Set dst (MaxI dst src));
12078 
12079   ins_cost(200);
12080   expand %{
12081     rFlagsReg cr;
12082     compI_rReg(cr, dst, src);
12083     cmovI_reg_l(dst, src, cr);
12084   %}
12085 %}
12086 
12087 // ============================================================================
12088 // Branch Instructions
12089 
12090 // Jump Direct - Label defines a relative address from JMP+1
12091 instruct jmpDir(label labl)
12092 %{
12093   match(Goto);
12094   effect(USE labl);
12095 
12096   ins_cost(300);
12097   format %{ "jmp     $labl" %}
12098   size(5);
12099   ins_encode %{
12100     Label* L = $labl$$label;
12101     __ jmp(*L, false); // Always long jump
12102   %}
12103   ins_pipe(pipe_jmp);
12104 %}
12105 
12106 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12107 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12108 %{
12109   match(If cop cr);
12110   effect(USE labl);
12111 
12112   ins_cost(300);
12113   format %{ "j$cop     $labl" %}
12114   size(6);
12115   ins_encode %{
12116     Label* L = $labl$$label;
12117     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12118   %}
12119   ins_pipe(pipe_jcc);
12120 %}
12121 
12122 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12123 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12124 %{
12125   predicate(!n->has_vector_mask_set());
12126   match(CountedLoopEnd cop cr);
12127   effect(USE labl);
12128 
12129   ins_cost(300);
12130   format %{ "j$cop     $labl\t# loop end" %}
12131   size(6);
12132   ins_encode %{
12133     Label* L = $labl$$label;
12134     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12135   %}
12136   ins_pipe(pipe_jcc);
12137 %}
12138 
12139 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12140 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12141   predicate(!n->has_vector_mask_set());
12142   match(CountedLoopEnd cop cmp);
12143   effect(USE labl);
12144 
12145   ins_cost(300);
12146   format %{ "j$cop,u   $labl\t# loop end" %}
12147   size(6);
12148   ins_encode %{
12149     Label* L = $labl$$label;
12150     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12151   %}
12152   ins_pipe(pipe_jcc);
12153 %}
12154 
12155 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12156   predicate(!n->has_vector_mask_set());
12157   match(CountedLoopEnd cop cmp);
12158   effect(USE labl);
12159 
12160   ins_cost(200);
12161   format %{ "j$cop,u   $labl\t# loop end" %}
12162   size(6);
12163   ins_encode %{
12164     Label* L = $labl$$label;
12165     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12166   %}
12167   ins_pipe(pipe_jcc);
12168 %}
12169 
12170 // mask version
12171 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12172 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
12173 %{
12174   predicate(n->has_vector_mask_set());
12175   match(CountedLoopEnd cop cr);
12176   effect(USE labl);
12177 
12178   ins_cost(400);
12179   format %{ "j$cop     $labl\t# loop end\n\t"
12180             "restorevectmask \t# vector mask restore for loops" %}
12181   size(10);
12182   ins_encode %{
12183     Label* L = $labl$$label;
12184     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12185     __ restorevectmask();
12186   %}
12187   ins_pipe(pipe_jcc);
12188 %}
12189 
12190 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12191 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12192   predicate(n->has_vector_mask_set());
12193   match(CountedLoopEnd cop cmp);
12194   effect(USE labl);
12195 
12196   ins_cost(400);
12197   format %{ "j$cop,u   $labl\t# loop end\n\t"
12198             "restorevectmask \t# vector mask restore for loops" %}
12199   size(10);
12200   ins_encode %{
12201     Label* L = $labl$$label;
12202     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12203     __ restorevectmask();
12204   %}
12205   ins_pipe(pipe_jcc);
12206 %}
12207 
12208 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12209   predicate(n->has_vector_mask_set());
12210   match(CountedLoopEnd cop cmp);
12211   effect(USE labl);
12212 
12213   ins_cost(300);
12214   format %{ "j$cop,u   $labl\t# loop end\n\t"
12215             "restorevectmask \t# vector mask restore for loops" %}
12216   size(10);
12217   ins_encode %{
12218     Label* L = $labl$$label;
12219     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12220     __ restorevectmask();
12221   %}
12222   ins_pipe(pipe_jcc);
12223 %}
12224 
12225 // Jump Direct Conditional - using unsigned comparison
12226 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12227   match(If cop cmp);
12228   effect(USE labl);
12229 
12230   ins_cost(300);
12231   format %{ "j$cop,u   $labl" %}
12232   size(6);
12233   ins_encode %{
12234     Label* L = $labl$$label;
12235     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12236   %}
12237   ins_pipe(pipe_jcc);
12238 %}
12239 
12240 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12241   match(If cop cmp);
12242   effect(USE labl);
12243 
12244   ins_cost(200);
12245   format %{ "j$cop,u   $labl" %}
12246   size(6);
12247   ins_encode %{
12248     Label* L = $labl$$label;
12249     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12250   %}
12251   ins_pipe(pipe_jcc);
12252 %}
12253 
12254 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12255   match(If cop cmp);
12256   effect(USE labl);
12257 
12258   ins_cost(200);
12259   format %{ $$template
12260     if ($cop$$cmpcode == Assembler::notEqual) {
12261       $$emit$$"jp,u    $labl\n\t"
12262       $$emit$$"j$cop,u   $labl"
12263     } else {
12264       $$emit$$"jp,u    done\n\t"
12265       $$emit$$"j$cop,u   $labl\n\t"
12266       $$emit$$"done:"
12267     }
12268   %}
12269   ins_encode %{
12270     Label* l = $labl$$label;
12271     if ($cop$$cmpcode == Assembler::notEqual) {
12272       __ jcc(Assembler::parity, *l, false);
12273       __ jcc(Assembler::notEqual, *l, false);
12274     } else if ($cop$$cmpcode == Assembler::equal) {
12275       Label done;
12276       __ jccb(Assembler::parity, done);
12277       __ jcc(Assembler::equal, *l, false);
12278       __ bind(done);
12279     } else {
12280        ShouldNotReachHere();
12281     }
12282   %}
12283   ins_pipe(pipe_jcc);
12284 %}
12285 
12286 // ============================================================================
12287 // The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary
12288 // superklass array for an instance of the superklass.  Set a hidden
12289 // internal cache on a hit (cache is checked with exposed code in
12290 // gen_subtype_check()).  Return NZ for a miss or zero for a hit.  The
12291 // encoding ALSO sets flags.
12292 
12293 instruct partialSubtypeCheck(rdi_RegP result,
12294                              rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12295                              rFlagsReg cr)
12296 %{
12297   match(Set result (PartialSubtypeCheck sub super));
12298   effect(KILL rcx, KILL cr);
12299 
12300   ins_cost(1100);  // slightly larger than the next version
12301   format %{ "movq    rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12302             "movl    rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12303             "addq    rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12304             "repne   scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12305             "jne,s   miss\t\t# Missed: rdi not-zero\n\t"
12306             "movq    [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12307             "xorq    $result, $result\t\t Hit: rdi zero\n\t"
12308     "miss:\t" %}
12309 
12310   opcode(0x1); // Force a XOR of RDI
12311   ins_encode(enc_PartialSubtypeCheck());
12312   ins_pipe(pipe_slow);
12313 %}
12314 
12315 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12316                                      rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12317                                      immP0 zero,
12318                                      rdi_RegP result)
12319 %{
12320   match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12321   effect(KILL rcx, KILL result);
12322 
12323   ins_cost(1000);
12324   format %{ "movq    rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12325             "movl    rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12326             "addq    rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12327             "repne   scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12328             "jne,s   miss\t\t# Missed: flags nz\n\t"
12329             "movq    [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12330     "miss:\t" %}
12331 
12332   opcode(0x0); // No need to XOR RDI
12333   ins_encode(enc_PartialSubtypeCheck());
12334   ins_pipe(pipe_slow);
12335 %}
12336 
12337 // ============================================================================
12338 // Branch Instructions -- short offset versions
12339 //
12340 // These instructions are used to replace jumps of a long offset (the default
12341 // match) with jumps of a shorter offset.  These instructions are all tagged
12342 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12343 // match rules in general matching.  Instead, the ADLC generates a conversion
12344 // method in the MachNode which can be used to do in-place replacement of the
12345 // long variant with the shorter variant.  The compiler will determine if a
12346 // branch can be taken by the is_short_branch_offset() predicate in the machine
12347 // specific code section of the file.
12348 
12349 // Jump Direct - Label defines a relative address from JMP+1
12350 instruct jmpDir_short(label labl) %{
12351   match(Goto);
12352   effect(USE labl);
12353 
12354   ins_cost(300);
12355   format %{ "jmp,s   $labl" %}
12356   size(2);
12357   ins_encode %{
12358     Label* L = $labl$$label;
12359     __ jmpb(*L);
12360   %}
12361   ins_pipe(pipe_jmp);
12362   ins_short_branch(1);
12363 %}
12364 
12365 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12366 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12367   match(If cop cr);
12368   effect(USE labl);
12369 
12370   ins_cost(300);
12371   format %{ "j$cop,s   $labl" %}
12372   size(2);
12373   ins_encode %{
12374     Label* L = $labl$$label;
12375     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12376   %}
12377   ins_pipe(pipe_jcc);
12378   ins_short_branch(1);
12379 %}
12380 
12381 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12382 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12383   match(CountedLoopEnd cop cr);
12384   effect(USE labl);
12385 
12386   ins_cost(300);
12387   format %{ "j$cop,s   $labl\t# loop end" %}
12388   size(2);
12389   ins_encode %{
12390     Label* L = $labl$$label;
12391     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12392   %}
12393   ins_pipe(pipe_jcc);
12394   ins_short_branch(1);
12395 %}
12396 
12397 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12398 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12399   match(CountedLoopEnd cop cmp);
12400   effect(USE labl);
12401 
12402   ins_cost(300);
12403   format %{ "j$cop,us  $labl\t# loop end" %}
12404   size(2);
12405   ins_encode %{
12406     Label* L = $labl$$label;
12407     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12408   %}
12409   ins_pipe(pipe_jcc);
12410   ins_short_branch(1);
12411 %}
12412 
12413 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12414   match(CountedLoopEnd cop cmp);
12415   effect(USE labl);
12416 
12417   ins_cost(300);
12418   format %{ "j$cop,us  $labl\t# loop end" %}
12419   size(2);
12420   ins_encode %{
12421     Label* L = $labl$$label;
12422     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12423   %}
12424   ins_pipe(pipe_jcc);
12425   ins_short_branch(1);
12426 %}
12427 
12428 // Jump Direct Conditional - using unsigned comparison
12429 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12430   match(If cop cmp);
12431   effect(USE labl);
12432 
12433   ins_cost(300);
12434   format %{ "j$cop,us  $labl" %}
12435   size(2);
12436   ins_encode %{
12437     Label* L = $labl$$label;
12438     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12439   %}
12440   ins_pipe(pipe_jcc);
12441   ins_short_branch(1);
12442 %}
12443 
12444 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12445   match(If cop cmp);
12446   effect(USE labl);
12447 
12448   ins_cost(300);
12449   format %{ "j$cop,us  $labl" %}
12450   size(2);
12451   ins_encode %{
12452     Label* L = $labl$$label;
12453     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12454   %}
12455   ins_pipe(pipe_jcc);
12456   ins_short_branch(1);
12457 %}
12458 
12459 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12460   match(If cop cmp);
12461   effect(USE labl);
12462 
12463   ins_cost(300);
12464   format %{ $$template
12465     if ($cop$$cmpcode == Assembler::notEqual) {
12466       $$emit$$"jp,u,s  $labl\n\t"
12467       $$emit$$"j$cop,u,s  $labl"
12468     } else {
12469       $$emit$$"jp,u,s  done\n\t"
12470       $$emit$$"j$cop,u,s  $labl\n\t"
12471       $$emit$$"done:"
12472     }
12473   %}
12474   size(4);
12475   ins_encode %{
12476     Label* l = $labl$$label;
12477     if ($cop$$cmpcode == Assembler::notEqual) {
12478       __ jccb(Assembler::parity, *l);
12479       __ jccb(Assembler::notEqual, *l);
12480     } else if ($cop$$cmpcode == Assembler::equal) {
12481       Label done;
12482       __ jccb(Assembler::parity, done);
12483       __ jccb(Assembler::equal, *l);
12484       __ bind(done);
12485     } else {
12486        ShouldNotReachHere();
12487     }
12488   %}
12489   ins_pipe(pipe_jcc);
12490   ins_short_branch(1);
12491 %}
12492 
12493 // ============================================================================
12494 // inlined locking and unlocking
12495 
12496 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12497   predicate(Compile::current()->use_rtm());
12498   match(Set cr (FastLock object box));
12499   effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12500   ins_cost(300);
12501   format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12502   ins_encode %{
12503     __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12504                  $scr$$Register, $cx1$$Register, $cx2$$Register,
12505                  _counters, _rtm_counters, _stack_rtm_counters,
12506                  ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12507                  true, ra_->C->profile_rtm());
12508   %}
12509   ins_pipe(pipe_slow);
12510 %}
12511 
12512 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr, rRegP cx1) %{
12513   predicate(!Compile::current()->use_rtm());
12514   match(Set cr (FastLock object box));
12515   effect(TEMP tmp, TEMP scr, TEMP cx1, USE_KILL box);
12516   ins_cost(300);
12517   format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12518   ins_encode %{
12519     __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12520                  $scr$$Register, $cx1$$Register, noreg, _counters, NULL, NULL, NULL, false, false);
12521   %}
12522   ins_pipe(pipe_slow);
12523 %}
12524 
12525 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12526   match(Set cr (FastUnlock object box));
12527   effect(TEMP tmp, USE_KILL box);
12528   ins_cost(300);
12529   format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12530   ins_encode %{
12531     __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12532   %}
12533   ins_pipe(pipe_slow);
12534 %}
12535 
12536 
12537 // ============================================================================
12538 // Safepoint Instructions
12539 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12540 %{
12541   match(SafePoint poll);
12542   effect(KILL cr, USE poll);
12543 
12544   format %{ "testl   rax, [$poll]\t"
12545             "# Safepoint: poll for GC" %}
12546   ins_cost(125);
12547   size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12548   ins_encode %{
12549     __ relocate(relocInfo::poll_type);
12550     address pre_pc = __ pc();
12551     __ testl(rax, Address($poll$$Register, 0));
12552     assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
12553   %}
12554   ins_pipe(ialu_reg_mem);
12555 %}
12556 
12557 // ============================================================================
12558 // Procedure Call/Return Instructions
12559 // Call Java Static Instruction
12560 // Note: If this code changes, the corresponding ret_addr_offset() and
12561 //       compute_padding() functions will have to be adjusted.
12562 instruct CallStaticJavaDirect(method meth) %{
12563   match(CallStaticJava);
12564   effect(USE meth);
12565 
12566   ins_cost(300);
12567   format %{ "call,static " %}
12568   opcode(0xE8); /* E8 cd */
12569   ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12570   ins_pipe(pipe_slow);
12571   ins_alignment(4);
12572 %}
12573 
12574 // Call Java Dynamic Instruction
12575 // Note: If this code changes, the corresponding ret_addr_offset() and
12576 //       compute_padding() functions will have to be adjusted.
12577 instruct CallDynamicJavaDirect(method meth)
12578 %{
12579   match(CallDynamicJava);
12580   effect(USE meth);
12581 
12582   ins_cost(300);
12583   format %{ "movq    rax, #Universe::non_oop_word()\n\t"
12584             "call,dynamic " %}
12585   ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12586   ins_pipe(pipe_slow);
12587   ins_alignment(4);
12588 %}
12589 
12590 // Call Runtime Instruction
12591 instruct CallRuntimeDirect(method meth)
12592 %{
12593   match(CallRuntime);
12594   effect(USE meth);
12595 
12596   ins_cost(300);
12597   format %{ "call,runtime " %}
12598   ins_encode(clear_avx, Java_To_Runtime(meth));
12599   ins_pipe(pipe_slow);
12600 %}
12601 
12602 // Call runtime without safepoint
12603 instruct CallLeafDirect(method meth)
12604 %{
12605   match(CallLeaf);
12606   effect(USE meth);
12607 
12608   ins_cost(300);
12609   format %{ "call_leaf,runtime " %}
12610   ins_encode(clear_avx, Java_To_Runtime(meth));
12611   ins_pipe(pipe_slow);
12612 %}
12613 
12614 // Call runtime without safepoint
12615 instruct CallLeafNoFPDirect(method meth)
12616 %{
12617   match(CallLeafNoFP);
12618   effect(USE meth);
12619 
12620   ins_cost(300);
12621   format %{ "call_leaf_nofp,runtime " %}
12622   ins_encode(clear_avx, Java_To_Runtime(meth));
12623   ins_pipe(pipe_slow);
12624 %}
12625 
12626 // Return Instruction
12627 // Remove the return address & jump to it.
12628 // Notice: We always emit a nop after a ret to make sure there is room
12629 // for safepoint patching
12630 instruct Ret()
12631 %{
12632   match(Return);
12633 
12634   format %{ "ret" %}
12635   opcode(0xC3);
12636   ins_encode(OpcP);
12637   ins_pipe(pipe_jmp);
12638 %}
12639 
12640 // Tail Call; Jump from runtime stub to Java code.
12641 // Also known as an 'interprocedural jump'.
12642 // Target of jump will eventually return to caller.
12643 // TailJump below removes the return address.
12644 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12645 %{
12646   match(TailCall jump_target method_oop);
12647 
12648   ins_cost(300);
12649   format %{ "jmp     $jump_target\t# rbx holds method oop" %}
12650   opcode(0xFF, 0x4); /* Opcode FF /4 */
12651   ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12652   ins_pipe(pipe_jmp);
12653 %}
12654 
12655 // Tail Jump; remove the return address; jump to target.
12656 // TailCall above leaves the return address around.
12657 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12658 %{
12659   match(TailJump jump_target ex_oop);
12660 
12661   ins_cost(300);
12662   format %{ "popq    rdx\t# pop return address\n\t"
12663             "jmp     $jump_target" %}
12664   opcode(0xFF, 0x4); /* Opcode FF /4 */
12665   ins_encode(Opcode(0x5a), // popq rdx
12666              REX_reg(jump_target), OpcP, reg_opc(jump_target));
12667   ins_pipe(pipe_jmp);
12668 %}
12669 
12670 // Create exception oop: created by stack-crawling runtime code.
12671 // Created exception is now available to this handler, and is setup
12672 // just prior to jumping to this handler.  No code emitted.
12673 instruct CreateException(rax_RegP ex_oop)
12674 %{
12675   match(Set ex_oop (CreateEx));
12676 
12677   size(0);
12678   // use the following format syntax
12679   format %{ "# exception oop is in rax; no code emitted" %}
12680   ins_encode();
12681   ins_pipe(empty);
12682 %}
12683 
12684 // Rethrow exception:
12685 // The exception oop will come in the first argument position.
12686 // Then JUMP (not call) to the rethrow stub code.
12687 instruct RethrowException()
12688 %{
12689   match(Rethrow);
12690 
12691   // use the following format syntax
12692   format %{ "jmp     rethrow_stub" %}
12693   ins_encode(enc_rethrow);
12694   ins_pipe(pipe_jmp);
12695 %}
12696 
12697 // ============================================================================
12698 // This name is KNOWN by the ADLC and cannot be changed.
12699 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12700 // for this guy.
12701 instruct tlsLoadP(r15_RegP dst) %{
12702   match(Set dst (ThreadLocal));
12703   effect(DEF dst);
12704 
12705   size(0);
12706   format %{ "# TLS is in R15" %}
12707   ins_encode( /*empty encoding*/ );
12708   ins_pipe(ialu_reg_reg);
12709 %}
12710 
12711 
12712 //----------PEEPHOLE RULES-----------------------------------------------------
12713 // These must follow all instruction definitions as they use the names
12714 // defined in the instructions definitions.
12715 //
12716 // peepmatch ( root_instr_name [preceding_instruction]* );
12717 //
12718 // peepconstraint %{
12719 // (instruction_number.operand_name relational_op instruction_number.operand_name
12720 //  [, ...] );
12721 // // instruction numbers are zero-based using left to right order in peepmatch
12722 //
12723 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
12724 // // provide an instruction_number.operand_name for each operand that appears
12725 // // in the replacement instruction's match rule
12726 //
12727 // ---------VM FLAGS---------------------------------------------------------
12728 //
12729 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12730 //
12731 // Each peephole rule is given an identifying number starting with zero and
12732 // increasing by one in the order seen by the parser.  An individual peephole
12733 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12734 // on the command-line.
12735 //
12736 // ---------CURRENT LIMITATIONS----------------------------------------------
12737 //
12738 // Only match adjacent instructions in same basic block
12739 // Only equality constraints
12740 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12741 // Only one replacement instruction
12742 //
12743 // ---------EXAMPLE----------------------------------------------------------
12744 //
12745 // // pertinent parts of existing instructions in architecture description
12746 // instruct movI(rRegI dst, rRegI src)
12747 // %{
12748 //   match(Set dst (CopyI src));
12749 // %}
12750 //
12751 // instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
12752 // %{
12753 //   match(Set dst (AddI dst src));
12754 //   effect(KILL cr);
12755 // %}
12756 //
12757 // // Change (inc mov) to lea
12758 // peephole %{
12759 //   // increment preceeded by register-register move
12760 //   peepmatch ( incI_rReg movI );
12761 //   // require that the destination register of the increment
12762 //   // match the destination register of the move
12763 //   peepconstraint ( 0.dst == 1.dst );
12764 //   // construct a replacement instruction that sets
12765 //   // the destination to ( move's source register + one )
12766 //   peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12767 // %}
12768 //
12769 
12770 // Implementation no longer uses movX instructions since
12771 // machine-independent system no longer uses CopyX nodes.
12772 //
12773 // peephole
12774 // %{
12775 //   peepmatch (incI_rReg movI);
12776 //   peepconstraint (0.dst == 1.dst);
12777 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12778 // %}
12779 
12780 // peephole
12781 // %{
12782 //   peepmatch (decI_rReg movI);
12783 //   peepconstraint (0.dst == 1.dst);
12784 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12785 // %}
12786 
12787 // peephole
12788 // %{
12789 //   peepmatch (addI_rReg_imm movI);
12790 //   peepconstraint (0.dst == 1.dst);
12791 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12792 // %}
12793 
12794 // peephole
12795 // %{
12796 //   peepmatch (incL_rReg movL);
12797 //   peepconstraint (0.dst == 1.dst);
12798 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12799 // %}
12800 
12801 // peephole
12802 // %{
12803 //   peepmatch (decL_rReg movL);
12804 //   peepconstraint (0.dst == 1.dst);
12805 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12806 // %}
12807 
12808 // peephole
12809 // %{
12810 //   peepmatch (addL_rReg_imm movL);
12811 //   peepconstraint (0.dst == 1.dst);
12812 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12813 // %}
12814 
12815 // peephole
12816 // %{
12817 //   peepmatch (addP_rReg_imm movP);
12818 //   peepconstraint (0.dst == 1.dst);
12819 //   peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12820 // %}
12821 
12822 // // Change load of spilled value to only a spill
12823 // instruct storeI(memory mem, rRegI src)
12824 // %{
12825 //   match(Set mem (StoreI mem src));
12826 // %}
12827 //
12828 // instruct loadI(rRegI dst, memory mem)
12829 // %{
12830 //   match(Set dst (LoadI mem));
12831 // %}
12832 //
12833 
12834 peephole
12835 %{
12836   peepmatch (loadI storeI);
12837   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12838   peepreplace (storeI(1.mem 1.mem 1.src));
12839 %}
12840 
12841 peephole
12842 %{
12843   peepmatch (loadL storeL);
12844   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12845   peepreplace (storeL(1.mem 1.mem 1.src));
12846 %}
12847 
12848 //----------SMARTSPILL RULES---------------------------------------------------
12849 // These must follow all instruction definitions as they use the names
12850 // defined in the instructions definitions.