1 /*
2 * Copyright 2000-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 # include "incls/_precompiled.incl"
26 # include "incls/_c1_LIRAssembler_sparc.cpp.incl"
27
28 #define __ _masm->
29
30
31 //------------------------------------------------------------
32
33
34 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
35 if (opr->is_constant()) {
36 LIR_Const* constant = opr->as_constant_ptr();
37 switch (constant->type()) {
38 case T_INT: {
39 jint value = constant->as_jint();
40 return Assembler::is_simm13(value);
41 }
42
43 default:
44 return false;
45 }
46 }
47 return false;
48 }
49
50
51 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
52 switch (op->code()) {
53 case lir_null_check:
54 return true;
55
56
57 case lir_add:
58 case lir_ushr:
59 case lir_shr:
60 case lir_shl:
61 // integer shifts and adds are always one instruction
62 return op->result_opr()->is_single_cpu();
63
64
65 case lir_move: {
66 LIR_Op1* op1 = op->as_Op1();
67 LIR_Opr src = op1->in_opr();
68 LIR_Opr dst = op1->result_opr();
69
70 if (src == dst) {
71 NEEDS_CLEANUP;
72 // this works around a problem where moves with the same src and dst
73 // end up in the delay slot and then the assembler swallows the mov
74 // since it has no effect and then it complains because the delay slot
75 // is empty. returning false stops the optimizer from putting this in
76 // the delay slot
77 return false;
78 }
79
80 // don't put moves involving oops into the delay slot since the VerifyOops code
81 // will make it much larger than a single instruction.
82 if (VerifyOops) {
83 return false;
84 }
85
86 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
87 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
88 return false;
89 }
90
91 if (dst->is_register()) {
92 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
93 return !PatchALot;
94 } else if (src->is_single_stack()) {
95 return true;
96 }
97 }
98
99 if (src->is_register()) {
100 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
101 return !PatchALot;
102 } else if (dst->is_single_stack()) {
103 return true;
104 }
105 }
106
107 if (dst->is_register() &&
108 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
109 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
110 return true;
111 }
112
113 return false;
114 }
115
116 default:
117 return false;
118 }
119 ShouldNotReachHere();
120 }
121
122
123 LIR_Opr LIR_Assembler::receiverOpr() {
124 return FrameMap::O0_oop_opr;
125 }
126
127
128 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
129 return FrameMap::I0_oop_opr;
130 }
131
132
133 LIR_Opr LIR_Assembler::osrBufferPointer() {
134 return FrameMap::I0_opr;
135 }
136
137
138 int LIR_Assembler::initial_frame_size_in_bytes() {
139 return in_bytes(frame_map()->framesize_in_bytes());
140 }
141
142
143 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
144 // we fetch the class of the receiver (O0) and compare it with the cached class.
145 // If they do not match we jump to slow case.
146 int LIR_Assembler::check_icache() {
147 int offset = __ offset();
148 __ inline_cache_check(O0, G5_inline_cache_reg);
149 return offset;
150 }
151
152
153 void LIR_Assembler::osr_entry() {
154 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
155 //
156 // 1. Create a new compiled activation.
157 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
158 // at the osr_bci; it is not initialized.
159 // 3. Jump to the continuation address in compiled code to resume execution.
160
161 // OSR entry point
162 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
163 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
164 ValueStack* entry_state = osr_entry->end()->state();
165 int number_of_locks = entry_state->locks_size();
166
167 // Create a frame for the compiled activation.
168 __ build_frame(initial_frame_size_in_bytes());
169
170 // OSR buffer is
171 //
172 // locals[nlocals-1..0]
173 // monitors[number_of_locks-1..0]
174 //
175 // locals is a direct copy of the interpreter frame so in the osr buffer
176 // so first slot in the local array is the last local from the interpreter
177 // and last slot is local[0] (receiver) from the interpreter
178 //
179 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
180 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
181 // in the interpreter frame (the method lock if a sync method)
182
183 // Initialize monitors in the compiled activation.
184 // I0: pointer to osr buffer
185 //
186 // All other registers are dead at this point and the locals will be
187 // copied into place by code emitted in the IR.
188
189 Register OSR_buf = osrBufferPointer()->as_register();
190 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
191 int monitor_offset = BytesPerWord * method()->max_locals() +
192 (2 * BytesPerWord) * (number_of_locks - 1);
193 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
194 // the OSR buffer using 2 word entries: first the lock and then
195 // the oop.
196 for (int i = 0; i < number_of_locks; i++) {
197 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
198 #ifdef ASSERT
199 // verify the interpreter's monitor has a non-null object
200 {
201 Label L;
202 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
203 __ cmp(G0, O7);
204 __ br(Assembler::notEqual, false, Assembler::pt, L);
205 __ delayed()->nop();
206 __ stop("locked object is NULL");
207 __ bind(L);
208 }
209 #endif // ASSERT
210 // Copy the lock field into the compiled activation.
211 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
212 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
213 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
214 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
215 }
216 }
217 }
218
219
220 // Optimized Library calls
221 // This is the fast version of java.lang.String.compare; it has not
222 // OSR-entry and therefore, we generate a slow version for OSR's
223 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {
224 Register str0 = left->as_register();
225 Register str1 = right->as_register();
226
227 Label Ldone;
228
229 Register result = dst->as_register();
230 {
231 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0
232 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1
233 // Also, get string0.count-string1.count in o7 and get the condition code set
234 // Note: some instructions have been hoisted for better instruction scheduling
235
236 Register tmp0 = L0;
237 Register tmp1 = L1;
238 Register tmp2 = L2;
239
240 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array
241 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
242 int count_offset = java_lang_String:: count_offset_in_bytes();
243
244 __ ld_ptr(str0, value_offset, tmp0);
245 __ ld(str0, offset_offset, tmp2);
246 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
247 __ ld(str0, count_offset, str0);
248 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
249
250 // str1 may be null
251 add_debug_info_for_null_check_here(info);
252
253 __ ld_ptr(str1, value_offset, tmp1);
254 __ add(tmp0, tmp2, tmp0);
255
256 __ ld(str1, offset_offset, tmp2);
257 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
258 __ ld(str1, count_offset, str1);
259 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
260 __ subcc(str0, str1, O7);
261 __ add(tmp1, tmp2, tmp1);
262 }
263
264 {
265 // Compute the minimum of the string lengths, scale it and store it in limit
266 Register count0 = I0;
267 Register count1 = I1;
268 Register limit = L3;
269
270 Label Lskip;
271 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter
272 __ br(Assembler::greater, true, Assembler::pt, Lskip);
273 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter
274 __ bind(Lskip);
275
276 // If either string is empty (or both of them) the result is the difference in lengths
277 __ cmp(limit, 0);
278 __ br(Assembler::equal, true, Assembler::pn, Ldone);
279 __ delayed()->mov(O7, result); // result is difference in lengths
280 }
281
282 {
283 // Neither string is empty
284 Label Lloop;
285
286 Register base0 = L0;
287 Register base1 = L1;
288 Register chr0 = I0;
289 Register chr1 = I1;
290 Register limit = L3;
291
292 // Shift base0 and base1 to the end of the arrays, negate limit
293 __ add(base0, limit, base0);
294 __ add(base1, limit, base1);
295 __ neg(limit); // limit = -min{string0.count, strin1.count}
296
297 __ lduh(base0, limit, chr0);
298 __ bind(Lloop);
299 __ lduh(base1, limit, chr1);
300 __ subcc(chr0, chr1, chr0);
301 __ br(Assembler::notZero, false, Assembler::pn, Ldone);
302 assert(chr0 == result, "result must be pre-placed");
303 __ delayed()->inccc(limit, sizeof(jchar));
304 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
305 __ delayed()->lduh(base0, limit, chr0);
306 }
307
308 // If strings are equal up to min length, return the length difference.
309 __ mov(O7, result);
310
311 // Otherwise, return the difference between the first mismatched chars.
312 __ bind(Ldone);
313 }
314
315
316 // --------------------------------------------------------------------------------------------
317
318 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
319 if (!GenerateSynchronizationCode) return;
320
321 Register obj_reg = obj_opr->as_register();
322 Register lock_reg = lock_opr->as_register();
323
324 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
325 Register reg = mon_addr.base();
326 int offset = mon_addr.disp();
327 // compute pointer to BasicLock
328 if (mon_addr.is_simm13()) {
329 __ add(reg, offset, lock_reg);
330 }
331 else {
332 __ set(offset, lock_reg);
333 __ add(reg, lock_reg, lock_reg);
334 }
335 // unlock object
336 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
337 // _slow_case_stubs->append(slow_case);
338 // temporary fix: must be created after exceptionhandler, therefore as call stub
339 _slow_case_stubs->append(slow_case);
340 if (UseFastLocking) {
341 // try inlined fast unlocking first, revert to slow locking if it fails
342 // note: lock_reg points to the displaced header since the displaced header offset is 0!
343 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
344 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
345 } else {
346 // always do slow unlocking
347 // note: the slow unlocking code could be inlined here, however if we use
348 // slow unlocking, speed doesn't matter anyway and this solution is
349 // simpler and requires less duplicated code - additionally, the
350 // slow unlocking code is the same in either case which simplifies
351 // debugging
352 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
353 __ delayed()->nop();
354 }
355 // done
356 __ bind(*slow_case->continuation());
357 }
358
359
360 void LIR_Assembler::emit_exception_handler() {
361 // if the last instruction is a call (typically to do a throw which
362 // is coming at the end after block reordering) the return address
363 // must still point into the code area in order to avoid assertion
364 // failures when searching for the corresponding bci => add a nop
365 // (was bug 5/14/1999 - gri)
366 __ nop();
367
368 // generate code for exception handler
369 ciMethod* method = compilation()->method();
370
371 address handler_base = __ start_a_stub(exception_handler_size);
372
373 if (handler_base == NULL) {
374 // not enough space left for the handler
375 bailout("exception handler overflow");
376 return;
377 }
378 #ifdef ASSERT
379 int offset = code_offset();
380 #endif // ASSERT
381 compilation()->offsets()->set_value(CodeOffsets::Exceptions, code_offset());
382
383
384 if (compilation()->has_exception_handlers() || compilation()->env()->jvmti_can_post_on_exceptions()) {
385 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
386 __ delayed()->nop();
387 }
388
389 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
390 __ delayed()->nop();
391 debug_only(__ stop("should have gone to the caller");)
392 assert(code_offset() - offset <= exception_handler_size, "overflow");
393
394 __ end_a_stub();
395 }
396
397 void LIR_Assembler::emit_deopt_handler() {
398 // if the last instruction is a call (typically to do a throw which
399 // is coming at the end after block reordering) the return address
400 // must still point into the code area in order to avoid assertion
401 // failures when searching for the corresponding bci => add a nop
402 // (was bug 5/14/1999 - gri)
403 __ nop();
404
405 // generate code for deopt handler
406 ciMethod* method = compilation()->method();
407 address handler_base = __ start_a_stub(deopt_handler_size);
408 if (handler_base == NULL) {
409 // not enough space left for the handler
410 bailout("deopt handler overflow");
411 return;
412 }
413 #ifdef ASSERT
414 int offset = code_offset();
415 #endif // ASSERT
416 compilation()->offsets()->set_value(CodeOffsets::Deopt, code_offset());
417
418 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
419
420 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
421 __ delayed()->nop();
422
423 assert(code_offset() - offset <= deopt_handler_size, "overflow");
424
425 debug_only(__ stop("should have gone to the caller");)
426
427 __ end_a_stub();
428 }
429
430
431 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
432 if (o == NULL) {
433 __ set(NULL_WORD, reg);
434 } else {
435 int oop_index = __ oop_recorder()->find_index(o);
436 RelocationHolder rspec = oop_Relocation::spec(oop_index);
437 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
438 }
439 }
440
441
442 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
443 // Allocate a new index in oop table to hold the oop once it's been patched
444 int oop_index = __ oop_recorder()->allocate_index((jobject)NULL);
445 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index);
446
447 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
448 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
449 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
450 // NULL will be dynamically patched later and the patched value may be large. We must
451 // therefore generate the sethi/add as a placeholders
452 __ patchable_set(addrlit, reg);
453
454 patching_epilog(patch, lir_patch_normal, reg, info);
455 }
456
457
458 void LIR_Assembler::emit_op3(LIR_Op3* op) {
459 Register Rdividend = op->in_opr1()->as_register();
460 Register Rdivisor = noreg;
461 Register Rscratch = op->in_opr3()->as_register();
462 Register Rresult = op->result_opr()->as_register();
463 int divisor = -1;
464
465 if (op->in_opr2()->is_register()) {
466 Rdivisor = op->in_opr2()->as_register();
467 } else {
468 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
469 assert(Assembler::is_simm13(divisor), "can only handle simm13");
470 }
471
472 assert(Rdividend != Rscratch, "");
473 assert(Rdivisor != Rscratch, "");
474 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
475
476 if (Rdivisor == noreg && is_power_of_2(divisor)) {
477 // convert division by a power of two into some shifts and logical operations
478 if (op->code() == lir_idiv) {
479 if (divisor == 2) {
480 __ srl(Rdividend, 31, Rscratch);
481 } else {
482 __ sra(Rdividend, 31, Rscratch);
483 __ and3(Rscratch, divisor - 1, Rscratch);
484 }
485 __ add(Rdividend, Rscratch, Rscratch);
486 __ sra(Rscratch, log2_intptr(divisor), Rresult);
487 return;
488 } else {
489 if (divisor == 2) {
490 __ srl(Rdividend, 31, Rscratch);
491 } else {
492 __ sra(Rdividend, 31, Rscratch);
493 __ and3(Rscratch, divisor - 1,Rscratch);
494 }
495 __ add(Rdividend, Rscratch, Rscratch);
496 __ andn(Rscratch, divisor - 1,Rscratch);
497 __ sub(Rdividend, Rscratch, Rresult);
498 return;
499 }
500 }
501
502 __ sra(Rdividend, 31, Rscratch);
503 __ wry(Rscratch);
504 if (!VM_Version::v9_instructions_work()) {
505 // v9 doesn't require these nops
506 __ nop();
507 __ nop();
508 __ nop();
509 __ nop();
510 }
511
512 add_debug_info_for_div0_here(op->info());
513
514 if (Rdivisor != noreg) {
515 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
516 } else {
517 assert(Assembler::is_simm13(divisor), "can only handle simm13");
518 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
519 }
520
521 Label skip;
522 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
523 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
524 __ bind(skip);
525
526 if (op->code() == lir_irem) {
527 if (Rdivisor != noreg) {
528 __ smul(Rscratch, Rdivisor, Rscratch);
529 } else {
530 __ smul(Rscratch, divisor, Rscratch);
531 }
532 __ sub(Rdividend, Rscratch, Rresult);
533 }
534 }
535
536
537 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
538 #ifdef ASSERT
539 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
540 if (op->block() != NULL) _branch_target_blocks.append(op->block());
541 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
542 #endif
543 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
544
545 if (op->cond() == lir_cond_always) {
546 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
547 } else if (op->code() == lir_cond_float_branch) {
548 assert(op->ublock() != NULL, "must have unordered successor");
549 bool is_unordered = (op->ublock() == op->block());
550 Assembler::Condition acond;
551 switch (op->cond()) {
552 case lir_cond_equal: acond = Assembler::f_equal; break;
553 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
554 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
555 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
556 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
557 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
558 default : ShouldNotReachHere();
559 };
560
561 if (!VM_Version::v9_instructions_work()) {
562 __ nop();
563 }
564 __ fb( acond, false, Assembler::pn, *(op->label()));
565 } else {
566 assert (op->code() == lir_branch, "just checking");
567
568 Assembler::Condition acond;
569 switch (op->cond()) {
570 case lir_cond_equal: acond = Assembler::equal; break;
571 case lir_cond_notEqual: acond = Assembler::notEqual; break;
572 case lir_cond_less: acond = Assembler::less; break;
573 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
574 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
575 case lir_cond_greater: acond = Assembler::greater; break;
576 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
577 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
578 default: ShouldNotReachHere();
579 };
580
581 // sparc has different condition codes for testing 32-bit
582 // vs. 64-bit values. We could always test xcc is we could
583 // guarantee that 32-bit loads always sign extended but that isn't
584 // true and since sign extension isn't free, it would impose a
585 // slight cost.
586 #ifdef _LP64
587 if (op->type() == T_INT) {
588 __ br(acond, false, Assembler::pn, *(op->label()));
589 } else
590 #endif
591 __ brx(acond, false, Assembler::pn, *(op->label()));
592 }
593 // The peephole pass fills the delay slot
594 }
595
596
597 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
598 Bytecodes::Code code = op->bytecode();
599 LIR_Opr dst = op->result_opr();
600
601 switch(code) {
602 case Bytecodes::_i2l: {
603 Register rlo = dst->as_register_lo();
604 Register rhi = dst->as_register_hi();
605 Register rval = op->in_opr()->as_register();
606 #ifdef _LP64
607 __ sra(rval, 0, rlo);
608 #else
609 __ mov(rval, rlo);
610 __ sra(rval, BitsPerInt-1, rhi);
611 #endif
612 break;
613 }
614 case Bytecodes::_i2d:
615 case Bytecodes::_i2f: {
616 bool is_double = (code == Bytecodes::_i2d);
617 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
618 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
619 FloatRegister rsrc = op->in_opr()->as_float_reg();
620 if (rsrc != rdst) {
621 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
622 }
623 __ fitof(w, rdst, rdst);
624 break;
625 }
626 case Bytecodes::_f2i:{
627 FloatRegister rsrc = op->in_opr()->as_float_reg();
628 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
629 Label L;
630 // result must be 0 if value is NaN; test by comparing value to itself
631 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
632 if (!VM_Version::v9_instructions_work()) {
633 __ nop();
634 }
635 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
636 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
637 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
638 // move integer result from float register to int register
639 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
640 __ bind (L);
641 break;
642 }
643 case Bytecodes::_l2i: {
644 Register rlo = op->in_opr()->as_register_lo();
645 Register rhi = op->in_opr()->as_register_hi();
646 Register rdst = dst->as_register();
647 #ifdef _LP64
648 __ sra(rlo, 0, rdst);
649 #else
650 __ mov(rlo, rdst);
651 #endif
652 break;
653 }
654 case Bytecodes::_d2f:
655 case Bytecodes::_f2d: {
656 bool is_double = (code == Bytecodes::_f2d);
657 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
658 LIR_Opr val = op->in_opr();
659 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
660 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
661 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
662 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
663 __ ftof(vw, dw, rval, rdst);
664 break;
665 }
666 case Bytecodes::_i2s:
667 case Bytecodes::_i2b: {
668 Register rval = op->in_opr()->as_register();
669 Register rdst = dst->as_register();
670 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
671 __ sll (rval, shift, rdst);
672 __ sra (rdst, shift, rdst);
673 break;
674 }
675 case Bytecodes::_i2c: {
676 Register rval = op->in_opr()->as_register();
677 Register rdst = dst->as_register();
678 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
679 __ sll (rval, shift, rdst);
680 __ srl (rdst, shift, rdst);
681 break;
682 }
683
684 default: ShouldNotReachHere();
685 }
686 }
687
688
689 void LIR_Assembler::align_call(LIR_Code) {
690 // do nothing since all instructions are word aligned on sparc
691 }
692
693
694 void LIR_Assembler::call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info) {
695 __ call(entry, rtype);
696 // the peephole pass fills the delay slot
697 }
698
699
700 void LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) {
701 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
702 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
703 __ relocate(rspec);
704 __ call(entry, relocInfo::none);
705 // the peephole pass fills the delay slot
706 }
707
708
709 void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) {
710 add_debug_info_for_null_check_here(info);
711 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
712 if (__ is_simm13(vtable_offset) ) {
713 __ ld_ptr(G3_scratch, vtable_offset, G5_method);
714 } else {
715 // This will generate 2 instructions
716 __ set(vtable_offset, G5_method);
717 // ld_ptr, set_hi, set
718 __ ld_ptr(G3_scratch, G5_method, G5_method);
719 }
720 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
721 __ callr(G3_scratch, G0);
722 // the peephole pass fills the delay slot
723 }
724
725
726 // load with 32-bit displacement
727 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
728 int load_offset = code_offset();
729 if (Assembler::is_simm13(disp)) {
730 if (info != NULL) add_debug_info_for_null_check_here(info);
731 switch(ld_type) {
732 case T_BOOLEAN: // fall through
733 case T_BYTE : __ ldsb(s, disp, d); break;
734 case T_CHAR : __ lduh(s, disp, d); break;
735 case T_SHORT : __ ldsh(s, disp, d); break;
736 case T_INT : __ ld(s, disp, d); break;
737 case T_ADDRESS:// fall through
738 case T_ARRAY : // fall through
739 case T_OBJECT: __ ld_ptr(s, disp, d); break;
740 default : ShouldNotReachHere();
741 }
742 } else {
743 __ set(disp, O7);
744 if (info != NULL) add_debug_info_for_null_check_here(info);
745 load_offset = code_offset();
746 switch(ld_type) {
747 case T_BOOLEAN: // fall through
748 case T_BYTE : __ ldsb(s, O7, d); break;
749 case T_CHAR : __ lduh(s, O7, d); break;
750 case T_SHORT : __ ldsh(s, O7, d); break;
751 case T_INT : __ ld(s, O7, d); break;
752 case T_ADDRESS:// fall through
753 case T_ARRAY : // fall through
754 case T_OBJECT: __ ld_ptr(s, O7, d); break;
755 default : ShouldNotReachHere();
756 }
757 }
758 if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d);
759 return load_offset;
760 }
761
762
763 // store with 32-bit displacement
764 void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
765 if (Assembler::is_simm13(offset)) {
766 if (info != NULL) add_debug_info_for_null_check_here(info);
767 switch (type) {
768 case T_BOOLEAN: // fall through
769 case T_BYTE : __ stb(value, base, offset); break;
770 case T_CHAR : __ sth(value, base, offset); break;
771 case T_SHORT : __ sth(value, base, offset); break;
772 case T_INT : __ stw(value, base, offset); break;
773 case T_ADDRESS:// fall through
774 case T_ARRAY : // fall through
775 case T_OBJECT: __ st_ptr(value, base, offset); break;
776 default : ShouldNotReachHere();
777 }
778 } else {
779 __ set(offset, O7);
780 if (info != NULL) add_debug_info_for_null_check_here(info);
781 switch (type) {
782 case T_BOOLEAN: // fall through
783 case T_BYTE : __ stb(value, base, O7); break;
784 case T_CHAR : __ sth(value, base, O7); break;
785 case T_SHORT : __ sth(value, base, O7); break;
786 case T_INT : __ stw(value, base, O7); break;
787 case T_ADDRESS:// fall through
788 case T_ARRAY : //fall through
789 case T_OBJECT: __ st_ptr(value, base, O7); break;
790 default : ShouldNotReachHere();
791 }
792 }
793 // Note: Do the store before verification as the code might be patched!
794 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value);
795 }
796
797
798 // load float with 32-bit displacement
799 void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
800 FloatRegisterImpl::Width w;
801 switch(ld_type) {
802 case T_FLOAT : w = FloatRegisterImpl::S; break;
803 case T_DOUBLE: w = FloatRegisterImpl::D; break;
804 default : ShouldNotReachHere();
805 }
806
807 if (Assembler::is_simm13(disp)) {
808 if (info != NULL) add_debug_info_for_null_check_here(info);
809 if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) {
810 __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor());
811 __ ldf(FloatRegisterImpl::S, s, disp , d);
812 } else {
813 __ ldf(w, s, disp, d);
814 }
815 } else {
816 __ set(disp, O7);
817 if (info != NULL) add_debug_info_for_null_check_here(info);
818 __ ldf(w, s, O7, d);
819 }
820 }
821
822
823 // store float with 32-bit displacement
824 void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
825 FloatRegisterImpl::Width w;
826 switch(type) {
827 case T_FLOAT : w = FloatRegisterImpl::S; break;
828 case T_DOUBLE: w = FloatRegisterImpl::D; break;
829 default : ShouldNotReachHere();
830 }
831
832 if (Assembler::is_simm13(offset)) {
833 if (info != NULL) add_debug_info_for_null_check_here(info);
834 if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) {
835 __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord);
836 __ stf(FloatRegisterImpl::S, value , base, offset);
837 } else {
838 __ stf(w, value, base, offset);
839 }
840 } else {
841 __ set(offset, O7);
842 if (info != NULL) add_debug_info_for_null_check_here(info);
843 __ stf(w, value, O7, base);
844 }
845 }
846
847
848 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) {
849 int store_offset;
850 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
851 assert(!unaligned, "can't handle this");
852 // for offsets larger than a simm13 we setup the offset in O7
853 __ set(offset, O7);
854 store_offset = store(from_reg, base, O7, type);
855 } else {
856 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
857 store_offset = code_offset();
858 switch (type) {
859 case T_BOOLEAN: // fall through
860 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
861 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
862 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
863 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
864 case T_LONG :
865 #ifdef _LP64
866 if (unaligned || PatchALot) {
867 __ srax(from_reg->as_register_lo(), 32, O7);
868 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
869 __ stw(O7, base, offset + hi_word_offset_in_bytes);
870 } else {
871 __ stx(from_reg->as_register_lo(), base, offset);
872 }
873 #else
874 assert(Assembler::is_simm13(offset + 4), "must be");
875 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
876 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
877 #endif
878 break;
879 case T_ADDRESS:// fall through
880 case T_ARRAY : // fall through
881 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break;
882 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
883 case T_DOUBLE:
884 {
885 FloatRegister reg = from_reg->as_double_reg();
886 // split unaligned stores
887 if (unaligned || PatchALot) {
888 assert(Assembler::is_simm13(offset + 4), "must be");
889 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
890 __ stf(FloatRegisterImpl::S, reg, base, offset);
891 } else {
892 __ stf(FloatRegisterImpl::D, reg, base, offset);
893 }
894 break;
895 }
896 default : ShouldNotReachHere();
897 }
898 }
899 return store_offset;
900 }
901
902
903 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) {
904 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
905 int store_offset = code_offset();
906 switch (type) {
907 case T_BOOLEAN: // fall through
908 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
909 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
910 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
911 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
912 case T_LONG :
913 #ifdef _LP64
914 __ stx(from_reg->as_register_lo(), base, disp);
915 #else
916 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
917 __ std(from_reg->as_register_hi(), base, disp);
918 #endif
919 break;
920 case T_ADDRESS:// fall through
921 case T_ARRAY : // fall through
922 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break;
923 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
924 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
925 default : ShouldNotReachHere();
926 }
927 return store_offset;
928 }
929
930
931 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) {
932 int load_offset;
933 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
934 assert(base != O7, "destroying register");
935 assert(!unaligned, "can't handle this");
936 // for offsets larger than a simm13 we setup the offset in O7
937 __ set(offset, O7);
938 load_offset = load(base, O7, to_reg, type);
939 } else {
940 load_offset = code_offset();
941 switch(type) {
942 case T_BOOLEAN: // fall through
943 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
944 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
945 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
946 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
947 case T_LONG :
948 if (!unaligned) {
949 #ifdef _LP64
950 __ ldx(base, offset, to_reg->as_register_lo());
951 #else
952 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
953 "must be sequential");
954 __ ldd(base, offset, to_reg->as_register_hi());
955 #endif
956 } else {
957 #ifdef _LP64
958 assert(base != to_reg->as_register_lo(), "can't handle this");
959 assert(O7 != to_reg->as_register_lo(), "can't handle this");
960 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
961 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
962 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
963 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
964 #else
965 if (base == to_reg->as_register_lo()) {
966 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
967 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
968 } else {
969 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
970 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
971 }
972 #endif
973 }
974 break;
975 case T_ADDRESS:// fall through
976 case T_ARRAY : // fall through
977 case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break;
978 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
979 case T_DOUBLE:
980 {
981 FloatRegister reg = to_reg->as_double_reg();
982 // split unaligned loads
983 if (unaligned || PatchALot) {
984 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
985 __ ldf(FloatRegisterImpl::S, base, offset, reg);
986 } else {
987 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
988 }
989 break;
990 }
991 default : ShouldNotReachHere();
992 }
993 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
994 }
995 return load_offset;
996 }
997
998
999 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) {
1000 int load_offset = code_offset();
1001 switch(type) {
1002 case T_BOOLEAN: // fall through
1003 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
1004 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
1005 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
1006 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
1007 case T_ADDRESS:// fall through
1008 case T_ARRAY : // fall through
1009 case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break;
1010 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
1011 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
1012 case T_LONG :
1013 #ifdef _LP64
1014 __ ldx(base, disp, to_reg->as_register_lo());
1015 #else
1016 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1017 "must be sequential");
1018 __ ldd(base, disp, to_reg->as_register_hi());
1019 #endif
1020 break;
1021 default : ShouldNotReachHere();
1022 }
1023 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
1024 return load_offset;
1025 }
1026
1027
1028 // load/store with an Address
1029 void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1030 load(a.base(), a.disp() + offset, d, ld_type, info);
1031 }
1032
1033
1034 void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1035 store(value, dest.base(), dest.disp() + offset, type, info);
1036 }
1037
1038
1039 // loadf/storef with an Address
1040 void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1041 load(a.base(), a.disp() + offset, d, ld_type, info);
1042 }
1043
1044
1045 void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1046 store(value, dest.base(), dest.disp() + offset, type, info);
1047 }
1048
1049
1050 // load/store with an Address
1051 void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) {
1052 load(as_Address(a), d, ld_type, info);
1053 }
1054
1055
1056 void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1057 store(value, as_Address(dest), type, info);
1058 }
1059
1060
1061 // loadf/storef with an Address
1062 void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
1063 load(as_Address(a), d, ld_type, info);
1064 }
1065
1066
1067 void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1068 store(value, as_Address(dest), type, info);
1069 }
1070
1071
1072 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
1073 LIR_Const* c = src->as_constant_ptr();
1074 switch (c->type()) {
1075 case T_INT:
1076 case T_FLOAT: {
1077 Register src_reg = O7;
1078 int value = c->as_jint_bits();
1079 if (value == 0) {
1080 src_reg = G0;
1081 } else {
1082 __ set(value, O7);
1083 }
1084 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1085 __ stw(src_reg, addr.base(), addr.disp());
1086 break;
1087 }
1088 case T_OBJECT: {
1089 Register src_reg = O7;
1090 jobject2reg(c->as_jobject(), src_reg);
1091 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1092 __ st_ptr(src_reg, addr.base(), addr.disp());
1093 break;
1094 }
1095 case T_LONG:
1096 case T_DOUBLE: {
1097 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
1098
1099 Register tmp = O7;
1100 int value_lo = c->as_jint_lo_bits();
1101 if (value_lo == 0) {
1102 tmp = G0;
1103 } else {
1104 __ set(value_lo, O7);
1105 }
1106 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
1107 int value_hi = c->as_jint_hi_bits();
1108 if (value_hi == 0) {
1109 tmp = G0;
1110 } else {
1111 __ set(value_hi, O7);
1112 }
1113 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
1114 break;
1115 }
1116 default:
1117 Unimplemented();
1118 }
1119 }
1120
1121
1122 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
1123 LIR_Const* c = src->as_constant_ptr();
1124 LIR_Address* addr = dest->as_address_ptr();
1125 Register base = addr->base()->as_pointer_register();
1126
1127 if (info != NULL) {
1128 add_debug_info_for_null_check_here(info);
1129 }
1130 switch (c->type()) {
1131 case T_INT:
1132 case T_FLOAT: {
1133 LIR_Opr tmp = FrameMap::O7_opr;
1134 int value = c->as_jint_bits();
1135 if (value == 0) {
1136 tmp = FrameMap::G0_opr;
1137 } else if (Assembler::is_simm13(value)) {
1138 __ set(value, O7);
1139 }
1140 if (addr->index()->is_valid()) {
1141 assert(addr->disp() == 0, "must be zero");
1142 store(tmp, base, addr->index()->as_pointer_register(), type);
1143 } else {
1144 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1145 store(tmp, base, addr->disp(), type);
1146 }
1147 break;
1148 }
1149 case T_LONG:
1150 case T_DOUBLE: {
1151 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1152 assert(Assembler::is_simm13(addr->disp()) &&
1153 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1154
1155 Register tmp = O7;
1156 int value_lo = c->as_jint_lo_bits();
1157 if (value_lo == 0) {
1158 tmp = G0;
1159 } else {
1160 __ set(value_lo, O7);
1161 }
1162 store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT);
1163 int value_hi = c->as_jint_hi_bits();
1164 if (value_hi == 0) {
1165 tmp = G0;
1166 } else {
1167 __ set(value_hi, O7);
1168 }
1169 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT);
1170 break;
1171 }
1172 case T_OBJECT: {
1173 jobject obj = c->as_jobject();
1174 LIR_Opr tmp;
1175 if (obj == NULL) {
1176 tmp = FrameMap::G0_opr;
1177 } else {
1178 tmp = FrameMap::O7_opr;
1179 jobject2reg(c->as_jobject(), O7);
1180 }
1181 // handle either reg+reg or reg+disp address
1182 if (addr->index()->is_valid()) {
1183 assert(addr->disp() == 0, "must be zero");
1184 store(tmp, base, addr->index()->as_pointer_register(), type);
1185 } else {
1186 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1187 store(tmp, base, addr->disp(), type);
1188 }
1189
1190 break;
1191 }
1192 default:
1193 Unimplemented();
1194 }
1195 }
1196
1197
1198 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1199 LIR_Const* c = src->as_constant_ptr();
1200 LIR_Opr to_reg = dest;
1201
1202 switch (c->type()) {
1203 case T_INT:
1204 {
1205 jint con = c->as_jint();
1206 if (to_reg->is_single_cpu()) {
1207 assert(patch_code == lir_patch_none, "no patching handled here");
1208 __ set(con, to_reg->as_register());
1209 } else {
1210 ShouldNotReachHere();
1211 assert(to_reg->is_single_fpu(), "wrong register kind");
1212
1213 __ set(con, O7);
1214 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1215 __ st(O7, temp_slot);
1216 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1217 }
1218 }
1219 break;
1220
1221 case T_LONG:
1222 {
1223 jlong con = c->as_jlong();
1224
1225 if (to_reg->is_double_cpu()) {
1226 #ifdef _LP64
1227 __ set(con, to_reg->as_register_lo());
1228 #else
1229 __ set(low(con), to_reg->as_register_lo());
1230 __ set(high(con), to_reg->as_register_hi());
1231 #endif
1232 #ifdef _LP64
1233 } else if (to_reg->is_single_cpu()) {
1234 __ set(con, to_reg->as_register());
1235 #endif
1236 } else {
1237 ShouldNotReachHere();
1238 assert(to_reg->is_double_fpu(), "wrong register kind");
1239 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1240 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1241 __ set(low(con), O7);
1242 __ st(O7, temp_slot_lo);
1243 __ set(high(con), O7);
1244 __ st(O7, temp_slot_hi);
1245 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1246 }
1247 }
1248 break;
1249
1250 case T_OBJECT:
1251 {
1252 if (patch_code == lir_patch_none) {
1253 jobject2reg(c->as_jobject(), to_reg->as_register());
1254 } else {
1255 jobject2reg_with_patching(to_reg->as_register(), info);
1256 }
1257 }
1258 break;
1259
1260 case T_FLOAT:
1261 {
1262 address const_addr = __ float_constant(c->as_jfloat());
1263 if (const_addr == NULL) {
1264 bailout("const section overflow");
1265 break;
1266 }
1267 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1268 AddressLiteral const_addrlit(const_addr, rspec);
1269 if (to_reg->is_single_fpu()) {
1270 __ patchable_sethi(const_addrlit, O7);
1271 __ relocate(rspec);
1272 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1273
1274 } else {
1275 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1276
1277 __ set(const_addrlit, O7);
1278 load(O7, 0, to_reg->as_register(), T_INT);
1279 }
1280 }
1281 break;
1282
1283 case T_DOUBLE:
1284 {
1285 address const_addr = __ double_constant(c->as_jdouble());
1286 if (const_addr == NULL) {
1287 bailout("const section overflow");
1288 break;
1289 }
1290 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1291
1292 if (to_reg->is_double_fpu()) {
1293 AddressLiteral const_addrlit(const_addr, rspec);
1294 __ patchable_sethi(const_addrlit, O7);
1295 __ relocate(rspec);
1296 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1297 } else {
1298 assert(to_reg->is_double_cpu(), "Must be a long register.");
1299 #ifdef _LP64
1300 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1301 #else
1302 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1303 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1304 #endif
1305 }
1306
1307 }
1308 break;
1309
1310 default:
1311 ShouldNotReachHere();
1312 }
1313 }
1314
1315 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1316 Register reg = addr->base()->as_register();
1317 return Address(reg, addr->disp());
1318 }
1319
1320
1321 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1322 switch (type) {
1323 case T_INT:
1324 case T_FLOAT: {
1325 Register tmp = O7;
1326 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1327 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1328 __ lduw(from.base(), from.disp(), tmp);
1329 __ stw(tmp, to.base(), to.disp());
1330 break;
1331 }
1332 case T_OBJECT: {
1333 Register tmp = O7;
1334 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1335 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1336 __ ld_ptr(from.base(), from.disp(), tmp);
1337 __ st_ptr(tmp, to.base(), to.disp());
1338 break;
1339 }
1340 case T_LONG:
1341 case T_DOUBLE: {
1342 Register tmp = O7;
1343 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1344 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1345 __ lduw(from.base(), from.disp(), tmp);
1346 __ stw(tmp, to.base(), to.disp());
1347 __ lduw(from.base(), from.disp() + 4, tmp);
1348 __ stw(tmp, to.base(), to.disp() + 4);
1349 break;
1350 }
1351
1352 default:
1353 ShouldNotReachHere();
1354 }
1355 }
1356
1357
1358 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1359 Address base = as_Address(addr);
1360 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1361 }
1362
1363
1364 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1365 Address base = as_Address(addr);
1366 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1367 }
1368
1369
1370 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1371 LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) {
1372
1373 LIR_Address* addr = src_opr->as_address_ptr();
1374 LIR_Opr to_reg = dest;
1375
1376 Register src = addr->base()->as_pointer_register();
1377 Register disp_reg = noreg;
1378 int disp_value = addr->disp();
1379 bool needs_patching = (patch_code != lir_patch_none);
1380
1381 if (addr->base()->type() == T_OBJECT) {
1382 __ verify_oop(src);
1383 }
1384
1385 PatchingStub* patch = NULL;
1386 if (needs_patching) {
1387 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1388 assert(!to_reg->is_double_cpu() ||
1389 patch_code == lir_patch_none ||
1390 patch_code == lir_patch_normal, "patching doesn't match register");
1391 }
1392
1393 if (addr->index()->is_illegal()) {
1394 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1395 if (needs_patching) {
1396 __ patchable_set(0, O7);
1397 } else {
1398 __ set(disp_value, O7);
1399 }
1400 disp_reg = O7;
1401 }
1402 } else if (unaligned || PatchALot) {
1403 __ add(src, addr->index()->as_register(), O7);
1404 src = O7;
1405 } else {
1406 disp_reg = addr->index()->as_pointer_register();
1407 assert(disp_value == 0, "can't handle 3 operand addresses");
1408 }
1409
1410 // remember the offset of the load. The patching_epilog must be done
1411 // before the call to add_debug_info, otherwise the PcDescs don't get
1412 // entered in increasing order.
1413 int offset = code_offset();
1414
1415 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1416 if (disp_reg == noreg) {
1417 offset = load(src, disp_value, to_reg, type, unaligned);
1418 } else {
1419 assert(!unaligned, "can't handle this");
1420 offset = load(src, disp_reg, to_reg, type);
1421 }
1422
1423 if (patch != NULL) {
1424 patching_epilog(patch, patch_code, src, info);
1425 }
1426
1427 if (info != NULL) add_debug_info_for_null_check(offset, info);
1428 }
1429
1430
1431 void LIR_Assembler::prefetchr(LIR_Opr src) {
1432 LIR_Address* addr = src->as_address_ptr();
1433 Address from_addr = as_Address(addr);
1434
1435 if (VM_Version::has_v9()) {
1436 __ prefetch(from_addr, Assembler::severalReads);
1437 }
1438 }
1439
1440
1441 void LIR_Assembler::prefetchw(LIR_Opr src) {
1442 LIR_Address* addr = src->as_address_ptr();
1443 Address from_addr = as_Address(addr);
1444
1445 if (VM_Version::has_v9()) {
1446 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads);
1447 }
1448 }
1449
1450
1451 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1452 Address addr;
1453 if (src->is_single_word()) {
1454 addr = frame_map()->address_for_slot(src->single_stack_ix());
1455 } else if (src->is_double_word()) {
1456 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1457 }
1458
1459 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1460 load(addr.base(), addr.disp(), dest, dest->type(), unaligned);
1461 }
1462
1463
1464 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1465 Address addr;
1466 if (dest->is_single_word()) {
1467 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1468 } else if (dest->is_double_word()) {
1469 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1470 }
1471 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1472 store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned);
1473 }
1474
1475
1476 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1477 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1478 if (from_reg->is_double_fpu()) {
1479 // double to double moves
1480 assert(to_reg->is_double_fpu(), "should match");
1481 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1482 } else {
1483 // float to float moves
1484 assert(to_reg->is_single_fpu(), "should match");
1485 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1486 }
1487 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1488 if (from_reg->is_double_cpu()) {
1489 #ifdef _LP64
1490 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1491 #else
1492 assert(to_reg->is_double_cpu() &&
1493 from_reg->as_register_hi() != to_reg->as_register_lo() &&
1494 from_reg->as_register_lo() != to_reg->as_register_hi(),
1495 "should both be long and not overlap");
1496 // long to long moves
1497 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
1498 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
1499 #endif
1500 #ifdef _LP64
1501 } else if (to_reg->is_double_cpu()) {
1502 // int to int moves
1503 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1504 #endif
1505 } else {
1506 // int to int moves
1507 __ mov(from_reg->as_register(), to_reg->as_register());
1508 }
1509 } else {
1510 ShouldNotReachHere();
1511 }
1512 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1513 __ verify_oop(to_reg->as_register());
1514 }
1515 }
1516
1517
1518 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1519 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1520 bool unaligned) {
1521 LIR_Address* addr = dest->as_address_ptr();
1522
1523 Register src = addr->base()->as_pointer_register();
1524 Register disp_reg = noreg;
1525 int disp_value = addr->disp();
1526 bool needs_patching = (patch_code != lir_patch_none);
1527
1528 if (addr->base()->is_oop_register()) {
1529 __ verify_oop(src);
1530 }
1531
1532 PatchingStub* patch = NULL;
1533 if (needs_patching) {
1534 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1535 assert(!from_reg->is_double_cpu() ||
1536 patch_code == lir_patch_none ||
1537 patch_code == lir_patch_normal, "patching doesn't match register");
1538 }
1539
1540 if (addr->index()->is_illegal()) {
1541 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1542 if (needs_patching) {
1543 __ patchable_set(0, O7);
1544 } else {
1545 __ set(disp_value, O7);
1546 }
1547 disp_reg = O7;
1548 }
1549 } else if (unaligned || PatchALot) {
1550 __ add(src, addr->index()->as_register(), O7);
1551 src = O7;
1552 } else {
1553 disp_reg = addr->index()->as_pointer_register();
1554 assert(disp_value == 0, "can't handle 3 operand addresses");
1555 }
1556
1557 // remember the offset of the store. The patching_epilog must be done
1558 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1559 // entered in increasing order.
1560 int offset;
1561
1562 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1563 if (disp_reg == noreg) {
1564 offset = store(from_reg, src, disp_value, type, unaligned);
1565 } else {
1566 assert(!unaligned, "can't handle this");
1567 offset = store(from_reg, src, disp_reg, type);
1568 }
1569
1570 if (patch != NULL) {
1571 patching_epilog(patch, patch_code, src, info);
1572 }
1573
1574 if (info != NULL) add_debug_info_for_null_check(offset, info);
1575 }
1576
1577
1578 void LIR_Assembler::return_op(LIR_Opr result) {
1579 // the poll may need a register so just pick one that isn't the return register
1580 #ifdef TIERED
1581 if (result->type_field() == LIR_OprDesc::long_type) {
1582 // Must move the result to G1
1583 // Must leave proper result in O0,O1 and G1 (TIERED only)
1584 __ sllx(I0, 32, G1); // Shift bits into high G1
1585 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
1586 __ or3 (I1, G1, G1); // OR 64 bits into G1
1587 }
1588 #endif // TIERED
1589 __ set((intptr_t)os::get_polling_page(), L0);
1590 __ relocate(relocInfo::poll_return_type);
1591 __ ld_ptr(L0, 0, G0);
1592 __ ret();
1593 __ delayed()->restore();
1594 }
1595
1596
1597 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1598 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1599 if (info != NULL) {
1600 add_debug_info_for_branch(info);
1601 } else {
1602 __ relocate(relocInfo::poll_type);
1603 }
1604
1605 int offset = __ offset();
1606 __ ld_ptr(tmp->as_register(), 0, G0);
1607
1608 return offset;
1609 }
1610
1611
1612 void LIR_Assembler::emit_static_call_stub() {
1613 address call_pc = __ pc();
1614 address stub = __ start_a_stub(call_stub_size);
1615 if (stub == NULL) {
1616 bailout("static call stub overflow");
1617 return;
1618 }
1619
1620 int start = __ offset();
1621 __ relocate(static_stub_Relocation::spec(call_pc));
1622
1623 __ set_oop(NULL, G5);
1624 // must be set to -1 at code generation time
1625 AddressLiteral addrlit(-1);
1626 __ jump_to(addrlit, G3);
1627 __ delayed()->nop();
1628
1629 assert(__ offset() - start <= call_stub_size, "stub too big");
1630 __ end_a_stub();
1631 }
1632
1633
1634 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1635 if (opr1->is_single_fpu()) {
1636 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1637 } else if (opr1->is_double_fpu()) {
1638 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1639 } else if (opr1->is_single_cpu()) {
1640 if (opr2->is_constant()) {
1641 switch (opr2->as_constant_ptr()->type()) {
1642 case T_INT:
1643 { jint con = opr2->as_constant_ptr()->as_jint();
1644 if (Assembler::is_simm13(con)) {
1645 __ cmp(opr1->as_register(), con);
1646 } else {
1647 __ set(con, O7);
1648 __ cmp(opr1->as_register(), O7);
1649 }
1650 }
1651 break;
1652
1653 case T_OBJECT:
1654 // there are only equal/notequal comparisions on objects
1655 { jobject con = opr2->as_constant_ptr()->as_jobject();
1656 if (con == NULL) {
1657 __ cmp(opr1->as_register(), 0);
1658 } else {
1659 jobject2reg(con, O7);
1660 __ cmp(opr1->as_register(), O7);
1661 }
1662 }
1663 break;
1664
1665 default:
1666 ShouldNotReachHere();
1667 break;
1668 }
1669 } else {
1670 if (opr2->is_address()) {
1671 LIR_Address * addr = opr2->as_address_ptr();
1672 BasicType type = addr->type();
1673 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1674 else __ ld(as_Address(addr), O7);
1675 __ cmp(opr1->as_register(), O7);
1676 } else {
1677 __ cmp(opr1->as_register(), opr2->as_register());
1678 }
1679 }
1680 } else if (opr1->is_double_cpu()) {
1681 Register xlo = opr1->as_register_lo();
1682 Register xhi = opr1->as_register_hi();
1683 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1684 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1685 #ifdef _LP64
1686 __ orcc(xhi, G0, G0);
1687 #else
1688 __ orcc(xhi, xlo, G0);
1689 #endif
1690 } else if (opr2->is_register()) {
1691 Register ylo = opr2->as_register_lo();
1692 Register yhi = opr2->as_register_hi();
1693 #ifdef _LP64
1694 __ cmp(xlo, ylo);
1695 #else
1696 __ subcc(xlo, ylo, xlo);
1697 __ subccc(xhi, yhi, xhi);
1698 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1699 __ orcc(xhi, xlo, G0);
1700 }
1701 #endif
1702 } else {
1703 ShouldNotReachHere();
1704 }
1705 } else if (opr1->is_address()) {
1706 LIR_Address * addr = opr1->as_address_ptr();
1707 BasicType type = addr->type();
1708 assert (opr2->is_constant(), "Checking");
1709 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1710 else __ ld(as_Address(addr), O7);
1711 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1712 } else {
1713 ShouldNotReachHere();
1714 }
1715 }
1716
1717
1718 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1719 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1720 bool is_unordered_less = (code == lir_ucmp_fd2i);
1721 if (left->is_single_fpu()) {
1722 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1723 } else if (left->is_double_fpu()) {
1724 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1725 } else {
1726 ShouldNotReachHere();
1727 }
1728 } else if (code == lir_cmp_l2i) {
1729 __ lcmp(left->as_register_hi(), left->as_register_lo(),
1730 right->as_register_hi(), right->as_register_lo(),
1731 dst->as_register());
1732 } else {
1733 ShouldNotReachHere();
1734 }
1735 }
1736
1737
1738 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
1739
1740 Assembler::Condition acond;
1741 switch (condition) {
1742 case lir_cond_equal: acond = Assembler::equal; break;
1743 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1744 case lir_cond_less: acond = Assembler::less; break;
1745 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1746 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1747 case lir_cond_greater: acond = Assembler::greater; break;
1748 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1749 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1750 default: ShouldNotReachHere();
1751 };
1752
1753 if (opr1->is_constant() && opr1->type() == T_INT) {
1754 Register dest = result->as_register();
1755 // load up first part of constant before branch
1756 // and do the rest in the delay slot.
1757 if (!Assembler::is_simm13(opr1->as_jint())) {
1758 __ sethi(opr1->as_jint(), dest);
1759 }
1760 } else if (opr1->is_constant()) {
1761 const2reg(opr1, result, lir_patch_none, NULL);
1762 } else if (opr1->is_register()) {
1763 reg2reg(opr1, result);
1764 } else if (opr1->is_stack()) {
1765 stack2reg(opr1, result, result->type());
1766 } else {
1767 ShouldNotReachHere();
1768 }
1769 Label skip;
1770 __ br(acond, false, Assembler::pt, skip);
1771 if (opr1->is_constant() && opr1->type() == T_INT) {
1772 Register dest = result->as_register();
1773 if (Assembler::is_simm13(opr1->as_jint())) {
1774 __ delayed()->or3(G0, opr1->as_jint(), dest);
1775 } else {
1776 // the sethi has been done above, so just put in the low 10 bits
1777 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1778 }
1779 } else {
1780 // can't do anything useful in the delay slot
1781 __ delayed()->nop();
1782 }
1783 if (opr2->is_constant()) {
1784 const2reg(opr2, result, lir_patch_none, NULL);
1785 } else if (opr2->is_register()) {
1786 reg2reg(opr2, result);
1787 } else if (opr2->is_stack()) {
1788 stack2reg(opr2, result, result->type());
1789 } else {
1790 ShouldNotReachHere();
1791 }
1792 __ bind(skip);
1793 }
1794
1795
1796 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1797 assert(info == NULL, "unused on this code path");
1798 assert(left->is_register(), "wrong items state");
1799 assert(dest->is_register(), "wrong items state");
1800
1801 if (right->is_register()) {
1802 if (dest->is_float_kind()) {
1803
1804 FloatRegister lreg, rreg, res;
1805 FloatRegisterImpl::Width w;
1806 if (right->is_single_fpu()) {
1807 w = FloatRegisterImpl::S;
1808 lreg = left->as_float_reg();
1809 rreg = right->as_float_reg();
1810 res = dest->as_float_reg();
1811 } else {
1812 w = FloatRegisterImpl::D;
1813 lreg = left->as_double_reg();
1814 rreg = right->as_double_reg();
1815 res = dest->as_double_reg();
1816 }
1817
1818 switch (code) {
1819 case lir_add: __ fadd(w, lreg, rreg, res); break;
1820 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1821 case lir_mul: // fall through
1822 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1823 case lir_div: // fall through
1824 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1825 default: ShouldNotReachHere();
1826 }
1827
1828 } else if (dest->is_double_cpu()) {
1829 #ifdef _LP64
1830 Register dst_lo = dest->as_register_lo();
1831 Register op1_lo = left->as_pointer_register();
1832 Register op2_lo = right->as_pointer_register();
1833
1834 switch (code) {
1835 case lir_add:
1836 __ add(op1_lo, op2_lo, dst_lo);
1837 break;
1838
1839 case lir_sub:
1840 __ sub(op1_lo, op2_lo, dst_lo);
1841 break;
1842
1843 default: ShouldNotReachHere();
1844 }
1845 #else
1846 Register op1_lo = left->as_register_lo();
1847 Register op1_hi = left->as_register_hi();
1848 Register op2_lo = right->as_register_lo();
1849 Register op2_hi = right->as_register_hi();
1850 Register dst_lo = dest->as_register_lo();
1851 Register dst_hi = dest->as_register_hi();
1852
1853 switch (code) {
1854 case lir_add:
1855 __ addcc(op1_lo, op2_lo, dst_lo);
1856 __ addc (op1_hi, op2_hi, dst_hi);
1857 break;
1858
1859 case lir_sub:
1860 __ subcc(op1_lo, op2_lo, dst_lo);
1861 __ subc (op1_hi, op2_hi, dst_hi);
1862 break;
1863
1864 default: ShouldNotReachHere();
1865 }
1866 #endif
1867 } else {
1868 assert (right->is_single_cpu(), "Just Checking");
1869
1870 Register lreg = left->as_register();
1871 Register res = dest->as_register();
1872 Register rreg = right->as_register();
1873 switch (code) {
1874 case lir_add: __ add (lreg, rreg, res); break;
1875 case lir_sub: __ sub (lreg, rreg, res); break;
1876 case lir_mul: __ mult (lreg, rreg, res); break;
1877 default: ShouldNotReachHere();
1878 }
1879 }
1880 } else {
1881 assert (right->is_constant(), "must be constant");
1882
1883 if (dest->is_single_cpu()) {
1884 Register lreg = left->as_register();
1885 Register res = dest->as_register();
1886 int simm13 = right->as_constant_ptr()->as_jint();
1887
1888 switch (code) {
1889 case lir_add: __ add (lreg, simm13, res); break;
1890 case lir_sub: __ sub (lreg, simm13, res); break;
1891 case lir_mul: __ mult (lreg, simm13, res); break;
1892 default: ShouldNotReachHere();
1893 }
1894 } else {
1895 Register lreg = left->as_pointer_register();
1896 Register res = dest->as_register_lo();
1897 long con = right->as_constant_ptr()->as_jlong();
1898 assert(Assembler::is_simm13(con), "must be simm13");
1899
1900 switch (code) {
1901 case lir_add: __ add (lreg, (int)con, res); break;
1902 case lir_sub: __ sub (lreg, (int)con, res); break;
1903 case lir_mul: __ mult (lreg, (int)con, res); break;
1904 default: ShouldNotReachHere();
1905 }
1906 }
1907 }
1908 }
1909
1910
1911 void LIR_Assembler::fpop() {
1912 // do nothing
1913 }
1914
1915
1916 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1917 switch (code) {
1918 case lir_sin:
1919 case lir_tan:
1920 case lir_cos: {
1921 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1922 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1923 break;
1924 }
1925 case lir_sqrt: {
1926 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1927 FloatRegister src_reg = value->as_double_reg();
1928 FloatRegister dst_reg = dest->as_double_reg();
1929 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1930 break;
1931 }
1932 case lir_abs: {
1933 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1934 FloatRegister src_reg = value->as_double_reg();
1935 FloatRegister dst_reg = dest->as_double_reg();
1936 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1937 break;
1938 }
1939 default: {
1940 ShouldNotReachHere();
1941 break;
1942 }
1943 }
1944 }
1945
1946
1947 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1948 if (right->is_constant()) {
1949 if (dest->is_single_cpu()) {
1950 int simm13 = right->as_constant_ptr()->as_jint();
1951 switch (code) {
1952 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1953 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1954 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1955 default: ShouldNotReachHere();
1956 }
1957 } else {
1958 long c = right->as_constant_ptr()->as_jlong();
1959 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1960 int simm13 = (int)c;
1961 switch (code) {
1962 case lir_logic_and:
1963 #ifndef _LP64
1964 __ and3 (left->as_register_hi(), 0, dest->as_register_hi());
1965 #endif
1966 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1967 break;
1968
1969 case lir_logic_or:
1970 #ifndef _LP64
1971 __ or3 (left->as_register_hi(), 0, dest->as_register_hi());
1972 #endif
1973 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1974 break;
1975
1976 case lir_logic_xor:
1977 #ifndef _LP64
1978 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi());
1979 #endif
1980 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1981 break;
1982
1983 default: ShouldNotReachHere();
1984 }
1985 }
1986 } else {
1987 assert(right->is_register(), "right should be in register");
1988
1989 if (dest->is_single_cpu()) {
1990 switch (code) {
1991 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1992 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1993 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1994 default: ShouldNotReachHere();
1995 }
1996 } else {
1997 #ifdef _LP64
1998 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1999 left->as_register_lo();
2000 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
2001 right->as_register_lo();
2002
2003 switch (code) {
2004 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
2005 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
2006 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
2007 default: ShouldNotReachHere();
2008 }
2009 #else
2010 switch (code) {
2011 case lir_logic_and:
2012 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2013 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2014 break;
2015
2016 case lir_logic_or:
2017 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2018 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2019 break;
2020
2021 case lir_logic_xor:
2022 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2023 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2024 break;
2025
2026 default: ShouldNotReachHere();
2027 }
2028 #endif
2029 }
2030 }
2031 }
2032
2033
2034 int LIR_Assembler::shift_amount(BasicType t) {
2035 int elem_size = type2aelembytes(t);
2036 switch (elem_size) {
2037 case 1 : return 0;
2038 case 2 : return 1;
2039 case 4 : return 2;
2040 case 8 : return 3;
2041 }
2042 ShouldNotReachHere();
2043 return -1;
2044 }
2045
2046
2047 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) {
2048 assert(exceptionOop->as_register() == Oexception, "should match");
2049 assert(unwind || exceptionPC->as_register() == Oissuing_pc, "should match");
2050
2051 info->add_register_oop(exceptionOop);
2052
2053 if (unwind) {
2054 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
2055 __ delayed()->nop();
2056 } else {
2057 // reuse the debug info from the safepoint poll for the throw op itself
2058 address pc_for_athrow = __ pc();
2059 int pc_for_athrow_offset = __ offset();
2060 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
2061 __ set(pc_for_athrow, Oissuing_pc, rspec);
2062 add_call_info(pc_for_athrow_offset, info); // for exception handler
2063
2064 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
2065 __ delayed()->nop();
2066 }
2067 }
2068
2069
2070 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2071 Register src = op->src()->as_register();
2072 Register dst = op->dst()->as_register();
2073 Register src_pos = op->src_pos()->as_register();
2074 Register dst_pos = op->dst_pos()->as_register();
2075 Register length = op->length()->as_register();
2076 Register tmp = op->tmp()->as_register();
2077 Register tmp2 = O7;
2078
2079 int flags = op->flags();
2080 ciArrayKlass* default_type = op->expected_type();
2081 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2082 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2083
2084 // set up the arraycopy stub information
2085 ArrayCopyStub* stub = op->stub();
2086
2087 // always do stub if no type information is available. it's ok if
2088 // the known type isn't loaded since the code sanity checks
2089 // in debug mode and the type isn't required when we know the exact type
2090 // also check that the type is an array type.
2091 // We also, for now, always call the stub if the barrier set requires a
2092 // write_ref_pre barrier (which the stub does, but none of the optimized
2093 // cases currently does).
2094 if (op->expected_type() == NULL ||
2095 Universe::heap()->barrier_set()->has_write_ref_pre_barrier()) {
2096 __ mov(src, O0);
2097 __ mov(src_pos, O1);
2098 __ mov(dst, O2);
2099 __ mov(dst_pos, O3);
2100 __ mov(length, O4);
2101 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
2102
2103 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry());
2104 __ delayed()->nop();
2105 __ bind(*stub->continuation());
2106 return;
2107 }
2108
2109 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
2110
2111 // make sure src and dst are non-null and load array length
2112 if (flags & LIR_OpArrayCopy::src_null_check) {
2113 __ tst(src);
2114 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2115 __ delayed()->nop();
2116 }
2117
2118 if (flags & LIR_OpArrayCopy::dst_null_check) {
2119 __ tst(dst);
2120 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2121 __ delayed()->nop();
2122 }
2123
2124 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2125 // test src_pos register
2126 __ tst(src_pos);
2127 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2128 __ delayed()->nop();
2129 }
2130
2131 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2132 // test dst_pos register
2133 __ tst(dst_pos);
2134 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2135 __ delayed()->nop();
2136 }
2137
2138 if (flags & LIR_OpArrayCopy::length_positive_check) {
2139 // make sure length isn't negative
2140 __ tst(length);
2141 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2142 __ delayed()->nop();
2143 }
2144
2145 if (flags & LIR_OpArrayCopy::src_range_check) {
2146 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
2147 __ add(length, src_pos, tmp);
2148 __ cmp(tmp2, tmp);
2149 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2150 __ delayed()->nop();
2151 }
2152
2153 if (flags & LIR_OpArrayCopy::dst_range_check) {
2154 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
2155 __ add(length, dst_pos, tmp);
2156 __ cmp(tmp2, tmp);
2157 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2158 __ delayed()->nop();
2159 }
2160
2161 if (flags & LIR_OpArrayCopy::type_check) {
2162 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
2163 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2164 __ cmp(tmp, tmp2);
2165 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2166 __ delayed()->nop();
2167 }
2168
2169 #ifdef ASSERT
2170 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2171 // Sanity check the known type with the incoming class. For the
2172 // primitive case the types must match exactly with src.klass and
2173 // dst.klass each exactly matching the default type. For the
2174 // object array case, if no type check is needed then either the
2175 // dst type is exactly the expected type and the src type is a
2176 // subtype which we can't check or src is the same array as dst
2177 // but not necessarily exactly of type default_type.
2178 Label known_ok, halt;
2179 jobject2reg(op->expected_type()->constant_encoding(), tmp);
2180 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2181 if (basic_type != T_OBJECT) {
2182 __ cmp(tmp, tmp2);
2183 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2184 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2185 __ cmp(tmp, tmp2);
2186 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2187 __ delayed()->nop();
2188 } else {
2189 __ cmp(tmp, tmp2);
2190 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2191 __ delayed()->cmp(src, dst);
2192 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2193 __ delayed()->nop();
2194 }
2195 __ bind(halt);
2196 __ stop("incorrect type information in arraycopy");
2197 __ bind(known_ok);
2198 }
2199 #endif
2200
2201 int shift = shift_amount(basic_type);
2202
2203 Register src_ptr = O0;
2204 Register dst_ptr = O1;
2205 Register len = O2;
2206
2207 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2208 LP64_ONLY(__ sra(src_pos, 0, src_pos);) //higher 32bits must be null
2209 if (shift == 0) {
2210 __ add(src_ptr, src_pos, src_ptr);
2211 } else {
2212 __ sll(src_pos, shift, tmp);
2213 __ add(src_ptr, tmp, src_ptr);
2214 }
2215
2216 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2217 LP64_ONLY(__ sra(dst_pos, 0, dst_pos);) //higher 32bits must be null
2218 if (shift == 0) {
2219 __ add(dst_ptr, dst_pos, dst_ptr);
2220 } else {
2221 __ sll(dst_pos, shift, tmp);
2222 __ add(dst_ptr, tmp, dst_ptr);
2223 }
2224
2225 if (basic_type != T_OBJECT) {
2226 if (shift == 0) {
2227 __ mov(length, len);
2228 } else {
2229 __ sll(length, shift, len);
2230 }
2231 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy));
2232 } else {
2233 // oop_arraycopy takes a length in number of elements, so don't scale it.
2234 __ mov(length, len);
2235 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy));
2236 }
2237
2238 __ bind(*stub->continuation());
2239 }
2240
2241
2242 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2243 if (dest->is_single_cpu()) {
2244 #ifdef _LP64
2245 if (left->type() == T_OBJECT) {
2246 switch (code) {
2247 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2248 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2249 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2250 default: ShouldNotReachHere();
2251 }
2252 } else
2253 #endif
2254 switch (code) {
2255 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2256 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2257 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2258 default: ShouldNotReachHere();
2259 }
2260 } else {
2261 #ifdef _LP64
2262 switch (code) {
2263 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2264 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2265 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2266 default: ShouldNotReachHere();
2267 }
2268 #else
2269 switch (code) {
2270 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2271 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2272 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2273 default: ShouldNotReachHere();
2274 }
2275 #endif
2276 }
2277 }
2278
2279
2280 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2281 #ifdef _LP64
2282 if (left->type() == T_OBJECT) {
2283 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2284 Register l = left->as_register();
2285 Register d = dest->as_register_lo();
2286 switch (code) {
2287 case lir_shl: __ sllx (l, count, d); break;
2288 case lir_shr: __ srax (l, count, d); break;
2289 case lir_ushr: __ srlx (l, count, d); break;
2290 default: ShouldNotReachHere();
2291 }
2292 return;
2293 }
2294 #endif
2295
2296 if (dest->is_single_cpu()) {
2297 count = count & 0x1F; // Java spec
2298 switch (code) {
2299 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2300 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2301 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2302 default: ShouldNotReachHere();
2303 }
2304 } else if (dest->is_double_cpu()) {
2305 count = count & 63; // Java spec
2306 switch (code) {
2307 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2308 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2309 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2310 default: ShouldNotReachHere();
2311 }
2312 } else {
2313 ShouldNotReachHere();
2314 }
2315 }
2316
2317
2318 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2319 assert(op->tmp1()->as_register() == G1 &&
2320 op->tmp2()->as_register() == G3 &&
2321 op->tmp3()->as_register() == G4 &&
2322 op->obj()->as_register() == O0 &&
2323 op->klass()->as_register() == G5, "must be");
2324 if (op->init_check()) {
2325 __ ld(op->klass()->as_register(),
2326 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc),
2327 op->tmp1()->as_register());
2328 add_debug_info_for_null_check_here(op->stub()->info());
2329 __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized);
2330 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2331 __ delayed()->nop();
2332 }
2333 __ allocate_object(op->obj()->as_register(),
2334 op->tmp1()->as_register(),
2335 op->tmp2()->as_register(),
2336 op->tmp3()->as_register(),
2337 op->header_size(),
2338 op->object_size(),
2339 op->klass()->as_register(),
2340 *op->stub()->entry());
2341 __ bind(*op->stub()->continuation());
2342 __ verify_oop(op->obj()->as_register());
2343 }
2344
2345
2346 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2347 assert(op->tmp1()->as_register() == G1 &&
2348 op->tmp2()->as_register() == G3 &&
2349 op->tmp3()->as_register() == G4 &&
2350 op->tmp4()->as_register() == O1 &&
2351 op->klass()->as_register() == G5, "must be");
2352 if (UseSlowPath ||
2353 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2354 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2355 __ br(Assembler::always, false, Assembler::pn, *op->stub()->entry());
2356 __ delayed()->nop();
2357 } else {
2358 __ allocate_array(op->obj()->as_register(),
2359 op->len()->as_register(),
2360 op->tmp1()->as_register(),
2361 op->tmp2()->as_register(),
2362 op->tmp3()->as_register(),
2363 arrayOopDesc::header_size(op->type()),
2364 type2aelembytes(op->type()),
2365 op->klass()->as_register(),
2366 *op->stub()->entry());
2367 }
2368 __ bind(*op->stub()->continuation());
2369 }
2370
2371
2372 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2373 LIR_Code code = op->code();
2374 if (code == lir_store_check) {
2375 Register value = op->object()->as_register();
2376 Register array = op->array()->as_register();
2377 Register k_RInfo = op->tmp1()->as_register();
2378 Register klass_RInfo = op->tmp2()->as_register();
2379 Register Rtmp1 = op->tmp3()->as_register();
2380
2381 __ verify_oop(value);
2382
2383 CodeStub* stub = op->stub();
2384 Label done;
2385 __ cmp(value, 0);
2386 __ br(Assembler::equal, false, Assembler::pn, done);
2387 __ delayed()->nop();
2388 load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception());
2389 load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2390
2391 // get instance klass
2392 load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL);
2393 // perform the fast part of the checking logic
2394 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, &done, stub->entry(), NULL);
2395
2396 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2397 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2398 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2399 __ delayed()->nop();
2400 __ cmp(G3, 0);
2401 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2402 __ delayed()->nop();
2403 __ bind(done);
2404 } else if (op->code() == lir_checkcast) {
2405 // we always need a stub for the failure case.
2406 CodeStub* stub = op->stub();
2407 Register obj = op->object()->as_register();
2408 Register k_RInfo = op->tmp1()->as_register();
2409 Register klass_RInfo = op->tmp2()->as_register();
2410 Register dst = op->result_opr()->as_register();
2411 Register Rtmp1 = op->tmp3()->as_register();
2412 ciKlass* k = op->klass();
2413
2414 if (obj == k_RInfo) {
2415 k_RInfo = klass_RInfo;
2416 klass_RInfo = obj;
2417 }
2418 if (op->profiled_method() != NULL) {
2419 ciMethod* method = op->profiled_method();
2420 int bci = op->profiled_bci();
2421
2422 // We need two temporaries to perform this operation on SPARC,
2423 // so to keep things simple we perform a redundant test here
2424 Label profile_done;
2425 __ cmp(obj, 0);
2426 __ br(Assembler::notEqual, false, Assembler::pn, profile_done);
2427 __ delayed()->nop();
2428 // Object is null; update methodDataOop
2429 ciMethodData* md = method->method_data();
2430 if (md == NULL) {
2431 bailout("out of memory building methodDataOop");
2432 return;
2433 }
2434 ciProfileData* data = md->bci_to_data(bci);
2435 assert(data != NULL, "need data for checkcast");
2436 assert(data->is_BitData(), "need BitData for checkcast");
2437 Register mdo = k_RInfo;
2438 Register data_val = Rtmp1;
2439 jobject2reg(md->constant_encoding(), mdo);
2440
2441 int mdo_offset_bias = 0;
2442 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2443 // The offset is large so bias the mdo by the base of the slot so
2444 // that the ld can use simm13s to reference the slots of the data
2445 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2446 __ set(mdo_offset_bias, data_val);
2447 __ add(mdo, data_val, mdo);
2448 }
2449
2450
2451 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2452 __ ldub(flags_addr, data_val);
2453 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2454 __ stb(data_val, flags_addr);
2455 __ bind(profile_done);
2456 }
2457
2458 Label done;
2459 // patching may screw with our temporaries on sparc,
2460 // so let's do it before loading the class
2461 if (k->is_loaded()) {
2462 jobject2reg(k->constant_encoding(), k_RInfo);
2463 } else {
2464 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2465 }
2466 assert(obj != k_RInfo, "must be different");
2467 __ cmp(obj, 0);
2468 __ br(Assembler::equal, false, Assembler::pn, done);
2469 __ delayed()->nop();
2470
2471 // get object class
2472 // not a safepoint as obj null check happens earlier
2473 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2474 if (op->fast_check()) {
2475 assert_different_registers(klass_RInfo, k_RInfo);
2476 __ cmp(k_RInfo, klass_RInfo);
2477 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2478 __ delayed()->nop();
2479 __ bind(done);
2480 } else {
2481 bool need_slow_path = true;
2482 if (k->is_loaded()) {
2483 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2484 need_slow_path = false;
2485 // perform the fast part of the checking logic
2486 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2487 (need_slow_path ? &done : NULL),
2488 stub->entry(), NULL,
2489 RegisterOrConstant(k->super_check_offset()));
2490 } else {
2491 // perform the fast part of the checking logic
2492 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7,
2493 &done, stub->entry(), NULL);
2494 }
2495 if (need_slow_path) {
2496 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2497 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2498 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2499 __ delayed()->nop();
2500 __ cmp(G3, 0);
2501 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2502 __ delayed()->nop();
2503 }
2504 __ bind(done);
2505 }
2506 __ mov(obj, dst);
2507 } else if (code == lir_instanceof) {
2508 Register obj = op->object()->as_register();
2509 Register k_RInfo = op->tmp1()->as_register();
2510 Register klass_RInfo = op->tmp2()->as_register();
2511 Register dst = op->result_opr()->as_register();
2512 Register Rtmp1 = op->tmp3()->as_register();
2513 ciKlass* k = op->klass();
2514
2515 Label done;
2516 if (obj == k_RInfo) {
2517 k_RInfo = klass_RInfo;
2518 klass_RInfo = obj;
2519 }
2520 // patching may screw with our temporaries on sparc,
2521 // so let's do it before loading the class
2522 if (k->is_loaded()) {
2523 jobject2reg(k->constant_encoding(), k_RInfo);
2524 } else {
2525 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2526 }
2527 assert(obj != k_RInfo, "must be different");
2528 __ cmp(obj, 0);
2529 __ br(Assembler::equal, true, Assembler::pn, done);
2530 __ delayed()->set(0, dst);
2531
2532 // get object class
2533 // not a safepoint as obj null check happens earlier
2534 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2535 if (op->fast_check()) {
2536 __ cmp(k_RInfo, klass_RInfo);
2537 __ br(Assembler::equal, true, Assembler::pt, done);
2538 __ delayed()->set(1, dst);
2539 __ set(0, dst);
2540 __ bind(done);
2541 } else {
2542 bool need_slow_path = true;
2543 if (k->is_loaded()) {
2544 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2545 need_slow_path = false;
2546 // perform the fast part of the checking logic
2547 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, noreg,
2548 (need_slow_path ? &done : NULL),
2549 (need_slow_path ? &done : NULL), NULL,
2550 RegisterOrConstant(k->super_check_offset()),
2551 dst);
2552 } else {
2553 assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers");
2554 // perform the fast part of the checking logic
2555 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, dst,
2556 &done, &done, NULL,
2557 RegisterOrConstant(-1),
2558 dst);
2559 }
2560 if (need_slow_path) {
2561 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2562 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2563 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2564 __ delayed()->nop();
2565 __ mov(G3, dst);
2566 }
2567 __ bind(done);
2568 }
2569 } else {
2570 ShouldNotReachHere();
2571 }
2572
2573 }
2574
2575
2576 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2577 if (op->code() == lir_cas_long) {
2578 assert(VM_Version::supports_cx8(), "wrong machine");
2579 Register addr = op->addr()->as_pointer_register();
2580 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2581 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2582 Register new_value_lo = op->new_value()->as_register_lo();
2583 Register new_value_hi = op->new_value()->as_register_hi();
2584 Register t1 = op->tmp1()->as_register();
2585 Register t2 = op->tmp2()->as_register();
2586 #ifdef _LP64
2587 __ mov(cmp_value_lo, t1);
2588 __ mov(new_value_lo, t2);
2589 #else
2590 // move high and low halves of long values into single registers
2591 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
2592 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2593 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
2594 __ sllx(new_value_hi, 32, t2);
2595 __ srl(new_value_lo, 0, new_value_lo);
2596 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
2597 #endif
2598 // perform the compare and swap operation
2599 __ casx(addr, t1, t2);
2600 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2601 // overwritten with the original value in "addr" and will be equal to t1.
2602 __ cmp(t1, t2);
2603
2604 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2605 Register addr = op->addr()->as_pointer_register();
2606 Register cmp_value = op->cmp_value()->as_register();
2607 Register new_value = op->new_value()->as_register();
2608 Register t1 = op->tmp1()->as_register();
2609 Register t2 = op->tmp2()->as_register();
2610 __ mov(cmp_value, t1);
2611 __ mov(new_value, t2);
2612 #ifdef _LP64
2613 if (op->code() == lir_cas_obj) {
2614 __ casx(addr, t1, t2);
2615 } else
2616 #endif
2617 {
2618 __ cas(addr, t1, t2);
2619 }
2620 __ cmp(t1, t2);
2621 } else {
2622 Unimplemented();
2623 }
2624 }
2625
2626 void LIR_Assembler::set_24bit_FPU() {
2627 Unimplemented();
2628 }
2629
2630
2631 void LIR_Assembler::reset_FPU() {
2632 Unimplemented();
2633 }
2634
2635
2636 void LIR_Assembler::breakpoint() {
2637 __ breakpoint_trap();
2638 }
2639
2640
2641 void LIR_Assembler::push(LIR_Opr opr) {
2642 Unimplemented();
2643 }
2644
2645
2646 void LIR_Assembler::pop(LIR_Opr opr) {
2647 Unimplemented();
2648 }
2649
2650
2651 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2652 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2653 Register dst = dst_opr->as_register();
2654 Register reg = mon_addr.base();
2655 int offset = mon_addr.disp();
2656 // compute pointer to BasicLock
2657 if (mon_addr.is_simm13()) {
2658 __ add(reg, offset, dst);
2659 } else {
2660 __ set(offset, dst);
2661 __ add(dst, reg, dst);
2662 }
2663 }
2664
2665
2666 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2667 Register obj = op->obj_opr()->as_register();
2668 Register hdr = op->hdr_opr()->as_register();
2669 Register lock = op->lock_opr()->as_register();
2670
2671 // obj may not be an oop
2672 if (op->code() == lir_lock) {
2673 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2674 if (UseFastLocking) {
2675 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2676 // add debug info for NullPointerException only if one is possible
2677 if (op->info() != NULL) {
2678 add_debug_info_for_null_check_here(op->info());
2679 }
2680 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2681 } else {
2682 // always do slow locking
2683 // note: the slow locking code could be inlined here, however if we use
2684 // slow locking, speed doesn't matter anyway and this solution is
2685 // simpler and requires less duplicated code - additionally, the
2686 // slow locking code is the same in either case which simplifies
2687 // debugging
2688 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2689 __ delayed()->nop();
2690 }
2691 } else {
2692 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2693 if (UseFastLocking) {
2694 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2695 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2696 } else {
2697 // always do slow unlocking
2698 // note: the slow unlocking code could be inlined here, however if we use
2699 // slow unlocking, speed doesn't matter anyway and this solution is
2700 // simpler and requires less duplicated code - additionally, the
2701 // slow unlocking code is the same in either case which simplifies
2702 // debugging
2703 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2704 __ delayed()->nop();
2705 }
2706 }
2707 __ bind(*op->stub()->continuation());
2708 }
2709
2710
2711 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2712 ciMethod* method = op->profiled_method();
2713 int bci = op->profiled_bci();
2714
2715 // Update counter for all call types
2716 ciMethodData* md = method->method_data();
2717 if (md == NULL) {
2718 bailout("out of memory building methodDataOop");
2719 return;
2720 }
2721 ciProfileData* data = md->bci_to_data(bci);
2722 assert(data->is_CounterData(), "need CounterData for calls");
2723 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2724 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2725 Register mdo = op->mdo()->as_register();
2726 Register tmp1 = op->tmp1()->as_register();
2727 jobject2reg(md->constant_encoding(), mdo);
2728 int mdo_offset_bias = 0;
2729 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2730 data->size_in_bytes())) {
2731 // The offset is large so bias the mdo by the base of the slot so
2732 // that the ld can use simm13s to reference the slots of the data
2733 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2734 __ set(mdo_offset_bias, O7);
2735 __ add(mdo, O7, mdo);
2736 }
2737
2738 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2739 __ lduw(counter_addr, tmp1);
2740 __ add(tmp1, DataLayout::counter_increment, tmp1);
2741 __ stw(tmp1, counter_addr);
2742 Bytecodes::Code bc = method->java_code_at_bci(bci);
2743 // Perform additional virtual call profiling for invokevirtual and
2744 // invokeinterface bytecodes
2745 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2746 Tier1ProfileVirtualCalls) {
2747 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2748 Register recv = op->recv()->as_register();
2749 assert_different_registers(mdo, tmp1, recv);
2750 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2751 ciKlass* known_klass = op->known_holder();
2752 if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) {
2753 // We know the type that will be seen at this call site; we can
2754 // statically update the methodDataOop rather than needing to do
2755 // dynamic tests on the receiver type
2756
2757 // NOTE: we should probably put a lock around this search to
2758 // avoid collisions by concurrent compilations
2759 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2760 uint i;
2761 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2762 ciKlass* receiver = vc_data->receiver(i);
2763 if (known_klass->equals(receiver)) {
2764 Address data_addr(mdo, md->byte_offset_of_slot(data,
2765 VirtualCallData::receiver_count_offset(i)) -
2766 mdo_offset_bias);
2767 __ lduw(data_addr, tmp1);
2768 __ add(tmp1, DataLayout::counter_increment, tmp1);
2769 __ stw(tmp1, data_addr);
2770 return;
2771 }
2772 }
2773
2774 // Receiver type not found in profile data; select an empty slot
2775
2776 // Note that this is less efficient than it should be because it
2777 // always does a write to the receiver part of the
2778 // VirtualCallData rather than just the first time
2779 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2780 ciKlass* receiver = vc_data->receiver(i);
2781 if (receiver == NULL) {
2782 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2783 mdo_offset_bias);
2784 jobject2reg(known_klass->constant_encoding(), tmp1);
2785 __ st_ptr(tmp1, recv_addr);
2786 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2787 mdo_offset_bias);
2788 __ lduw(data_addr, tmp1);
2789 __ add(tmp1, DataLayout::counter_increment, tmp1);
2790 __ stw(tmp1, data_addr);
2791 return;
2792 }
2793 }
2794 } else {
2795 load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
2796 Label update_done;
2797 uint i;
2798 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2799 Label next_test;
2800 // See if the receiver is receiver[n].
2801 Address receiver_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2802 mdo_offset_bias);
2803 __ ld_ptr(receiver_addr, tmp1);
2804 __ verify_oop(tmp1);
2805 __ cmp(recv, tmp1);
2806 __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
2807 __ delayed()->nop();
2808 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2809 mdo_offset_bias);
2810 __ lduw(data_addr, tmp1);
2811 __ add(tmp1, DataLayout::counter_increment, tmp1);
2812 __ stw(tmp1, data_addr);
2813 __ br(Assembler::always, false, Assembler::pt, update_done);
2814 __ delayed()->nop();
2815 __ bind(next_test);
2816 }
2817
2818 // Didn't find receiver; find next empty slot and fill it in
2819 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2820 Label next_test;
2821 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2822 mdo_offset_bias);
2823 load(recv_addr, tmp1, T_OBJECT);
2824 __ tst(tmp1);
2825 __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
2826 __ delayed()->nop();
2827 __ st_ptr(recv, recv_addr);
2828 __ set(DataLayout::counter_increment, tmp1);
2829 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2830 mdo_offset_bias);
2831 if (i < (VirtualCallData::row_limit() - 1)) {
2832 __ br(Assembler::always, false, Assembler::pt, update_done);
2833 __ delayed()->nop();
2834 }
2835 __ bind(next_test);
2836 }
2837
2838 __ bind(update_done);
2839 }
2840 }
2841 }
2842
2843
2844 void LIR_Assembler::align_backward_branch_target() {
2845 __ align(16);
2846 }
2847
2848
2849 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2850 // make sure we are expecting a delay
2851 // this has the side effect of clearing the delay state
2852 // so we can use _masm instead of _masm->delayed() to do the
2853 // code generation.
2854 __ delayed();
2855
2856 // make sure we only emit one instruction
2857 int offset = code_offset();
2858 op->delay_op()->emit_code(this);
2859 #ifdef ASSERT
2860 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
2861 op->delay_op()->print();
2862 }
2863 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
2864 "only one instruction can go in a delay slot");
2865 #endif
2866
2867 // we may also be emitting the call info for the instruction
2868 // which we are the delay slot of.
2869 CodeEmitInfo * call_info = op->call_info();
2870 if (call_info) {
2871 add_call_info(code_offset(), call_info);
2872 }
2873
2874 if (VerifyStackAtCalls) {
2875 _masm->sub(FP, SP, O7);
2876 _masm->cmp(O7, initial_frame_size_in_bytes());
2877 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
2878 }
2879 }
2880
2881
2882 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2883 assert(left->is_register(), "can only handle registers");
2884
2885 if (left->is_single_cpu()) {
2886 __ neg(left->as_register(), dest->as_register());
2887 } else if (left->is_single_fpu()) {
2888 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
2889 } else if (left->is_double_fpu()) {
2890 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
2891 } else {
2892 assert (left->is_double_cpu(), "Must be a long");
2893 Register Rlow = left->as_register_lo();
2894 Register Rhi = left->as_register_hi();
2895 #ifdef _LP64
2896 __ sub(G0, Rlow, dest->as_register_lo());
2897 #else
2898 __ subcc(G0, Rlow, dest->as_register_lo());
2899 __ subc (G0, Rhi, dest->as_register_hi());
2900 #endif
2901 }
2902 }
2903
2904
2905 void LIR_Assembler::fxch(int i) {
2906 Unimplemented();
2907 }
2908
2909 void LIR_Assembler::fld(int i) {
2910 Unimplemented();
2911 }
2912
2913 void LIR_Assembler::ffree(int i) {
2914 Unimplemented();
2915 }
2916
2917 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2918 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2919
2920 // if tmp is invalid, then the function being called doesn't destroy the thread
2921 if (tmp->is_valid()) {
2922 __ save_thread(tmp->as_register());
2923 }
2924 __ call(dest, relocInfo::runtime_call_type);
2925 __ delayed()->nop();
2926 if (info != NULL) {
2927 add_call_info_here(info);
2928 }
2929 if (tmp->is_valid()) {
2930 __ restore_thread(tmp->as_register());
2931 }
2932
2933 #ifdef ASSERT
2934 __ verify_thread();
2935 #endif // ASSERT
2936 }
2937
2938
2939 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2940 #ifdef _LP64
2941 ShouldNotReachHere();
2942 #endif
2943
2944 NEEDS_CLEANUP;
2945 if (type == T_LONG) {
2946 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
2947
2948 // (extended to allow indexed as well as constant displaced for JSR-166)
2949 Register idx = noreg; // contains either constant offset or index
2950
2951 int disp = mem_addr->disp();
2952 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
2953 if (!Assembler::is_simm13(disp)) {
2954 idx = O7;
2955 __ set(disp, idx);
2956 }
2957 } else {
2958 assert(disp == 0, "not both indexed and disp");
2959 idx = mem_addr->index()->as_register();
2960 }
2961
2962 int null_check_offset = -1;
2963
2964 Register base = mem_addr->base()->as_register();
2965 if (src->is_register() && dest->is_address()) {
2966 // G4 is high half, G5 is low half
2967 if (VM_Version::v9_instructions_work()) {
2968 // clear the top bits of G5, and scale up G4
2969 __ srl (src->as_register_lo(), 0, G5);
2970 __ sllx(src->as_register_hi(), 32, G4);
2971 // combine the two halves into the 64 bits of G4
2972 __ or3(G4, G5, G4);
2973 null_check_offset = __ offset();
2974 if (idx == noreg) {
2975 __ stx(G4, base, disp);
2976 } else {
2977 __ stx(G4, base, idx);
2978 }
2979 } else {
2980 __ mov (src->as_register_hi(), G4);
2981 __ mov (src->as_register_lo(), G5);
2982 null_check_offset = __ offset();
2983 if (idx == noreg) {
2984 __ std(G4, base, disp);
2985 } else {
2986 __ std(G4, base, idx);
2987 }
2988 }
2989 } else if (src->is_address() && dest->is_register()) {
2990 null_check_offset = __ offset();
2991 if (VM_Version::v9_instructions_work()) {
2992 if (idx == noreg) {
2993 __ ldx(base, disp, G5);
2994 } else {
2995 __ ldx(base, idx, G5);
2996 }
2997 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
2998 __ mov (G5, dest->as_register_lo()); // copy low half into lo
2999 } else {
3000 if (idx == noreg) {
3001 __ ldd(base, disp, G4);
3002 } else {
3003 __ ldd(base, idx, G4);
3004 }
3005 // G4 is high half, G5 is low half
3006 __ mov (G4, dest->as_register_hi());
3007 __ mov (G5, dest->as_register_lo());
3008 }
3009 } else {
3010 Unimplemented();
3011 }
3012 if (info != NULL) {
3013 add_debug_info_for_null_check(null_check_offset, info);
3014 }
3015
3016 } else {
3017 // use normal move for all other volatiles since they don't need
3018 // special handling to remain atomic.
3019 move_op(src, dest, type, lir_patch_none, info, false, false);
3020 }
3021 }
3022
3023 void LIR_Assembler::membar() {
3024 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3025 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3026 }
3027
3028 void LIR_Assembler::membar_acquire() {
3029 // no-op on TSO
3030 }
3031
3032 void LIR_Assembler::membar_release() {
3033 // no-op on TSO
3034 }
3035
3036 // Macro to Pack two sequential registers containing 32 bit values
3037 // into a single 64 bit register.
3038 // rs and rs->successor() are packed into rd
3039 // rd and rs may be the same register.
3040 // Note: rs and rs->successor() are destroyed.
3041 void LIR_Assembler::pack64( Register rs, Register rd ) {
3042 __ sllx(rs, 32, rs);
3043 __ srl(rs->successor(), 0, rs->successor());
3044 __ or3(rs, rs->successor(), rd);
3045 }
3046
3047 // Macro to unpack a 64 bit value in a register into
3048 // two sequential registers.
3049 // rd is unpacked into rd and rd->successor()
3050 void LIR_Assembler::unpack64( Register rd ) {
3051 __ mov(rd, rd->successor());
3052 __ srax(rd, 32, rd);
3053 __ sra(rd->successor(), 0, rd->successor());
3054 }
3055
3056
3057 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3058 LIR_Address* addr = addr_opr->as_address_ptr();
3059 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet");
3060 __ add(addr->base()->as_register(), addr->disp(), dest->as_register());
3061 }
3062
3063
3064 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3065 assert(result_reg->is_register(), "check");
3066 __ mov(G2_thread, result_reg->as_register());
3067 }
3068
3069
3070 void LIR_Assembler::peephole(LIR_List* lir) {
3071 LIR_OpList* inst = lir->instructions_list();
3072 for (int i = 0; i < inst->length(); i++) {
3073 LIR_Op* op = inst->at(i);
3074 switch (op->code()) {
3075 case lir_cond_float_branch:
3076 case lir_branch: {
3077 LIR_OpBranch* branch = op->as_OpBranch();
3078 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3079 LIR_Op* delay_op = NULL;
3080 // we'd like to be able to pull following instructions into
3081 // this slot but we don't know enough to do it safely yet so
3082 // only optimize block to block control flow.
3083 if (LIRFillDelaySlots && branch->block()) {
3084 LIR_Op* prev = inst->at(i - 1);
3085 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3086 // swap previous instruction into delay slot
3087 inst->at_put(i - 1, op);
3088 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3089 #ifndef PRODUCT
3090 if (LIRTracePeephole) {
3091 tty->print_cr("delayed");
3092 inst->at(i - 1)->print();
3093 inst->at(i)->print();
3094 }
3095 #endif
3096 continue;
3097 }
3098 }
3099
3100 if (!delay_op) {
3101 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3102 }
3103 inst->insert_before(i + 1, delay_op);
3104 break;
3105 }
3106 case lir_static_call:
3107 case lir_virtual_call:
3108 case lir_icvirtual_call:
3109 case lir_optvirtual_call: {
3110 LIR_Op* delay_op = NULL;
3111 LIR_Op* prev = inst->at(i - 1);
3112 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3113 (op->code() != lir_virtual_call ||
3114 !prev->result_opr()->is_single_cpu() ||
3115 prev->result_opr()->as_register() != O0) &&
3116 LIR_Assembler::is_single_instruction(prev)) {
3117 // Only moves without info can be put into the delay slot.
3118 // Also don't allow the setup of the receiver in the delay
3119 // slot for vtable calls.
3120 inst->at_put(i - 1, op);
3121 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3122 #ifndef PRODUCT
3123 if (LIRTracePeephole) {
3124 tty->print_cr("delayed");
3125 inst->at(i - 1)->print();
3126 inst->at(i)->print();
3127 }
3128 #endif
3129 continue;
3130 }
3131
3132 if (!delay_op) {
3133 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3134 inst->insert_before(i + 1, delay_op);
3135 }
3136 break;
3137 }
3138 }
3139 }
3140 }
3141
3142
3143
3144
3145 #undef __