src/cpu/x86/vm/vm_version_x86.cpp

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rev 2190 : make no sw prefetch default for family 15h
rev 2191 : adjust rule for choosing no sw prefetch


 419       if( supports_sse4a() ) {
 420         UseXmmI2F = true;
 421       } else {
 422         UseXmmI2F = false;
 423       }
 424     }
 425     if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
 426       if( supports_sse4a() ) {
 427         UseXmmI2D = true;
 428       } else {
 429         UseXmmI2D = false;
 430       }
 431     }
 432 
 433     // Use count leading zeros count instruction if available.
 434     if (supports_lzcnt()) {
 435       if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
 436         UseCountLeadingZerosInstruction = true;
 437       }
 438     }







 439   }
 440 
 441   if( is_intel() ) { // Intel cpus specific settings
 442     if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
 443       UseStoreImmI16 = false; // don't use it on Intel cpus
 444     }
 445     if( cpu_family() == 6 || cpu_family() == 15 ) {
 446       if( FLAG_IS_DEFAULT(UseAddressNop) ) {
 447         // Use it on all Intel cpus starting from PentiumPro
 448         UseAddressNop = true;
 449       }
 450     }
 451     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
 452       UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
 453     }
 454     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
 455       if( supports_sse3() ) {
 456         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
 457       } else {
 458         UseXmmRegToRegMoveAll = false;




 419       if( supports_sse4a() ) {
 420         UseXmmI2F = true;
 421       } else {
 422         UseXmmI2F = false;
 423       }
 424     }
 425     if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
 426       if( supports_sse4a() ) {
 427         UseXmmI2D = true;
 428       } else {
 429         UseXmmI2D = false;
 430       }
 431     }
 432 
 433     // Use count leading zeros count instruction if available.
 434     if (supports_lzcnt()) {
 435       if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
 436         UseCountLeadingZerosInstruction = true;
 437       }
 438     }
 439 
 440     // On family 21 processors default is no sw prefetch
 441     if ( cpu_family() == 21 ) {
 442       if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
 443         AllocatePrefetchStyle = 0;
 444       }
 445     }
 446   }
 447 
 448   if( is_intel() ) { // Intel cpus specific settings
 449     if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
 450       UseStoreImmI16 = false; // don't use it on Intel cpus
 451     }
 452     if( cpu_family() == 6 || cpu_family() == 15 ) {
 453       if( FLAG_IS_DEFAULT(UseAddressNop) ) {
 454         // Use it on all Intel cpus starting from PentiumPro
 455         UseAddressNop = true;
 456       }
 457     }
 458     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
 459       UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
 460     }
 461     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
 462       if( supports_sse3() ) {
 463         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
 464       } else {
 465         UseXmmRegToRegMoveAll = false;