1 //
2 // Copyright (c) 2011, 2014, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2014 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
266
267 // It's worth about 1% on SPEC geomean to get this right.
268
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
279
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
283
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
286
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
305
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
309
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
319
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
327
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
331
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
334
335 // scratch register
336 F0, F0_H,
337
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
352
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
373
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
376
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
386
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
397
398 //-------Architecture Description Register Classes-----------------------
399
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
402
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
408
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
412
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
417
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29*/ // global TOC
451 /*R30*/ // Narrow Oop Base
452 R31
453 );
454
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29*/
488 /*R30*/ // Narrow Oop Base
489 R31
490 );
491
492 // Complement-required-in-pipeline operands for narrow oops.
493 reg_class bits32_reg_ro_not_complement (
494 /*R0*/ // R0
495 R1, // SP
496 R2, // TOC
497 R3,
498 R4,
499 R5,
500 R6,
501 R7,
502 R8,
503 R9,
504 R10,
505 R11,
506 R12,
507 /*R13,*/ // system thread id
508 R14,
509 R15,
510 R16, // R16_thread
511 R17,
512 R18,
513 R19,
514 R20,
515 R21,
516 R22,
517 /*R23,
518 R24,
519 R25,
520 R26,
521 R27,
522 R28,*/
523 /*R29,*/ // TODO: let allocator handle TOC!!
524 /*R30,*/
525 R31
526 );
527
528 // Complement-required-in-pipeline operands for narrow oops.
529 // See 64-bit declaration.
530 reg_class bits32_reg_ro_complement (
531 R23,
532 R24,
533 R25,
534 R26,
535 R27,
536 R28
537 );
538
539 reg_class rscratch1_bits32_reg(R11);
540 reg_class rscratch2_bits32_reg(R12);
541 reg_class rarg1_bits32_reg(R3);
542 reg_class rarg2_bits32_reg(R4);
543 reg_class rarg3_bits32_reg(R5);
544 reg_class rarg4_bits32_reg(R6);
545
546 // ----------------------------
547 // 64 Bit Register Classes
548 // ----------------------------
549 // 64-bit build means 64-bit pointers means hi/lo pairs
550
551 reg_class rscratch1_bits64_reg(R11_H, R11);
552 reg_class rscratch2_bits64_reg(R12_H, R12);
553 reg_class rarg1_bits64_reg(R3_H, R3);
554 reg_class rarg2_bits64_reg(R4_H, R4);
555 reg_class rarg3_bits64_reg(R5_H, R5);
556 reg_class rarg4_bits64_reg(R6_H, R6);
557 // Thread register, 'written' by tlsLoadP, see there.
558 reg_class thread_bits64_reg(R16_H, R16);
559
560 reg_class r19_bits64_reg(R19_H, R19);
561
562 // 64 bit registers that can be read and written i.e. these registers
563 // can be dest (or src) of normal instructions.
564 reg_class bits64_reg_rw(
565 /*R0_H, R0*/ // R0
566 /*R1_H, R1*/ // SP
567 R2_H, R2, // TOC
568 R3_H, R3,
569 R4_H, R4,
570 R5_H, R5,
571 R6_H, R6,
572 R7_H, R7,
573 R8_H, R8,
574 R9_H, R9,
575 R10_H, R10,
576 R11_H, R11,
577 R12_H, R12,
578 /*R13_H, R13*/ // system thread id
579 R14_H, R14,
580 R15_H, R15,
581 /*R16_H, R16*/ // R16_thread
582 R17_H, R17,
583 R18_H, R18,
584 R19_H, R19,
585 R20_H, R20,
586 R21_H, R21,
587 R22_H, R22,
588 R23_H, R23,
589 R24_H, R24,
590 R25_H, R25,
591 R26_H, R26,
592 R27_H, R27,
593 R28_H, R28,
594 /*R29_H, R29*/
595 /*R30_H, R30*/
596 R31_H, R31
597 );
598
599 // 64 bit registers used excluding r2, r11 and r12
600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
601 // r2, r11 and r12 internally.
602 reg_class bits64_reg_leaf_call(
603 /*R0_H, R0*/ // R0
604 /*R1_H, R1*/ // SP
605 /*R2_H, R2*/ // TOC
606 R3_H, R3,
607 R4_H, R4,
608 R5_H, R5,
609 R6_H, R6,
610 R7_H, R7,
611 R8_H, R8,
612 R9_H, R9,
613 R10_H, R10,
614 /*R11_H, R11*/
615 /*R12_H, R12*/
616 /*R13_H, R13*/ // system thread id
617 R14_H, R14,
618 R15_H, R15,
619 /*R16_H, R16*/ // R16_thread
620 R17_H, R17,
621 R18_H, R18,
622 R19_H, R19,
623 R20_H, R20,
624 R21_H, R21,
625 R22_H, R22,
626 R23_H, R23,
627 R24_H, R24,
628 R25_H, R25,
629 R26_H, R26,
630 R27_H, R27,
631 R28_H, R28,
632 /*R29_H, R29*/
633 /*R30_H, R30*/
634 R31_H, R31
635 );
636
637 // Used to hold the TOC to avoid collisions with expanded DynamicCall
638 // which uses r19 as inline cache internally and expanded LeafCall which uses
639 // r2, r11 and r12 internally.
640 reg_class bits64_constant_table_base(
641 /*R0_H, R0*/ // R0
642 /*R1_H, R1*/ // SP
643 /*R2_H, R2*/ // TOC
644 R3_H, R3,
645 R4_H, R4,
646 R5_H, R5,
647 R6_H, R6,
648 R7_H, R7,
649 R8_H, R8,
650 R9_H, R9,
651 R10_H, R10,
652 /*R11_H, R11*/
653 /*R12_H, R12*/
654 /*R13_H, R13*/ // system thread id
655 R14_H, R14,
656 R15_H, R15,
657 /*R16_H, R16*/ // R16_thread
658 R17_H, R17,
659 R18_H, R18,
660 /*R19_H, R19*/
661 R20_H, R20,
662 R21_H, R21,
663 R22_H, R22,
664 R23_H, R23,
665 R24_H, R24,
666 R25_H, R25,
667 R26_H, R26,
668 R27_H, R27,
669 R28_H, R28,
670 /*R29_H, R29*/
671 /*R30_H, R30*/
672 R31_H, R31
673 );
674
675 // 64 bit registers that can only be read i.e. these registers can
676 // only be src of all instructions.
677 reg_class bits64_reg_ro(
678 /*R0_H, R0*/ // R0
679 R1_H, R1,
680 R2_H, R2, // TOC
681 R3_H, R3,
682 R4_H, R4,
683 R5_H, R5,
684 R6_H, R6,
685 R7_H, R7,
686 R8_H, R8,
687 R9_H, R9,
688 R10_H, R10,
689 R11_H, R11,
690 R12_H, R12,
691 /*R13_H, R13*/ // system thread id
692 R14_H, R14,
693 R15_H, R15,
694 R16_H, R16, // R16_thread
695 R17_H, R17,
696 R18_H, R18,
697 R19_H, R19,
698 R20_H, R20,
699 R21_H, R21,
700 R22_H, R22,
701 R23_H, R23,
702 R24_H, R24,
703 R25_H, R25,
704 R26_H, R26,
705 R27_H, R27,
706 R28_H, R28,
707 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
708 /*R30_H, R30,*/
709 R31_H, R31
710 );
711
712 // Complement-required-in-pipeline operands.
713 reg_class bits64_reg_ro_not_complement (
714 /*R0_H, R0*/ // R0
715 R1_H, R1, // SP
716 R2_H, R2, // TOC
717 R3_H, R3,
718 R4_H, R4,
719 R5_H, R5,
720 R6_H, R6,
721 R7_H, R7,
722 R8_H, R8,
723 R9_H, R9,
724 R10_H, R10,
725 R11_H, R11,
726 R12_H, R12,
727 /*R13_H, R13*/ // system thread id
728 R14_H, R14,
729 R15_H, R15,
730 R16_H, R16, // R16_thread
731 R17_H, R17,
732 R18_H, R18,
733 R19_H, R19,
734 R20_H, R20,
735 R21_H, R21,
736 R22_H, R22,
737 /*R23_H, R23,
738 R24_H, R24,
739 R25_H, R25,
740 R26_H, R26,
741 R27_H, R27,
742 R28_H, R28,*/
743 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
744 /*R30_H, R30,*/
745 R31_H, R31
746 );
747
748 // Complement-required-in-pipeline operands.
749 // This register mask is used for the trap instructions that implement
750 // the null checks on AIX. The trap instruction first computes the
751 // complement of the value it shall trap on. Because of this, the
752 // instruction can not be scheduled in the same cycle as an other
753 // instruction reading the normal value of the same register. So we
754 // force the value to check into 'bits64_reg_ro_not_complement'
755 // and then copy it to 'bits64_reg_ro_complement' for the trap.
756 reg_class bits64_reg_ro_complement (
757 R23_H, R23,
758 R24_H, R24,
759 R25_H, R25,
760 R26_H, R26,
761 R27_H, R27,
762 R28_H, R28
763 );
764
765
766 // ----------------------------
767 // Special Class for Condition Code Flags Register
768
769 reg_class int_flags(
770 /*CCR0*/ // scratch
771 /*CCR1*/ // scratch
772 /*CCR2*/ // nv!
773 /*CCR3*/ // nv!
774 /*CCR4*/ // nv!
775 CCR5,
776 CCR6,
777 CCR7
778 );
779
780 reg_class int_flags_CR0(CCR0);
781 reg_class int_flags_CR1(CCR1);
782 reg_class int_flags_CR6(CCR6);
783 reg_class ctr_reg(SR_CTR);
784
785 // ----------------------------
786 // Float Register Classes
787 // ----------------------------
788
789 reg_class flt_reg(
790 /*F0*/ // scratch
791 F1,
792 F2,
793 F3,
794 F4,
795 F5,
796 F6,
797 F7,
798 F8,
799 F9,
800 F10,
801 F11,
802 F12,
803 F13,
804 F14, // nv!
805 F15, // nv!
806 F16, // nv!
807 F17, // nv!
808 F18, // nv!
809 F19, // nv!
810 F20, // nv!
811 F21, // nv!
812 F22, // nv!
813 F23, // nv!
814 F24, // nv!
815 F25, // nv!
816 F26, // nv!
817 F27, // nv!
818 F28, // nv!
819 F29, // nv!
820 F30, // nv!
821 F31 // nv!
822 );
823
824 // Double precision float registers have virtual `high halves' that
825 // are needed by the allocator.
826 reg_class dbl_reg(
827 /*F0, F0_H*/ // scratch
828 F1, F1_H,
829 F2, F2_H,
830 F3, F3_H,
831 F4, F4_H,
832 F5, F5_H,
833 F6, F6_H,
834 F7, F7_H,
835 F8, F8_H,
836 F9, F9_H,
837 F10, F10_H,
838 F11, F11_H,
839 F12, F12_H,
840 F13, F13_H,
841 F14, F14_H, // nv!
842 F15, F15_H, // nv!
843 F16, F16_H, // nv!
844 F17, F17_H, // nv!
845 F18, F18_H, // nv!
846 F19, F19_H, // nv!
847 F20, F20_H, // nv!
848 F21, F21_H, // nv!
849 F22, F22_H, // nv!
850 F23, F23_H, // nv!
851 F24, F24_H, // nv!
852 F25, F25_H, // nv!
853 F26, F26_H, // nv!
854 F27, F27_H, // nv!
855 F28, F28_H, // nv!
856 F29, F29_H, // nv!
857 F30, F30_H, // nv!
858 F31, F31_H // nv!
859 );
860
861 %}
862
863 //----------DEFINITION BLOCK---------------------------------------------------
864 // Define name --> value mappings to inform the ADLC of an integer valued name
865 // Current support includes integer values in the range [0, 0x7FFFFFFF]
866 // Format:
867 // int_def <name> ( <int_value>, <expression>);
868 // Generated Code in ad_<arch>.hpp
869 // #define <name> (<expression>)
870 // // value == <int_value>
871 // Generated code in ad_<arch>.cpp adlc_verification()
872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
873 //
874 definitions %{
875 // The default cost (of an ALU instruction).
876 int_def DEFAULT_COST_LOW ( 30, 30);
877 int_def DEFAULT_COST ( 100, 100);
878 int_def HUGE_COST (1000000, 1000000);
879
880 // Memory refs
881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
883
884 // Branches are even more expensive.
885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
886 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
887 %}
888
889
890 //----------SOURCE BLOCK-------------------------------------------------------
891 // This is a block of C++ code which provides values, functions, and
892 // definitions necessary in the rest of the architecture description.
893 source_hpp %{
894 // Header information of the source block.
895 // Method declarations/definitions which are used outside
896 // the ad-scope can conveniently be defined here.
897 //
898 // To keep related declarations/definitions/uses close together,
899 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
900
901 // Returns true if Node n is followed by a MemBar node that
902 // will do an acquire. If so, this node must not do the acquire
903 // operation.
904 bool followed_by_acquire(const Node *n);
905 %}
906
907 source %{
908
909 // Optimize load-acquire.
910 //
911 // Check if acquire is unnecessary due to following operation that does
912 // acquire anyways.
913 // Walk the pattern:
914 //
915 // n: Load.acq
916 // |
917 // MemBarAcquire
918 // | |
919 // Proj(ctrl) Proj(mem)
920 // | |
921 // MemBarRelease/Volatile
922 //
923 bool followed_by_acquire(const Node *load) {
924 assert(load->is_Load(), "So far implemented only for loads.");
925
926 // Find MemBarAcquire.
927 const Node *mba = NULL;
928 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
929 const Node *out = load->fast_out(i);
930 if (out->Opcode() == Op_MemBarAcquire) {
931 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
932 mba = out;
933 break;
934 }
935 }
936 if (!mba) return false;
937
938 // Find following MemBar node.
939 //
940 // The following node must be reachable by control AND memory
941 // edge to assure no other operations are in between the two nodes.
942 //
943 // So first get the Proj node, mem_proj, to use it to iterate forward.
944 Node *mem_proj = NULL;
945 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
946 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
947 assert(mem_proj->is_Proj(), "only projections here");
948 ProjNode *proj = mem_proj->as_Proj();
949 if (proj->_con == TypeFunc::Memory &&
950 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
951 break;
952 }
953 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
954
955 // Search MemBar behind Proj. If there are other memory operations
956 // behind the Proj we lost.
957 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
958 Node *x = mem_proj->fast_out(j);
959 // Proj might have an edge to a store or load node which precedes the membar.
960 if (x->is_Mem()) return false;
961
962 // On PPC64 release and volatile are implemented by an instruction
963 // that also has acquire semantics. I.e. there is no need for an
964 // acquire before these.
965 int xop = x->Opcode();
966 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
967 // Make sure we're not missing Call/Phi/MergeMem by checking
968 // control edges. The control edge must directly lead back
969 // to the MemBarAcquire
970 Node *ctrl_proj = x->in(0);
971 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
972 return true;
973 }
974 }
975 }
976
977 return false;
978 }
979
980 #define __ _masm.
981
982 // Tertiary op of a LoadP or StoreP encoding.
983 #define REGP_OP true
984
985 // ****************************************************************************
986
987 // REQUIRED FUNCTIONALITY
988
989 // !!!!! Special hack to get all type of calls to specify the byte offset
990 // from the start of the call to the point where the return address
991 // will point.
992
993 // PPC port: Removed use of lazy constant construct.
994
995 int MachCallStaticJavaNode::ret_addr_offset() {
996 // It's only a single branch-and-link instruction.
997 return 4;
998 }
999
1000 int MachCallDynamicJavaNode::ret_addr_offset() {
1001 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
1002 // postalloc expanded calls if we use inline caches and do not update method data.
1003 if (UseInlineCaches)
1004 return 4;
1005
1006 int vtable_index = this->_vtable_index;
1007 if (vtable_index < 0) {
1008 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
1009 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1010 return 12;
1011 } else {
1012 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
1013 return 24;
1014 }
1015 }
1016
1017 int MachCallRuntimeNode::ret_addr_offset() {
1018 #if defined(ABI_ELFv2)
1019 return 28;
1020 #else
1021 return 40;
1022 #endif
1023 }
1024
1025 //=============================================================================
1026
1027 // condition code conversions
1028
1029 static int cc_to_boint(int cc) {
1030 return Assembler::bcondCRbiIs0 | (cc & 8);
1031 }
1032
1033 static int cc_to_inverse_boint(int cc) {
1034 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1035 }
1036
1037 static int cc_to_biint(int cc, int flags_reg) {
1038 return (flags_reg << 2) | (cc & 3);
1039 }
1040
1041 //=============================================================================
1042
1043 // Compute padding required for nodes which need alignment. The padding
1044 // is the number of bytes (not instructions) which will be inserted before
1045 // the instruction. The padding must match the size of a NOP instruction.
1046
1047 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
1048 return (3*4-current_offset)&31;
1049 }
1050
1051 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
1052 return (2*4-current_offset)&31;
1053 }
1054
1055 int string_indexOf_immNode::compute_padding(int current_offset) const {
1056 return (3*4-current_offset)&31;
1057 }
1058
1059 int string_indexOfNode::compute_padding(int current_offset) const {
1060 return (1*4-current_offset)&31;
1061 }
1062
1063 int string_compareNode::compute_padding(int current_offset) const {
1064 return (4*4-current_offset)&31;
1065 }
1066
1067 int string_equals_immNode::compute_padding(int current_offset) const {
1068 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
1069 return (2*4-current_offset)&31;
1070 }
1071
1072 int string_equalsNode::compute_padding(int current_offset) const {
1073 return (7*4-current_offset)&31;
1074 }
1075
1076 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
1077 return (2*4-current_offset)&31;
1078 }
1079
1080 //=============================================================================
1081
1082 // Indicate if the safepoint node needs the polling page as an input.
1083 bool SafePointNode::needs_polling_address_input() {
1084 // The address is loaded from thread by a seperate node.
1085 return true;
1086 }
1087
1088 //=============================================================================
1089
1090 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1091 void emit_break(CodeBuffer &cbuf) {
1092 MacroAssembler _masm(&cbuf);
1093 __ illtrap();
1094 }
1095
1096 #ifndef PRODUCT
1097 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1098 st->print("BREAKPOINT");
1099 }
1100 #endif
1101
1102 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1103 emit_break(cbuf);
1104 }
1105
1106 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1107 return MachNode::size(ra_);
1108 }
1109
1110 //=============================================================================
1111
1112 void emit_nop(CodeBuffer &cbuf) {
1113 MacroAssembler _masm(&cbuf);
1114 __ nop();
1115 }
1116
1117 static inline void emit_long(CodeBuffer &cbuf, int value) {
1118 *((int*)(cbuf.insts_end())) = value;
1119 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1120 }
1121
1122 //=============================================================================
1123
1124 %} // interrupt source
1125
1126 source_hpp %{ // Header information of the source block.
1127
1128 //--------------------------------------------------------------
1129 //---< Used for optimization in Compile::Shorten_branches >---
1130 //--------------------------------------------------------------
1131
1132 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1133
1134 class CallStubImpl {
1135
1136 public:
1137
1138 // Emit call stub, compiled java to interpreter.
1139 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1140
1141 // Size of call trampoline stub.
1142 // This doesn't need to be accurate to the byte, but it
1143 // must be larger than or equal to the real size of the stub.
1144 static uint size_call_trampoline() {
1145 return trampoline_stub_size;
1146 }
1147
1148 // number of relocations needed by a call trampoline stub
1149 static uint reloc_call_trampoline() {
1150 return 5;
1151 }
1152
1153 };
1154
1155 %} // end source_hpp
1156
1157 source %{
1158
1159 // Emit a trampoline stub for a call to a target which is too far away.
1160 //
1161 // code sequences:
1162 //
1163 // call-site:
1164 // branch-and-link to <destination> or <trampoline stub>
1165 //
1166 // Related trampoline stub for this call-site in the stub section:
1167 // load the call target from the constant pool
1168 // branch via CTR (LR/link still points to the call-site above)
1169
1170 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1171 // Start the stub.
1172 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1173 if (stub == NULL) {
1174 Compile::current()->env()->record_out_of_memory_failure();
1175 return;
1176 }
1177
1178 // For java_to_interp stubs we use R11_scratch1 as scratch register
1179 // and in call trampoline stubs we use R12_scratch2. This way we
1180 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1181 Register reg_scratch = R12_scratch2;
1182
1183 // Create a trampoline stub relocation which relates this trampoline stub
1184 // with the call instruction at insts_call_instruction_offset in the
1185 // instructions code-section.
1186 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1187 const int stub_start_offset = __ offset();
1188
1189 // Now, create the trampoline stub's code:
1190 // - load the TOC
1191 // - load the call target from the constant pool
1192 // - call
1193 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1194 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1195 __ mtctr(reg_scratch);
1196 __ bctr();
1197
1198 const address stub_start_addr = __ addr_at(stub_start_offset);
1199
1200 // FIXME: Assert that the trampoline stub can be identified and patched.
1201
1202 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1203 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1204 "encoded offset into the constant pool must match");
1205 // Trampoline_stub_size should be good.
1206 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1207 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1208
1209 // End the stub.
1210 __ end_a_stub();
1211 }
1212
1213 //=============================================================================
1214
1215 // Emit an inline branch-and-link call and a related trampoline stub.
1216 //
1217 // code sequences:
1218 //
1219 // call-site:
1220 // branch-and-link to <destination> or <trampoline stub>
1221 //
1222 // Related trampoline stub for this call-site in the stub section:
1223 // load the call target from the constant pool
1224 // branch via CTR (LR/link still points to the call-site above)
1225 //
1226
1227 typedef struct {
1228 int insts_call_instruction_offset;
1229 int ret_addr_offset;
1230 } EmitCallOffsets;
1231
1232 // Emit a branch-and-link instruction that branches to a trampoline.
1233 // - Remember the offset of the branch-and-link instruction.
1234 // - Add a relocation at the branch-and-link instruction.
1235 // - Emit a branch-and-link.
1236 // - Remember the return pc offset.
1237 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1238 EmitCallOffsets offsets = { -1, -1 };
1239 const int start_offset = __ offset();
1240 offsets.insts_call_instruction_offset = __ offset();
1241
1242 // No entry point given, use the current pc.
1243 if (entry_point == NULL) entry_point = __ pc();
1244
1245 if (!Compile::current()->in_scratch_emit_size()) {
1246 // Put the entry point as a constant into the constant pool.
1247 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1248 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1249
1250 // Emit the trampoline stub which will be related to the branch-and-link below.
1251 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1252 __ relocate(rtype);
1253 }
1254
1255 // Note: At this point we do not have the address of the trampoline
1256 // stub, and the entry point might be too far away for bl, so __ pc()
1257 // serves as dummy and the bl will be patched later.
1258 __ bl((address) __ pc());
1259
1260 offsets.ret_addr_offset = __ offset() - start_offset;
1261
1262 return offsets;
1263 }
1264
1265 //=============================================================================
1266
1267 // Factory for creating loadConL* nodes for large/small constant pool.
1268
1269 static inline jlong replicate_immF(float con) {
1270 // Replicate float con 2 times and pack into vector.
1271 int val = *((int*)&con);
1272 jlong lval = val;
1273 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1274 return lval;
1275 }
1276
1277 //=============================================================================
1278
1279 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1280 int Compile::ConstantTable::calculate_table_base_offset() const {
1281 return 0; // absolute addressing, no offset
1282 }
1283
1284 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1285 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1286 iRegPdstOper *op_dst = new iRegPdstOper();
1287 MachNode *m1 = new loadToc_hiNode();
1288 MachNode *m2 = new loadToc_loNode();
1289
1290 m1->add_req(NULL);
1291 m2->add_req(NULL, m1);
1292 m1->_opnds[0] = op_dst;
1293 m2->_opnds[0] = op_dst;
1294 m2->_opnds[1] = op_dst;
1295 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1296 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1297 nodes->push(m1);
1298 nodes->push(m2);
1299 }
1300
1301 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1302 // Is postalloc expanded.
1303 ShouldNotReachHere();
1304 }
1305
1306 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1307 return 0;
1308 }
1309
1310 #ifndef PRODUCT
1311 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1312 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1313 }
1314 #endif
1315
1316 //=============================================================================
1317
1318 #ifndef PRODUCT
1319 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1320 Compile* C = ra_->C;
1321 const long framesize = C->frame_slots() << LogBytesPerInt;
1322
1323 st->print("PROLOG\n\t");
1324 if (C->need_stack_bang(framesize)) {
1325 st->print("stack_overflow_check\n\t");
1326 }
1327
1328 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1329 st->print("save return pc\n\t");
1330 st->print("push frame %ld\n\t", -framesize);
1331 }
1332 }
1333 #endif
1334
1335 // Macro used instead of the common __ to emulate the pipes of PPC.
1336 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1337 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1338 // still no scheduling of this code is possible, the micro scheduler is aware of the
1339 // code and can update its internal data. The following mechanism is used to achieve this:
1340 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1341 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1342 #if 0 // TODO: PPC port
1343 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1344 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1345 _masm.
1346 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1347 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1348 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1349 C->hb_scheduling()->_pdScheduling->advance_offset
1350 #else
1351 #define ___(op) if (UsePower6SchedulerPPC64) \
1352 Unimplemented(); \
1353 _masm.
1354 #define ___stop if (UsePower6SchedulerPPC64) \
1355 Unimplemented()
1356 #define ___advance if (UsePower6SchedulerPPC64) \
1357 Unimplemented()
1358 #endif
1359
1360 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1361 Compile* C = ra_->C;
1362 MacroAssembler _masm(&cbuf);
1363
1364 const long framesize = C->frame_size_in_bytes();
1365 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1366
1367 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1368
1369 const Register return_pc = R20; // Must match return_addr() in frame section.
1370 const Register callers_sp = R21;
1371 const Register push_frame_temp = R22;
1372 const Register toc_temp = R23;
1373 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1374
1375 if (method_is_frameless) {
1376 // Add nop at beginning of all frameless methods to prevent any
1377 // oop instructions from getting overwritten by make_not_entrant
1378 // (patching attempt would fail).
1379 ___(nop) nop();
1380 } else {
1381 // Get return pc.
1382 ___(mflr) mflr(return_pc);
1383 }
1384
1385 // Calls to C2R adapters often do not accept exceptional returns.
1386 // We require that their callers must bang for them. But be
1387 // careful, because some VM calls (such as call site linkage) can
1388 // use several kilobytes of stack. But the stack safety zone should
1389 // account for that. See bugs 4446381, 4468289, 4497237.
1390
1391 int bangsize = C->bang_size_in_bytes();
1392 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1393 if (C->need_stack_bang(bangsize) && UseStackBanging) {
1394 // Unfortunately we cannot use the function provided in
1395 // assembler.cpp as we have to emulate the pipes. So I had to
1396 // insert the code of generate_stack_overflow_check(), see
1397 // assembler.cpp for some illuminative comments.
1398 const int page_size = os::vm_page_size();
1399 int bang_end = StackShadowPages * page_size;
1400
1401 // This is how far the previous frame's stack banging extended.
1402 const int bang_end_safe = bang_end;
1403
1404 if (bangsize > page_size) {
1405 bang_end += bangsize;
1406 }
1407
1408 int bang_offset = bang_end_safe;
1409
1410 while (bang_offset <= bang_end) {
1411 // Need at least one stack bang at end of shadow zone.
1412
1413 // Again I had to copy code, this time from assembler_ppc64.cpp,
1414 // bang_stack_with_offset - see there for comments.
1415
1416 // Stack grows down, caller passes positive offset.
1417 assert(bang_offset > 0, "must bang with positive offset");
1418
1419 long stdoffset = -bang_offset;
1420
1421 if (Assembler::is_simm(stdoffset, 16)) {
1422 // Signed 16 bit offset, a simple std is ok.
1423 if (UseLoadInstructionsForStackBangingPPC64) {
1424 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1425 } else {
1426 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1427 }
1428 } else if (Assembler::is_simm(stdoffset, 31)) {
1429 // Use largeoffset calculations for addis & ld/std.
1430 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1431 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1432
1433 Register tmp = R11;
1434 ___(addis) addis(tmp, R1_SP, hi);
1435 if (UseLoadInstructionsForStackBangingPPC64) {
1436 ___(ld) ld(R0, lo, tmp);
1437 } else {
1438 ___(std) std(R0, lo, tmp);
1439 }
1440 } else {
1441 ShouldNotReachHere();
1442 }
1443
1444 bang_offset += page_size;
1445 }
1446 // R11 trashed
1447 } // C->need_stack_bang(framesize) && UseStackBanging
1448
1449 unsigned int bytes = (unsigned int)framesize;
1450 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1451 ciMethod *currMethod = C->method();
1452
1453 // Optimized version for most common case.
1454 if (UsePower6SchedulerPPC64 &&
1455 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1456 !(false /* ConstantsALot TODO: PPC port*/)) {
1457 ___(or) mr(callers_sp, R1_SP);
1458 ___(std) std(return_pc, _abi(lr), R1_SP);
1459 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1460 return;
1461 }
1462
1463 if (!method_is_frameless) {
1464 // Get callers sp.
1465 ___(or) mr(callers_sp, R1_SP);
1466
1467 // Push method's frame, modifies SP.
1468 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1469 // The ABI is already accounted for in 'framesize' via the
1470 // 'out_preserve' area.
1471 Register tmp = push_frame_temp;
1472 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1473 if (Assembler::is_simm(-offset, 16)) {
1474 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1475 } else {
1476 long x = -offset;
1477 // Had to insert load_const(tmp, -offset).
1478 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1479 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1480 ___(rldicr) sldi(tmp, tmp, 32);
1481 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1482 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1483
1484 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1485 }
1486 }
1487 #if 0 // TODO: PPC port
1488 // For testing large constant pools, emit a lot of constants to constant pool.
1489 // "Randomize" const_size.
1490 if (ConstantsALot) {
1491 const int num_consts = const_size();
1492 for (int i = 0; i < num_consts; i++) {
1493 __ long_constant(0xB0B5B00BBABE);
1494 }
1495 }
1496 #endif
1497 if (!method_is_frameless) {
1498 // Save return pc.
1499 ___(std) std(return_pc, _abi(lr), callers_sp);
1500 }
1501 }
1502 #undef ___
1503 #undef ___stop
1504 #undef ___advance
1505
1506 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1507 // Variable size. determine dynamically.
1508 return MachNode::size(ra_);
1509 }
1510
1511 int MachPrologNode::reloc() const {
1512 // Return number of relocatable values contained in this instruction.
1513 return 1; // 1 reloc entry for load_const(toc).
1514 }
1515
1516 //=============================================================================
1517
1518 #ifndef PRODUCT
1519 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1520 Compile* C = ra_->C;
1521
1522 st->print("EPILOG\n\t");
1523 st->print("restore return pc\n\t");
1524 st->print("pop frame\n\t");
1525
1526 if (do_polling() && C->is_method_compilation()) {
1527 st->print("touch polling page\n\t");
1528 }
1529 }
1530 #endif
1531
1532 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1533 Compile* C = ra_->C;
1534 MacroAssembler _masm(&cbuf);
1535
1536 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1537 assert(framesize >= 0, "negative frame-size?");
1538
1539 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1540 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1541 const Register return_pc = R11;
1542 const Register polling_page = R12;
1543
1544 if (!method_is_frameless) {
1545 // Restore return pc relative to callers' sp.
1546 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1547 }
1548
1549 if (method_needs_polling) {
1550 if (LoadPollAddressFromThread) {
1551 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1552 Unimplemented();
1553 } else {
1554 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1555 }
1556 }
1557
1558 if (!method_is_frameless) {
1559 // Move return pc to LR.
1560 __ mtlr(return_pc);
1561 // Pop frame (fixed frame-size).
1562 __ addi(R1_SP, R1_SP, (int)framesize);
1563 }
1564
1565 if (method_needs_polling) {
1566 // We need to mark the code position where the load from the safepoint
1567 // polling page was emitted as relocInfo::poll_return_type here.
1568 __ relocate(relocInfo::poll_return_type);
1569 __ load_from_polling_page(polling_page);
1570 }
1571 }
1572
1573 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1574 // Variable size. Determine dynamically.
1575 return MachNode::size(ra_);
1576 }
1577
1578 int MachEpilogNode::reloc() const {
1579 // Return number of relocatable values contained in this instruction.
1580 return 1; // 1 for load_from_polling_page.
1581 }
1582
1583 const Pipeline * MachEpilogNode::pipeline() const {
1584 return MachNode::pipeline_class();
1585 }
1586
1587 // This method seems to be obsolete. It is declared in machnode.hpp
1588 // and defined in all *.ad files, but it is never called. Should we
1589 // get rid of it?
1590 int MachEpilogNode::safepoint_offset() const {
1591 assert(do_polling(), "no return for this epilog node");
1592 return 0;
1593 }
1594
1595 #if 0 // TODO: PPC port
1596 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1597 MacroAssembler _masm(&cbuf);
1598 if (LoadPollAddressFromThread) {
1599 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1600 } else {
1601 _masm.nop();
1602 }
1603 }
1604
1605 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1606 if (LoadPollAddressFromThread) {
1607 return 4;
1608 } else {
1609 return 4;
1610 }
1611 }
1612
1613 #ifndef PRODUCT
1614 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1615 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1616 }
1617 #endif
1618
1619 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1620 return RSCRATCH1_BITS64_REG_mask();
1621 }
1622 #endif // PPC port
1623
1624 // =============================================================================
1625
1626 // Figure out which register class each belongs in: rc_int, rc_float or
1627 // rc_stack.
1628 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1629
1630 static enum RC rc_class(OptoReg::Name reg) {
1631 // Return the register class for the given register. The given register
1632 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1633 // enumeration in adGlobals_ppc.hpp.
1634
1635 if (reg == OptoReg::Bad) return rc_bad;
1636
1637 // We have 64 integer register halves, starting at index 0.
1638 if (reg < 64) return rc_int;
1639
1640 // We have 64 floating-point register halves, starting at index 64.
1641 if (reg < 64+64) return rc_float;
1642
1643 // Between float regs & stack are the flags regs.
1644 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1645
1646 return rc_stack;
1647 }
1648
1649 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1650 bool do_print, Compile* C, outputStream *st) {
1651
1652 assert(opcode == Assembler::LD_OPCODE ||
1653 opcode == Assembler::STD_OPCODE ||
1654 opcode == Assembler::LWZ_OPCODE ||
1655 opcode == Assembler::STW_OPCODE ||
1656 opcode == Assembler::LFD_OPCODE ||
1657 opcode == Assembler::STFD_OPCODE ||
1658 opcode == Assembler::LFS_OPCODE ||
1659 opcode == Assembler::STFS_OPCODE,
1660 "opcode not supported");
1661
1662 if (cbuf) {
1663 int d =
1664 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1665 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1666 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1667 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1668 }
1669 #ifndef PRODUCT
1670 else if (do_print) {
1671 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1672 op_str,
1673 Matcher::regName[reg],
1674 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1675 }
1676 #endif
1677 return 4; // size
1678 }
1679
1680 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1681 Compile* C = ra_->C;
1682
1683 // Get registers to move.
1684 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1685 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1686 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1687 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1688
1689 enum RC src_hi_rc = rc_class(src_hi);
1690 enum RC src_lo_rc = rc_class(src_lo);
1691 enum RC dst_hi_rc = rc_class(dst_hi);
1692 enum RC dst_lo_rc = rc_class(dst_lo);
1693
1694 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1695 if (src_hi != OptoReg::Bad)
1696 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1697 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1698 "expected aligned-adjacent pairs");
1699 // Generate spill code!
1700 int size = 0;
1701
1702 if (src_lo == dst_lo && src_hi == dst_hi)
1703 return size; // Self copy, no move.
1704
1705 // --------------------------------------
1706 // Memory->Memory Spill. Use R0 to hold the value.
1707 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1708 int src_offset = ra_->reg2offset(src_lo);
1709 int dst_offset = ra_->reg2offset(dst_lo);
1710 if (src_hi != OptoReg::Bad) {
1711 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1712 "expected same type of move for high parts");
1713 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1714 if (!cbuf && !do_size) st->print("\n\t");
1715 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1716 } else {
1717 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1718 if (!cbuf && !do_size) st->print("\n\t");
1719 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1720 }
1721 return size;
1722 }
1723
1724 // --------------------------------------
1725 // Check for float->int copy; requires a trip through memory.
1726 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1727 Unimplemented();
1728 }
1729
1730 // --------------------------------------
1731 // Check for integer reg-reg copy.
1732 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1733 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1734 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1735 size = (Rsrc != Rdst) ? 4 : 0;
1736
1737 if (cbuf) {
1738 MacroAssembler _masm(cbuf);
1739 if (size) {
1740 __ mr(Rdst, Rsrc);
1741 }
1742 }
1743 #ifndef PRODUCT
1744 else if (!do_size) {
1745 if (size) {
1746 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1747 } else {
1748 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1749 }
1750 }
1751 #endif
1752 return size;
1753 }
1754
1755 // Check for integer store.
1756 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1757 int dst_offset = ra_->reg2offset(dst_lo);
1758 if (src_hi != OptoReg::Bad) {
1759 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1760 "expected same type of move for high parts");
1761 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1762 } else {
1763 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1764 }
1765 return size;
1766 }
1767
1768 // Check for integer load.
1769 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1770 int src_offset = ra_->reg2offset(src_lo);
1771 if (src_hi != OptoReg::Bad) {
1772 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1773 "expected same type of move for high parts");
1774 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1775 } else {
1776 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1777 }
1778 return size;
1779 }
1780
1781 // Check for float reg-reg copy.
1782 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1783 if (cbuf) {
1784 MacroAssembler _masm(cbuf);
1785 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1786 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1787 __ fmr(Rdst, Rsrc);
1788 }
1789 #ifndef PRODUCT
1790 else if (!do_size) {
1791 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1792 }
1793 #endif
1794 return 4;
1795 }
1796
1797 // Check for float store.
1798 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1799 int dst_offset = ra_->reg2offset(dst_lo);
1800 if (src_hi != OptoReg::Bad) {
1801 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1802 "expected same type of move for high parts");
1803 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1804 } else {
1805 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1806 }
1807 return size;
1808 }
1809
1810 // Check for float load.
1811 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1812 int src_offset = ra_->reg2offset(src_lo);
1813 if (src_hi != OptoReg::Bad) {
1814 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1815 "expected same type of move for high parts");
1816 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1817 } else {
1818 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1819 }
1820 return size;
1821 }
1822
1823 // --------------------------------------------------------------------
1824 // Check for hi bits still needing moving. Only happens for misaligned
1825 // arguments to native calls.
1826 if (src_hi == dst_hi)
1827 return size; // Self copy; no move.
1828
1829 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1830 ShouldNotReachHere(); // Unimplemented
1831 return 0;
1832 }
1833
1834 #ifndef PRODUCT
1835 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1836 if (!ra_)
1837 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1838 else
1839 implementation(NULL, ra_, false, st);
1840 }
1841 #endif
1842
1843 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1844 implementation(&cbuf, ra_, false, NULL);
1845 }
1846
1847 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1848 return implementation(NULL, ra_, true, NULL);
1849 }
1850
1851 #if 0 // TODO: PPC port
1852 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1853 #ifndef PRODUCT
1854 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1855 #endif
1856 assert(ra_->node_regs_max_index() != 0, "");
1857
1858 // Get registers to move.
1859 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1860 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1861 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1862 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1863
1864 enum RC src_lo_rc = rc_class(src_lo);
1865 enum RC dst_lo_rc = rc_class(dst_lo);
1866
1867 if (src_lo == dst_lo && src_hi == dst_hi)
1868 return ppc64Opcode_none; // Self copy, no move.
1869
1870 // --------------------------------------
1871 // Memory->Memory Spill. Use R0 to hold the value.
1872 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1873 return ppc64Opcode_compound;
1874 }
1875
1876 // --------------------------------------
1877 // Check for float->int copy; requires a trip through memory.
1878 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1879 Unimplemented();
1880 }
1881
1882 // --------------------------------------
1883 // Check for integer reg-reg copy.
1884 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1885 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1886 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1887 if (Rsrc == Rdst) {
1888 return ppc64Opcode_none;
1889 } else {
1890 return ppc64Opcode_or;
1891 }
1892 }
1893
1894 // Check for integer store.
1895 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1896 if (src_hi != OptoReg::Bad) {
1897 return ppc64Opcode_std;
1898 } else {
1899 return ppc64Opcode_stw;
1900 }
1901 }
1902
1903 // Check for integer load.
1904 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1905 if (src_hi != OptoReg::Bad) {
1906 return ppc64Opcode_ld;
1907 } else {
1908 return ppc64Opcode_lwz;
1909 }
1910 }
1911
1912 // Check for float reg-reg copy.
1913 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1914 return ppc64Opcode_fmr;
1915 }
1916
1917 // Check for float store.
1918 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1919 if (src_hi != OptoReg::Bad) {
1920 return ppc64Opcode_stfd;
1921 } else {
1922 return ppc64Opcode_stfs;
1923 }
1924 }
1925
1926 // Check for float load.
1927 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1928 if (src_hi != OptoReg::Bad) {
1929 return ppc64Opcode_lfd;
1930 } else {
1931 return ppc64Opcode_lfs;
1932 }
1933 }
1934
1935 // --------------------------------------------------------------------
1936 // Check for hi bits still needing moving. Only happens for misaligned
1937 // arguments to native calls.
1938 if (src_hi == dst_hi)
1939 return ppc64Opcode_none; // Self copy; no move.
1940
1941 ShouldNotReachHere();
1942 return ppc64Opcode_undefined;
1943 }
1944 #endif // PPC port
1945
1946 #ifndef PRODUCT
1947 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1948 st->print("NOP \t// %d nops to pad for loops.", _count);
1949 }
1950 #endif
1951
1952 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1953 MacroAssembler _masm(&cbuf);
1954 // _count contains the number of nops needed for padding.
1955 for (int i = 0; i < _count; i++) {
1956 __ nop();
1957 }
1958 }
1959
1960 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1961 return _count * 4;
1962 }
1963
1964 #ifndef PRODUCT
1965 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1966 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1967 int reg = ra_->get_reg_first(this);
1968 st->print("ADDI %s, SP, %d \t// box node", Matcher::regName[reg], offset);
1969 }
1970 #endif
1971
1972 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1973 MacroAssembler _masm(&cbuf);
1974
1975 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1976 int reg = ra_->get_encode(this);
1977
1978 if (Assembler::is_simm(offset, 16)) {
1979 __ addi(as_Register(reg), R1, offset);
1980 } else {
1981 ShouldNotReachHere();
1982 }
1983 }
1984
1985 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1986 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1987 return 4;
1988 }
1989
1990 #ifndef PRODUCT
1991 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1992 st->print_cr("---- MachUEPNode ----");
1993 st->print_cr("...");
1994 }
1995 #endif
1996
1997 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1998 // This is the unverified entry point.
1999 MacroAssembler _masm(&cbuf);
2000
2001 // Inline_cache contains a klass.
2002 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
2003 Register receiver_klass = R0; // tmp
2004
2005 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
2006 assert(R11_scratch1 == R11, "need prologue scratch register");
2007
2008 // Check for NULL argument if we don't have implicit null checks.
2009 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
2010 if (TrapBasedNullChecks) {
2011 __ trap_null_check(R3_ARG1);
2012 } else {
2013 Label valid;
2014 __ cmpdi(CCR0, R3_ARG1, 0);
2015 __ bne_predict_taken(CCR0, valid);
2016 // We have a null argument, branch to ic_miss_stub.
2017 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2018 relocInfo::runtime_call_type);
2019 __ bind(valid);
2020 }
2021 }
2022 // Assume argument is not NULL, load klass from receiver.
2023 __ load_klass(receiver_klass, R3_ARG1);
2024
2025 if (TrapBasedICMissChecks) {
2026 __ trap_ic_miss_check(receiver_klass, ic_klass);
2027 } else {
2028 Label valid;
2029 __ cmpd(CCR0, receiver_klass, ic_klass);
2030 __ beq_predict_taken(CCR0, valid);
2031 // We have an unexpected klass, branch to ic_miss_stub.
2032 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2033 relocInfo::runtime_call_type);
2034 __ bind(valid);
2035 }
2036
2037 // Argument is valid and klass is as expected, continue.
2038 }
2039
2040 #if 0 // TODO: PPC port
2041 // Optimize UEP code on z (save a load_const() call in main path).
2042 int MachUEPNode::ep_offset() {
2043 return 0;
2044 }
2045 #endif
2046
2047 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
2048 // Variable size. Determine dynamically.
2049 return MachNode::size(ra_);
2050 }
2051
2052 //=============================================================================
2053
2054 %} // interrupt source
2055
2056 source_hpp %{ // Header information of the source block.
2057
2058 class HandlerImpl {
2059
2060 public:
2061
2062 static int emit_exception_handler(CodeBuffer &cbuf);
2063 static int emit_deopt_handler(CodeBuffer& cbuf);
2064
2065 static uint size_exception_handler() {
2066 // The exception_handler is a b64_patchable.
2067 return MacroAssembler::b64_patchable_size;
2068 }
2069
2070 static uint size_deopt_handler() {
2071 // The deopt_handler is a bl64_patchable.
2072 return MacroAssembler::bl64_patchable_size;
2073 }
2074
2075 };
2076
2077 %} // end source_hpp
2078
2079 source %{
2080
2081 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
2082 MacroAssembler _masm(&cbuf);
2083
2084 address base = __ start_a_stub(size_exception_handler());
2085 if (base == NULL) return 0; // CodeBuffer::expand failed
2086
2087 int offset = __ offset();
2088 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2089 relocInfo::runtime_call_type);
2090 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2091 __ end_a_stub();
2092
2093 return offset;
2094 }
2095
2096 // The deopt_handler is like the exception handler, but it calls to
2097 // the deoptimization blob instead of jumping to the exception blob.
2098 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2099 MacroAssembler _masm(&cbuf);
2100
2101 address base = __ start_a_stub(size_deopt_handler());
2102 if (base == NULL) return 0; // CodeBuffer::expand failed
2103
2104 int offset = __ offset();
2105 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2106 relocInfo::runtime_call_type);
2107 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2108 __ end_a_stub();
2109
2110 return offset;
2111 }
2112
2113 //=============================================================================
2114
2115 // Use a frame slots bias for frameless methods if accessing the stack.
2116 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2117 if (as_Register(reg_enc) == R1_SP) {
2118 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2119 }
2120 return 0;
2121 }
2122
2123 const bool Matcher::match_rule_supported(int opcode) {
2124 if (!has_match_rule(opcode))
2125 return false;
2126
2127 switch (opcode) {
2128 case Op_SqrtD:
2129 return VM_Version::has_fsqrt();
2130 case Op_CountLeadingZerosI:
2131 case Op_CountLeadingZerosL:
2132 case Op_CountTrailingZerosI:
2133 case Op_CountTrailingZerosL:
2134 if (!UseCountLeadingZerosInstructionsPPC64)
2135 return false;
2136 break;
2137
2138 case Op_PopCountI:
2139 case Op_PopCountL:
2140 return (UsePopCountInstruction && VM_Version::has_popcntw());
2141
2142 case Op_StrComp:
2143 return SpecialStringCompareTo;
2144 case Op_StrEquals:
2145 return SpecialStringEquals;
2146 case Op_StrIndexOf:
2147 return SpecialStringIndexOf;
2148 }
2149
2150 return true; // Per default match rules are supported.
2151 }
2152
2153 int Matcher::regnum_to_fpu_offset(int regnum) {
2154 // No user for this method?
2155 Unimplemented();
2156 return 999;
2157 }
2158
2159 const bool Matcher::convL2FSupported(void) {
2160 // fcfids can do the conversion (>= Power7).
2161 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2162 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2163 }
2164
2165 // Vector width in bytes.
2166 const int Matcher::vector_width_in_bytes(BasicType bt) {
2167 assert(MaxVectorSize == 8, "");
2168 return 8;
2169 }
2170
2171 // Vector ideal reg.
2172 const int Matcher::vector_ideal_reg(int size) {
2173 assert(MaxVectorSize == 8 && size == 8, "");
2174 return Op_RegL;
2175 }
2176
2177 const int Matcher::vector_shift_count_ideal_reg(int size) {
2178 fatal("vector shift is not supported");
2179 return Node::NotAMachineReg;
2180 }
2181
2182 // Limits on vector size (number of elements) loaded into vector.
2183 const int Matcher::max_vector_size(const BasicType bt) {
2184 assert(is_java_primitive(bt), "only primitive type vectors");
2185 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2186 }
2187
2188 const int Matcher::min_vector_size(const BasicType bt) {
2189 return max_vector_size(bt); // Same as max.
2190 }
2191
2192 // PPC doesn't support misaligned vectors store/load.
2193 const bool Matcher::misaligned_vectors_ok() {
2194 return false;
2195 }
2196
2197 // PPC AES support not yet implemented
2198 const bool Matcher::pass_original_key_for_aes() {
2199 return false;
2200 }
2201
2202 // RETURNS: whether this branch offset is short enough that a short
2203 // branch can be used.
2204 //
2205 // If the platform does not provide any short branch variants, then
2206 // this method should return `false' for offset 0.
2207 //
2208 // `Compile::Fill_buffer' will decide on basis of this information
2209 // whether to do the pass `Compile::Shorten_branches' at all.
2210 //
2211 // And `Compile::Shorten_branches' will decide on basis of this
2212 // information whether to replace particular branch sites by short
2213 // ones.
2214 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2215 // Is the offset within the range of a ppc64 pc relative branch?
2216 bool b;
2217
2218 const int safety_zone = 3 * BytesPerInstWord;
2219 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2220 29 - 16 + 1 + 2);
2221 return b;
2222 }
2223
2224 const bool Matcher::isSimpleConstant64(jlong value) {
2225 // Probably always true, even if a temp register is required.
2226 return true;
2227 }
2228 /* TODO: PPC port
2229 // Make a new machine dependent decode node (with its operands).
2230 MachTypeNode *Matcher::make_decode_node() {
2231 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2232 "This method is only implemented for unscaled cOops mode so far");
2233 MachTypeNode *decode = new decodeN_unscaledNode();
2234 decode->set_opnd_array(0, new iRegPdstOper());
2235 decode->set_opnd_array(1, new iRegNsrcOper());
2236 return decode;
2237 }
2238 */
2239 // Threshold size for cleararray.
2240 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2241
2242 // false => size gets scaled to BytesPerLong, ok.
2243 const bool Matcher::init_array_count_is_in_bytes = false;
2244
2245 // Use conditional move (CMOVL) on Power7.
2246 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2247
2248 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2249 // fsel doesn't accept a condition register as input, so this would be slightly different.
2250 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2251
2252 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2253 const bool Matcher::require_postalloc_expand = true;
2254
2255 // Should the Matcher clone shifts on addressing modes, expecting them to
2256 // be subsumed into complex addressing expressions or compute them into
2257 // registers? True for Intel but false for most RISCs.
2258 const bool Matcher::clone_shift_expressions = false;
2259
2260 // Do we need to mask the count passed to shift instructions or does
2261 // the cpu only look at the lower 5/6 bits anyway?
2262 // Off, as masks are generated in expand rules where required.
2263 // Constant shift counts are handled in Ideal phase.
2264 const bool Matcher::need_masked_shift_count = false;
2265
2266 // This affects two different things:
2267 // - how Decode nodes are matched
2268 // - how ImplicitNullCheck opportunities are recognized
2269 // If true, the matcher will try to remove all Decodes and match them
2270 // (as operands) into nodes. NullChecks are not prepared to deal with
2271 // Decodes by final_graph_reshaping().
2272 // If false, final_graph_reshaping() forces the decode behind the Cmp
2273 // for a NullCheck. The matcher matches the Decode node into a register.
2274 // Implicit_null_check optimization moves the Decode along with the
2275 // memory operation back up before the NullCheck.
2276 bool Matcher::narrow_oop_use_complex_address() {
2277 // TODO: PPC port if (MatchDecodeNodes) return true;
2278 return false;
2279 }
2280
2281 bool Matcher::narrow_klass_use_complex_address() {
2282 NOT_LP64(ShouldNotCallThis());
2283 assert(UseCompressedClassPointers, "only for compressed klass code");
2284 // TODO: PPC port if (MatchDecodeNodes) return true;
2285 return false;
2286 }
2287
2288 // Is it better to copy float constants, or load them directly from memory?
2289 // Intel can load a float constant from a direct address, requiring no
2290 // extra registers. Most RISCs will have to materialize an address into a
2291 // register first, so they would do better to copy the constant from stack.
2292 const bool Matcher::rematerialize_float_constants = false;
2293
2294 // If CPU can load and store mis-aligned doubles directly then no fixup is
2295 // needed. Else we split the double into 2 integer pieces and move it
2296 // piece-by-piece. Only happens when passing doubles into C code as the
2297 // Java calling convention forces doubles to be aligned.
2298 const bool Matcher::misaligned_doubles_ok = true;
2299
2300 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2301 Unimplemented();
2302 }
2303
2304 // Advertise here if the CPU requires explicit rounding operations
2305 // to implement the UseStrictFP mode.
2306 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2307
2308 // Do floats take an entire double register or just half?
2309 //
2310 // A float occupies a ppc64 double register. For the allocator, a
2311 // ppc64 double register appears as a pair of float registers.
2312 bool Matcher::float_in_double() { return true; }
2313
2314 // Do ints take an entire long register or just half?
2315 // The relevant question is how the int is callee-saved:
2316 // the whole long is written but de-opt'ing will have to extract
2317 // the relevant 32 bits.
2318 const bool Matcher::int_in_long = true;
2319
2320 // Constants for c2c and c calling conventions.
2321
2322 const MachRegisterNumbers iarg_reg[8] = {
2323 R3_num, R4_num, R5_num, R6_num,
2324 R7_num, R8_num, R9_num, R10_num
2325 };
2326
2327 const MachRegisterNumbers farg_reg[13] = {
2328 F1_num, F2_num, F3_num, F4_num,
2329 F5_num, F6_num, F7_num, F8_num,
2330 F9_num, F10_num, F11_num, F12_num,
2331 F13_num
2332 };
2333
2334 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2335
2336 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2337
2338 // Return whether or not this register is ever used as an argument. This
2339 // function is used on startup to build the trampoline stubs in generateOptoStub.
2340 // Registers not mentioned will be killed by the VM call in the trampoline, and
2341 // arguments in those registers not be available to the callee.
2342 bool Matcher::can_be_java_arg(int reg) {
2343 // We return true for all registers contained in iarg_reg[] and
2344 // farg_reg[] and their virtual halves.
2345 // We must include the virtual halves in order to get STDs and LDs
2346 // instead of STWs and LWs in the trampoline stubs.
2347
2348 if ( reg == R3_num || reg == R3_H_num
2349 || reg == R4_num || reg == R4_H_num
2350 || reg == R5_num || reg == R5_H_num
2351 || reg == R6_num || reg == R6_H_num
2352 || reg == R7_num || reg == R7_H_num
2353 || reg == R8_num || reg == R8_H_num
2354 || reg == R9_num || reg == R9_H_num
2355 || reg == R10_num || reg == R10_H_num)
2356 return true;
2357
2358 if ( reg == F1_num || reg == F1_H_num
2359 || reg == F2_num || reg == F2_H_num
2360 || reg == F3_num || reg == F3_H_num
2361 || reg == F4_num || reg == F4_H_num
2362 || reg == F5_num || reg == F5_H_num
2363 || reg == F6_num || reg == F6_H_num
2364 || reg == F7_num || reg == F7_H_num
2365 || reg == F8_num || reg == F8_H_num
2366 || reg == F9_num || reg == F9_H_num
2367 || reg == F10_num || reg == F10_H_num
2368 || reg == F11_num || reg == F11_H_num
2369 || reg == F12_num || reg == F12_H_num
2370 || reg == F13_num || reg == F13_H_num)
2371 return true;
2372
2373 return false;
2374 }
2375
2376 bool Matcher::is_spillable_arg(int reg) {
2377 return can_be_java_arg(reg);
2378 }
2379
2380 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2381 return false;
2382 }
2383
2384 // Register for DIVI projection of divmodI.
2385 RegMask Matcher::divI_proj_mask() {
2386 ShouldNotReachHere();
2387 return RegMask();
2388 }
2389
2390 // Register for MODI projection of divmodI.
2391 RegMask Matcher::modI_proj_mask() {
2392 ShouldNotReachHere();
2393 return RegMask();
2394 }
2395
2396 // Register for DIVL projection of divmodL.
2397 RegMask Matcher::divL_proj_mask() {
2398 ShouldNotReachHere();
2399 return RegMask();
2400 }
2401
2402 // Register for MODL projection of divmodL.
2403 RegMask Matcher::modL_proj_mask() {
2404 ShouldNotReachHere();
2405 return RegMask();
2406 }
2407
2408 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2409 return RegMask();
2410 }
2411
2412 %}
2413
2414 //----------ENCODING BLOCK-----------------------------------------------------
2415 // This block specifies the encoding classes used by the compiler to output
2416 // byte streams. Encoding classes are parameterized macros used by
2417 // Machine Instruction Nodes in order to generate the bit encoding of the
2418 // instruction. Operands specify their base encoding interface with the
2419 // interface keyword. There are currently supported four interfaces,
2420 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2421 // operand to generate a function which returns its register number when
2422 // queried. CONST_INTER causes an operand to generate a function which
2423 // returns the value of the constant when queried. MEMORY_INTER causes an
2424 // operand to generate four functions which return the Base Register, the
2425 // Index Register, the Scale Value, and the Offset Value of the operand when
2426 // queried. COND_INTER causes an operand to generate six functions which
2427 // return the encoding code (ie - encoding bits for the instruction)
2428 // associated with each basic boolean condition for a conditional instruction.
2429 //
2430 // Instructions specify two basic values for encoding. Again, a function
2431 // is available to check if the constant displacement is an oop. They use the
2432 // ins_encode keyword to specify their encoding classes (which must be
2433 // a sequence of enc_class names, and their parameters, specified in
2434 // the encoding block), and they use the
2435 // opcode keyword to specify, in order, their primary, secondary, and
2436 // tertiary opcode. Only the opcode sections which a particular instruction
2437 // needs for encoding need to be specified.
2438 encode %{
2439 enc_class enc_unimplemented %{
2440 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2441 MacroAssembler _masm(&cbuf);
2442 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2443 %}
2444
2445 enc_class enc_untested %{
2446 #ifdef ASSERT
2447 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2448 MacroAssembler _masm(&cbuf);
2449 __ untested("Untested mach node encoding in AD file.");
2450 #else
2451 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2452 #endif
2453 %}
2454
2455 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2456 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2457 MacroAssembler _masm(&cbuf);
2458 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2459 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2460 %}
2461
2462 // Load acquire.
2463 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2464 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2465 MacroAssembler _masm(&cbuf);
2466 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2467 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2468 __ twi_0($dst$$Register);
2469 __ isync();
2470 %}
2471
2472 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2473 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2474
2475 MacroAssembler _masm(&cbuf);
2476 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2477 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2478 %}
2479
2480 // Load acquire.
2481 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2482 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2483
2484 MacroAssembler _masm(&cbuf);
2485 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2486 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2487 __ twi_0($dst$$Register);
2488 __ isync();
2489 %}
2490
2491 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2492 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2493
2494 MacroAssembler _masm(&cbuf);
2495 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2496 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2497 %}
2498
2499 // Load acquire.
2500 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2501 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2502
2503 MacroAssembler _masm(&cbuf);
2504 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2505 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2506 __ twi_0($dst$$Register);
2507 __ isync();
2508 %}
2509
2510 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2511 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2512 MacroAssembler _masm(&cbuf);
2513 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2514 // Operand 'ds' requires 4-alignment.
2515 assert((Idisp & 0x3) == 0, "unaligned offset");
2516 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2517 %}
2518
2519 // Load acquire.
2520 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2521 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2522 MacroAssembler _masm(&cbuf);
2523 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2524 // Operand 'ds' requires 4-alignment.
2525 assert((Idisp & 0x3) == 0, "unaligned offset");
2526 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2527 __ twi_0($dst$$Register);
2528 __ isync();
2529 %}
2530
2531 enc_class enc_lfd(RegF dst, memory mem) %{
2532 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2533 MacroAssembler _masm(&cbuf);
2534 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2535 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2536 %}
2537
2538 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2539 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2540
2541 MacroAssembler _masm(&cbuf);
2542 int toc_offset = 0;
2543
2544 if (!ra_->C->in_scratch_emit_size()) {
2545 address const_toc_addr;
2546 // Create a non-oop constant, no relocation needed.
2547 // If it is an IC, it has a virtual_call_Relocation.
2548 const_toc_addr = __ long_constant((jlong)$src$$constant);
2549
2550 // Get the constant's TOC offset.
2551 toc_offset = __ offset_to_method_toc(const_toc_addr);
2552
2553 // Keep the current instruction offset in mind.
2554 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2555 }
2556
2557 __ ld($dst$$Register, toc_offset, $toc$$Register);
2558 %}
2559
2560 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2561 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2562
2563 MacroAssembler _masm(&cbuf);
2564
2565 if (!ra_->C->in_scratch_emit_size()) {
2566 address const_toc_addr;
2567 // Create a non-oop constant, no relocation needed.
2568 // If it is an IC, it has a virtual_call_Relocation.
2569 const_toc_addr = __ long_constant((jlong)$src$$constant);
2570
2571 // Get the constant's TOC offset.
2572 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2573 // Store the toc offset of the constant.
2574 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2575
2576 // Also keep the current instruction offset in mind.
2577 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2578 }
2579
2580 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2581 %}
2582
2583 %} // encode
2584
2585 source %{
2586
2587 typedef struct {
2588 loadConL_hiNode *_large_hi;
2589 loadConL_loNode *_large_lo;
2590 loadConLNode *_small;
2591 MachNode *_last;
2592 } loadConLNodesTuple;
2593
2594 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2595 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2596 loadConLNodesTuple nodes;
2597
2598 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2599 if (large_constant_pool) {
2600 // Create new nodes.
2601 loadConL_hiNode *m1 = new loadConL_hiNode();
2602 loadConL_loNode *m2 = new loadConL_loNode();
2603
2604 // inputs for new nodes
2605 m1->add_req(NULL, toc);
2606 m2->add_req(NULL, m1);
2607
2608 // operands for new nodes
2609 m1->_opnds[0] = new iRegLdstOper(); // dst
2610 m1->_opnds[1] = immSrc; // src
2611 m1->_opnds[2] = new iRegPdstOper(); // toc
2612 m2->_opnds[0] = new iRegLdstOper(); // dst
2613 m2->_opnds[1] = immSrc; // src
2614 m2->_opnds[2] = new iRegLdstOper(); // base
2615
2616 // Initialize ins_attrib TOC fields.
2617 m1->_const_toc_offset = -1;
2618 m2->_const_toc_offset_hi_node = m1;
2619
2620 // Initialize ins_attrib instruction offset.
2621 m1->_cbuf_insts_offset = -1;
2622
2623 // register allocation for new nodes
2624 ra_->set_pair(m1->_idx, reg_second, reg_first);
2625 ra_->set_pair(m2->_idx, reg_second, reg_first);
2626
2627 // Create result.
2628 nodes._large_hi = m1;
2629 nodes._large_lo = m2;
2630 nodes._small = NULL;
2631 nodes._last = nodes._large_lo;
2632 assert(m2->bottom_type()->isa_long(), "must be long");
2633 } else {
2634 loadConLNode *m2 = new loadConLNode();
2635
2636 // inputs for new nodes
2637 m2->add_req(NULL, toc);
2638
2639 // operands for new nodes
2640 m2->_opnds[0] = new iRegLdstOper(); // dst
2641 m2->_opnds[1] = immSrc; // src
2642 m2->_opnds[2] = new iRegPdstOper(); // toc
2643
2644 // Initialize ins_attrib instruction offset.
2645 m2->_cbuf_insts_offset = -1;
2646
2647 // register allocation for new nodes
2648 ra_->set_pair(m2->_idx, reg_second, reg_first);
2649
2650 // Create result.
2651 nodes._large_hi = NULL;
2652 nodes._large_lo = NULL;
2653 nodes._small = m2;
2654 nodes._last = nodes._small;
2655 assert(m2->bottom_type()->isa_long(), "must be long");
2656 }
2657
2658 return nodes;
2659 }
2660
2661 %} // source
2662
2663 encode %{
2664 // Postalloc expand emitter for loading a long constant from the method's TOC.
2665 // Enc_class needed as consttanttablebase is not supported by postalloc
2666 // expand.
2667 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2668 // Create new nodes.
2669 loadConLNodesTuple loadConLNodes =
2670 loadConLNodesTuple_create(ra_, n_toc, op_src,
2671 ra_->get_reg_second(this), ra_->get_reg_first(this));
2672
2673 // Push new nodes.
2674 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2675 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2676
2677 // some asserts
2678 assert(nodes->length() >= 1, "must have created at least 1 node");
2679 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2680 %}
2681
2682 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2683 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2684
2685 MacroAssembler _masm(&cbuf);
2686 int toc_offset = 0;
2687
2688 if (!ra_->C->in_scratch_emit_size()) {
2689 intptr_t val = $src$$constant;
2690 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2691 address const_toc_addr;
2692 if (constant_reloc == relocInfo::oop_type) {
2693 // Create an oop constant and a corresponding relocation.
2694 AddressLiteral a = __ allocate_oop_address((jobject)val);
2695 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2696 __ relocate(a.rspec());
2697 } else if (constant_reloc == relocInfo::metadata_type) {
2698 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2699 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2700 __ relocate(a.rspec());
2701 } else {
2702 // Create a non-oop constant, no relocation needed.
2703 const_toc_addr = __ long_constant((jlong)$src$$constant);
2704 }
2705
2706 // Get the constant's TOC offset.
2707 toc_offset = __ offset_to_method_toc(const_toc_addr);
2708 }
2709
2710 __ ld($dst$$Register, toc_offset, $toc$$Register);
2711 %}
2712
2713 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2714 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2715
2716 MacroAssembler _masm(&cbuf);
2717 if (!ra_->C->in_scratch_emit_size()) {
2718 intptr_t val = $src$$constant;
2719 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2720 address const_toc_addr;
2721 if (constant_reloc == relocInfo::oop_type) {
2722 // Create an oop constant and a corresponding relocation.
2723 AddressLiteral a = __ allocate_oop_address((jobject)val);
2724 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2725 __ relocate(a.rspec());
2726 } else if (constant_reloc == relocInfo::metadata_type) {
2727 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2728 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2729 __ relocate(a.rspec());
2730 } else { // non-oop pointers, e.g. card mark base, heap top
2731 // Create a non-oop constant, no relocation needed.
2732 const_toc_addr = __ long_constant((jlong)$src$$constant);
2733 }
2734
2735 // Get the constant's TOC offset.
2736 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2737 // Store the toc offset of the constant.
2738 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2739 }
2740
2741 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2742 %}
2743
2744 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2745 // Enc_class needed as consttanttablebase is not supported by postalloc
2746 // expand.
2747 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2748 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2749 if (large_constant_pool) {
2750 // Create new nodes.
2751 loadConP_hiNode *m1 = new loadConP_hiNode();
2752 loadConP_loNode *m2 = new loadConP_loNode();
2753
2754 // inputs for new nodes
2755 m1->add_req(NULL, n_toc);
2756 m2->add_req(NULL, m1);
2757
2758 // operands for new nodes
2759 m1->_opnds[0] = new iRegPdstOper(); // dst
2760 m1->_opnds[1] = op_src; // src
2761 m1->_opnds[2] = new iRegPdstOper(); // toc
2762 m2->_opnds[0] = new iRegPdstOper(); // dst
2763 m2->_opnds[1] = op_src; // src
2764 m2->_opnds[2] = new iRegLdstOper(); // base
2765
2766 // Initialize ins_attrib TOC fields.
2767 m1->_const_toc_offset = -1;
2768 m2->_const_toc_offset_hi_node = m1;
2769
2770 // Register allocation for new nodes.
2771 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2772 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2773
2774 nodes->push(m1);
2775 nodes->push(m2);
2776 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2777 } else {
2778 loadConPNode *m2 = new loadConPNode();
2779
2780 // inputs for new nodes
2781 m2->add_req(NULL, n_toc);
2782
2783 // operands for new nodes
2784 m2->_opnds[0] = new iRegPdstOper(); // dst
2785 m2->_opnds[1] = op_src; // src
2786 m2->_opnds[2] = new iRegPdstOper(); // toc
2787
2788 // Register allocation for new nodes.
2789 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2790
2791 nodes->push(m2);
2792 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2793 }
2794 %}
2795
2796 // Enc_class needed as consttanttablebase is not supported by postalloc
2797 // expand.
2798 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2799 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2800
2801 MachNode *m2;
2802 if (large_constant_pool) {
2803 m2 = new loadConFCompNode();
2804 } else {
2805 m2 = new loadConFNode();
2806 }
2807 // inputs for new nodes
2808 m2->add_req(NULL, n_toc);
2809
2810 // operands for new nodes
2811 m2->_opnds[0] = op_dst;
2812 m2->_opnds[1] = op_src;
2813 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2814
2815 // register allocation for new nodes
2816 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2817 nodes->push(m2);
2818 %}
2819
2820 // Enc_class needed as consttanttablebase is not supported by postalloc
2821 // expand.
2822 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2823 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2824
2825 MachNode *m2;
2826 if (large_constant_pool) {
2827 m2 = new loadConDCompNode();
2828 } else {
2829 m2 = new loadConDNode();
2830 }
2831 // inputs for new nodes
2832 m2->add_req(NULL, n_toc);
2833
2834 // operands for new nodes
2835 m2->_opnds[0] = op_dst;
2836 m2->_opnds[1] = op_src;
2837 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2838
2839 // register allocation for new nodes
2840 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2841 nodes->push(m2);
2842 %}
2843
2844 enc_class enc_stw(iRegIsrc src, memory mem) %{
2845 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2846 MacroAssembler _masm(&cbuf);
2847 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2848 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2849 %}
2850
2851 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2852 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2853 MacroAssembler _masm(&cbuf);
2854 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2855 // Operand 'ds' requires 4-alignment.
2856 assert((Idisp & 0x3) == 0, "unaligned offset");
2857 __ std($src$$Register, Idisp, $mem$$base$$Register);
2858 %}
2859
2860 enc_class enc_stfs(RegF src, memory mem) %{
2861 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2862 MacroAssembler _masm(&cbuf);
2863 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2864 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2865 %}
2866
2867 enc_class enc_stfd(RegF src, memory mem) %{
2868 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2869 MacroAssembler _masm(&cbuf);
2870 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2871 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2872 %}
2873
2874 // Use release_store for card-marking to ensure that previous
2875 // oop-stores are visible before the card-mark change.
2876 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{
2877 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2878 // FIXME: Implement this as a cmove and use a fixed condition code
2879 // register which is written on every transition to compiled code,
2880 // e.g. in call-stub and when returning from runtime stubs.
2881 //
2882 // Proposed code sequence for the cmove implementation:
2883 //
2884 // Label skip_release;
2885 // __ beq(CCRfixed, skip_release);
2886 // __ release();
2887 // __ bind(skip_release);
2888 // __ stb(card mark);
2889
2890 MacroAssembler _masm(&cbuf);
2891 Label skip_storestore;
2892
2893 #if 0 // TODO: PPC port
2894 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2895 // StoreStore barrier conditionally.
2896 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2897 __ cmpwi(CCR0, R0, 0);
2898 __ beq_predict_taken(CCR0, skip_storestore);
2899 #endif
2900 __ li(R0, 0);
2901 __ membar(Assembler::StoreStore);
2902 #if 0 // TODO: PPC port
2903 __ bind(skip_storestore);
2904 #endif
2905
2906 // Do the store.
2907 if ($mem$$index == 0) {
2908 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2909 } else {
2910 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2911 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2912 }
2913 %}
2914
2915 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2916
2917 if (VM_Version::has_isel()) {
2918 // use isel instruction with Power 7
2919 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2920 encodeP_subNode *n_sub_base = new encodeP_subNode();
2921 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2922 cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2923
2924 n_compare->add_req(n_region, n_src);
2925 n_compare->_opnds[0] = op_crx;
2926 n_compare->_opnds[1] = op_src;
2927 n_compare->_opnds[2] = new immL16Oper(0);
2928
2929 n_sub_base->add_req(n_region, n_src);
2930 n_sub_base->_opnds[0] = op_dst;
2931 n_sub_base->_opnds[1] = op_src;
2932 n_sub_base->_bottom_type = _bottom_type;
2933
2934 n_shift->add_req(n_region, n_sub_base);
2935 n_shift->_opnds[0] = op_dst;
2936 n_shift->_opnds[1] = op_dst;
2937 n_shift->_bottom_type = _bottom_type;
2938
2939 n_cond_set->add_req(n_region, n_compare, n_shift);
2940 n_cond_set->_opnds[0] = op_dst;
2941 n_cond_set->_opnds[1] = op_crx;
2942 n_cond_set->_opnds[2] = op_dst;
2943 n_cond_set->_bottom_type = _bottom_type;
2944
2945 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2946 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2947 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2948 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2949
2950 nodes->push(n_compare);
2951 nodes->push(n_sub_base);
2952 nodes->push(n_shift);
2953 nodes->push(n_cond_set);
2954
2955 } else {
2956 // before Power 7
2957 moveRegNode *n_move = new moveRegNode();
2958 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2959 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2960 cond_sub_baseNode *n_sub_base = new cond_sub_baseNode();
2961
2962 n_move->add_req(n_region, n_src);
2963 n_move->_opnds[0] = op_dst;
2964 n_move->_opnds[1] = op_src;
2965 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2966
2967 n_compare->add_req(n_region, n_src);
2968 n_compare->add_prec(n_move);
2969
2970 n_compare->_opnds[0] = op_crx;
2971 n_compare->_opnds[1] = op_src;
2972 n_compare->_opnds[2] = new immL16Oper(0);
2973
2974 n_sub_base->add_req(n_region, n_compare, n_src);
2975 n_sub_base->_opnds[0] = op_dst;
2976 n_sub_base->_opnds[1] = op_crx;
2977 n_sub_base->_opnds[2] = op_src;
2978 n_sub_base->_bottom_type = _bottom_type;
2979
2980 n_shift->add_req(n_region, n_sub_base);
2981 n_shift->_opnds[0] = op_dst;
2982 n_shift->_opnds[1] = op_dst;
2983 n_shift->_bottom_type = _bottom_type;
2984
2985 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2986 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2987 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2988 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2989
2990 nodes->push(n_move);
2991 nodes->push(n_compare);
2992 nodes->push(n_sub_base);
2993 nodes->push(n_shift);
2994 }
2995
2996 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2997 %}
2998
2999 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
3000
3001 encodeP_subNode *n1 = new encodeP_subNode();
3002 n1->add_req(n_region, n_src);
3003 n1->_opnds[0] = op_dst;
3004 n1->_opnds[1] = op_src;
3005 n1->_bottom_type = _bottom_type;
3006
3007 encodeP_shiftNode *n2 = new encodeP_shiftNode();
3008 n2->add_req(n_region, n1);
3009 n2->_opnds[0] = op_dst;
3010 n2->_opnds[1] = op_dst;
3011 n2->_bottom_type = _bottom_type;
3012 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3013 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3014
3015 nodes->push(n1);
3016 nodes->push(n2);
3017 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
3018 %}
3019
3020 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
3021 decodeN_shiftNode *n_shift = new decodeN_shiftNode();
3022 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
3023
3024 n_compare->add_req(n_region, n_src);
3025 n_compare->_opnds[0] = op_crx;
3026 n_compare->_opnds[1] = op_src;
3027 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
3028
3029 n_shift->add_req(n_region, n_src);
3030 n_shift->_opnds[0] = op_dst;
3031 n_shift->_opnds[1] = op_src;
3032 n_shift->_bottom_type = _bottom_type;
3033
3034 if (VM_Version::has_isel()) {
3035 // use isel instruction with Power 7
3036
3037 decodeN_addNode *n_add_base = new decodeN_addNode();
3038 n_add_base->add_req(n_region, n_shift);
3039 n_add_base->_opnds[0] = op_dst;
3040 n_add_base->_opnds[1] = op_dst;
3041 n_add_base->_bottom_type = _bottom_type;
3042
3043 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
3044 n_cond_set->add_req(n_region, n_compare, n_add_base);
3045 n_cond_set->_opnds[0] = op_dst;
3046 n_cond_set->_opnds[1] = op_crx;
3047 n_cond_set->_opnds[2] = op_dst;
3048 n_cond_set->_bottom_type = _bottom_type;
3049
3050 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3051 ra_->set_oop(n_cond_set, true);
3052
3053 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3054 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3055 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3056 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3057
3058 nodes->push(n_compare);
3059 nodes->push(n_shift);
3060 nodes->push(n_add_base);
3061 nodes->push(n_cond_set);
3062
3063 } else {
3064 // before Power 7
3065 cond_add_baseNode *n_add_base = new cond_add_baseNode();
3066
3067 n_add_base->add_req(n_region, n_compare, n_shift);
3068 n_add_base->_opnds[0] = op_dst;
3069 n_add_base->_opnds[1] = op_crx;
3070 n_add_base->_opnds[2] = op_dst;
3071 n_add_base->_bottom_type = _bottom_type;
3072
3073 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3074 ra_->set_oop(n_add_base, true);
3075
3076 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3077 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3078 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3079
3080 nodes->push(n_compare);
3081 nodes->push(n_shift);
3082 nodes->push(n_add_base);
3083 }
3084 %}
3085
3086 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3087 decodeN_shiftNode *n1 = new decodeN_shiftNode();
3088 n1->add_req(n_region, n_src);
3089 n1->_opnds[0] = op_dst;
3090 n1->_opnds[1] = op_src;
3091 n1->_bottom_type = _bottom_type;
3092
3093 decodeN_addNode *n2 = new decodeN_addNode();
3094 n2->add_req(n_region, n1);
3095 n2->_opnds[0] = op_dst;
3096 n2->_opnds[1] = op_dst;
3097 n2->_bottom_type = _bottom_type;
3098 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3099 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3100
3101 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3102 ra_->set_oop(n2, true);
3103
3104 nodes->push(n1);
3105 nodes->push(n2);
3106 %}
3107
3108 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{
3109 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3110
3111 MacroAssembler _masm(&cbuf);
3112 int cc = $cmp$$cmpcode;
3113 int flags_reg = $crx$$reg;
3114 Label done;
3115 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3116 // Branch if not (cmp crx).
3117 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3118 __ mr($dst$$Register, $src$$Register);
3119 // TODO PPC port __ endgroup_if_needed(_size == 12);
3120 __ bind(done);
3121 %}
3122
3123 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{
3124 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3125
3126 MacroAssembler _masm(&cbuf);
3127 Label done;
3128 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3129 // Branch if not (cmp crx).
3130 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3131 __ li($dst$$Register, $src$$constant);
3132 // TODO PPC port __ endgroup_if_needed(_size == 12);
3133 __ bind(done);
3134 %}
3135
3136 // New atomics.
3137 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3138 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3139
3140 MacroAssembler _masm(&cbuf);
3141 Register Rtmp = R0;
3142 Register Rres = $res$$Register;
3143 Register Rsrc = $src$$Register;
3144 Register Rptr = $mem_ptr$$Register;
3145 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3146 Register Rold = RegCollision ? Rtmp : Rres;
3147
3148 Label Lretry;
3149 __ bind(Lretry);
3150 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3151 __ add(Rtmp, Rsrc, Rold);
3152 __ stwcx_(Rtmp, Rptr);
3153 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3154 __ bne_predict_not_taken(CCR0, Lretry);
3155 } else {
3156 __ bne( CCR0, Lretry);
3157 }
3158 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3159 __ fence();
3160 %}
3161
3162 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3163 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3164
3165 MacroAssembler _masm(&cbuf);
3166 Register Rtmp = R0;
3167 Register Rres = $res$$Register;
3168 Register Rsrc = $src$$Register;
3169 Register Rptr = $mem_ptr$$Register;
3170 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3171 Register Rold = RegCollision ? Rtmp : Rres;
3172
3173 Label Lretry;
3174 __ bind(Lretry);
3175 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3176 __ add(Rtmp, Rsrc, Rold);
3177 __ stdcx_(Rtmp, Rptr);
3178 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3179 __ bne_predict_not_taken(CCR0, Lretry);
3180 } else {
3181 __ bne( CCR0, Lretry);
3182 }
3183 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3184 __ fence();
3185 %}
3186
3187 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3188 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3189
3190 MacroAssembler _masm(&cbuf);
3191 Register Rtmp = R0;
3192 Register Rres = $res$$Register;
3193 Register Rsrc = $src$$Register;
3194 Register Rptr = $mem_ptr$$Register;
3195 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3196 Register Rold = RegCollision ? Rtmp : Rres;
3197
3198 Label Lretry;
3199 __ bind(Lretry);
3200 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3201 __ stwcx_(Rsrc, Rptr);
3202 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3203 __ bne_predict_not_taken(CCR0, Lretry);
3204 } else {
3205 __ bne( CCR0, Lretry);
3206 }
3207 if (RegCollision) __ mr(Rres, Rtmp);
3208 __ fence();
3209 %}
3210
3211 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3212 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3213
3214 MacroAssembler _masm(&cbuf);
3215 Register Rtmp = R0;
3216 Register Rres = $res$$Register;
3217 Register Rsrc = $src$$Register;
3218 Register Rptr = $mem_ptr$$Register;
3219 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3220 Register Rold = RegCollision ? Rtmp : Rres;
3221
3222 Label Lretry;
3223 __ bind(Lretry);
3224 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3225 __ stdcx_(Rsrc, Rptr);
3226 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3227 __ bne_predict_not_taken(CCR0, Lretry);
3228 } else {
3229 __ bne( CCR0, Lretry);
3230 }
3231 if (RegCollision) __ mr(Rres, Rtmp);
3232 __ fence();
3233 %}
3234
3235 // This enc_class is needed so that scheduler gets proper
3236 // input mapping for latency computation.
3237 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3238 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3239 MacroAssembler _masm(&cbuf);
3240 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3241 %}
3242
3243 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3244 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3245
3246 MacroAssembler _masm(&cbuf);
3247
3248 Label done;
3249 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3250 __ li($dst$$Register, $zero$$constant);
3251 __ beq($crx$$CondRegister, done);
3252 __ li($dst$$Register, $notzero$$constant);
3253 __ bind(done);
3254 %}
3255
3256 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3257 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3258
3259 MacroAssembler _masm(&cbuf);
3260
3261 Label done;
3262 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3263 __ li($dst$$Register, $zero$$constant);
3264 __ beq($crx$$CondRegister, done);
3265 __ li($dst$$Register, $notzero$$constant);
3266 __ bind(done);
3267 %}
3268
3269 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{
3270 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3271
3272 MacroAssembler _masm(&cbuf);
3273 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3274 Label done;
3275 __ bso($crx$$CondRegister, done);
3276 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3277 // TODO PPC port __ endgroup_if_needed(_size == 12);
3278 __ bind(done);
3279 %}
3280
3281 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{
3282 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3283
3284 MacroAssembler _masm(&cbuf);
3285 Label d; // dummy
3286 __ bind(d);
3287 Label* p = ($lbl$$label);
3288 // `p' is `NULL' when this encoding class is used only to
3289 // determine the size of the encoded instruction.
3290 Label& l = (NULL == p)? d : *(p);
3291 int cc = $cmp$$cmpcode;
3292 int flags_reg = $crx$$reg;
3293 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3294 int bhint = Assembler::bhintNoHint;
3295
3296 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3297 if (_prob <= PROB_NEVER) {
3298 bhint = Assembler::bhintIsNotTaken;
3299 } else if (_prob >= PROB_ALWAYS) {
3300 bhint = Assembler::bhintIsTaken;
3301 }
3302 }
3303
3304 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3305 cc_to_biint(cc, flags_reg),
3306 l);
3307 %}
3308
3309 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3310 // The scheduler doesn't know about branch shortening, so we set the opcode
3311 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3312 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3313
3314 MacroAssembler _masm(&cbuf);
3315 Label d; // dummy
3316 __ bind(d);
3317 Label* p = ($lbl$$label);
3318 // `p' is `NULL' when this encoding class is used only to
3319 // determine the size of the encoded instruction.
3320 Label& l = (NULL == p)? d : *(p);
3321 int cc = $cmp$$cmpcode;
3322 int flags_reg = $crx$$reg;
3323 int bhint = Assembler::bhintNoHint;
3324
3325 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3326 if (_prob <= PROB_NEVER) {
3327 bhint = Assembler::bhintIsNotTaken;
3328 } else if (_prob >= PROB_ALWAYS) {
3329 bhint = Assembler::bhintIsTaken;
3330 }
3331 }
3332
3333 // Tell the conditional far branch to optimize itself when being relocated.
3334 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3335 cc_to_biint(cc, flags_reg),
3336 l,
3337 MacroAssembler::bc_far_optimize_on_relocate);
3338 %}
3339
3340 // Branch used with Power6 scheduling (can be shortened without changing the node).
3341 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3342 // The scheduler doesn't know about branch shortening, so we set the opcode
3343 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3344 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3345
3346 MacroAssembler _masm(&cbuf);
3347 Label d; // dummy
3348 __ bind(d);
3349 Label* p = ($lbl$$label);
3350 // `p' is `NULL' when this encoding class is used only to
3351 // determine the size of the encoded instruction.
3352 Label& l = (NULL == p)? d : *(p);
3353 int cc = $cmp$$cmpcode;
3354 int flags_reg = $crx$$reg;
3355 int bhint = Assembler::bhintNoHint;
3356
3357 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3358 if (_prob <= PROB_NEVER) {
3359 bhint = Assembler::bhintIsNotTaken;
3360 } else if (_prob >= PROB_ALWAYS) {
3361 bhint = Assembler::bhintIsTaken;
3362 }
3363 }
3364
3365 #if 0 // TODO: PPC port
3366 if (_size == 8) {
3367 // Tell the conditional far branch to optimize itself when being relocated.
3368 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3369 cc_to_biint(cc, flags_reg),
3370 l,
3371 MacroAssembler::bc_far_optimize_on_relocate);
3372 } else {
3373 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3374 cc_to_biint(cc, flags_reg),
3375 l);
3376 }
3377 #endif
3378 Unimplemented();
3379 %}
3380
3381 // Postalloc expand emitter for loading a replicatef float constant from
3382 // the method's TOC.
3383 // Enc_class needed as consttanttablebase is not supported by postalloc
3384 // expand.
3385 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3386 // Create new nodes.
3387
3388 // Make an operand with the bit pattern to load as float.
3389 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3390
3391 loadConLNodesTuple loadConLNodes =
3392 loadConLNodesTuple_create(ra_, n_toc, op_repl,
3393 ra_->get_reg_second(this), ra_->get_reg_first(this));
3394
3395 // Push new nodes.
3396 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3397 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3398
3399 assert(nodes->length() >= 1, "must have created at least 1 node");
3400 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3401 %}
3402
3403 // This enc_class is needed so that scheduler gets proper
3404 // input mapping for latency computation.
3405 enc_class enc_poll(immI dst, iRegLdst poll) %{
3406 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3407 // Fake operand dst needed for PPC scheduler.
3408 assert($dst$$constant == 0x0, "dst must be 0x0");
3409
3410 MacroAssembler _masm(&cbuf);
3411 // Mark the code position where the load from the safepoint
3412 // polling page was emitted as relocInfo::poll_type.
3413 __ relocate(relocInfo::poll_type);
3414 __ load_from_polling_page($poll$$Register);
3415 %}
3416
3417 // A Java static call or a runtime call.
3418 //
3419 // Branch-and-link relative to a trampoline.
3420 // The trampoline loads the target address and does a long branch to there.
3421 // In case we call java, the trampoline branches to a interpreter_stub
3422 // which loads the inline cache and the real call target from the constant pool.
3423 //
3424 // This basically looks like this:
3425 //
3426 // >>>> consts -+ -+
3427 // | |- offset1
3428 // [call target1] | <-+
3429 // [IC cache] |- offset2
3430 // [call target2] <--+
3431 //
3432 // <<<< consts
3433 // >>>> insts
3434 //
3435 // bl offset16 -+ -+ ??? // How many bits available?
3436 // | |
3437 // <<<< insts | |
3438 // >>>> stubs | |
3439 // | |- trampoline_stub_Reloc
3440 // trampoline stub: | <-+
3441 // r2 = toc |
3442 // r2 = [r2 + offset1] | // Load call target1 from const section
3443 // mtctr r2 |
3444 // bctr |- static_stub_Reloc
3445 // comp_to_interp_stub: <---+
3446 // r1 = toc
3447 // ICreg = [r1 + IC_offset] // Load IC from const section
3448 // r1 = [r1 + offset2] // Load call target2 from const section
3449 // mtctr r1
3450 // bctr
3451 //
3452 // <<<< stubs
3453 //
3454 // The call instruction in the code either
3455 // - Branches directly to a compiled method if the offset is encodable in instruction.
3456 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3457 // - Branches to the compiled_to_interp stub if the target is interpreted.
3458 //
3459 // Further there are three relocations from the loads to the constants in
3460 // the constant section.
3461 //
3462 // Usage of r1 and r2 in the stubs allows to distinguish them.
3463 enc_class enc_java_static_call(method meth) %{
3464 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3465
3466 MacroAssembler _masm(&cbuf);
3467 address entry_point = (address)$meth$$method;
3468
3469 if (!_method) {
3470 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3471 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3472 } else {
3473 // Remember the offset not the address.
3474 const int start_offset = __ offset();
3475 // The trampoline stub.
3476 if (!Compile::current()->in_scratch_emit_size()) {
3477 // No entry point given, use the current pc.
3478 // Make sure branch fits into
3479 if (entry_point == 0) entry_point = __ pc();
3480
3481 // Put the entry point as a constant into the constant pool.
3482 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3483 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3484
3485 // Emit the trampoline stub which will be related to the branch-and-link below.
3486 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3487 __ relocate(_optimized_virtual ?
3488 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3489 }
3490
3491 // The real call.
3492 // Note: At this point we do not have the address of the trampoline
3493 // stub, and the entry point might be too far away for bl, so __ pc()
3494 // serves as dummy and the bl will be patched later.
3495 cbuf.set_insts_mark();
3496 __ bl(__ pc()); // Emits a relocation.
3497
3498 // The stub for call to interpreter.
3499 CompiledStaticCall::emit_to_interp_stub(cbuf);
3500 }
3501 %}
3502
3503 // Emit a method handle call.
3504 //
3505 // Method handle calls from compiled to compiled are going thru a
3506 // c2i -> i2c adapter, extending the frame for their arguments. The
3507 // caller however, returns directly to the compiled callee, that has
3508 // to cope with the extended frame. We restore the original frame by
3509 // loading the callers sp and adding the calculated framesize.
3510 enc_class enc_java_handle_call(method meth) %{
3511 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3512
3513 MacroAssembler _masm(&cbuf);
3514 address entry_point = (address)$meth$$method;
3515
3516 // Remember the offset not the address.
3517 const int start_offset = __ offset();
3518 // The trampoline stub.
3519 if (!ra_->C->in_scratch_emit_size()) {
3520 // No entry point given, use the current pc.
3521 // Make sure branch fits into
3522 if (entry_point == 0) entry_point = __ pc();
3523
3524 // Put the entry point as a constant into the constant pool.
3525 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3526 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3527
3528 // Emit the trampoline stub which will be related to the branch-and-link below.
3529 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3530 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3531 __ relocate(relocInfo::opt_virtual_call_type);
3532 }
3533
3534 // The real call.
3535 // Note: At this point we do not have the address of the trampoline
3536 // stub, and the entry point might be too far away for bl, so __ pc()
3537 // serves as dummy and the bl will be patched later.
3538 cbuf.set_insts_mark();
3539 __ bl(__ pc()); // Emits a relocation.
3540
3541 assert(_method, "execute next statement conditionally");
3542 // The stub for call to interpreter.
3543 CompiledStaticCall::emit_to_interp_stub(cbuf);
3544
3545 // Restore original sp.
3546 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3547 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3548 unsigned int bytes = (unsigned int)framesize;
3549 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3550 if (Assembler::is_simm(-offset, 16)) {
3551 __ addi(R1_SP, R11_scratch1, -offset);
3552 } else {
3553 __ load_const_optimized(R12_scratch2, -offset);
3554 __ add(R1_SP, R11_scratch1, R12_scratch2);
3555 }
3556 #ifdef ASSERT
3557 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3558 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3559 __ asm_assert_eq("backlink changed", 0x8000);
3560 #endif
3561 // If fails should store backlink before unextending.
3562
3563 if (ra_->C->env()->failing()) {
3564 return;
3565 }
3566 %}
3567
3568 // Second node of expanded dynamic call - the call.
3569 enc_class enc_java_dynamic_call_sched(method meth) %{
3570 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3571
3572 MacroAssembler _masm(&cbuf);
3573
3574 if (!ra_->C->in_scratch_emit_size()) {
3575 // Create a call trampoline stub for the given method.
3576 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3577 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3578 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3579 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3580
3581 if (ra_->C->env()->failing())
3582 return;
3583
3584 // Build relocation at call site with ic position as data.
3585 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3586 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3587 "must have one, but can't have both");
3588 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3589 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3590 "must contain instruction offset");
3591 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3592 ? _load_ic_hi_node->_cbuf_insts_offset
3593 : _load_ic_node->_cbuf_insts_offset;
3594 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3595 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3596 "should be load from TOC");
3597
3598 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3599 }
3600
3601 // At this point I do not have the address of the trampoline stub,
3602 // and the entry point might be too far away for bl. Pc() serves
3603 // as dummy and bl will be patched later.
3604 __ bl((address) __ pc());
3605 %}
3606
3607 // postalloc expand emitter for virtual calls.
3608 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3609
3610 // Create the nodes for loading the IC from the TOC.
3611 loadConLNodesTuple loadConLNodes_IC =
3612 loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3613 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3614
3615 // Create the call node.
3616 CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3617 call->_method_handle_invoke = _method_handle_invoke;
3618 call->_vtable_index = _vtable_index;
3619 call->_method = _method;
3620 call->_bci = _bci;
3621 call->_optimized_virtual = _optimized_virtual;
3622 call->_tf = _tf;
3623 call->_entry_point = _entry_point;
3624 call->_cnt = _cnt;
3625 call->_argsize = _argsize;
3626 call->_oop_map = _oop_map;
3627 call->_jvms = _jvms;
3628 call->_jvmadj = _jvmadj;
3629 call->_in_rms = _in_rms;
3630 call->_nesting = _nesting;
3631
3632 // New call needs all inputs of old call.
3633 // Req...
3634 for (uint i = 0; i < req(); ++i) {
3635 // The expanded node does not need toc any more.
3636 // Add the inline cache constant here instead. This expresses the
3637 // register of the inline cache must be live at the call.
3638 // Else we would have to adapt JVMState by -1.
3639 if (i == mach_constant_base_node_input()) {
3640 call->add_req(loadConLNodes_IC._last);
3641 } else {
3642 call->add_req(in(i));
3643 }
3644 }
3645 // ...as well as prec
3646 for (uint i = req(); i < len(); ++i) {
3647 call->add_prec(in(i));
3648 }
3649
3650 // Remember nodes loading the inline cache into r19.
3651 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3652 call->_load_ic_node = loadConLNodes_IC._small;
3653
3654 // Operands for new nodes.
3655 call->_opnds[0] = _opnds[0];
3656 call->_opnds[1] = _opnds[1];
3657
3658 // Only the inline cache is associated with a register.
3659 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3660
3661 // Push new nodes.
3662 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3663 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3664 nodes->push(call);
3665 %}
3666
3667 // Compound version of call dynamic
3668 // Toc is only passed so that it can be used in ins_encode statement.
3669 // In the code we have to use $constanttablebase.
3670 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3671 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3672 MacroAssembler _masm(&cbuf);
3673 int start_offset = __ offset();
3674
3675 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3676 #if 0
3677 int vtable_index = this->_vtable_index;
3678 if (_vtable_index < 0) {
3679 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3680 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3681 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3682
3683 // Virtual call relocation will point to ic load.
3684 address virtual_call_meta_addr = __ pc();
3685 // Load a clear inline cache.
3686 AddressLiteral empty_ic((address) Universe::non_oop_word());
3687 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
3688 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3689 // to determine who we intended to call.
3690 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3691 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3692 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3693 "Fix constant in ret_addr_offset()");
3694 } else {
3695 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3696 // Go thru the vtable. Get receiver klass. Receiver already
3697 // checked for non-null. If we'll go thru a C2I adapter, the
3698 // interpreter expects method in R19_method.
3699
3700 __ load_klass(R11_scratch1, R3);
3701
3702 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3703 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3704 __ li(R19_method, v_off);
3705 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3706 // NOTE: for vtable dispatches, the vtable entry will never be
3707 // null. However it may very well end up in handle_wrong_method
3708 // if the method is abstract for the particular class.
3709 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3710 // Call target. Either compiled code or C2I adapter.
3711 __ mtctr(R11_scratch1);
3712 __ bctrl();
3713 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3714 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3715 }
3716 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3717 "Fix constant in ret_addr_offset()");
3718 }
3719 #endif
3720 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3721 %}
3722
3723 // a runtime call
3724 enc_class enc_java_to_runtime_call (method meth) %{
3725 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3726
3727 MacroAssembler _masm(&cbuf);
3728 const address start_pc = __ pc();
3729
3730 #if defined(ABI_ELFv2)
3731 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3732 __ call_c(entry, relocInfo::runtime_call_type);
3733 #else
3734 // The function we're going to call.
3735 FunctionDescriptor fdtemp;
3736 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3737
3738 Register Rtoc = R12_scratch2;
3739 // Calculate the method's TOC.
3740 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3741 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3742 // pool entries; call_c_using_toc will optimize the call.
3743 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3744 #endif
3745
3746 // Check the ret_addr_offset.
3747 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3748 "Fix constant in ret_addr_offset()");
3749 %}
3750
3751 // Move to ctr for leaf call.
3752 // This enc_class is needed so that scheduler gets proper
3753 // input mapping for latency computation.
3754 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3755 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3756 MacroAssembler _masm(&cbuf);
3757 __ mtctr($src$$Register);
3758 %}
3759
3760 // Postalloc expand emitter for runtime leaf calls.
3761 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3762 loadConLNodesTuple loadConLNodes_Entry;
3763 #if defined(ABI_ELFv2)
3764 jlong entry_address = (jlong) this->entry_point();
3765 assert(entry_address, "need address here");
3766 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3767 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3768 #else
3769 // Get the struct that describes the function we are about to call.
3770 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3771 assert(fd, "need fd here");
3772 jlong entry_address = (jlong) fd->entry();
3773 // new nodes
3774 loadConLNodesTuple loadConLNodes_Env;
3775 loadConLNodesTuple loadConLNodes_Toc;
3776
3777 // Create nodes and operands for loading the entry point.
3778 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3779 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3780
3781
3782 // Create nodes and operands for loading the env pointer.
3783 if (fd->env() != NULL) {
3784 loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3785 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3786 } else {
3787 loadConLNodes_Env._large_hi = NULL;
3788 loadConLNodes_Env._large_lo = NULL;
3789 loadConLNodes_Env._small = NULL;
3790 loadConLNodes_Env._last = new loadConL16Node();
3791 loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3792 loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3793 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3794 }
3795
3796 // Create nodes and operands for loading the Toc point.
3797 loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3798 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3799 #endif // ABI_ELFv2
3800 // mtctr node
3801 MachNode *mtctr = new CallLeafDirect_mtctrNode();
3802
3803 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3804 mtctr->add_req(0, loadConLNodes_Entry._last);
3805
3806 mtctr->_opnds[0] = new iRegLdstOper();
3807 mtctr->_opnds[1] = new iRegLdstOper();
3808
3809 // call node
3810 MachCallLeafNode *call = new CallLeafDirectNode();
3811
3812 call->_opnds[0] = _opnds[0];
3813 call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3814
3815 // Make the new call node look like the old one.
3816 call->_name = _name;
3817 call->_tf = _tf;
3818 call->_entry_point = _entry_point;
3819 call->_cnt = _cnt;
3820 call->_argsize = _argsize;
3821 call->_oop_map = _oop_map;
3822 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3823 call->_jvms = NULL;
3824 call->_jvmadj = _jvmadj;
3825 call->_in_rms = _in_rms;
3826 call->_nesting = _nesting;
3827
3828
3829 // New call needs all inputs of old call.
3830 // Req...
3831 for (uint i = 0; i < req(); ++i) {
3832 if (i != mach_constant_base_node_input()) {
3833 call->add_req(in(i));
3834 }
3835 }
3836
3837 // These must be reqired edges, as the registers are live up to
3838 // the call. Else the constants are handled as kills.
3839 call->add_req(mtctr);
3840 #if !defined(ABI_ELFv2)
3841 call->add_req(loadConLNodes_Env._last);
3842 call->add_req(loadConLNodes_Toc._last);
3843 #endif
3844
3845 // ...as well as prec
3846 for (uint i = req(); i < len(); ++i) {
3847 call->add_prec(in(i));
3848 }
3849
3850 // registers
3851 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3852
3853 // Insert the new nodes.
3854 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3855 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3856 #if !defined(ABI_ELFv2)
3857 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3858 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3859 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3860 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3861 #endif
3862 nodes->push(mtctr);
3863 nodes->push(call);
3864 %}
3865 %}
3866
3867 //----------FRAME--------------------------------------------------------------
3868 // Definition of frame structure and management information.
3869
3870 frame %{
3871 // What direction does stack grow in (assumed to be same for native & Java).
3872 stack_direction(TOWARDS_LOW);
3873
3874 // These two registers define part of the calling convention between
3875 // compiled code and the interpreter.
3876
3877 // Inline Cache Register or method for I2C.
3878 inline_cache_reg(R19); // R19_method
3879
3880 // Method Oop Register when calling interpreter.
3881 interpreter_method_oop_reg(R19); // R19_method
3882
3883 // Optional: name the operand used by cisc-spilling to access
3884 // [stack_pointer + offset].
3885 cisc_spilling_operand_name(indOffset);
3886
3887 // Number of stack slots consumed by a Monitor enter.
3888 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3889
3890 // Compiled code's Frame Pointer.
3891 frame_pointer(R1); // R1_SP
3892
3893 // Interpreter stores its frame pointer in a register which is
3894 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3895 // interpreted java to compiled java.
3896 //
3897 // R14_state holds pointer to caller's cInterpreter.
3898 interpreter_frame_pointer(R14); // R14_state
3899
3900 stack_alignment(frame::alignment_in_bytes);
3901
3902 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3903
3904 // Number of outgoing stack slots killed above the
3905 // out_preserve_stack_slots for calls to C. Supports the var-args
3906 // backing area for register parms.
3907 //
3908 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3909
3910 // The after-PROLOG location of the return address. Location of
3911 // return address specifies a type (REG or STACK) and a number
3912 // representing the register number (i.e. - use a register name) or
3913 // stack slot.
3914 //
3915 // A: Link register is stored in stack slot ...
3916 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3917 // J: Therefore, we make sure that the link register is also in R11_scratch1
3918 // at the end of the prolog.
3919 // B: We use R20, now.
3920 //return_addr(REG R20);
3921
3922 // G: After reading the comments made by all the luminaries on their
3923 // failure to tell the compiler where the return address really is,
3924 // I hardly dare to try myself. However, I'm convinced it's in slot
3925 // 4 what apparently works and saves us some spills.
3926 return_addr(STACK 4);
3927
3928 // This is the body of the function
3929 //
3930 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3931 // uint length, // length of array
3932 // bool is_outgoing)
3933 //
3934 // The `sig' array is to be updated. sig[j] represents the location
3935 // of the j-th argument, either a register or a stack slot.
3936
3937 // Comment taken from i486.ad:
3938 // Body of function which returns an integer array locating
3939 // arguments either in registers or in stack slots. Passed an array
3940 // of ideal registers called "sig" and a "length" count. Stack-slot
3941 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3942 // arguments for a CALLEE. Incoming stack arguments are
3943 // automatically biased by the preserve_stack_slots field above.
3944 calling_convention %{
3945 // No difference between ingoing/outgoing. Just pass false.
3946 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3947 %}
3948
3949 // Comment taken from i486.ad:
3950 // Body of function which returns an integer array locating
3951 // arguments either in registers or in stack slots. Passed an array
3952 // of ideal registers called "sig" and a "length" count. Stack-slot
3953 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3954 // arguments for a CALLEE. Incoming stack arguments are
3955 // automatically biased by the preserve_stack_slots field above.
3956 c_calling_convention %{
3957 // This is obviously always outgoing.
3958 // C argument in register AND stack slot.
3959 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3960 %}
3961
3962 // Location of native (C/C++) and interpreter return values. This
3963 // is specified to be the same as Java. In the 32-bit VM, long
3964 // values are actually returned from native calls in O0:O1 and
3965 // returned to the interpreter in I0:I1. The copying to and from
3966 // the register pairs is done by the appropriate call and epilog
3967 // opcodes. This simplifies the register allocator.
3968 c_return_value %{
3969 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3970 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3971 "only return normal values");
3972 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3973 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3974 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3975 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3976 %}
3977
3978 // Location of compiled Java return values. Same as C
3979 return_value %{
3980 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3981 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3982 "only return normal values");
3983 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3984 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3985 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3986 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3987 %}
3988 %}
3989
3990
3991 //----------ATTRIBUTES---------------------------------------------------------
3992
3993 //----------Operand Attributes-------------------------------------------------
3994 op_attrib op_cost(1); // Required cost attribute.
3995
3996 //----------Instruction Attributes---------------------------------------------
3997
3998 // Cost attribute. required.
3999 ins_attrib ins_cost(DEFAULT_COST);
4000
4001 // Is this instruction a non-matching short branch variant of some
4002 // long branch? Not required.
4003 ins_attrib ins_short_branch(0);
4004
4005 ins_attrib ins_is_TrapBasedCheckNode(true);
4006
4007 // Number of constants.
4008 // This instruction uses the given number of constants
4009 // (optional attribute).
4010 // This is needed to determine in time whether the constant pool will
4011 // exceed 4000 entries. Before postalloc_expand the overall number of constants
4012 // is determined. It's also used to compute the constant pool size
4013 // in Output().
4014 ins_attrib ins_num_consts(0);
4015
4016 // Required alignment attribute (must be a power of 2) specifies the
4017 // alignment that some part of the instruction (not necessarily the
4018 // start) requires. If > 1, a compute_padding() function must be
4019 // provided for the instruction.
4020 ins_attrib ins_alignment(1);
4021
4022 // Enforce/prohibit rematerializations.
4023 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
4024 // then rematerialization of that instruction is prohibited and the
4025 // instruction's value will be spilled if necessary.
4026 // Causes that MachNode::rematerialize() returns false.
4027 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
4028 // then rematerialization should be enforced and a copy of the instruction
4029 // should be inserted if possible; rematerialization is not guaranteed.
4030 // Note: this may result in rematerializations in front of every use.
4031 // Causes that MachNode::rematerialize() can return true.
4032 // (optional attribute)
4033 ins_attrib ins_cannot_rematerialize(false);
4034 ins_attrib ins_should_rematerialize(false);
4035
4036 // Instruction has variable size depending on alignment.
4037 ins_attrib ins_variable_size_depending_on_alignment(false);
4038
4039 // Instruction is a nop.
4040 ins_attrib ins_is_nop(false);
4041
4042 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
4043 ins_attrib ins_use_mach_if_fast_lock_node(false);
4044
4045 // Field for the toc offset of a constant.
4046 //
4047 // This is needed if the toc offset is not encodable as an immediate in
4048 // the PPC load instruction. If so, the upper (hi) bits of the offset are
4049 // added to the toc, and from this a load with immediate is performed.
4050 // With postalloc expand, we get two nodes that require the same offset
4051 // but which don't know about each other. The offset is only known
4052 // when the constant is added to the constant pool during emitting.
4053 // It is generated in the 'hi'-node adding the upper bits, and saved
4054 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
4055 // the offset from there when it gets encoded.
4056 ins_attrib ins_field_const_toc_offset(0);
4057 ins_attrib ins_field_const_toc_offset_hi_node(0);
4058
4059 // A field that can hold the instructions offset in the code buffer.
4060 // Set in the nodes emitter.
4061 ins_attrib ins_field_cbuf_insts_offset(-1);
4062
4063 // Fields for referencing a call's load-IC-node.
4064 // If the toc offset can not be encoded as an immediate in a load, we
4065 // use two nodes.
4066 ins_attrib ins_field_load_ic_hi_node(0);
4067 ins_attrib ins_field_load_ic_node(0);
4068
4069 //----------OPERANDS-----------------------------------------------------------
4070 // Operand definitions must precede instruction definitions for correct
4071 // parsing in the ADLC because operands constitute user defined types
4072 // which are used in instruction definitions.
4073 //
4074 // Formats are generated automatically for constants and base registers.
4075
4076 //----------Simple Operands----------------------------------------------------
4077 // Immediate Operands
4078
4079 // Integer Immediate: 32-bit
4080 operand immI() %{
4081 match(ConI);
4082 op_cost(40);
4083 format %{ %}
4084 interface(CONST_INTER);
4085 %}
4086
4087 operand immI8() %{
4088 predicate(Assembler::is_simm(n->get_int(), 8));
4089 op_cost(0);
4090 match(ConI);
4091 format %{ %}
4092 interface(CONST_INTER);
4093 %}
4094
4095 // Integer Immediate: 16-bit
4096 operand immI16() %{
4097 predicate(Assembler::is_simm(n->get_int(), 16));
4098 op_cost(0);
4099 match(ConI);
4100 format %{ %}
4101 interface(CONST_INTER);
4102 %}
4103
4104 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4105 operand immIhi16() %{
4106 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4107 match(ConI);
4108 op_cost(0);
4109 format %{ %}
4110 interface(CONST_INTER);
4111 %}
4112
4113 operand immInegpow2() %{
4114 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4115 match(ConI);
4116 op_cost(0);
4117 format %{ %}
4118 interface(CONST_INTER);
4119 %}
4120
4121 operand immIpow2minus1() %{
4122 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4123 match(ConI);
4124 op_cost(0);
4125 format %{ %}
4126 interface(CONST_INTER);
4127 %}
4128
4129 operand immIpowerOf2() %{
4130 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4131 match(ConI);
4132 op_cost(0);
4133 format %{ %}
4134 interface(CONST_INTER);
4135 %}
4136
4137 // Unsigned Integer Immediate: the values 0-31
4138 operand uimmI5() %{
4139 predicate(Assembler::is_uimm(n->get_int(), 5));
4140 match(ConI);
4141 op_cost(0);
4142 format %{ %}
4143 interface(CONST_INTER);
4144 %}
4145
4146 // Unsigned Integer Immediate: 6-bit
4147 operand uimmI6() %{
4148 predicate(Assembler::is_uimm(n->get_int(), 6));
4149 match(ConI);
4150 op_cost(0);
4151 format %{ %}
4152 interface(CONST_INTER);
4153 %}
4154
4155 // Unsigned Integer Immediate: 6-bit int, greater than 32
4156 operand uimmI6_ge32() %{
4157 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4158 match(ConI);
4159 op_cost(0);
4160 format %{ %}
4161 interface(CONST_INTER);
4162 %}
4163
4164 // Unsigned Integer Immediate: 15-bit
4165 operand uimmI15() %{
4166 predicate(Assembler::is_uimm(n->get_int(), 15));
4167 match(ConI);
4168 op_cost(0);
4169 format %{ %}
4170 interface(CONST_INTER);
4171 %}
4172
4173 // Unsigned Integer Immediate: 16-bit
4174 operand uimmI16() %{
4175 predicate(Assembler::is_uimm(n->get_int(), 16));
4176 match(ConI);
4177 op_cost(0);
4178 format %{ %}
4179 interface(CONST_INTER);
4180 %}
4181
4182 // constant 'int 0'.
4183 operand immI_0() %{
4184 predicate(n->get_int() == 0);
4185 match(ConI);
4186 op_cost(0);
4187 format %{ %}
4188 interface(CONST_INTER);
4189 %}
4190
4191 // constant 'int 1'.
4192 operand immI_1() %{
4193 predicate(n->get_int() == 1);
4194 match(ConI);
4195 op_cost(0);
4196 format %{ %}
4197 interface(CONST_INTER);
4198 %}
4199
4200 // constant 'int -1'.
4201 operand immI_minus1() %{
4202 predicate(n->get_int() == -1);
4203 match(ConI);
4204 op_cost(0);
4205 format %{ %}
4206 interface(CONST_INTER);
4207 %}
4208
4209 // int value 16.
4210 operand immI_16() %{
4211 predicate(n->get_int() == 16);
4212 match(ConI);
4213 op_cost(0);
4214 format %{ %}
4215 interface(CONST_INTER);
4216 %}
4217
4218 // int value 24.
4219 operand immI_24() %{
4220 predicate(n->get_int() == 24);
4221 match(ConI);
4222 op_cost(0);
4223 format %{ %}
4224 interface(CONST_INTER);
4225 %}
4226
4227 // Compressed oops constants
4228 // Pointer Immediate
4229 operand immN() %{
4230 match(ConN);
4231
4232 op_cost(10);
4233 format %{ %}
4234 interface(CONST_INTER);
4235 %}
4236
4237 // NULL Pointer Immediate
4238 operand immN_0() %{
4239 predicate(n->get_narrowcon() == 0);
4240 match(ConN);
4241
4242 op_cost(0);
4243 format %{ %}
4244 interface(CONST_INTER);
4245 %}
4246
4247 // Compressed klass constants
4248 operand immNKlass() %{
4249 match(ConNKlass);
4250
4251 op_cost(0);
4252 format %{ %}
4253 interface(CONST_INTER);
4254 %}
4255
4256 // This operand can be used to avoid matching of an instruct
4257 // with chain rule.
4258 operand immNKlass_NM() %{
4259 match(ConNKlass);
4260 predicate(false);
4261 op_cost(0);
4262 format %{ %}
4263 interface(CONST_INTER);
4264 %}
4265
4266 // Pointer Immediate: 64-bit
4267 operand immP() %{
4268 match(ConP);
4269 op_cost(0);
4270 format %{ %}
4271 interface(CONST_INTER);
4272 %}
4273
4274 // Operand to avoid match of loadConP.
4275 // This operand can be used to avoid matching of an instruct
4276 // with chain rule.
4277 operand immP_NM() %{
4278 match(ConP);
4279 predicate(false);
4280 op_cost(0);
4281 format %{ %}
4282 interface(CONST_INTER);
4283 %}
4284
4285 // costant 'pointer 0'.
4286 operand immP_0() %{
4287 predicate(n->get_ptr() == 0);
4288 match(ConP);
4289 op_cost(0);
4290 format %{ %}
4291 interface(CONST_INTER);
4292 %}
4293
4294 // pointer 0x0 or 0x1
4295 operand immP_0or1() %{
4296 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4297 match(ConP);
4298 op_cost(0);
4299 format %{ %}
4300 interface(CONST_INTER);
4301 %}
4302
4303 operand immL() %{
4304 match(ConL);
4305 op_cost(40);
4306 format %{ %}
4307 interface(CONST_INTER);
4308 %}
4309
4310 // Long Immediate: 16-bit
4311 operand immL16() %{
4312 predicate(Assembler::is_simm(n->get_long(), 16));
4313 match(ConL);
4314 op_cost(0);
4315 format %{ %}
4316 interface(CONST_INTER);
4317 %}
4318
4319 // Long Immediate: 16-bit, 4-aligned
4320 operand immL16Alg4() %{
4321 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4322 match(ConL);
4323 op_cost(0);
4324 format %{ %}
4325 interface(CONST_INTER);
4326 %}
4327
4328 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4329 operand immL32hi16() %{
4330 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4331 match(ConL);
4332 op_cost(0);
4333 format %{ %}
4334 interface(CONST_INTER);
4335 %}
4336
4337 // Long Immediate: 32-bit
4338 operand immL32() %{
4339 predicate(Assembler::is_simm(n->get_long(), 32));
4340 match(ConL);
4341 op_cost(0);
4342 format %{ %}
4343 interface(CONST_INTER);
4344 %}
4345
4346 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4347 operand immLhighest16() %{
4348 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4349 match(ConL);
4350 op_cost(0);
4351 format %{ %}
4352 interface(CONST_INTER);
4353 %}
4354
4355 operand immLnegpow2() %{
4356 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4357 match(ConL);
4358 op_cost(0);
4359 format %{ %}
4360 interface(CONST_INTER);
4361 %}
4362
4363 operand immLpow2minus1() %{
4364 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4365 (n->get_long() != (jlong)0xffffffffffffffffL));
4366 match(ConL);
4367 op_cost(0);
4368 format %{ %}
4369 interface(CONST_INTER);
4370 %}
4371
4372 // constant 'long 0'.
4373 operand immL_0() %{
4374 predicate(n->get_long() == 0L);
4375 match(ConL);
4376 op_cost(0);
4377 format %{ %}
4378 interface(CONST_INTER);
4379 %}
4380
4381 // constat ' long -1'.
4382 operand immL_minus1() %{
4383 predicate(n->get_long() == -1L);
4384 match(ConL);
4385 op_cost(0);
4386 format %{ %}
4387 interface(CONST_INTER);
4388 %}
4389
4390 // Long Immediate: low 32-bit mask
4391 operand immL_32bits() %{
4392 predicate(n->get_long() == 0xFFFFFFFFL);
4393 match(ConL);
4394 op_cost(0);
4395 format %{ %}
4396 interface(CONST_INTER);
4397 %}
4398
4399 // Unsigned Long Immediate: 16-bit
4400 operand uimmL16() %{
4401 predicate(Assembler::is_uimm(n->get_long(), 16));
4402 match(ConL);
4403 op_cost(0);
4404 format %{ %}
4405 interface(CONST_INTER);
4406 %}
4407
4408 // Float Immediate
4409 operand immF() %{
4410 match(ConF);
4411 op_cost(40);
4412 format %{ %}
4413 interface(CONST_INTER);
4414 %}
4415
4416 // constant 'float +0.0'.
4417 operand immF_0() %{
4418 predicate((n->getf() == 0) &&
4419 (fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0));
4420 match(ConF);
4421 op_cost(0);
4422 format %{ %}
4423 interface(CONST_INTER);
4424 %}
4425
4426 // Double Immediate
4427 operand immD() %{
4428 match(ConD);
4429 op_cost(40);
4430 format %{ %}
4431 interface(CONST_INTER);
4432 %}
4433
4434 // Integer Register Operands
4435 // Integer Destination Register
4436 // See definition of reg_class bits32_reg_rw.
4437 operand iRegIdst() %{
4438 constraint(ALLOC_IN_RC(bits32_reg_rw));
4439 match(RegI);
4440 match(rscratch1RegI);
4441 match(rscratch2RegI);
4442 match(rarg1RegI);
4443 match(rarg2RegI);
4444 match(rarg3RegI);
4445 match(rarg4RegI);
4446 format %{ %}
4447 interface(REG_INTER);
4448 %}
4449
4450 // Integer Source Register
4451 // See definition of reg_class bits32_reg_ro.
4452 operand iRegIsrc() %{
4453 constraint(ALLOC_IN_RC(bits32_reg_ro));
4454 match(RegI);
4455 match(rscratch1RegI);
4456 match(rscratch2RegI);
4457 match(rarg1RegI);
4458 match(rarg2RegI);
4459 match(rarg3RegI);
4460 match(rarg4RegI);
4461 format %{ %}
4462 interface(REG_INTER);
4463 %}
4464
4465 operand rscratch1RegI() %{
4466 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4467 match(iRegIdst);
4468 format %{ %}
4469 interface(REG_INTER);
4470 %}
4471
4472 operand rscratch2RegI() %{
4473 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4474 match(iRegIdst);
4475 format %{ %}
4476 interface(REG_INTER);
4477 %}
4478
4479 operand rarg1RegI() %{
4480 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4481 match(iRegIdst);
4482 format %{ %}
4483 interface(REG_INTER);
4484 %}
4485
4486 operand rarg2RegI() %{
4487 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4488 match(iRegIdst);
4489 format %{ %}
4490 interface(REG_INTER);
4491 %}
4492
4493 operand rarg3RegI() %{
4494 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4495 match(iRegIdst);
4496 format %{ %}
4497 interface(REG_INTER);
4498 %}
4499
4500 operand rarg4RegI() %{
4501 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4502 match(iRegIdst);
4503 format %{ %}
4504 interface(REG_INTER);
4505 %}
4506
4507 operand rarg1RegL() %{
4508 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4509 match(iRegLdst);
4510 format %{ %}
4511 interface(REG_INTER);
4512 %}
4513
4514 operand rarg2RegL() %{
4515 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4516 match(iRegLdst);
4517 format %{ %}
4518 interface(REG_INTER);
4519 %}
4520
4521 operand rarg3RegL() %{
4522 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4523 match(iRegLdst);
4524 format %{ %}
4525 interface(REG_INTER);
4526 %}
4527
4528 operand rarg4RegL() %{
4529 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4530 match(iRegLdst);
4531 format %{ %}
4532 interface(REG_INTER);
4533 %}
4534
4535 // Pointer Destination Register
4536 // See definition of reg_class bits64_reg_rw.
4537 operand iRegPdst() %{
4538 constraint(ALLOC_IN_RC(bits64_reg_rw));
4539 match(RegP);
4540 match(rscratch1RegP);
4541 match(rscratch2RegP);
4542 match(rarg1RegP);
4543 match(rarg2RegP);
4544 match(rarg3RegP);
4545 match(rarg4RegP);
4546 format %{ %}
4547 interface(REG_INTER);
4548 %}
4549
4550 // Pointer Destination Register
4551 // Operand not using r11 and r12 (killed in epilog).
4552 operand iRegPdstNoScratch() %{
4553 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4554 match(RegP);
4555 match(rarg1RegP);
4556 match(rarg2RegP);
4557 match(rarg3RegP);
4558 match(rarg4RegP);
4559 format %{ %}
4560 interface(REG_INTER);
4561 %}
4562
4563 // Pointer Source Register
4564 // See definition of reg_class bits64_reg_ro.
4565 operand iRegPsrc() %{
4566 constraint(ALLOC_IN_RC(bits64_reg_ro));
4567 match(RegP);
4568 match(iRegPdst);
4569 match(rscratch1RegP);
4570 match(rscratch2RegP);
4571 match(rarg1RegP);
4572 match(rarg2RegP);
4573 match(rarg3RegP);
4574 match(rarg4RegP);
4575 match(threadRegP);
4576 format %{ %}
4577 interface(REG_INTER);
4578 %}
4579
4580 // Thread operand.
4581 operand threadRegP() %{
4582 constraint(ALLOC_IN_RC(thread_bits64_reg));
4583 match(iRegPdst);
4584 format %{ "R16" %}
4585 interface(REG_INTER);
4586 %}
4587
4588 operand rscratch1RegP() %{
4589 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4590 match(iRegPdst);
4591 format %{ "R11" %}
4592 interface(REG_INTER);
4593 %}
4594
4595 operand rscratch2RegP() %{
4596 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4597 match(iRegPdst);
4598 format %{ %}
4599 interface(REG_INTER);
4600 %}
4601
4602 operand rarg1RegP() %{
4603 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4604 match(iRegPdst);
4605 format %{ %}
4606 interface(REG_INTER);
4607 %}
4608
4609 operand rarg2RegP() %{
4610 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4611 match(iRegPdst);
4612 format %{ %}
4613 interface(REG_INTER);
4614 %}
4615
4616 operand rarg3RegP() %{
4617 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4618 match(iRegPdst);
4619 format %{ %}
4620 interface(REG_INTER);
4621 %}
4622
4623 operand rarg4RegP() %{
4624 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4625 match(iRegPdst);
4626 format %{ %}
4627 interface(REG_INTER);
4628 %}
4629
4630 operand iRegNsrc() %{
4631 constraint(ALLOC_IN_RC(bits32_reg_ro));
4632 match(RegN);
4633 match(iRegNdst);
4634
4635 format %{ %}
4636 interface(REG_INTER);
4637 %}
4638
4639 operand iRegNdst() %{
4640 constraint(ALLOC_IN_RC(bits32_reg_rw));
4641 match(RegN);
4642
4643 format %{ %}
4644 interface(REG_INTER);
4645 %}
4646
4647 // Long Destination Register
4648 // See definition of reg_class bits64_reg_rw.
4649 operand iRegLdst() %{
4650 constraint(ALLOC_IN_RC(bits64_reg_rw));
4651 match(RegL);
4652 match(rscratch1RegL);
4653 match(rscratch2RegL);
4654 format %{ %}
4655 interface(REG_INTER);
4656 %}
4657
4658 // Long Source Register
4659 // See definition of reg_class bits64_reg_ro.
4660 operand iRegLsrc() %{
4661 constraint(ALLOC_IN_RC(bits64_reg_ro));
4662 match(RegL);
4663 match(iRegLdst);
4664 match(rscratch1RegL);
4665 match(rscratch2RegL);
4666 format %{ %}
4667 interface(REG_INTER);
4668 %}
4669
4670 // Special operand for ConvL2I.
4671 operand iRegL2Isrc(iRegLsrc reg) %{
4672 constraint(ALLOC_IN_RC(bits64_reg_ro));
4673 match(ConvL2I reg);
4674 format %{ "ConvL2I($reg)" %}
4675 interface(REG_INTER)
4676 %}
4677
4678 operand rscratch1RegL() %{
4679 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4680 match(RegL);
4681 format %{ %}
4682 interface(REG_INTER);
4683 %}
4684
4685 operand rscratch2RegL() %{
4686 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4687 match(RegL);
4688 format %{ %}
4689 interface(REG_INTER);
4690 %}
4691
4692 // Condition Code Flag Registers
4693 operand flagsReg() %{
4694 constraint(ALLOC_IN_RC(int_flags));
4695 match(RegFlags);
4696 format %{ %}
4697 interface(REG_INTER);
4698 %}
4699
4700 // Condition Code Flag Register CR0
4701 operand flagsRegCR0() %{
4702 constraint(ALLOC_IN_RC(int_flags_CR0));
4703 match(RegFlags);
4704 format %{ "CR0" %}
4705 interface(REG_INTER);
4706 %}
4707
4708 operand flagsRegCR1() %{
4709 constraint(ALLOC_IN_RC(int_flags_CR1));
4710 match(RegFlags);
4711 format %{ "CR1" %}
4712 interface(REG_INTER);
4713 %}
4714
4715 operand flagsRegCR6() %{
4716 constraint(ALLOC_IN_RC(int_flags_CR6));
4717 match(RegFlags);
4718 format %{ "CR6" %}
4719 interface(REG_INTER);
4720 %}
4721
4722 operand regCTR() %{
4723 constraint(ALLOC_IN_RC(ctr_reg));
4724 // RegFlags should work. Introducing a RegSpecial type would cause a
4725 // lot of changes.
4726 match(RegFlags);
4727 format %{"SR_CTR" %}
4728 interface(REG_INTER);
4729 %}
4730
4731 operand regD() %{
4732 constraint(ALLOC_IN_RC(dbl_reg));
4733 match(RegD);
4734 format %{ %}
4735 interface(REG_INTER);
4736 %}
4737
4738 operand regF() %{
4739 constraint(ALLOC_IN_RC(flt_reg));
4740 match(RegF);
4741 format %{ %}
4742 interface(REG_INTER);
4743 %}
4744
4745 // Special Registers
4746
4747 // Method Register
4748 operand inline_cache_regP(iRegPdst reg) %{
4749 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4750 match(reg);
4751 format %{ %}
4752 interface(REG_INTER);
4753 %}
4754
4755 operand compiler_method_oop_regP(iRegPdst reg) %{
4756 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4757 match(reg);
4758 format %{ %}
4759 interface(REG_INTER);
4760 %}
4761
4762 operand interpreter_method_oop_regP(iRegPdst reg) %{
4763 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4764 match(reg);
4765 format %{ %}
4766 interface(REG_INTER);
4767 %}
4768
4769 // Operands to remove register moves in unscaled mode.
4770 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4771 operand iRegP2N(iRegPsrc reg) %{
4772 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4773 constraint(ALLOC_IN_RC(bits64_reg_ro));
4774 match(EncodeP reg);
4775 format %{ "$reg" %}
4776 interface(REG_INTER)
4777 %}
4778
4779 operand iRegN2P(iRegNsrc reg) %{
4780 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4781 constraint(ALLOC_IN_RC(bits32_reg_ro));
4782 match(DecodeN reg);
4783 match(DecodeNKlass reg);
4784 format %{ "$reg" %}
4785 interface(REG_INTER)
4786 %}
4787
4788 //----------Complex Operands---------------------------------------------------
4789 // Indirect Memory Reference
4790 operand indirect(iRegPsrc reg) %{
4791 constraint(ALLOC_IN_RC(bits64_reg_ro));
4792 match(reg);
4793 op_cost(100);
4794 format %{ "[$reg]" %}
4795 interface(MEMORY_INTER) %{
4796 base($reg);
4797 index(0x0);
4798 scale(0x0);
4799 disp(0x0);
4800 %}
4801 %}
4802
4803 // Indirect with Offset
4804 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4805 constraint(ALLOC_IN_RC(bits64_reg_ro));
4806 match(AddP reg offset);
4807 op_cost(100);
4808 format %{ "[$reg + $offset]" %}
4809 interface(MEMORY_INTER) %{
4810 base($reg);
4811 index(0x0);
4812 scale(0x0);
4813 disp($offset);
4814 %}
4815 %}
4816
4817 // Indirect with 4-aligned Offset
4818 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4819 constraint(ALLOC_IN_RC(bits64_reg_ro));
4820 match(AddP reg offset);
4821 op_cost(100);
4822 format %{ "[$reg + $offset]" %}
4823 interface(MEMORY_INTER) %{
4824 base($reg);
4825 index(0x0);
4826 scale(0x0);
4827 disp($offset);
4828 %}
4829 %}
4830
4831 //----------Complex Operands for Compressed OOPs-------------------------------
4832 // Compressed OOPs with narrow_oop_shift == 0.
4833
4834 // Indirect Memory Reference, compressed OOP
4835 operand indirectNarrow(iRegNsrc reg) %{
4836 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4837 constraint(ALLOC_IN_RC(bits64_reg_ro));
4838 match(DecodeN reg);
4839 match(DecodeNKlass reg);
4840 op_cost(100);
4841 format %{ "[$reg]" %}
4842 interface(MEMORY_INTER) %{
4843 base($reg);
4844 index(0x0);
4845 scale(0x0);
4846 disp(0x0);
4847 %}
4848 %}
4849
4850 // Indirect with Offset, compressed OOP
4851 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4852 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4853 constraint(ALLOC_IN_RC(bits64_reg_ro));
4854 match(AddP (DecodeN reg) offset);
4855 match(AddP (DecodeNKlass reg) offset);
4856 op_cost(100);
4857 format %{ "[$reg + $offset]" %}
4858 interface(MEMORY_INTER) %{
4859 base($reg);
4860 index(0x0);
4861 scale(0x0);
4862 disp($offset);
4863 %}
4864 %}
4865
4866 // Indirect with 4-aligned Offset, compressed OOP
4867 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4868 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4869 constraint(ALLOC_IN_RC(bits64_reg_ro));
4870 match(AddP (DecodeN reg) offset);
4871 match(AddP (DecodeNKlass reg) offset);
4872 op_cost(100);
4873 format %{ "[$reg + $offset]" %}
4874 interface(MEMORY_INTER) %{
4875 base($reg);
4876 index(0x0);
4877 scale(0x0);
4878 disp($offset);
4879 %}
4880 %}
4881
4882 //----------Special Memory Operands--------------------------------------------
4883 // Stack Slot Operand
4884 //
4885 // This operand is used for loading and storing temporary values on
4886 // the stack where a match requires a value to flow through memory.
4887 operand stackSlotI(sRegI reg) %{
4888 constraint(ALLOC_IN_RC(stack_slots));
4889 op_cost(100);
4890 //match(RegI);
4891 format %{ "[sp+$reg]" %}
4892 interface(MEMORY_INTER) %{
4893 base(0x1); // R1_SP
4894 index(0x0);
4895 scale(0x0);
4896 disp($reg); // Stack Offset
4897 %}
4898 %}
4899
4900 operand stackSlotL(sRegL reg) %{
4901 constraint(ALLOC_IN_RC(stack_slots));
4902 op_cost(100);
4903 //match(RegL);
4904 format %{ "[sp+$reg]" %}
4905 interface(MEMORY_INTER) %{
4906 base(0x1); // R1_SP
4907 index(0x0);
4908 scale(0x0);
4909 disp($reg); // Stack Offset
4910 %}
4911 %}
4912
4913 operand stackSlotP(sRegP reg) %{
4914 constraint(ALLOC_IN_RC(stack_slots));
4915 op_cost(100);
4916 //match(RegP);
4917 format %{ "[sp+$reg]" %}
4918 interface(MEMORY_INTER) %{
4919 base(0x1); // R1_SP
4920 index(0x0);
4921 scale(0x0);
4922 disp($reg); // Stack Offset
4923 %}
4924 %}
4925
4926 operand stackSlotF(sRegF reg) %{
4927 constraint(ALLOC_IN_RC(stack_slots));
4928 op_cost(100);
4929 //match(RegF);
4930 format %{ "[sp+$reg]" %}
4931 interface(MEMORY_INTER) %{
4932 base(0x1); // R1_SP
4933 index(0x0);
4934 scale(0x0);
4935 disp($reg); // Stack Offset
4936 %}
4937 %}
4938
4939 operand stackSlotD(sRegD reg) %{
4940 constraint(ALLOC_IN_RC(stack_slots));
4941 op_cost(100);
4942 //match(RegD);
4943 format %{ "[sp+$reg]" %}
4944 interface(MEMORY_INTER) %{
4945 base(0x1); // R1_SP
4946 index(0x0);
4947 scale(0x0);
4948 disp($reg); // Stack Offset
4949 %}
4950 %}
4951
4952 // Operands for expressing Control Flow
4953 // NOTE: Label is a predefined operand which should not be redefined in
4954 // the AD file. It is generically handled within the ADLC.
4955
4956 //----------Conditional Branch Operands----------------------------------------
4957 // Comparison Op
4958 //
4959 // This is the operation of the comparison, and is limited to the
4960 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4961 // (!=).
4962 //
4963 // Other attributes of the comparison, such as unsignedness, are specified
4964 // by the comparison instruction that sets a condition code flags register.
4965 // That result is represented by a flags operand whose subtype is appropriate
4966 // to the unsignedness (etc.) of the comparison.
4967 //
4968 // Later, the instruction which matches both the Comparison Op (a Bool) and
4969 // the flags (produced by the Cmp) specifies the coding of the comparison op
4970 // by matching a specific subtype of Bool operand below.
4971
4972 // When used for floating point comparisons: unordered same as less.
4973 operand cmpOp() %{
4974 match(Bool);
4975 format %{ "" %}
4976 interface(COND_INTER) %{
4977 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4978 // BO & BI
4979 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4980 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4981 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4982 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4983 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4984 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4985 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4986 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4987 %}
4988 %}
4989
4990 //----------OPERAND CLASSES----------------------------------------------------
4991 // Operand Classes are groups of operands that are used to simplify
4992 // instruction definitions by not requiring the AD writer to specify
4993 // seperate instructions for every form of operand when the
4994 // instruction accepts multiple operand types with the same basic
4995 // encoding and format. The classic case of this is memory operands.
4996 // Indirect is not included since its use is limited to Compare & Swap.
4997
4998 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow);
4999 // Memory operand where offsets are 4-aligned. Required for ld, std.
5000 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4);
5001 opclass indirectMemory(indirect, indirectNarrow);
5002
5003 // Special opclass for I and ConvL2I.
5004 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
5005
5006 // Operand classes to match encode and decode. iRegN_P2N is only used
5007 // for storeN. I have never seen an encode node elsewhere.
5008 opclass iRegN_P2N(iRegNsrc, iRegP2N);
5009 opclass iRegP_N2P(iRegPsrc, iRegN2P);
5010
5011 //----------PIPELINE-----------------------------------------------------------
5012
5013 pipeline %{
5014
5015 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
5016 // J. Res. & Dev., No. 1, Jan. 2002.
5017
5018 //----------ATTRIBUTES---------------------------------------------------------
5019 attributes %{
5020
5021 // Power4 instructions are of fixed length.
5022 fixed_size_instructions;
5023
5024 // TODO: if `bundle' means number of instructions fetched
5025 // per cycle, this is 8. If `bundle' means Power4 `group', that is
5026 // max instructions issued per cycle, this is 5.
5027 max_instructions_per_bundle = 8;
5028
5029 // A Power4 instruction is 4 bytes long.
5030 instruction_unit_size = 4;
5031
5032 // The Power4 processor fetches 64 bytes...
5033 instruction_fetch_unit_size = 64;
5034
5035 // ...in one line
5036 instruction_fetch_units = 1
5037
5038 // Unused, list one so that array generated by adlc is not empty.
5039 // Aix compiler chokes if _nop_count = 0.
5040 nops(fxNop);
5041 %}
5042
5043 //----------RESOURCES----------------------------------------------------------
5044 // Resources are the functional units available to the machine
5045 resources(
5046 PPC_BR, // branch unit
5047 PPC_CR, // condition unit
5048 PPC_FX1, // integer arithmetic unit 1
5049 PPC_FX2, // integer arithmetic unit 2
5050 PPC_LDST1, // load/store unit 1
5051 PPC_LDST2, // load/store unit 2
5052 PPC_FP1, // float arithmetic unit 1
5053 PPC_FP2, // float arithmetic unit 2
5054 PPC_LDST = PPC_LDST1 | PPC_LDST2,
5055 PPC_FX = PPC_FX1 | PPC_FX2,
5056 PPC_FP = PPC_FP1 | PPC_FP2
5057 );
5058
5059 //----------PIPELINE DESCRIPTION-----------------------------------------------
5060 // Pipeline Description specifies the stages in the machine's pipeline
5061 pipe_desc(
5062 // Power4 longest pipeline path
5063 PPC_IF, // instruction fetch
5064 PPC_IC,
5065 //PPC_BP, // branch prediction
5066 PPC_D0, // decode
5067 PPC_D1, // decode
5068 PPC_D2, // decode
5069 PPC_D3, // decode
5070 PPC_Xfer1,
5071 PPC_GD, // group definition
5072 PPC_MP, // map
5073 PPC_ISS, // issue
5074 PPC_RF, // resource fetch
5075 PPC_EX1, // execute (all units)
5076 PPC_EX2, // execute (FP, LDST)
5077 PPC_EX3, // execute (FP, LDST)
5078 PPC_EX4, // execute (FP)
5079 PPC_EX5, // execute (FP)
5080 PPC_EX6, // execute (FP)
5081 PPC_WB, // write back
5082 PPC_Xfer2,
5083 PPC_CP
5084 );
5085
5086 //----------PIPELINE CLASSES---------------------------------------------------
5087 // Pipeline Classes describe the stages in which input and output are
5088 // referenced by the hardware pipeline.
5089
5090 // Simple pipeline classes.
5091
5092 // Default pipeline class.
5093 pipe_class pipe_class_default() %{
5094 single_instruction;
5095 fixed_latency(2);
5096 %}
5097
5098 // Pipeline class for empty instructions.
5099 pipe_class pipe_class_empty() %{
5100 single_instruction;
5101 fixed_latency(0);
5102 %}
5103
5104 // Pipeline class for compares.
5105 pipe_class pipe_class_compare() %{
5106 single_instruction;
5107 fixed_latency(16);
5108 %}
5109
5110 // Pipeline class for traps.
5111 pipe_class pipe_class_trap() %{
5112 single_instruction;
5113 fixed_latency(100);
5114 %}
5115
5116 // Pipeline class for memory operations.
5117 pipe_class pipe_class_memory() %{
5118 single_instruction;
5119 fixed_latency(16);
5120 %}
5121
5122 // Pipeline class for call.
5123 pipe_class pipe_class_call() %{
5124 single_instruction;
5125 fixed_latency(100);
5126 %}
5127
5128 // Define the class for the Nop node.
5129 define %{
5130 MachNop = pipe_class_default;
5131 %}
5132
5133 %}
5134
5135 //----------INSTRUCTIONS-------------------------------------------------------
5136
5137 // Naming of instructions:
5138 // opA_operB / opA_operB_operC:
5139 // Operation 'op' with one or two source operands 'oper'. Result
5140 // type is A, source operand types are B and C.
5141 // Iff A == B == C, B and C are left out.
5142 //
5143 // The instructions are ordered according to the following scheme:
5144 // - loads
5145 // - load constants
5146 // - prefetch
5147 // - store
5148 // - encode/decode
5149 // - membar
5150 // - conditional moves
5151 // - compare & swap
5152 // - arithmetic and logic operations
5153 // * int: Add, Sub, Mul, Div, Mod
5154 // * int: lShift, arShift, urShift, rot
5155 // * float: Add, Sub, Mul, Div
5156 // * and, or, xor ...
5157 // - register moves: float <-> int, reg <-> stack, repl
5158 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5159 // - conv (low level type cast requiring bit changes (sign extend etc)
5160 // - compares, range & zero checks.
5161 // - branches
5162 // - complex operations, intrinsics, min, max, replicate
5163 // - lock
5164 // - Calls
5165 //
5166 // If there are similar instructions with different types they are sorted:
5167 // int before float
5168 // small before big
5169 // signed before unsigned
5170 // e.g., loadS before loadUS before loadI before loadF.
5171
5172
5173 //----------Load/Store Instructions--------------------------------------------
5174
5175 //----------Load Instructions--------------------------------------------------
5176
5177 // Converts byte to int.
5178 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5179 // reuses the 'amount' operand, but adlc expects that operand specification
5180 // and operands in match rule are equivalent.
5181 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5182 effect(DEF dst, USE src);
5183 format %{ "EXTSB $dst, $src \t// byte->int" %}
5184 size(4);
5185 ins_encode %{
5186 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5187 __ extsb($dst$$Register, $src$$Register);
5188 %}
5189 ins_pipe(pipe_class_default);
5190 %}
5191
5192 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5193 // match-rule, false predicate
5194 match(Set dst (LoadB mem));
5195 predicate(false);
5196
5197 format %{ "LBZ $dst, $mem" %}
5198 size(4);
5199 ins_encode( enc_lbz(dst, mem) );
5200 ins_pipe(pipe_class_memory);
5201 %}
5202
5203 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5204 // match-rule, false predicate
5205 match(Set dst (LoadB mem));
5206 predicate(false);
5207
5208 format %{ "LBZ $dst, $mem\n\t"
5209 "TWI $dst\n\t"
5210 "ISYNC" %}
5211 size(12);
5212 ins_encode( enc_lbz_ac(dst, mem) );
5213 ins_pipe(pipe_class_memory);
5214 %}
5215
5216 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5217 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5218 match(Set dst (LoadB mem));
5219 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5220 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5221 expand %{
5222 iRegIdst tmp;
5223 loadUB_indirect(tmp, mem);
5224 convB2I_reg_2(dst, tmp);
5225 %}
5226 %}
5227
5228 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5229 match(Set dst (LoadB mem));
5230 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5231 expand %{
5232 iRegIdst tmp;
5233 loadUB_indirect_ac(tmp, mem);
5234 convB2I_reg_2(dst, tmp);
5235 %}
5236 %}
5237
5238 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5239 // match-rule, false predicate
5240 match(Set dst (LoadB mem));
5241 predicate(false);
5242
5243 format %{ "LBZ $dst, $mem" %}
5244 size(4);
5245 ins_encode( enc_lbz(dst, mem) );
5246 ins_pipe(pipe_class_memory);
5247 %}
5248
5249 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5250 // match-rule, false predicate
5251 match(Set dst (LoadB mem));
5252 predicate(false);
5253
5254 format %{ "LBZ $dst, $mem\n\t"
5255 "TWI $dst\n\t"
5256 "ISYNC" %}
5257 size(12);
5258 ins_encode( enc_lbz_ac(dst, mem) );
5259 ins_pipe(pipe_class_memory);
5260 %}
5261
5262 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5263 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5264 match(Set dst (LoadB mem));
5265 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5266 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5267
5268 expand %{
5269 iRegIdst tmp;
5270 loadUB_indOffset16(tmp, mem);
5271 convB2I_reg_2(dst, tmp);
5272 %}
5273 %}
5274
5275 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5276 match(Set dst (LoadB mem));
5277 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5278
5279 expand %{
5280 iRegIdst tmp;
5281 loadUB_indOffset16_ac(tmp, mem);
5282 convB2I_reg_2(dst, tmp);
5283 %}
5284 %}
5285
5286 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5287 instruct loadUB(iRegIdst dst, memory mem) %{
5288 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5289 match(Set dst (LoadUB mem));
5290 ins_cost(MEMORY_REF_COST);
5291
5292 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5293 size(4);
5294 ins_encode( enc_lbz(dst, mem) );
5295 ins_pipe(pipe_class_memory);
5296 %}
5297
5298 // Load Unsigned Byte (8bit UNsigned) acquire.
5299 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5300 match(Set dst (LoadUB mem));
5301 ins_cost(3*MEMORY_REF_COST);
5302
5303 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5304 "TWI $dst\n\t"
5305 "ISYNC" %}
5306 size(12);
5307 ins_encode( enc_lbz_ac(dst, mem) );
5308 ins_pipe(pipe_class_memory);
5309 %}
5310
5311 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5312 instruct loadUB2L(iRegLdst dst, memory mem) %{
5313 match(Set dst (ConvI2L (LoadUB mem)));
5314 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5315 ins_cost(MEMORY_REF_COST);
5316
5317 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5318 size(4);
5319 ins_encode( enc_lbz(dst, mem) );
5320 ins_pipe(pipe_class_memory);
5321 %}
5322
5323 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5324 match(Set dst (ConvI2L (LoadUB mem)));
5325 ins_cost(3*MEMORY_REF_COST);
5326
5327 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5328 "TWI $dst\n\t"
5329 "ISYNC" %}
5330 size(12);
5331 ins_encode( enc_lbz_ac(dst, mem) );
5332 ins_pipe(pipe_class_memory);
5333 %}
5334
5335 // Load Short (16bit signed)
5336 instruct loadS(iRegIdst dst, memory mem) %{
5337 match(Set dst (LoadS mem));
5338 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5339 ins_cost(MEMORY_REF_COST);
5340
5341 format %{ "LHA $dst, $mem" %}
5342 size(4);
5343 ins_encode %{
5344 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5345 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5346 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5347 %}
5348 ins_pipe(pipe_class_memory);
5349 %}
5350
5351 // Load Short (16bit signed) acquire.
5352 instruct loadS_ac(iRegIdst dst, memory mem) %{
5353 match(Set dst (LoadS mem));
5354 ins_cost(3*MEMORY_REF_COST);
5355
5356 format %{ "LHA $dst, $mem\t acquire\n\t"
5357 "TWI $dst\n\t"
5358 "ISYNC" %}
5359 size(12);
5360 ins_encode %{
5361 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5362 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5363 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5364 __ twi_0($dst$$Register);
5365 __ isync();
5366 %}
5367 ins_pipe(pipe_class_memory);
5368 %}
5369
5370 // Load Char (16bit unsigned)
5371 instruct loadUS(iRegIdst dst, memory mem) %{
5372 match(Set dst (LoadUS mem));
5373 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5374 ins_cost(MEMORY_REF_COST);
5375
5376 format %{ "LHZ $dst, $mem" %}
5377 size(4);
5378 ins_encode( enc_lhz(dst, mem) );
5379 ins_pipe(pipe_class_memory);
5380 %}
5381
5382 // Load Char (16bit unsigned) acquire.
5383 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5384 match(Set dst (LoadUS mem));
5385 ins_cost(3*MEMORY_REF_COST);
5386
5387 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5388 "TWI $dst\n\t"
5389 "ISYNC" %}
5390 size(12);
5391 ins_encode( enc_lhz_ac(dst, mem) );
5392 ins_pipe(pipe_class_memory);
5393 %}
5394
5395 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5396 instruct loadUS2L(iRegLdst dst, memory mem) %{
5397 match(Set dst (ConvI2L (LoadUS mem)));
5398 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5399 ins_cost(MEMORY_REF_COST);
5400
5401 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5402 size(4);
5403 ins_encode( enc_lhz(dst, mem) );
5404 ins_pipe(pipe_class_memory);
5405 %}
5406
5407 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5408 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5409 match(Set dst (ConvI2L (LoadUS mem)));
5410 ins_cost(3*MEMORY_REF_COST);
5411
5412 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5413 "TWI $dst\n\t"
5414 "ISYNC" %}
5415 size(12);
5416 ins_encode( enc_lhz_ac(dst, mem) );
5417 ins_pipe(pipe_class_memory);
5418 %}
5419
5420 // Load Integer.
5421 instruct loadI(iRegIdst dst, memory mem) %{
5422 match(Set dst (LoadI mem));
5423 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5424 ins_cost(MEMORY_REF_COST);
5425
5426 format %{ "LWZ $dst, $mem" %}
5427 size(4);
5428 ins_encode( enc_lwz(dst, mem) );
5429 ins_pipe(pipe_class_memory);
5430 %}
5431
5432 // Load Integer acquire.
5433 instruct loadI_ac(iRegIdst dst, memory mem) %{
5434 match(Set dst (LoadI mem));
5435 ins_cost(3*MEMORY_REF_COST);
5436
5437 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5438 "TWI $dst\n\t"
5439 "ISYNC" %}
5440 size(12);
5441 ins_encode( enc_lwz_ac(dst, mem) );
5442 ins_pipe(pipe_class_memory);
5443 %}
5444
5445 // Match loading integer and casting it to unsigned int in
5446 // long register.
5447 // LoadI + ConvI2L + AndL 0xffffffff.
5448 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5449 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5450 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5451 ins_cost(MEMORY_REF_COST);
5452
5453 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5454 size(4);
5455 ins_encode( enc_lwz(dst, mem) );
5456 ins_pipe(pipe_class_memory);
5457 %}
5458
5459 // Match loading integer and casting it to long.
5460 instruct loadI2L(iRegLdst dst, memory mem) %{
5461 match(Set dst (ConvI2L (LoadI mem)));
5462 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5463 ins_cost(MEMORY_REF_COST);
5464
5465 format %{ "LWA $dst, $mem \t// loadI2L" %}
5466 size(4);
5467 ins_encode %{
5468 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5469 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5470 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5471 %}
5472 ins_pipe(pipe_class_memory);
5473 %}
5474
5475 // Match loading integer and casting it to long - acquire.
5476 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5477 match(Set dst (ConvI2L (LoadI mem)));
5478 ins_cost(3*MEMORY_REF_COST);
5479
5480 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5481 "TWI $dst\n\t"
5482 "ISYNC" %}
5483 size(12);
5484 ins_encode %{
5485 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5486 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5487 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5488 __ twi_0($dst$$Register);
5489 __ isync();
5490 %}
5491 ins_pipe(pipe_class_memory);
5492 %}
5493
5494 // Load Long - aligned
5495 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5496 match(Set dst (LoadL mem));
5497 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5498 ins_cost(MEMORY_REF_COST);
5499
5500 format %{ "LD $dst, $mem \t// long" %}
5501 size(4);
5502 ins_encode( enc_ld(dst, mem) );
5503 ins_pipe(pipe_class_memory);
5504 %}
5505
5506 // Load Long - aligned acquire.
5507 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5508 match(Set dst (LoadL mem));
5509 ins_cost(3*MEMORY_REF_COST);
5510
5511 format %{ "LD $dst, $mem \t// long acquire\n\t"
5512 "TWI $dst\n\t"
5513 "ISYNC" %}
5514 size(12);
5515 ins_encode( enc_ld_ac(dst, mem) );
5516 ins_pipe(pipe_class_memory);
5517 %}
5518
5519 // Load Long - UNaligned
5520 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5521 match(Set dst (LoadL_unaligned mem));
5522 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5523 ins_cost(MEMORY_REF_COST);
5524
5525 format %{ "LD $dst, $mem \t// unaligned long" %}
5526 size(4);
5527 ins_encode( enc_ld(dst, mem) );
5528 ins_pipe(pipe_class_memory);
5529 %}
5530
5531 // Load nodes for superwords
5532
5533 // Load Aligned Packed Byte
5534 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5535 predicate(n->as_LoadVector()->memory_size() == 8);
5536 match(Set dst (LoadVector mem));
5537 ins_cost(MEMORY_REF_COST);
5538
5539 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5540 size(4);
5541 ins_encode( enc_ld(dst, mem) );
5542 ins_pipe(pipe_class_memory);
5543 %}
5544
5545 // Load Range, range = array length (=jint)
5546 instruct loadRange(iRegIdst dst, memory mem) %{
5547 match(Set dst (LoadRange mem));
5548 ins_cost(MEMORY_REF_COST);
5549
5550 format %{ "LWZ $dst, $mem \t// range" %}
5551 size(4);
5552 ins_encode( enc_lwz(dst, mem) );
5553 ins_pipe(pipe_class_memory);
5554 %}
5555
5556 // Load Compressed Pointer
5557 instruct loadN(iRegNdst dst, memory mem) %{
5558 match(Set dst (LoadN mem));
5559 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5560 ins_cost(MEMORY_REF_COST);
5561
5562 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5563 size(4);
5564 ins_encode( enc_lwz(dst, mem) );
5565 ins_pipe(pipe_class_memory);
5566 %}
5567
5568 // Load Compressed Pointer acquire.
5569 instruct loadN_ac(iRegNdst dst, memory mem) %{
5570 match(Set dst (LoadN mem));
5571 ins_cost(3*MEMORY_REF_COST);
5572
5573 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5574 "TWI $dst\n\t"
5575 "ISYNC" %}
5576 size(12);
5577 ins_encode( enc_lwz_ac(dst, mem) );
5578 ins_pipe(pipe_class_memory);
5579 %}
5580
5581 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5582 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5583 match(Set dst (DecodeN (LoadN mem)));
5584 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5585 ins_cost(MEMORY_REF_COST);
5586
5587 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5588 size(4);
5589 ins_encode( enc_lwz(dst, mem) );
5590 ins_pipe(pipe_class_memory);
5591 %}
5592
5593 // Load Pointer
5594 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5595 match(Set dst (LoadP mem));
5596 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5597 ins_cost(MEMORY_REF_COST);
5598
5599 format %{ "LD $dst, $mem \t// ptr" %}
5600 size(4);
5601 ins_encode( enc_ld(dst, mem) );
5602 ins_pipe(pipe_class_memory);
5603 %}
5604
5605 // Load Pointer acquire.
5606 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5607 match(Set dst (LoadP mem));
5608 ins_cost(3*MEMORY_REF_COST);
5609
5610 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5611 "TWI $dst\n\t"
5612 "ISYNC" %}
5613 size(12);
5614 ins_encode( enc_ld_ac(dst, mem) );
5615 ins_pipe(pipe_class_memory);
5616 %}
5617
5618 // LoadP + CastP2L
5619 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5620 match(Set dst (CastP2X (LoadP mem)));
5621 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5622 ins_cost(MEMORY_REF_COST);
5623
5624 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5625 size(4);
5626 ins_encode( enc_ld(dst, mem) );
5627 ins_pipe(pipe_class_memory);
5628 %}
5629
5630 // Load compressed klass pointer.
5631 instruct loadNKlass(iRegNdst dst, memory mem) %{
5632 match(Set dst (LoadNKlass mem));
5633 ins_cost(MEMORY_REF_COST);
5634
5635 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5636 size(4);
5637 ins_encode( enc_lwz(dst, mem) );
5638 ins_pipe(pipe_class_memory);
5639 %}
5640
5641 //// Load compressed klass and decode it if narrow_klass_shift == 0.
5642 //// TODO: will narrow_klass_shift ever be 0?
5643 //instruct decodeNKlass2Klass(iRegPdst dst, memory mem) %{
5644 // match(Set dst (DecodeNKlass (LoadNKlass mem)));
5645 // predicate(false /* TODO: PPC port Universe::narrow_klass_shift() == 0*);
5646 // ins_cost(MEMORY_REF_COST);
5647 //
5648 // format %{ "LWZ $dst, $mem \t// DecodeNKlass (unscaled)" %}
5649 // size(4);
5650 // ins_encode( enc_lwz(dst, mem) );
5651 // ins_pipe(pipe_class_memory);
5652 //%}
5653
5654 // Load Klass Pointer
5655 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5656 match(Set dst (LoadKlass mem));
5657 ins_cost(MEMORY_REF_COST);
5658
5659 format %{ "LD $dst, $mem \t// klass ptr" %}
5660 size(4);
5661 ins_encode( enc_ld(dst, mem) );
5662 ins_pipe(pipe_class_memory);
5663 %}
5664
5665 // Load Float
5666 instruct loadF(regF dst, memory mem) %{
5667 match(Set dst (LoadF mem));
5668 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5669 ins_cost(MEMORY_REF_COST);
5670
5671 format %{ "LFS $dst, $mem" %}
5672 size(4);
5673 ins_encode %{
5674 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5675 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5676 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5677 %}
5678 ins_pipe(pipe_class_memory);
5679 %}
5680
5681 // Load Float acquire.
5682 instruct loadF_ac(regF dst, memory mem) %{
5683 match(Set dst (LoadF mem));
5684 ins_cost(3*MEMORY_REF_COST);
5685
5686 format %{ "LFS $dst, $mem \t// acquire\n\t"
5687 "FCMPU cr0, $dst, $dst\n\t"
5688 "BNE cr0, next\n"
5689 "next:\n\t"
5690 "ISYNC" %}
5691 size(16);
5692 ins_encode %{
5693 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5694 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5695 Label next;
5696 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5697 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5698 __ bne(CCR0, next);
5699 __ bind(next);
5700 __ isync();
5701 %}
5702 ins_pipe(pipe_class_memory);
5703 %}
5704
5705 // Load Double - aligned
5706 instruct loadD(regD dst, memory mem) %{
5707 match(Set dst (LoadD mem));
5708 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5709 ins_cost(MEMORY_REF_COST);
5710
5711 format %{ "LFD $dst, $mem" %}
5712 size(4);
5713 ins_encode( enc_lfd(dst, mem) );
5714 ins_pipe(pipe_class_memory);
5715 %}
5716
5717 // Load Double - aligned acquire.
5718 instruct loadD_ac(regD dst, memory mem) %{
5719 match(Set dst (LoadD mem));
5720 ins_cost(3*MEMORY_REF_COST);
5721
5722 format %{ "LFD $dst, $mem \t// acquire\n\t"
5723 "FCMPU cr0, $dst, $dst\n\t"
5724 "BNE cr0, next\n"
5725 "next:\n\t"
5726 "ISYNC" %}
5727 size(16);
5728 ins_encode %{
5729 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5730 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5731 Label next;
5732 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5733 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5734 __ bne(CCR0, next);
5735 __ bind(next);
5736 __ isync();
5737 %}
5738 ins_pipe(pipe_class_memory);
5739 %}
5740
5741 // Load Double - UNaligned
5742 instruct loadD_unaligned(regD dst, memory mem) %{
5743 match(Set dst (LoadD_unaligned mem));
5744 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5745 ins_cost(MEMORY_REF_COST);
5746
5747 format %{ "LFD $dst, $mem" %}
5748 size(4);
5749 ins_encode( enc_lfd(dst, mem) );
5750 ins_pipe(pipe_class_memory);
5751 %}
5752
5753 //----------Constants--------------------------------------------------------
5754
5755 // Load MachConstantTableBase: add hi offset to global toc.
5756 // TODO: Handle hidden register r29 in bundler!
5757 instruct loadToc_hi(iRegLdst dst) %{
5758 effect(DEF dst);
5759 ins_cost(DEFAULT_COST);
5760
5761 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5762 size(4);
5763 ins_encode %{
5764 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5765 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5766 %}
5767 ins_pipe(pipe_class_default);
5768 %}
5769
5770 // Load MachConstantTableBase: add lo offset to global toc.
5771 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5772 effect(DEF dst, USE src);
5773 ins_cost(DEFAULT_COST);
5774
5775 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5776 size(4);
5777 ins_encode %{
5778 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5779 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5780 %}
5781 ins_pipe(pipe_class_default);
5782 %}
5783
5784 // Load 16-bit integer constant 0xssss????
5785 instruct loadConI16(iRegIdst dst, immI16 src) %{
5786 match(Set dst src);
5787
5788 format %{ "LI $dst, $src" %}
5789 size(4);
5790 ins_encode %{
5791 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5792 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5793 %}
5794 ins_pipe(pipe_class_default);
5795 %}
5796
5797 // Load integer constant 0x????0000
5798 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5799 match(Set dst src);
5800 ins_cost(DEFAULT_COST);
5801
5802 format %{ "LIS $dst, $src.hi" %}
5803 size(4);
5804 ins_encode %{
5805 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5806 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5807 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5808 %}
5809 ins_pipe(pipe_class_default);
5810 %}
5811
5812 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5813 // and sign extended), this adds the low 16 bits.
5814 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5815 // no match-rule, false predicate
5816 effect(DEF dst, USE src1, USE src2);
5817 predicate(false);
5818
5819 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5820 size(4);
5821 ins_encode %{
5822 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5823 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5824 %}
5825 ins_pipe(pipe_class_default);
5826 %}
5827
5828 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5829 match(Set dst src);
5830 ins_cost(DEFAULT_COST*2);
5831
5832 expand %{
5833 // Would like to use $src$$constant.
5834 immI16 srcLo %{ _opnds[1]->constant() %}
5835 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5836 immIhi16 srcHi %{ _opnds[1]->constant() %}
5837 iRegIdst tmpI;
5838 loadConIhi16(tmpI, srcHi);
5839 loadConI32_lo16(dst, tmpI, srcLo);
5840 %}
5841 %}
5842
5843 // No constant pool entries required.
5844 instruct loadConL16(iRegLdst dst, immL16 src) %{
5845 match(Set dst src);
5846
5847 format %{ "LI $dst, $src \t// long" %}
5848 size(4);
5849 ins_encode %{
5850 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5851 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5852 %}
5853 ins_pipe(pipe_class_default);
5854 %}
5855
5856 // Load long constant 0xssssssss????0000
5857 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5858 match(Set dst src);
5859 ins_cost(DEFAULT_COST);
5860
5861 format %{ "LIS $dst, $src.hi \t// long" %}
5862 size(4);
5863 ins_encode %{
5864 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5865 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5866 %}
5867 ins_pipe(pipe_class_default);
5868 %}
5869
5870 // To load a 32 bit constant: merge lower 16 bits into already loaded
5871 // high 16 bits.
5872 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5873 // no match-rule, false predicate
5874 effect(DEF dst, USE src1, USE src2);
5875 predicate(false);
5876
5877 format %{ "ORI $dst, $src1, $src2.lo" %}
5878 size(4);
5879 ins_encode %{
5880 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5881 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5882 %}
5883 ins_pipe(pipe_class_default);
5884 %}
5885
5886 // Load 32-bit long constant
5887 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5888 match(Set dst src);
5889 ins_cost(DEFAULT_COST*2);
5890
5891 expand %{
5892 // Would like to use $src$$constant.
5893 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5894 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5895 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5896 iRegLdst tmpL;
5897 loadConL32hi16(tmpL, srcHi);
5898 loadConL32_lo16(dst, tmpL, srcLo);
5899 %}
5900 %}
5901
5902 // Load long constant 0x????000000000000.
5903 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5904 match(Set dst src);
5905 ins_cost(DEFAULT_COST);
5906
5907 expand %{
5908 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5909 immI shift32 %{ 32 %}
5910 iRegLdst tmpL;
5911 loadConL32hi16(tmpL, srcHi);
5912 lshiftL_regL_immI(dst, tmpL, shift32);
5913 %}
5914 %}
5915
5916 // Expand node for constant pool load: small offset.
5917 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5918 effect(DEF dst, USE src, USE toc);
5919 ins_cost(MEMORY_REF_COST);
5920
5921 ins_num_consts(1);
5922 // Needed so that CallDynamicJavaDirect can compute the address of this
5923 // instruction for relocation.
5924 ins_field_cbuf_insts_offset(int);
5925
5926 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5927 size(4);
5928 ins_encode( enc_load_long_constL(dst, src, toc) );
5929 ins_pipe(pipe_class_memory);
5930 %}
5931
5932 // Expand node for constant pool load: large offset.
5933 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5934 effect(DEF dst, USE src, USE toc);
5935 predicate(false);
5936
5937 ins_num_consts(1);
5938 ins_field_const_toc_offset(int);
5939 // Needed so that CallDynamicJavaDirect can compute the address of this
5940 // instruction for relocation.
5941 ins_field_cbuf_insts_offset(int);
5942
5943 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5944 size(4);
5945 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5946 ins_pipe(pipe_class_default);
5947 %}
5948
5949 // Expand node for constant pool load: large offset.
5950 // No constant pool entries required.
5951 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5952 effect(DEF dst, USE src, USE base);
5953 predicate(false);
5954
5955 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5956
5957 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5958 size(4);
5959 ins_encode %{
5960 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5961 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5962 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5963 %}
5964 ins_pipe(pipe_class_memory);
5965 %}
5966
5967 // Load long constant from constant table. Expand in case of
5968 // offset > 16 bit is needed.
5969 // Adlc adds toc node MachConstantTableBase.
5970 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5971 match(Set dst src);
5972 ins_cost(MEMORY_REF_COST);
5973
5974 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5975 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5976 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5977 %}
5978
5979 // Load NULL as compressed oop.
5980 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5981 match(Set dst src);
5982 ins_cost(DEFAULT_COST);
5983
5984 format %{ "LI $dst, $src \t// compressed ptr" %}
5985 size(4);
5986 ins_encode %{
5987 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5988 __ li($dst$$Register, 0);
5989 %}
5990 ins_pipe(pipe_class_default);
5991 %}
5992
5993 // Load hi part of compressed oop constant.
5994 instruct loadConN_hi(iRegNdst dst, immN src) %{
5995 effect(DEF dst, USE src);
5996 ins_cost(DEFAULT_COST);
5997
5998 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5999 size(4);
6000 ins_encode %{
6001 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6002 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
6003 %}
6004 ins_pipe(pipe_class_default);
6005 %}
6006
6007 // Add lo part of compressed oop constant to already loaded hi part.
6008 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
6009 effect(DEF dst, USE src1, USE src2);
6010 ins_cost(DEFAULT_COST);
6011
6012 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
6013 size(4);
6014 ins_encode %{
6015 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6016 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6017 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
6018 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6019 __ relocate(rspec, 1);
6020 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
6021 %}
6022 ins_pipe(pipe_class_default);
6023 %}
6024
6025 // Needed to postalloc expand loadConN: ConN is loaded as ConI
6026 // leaving the upper 32 bits with sign-extension bits.
6027 // This clears these bits: dst = src & 0xFFFFFFFF.
6028 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6029 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6030 effect(DEF dst, USE src);
6031 predicate(false);
6032
6033 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
6034 size(4);
6035 ins_encode %{
6036 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6037 __ clrldi($dst$$Register, $src$$Register, 0x20);
6038 %}
6039 ins_pipe(pipe_class_default);
6040 %}
6041
6042 // Loading ConN must be postalloc expanded so that edges between
6043 // the nodes are safe. They may not interfere with a safepoint.
6044 // GL TODO: This needs three instructions: better put this into the constant pool.
6045 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6046 match(Set dst src);
6047 ins_cost(DEFAULT_COST*2);
6048
6049 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6050 postalloc_expand %{
6051 MachNode *m1 = new loadConN_hiNode();
6052 MachNode *m2 = new loadConN_loNode();
6053 MachNode *m3 = new clearMs32bNode();
6054 m1->add_req(NULL);
6055 m2->add_req(NULL, m1);
6056 m3->add_req(NULL, m2);
6057 m1->_opnds[0] = op_dst;
6058 m1->_opnds[1] = op_src;
6059 m2->_opnds[0] = op_dst;
6060 m2->_opnds[1] = op_dst;
6061 m2->_opnds[2] = op_src;
6062 m3->_opnds[0] = op_dst;
6063 m3->_opnds[1] = op_dst;
6064 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6065 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6066 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6067 nodes->push(m1);
6068 nodes->push(m2);
6069 nodes->push(m3);
6070 %}
6071 %}
6072
6073 instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{
6074 effect(DEF dst, USE src);
6075 ins_cost(DEFAULT_COST);
6076
6077 format %{ "LIS $dst, $src \t// narrow oop hi" %}
6078 size(4);
6079 ins_encode %{
6080 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6081 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6082 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6083 %}
6084 ins_pipe(pipe_class_default);
6085 %}
6086
6087 // This needs a match rule so that build_oop_map knows this is
6088 // not a narrow oop.
6089 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6090 match(Set dst src1);
6091 effect(TEMP src2);
6092 ins_cost(DEFAULT_COST);
6093
6094 format %{ "ADDI $dst, $src1, $src2 \t// narrow oop lo" %}
6095 size(4);
6096 ins_encode %{
6097 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6098 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6099 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6100 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6101 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6102
6103 __ relocate(rspec, 1);
6104 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6105 %}
6106 ins_pipe(pipe_class_default);
6107 %}
6108
6109 // Loading ConNKlass must be postalloc expanded so that edges between
6110 // the nodes are safe. They may not interfere with a safepoint.
6111 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6112 match(Set dst src);
6113 ins_cost(DEFAULT_COST*2);
6114
6115 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6116 postalloc_expand %{
6117 // Load high bits into register. Sign extended.
6118 MachNode *m1 = new loadConNKlass_hiNode();
6119 m1->add_req(NULL);
6120 m1->_opnds[0] = op_dst;
6121 m1->_opnds[1] = op_src;
6122 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6123 nodes->push(m1);
6124
6125 MachNode *m2 = m1;
6126 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6127 // Value might be 1-extended. Mask out these bits.
6128 m2 = new clearMs32bNode();
6129 m2->add_req(NULL, m1);
6130 m2->_opnds[0] = op_dst;
6131 m2->_opnds[1] = op_dst;
6132 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6133 nodes->push(m2);
6134 }
6135
6136 MachNode *m3 = new loadConNKlass_loNode();
6137 m3->add_req(NULL, m2);
6138 m3->_opnds[0] = op_dst;
6139 m3->_opnds[1] = op_src;
6140 m3->_opnds[2] = op_dst;
6141 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6142 nodes->push(m3);
6143 %}
6144 %}
6145
6146 // 0x1 is used in object initialization (initial object header).
6147 // No constant pool entries required.
6148 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6149 match(Set dst src);
6150
6151 format %{ "LI $dst, $src \t// ptr" %}
6152 size(4);
6153 ins_encode %{
6154 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6155 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6156 %}
6157 ins_pipe(pipe_class_default);
6158 %}
6159
6160 // Expand node for constant pool load: small offset.
6161 // The match rule is needed to generate the correct bottom_type(),
6162 // however this node should never match. The use of predicate is not
6163 // possible since ADLC forbids predicates for chain rules. The higher
6164 // costs do not prevent matching in this case. For that reason the
6165 // operand immP_NM with predicate(false) is used.
6166 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6167 match(Set dst src);
6168 effect(TEMP toc);
6169
6170 ins_num_consts(1);
6171
6172 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6173 size(4);
6174 ins_encode( enc_load_long_constP(dst, src, toc) );
6175 ins_pipe(pipe_class_memory);
6176 %}
6177
6178 // Expand node for constant pool load: large offset.
6179 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6180 effect(DEF dst, USE src, USE toc);
6181 predicate(false);
6182
6183 ins_num_consts(1);
6184 ins_field_const_toc_offset(int);
6185
6186 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6187 size(4);
6188 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6189 ins_pipe(pipe_class_default);
6190 %}
6191
6192 // Expand node for constant pool load: large offset.
6193 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6194 match(Set dst src);
6195 effect(TEMP base);
6196
6197 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6198
6199 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6200 size(4);
6201 ins_encode %{
6202 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6203 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6204 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6205 %}
6206 ins_pipe(pipe_class_memory);
6207 %}
6208
6209 // Load pointer constant from constant table. Expand in case an
6210 // offset > 16 bit is needed.
6211 // Adlc adds toc node MachConstantTableBase.
6212 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6213 match(Set dst src);
6214 ins_cost(MEMORY_REF_COST);
6215
6216 // This rule does not use "expand" because then
6217 // the result type is not known to be an Oop. An ADLC
6218 // enhancement will be needed to make that work - not worth it!
6219
6220 // If this instruction rematerializes, it prolongs the live range
6221 // of the toc node, causing illegal graphs.
6222 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6223 ins_cannot_rematerialize(true);
6224
6225 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6226 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6227 %}
6228
6229 // Expand node for constant pool load: small offset.
6230 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6231 effect(DEF dst, USE src, USE toc);
6232 ins_cost(MEMORY_REF_COST);
6233
6234 ins_num_consts(1);
6235
6236 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6237 size(4);
6238 ins_encode %{
6239 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6240 address float_address = __ float_constant($src$$constant);
6241 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6242 %}
6243 ins_pipe(pipe_class_memory);
6244 %}
6245
6246 // Expand node for constant pool load: large offset.
6247 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6248 effect(DEF dst, USE src, USE toc);
6249 ins_cost(MEMORY_REF_COST);
6250
6251 ins_num_consts(1);
6252
6253 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6254 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6255 "ADDIS $toc, $toc, -offset_hi"%}
6256 size(12);
6257 ins_encode %{
6258 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6259 FloatRegister Rdst = $dst$$FloatRegister;
6260 Register Rtoc = $toc$$Register;
6261 address float_address = __ float_constant($src$$constant);
6262 int offset = __ offset_to_method_toc(float_address);
6263 int hi = (offset + (1<<15))>>16;
6264 int lo = offset - hi * (1<<16);
6265
6266 __ addis(Rtoc, Rtoc, hi);
6267 __ lfs(Rdst, lo, Rtoc);
6268 __ addis(Rtoc, Rtoc, -hi);
6269 %}
6270 ins_pipe(pipe_class_memory);
6271 %}
6272
6273 // Adlc adds toc node MachConstantTableBase.
6274 instruct loadConF_Ex(regF dst, immF src) %{
6275 match(Set dst src);
6276 ins_cost(MEMORY_REF_COST);
6277
6278 // See loadConP.
6279 ins_cannot_rematerialize(true);
6280
6281 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6282 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6283 %}
6284
6285 // Expand node for constant pool load: small offset.
6286 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6287 effect(DEF dst, USE src, USE toc);
6288 ins_cost(MEMORY_REF_COST);
6289
6290 ins_num_consts(1);
6291
6292 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6293 size(4);
6294 ins_encode %{
6295 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6296 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6297 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6298 %}
6299 ins_pipe(pipe_class_memory);
6300 %}
6301
6302 // Expand node for constant pool load: large offset.
6303 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6304 effect(DEF dst, USE src, USE toc);
6305 ins_cost(MEMORY_REF_COST);
6306
6307 ins_num_consts(1);
6308
6309 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6310 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6311 "ADDIS $toc, $toc, -offset_hi" %}
6312 size(12);
6313 ins_encode %{
6314 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6315 FloatRegister Rdst = $dst$$FloatRegister;
6316 Register Rtoc = $toc$$Register;
6317 address float_address = __ double_constant($src$$constant);
6318 int offset = __ offset_to_method_toc(float_address);
6319 int hi = (offset + (1<<15))>>16;
6320 int lo = offset - hi * (1<<16);
6321
6322 __ addis(Rtoc, Rtoc, hi);
6323 __ lfd(Rdst, lo, Rtoc);
6324 __ addis(Rtoc, Rtoc, -hi);
6325 %}
6326 ins_pipe(pipe_class_memory);
6327 %}
6328
6329 // Adlc adds toc node MachConstantTableBase.
6330 instruct loadConD_Ex(regD dst, immD src) %{
6331 match(Set dst src);
6332 ins_cost(MEMORY_REF_COST);
6333
6334 // See loadConP.
6335 ins_cannot_rematerialize(true);
6336
6337 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6338 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6339 %}
6340
6341 // Prefetch instructions.
6342 // Must be safe to execute with invalid address (cannot fault).
6343
6344 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{
6345 match(PrefetchRead (AddP mem src));
6346 ins_cost(MEMORY_REF_COST);
6347
6348 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %}
6349 size(4);
6350 ins_encode %{
6351 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6352 __ dcbt($src$$Register, $mem$$base$$Register);
6353 %}
6354 ins_pipe(pipe_class_memory);
6355 %}
6356
6357 instruct prefetchr_no_offset(indirectMemory mem) %{
6358 match(PrefetchRead mem);
6359 ins_cost(MEMORY_REF_COST);
6360
6361 format %{ "PREFETCH $mem" %}
6362 size(4);
6363 ins_encode %{
6364 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6365 __ dcbt($mem$$base$$Register);
6366 %}
6367 ins_pipe(pipe_class_memory);
6368 %}
6369
6370 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{
6371 match(PrefetchWrite (AddP mem src));
6372 ins_cost(MEMORY_REF_COST);
6373
6374 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %}
6375 size(4);
6376 ins_encode %{
6377 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6378 __ dcbtst($src$$Register, $mem$$base$$Register);
6379 %}
6380 ins_pipe(pipe_class_memory);
6381 %}
6382
6383 instruct prefetchw_no_offset(indirectMemory mem) %{
6384 match(PrefetchWrite mem);
6385 ins_cost(MEMORY_REF_COST);
6386
6387 format %{ "PREFETCH $mem" %}
6388 size(4);
6389 ins_encode %{
6390 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6391 __ dcbtst($mem$$base$$Register);
6392 %}
6393 ins_pipe(pipe_class_memory);
6394 %}
6395
6396 // Special prefetch versions which use the dcbz instruction.
6397 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6398 match(PrefetchAllocation (AddP mem src));
6399 predicate(AllocatePrefetchStyle == 3);
6400 ins_cost(MEMORY_REF_COST);
6401
6402 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6403 size(4);
6404 ins_encode %{
6405 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6406 __ dcbz($src$$Register, $mem$$base$$Register);
6407 %}
6408 ins_pipe(pipe_class_memory);
6409 %}
6410
6411 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6412 match(PrefetchAllocation mem);
6413 predicate(AllocatePrefetchStyle == 3);
6414 ins_cost(MEMORY_REF_COST);
6415
6416 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6417 size(4);
6418 ins_encode %{
6419 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6420 __ dcbz($mem$$base$$Register);
6421 %}
6422 ins_pipe(pipe_class_memory);
6423 %}
6424
6425 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6426 match(PrefetchAllocation (AddP mem src));
6427 predicate(AllocatePrefetchStyle != 3);
6428 ins_cost(MEMORY_REF_COST);
6429
6430 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6431 size(4);
6432 ins_encode %{
6433 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6434 __ dcbtst($src$$Register, $mem$$base$$Register);
6435 %}
6436 ins_pipe(pipe_class_memory);
6437 %}
6438
6439 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6440 match(PrefetchAllocation mem);
6441 predicate(AllocatePrefetchStyle != 3);
6442 ins_cost(MEMORY_REF_COST);
6443
6444 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6445 size(4);
6446 ins_encode %{
6447 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6448 __ dcbtst($mem$$base$$Register);
6449 %}
6450 ins_pipe(pipe_class_memory);
6451 %}
6452
6453 //----------Store Instructions-------------------------------------------------
6454
6455 // Store Byte
6456 instruct storeB(memory mem, iRegIsrc src) %{
6457 match(Set mem (StoreB mem src));
6458 ins_cost(MEMORY_REF_COST);
6459
6460 format %{ "STB $src, $mem \t// byte" %}
6461 size(4);
6462 ins_encode %{
6463 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6464 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6465 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6466 %}
6467 ins_pipe(pipe_class_memory);
6468 %}
6469
6470 // Store Char/Short
6471 instruct storeC(memory mem, iRegIsrc src) %{
6472 match(Set mem (StoreC mem src));
6473 ins_cost(MEMORY_REF_COST);
6474
6475 format %{ "STH $src, $mem \t// short" %}
6476 size(4);
6477 ins_encode %{
6478 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6479 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6480 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6481 %}
6482 ins_pipe(pipe_class_memory);
6483 %}
6484
6485 // Store Integer
6486 instruct storeI(memory mem, iRegIsrc src) %{
6487 match(Set mem (StoreI mem src));
6488 ins_cost(MEMORY_REF_COST);
6489
6490 format %{ "STW $src, $mem" %}
6491 size(4);
6492 ins_encode( enc_stw(src, mem) );
6493 ins_pipe(pipe_class_memory);
6494 %}
6495
6496 // ConvL2I + StoreI.
6497 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6498 match(Set mem (StoreI mem (ConvL2I src)));
6499 ins_cost(MEMORY_REF_COST);
6500
6501 format %{ "STW l2i($src), $mem" %}
6502 size(4);
6503 ins_encode( enc_stw(src, mem) );
6504 ins_pipe(pipe_class_memory);
6505 %}
6506
6507 // Store Long
6508 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6509 match(Set mem (StoreL mem src));
6510 ins_cost(MEMORY_REF_COST);
6511
6512 format %{ "STD $src, $mem \t// long" %}
6513 size(4);
6514 ins_encode( enc_std(src, mem) );
6515 ins_pipe(pipe_class_memory);
6516 %}
6517
6518 // Store super word nodes.
6519
6520 // Store Aligned Packed Byte long register to memory
6521 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6522 predicate(n->as_StoreVector()->memory_size() == 8);
6523 match(Set mem (StoreVector mem src));
6524 ins_cost(MEMORY_REF_COST);
6525
6526 format %{ "STD $mem, $src \t// packed8B" %}
6527 size(4);
6528 ins_encode( enc_std(src, mem) );
6529 ins_pipe(pipe_class_memory);
6530 %}
6531
6532 // Store Compressed Oop
6533 instruct storeN(memory dst, iRegN_P2N src) %{
6534 match(Set dst (StoreN dst src));
6535 ins_cost(MEMORY_REF_COST);
6536
6537 format %{ "STW $src, $dst \t// compressed oop" %}
6538 size(4);
6539 ins_encode( enc_stw(src, dst) );
6540 ins_pipe(pipe_class_memory);
6541 %}
6542
6543 // Store Compressed KLass
6544 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6545 match(Set dst (StoreNKlass dst src));
6546 ins_cost(MEMORY_REF_COST);
6547
6548 format %{ "STW $src, $dst \t// compressed klass" %}
6549 size(4);
6550 ins_encode( enc_stw(src, dst) );
6551 ins_pipe(pipe_class_memory);
6552 %}
6553
6554 // Store Pointer
6555 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6556 match(Set dst (StoreP dst src));
6557 ins_cost(MEMORY_REF_COST);
6558
6559 format %{ "STD $src, $dst \t// ptr" %}
6560 size(4);
6561 ins_encode( enc_std(src, dst) );
6562 ins_pipe(pipe_class_memory);
6563 %}
6564
6565 // Store Float
6566 instruct storeF(memory mem, regF src) %{
6567 match(Set mem (StoreF mem src));
6568 ins_cost(MEMORY_REF_COST);
6569
6570 format %{ "STFS $src, $mem" %}
6571 size(4);
6572 ins_encode( enc_stfs(src, mem) );
6573 ins_pipe(pipe_class_memory);
6574 %}
6575
6576 // Store Double
6577 instruct storeD(memory mem, regD src) %{
6578 match(Set mem (StoreD mem src));
6579 ins_cost(MEMORY_REF_COST);
6580
6581 format %{ "STFD $src, $mem" %}
6582 size(4);
6583 ins_encode( enc_stfd(src, mem) );
6584 ins_pipe(pipe_class_memory);
6585 %}
6586
6587 //----------Store Instructions With Zeros--------------------------------------
6588
6589 // Card-mark for CMS garbage collection.
6590 // This cardmark does an optimization so that it must not always
6591 // do a releasing store. For this, it gets the address of
6592 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6593 // (Using releaseFieldAddr in the match rule is a hack.)
6594 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{
6595 match(Set mem (StoreCM mem releaseFieldAddr));
6596 predicate(false);
6597 ins_cost(MEMORY_REF_COST);
6598
6599 // See loadConP.
6600 ins_cannot_rematerialize(true);
6601
6602 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6603 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) );
6604 ins_pipe(pipe_class_memory);
6605 %}
6606
6607 // Card-mark for CMS garbage collection.
6608 // This cardmark does an optimization so that it must not always
6609 // do a releasing store. For this, it needs the constant address of
6610 // CMSCollectorCardTableModRefBSExt::_requires_release.
6611 // This constant address is split off here by expand so we can use
6612 // adlc / matcher functionality to load it from the constant section.
6613 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6614 match(Set mem (StoreCM mem zero));
6615 predicate(UseConcMarkSweepGC);
6616
6617 expand %{
6618 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6619 iRegLdst releaseFieldAddress;
6620 loadConL_Ex(releaseFieldAddress, baseImm);
6621 storeCM_CMS(mem, releaseFieldAddress);
6622 %}
6623 %}
6624
6625 instruct storeCM_G1(memory mem, immI_0 zero) %{
6626 match(Set mem (StoreCM mem zero));
6627 predicate(UseG1GC);
6628 ins_cost(MEMORY_REF_COST);
6629
6630 ins_cannot_rematerialize(true);
6631
6632 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6633 size(8);
6634 ins_encode %{
6635 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6636 __ li(R0, 0);
6637 //__ release(); // G1: oops are allowed to get visible after dirty marking
6638 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6639 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6640 %}
6641 ins_pipe(pipe_class_memory);
6642 %}
6643
6644 // Convert oop pointer into compressed form.
6645
6646 // Nodes for postalloc expand.
6647
6648 // Shift node for expand.
6649 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6650 // The match rule is needed to make it a 'MachTypeNode'!
6651 match(Set dst (EncodeP src));
6652 predicate(false);
6653
6654 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6655 size(4);
6656 ins_encode %{
6657 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6658 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6659 %}
6660 ins_pipe(pipe_class_default);
6661 %}
6662
6663 // Add node for expand.
6664 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6665 // The match rule is needed to make it a 'MachTypeNode'!
6666 match(Set dst (EncodeP src));
6667 predicate(false);
6668
6669 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6670 size(4);
6671 ins_encode %{
6672 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6673 __ subf($dst$$Register, R30, $src$$Register);
6674 %}
6675 ins_pipe(pipe_class_default);
6676 %}
6677
6678 // Conditional sub base.
6679 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6680 // The match rule is needed to make it a 'MachTypeNode'!
6681 match(Set dst (EncodeP (Binary crx src1)));
6682 predicate(false);
6683
6684 ins_variable_size_depending_on_alignment(true);
6685
6686 format %{ "BEQ $crx, done\n\t"
6687 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n"
6688 "done:" %}
6689 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
6690 ins_encode %{
6691 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6692 Label done;
6693 __ beq($crx$$CondRegister, done);
6694 __ subf($dst$$Register, R30, $src1$$Register);
6695 // TODO PPC port __ endgroup_if_needed(_size == 12);
6696 __ bind(done);
6697 %}
6698 ins_pipe(pipe_class_default);
6699 %}
6700
6701 // Power 7 can use isel instruction
6702 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6703 // The match rule is needed to make it a 'MachTypeNode'!
6704 match(Set dst (EncodeP (Binary crx src1)));
6705 predicate(false);
6706
6707 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6708 size(4);
6709 ins_encode %{
6710 // This is a Power7 instruction for which no machine description exists.
6711 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6712 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6713 %}
6714 ins_pipe(pipe_class_default);
6715 %}
6716
6717 // base != 0
6718 // 32G aligned narrow oop base.
6719 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{
6720 match(Set dst (EncodeP src));
6721 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/);
6722
6723 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6724 size(4);
6725 ins_encode %{
6726 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6727 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6728 %}
6729 ins_pipe(pipe_class_default);
6730 %}
6731
6732 // shift != 0, base != 0
6733 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6734 match(Set dst (EncodeP src));
6735 effect(TEMP crx);
6736 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6737 Universe::narrow_oop_shift() != 0 &&
6738 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6739
6740 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6741 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6742 %}
6743
6744 // shift != 0, base != 0
6745 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6746 match(Set dst (EncodeP src));
6747 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6748 Universe::narrow_oop_shift() != 0 &&
6749 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6750
6751 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6752 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6753 %}
6754
6755 // shift != 0, base == 0
6756 // TODO: This is the same as encodeP_shift. Merge!
6757 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6758 match(Set dst (EncodeP src));
6759 predicate(Universe::narrow_oop_shift() != 0 &&
6760 Universe::narrow_oop_base() ==0);
6761
6762 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6763 size(4);
6764 ins_encode %{
6765 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6766 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6767 %}
6768 ins_pipe(pipe_class_default);
6769 %}
6770
6771 // Compressed OOPs with narrow_oop_shift == 0.
6772 // shift == 0, base == 0
6773 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6774 match(Set dst (EncodeP src));
6775 predicate(Universe::narrow_oop_shift() == 0);
6776
6777 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6778 // variable size, 0 or 4.
6779 ins_encode %{
6780 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6781 __ mr_if_needed($dst$$Register, $src$$Register);
6782 %}
6783 ins_pipe(pipe_class_default);
6784 %}
6785
6786 // Decode nodes.
6787
6788 // Shift node for expand.
6789 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6790 // The match rule is needed to make it a 'MachTypeNode'!
6791 match(Set dst (DecodeN src));
6792 predicate(false);
6793
6794 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6795 size(4);
6796 ins_encode %{
6797 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6798 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6799 %}
6800 ins_pipe(pipe_class_default);
6801 %}
6802
6803 // Add node for expand.
6804 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6805 // The match rule is needed to make it a 'MachTypeNode'!
6806 match(Set dst (DecodeN src));
6807 predicate(false);
6808
6809 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %}
6810 size(4);
6811 ins_encode %{
6812 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6813 __ add($dst$$Register, $src$$Register, R30);
6814 %}
6815 ins_pipe(pipe_class_default);
6816 %}
6817
6818 // conditianal add base for expand
6819 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6820 // The match rule is needed to make it a 'MachTypeNode'!
6821 // NOTICE that the rule is nonsense - we just have to make sure that:
6822 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6823 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6824 match(Set dst (DecodeN (Binary crx src1)));
6825 predicate(false);
6826
6827 ins_variable_size_depending_on_alignment(true);
6828
6829 format %{ "BEQ $crx, done\n\t"
6830 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n"
6831 "done:" %}
6832 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8);
6833 ins_encode %{
6834 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6835 Label done;
6836 __ beq($crx$$CondRegister, done);
6837 __ add($dst$$Register, $src1$$Register, R30);
6838 // TODO PPC port __ endgroup_if_needed(_size == 12);
6839 __ bind(done);
6840 %}
6841 ins_pipe(pipe_class_default);
6842 %}
6843
6844 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6845 // The match rule is needed to make it a 'MachTypeNode'!
6846 // NOTICE that the rule is nonsense - we just have to make sure that:
6847 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6848 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6849 match(Set dst (DecodeN (Binary crx src1)));
6850 predicate(false);
6851
6852 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6853 size(4);
6854 ins_encode %{
6855 // This is a Power7 instruction for which no machine description exists.
6856 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6857 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6858 %}
6859 ins_pipe(pipe_class_default);
6860 %}
6861
6862 // shift != 0, base != 0
6863 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6864 match(Set dst (DecodeN src));
6865 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6866 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6867 Universe::narrow_oop_shift() != 0 &&
6868 Universe::narrow_oop_base() != 0);
6869 effect(TEMP crx);
6870
6871 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6872 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6873 %}
6874
6875 // shift != 0, base == 0
6876 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6877 match(Set dst (DecodeN src));
6878 predicate(Universe::narrow_oop_shift() != 0 &&
6879 Universe::narrow_oop_base() == 0);
6880
6881 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6882 size(4);
6883 ins_encode %{
6884 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6885 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6886 %}
6887 ins_pipe(pipe_class_default);
6888 %}
6889
6890 // src != 0, shift != 0, base != 0
6891 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6892 match(Set dst (DecodeN src));
6893 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6894 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6895 Universe::narrow_oop_shift() != 0 &&
6896 Universe::narrow_oop_base() != 0);
6897
6898 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6899 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6900 %}
6901
6902 // Compressed OOPs with narrow_oop_shift == 0.
6903 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6904 match(Set dst (DecodeN src));
6905 predicate(Universe::narrow_oop_shift() == 0);
6906 ins_cost(DEFAULT_COST);
6907
6908 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6909 // variable size, 0 or 4.
6910 ins_encode %{
6911 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6912 __ mr_if_needed($dst$$Register, $src$$Register);
6913 %}
6914 ins_pipe(pipe_class_default);
6915 %}
6916
6917 // Convert compressed oop into int for vectors alignment masking.
6918 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6919 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6920 predicate(Universe::narrow_oop_shift() == 0);
6921 ins_cost(DEFAULT_COST);
6922
6923 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6924 // variable size, 0 or 4.
6925 ins_encode %{
6926 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6927 __ mr_if_needed($dst$$Register, $src$$Register);
6928 %}
6929 ins_pipe(pipe_class_default);
6930 %}
6931
6932 // Convert klass pointer into compressed form.
6933
6934 // Nodes for postalloc expand.
6935
6936 // Shift node for expand.
6937 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6938 // The match rule is needed to make it a 'MachTypeNode'!
6939 match(Set dst (EncodePKlass src));
6940 predicate(false);
6941
6942 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6943 size(4);
6944 ins_encode %{
6945 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6946 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6947 %}
6948 ins_pipe(pipe_class_default);
6949 %}
6950
6951 // Add node for expand.
6952 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6953 // The match rule is needed to make it a 'MachTypeNode'!
6954 match(Set dst (EncodePKlass (Binary base src)));
6955 predicate(false);
6956
6957 format %{ "SUB $dst, $base, $src \t// encode" %}
6958 size(4);
6959 ins_encode %{
6960 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6961 __ subf($dst$$Register, $base$$Register, $src$$Register);
6962 %}
6963 ins_pipe(pipe_class_default);
6964 %}
6965
6966 // base != 0
6967 // 32G aligned narrow oop base.
6968 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{
6969 match(Set dst (EncodePKlass src));
6970 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6971
6972 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6973 size(4);
6974 ins_encode %{
6975 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6976 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6977 %}
6978 ins_pipe(pipe_class_default);
6979 %}
6980
6981 // shift != 0, base != 0
6982 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
6983 match(Set dst (EncodePKlass (Binary base src)));
6984 predicate(false);
6985
6986 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6987 postalloc_expand %{
6988 encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
6989 n1->add_req(n_region, n_base, n_src);
6990 n1->_opnds[0] = op_dst;
6991 n1->_opnds[1] = op_base;
6992 n1->_opnds[2] = op_src;
6993 n1->_bottom_type = _bottom_type;
6994
6995 encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
6996 n2->add_req(n_region, n1);
6997 n2->_opnds[0] = op_dst;
6998 n2->_opnds[1] = op_dst;
6999 n2->_bottom_type = _bottom_type;
7000 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7001 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7002
7003 nodes->push(n1);
7004 nodes->push(n2);
7005 %}
7006 %}
7007
7008 // shift != 0, base != 0
7009 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7010 match(Set dst (EncodePKlass src));
7011 //predicate(Universe::narrow_klass_shift() != 0 &&
7012 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7013
7014 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7015 ins_cost(DEFAULT_COST*2); // Don't count constant.
7016 expand %{
7017 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7018 iRegLdst base;
7019 loadConL_Ex(base, baseImm);
7020 encodePKlass_not_null_Ex(dst, base, src);
7021 %}
7022 %}
7023
7024 // Decode nodes.
7025
7026 // Shift node for expand.
7027 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7028 // The match rule is needed to make it a 'MachTypeNode'!
7029 match(Set dst (DecodeNKlass src));
7030 predicate(false);
7031
7032 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
7033 size(4);
7034 ins_encode %{
7035 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7036 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7037 %}
7038 ins_pipe(pipe_class_default);
7039 %}
7040
7041 // Add node for expand.
7042
7043 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7044 // The match rule is needed to make it a 'MachTypeNode'!
7045 match(Set dst (DecodeNKlass (Binary base src)));
7046 predicate(false);
7047
7048 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7049 size(4);
7050 ins_encode %{
7051 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7052 __ add($dst$$Register, $base$$Register, $src$$Register);
7053 %}
7054 ins_pipe(pipe_class_default);
7055 %}
7056
7057 // src != 0, shift != 0, base != 0
7058 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7059 match(Set dst (DecodeNKlass (Binary base src)));
7060 //effect(kill src); // We need a register for the immediate result after shifting.
7061 predicate(false);
7062
7063 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7064 postalloc_expand %{
7065 decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
7066 n1->add_req(n_region, n_base, n_src);
7067 n1->_opnds[0] = op_dst;
7068 n1->_opnds[1] = op_base;
7069 n1->_opnds[2] = op_src;
7070 n1->_bottom_type = _bottom_type;
7071
7072 decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
7073 n2->add_req(n_region, n1);
7074 n2->_opnds[0] = op_dst;
7075 n2->_opnds[1] = op_dst;
7076 n2->_bottom_type = _bottom_type;
7077
7078 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7079 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7080
7081 nodes->push(n1);
7082 nodes->push(n2);
7083 %}
7084 %}
7085
7086 // src != 0, shift != 0, base != 0
7087 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7088 match(Set dst (DecodeNKlass src));
7089 // predicate(Universe::narrow_klass_shift() != 0 &&
7090 // Universe::narrow_klass_base() != 0);
7091
7092 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7093
7094 ins_cost(DEFAULT_COST*2); // Don't count constant.
7095 expand %{
7096 // We add first, then we shift. Like this, we can get along with one register less.
7097 // But we have to load the base pre-shifted.
7098 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7099 iRegLdst base;
7100 loadConL_Ex(base, baseImm);
7101 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7102 %}
7103 %}
7104
7105 //----------MemBar Instructions-----------------------------------------------
7106 // Memory barrier flavors
7107
7108 instruct membar_acquire() %{
7109 match(LoadFence);
7110 ins_cost(4*MEMORY_REF_COST);
7111
7112 format %{ "MEMBAR-acquire" %}
7113 size(4);
7114 ins_encode %{
7115 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7116 __ acquire();
7117 %}
7118 ins_pipe(pipe_class_default);
7119 %}
7120
7121 instruct unnecessary_membar_acquire() %{
7122 match(MemBarAcquire);
7123 ins_cost(0);
7124
7125 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7126 size(0);
7127 ins_encode( /*empty*/ );
7128 ins_pipe(pipe_class_default);
7129 %}
7130
7131 instruct membar_acquire_lock() %{
7132 match(MemBarAcquireLock);
7133 ins_cost(0);
7134
7135 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7136 size(0);
7137 ins_encode( /*empty*/ );
7138 ins_pipe(pipe_class_default);
7139 %}
7140
7141 instruct membar_release() %{
7142 match(MemBarRelease);
7143 match(StoreFence);
7144 ins_cost(4*MEMORY_REF_COST);
7145
7146 format %{ "MEMBAR-release" %}
7147 size(4);
7148 ins_encode %{
7149 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7150 __ release();
7151 %}
7152 ins_pipe(pipe_class_default);
7153 %}
7154
7155 instruct membar_storestore() %{
7156 match(MemBarStoreStore);
7157 ins_cost(4*MEMORY_REF_COST);
7158
7159 format %{ "MEMBAR-store-store" %}
7160 size(4);
7161 ins_encode %{
7162 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7163 __ membar(Assembler::StoreStore);
7164 %}
7165 ins_pipe(pipe_class_default);
7166 %}
7167
7168 instruct membar_release_lock() %{
7169 match(MemBarReleaseLock);
7170 ins_cost(0);
7171
7172 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7173 size(0);
7174 ins_encode( /*empty*/ );
7175 ins_pipe(pipe_class_default);
7176 %}
7177
7178 instruct membar_volatile() %{
7179 match(MemBarVolatile);
7180 ins_cost(4*MEMORY_REF_COST);
7181
7182 format %{ "MEMBAR-volatile" %}
7183 size(4);
7184 ins_encode %{
7185 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7186 __ fence();
7187 %}
7188 ins_pipe(pipe_class_default);
7189 %}
7190
7191 // This optimization is wrong on PPC. The following pattern is not supported:
7192 // MemBarVolatile
7193 // ^ ^
7194 // | |
7195 // CtrlProj MemProj
7196 // ^ ^
7197 // | |
7198 // | Load
7199 // |
7200 // MemBarVolatile
7201 //
7202 // The first MemBarVolatile could get optimized out! According to
7203 // Vladimir, this pattern can not occur on Oracle platforms.
7204 // However, it does occur on PPC64 (because of membars in
7205 // inline_unsafe_load_store).
7206 //
7207 // Add this node again if we found a good solution for inline_unsafe_load_store().
7208 // Don't forget to look at the implementation of post_store_load_barrier again,
7209 // we did other fixes in that method.
7210 //instruct unnecessary_membar_volatile() %{
7211 // match(MemBarVolatile);
7212 // predicate(Matcher::post_store_load_barrier(n));
7213 // ins_cost(0);
7214 //
7215 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7216 // size(0);
7217 // ins_encode( /*empty*/ );
7218 // ins_pipe(pipe_class_default);
7219 //%}
7220
7221 instruct membar_CPUOrder() %{
7222 match(MemBarCPUOrder);
7223 ins_cost(0);
7224
7225 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7226 size(0);
7227 ins_encode( /*empty*/ );
7228 ins_pipe(pipe_class_default);
7229 %}
7230
7231 //----------Conditional Move---------------------------------------------------
7232
7233 // Cmove using isel.
7234 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7235 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7236 predicate(VM_Version::has_isel());
7237 ins_cost(DEFAULT_COST);
7238
7239 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7240 size(4);
7241 ins_encode %{
7242 // This is a Power7 instruction for which no machine description
7243 // exists. Anyways, the scheduler should be off on Power7.
7244 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7245 int cc = $cmp$$cmpcode;
7246 __ isel($dst$$Register, $crx$$CondRegister,
7247 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7248 %}
7249 ins_pipe(pipe_class_default);
7250 %}
7251
7252 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7253 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7254 predicate(!VM_Version::has_isel());
7255 ins_cost(DEFAULT_COST+BRANCH_COST);
7256
7257 ins_variable_size_depending_on_alignment(true);
7258
7259 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7260 // Worst case is branch + move + stop, no stop without scheduler
7261 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7262 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7263 ins_pipe(pipe_class_default);
7264 %}
7265
7266 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{
7267 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7268 ins_cost(DEFAULT_COST+BRANCH_COST);
7269
7270 ins_variable_size_depending_on_alignment(true);
7271
7272 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7273 // Worst case is branch + move + stop, no stop without scheduler
7274 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7275 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7276 ins_pipe(pipe_class_default);
7277 %}
7278
7279 // Cmove using isel.
7280 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7281 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7282 predicate(VM_Version::has_isel());
7283 ins_cost(DEFAULT_COST);
7284
7285 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7286 size(4);
7287 ins_encode %{
7288 // This is a Power7 instruction for which no machine description
7289 // exists. Anyways, the scheduler should be off on Power7.
7290 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7291 int cc = $cmp$$cmpcode;
7292 __ isel($dst$$Register, $crx$$CondRegister,
7293 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7294 %}
7295 ins_pipe(pipe_class_default);
7296 %}
7297
7298 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7299 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7300 predicate(!VM_Version::has_isel());
7301 ins_cost(DEFAULT_COST+BRANCH_COST);
7302
7303 ins_variable_size_depending_on_alignment(true);
7304
7305 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7306 // Worst case is branch + move + stop, no stop without scheduler.
7307 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7308 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7309 ins_pipe(pipe_class_default);
7310 %}
7311
7312 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{
7313 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7314 ins_cost(DEFAULT_COST+BRANCH_COST);
7315
7316 ins_variable_size_depending_on_alignment(true);
7317
7318 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7319 // Worst case is branch + move + stop, no stop without scheduler.
7320 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7321 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7322 ins_pipe(pipe_class_default);
7323 %}
7324
7325 // Cmove using isel.
7326 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7327 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7328 predicate(VM_Version::has_isel());
7329 ins_cost(DEFAULT_COST);
7330
7331 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7332 size(4);
7333 ins_encode %{
7334 // This is a Power7 instruction for which no machine description
7335 // exists. Anyways, the scheduler should be off on Power7.
7336 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7337 int cc = $cmp$$cmpcode;
7338 __ isel($dst$$Register, $crx$$CondRegister,
7339 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7340 %}
7341 ins_pipe(pipe_class_default);
7342 %}
7343
7344 // Conditional move for RegN. Only cmov(reg, reg).
7345 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7346 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7347 predicate(!VM_Version::has_isel());
7348 ins_cost(DEFAULT_COST+BRANCH_COST);
7349
7350 ins_variable_size_depending_on_alignment(true);
7351
7352 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7353 // Worst case is branch + move + stop, no stop without scheduler.
7354 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7355 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7356 ins_pipe(pipe_class_default);
7357 %}
7358
7359 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{
7360 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7361 ins_cost(DEFAULT_COST+BRANCH_COST);
7362
7363 ins_variable_size_depending_on_alignment(true);
7364
7365 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7366 // Worst case is branch + move + stop, no stop without scheduler.
7367 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7368 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7369 ins_pipe(pipe_class_default);
7370 %}
7371
7372 // Cmove using isel.
7373 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
7374 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7375 predicate(VM_Version::has_isel());
7376 ins_cost(DEFAULT_COST);
7377
7378 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7379 size(4);
7380 ins_encode %{
7381 // This is a Power7 instruction for which no machine description
7382 // exists. Anyways, the scheduler should be off on Power7.
7383 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7384 int cc = $cmp$$cmpcode;
7385 __ isel($dst$$Register, $crx$$CondRegister,
7386 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7387 %}
7388 ins_pipe(pipe_class_default);
7389 %}
7390
7391 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{
7392 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7393 predicate(!VM_Version::has_isel());
7394 ins_cost(DEFAULT_COST+BRANCH_COST);
7395
7396 ins_variable_size_depending_on_alignment(true);
7397
7398 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7399 // Worst case is branch + move + stop, no stop without scheduler.
7400 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7401 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7402 ins_pipe(pipe_class_default);
7403 %}
7404
7405 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{
7406 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7407 ins_cost(DEFAULT_COST+BRANCH_COST);
7408
7409 ins_variable_size_depending_on_alignment(true);
7410
7411 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7412 // Worst case is branch + move + stop, no stop without scheduler.
7413 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7414 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7415 ins_pipe(pipe_class_default);
7416 %}
7417
7418 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{
7419 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7420 ins_cost(DEFAULT_COST+BRANCH_COST);
7421
7422 ins_variable_size_depending_on_alignment(true);
7423
7424 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7425 // Worst case is branch + move + stop, no stop without scheduler.
7426 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7427 ins_encode %{
7428 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7429 Label done;
7430 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7431 // Branch if not (cmp crx).
7432 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7433 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7434 // TODO PPC port __ endgroup_if_needed(_size == 12);
7435 __ bind(done);
7436 %}
7437 ins_pipe(pipe_class_default);
7438 %}
7439
7440 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{
7441 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7442 ins_cost(DEFAULT_COST+BRANCH_COST);
7443
7444 ins_variable_size_depending_on_alignment(true);
7445
7446 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7447 // Worst case is branch + move + stop, no stop without scheduler.
7448 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7449 ins_encode %{
7450 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7451 Label done;
7452 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7453 // Branch if not (cmp crx).
7454 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7455 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7456 // TODO PPC port __ endgroup_if_needed(_size == 12);
7457 __ bind(done);
7458 %}
7459 ins_pipe(pipe_class_default);
7460 %}
7461
7462 //----------Conditional_store--------------------------------------------------
7463 // Conditional-store of the updated heap-top.
7464 // Used during allocation of the shared heap.
7465 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7466
7467 // As compareAndSwapL, but return flag register instead of boolean value in
7468 // int register.
7469 // Used by sun/misc/AtomicLongCSImpl.java.
7470 // Mem_ptr must be a memory operand, else this node does not get
7471 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7472 // can be rematerialized which leads to errors.
7473 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{
7474 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7475 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7476 ins_encode %{
7477 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7478 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7479 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7480 noreg, NULL, true);
7481 %}
7482 ins_pipe(pipe_class_default);
7483 %}
7484
7485 // As compareAndSwapP, but return flag register instead of boolean value in
7486 // int register.
7487 // This instruction is matched if UseTLAB is off.
7488 // Mem_ptr must be a memory operand, else this node does not get
7489 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7490 // can be rematerialized which leads to errors.
7491 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7492 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal)));
7493 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7494 ins_encode %{
7495 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7496 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7497 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7498 noreg, NULL, true);
7499 %}
7500 ins_pipe(pipe_class_default);
7501 %}
7502
7503 // Implement LoadPLocked. Must be ordered against changes of the memory location
7504 // by storePConditional.
7505 // Don't know whether this is ever used.
7506 instruct loadPLocked(iRegPdst dst, memory mem) %{
7507 match(Set dst (LoadPLocked mem));
7508 ins_cost(MEMORY_REF_COST);
7509
7510 format %{ "LD $dst, $mem \t// loadPLocked\n\t"
7511 "TWI $dst\n\t"
7512 "ISYNC" %}
7513 size(12);
7514 ins_encode( enc_ld_ac(dst, mem) );
7515 ins_pipe(pipe_class_memory);
7516 %}
7517
7518 //----------Compare-And-Swap---------------------------------------------------
7519
7520 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7521 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7522 // matched.
7523
7524 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{
7525 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7526 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7527 // Variable size: instruction count smaller if regs are disjoint.
7528 ins_encode %{
7529 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7530 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7531 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7532 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7533 $res$$Register, true);
7534 %}
7535 ins_pipe(pipe_class_default);
7536 %}
7537
7538 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{
7539 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7540 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7541 // Variable size: instruction count smaller if regs are disjoint.
7542 ins_encode %{
7543 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7544 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7545 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7546 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7547 $res$$Register, true);
7548 %}
7549 ins_pipe(pipe_class_default);
7550 %}
7551
7552 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{
7553 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7554 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7555 // Variable size: instruction count smaller if regs are disjoint.
7556 ins_encode %{
7557 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7558 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7559 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7560 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7561 $res$$Register, NULL, true);
7562 %}
7563 ins_pipe(pipe_class_default);
7564 %}
7565
7566 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{
7567 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7568 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7569 // Variable size: instruction count smaller if regs are disjoint.
7570 ins_encode %{
7571 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7572 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7573 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7574 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7575 $res$$Register, NULL, true);
7576 %}
7577 ins_pipe(pipe_class_default);
7578 %}
7579
7580 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7581 match(Set res (GetAndAddI mem_ptr src));
7582 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7583 // Variable size: instruction count smaller if regs are disjoint.
7584 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7585 ins_pipe(pipe_class_default);
7586 %}
7587
7588 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7589 match(Set res (GetAndAddL mem_ptr src));
7590 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7591 // Variable size: instruction count smaller if regs are disjoint.
7592 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7593 ins_pipe(pipe_class_default);
7594 %}
7595
7596 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7597 match(Set res (GetAndSetI mem_ptr src));
7598 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7599 // Variable size: instruction count smaller if regs are disjoint.
7600 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7601 ins_pipe(pipe_class_default);
7602 %}
7603
7604 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7605 match(Set res (GetAndSetL mem_ptr src));
7606 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7607 // Variable size: instruction count smaller if regs are disjoint.
7608 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7609 ins_pipe(pipe_class_default);
7610 %}
7611
7612 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{
7613 match(Set res (GetAndSetP mem_ptr src));
7614 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7615 // Variable size: instruction count smaller if regs are disjoint.
7616 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7617 ins_pipe(pipe_class_default);
7618 %}
7619
7620 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{
7621 match(Set res (GetAndSetN mem_ptr src));
7622 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7623 // Variable size: instruction count smaller if regs are disjoint.
7624 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7625 ins_pipe(pipe_class_default);
7626 %}
7627
7628 //----------Arithmetic Instructions--------------------------------------------
7629 // Addition Instructions
7630
7631 // Register Addition
7632 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7633 match(Set dst (AddI src1 src2));
7634 format %{ "ADD $dst, $src1, $src2" %}
7635 size(4);
7636 ins_encode %{
7637 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7638 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7639 %}
7640 ins_pipe(pipe_class_default);
7641 %}
7642
7643 // Expand does not work with above instruct. (??)
7644 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7645 // no match-rule
7646 effect(DEF dst, USE src1, USE src2);
7647 format %{ "ADD $dst, $src1, $src2" %}
7648 size(4);
7649 ins_encode %{
7650 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7651 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7652 %}
7653 ins_pipe(pipe_class_default);
7654 %}
7655
7656 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7657 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7658 ins_cost(DEFAULT_COST*3);
7659
7660 expand %{
7661 // FIXME: we should do this in the ideal world.
7662 iRegIdst tmp1;
7663 iRegIdst tmp2;
7664 addI_reg_reg(tmp1, src1, src2);
7665 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7666 addI_reg_reg(dst, tmp1, tmp2);
7667 %}
7668 %}
7669
7670 // Immediate Addition
7671 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7672 match(Set dst (AddI src1 src2));
7673 format %{ "ADDI $dst, $src1, $src2" %}
7674 size(4);
7675 ins_encode %{
7676 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7677 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7678 %}
7679 ins_pipe(pipe_class_default);
7680 %}
7681
7682 // Immediate Addition with 16-bit shifted operand
7683 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7684 match(Set dst (AddI src1 src2));
7685 format %{ "ADDIS $dst, $src1, $src2" %}
7686 size(4);
7687 ins_encode %{
7688 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7689 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7690 %}
7691 ins_pipe(pipe_class_default);
7692 %}
7693
7694 // Long Addition
7695 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7696 match(Set dst (AddL src1 src2));
7697 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7698 size(4);
7699 ins_encode %{
7700 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7701 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7702 %}
7703 ins_pipe(pipe_class_default);
7704 %}
7705
7706 // Expand does not work with above instruct. (??)
7707 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7708 // no match-rule
7709 effect(DEF dst, USE src1, USE src2);
7710 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7711 size(4);
7712 ins_encode %{
7713 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7714 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7715 %}
7716 ins_pipe(pipe_class_default);
7717 %}
7718
7719 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7720 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7721 ins_cost(DEFAULT_COST*3);
7722
7723 expand %{
7724 // FIXME: we should do this in the ideal world.
7725 iRegLdst tmp1;
7726 iRegLdst tmp2;
7727 addL_reg_reg(tmp1, src1, src2);
7728 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7729 addL_reg_reg(dst, tmp1, tmp2);
7730 %}
7731 %}
7732
7733 // AddL + ConvL2I.
7734 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7735 match(Set dst (ConvL2I (AddL src1 src2)));
7736
7737 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7738 size(4);
7739 ins_encode %{
7740 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7741 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7742 %}
7743 ins_pipe(pipe_class_default);
7744 %}
7745
7746 // No constant pool entries required.
7747 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7748 match(Set dst (AddL src1 src2));
7749
7750 format %{ "ADDI $dst, $src1, $src2" %}
7751 size(4);
7752 ins_encode %{
7753 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7754 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7755 %}
7756 ins_pipe(pipe_class_default);
7757 %}
7758
7759 // Long Immediate Addition with 16-bit shifted operand.
7760 // No constant pool entries required.
7761 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7762 match(Set dst (AddL src1 src2));
7763
7764 format %{ "ADDIS $dst, $src1, $src2" %}
7765 size(4);
7766 ins_encode %{
7767 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7768 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7769 %}
7770 ins_pipe(pipe_class_default);
7771 %}
7772
7773 // Pointer Register Addition
7774 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7775 match(Set dst (AddP src1 src2));
7776 format %{ "ADD $dst, $src1, $src2" %}
7777 size(4);
7778 ins_encode %{
7779 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7780 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7781 %}
7782 ins_pipe(pipe_class_default);
7783 %}
7784
7785 // Pointer Immediate Addition
7786 // No constant pool entries required.
7787 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7788 match(Set dst (AddP src1 src2));
7789
7790 format %{ "ADDI $dst, $src1, $src2" %}
7791 size(4);
7792 ins_encode %{
7793 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7794 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7795 %}
7796 ins_pipe(pipe_class_default);
7797 %}
7798
7799 // Pointer Immediate Addition with 16-bit shifted operand.
7800 // No constant pool entries required.
7801 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7802 match(Set dst (AddP src1 src2));
7803
7804 format %{ "ADDIS $dst, $src1, $src2" %}
7805 size(4);
7806 ins_encode %{
7807 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7808 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7809 %}
7810 ins_pipe(pipe_class_default);
7811 %}
7812
7813 //---------------------
7814 // Subtraction Instructions
7815
7816 // Register Subtraction
7817 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7818 match(Set dst (SubI src1 src2));
7819 format %{ "SUBF $dst, $src2, $src1" %}
7820 size(4);
7821 ins_encode %{
7822 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7823 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7824 %}
7825 ins_pipe(pipe_class_default);
7826 %}
7827
7828 // Immediate Subtraction
7829 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal),
7830 // so this rule seems to be unused.
7831 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7832 match(Set dst (SubI src1 src2));
7833 format %{ "SUBI $dst, $src1, $src2" %}
7834 size(4);
7835 ins_encode %{
7836 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7837 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7838 %}
7839 ins_pipe(pipe_class_default);
7840 %}
7841
7842 // SubI from constant (using subfic).
7843 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7844 match(Set dst (SubI src1 src2));
7845 format %{ "SUBI $dst, $src1, $src2" %}
7846
7847 size(4);
7848 ins_encode %{
7849 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7850 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7851 %}
7852 ins_pipe(pipe_class_default);
7853 %}
7854
7855 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7856 // positive integers and 0xF...F for negative ones.
7857 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7858 // no match-rule, false predicate
7859 effect(DEF dst, USE src);
7860 predicate(false);
7861
7862 format %{ "SRAWI $dst, $src, #31" %}
7863 size(4);
7864 ins_encode %{
7865 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7866 __ srawi($dst$$Register, $src$$Register, 0x1f);
7867 %}
7868 ins_pipe(pipe_class_default);
7869 %}
7870
7871 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7872 match(Set dst (AbsI src));
7873 ins_cost(DEFAULT_COST*3);
7874
7875 expand %{
7876 iRegIdst tmp1;
7877 iRegIdst tmp2;
7878 signmask32I_regI(tmp1, src);
7879 xorI_reg_reg(tmp2, tmp1, src);
7880 subI_reg_reg(dst, tmp2, tmp1);
7881 %}
7882 %}
7883
7884 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7885 match(Set dst (SubI zero src2));
7886 format %{ "NEG $dst, $src2" %}
7887 size(4);
7888 ins_encode %{
7889 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7890 __ neg($dst$$Register, $src2$$Register);
7891 %}
7892 ins_pipe(pipe_class_default);
7893 %}
7894
7895 // Long subtraction
7896 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7897 match(Set dst (SubL src1 src2));
7898 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7899 size(4);
7900 ins_encode %{
7901 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7902 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7903 %}
7904 ins_pipe(pipe_class_default);
7905 %}
7906
7907 // SubL + convL2I.
7908 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7909 match(Set dst (ConvL2I (SubL src1 src2)));
7910
7911 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7912 size(4);
7913 ins_encode %{
7914 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7915 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7916 %}
7917 ins_pipe(pipe_class_default);
7918 %}
7919
7920 // Immediate Subtraction
7921 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7922 // so this rule seems to be unused.
7923 // No constant pool entries required.
7924 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7925 match(Set dst (SubL src1 src2));
7926
7927 format %{ "SUBI $dst, $src1, $src2 \t// long" %}
7928 size(4);
7929 ins_encode %{
7930 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7931 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7932 %}
7933 ins_pipe(pipe_class_default);
7934 %}
7935
7936 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7937 // positive longs and 0xF...F for negative ones.
7938 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7939 // no match-rule, false predicate
7940 effect(DEF dst, USE src);
7941 predicate(false);
7942
7943 format %{ "SRADI $dst, $src, #63" %}
7944 size(4);
7945 ins_encode %{
7946 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7947 __ sradi($dst$$Register, $src$$Register, 0x3f);
7948 %}
7949 ins_pipe(pipe_class_default);
7950 %}
7951
7952 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7953 // positive longs and 0xF...F for negative ones.
7954 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
7955 // no match-rule, false predicate
7956 effect(DEF dst, USE src);
7957 predicate(false);
7958
7959 format %{ "SRADI $dst, $src, #63" %}
7960 size(4);
7961 ins_encode %{
7962 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7963 __ sradi($dst$$Register, $src$$Register, 0x3f);
7964 %}
7965 ins_pipe(pipe_class_default);
7966 %}
7967
7968 // Long negation
7969 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7970 match(Set dst (SubL zero src2));
7971 format %{ "NEG $dst, $src2 \t// long" %}
7972 size(4);
7973 ins_encode %{
7974 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7975 __ neg($dst$$Register, $src2$$Register);
7976 %}
7977 ins_pipe(pipe_class_default);
7978 %}
7979
7980 // NegL + ConvL2I.
7981 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
7982 match(Set dst (ConvL2I (SubL zero src2)));
7983
7984 format %{ "NEG $dst, $src2 \t// long + l2i" %}
7985 size(4);
7986 ins_encode %{
7987 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7988 __ neg($dst$$Register, $src2$$Register);
7989 %}
7990 ins_pipe(pipe_class_default);
7991 %}
7992
7993 // Multiplication Instructions
7994 // Integer Multiplication
7995
7996 // Register Multiplication
7997 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7998 match(Set dst (MulI src1 src2));
7999 ins_cost(DEFAULT_COST);
8000
8001 format %{ "MULLW $dst, $src1, $src2" %}
8002 size(4);
8003 ins_encode %{
8004 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8005 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8006 %}
8007 ins_pipe(pipe_class_default);
8008 %}
8009
8010 // Immediate Multiplication
8011 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8012 match(Set dst (MulI src1 src2));
8013 ins_cost(DEFAULT_COST);
8014
8015 format %{ "MULLI $dst, $src1, $src2" %}
8016 size(4);
8017 ins_encode %{
8018 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8019 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8020 %}
8021 ins_pipe(pipe_class_default);
8022 %}
8023
8024 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8025 match(Set dst (MulL src1 src2));
8026 ins_cost(DEFAULT_COST);
8027
8028 format %{ "MULLD $dst $src1, $src2 \t// long" %}
8029 size(4);
8030 ins_encode %{
8031 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8032 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8033 %}
8034 ins_pipe(pipe_class_default);
8035 %}
8036
8037 // Multiply high for optimized long division by constant.
8038 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8039 match(Set dst (MulHiL src1 src2));
8040 ins_cost(DEFAULT_COST);
8041
8042 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8043 size(4);
8044 ins_encode %{
8045 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8046 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8047 %}
8048 ins_pipe(pipe_class_default);
8049 %}
8050
8051 // Immediate Multiplication
8052 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8053 match(Set dst (MulL src1 src2));
8054 ins_cost(DEFAULT_COST);
8055
8056 format %{ "MULLI $dst, $src1, $src2" %}
8057 size(4);
8058 ins_encode %{
8059 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8060 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8061 %}
8062 ins_pipe(pipe_class_default);
8063 %}
8064
8065 // Integer Division with Immediate -1: Negate.
8066 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8067 match(Set dst (DivI src1 src2));
8068 ins_cost(DEFAULT_COST);
8069
8070 format %{ "NEG $dst, $src1 \t// /-1" %}
8071 size(4);
8072 ins_encode %{
8073 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8074 __ neg($dst$$Register, $src1$$Register);
8075 %}
8076 ins_pipe(pipe_class_default);
8077 %}
8078
8079 // Integer Division with constant, but not -1.
8080 // We should be able to improve this by checking the type of src2.
8081 // It might well be that src2 is known to be positive.
8082 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8083 match(Set dst (DivI src1 src2));
8084 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8085 ins_cost(2*DEFAULT_COST);
8086
8087 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8088 size(4);
8089 ins_encode %{
8090 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8091 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8092 %}
8093 ins_pipe(pipe_class_default);
8094 %}
8095
8096 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{
8097 effect(USE_DEF dst, USE src1, USE crx);
8098 predicate(false);
8099
8100 ins_variable_size_depending_on_alignment(true);
8101
8102 format %{ "CMOVE $dst, neg($src1), $crx" %}
8103 // Worst case is branch + move + stop, no stop without scheduler.
8104 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8105 ins_encode %{
8106 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8107 Label done;
8108 __ bne($crx$$CondRegister, done);
8109 __ neg($dst$$Register, $src1$$Register);
8110 // TODO PPC port __ endgroup_if_needed(_size == 12);
8111 __ bind(done);
8112 %}
8113 ins_pipe(pipe_class_default);
8114 %}
8115
8116 // Integer Division with Registers not containing constants.
8117 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8118 match(Set dst (DivI src1 src2));
8119 ins_cost(10*DEFAULT_COST);
8120
8121 expand %{
8122 immI16 imm %{ (int)-1 %}
8123 flagsReg tmp1;
8124 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8125 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8126 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8127 %}
8128 %}
8129
8130 // Long Division with Immediate -1: Negate.
8131 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8132 match(Set dst (DivL src1 src2));
8133 ins_cost(DEFAULT_COST);
8134
8135 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8136 size(4);
8137 ins_encode %{
8138 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8139 __ neg($dst$$Register, $src1$$Register);
8140 %}
8141 ins_pipe(pipe_class_default);
8142 %}
8143
8144 // Long Division with constant, but not -1.
8145 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8146 match(Set dst (DivL src1 src2));
8147 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8148 ins_cost(2*DEFAULT_COST);
8149
8150 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8151 size(4);
8152 ins_encode %{
8153 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8154 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8155 %}
8156 ins_pipe(pipe_class_default);
8157 %}
8158
8159 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{
8160 effect(USE_DEF dst, USE src1, USE crx);
8161 predicate(false);
8162
8163 ins_variable_size_depending_on_alignment(true);
8164
8165 format %{ "CMOVE $dst, neg($src1), $crx" %}
8166 // Worst case is branch + move + stop, no stop without scheduler.
8167 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8168 ins_encode %{
8169 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8170 Label done;
8171 __ bne($crx$$CondRegister, done);
8172 __ neg($dst$$Register, $src1$$Register);
8173 // TODO PPC port __ endgroup_if_needed(_size == 12);
8174 __ bind(done);
8175 %}
8176 ins_pipe(pipe_class_default);
8177 %}
8178
8179 // Long Division with Registers not containing constants.
8180 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8181 match(Set dst (DivL src1 src2));
8182 ins_cost(10*DEFAULT_COST);
8183
8184 expand %{
8185 immL16 imm %{ (int)-1 %}
8186 flagsReg tmp1;
8187 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8188 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8189 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8190 %}
8191 %}
8192
8193 // Integer Remainder with registers.
8194 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8195 match(Set dst (ModI src1 src2));
8196 ins_cost(10*DEFAULT_COST);
8197
8198 expand %{
8199 immI16 imm %{ (int)-1 %}
8200 flagsReg tmp1;
8201 iRegIdst tmp2;
8202 iRegIdst tmp3;
8203 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8204 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8205 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8206 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8207 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8208 %}
8209 %}
8210
8211 // Long Remainder with registers
8212 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8213 match(Set dst (ModL src1 src2));
8214 ins_cost(10*DEFAULT_COST);
8215
8216 expand %{
8217 immL16 imm %{ (int)-1 %}
8218 flagsReg tmp1;
8219 iRegLdst tmp2;
8220 iRegLdst tmp3;
8221 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8222 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8223 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8224 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8225 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8226 %}
8227 %}
8228
8229 // Integer Shift Instructions
8230
8231 // Register Shift Left
8232
8233 // Clear all but the lowest #mask bits.
8234 // Used to normalize shift amounts in registers.
8235 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8236 // no match-rule, false predicate
8237 effect(DEF dst, USE src, USE mask);
8238 predicate(false);
8239
8240 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8241 size(4);
8242 ins_encode %{
8243 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8244 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8245 %}
8246 ins_pipe(pipe_class_default);
8247 %}
8248
8249 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8250 // no match-rule, false predicate
8251 effect(DEF dst, USE src1, USE src2);
8252 predicate(false);
8253
8254 format %{ "SLW $dst, $src1, $src2" %}
8255 size(4);
8256 ins_encode %{
8257 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8258 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8259 %}
8260 ins_pipe(pipe_class_default);
8261 %}
8262
8263 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8264 match(Set dst (LShiftI src1 src2));
8265 ins_cost(DEFAULT_COST*2);
8266 expand %{
8267 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8268 iRegIdst tmpI;
8269 maskI_reg_imm(tmpI, src2, mask);
8270 lShiftI_reg_reg(dst, src1, tmpI);
8271 %}
8272 %}
8273
8274 // Register Shift Left Immediate
8275 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8276 match(Set dst (LShiftI src1 src2));
8277
8278 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8279 size(4);
8280 ins_encode %{
8281 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8282 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8283 %}
8284 ins_pipe(pipe_class_default);
8285 %}
8286
8287 // AndI with negpow2-constant + LShiftI
8288 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8289 match(Set dst (LShiftI (AndI src1 src2) src3));
8290 predicate(UseRotateAndMaskInstructionsPPC64);
8291
8292 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8293 size(4);
8294 ins_encode %{
8295 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8296 long src2 = $src2$$constant;
8297 long src3 = $src3$$constant;
8298 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8299 if (maskbits >= 32) {
8300 __ li($dst$$Register, 0); // addi
8301 } else {
8302 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8303 }
8304 %}
8305 ins_pipe(pipe_class_default);
8306 %}
8307
8308 // RShiftI + AndI with negpow2-constant + LShiftI
8309 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8310 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8311 predicate(UseRotateAndMaskInstructionsPPC64);
8312
8313 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8314 size(4);
8315 ins_encode %{
8316 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8317 long src2 = $src2$$constant;
8318 long src3 = $src3$$constant;
8319 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8320 if (maskbits >= 32) {
8321 __ li($dst$$Register, 0); // addi
8322 } else {
8323 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8324 }
8325 %}
8326 ins_pipe(pipe_class_default);
8327 %}
8328
8329 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8330 // no match-rule, false predicate
8331 effect(DEF dst, USE src1, USE src2);
8332 predicate(false);
8333
8334 format %{ "SLD $dst, $src1, $src2" %}
8335 size(4);
8336 ins_encode %{
8337 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8338 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8339 %}
8340 ins_pipe(pipe_class_default);
8341 %}
8342
8343 // Register Shift Left
8344 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8345 match(Set dst (LShiftL src1 src2));
8346 ins_cost(DEFAULT_COST*2);
8347 expand %{
8348 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8349 iRegIdst tmpI;
8350 maskI_reg_imm(tmpI, src2, mask);
8351 lShiftL_regL_regI(dst, src1, tmpI);
8352 %}
8353 %}
8354
8355 // Register Shift Left Immediate
8356 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8357 match(Set dst (LShiftL src1 src2));
8358 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8359 size(4);
8360 ins_encode %{
8361 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8362 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8363 %}
8364 ins_pipe(pipe_class_default);
8365 %}
8366
8367 // If we shift more than 32 bits, we need not convert I2L.
8368 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8369 match(Set dst (LShiftL (ConvI2L src1) src2));
8370 ins_cost(DEFAULT_COST);
8371
8372 size(4);
8373 format %{ "SLDI $dst, i2l($src1), $src2" %}
8374 ins_encode %{
8375 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8376 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8377 %}
8378 ins_pipe(pipe_class_default);
8379 %}
8380
8381 // Shift a postivie int to the left.
8382 // Clrlsldi clears the upper 32 bits and shifts.
8383 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8384 match(Set dst (LShiftL (ConvI2L src1) src2));
8385 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8386
8387 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8388 size(4);
8389 ins_encode %{
8390 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8391 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8392 %}
8393 ins_pipe(pipe_class_default);
8394 %}
8395
8396 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8397 // no match-rule, false predicate
8398 effect(DEF dst, USE src1, USE src2);
8399 predicate(false);
8400
8401 format %{ "SRAW $dst, $src1, $src2" %}
8402 size(4);
8403 ins_encode %{
8404 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8405 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8406 %}
8407 ins_pipe(pipe_class_default);
8408 %}
8409
8410 // Register Arithmetic Shift Right
8411 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8412 match(Set dst (RShiftI src1 src2));
8413 ins_cost(DEFAULT_COST*2);
8414 expand %{
8415 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8416 iRegIdst tmpI;
8417 maskI_reg_imm(tmpI, src2, mask);
8418 arShiftI_reg_reg(dst, src1, tmpI);
8419 %}
8420 %}
8421
8422 // Register Arithmetic Shift Right Immediate
8423 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8424 match(Set dst (RShiftI src1 src2));
8425
8426 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8427 size(4);
8428 ins_encode %{
8429 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8430 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8431 %}
8432 ins_pipe(pipe_class_default);
8433 %}
8434
8435 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8436 // no match-rule, false predicate
8437 effect(DEF dst, USE src1, USE src2);
8438 predicate(false);
8439
8440 format %{ "SRAD $dst, $src1, $src2" %}
8441 size(4);
8442 ins_encode %{
8443 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8444 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8445 %}
8446 ins_pipe(pipe_class_default);
8447 %}
8448
8449 // Register Shift Right Arithmetic Long
8450 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8451 match(Set dst (RShiftL src1 src2));
8452 ins_cost(DEFAULT_COST*2);
8453
8454 expand %{
8455 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8456 iRegIdst tmpI;
8457 maskI_reg_imm(tmpI, src2, mask);
8458 arShiftL_regL_regI(dst, src1, tmpI);
8459 %}
8460 %}
8461
8462 // Register Shift Right Immediate
8463 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8464 match(Set dst (RShiftL src1 src2));
8465
8466 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8467 size(4);
8468 ins_encode %{
8469 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8470 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8471 %}
8472 ins_pipe(pipe_class_default);
8473 %}
8474
8475 // RShiftL + ConvL2I
8476 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8477 match(Set dst (ConvL2I (RShiftL src1 src2)));
8478
8479 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8480 size(4);
8481 ins_encode %{
8482 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8483 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8484 %}
8485 ins_pipe(pipe_class_default);
8486 %}
8487
8488 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8489 // no match-rule, false predicate
8490 effect(DEF dst, USE src1, USE src2);
8491 predicate(false);
8492
8493 format %{ "SRW $dst, $src1, $src2" %}
8494 size(4);
8495 ins_encode %{
8496 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8497 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8498 %}
8499 ins_pipe(pipe_class_default);
8500 %}
8501
8502 // Register Shift Right
8503 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8504 match(Set dst (URShiftI src1 src2));
8505 ins_cost(DEFAULT_COST*2);
8506
8507 expand %{
8508 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8509 iRegIdst tmpI;
8510 maskI_reg_imm(tmpI, src2, mask);
8511 urShiftI_reg_reg(dst, src1, tmpI);
8512 %}
8513 %}
8514
8515 // Register Shift Right Immediate
8516 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8517 match(Set dst (URShiftI src1 src2));
8518
8519 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8520 size(4);
8521 ins_encode %{
8522 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8523 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8524 %}
8525 ins_pipe(pipe_class_default);
8526 %}
8527
8528 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8529 // no match-rule, false predicate
8530 effect(DEF dst, USE src1, USE src2);
8531 predicate(false);
8532
8533 format %{ "SRD $dst, $src1, $src2" %}
8534 size(4);
8535 ins_encode %{
8536 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8537 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8538 %}
8539 ins_pipe(pipe_class_default);
8540 %}
8541
8542 // Register Shift Right
8543 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8544 match(Set dst (URShiftL src1 src2));
8545 ins_cost(DEFAULT_COST*2);
8546
8547 expand %{
8548 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8549 iRegIdst tmpI;
8550 maskI_reg_imm(tmpI, src2, mask);
8551 urShiftL_regL_regI(dst, src1, tmpI);
8552 %}
8553 %}
8554
8555 // Register Shift Right Immediate
8556 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8557 match(Set dst (URShiftL src1 src2));
8558
8559 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8560 size(4);
8561 ins_encode %{
8562 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8563 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8564 %}
8565 ins_pipe(pipe_class_default);
8566 %}
8567
8568 // URShiftL + ConvL2I.
8569 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8570 match(Set dst (ConvL2I (URShiftL src1 src2)));
8571
8572 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8573 size(4);
8574 ins_encode %{
8575 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8576 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8577 %}
8578 ins_pipe(pipe_class_default);
8579 %}
8580
8581 // Register Shift Right Immediate with a CastP2X
8582 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8583 match(Set dst (URShiftL (CastP2X src1) src2));
8584
8585 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8586 size(4);
8587 ins_encode %{
8588 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8589 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8590 %}
8591 ins_pipe(pipe_class_default);
8592 %}
8593
8594 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8595 match(Set dst (ConvL2I (ConvI2L src)));
8596
8597 format %{ "EXTSW $dst, $src \t// int->int" %}
8598 size(4);
8599 ins_encode %{
8600 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8601 __ extsw($dst$$Register, $src$$Register);
8602 %}
8603 ins_pipe(pipe_class_default);
8604 %}
8605
8606 //----------Rotate Instructions------------------------------------------------
8607
8608 // Rotate Left by 8-bit immediate
8609 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8610 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8611 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8612
8613 format %{ "ROTLWI $dst, $src, $lshift" %}
8614 size(4);
8615 ins_encode %{
8616 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8617 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8618 %}
8619 ins_pipe(pipe_class_default);
8620 %}
8621
8622 // Rotate Right by 8-bit immediate
8623 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8624 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8625 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8626
8627 format %{ "ROTRWI $dst, $rshift" %}
8628 size(4);
8629 ins_encode %{
8630 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8631 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8632 %}
8633 ins_pipe(pipe_class_default);
8634 %}
8635
8636 //----------Floating Point Arithmetic Instructions-----------------------------
8637
8638 // Add float single precision
8639 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8640 match(Set dst (AddF src1 src2));
8641
8642 format %{ "FADDS $dst, $src1, $src2" %}
8643 size(4);
8644 ins_encode %{
8645 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8646 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8647 %}
8648 ins_pipe(pipe_class_default);
8649 %}
8650
8651 // Add float double precision
8652 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8653 match(Set dst (AddD src1 src2));
8654
8655 format %{ "FADD $dst, $src1, $src2" %}
8656 size(4);
8657 ins_encode %{
8658 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8659 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8660 %}
8661 ins_pipe(pipe_class_default);
8662 %}
8663
8664 // Sub float single precision
8665 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8666 match(Set dst (SubF src1 src2));
8667
8668 format %{ "FSUBS $dst, $src1, $src2" %}
8669 size(4);
8670 ins_encode %{
8671 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8672 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8673 %}
8674 ins_pipe(pipe_class_default);
8675 %}
8676
8677 // Sub float double precision
8678 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8679 match(Set dst (SubD src1 src2));
8680 format %{ "FSUB $dst, $src1, $src2" %}
8681 size(4);
8682 ins_encode %{
8683 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8684 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8685 %}
8686 ins_pipe(pipe_class_default);
8687 %}
8688
8689 // Mul float single precision
8690 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8691 match(Set dst (MulF src1 src2));
8692 format %{ "FMULS $dst, $src1, $src2" %}
8693 size(4);
8694 ins_encode %{
8695 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8696 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8697 %}
8698 ins_pipe(pipe_class_default);
8699 %}
8700
8701 // Mul float double precision
8702 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8703 match(Set dst (MulD src1 src2));
8704 format %{ "FMUL $dst, $src1, $src2" %}
8705 size(4);
8706 ins_encode %{
8707 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8708 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8709 %}
8710 ins_pipe(pipe_class_default);
8711 %}
8712
8713 // Div float single precision
8714 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8715 match(Set dst (DivF src1 src2));
8716 format %{ "FDIVS $dst, $src1, $src2" %}
8717 size(4);
8718 ins_encode %{
8719 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8720 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8721 %}
8722 ins_pipe(pipe_class_default);
8723 %}
8724
8725 // Div float double precision
8726 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8727 match(Set dst (DivD src1 src2));
8728 format %{ "FDIV $dst, $src1, $src2" %}
8729 size(4);
8730 ins_encode %{
8731 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8732 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8733 %}
8734 ins_pipe(pipe_class_default);
8735 %}
8736
8737 // Absolute float single precision
8738 instruct absF_reg(regF dst, regF src) %{
8739 match(Set dst (AbsF src));
8740 format %{ "FABS $dst, $src \t// float" %}
8741 size(4);
8742 ins_encode %{
8743 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8744 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8745 %}
8746 ins_pipe(pipe_class_default);
8747 %}
8748
8749 // Absolute float double precision
8750 instruct absD_reg(regD dst, regD src) %{
8751 match(Set dst (AbsD src));
8752 format %{ "FABS $dst, $src \t// double" %}
8753 size(4);
8754 ins_encode %{
8755 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8756 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8757 %}
8758 ins_pipe(pipe_class_default);
8759 %}
8760
8761 instruct negF_reg(regF dst, regF src) %{
8762 match(Set dst (NegF src));
8763 format %{ "FNEG $dst, $src \t// float" %}
8764 size(4);
8765 ins_encode %{
8766 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8767 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8768 %}
8769 ins_pipe(pipe_class_default);
8770 %}
8771
8772 instruct negD_reg(regD dst, regD src) %{
8773 match(Set dst (NegD src));
8774 format %{ "FNEG $dst, $src \t// double" %}
8775 size(4);
8776 ins_encode %{
8777 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8778 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8779 %}
8780 ins_pipe(pipe_class_default);
8781 %}
8782
8783 // AbsF + NegF.
8784 instruct negF_absF_reg(regF dst, regF src) %{
8785 match(Set dst (NegF (AbsF src)));
8786 format %{ "FNABS $dst, $src \t// float" %}
8787 size(4);
8788 ins_encode %{
8789 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8790 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8791 %}
8792 ins_pipe(pipe_class_default);
8793 %}
8794
8795 // AbsD + NegD.
8796 instruct negD_absD_reg(regD dst, regD src) %{
8797 match(Set dst (NegD (AbsD src)));
8798 format %{ "FNABS $dst, $src \t// double" %}
8799 size(4);
8800 ins_encode %{
8801 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8802 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8803 %}
8804 ins_pipe(pipe_class_default);
8805 %}
8806
8807 // VM_Version::has_fsqrt() decides if this node will be used.
8808 // Sqrt float double precision
8809 instruct sqrtD_reg(regD dst, regD src) %{
8810 match(Set dst (SqrtD src));
8811 format %{ "FSQRT $dst, $src" %}
8812 size(4);
8813 ins_encode %{
8814 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8815 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8816 %}
8817 ins_pipe(pipe_class_default);
8818 %}
8819
8820 // Single-precision sqrt.
8821 instruct sqrtF_reg(regF dst, regF src) %{
8822 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8823 predicate(VM_Version::has_fsqrts());
8824 ins_cost(DEFAULT_COST);
8825
8826 format %{ "FSQRTS $dst, $src" %}
8827 size(4);
8828 ins_encode %{
8829 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8830 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8831 %}
8832 ins_pipe(pipe_class_default);
8833 %}
8834
8835 instruct roundDouble_nop(regD dst) %{
8836 match(Set dst (RoundDouble dst));
8837 ins_cost(0);
8838
8839 format %{ " -- \t// RoundDouble not needed - empty" %}
8840 size(0);
8841 // PPC results are already "rounded" (i.e., normal-format IEEE).
8842 ins_encode( /*empty*/ );
8843 ins_pipe(pipe_class_default);
8844 %}
8845
8846 instruct roundFloat_nop(regF dst) %{
8847 match(Set dst (RoundFloat dst));
8848 ins_cost(0);
8849
8850 format %{ " -- \t// RoundFloat not needed - empty" %}
8851 size(0);
8852 // PPC results are already "rounded" (i.e., normal-format IEEE).
8853 ins_encode( /*empty*/ );
8854 ins_pipe(pipe_class_default);
8855 %}
8856
8857 //----------Logical Instructions-----------------------------------------------
8858
8859 // And Instructions
8860
8861 // Register And
8862 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8863 match(Set dst (AndI src1 src2));
8864 format %{ "AND $dst, $src1, $src2" %}
8865 size(4);
8866 ins_encode %{
8867 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8868 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8869 %}
8870 ins_pipe(pipe_class_default);
8871 %}
8872
8873 // Immediate And
8874 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8875 match(Set dst (AndI src1 src2));
8876 effect(KILL cr0);
8877
8878 format %{ "ANDI $dst, $src1, $src2" %}
8879 size(4);
8880 ins_encode %{
8881 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8882 // FIXME: avoid andi_ ?
8883 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8884 %}
8885 ins_pipe(pipe_class_default);
8886 %}
8887
8888 // Immediate And where the immediate is a negative power of 2.
8889 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8890 match(Set dst (AndI src1 src2));
8891 format %{ "ANDWI $dst, $src1, $src2" %}
8892 size(4);
8893 ins_encode %{
8894 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8895 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8896 %}
8897 ins_pipe(pipe_class_default);
8898 %}
8899
8900 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8901 match(Set dst (AndI src1 src2));
8902 format %{ "ANDWI $dst, $src1, $src2" %}
8903 size(4);
8904 ins_encode %{
8905 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8906 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8907 %}
8908 ins_pipe(pipe_class_default);
8909 %}
8910
8911 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8912 match(Set dst (AndI src1 src2));
8913 predicate(UseRotateAndMaskInstructionsPPC64);
8914 format %{ "ANDWI $dst, $src1, $src2" %}
8915 size(4);
8916 ins_encode %{
8917 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8918 __ rlwinm($dst$$Register, $src1$$Register, 0,
8919 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8920 %}
8921 ins_pipe(pipe_class_default);
8922 %}
8923
8924 // Register And Long
8925 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8926 match(Set dst (AndL src1 src2));
8927 ins_cost(DEFAULT_COST);
8928
8929 format %{ "AND $dst, $src1, $src2 \t// long" %}
8930 size(4);
8931 ins_encode %{
8932 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8933 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8934 %}
8935 ins_pipe(pipe_class_default);
8936 %}
8937
8938 // Immediate And long
8939 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8940 match(Set dst (AndL src1 src2));
8941 effect(KILL cr0);
8942 ins_cost(DEFAULT_COST);
8943
8944 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8945 size(4);
8946 ins_encode %{
8947 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8948 // FIXME: avoid andi_ ?
8949 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8950 %}
8951 ins_pipe(pipe_class_default);
8952 %}
8953
8954 // Immediate And Long where the immediate is a negative power of 2.
8955 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8956 match(Set dst (AndL src1 src2));
8957 format %{ "ANDDI $dst, $src1, $src2" %}
8958 size(4);
8959 ins_encode %{
8960 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8961 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8962 %}
8963 ins_pipe(pipe_class_default);
8964 %}
8965
8966 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8967 match(Set dst (AndL src1 src2));
8968 format %{ "ANDDI $dst, $src1, $src2" %}
8969 size(4);
8970 ins_encode %{
8971 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8972 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8973 %}
8974 ins_pipe(pipe_class_default);
8975 %}
8976
8977 // AndL + ConvL2I.
8978 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8979 match(Set dst (ConvL2I (AndL src1 src2)));
8980 ins_cost(DEFAULT_COST);
8981
8982 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
8983 size(4);
8984 ins_encode %{
8985 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8986 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8987 %}
8988 ins_pipe(pipe_class_default);
8989 %}
8990
8991 // Or Instructions
8992
8993 // Register Or
8994 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8995 match(Set dst (OrI src1 src2));
8996 format %{ "OR $dst, $src1, $src2" %}
8997 size(4);
8998 ins_encode %{
8999 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9000 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9001 %}
9002 ins_pipe(pipe_class_default);
9003 %}
9004
9005 // Expand does not work with above instruct. (??)
9006 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9007 // no match-rule
9008 effect(DEF dst, USE src1, USE src2);
9009 format %{ "OR $dst, $src1, $src2" %}
9010 size(4);
9011 ins_encode %{
9012 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9013 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9014 %}
9015 ins_pipe(pipe_class_default);
9016 %}
9017
9018 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9019 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9020 ins_cost(DEFAULT_COST*3);
9021
9022 expand %{
9023 // FIXME: we should do this in the ideal world.
9024 iRegIdst tmp1;
9025 iRegIdst tmp2;
9026 orI_reg_reg(tmp1, src1, src2);
9027 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9028 orI_reg_reg(dst, tmp1, tmp2);
9029 %}
9030 %}
9031
9032 // Immediate Or
9033 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9034 match(Set dst (OrI src1 src2));
9035 format %{ "ORI $dst, $src1, $src2" %}
9036 size(4);
9037 ins_encode %{
9038 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9039 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9040 %}
9041 ins_pipe(pipe_class_default);
9042 %}
9043
9044 // Register Or Long
9045 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9046 match(Set dst (OrL src1 src2));
9047 ins_cost(DEFAULT_COST);
9048
9049 size(4);
9050 format %{ "OR $dst, $src1, $src2 \t// long" %}
9051 ins_encode %{
9052 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9053 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9054 %}
9055 ins_pipe(pipe_class_default);
9056 %}
9057
9058 // OrL + ConvL2I.
9059 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9060 match(Set dst (ConvL2I (OrL src1 src2)));
9061 ins_cost(DEFAULT_COST);
9062
9063 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9064 size(4);
9065 ins_encode %{
9066 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9067 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9068 %}
9069 ins_pipe(pipe_class_default);
9070 %}
9071
9072 // Immediate Or long
9073 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9074 match(Set dst (OrL src1 con));
9075 ins_cost(DEFAULT_COST);
9076
9077 format %{ "ORI $dst, $src1, $con \t// long" %}
9078 size(4);
9079 ins_encode %{
9080 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9081 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9082 %}
9083 ins_pipe(pipe_class_default);
9084 %}
9085
9086 // Xor Instructions
9087
9088 // Register Xor
9089 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9090 match(Set dst (XorI src1 src2));
9091 format %{ "XOR $dst, $src1, $src2" %}
9092 size(4);
9093 ins_encode %{
9094 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9095 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9096 %}
9097 ins_pipe(pipe_class_default);
9098 %}
9099
9100 // Expand does not work with above instruct. (??)
9101 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9102 // no match-rule
9103 effect(DEF dst, USE src1, USE src2);
9104 format %{ "XOR $dst, $src1, $src2" %}
9105 size(4);
9106 ins_encode %{
9107 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9108 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9109 %}
9110 ins_pipe(pipe_class_default);
9111 %}
9112
9113 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9114 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9115 ins_cost(DEFAULT_COST*3);
9116
9117 expand %{
9118 // FIXME: we should do this in the ideal world.
9119 iRegIdst tmp1;
9120 iRegIdst tmp2;
9121 xorI_reg_reg(tmp1, src1, src2);
9122 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9123 xorI_reg_reg(dst, tmp1, tmp2);
9124 %}
9125 %}
9126
9127 // Immediate Xor
9128 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9129 match(Set dst (XorI src1 src2));
9130 format %{ "XORI $dst, $src1, $src2" %}
9131 size(4);
9132 ins_encode %{
9133 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9134 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9135 %}
9136 ins_pipe(pipe_class_default);
9137 %}
9138
9139 // Register Xor Long
9140 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9141 match(Set dst (XorL src1 src2));
9142 ins_cost(DEFAULT_COST);
9143
9144 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9145 size(4);
9146 ins_encode %{
9147 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9148 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9149 %}
9150 ins_pipe(pipe_class_default);
9151 %}
9152
9153 // XorL + ConvL2I.
9154 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9155 match(Set dst (ConvL2I (XorL src1 src2)));
9156 ins_cost(DEFAULT_COST);
9157
9158 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9159 size(4);
9160 ins_encode %{
9161 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9162 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9163 %}
9164 ins_pipe(pipe_class_default);
9165 %}
9166
9167 // Immediate Xor Long
9168 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9169 match(Set dst (XorL src1 src2));
9170 ins_cost(DEFAULT_COST);
9171
9172 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9173 size(4);
9174 ins_encode %{
9175 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9176 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9177 %}
9178 ins_pipe(pipe_class_default);
9179 %}
9180
9181 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9182 match(Set dst (XorI src1 src2));
9183 ins_cost(DEFAULT_COST);
9184
9185 format %{ "NOT $dst, $src1 ($src2)" %}
9186 size(4);
9187 ins_encode %{
9188 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9189 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9190 %}
9191 ins_pipe(pipe_class_default);
9192 %}
9193
9194 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9195 match(Set dst (XorL src1 src2));
9196 ins_cost(DEFAULT_COST);
9197
9198 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9199 size(4);
9200 ins_encode %{
9201 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9202 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9203 %}
9204 ins_pipe(pipe_class_default);
9205 %}
9206
9207 // And-complement
9208 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9209 match(Set dst (AndI (XorI src1 src2) src3));
9210 ins_cost(DEFAULT_COST);
9211
9212 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9213 size(4);
9214 ins_encode( enc_andc(dst, src3, src1) );
9215 ins_pipe(pipe_class_default);
9216 %}
9217
9218 // And-complement
9219 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9220 // no match-rule, false predicate
9221 effect(DEF dst, USE src1, USE src2);
9222 predicate(false);
9223
9224 format %{ "ANDC $dst, $src1, $src2" %}
9225 size(4);
9226 ins_encode %{
9227 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9228 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9229 %}
9230 ins_pipe(pipe_class_default);
9231 %}
9232
9233 //----------Moves between int/long and float/double----------------------------
9234 //
9235 // The following rules move values from int/long registers/stack-locations
9236 // to float/double registers/stack-locations and vice versa, without doing any
9237 // conversions. These rules are used to implement the bit-conversion methods
9238 // of java.lang.Float etc., e.g.
9239 // int floatToIntBits(float value)
9240 // float intBitsToFloat(int bits)
9241 //
9242 // Notes on the implementation on ppc64:
9243 // We only provide rules which move between a register and a stack-location,
9244 // because we always have to go through memory when moving between a float
9245 // register and an integer register.
9246
9247 //---------- Chain stack slots between similar types --------
9248
9249 // These are needed so that the rules below can match.
9250
9251 // Load integer from stack slot
9252 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9253 match(Set dst src);
9254 ins_cost(MEMORY_REF_COST);
9255
9256 format %{ "LWZ $dst, $src" %}
9257 size(4);
9258 ins_encode( enc_lwz(dst, src) );
9259 ins_pipe(pipe_class_memory);
9260 %}
9261
9262 // Store integer to stack slot
9263 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9264 match(Set dst src);
9265 ins_cost(MEMORY_REF_COST);
9266
9267 format %{ "STW $src, $dst \t// stk" %}
9268 size(4);
9269 ins_encode( enc_stw(src, dst) ); // rs=rt
9270 ins_pipe(pipe_class_memory);
9271 %}
9272
9273 // Load long from stack slot
9274 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9275 match(Set dst src);
9276 ins_cost(MEMORY_REF_COST);
9277
9278 format %{ "LD $dst, $src \t// long" %}
9279 size(4);
9280 ins_encode( enc_ld(dst, src) );
9281 ins_pipe(pipe_class_memory);
9282 %}
9283
9284 // Store long to stack slot
9285 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9286 match(Set dst src);
9287 ins_cost(MEMORY_REF_COST);
9288
9289 format %{ "STD $src, $dst \t// long" %}
9290 size(4);
9291 ins_encode( enc_std(src, dst) ); // rs=rt
9292 ins_pipe(pipe_class_memory);
9293 %}
9294
9295 //----------Moves between int and float
9296
9297 // Move float value from float stack-location to integer register.
9298 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9299 match(Set dst (MoveF2I src));
9300 ins_cost(MEMORY_REF_COST);
9301
9302 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9303 size(4);
9304 ins_encode( enc_lwz(dst, src) );
9305 ins_pipe(pipe_class_memory);
9306 %}
9307
9308 // Move float value from float register to integer stack-location.
9309 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9310 match(Set dst (MoveF2I src));
9311 ins_cost(MEMORY_REF_COST);
9312
9313 format %{ "STFS $src, $dst \t// MoveF2I" %}
9314 size(4);
9315 ins_encode( enc_stfs(src, dst) );
9316 ins_pipe(pipe_class_memory);
9317 %}
9318
9319 // Move integer value from integer stack-location to float register.
9320 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9321 match(Set dst (MoveI2F src));
9322 ins_cost(MEMORY_REF_COST);
9323
9324 format %{ "LFS $dst, $src \t// MoveI2F" %}
9325 size(4);
9326 ins_encode %{
9327 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9328 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9329 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9330 %}
9331 ins_pipe(pipe_class_memory);
9332 %}
9333
9334 // Move integer value from integer register to float stack-location.
9335 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9336 match(Set dst (MoveI2F src));
9337 ins_cost(MEMORY_REF_COST);
9338
9339 format %{ "STW $src, $dst \t// MoveI2F" %}
9340 size(4);
9341 ins_encode( enc_stw(src, dst) );
9342 ins_pipe(pipe_class_memory);
9343 %}
9344
9345 //----------Moves between long and float
9346
9347 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9348 // no match-rule, false predicate
9349 effect(DEF dst, USE src);
9350 predicate(false);
9351
9352 format %{ "storeD $src, $dst \t// STACK" %}
9353 size(4);
9354 ins_encode( enc_stfd(src, dst) );
9355 ins_pipe(pipe_class_default);
9356 %}
9357
9358 //----------Moves between long and double
9359
9360 // Move double value from double stack-location to long register.
9361 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9362 match(Set dst (MoveD2L src));
9363 ins_cost(MEMORY_REF_COST);
9364 size(4);
9365 format %{ "LD $dst, $src \t// MoveD2L" %}
9366 ins_encode( enc_ld(dst, src) );
9367 ins_pipe(pipe_class_memory);
9368 %}
9369
9370 // Move double value from double register to long stack-location.
9371 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9372 match(Set dst (MoveD2L src));
9373 effect(DEF dst, USE src);
9374 ins_cost(MEMORY_REF_COST);
9375
9376 format %{ "STFD $src, $dst \t// MoveD2L" %}
9377 size(4);
9378 ins_encode( enc_stfd(src, dst) );
9379 ins_pipe(pipe_class_memory);
9380 %}
9381
9382 // Move long value from long stack-location to double register.
9383 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9384 match(Set dst (MoveL2D src));
9385 ins_cost(MEMORY_REF_COST);
9386
9387 format %{ "LFD $dst, $src \t// MoveL2D" %}
9388 size(4);
9389 ins_encode( enc_lfd(dst, src) );
9390 ins_pipe(pipe_class_memory);
9391 %}
9392
9393 // Move long value from long register to double stack-location.
9394 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9395 match(Set dst (MoveL2D src));
9396 ins_cost(MEMORY_REF_COST);
9397
9398 format %{ "STD $src, $dst \t// MoveL2D" %}
9399 size(4);
9400 ins_encode( enc_std(src, dst) );
9401 ins_pipe(pipe_class_memory);
9402 %}
9403
9404 //----------Register Move Instructions-----------------------------------------
9405
9406 // Replicate for Superword
9407
9408 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9409 predicate(false);
9410 effect(DEF dst, USE src);
9411
9412 format %{ "MR $dst, $src \t// replicate " %}
9413 // variable size, 0 or 4.
9414 ins_encode %{
9415 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9416 __ mr_if_needed($dst$$Register, $src$$Register);
9417 %}
9418 ins_pipe(pipe_class_default);
9419 %}
9420
9421 //----------Cast instructions (Java-level type cast)---------------------------
9422
9423 // Cast Long to Pointer for unsafe natives.
9424 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9425 match(Set dst (CastX2P src));
9426
9427 format %{ "MR $dst, $src \t// Long->Ptr" %}
9428 // variable size, 0 or 4.
9429 ins_encode %{
9430 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9431 __ mr_if_needed($dst$$Register, $src$$Register);
9432 %}
9433 ins_pipe(pipe_class_default);
9434 %}
9435
9436 // Cast Pointer to Long for unsafe natives.
9437 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9438 match(Set dst (CastP2X src));
9439
9440 format %{ "MR $dst, $src \t// Ptr->Long" %}
9441 // variable size, 0 or 4.
9442 ins_encode %{
9443 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9444 __ mr_if_needed($dst$$Register, $src$$Register);
9445 %}
9446 ins_pipe(pipe_class_default);
9447 %}
9448
9449 instruct castPP(iRegPdst dst) %{
9450 match(Set dst (CastPP dst));
9451 format %{ " -- \t// castPP of $dst" %}
9452 size(0);
9453 ins_encode( /*empty*/ );
9454 ins_pipe(pipe_class_default);
9455 %}
9456
9457 instruct castII(iRegIdst dst) %{
9458 match(Set dst (CastII dst));
9459 format %{ " -- \t// castII of $dst" %}
9460 size(0);
9461 ins_encode( /*empty*/ );
9462 ins_pipe(pipe_class_default);
9463 %}
9464
9465 instruct checkCastPP(iRegPdst dst) %{
9466 match(Set dst (CheckCastPP dst));
9467 format %{ " -- \t// checkcastPP of $dst" %}
9468 size(0);
9469 ins_encode( /*empty*/ );
9470 ins_pipe(pipe_class_default);
9471 %}
9472
9473 //----------Convert instructions-----------------------------------------------
9474
9475 // Convert to boolean.
9476
9477 // int_to_bool(src) : { 1 if src != 0
9478 // { 0 else
9479 //
9480 // strategy:
9481 // 1) Count leading zeros of 32 bit-value src,
9482 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9483 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9484 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9485
9486 // convI2Bool
9487 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9488 match(Set dst (Conv2B src));
9489 predicate(UseCountLeadingZerosInstructionsPPC64);
9490 ins_cost(DEFAULT_COST);
9491
9492 expand %{
9493 immI shiftAmount %{ 0x5 %}
9494 uimmI16 mask %{ 0x1 %}
9495 iRegIdst tmp1;
9496 iRegIdst tmp2;
9497 countLeadingZerosI(tmp1, src);
9498 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9499 xorI_reg_uimm16(dst, tmp2, mask);
9500 %}
9501 %}
9502
9503 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9504 match(Set dst (Conv2B src));
9505 effect(TEMP crx);
9506 predicate(!UseCountLeadingZerosInstructionsPPC64);
9507 ins_cost(DEFAULT_COST);
9508
9509 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9510 "LI $dst, #0\n\t"
9511 "BEQ $crx, done\n\t"
9512 "LI $dst, #1\n"
9513 "done:" %}
9514 size(16);
9515 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9516 ins_pipe(pipe_class_compare);
9517 %}
9518
9519 // ConvI2B + XorI
9520 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9521 match(Set dst (XorI (Conv2B src) mask));
9522 predicate(UseCountLeadingZerosInstructionsPPC64);
9523 ins_cost(DEFAULT_COST);
9524
9525 expand %{
9526 immI shiftAmount %{ 0x5 %}
9527 iRegIdst tmp1;
9528 countLeadingZerosI(tmp1, src);
9529 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9530 %}
9531 %}
9532
9533 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9534 match(Set dst (XorI (Conv2B src) mask));
9535 effect(TEMP crx);
9536 predicate(!UseCountLeadingZerosInstructionsPPC64);
9537 ins_cost(DEFAULT_COST);
9538
9539 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9540 "LI $dst, #1\n\t"
9541 "BEQ $crx, done\n\t"
9542 "LI $dst, #0\n"
9543 "done:" %}
9544 size(16);
9545 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9546 ins_pipe(pipe_class_compare);
9547 %}
9548
9549 // AndI 0b0..010..0 + ConvI2B
9550 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9551 match(Set dst (Conv2B (AndI src mask)));
9552 predicate(UseRotateAndMaskInstructionsPPC64);
9553 ins_cost(DEFAULT_COST);
9554
9555 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9556 size(4);
9557 ins_encode %{
9558 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9559 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9560 %}
9561 ins_pipe(pipe_class_default);
9562 %}
9563
9564 // Convert pointer to boolean.
9565 //
9566 // ptr_to_bool(src) : { 1 if src != 0
9567 // { 0 else
9568 //
9569 // strategy:
9570 // 1) Count leading zeros of 64 bit-value src,
9571 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9572 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9573 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9574
9575 // ConvP2B
9576 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9577 match(Set dst (Conv2B src));
9578 predicate(UseCountLeadingZerosInstructionsPPC64);
9579 ins_cost(DEFAULT_COST);
9580
9581 expand %{
9582 immI shiftAmount %{ 0x6 %}
9583 uimmI16 mask %{ 0x1 %}
9584 iRegIdst tmp1;
9585 iRegIdst tmp2;
9586 countLeadingZerosP(tmp1, src);
9587 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9588 xorI_reg_uimm16(dst, tmp2, mask);
9589 %}
9590 %}
9591
9592 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9593 match(Set dst (Conv2B src));
9594 effect(TEMP crx);
9595 predicate(!UseCountLeadingZerosInstructionsPPC64);
9596 ins_cost(DEFAULT_COST);
9597
9598 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9599 "LI $dst, #0\n\t"
9600 "BEQ $crx, done\n\t"
9601 "LI $dst, #1\n"
9602 "done:" %}
9603 size(16);
9604 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9605 ins_pipe(pipe_class_compare);
9606 %}
9607
9608 // ConvP2B + XorI
9609 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9610 match(Set dst (XorI (Conv2B src) mask));
9611 predicate(UseCountLeadingZerosInstructionsPPC64);
9612 ins_cost(DEFAULT_COST);
9613
9614 expand %{
9615 immI shiftAmount %{ 0x6 %}
9616 iRegIdst tmp1;
9617 countLeadingZerosP(tmp1, src);
9618 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9619 %}
9620 %}
9621
9622 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9623 match(Set dst (XorI (Conv2B src) mask));
9624 effect(TEMP crx);
9625 predicate(!UseCountLeadingZerosInstructionsPPC64);
9626 ins_cost(DEFAULT_COST);
9627
9628 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9629 "LI $dst, #1\n\t"
9630 "BEQ $crx, done\n\t"
9631 "LI $dst, #0\n"
9632 "done:" %}
9633 size(16);
9634 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9635 ins_pipe(pipe_class_compare);
9636 %}
9637
9638 // if src1 < src2, return -1 else return 0
9639 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9640 match(Set dst (CmpLTMask src1 src2));
9641 ins_cost(DEFAULT_COST*4);
9642
9643 expand %{
9644 iRegLdst src1s;
9645 iRegLdst src2s;
9646 iRegLdst diff;
9647 convI2L_reg(src1s, src1); // Ensure proper sign extension.
9648 convI2L_reg(src2s, src2); // Ensure proper sign extension.
9649 subL_reg_reg(diff, src1s, src2s);
9650 // Need to consider >=33 bit result, therefore we need signmaskL.
9651 signmask64I_regL(dst, diff);
9652 %}
9653 %}
9654
9655 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9656 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9657 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9658 size(4);
9659 ins_encode %{
9660 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9661 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9662 %}
9663 ins_pipe(pipe_class_default);
9664 %}
9665
9666 //----------Arithmetic Conversion Instructions---------------------------------
9667
9668 // Convert to Byte -- nop
9669 // Convert to Short -- nop
9670
9671 // Convert to Int
9672
9673 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9674 match(Set dst (RShiftI (LShiftI src amount) amount));
9675 format %{ "EXTSB $dst, $src \t// byte->int" %}
9676 size(4);
9677 ins_encode %{
9678 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9679 __ extsb($dst$$Register, $src$$Register);
9680 %}
9681 ins_pipe(pipe_class_default);
9682 %}
9683
9684 // LShiftI 16 + RShiftI 16 converts short to int.
9685 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9686 match(Set dst (RShiftI (LShiftI src amount) amount));
9687 format %{ "EXTSH $dst, $src \t// short->int" %}
9688 size(4);
9689 ins_encode %{
9690 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9691 __ extsh($dst$$Register, $src$$Register);
9692 %}
9693 ins_pipe(pipe_class_default);
9694 %}
9695
9696 // ConvL2I + ConvI2L: Sign extend int in long register.
9697 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9698 match(Set dst (ConvI2L (ConvL2I src)));
9699
9700 format %{ "EXTSW $dst, $src \t// long->long" %}
9701 size(4);
9702 ins_encode %{
9703 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9704 __ extsw($dst$$Register, $src$$Register);
9705 %}
9706 ins_pipe(pipe_class_default);
9707 %}
9708
9709 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9710 match(Set dst (ConvL2I src));
9711 format %{ "MR $dst, $src \t// long->int" %}
9712 // variable size, 0 or 4
9713 ins_encode %{
9714 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9715 __ mr_if_needed($dst$$Register, $src$$Register);
9716 %}
9717 ins_pipe(pipe_class_default);
9718 %}
9719
9720 instruct convD2IRaw_regD(regD dst, regD src) %{
9721 // no match-rule, false predicate
9722 effect(DEF dst, USE src);
9723 predicate(false);
9724
9725 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9726 size(4);
9727 ins_encode %{
9728 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9729 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9730 %}
9731 ins_pipe(pipe_class_default);
9732 %}
9733
9734 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{
9735 // no match-rule, false predicate
9736 effect(DEF dst, USE crx, USE src);
9737 predicate(false);
9738
9739 ins_variable_size_depending_on_alignment(true);
9740
9741 format %{ "cmovI $crx, $dst, $src" %}
9742 // Worst case is branch + move + stop, no stop without scheduler.
9743 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9744 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9745 ins_pipe(pipe_class_default);
9746 %}
9747
9748 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{
9749 // no match-rule, false predicate
9750 effect(DEF dst, USE crx, USE mem);
9751 predicate(false);
9752
9753 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9754 postalloc_expand %{
9755 //
9756 // replaces
9757 //
9758 // region dst crx mem
9759 // \ | | /
9760 // dst=cmovI_bso_stackSlotL_conLvalue0
9761 //
9762 // with
9763 //
9764 // region dst
9765 // \ /
9766 // dst=loadConI16(0)
9767 // |
9768 // ^ region dst crx mem
9769 // | \ | | /
9770 // dst=cmovI_bso_stackSlotL
9771 //
9772
9773 // Create new nodes.
9774 MachNode *m1 = new loadConI16Node();
9775 MachNode *m2 = new cmovI_bso_stackSlotLNode();
9776
9777 // inputs for new nodes
9778 m1->add_req(n_region);
9779 m2->add_req(n_region, n_crx, n_mem);
9780
9781 // precedences for new nodes
9782 m2->add_prec(m1);
9783
9784 // operands for new nodes
9785 m1->_opnds[0] = op_dst;
9786 m1->_opnds[1] = new immI16Oper(0);
9787
9788 m2->_opnds[0] = op_dst;
9789 m2->_opnds[1] = op_crx;
9790 m2->_opnds[2] = op_mem;
9791
9792 // registers for new nodes
9793 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9794 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9795
9796 // Insert new nodes.
9797 nodes->push(m1);
9798 nodes->push(m2);
9799 %}
9800 %}
9801
9802 // Double to Int conversion, NaN is mapped to 0.
9803 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9804 match(Set dst (ConvD2I src));
9805 ins_cost(DEFAULT_COST);
9806
9807 expand %{
9808 regD tmpD;
9809 stackSlotL tmpS;
9810 flagsReg crx;
9811 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9812 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9813 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9814 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9815 %}
9816 %}
9817
9818 instruct convF2IRaw_regF(regF dst, regF src) %{
9819 // no match-rule, false predicate
9820 effect(DEF dst, USE src);
9821 predicate(false);
9822
9823 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9824 size(4);
9825 ins_encode %{
9826 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9827 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9828 %}
9829 ins_pipe(pipe_class_default);
9830 %}
9831
9832 // Float to Int conversion, NaN is mapped to 0.
9833 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9834 match(Set dst (ConvF2I src));
9835 ins_cost(DEFAULT_COST);
9836
9837 expand %{
9838 regF tmpF;
9839 stackSlotL tmpS;
9840 flagsReg crx;
9841 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9842 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9843 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9844 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9845 %}
9846 %}
9847
9848 // Convert to Long
9849
9850 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9851 match(Set dst (ConvI2L src));
9852 format %{ "EXTSW $dst, $src \t// int->long" %}
9853 size(4);
9854 ins_encode %{
9855 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9856 __ extsw($dst$$Register, $src$$Register);
9857 %}
9858 ins_pipe(pipe_class_default);
9859 %}
9860
9861 // Zero-extend: convert unsigned int to long (convUI2L).
9862 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9863 match(Set dst (AndL (ConvI2L src) mask));
9864 ins_cost(DEFAULT_COST);
9865
9866 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9867 size(4);
9868 ins_encode %{
9869 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9870 __ clrldi($dst$$Register, $src$$Register, 32);
9871 %}
9872 ins_pipe(pipe_class_default);
9873 %}
9874
9875 // Zero-extend: convert unsigned int to long in long register.
9876 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9877 match(Set dst (AndL src mask));
9878 ins_cost(DEFAULT_COST);
9879
9880 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9881 size(4);
9882 ins_encode %{
9883 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9884 __ clrldi($dst$$Register, $src$$Register, 32);
9885 %}
9886 ins_pipe(pipe_class_default);
9887 %}
9888
9889 instruct convF2LRaw_regF(regF dst, regF src) %{
9890 // no match-rule, false predicate
9891 effect(DEF dst, USE src);
9892 predicate(false);
9893
9894 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9895 size(4);
9896 ins_encode %{
9897 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9898 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9899 %}
9900 ins_pipe(pipe_class_default);
9901 %}
9902
9903 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{
9904 // no match-rule, false predicate
9905 effect(DEF dst, USE crx, USE src);
9906 predicate(false);
9907
9908 ins_variable_size_depending_on_alignment(true);
9909
9910 format %{ "cmovL $crx, $dst, $src" %}
9911 // Worst case is branch + move + stop, no stop without scheduler.
9912 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9913 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9914 ins_pipe(pipe_class_default);
9915 %}
9916
9917 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{
9918 // no match-rule, false predicate
9919 effect(DEF dst, USE crx, USE mem);
9920 predicate(false);
9921
9922 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9923 postalloc_expand %{
9924 //
9925 // replaces
9926 //
9927 // region dst crx mem
9928 // \ | | /
9929 // dst=cmovL_bso_stackSlotL_conLvalue0
9930 //
9931 // with
9932 //
9933 // region dst
9934 // \ /
9935 // dst=loadConL16(0)
9936 // |
9937 // ^ region dst crx mem
9938 // | \ | | /
9939 // dst=cmovL_bso_stackSlotL
9940 //
9941
9942 // Create new nodes.
9943 MachNode *m1 = new loadConL16Node();
9944 MachNode *m2 = new cmovL_bso_stackSlotLNode();
9945
9946 // inputs for new nodes
9947 m1->add_req(n_region);
9948 m2->add_req(n_region, n_crx, n_mem);
9949 m2->add_prec(m1);
9950
9951 // operands for new nodes
9952 m1->_opnds[0] = op_dst;
9953 m1->_opnds[1] = new immL16Oper(0);
9954 m2->_opnds[0] = op_dst;
9955 m2->_opnds[1] = op_crx;
9956 m2->_opnds[2] = op_mem;
9957
9958 // registers for new nodes
9959 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9960 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9961
9962 // Insert new nodes.
9963 nodes->push(m1);
9964 nodes->push(m2);
9965 %}
9966 %}
9967
9968 // Float to Long conversion, NaN is mapped to 0.
9969 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9970 match(Set dst (ConvF2L src));
9971 ins_cost(DEFAULT_COST);
9972
9973 expand %{
9974 regF tmpF;
9975 stackSlotL tmpS;
9976 flagsReg crx;
9977 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9978 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
9979 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9980 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9981 %}
9982 %}
9983
9984 instruct convD2LRaw_regD(regD dst, regD src) %{
9985 // no match-rule, false predicate
9986 effect(DEF dst, USE src);
9987 predicate(false);
9988
9989 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
9990 size(4);
9991 ins_encode %{
9992 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9993 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9994 %}
9995 ins_pipe(pipe_class_default);
9996 %}
9997
9998 // Double to Long conversion, NaN is mapped to 0.
9999 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10000 match(Set dst (ConvD2L src));
10001 ins_cost(DEFAULT_COST);
10002
10003 expand %{
10004 regD tmpD;
10005 stackSlotL tmpS;
10006 flagsReg crx;
10007 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10008 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
10009 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
10010 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10011 %}
10012 %}
10013
10014 // Convert to Float
10015
10016 // Placed here as needed in expand.
10017 instruct convL2DRaw_regD(regD dst, regD src) %{
10018 // no match-rule, false predicate
10019 effect(DEF dst, USE src);
10020 predicate(false);
10021
10022 format %{ "FCFID $dst, $src \t// convL2D" %}
10023 size(4);
10024 ins_encode %{
10025 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10026 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10027 %}
10028 ins_pipe(pipe_class_default);
10029 %}
10030
10031 // Placed here as needed in expand.
10032 instruct convD2F_reg(regF dst, regD src) %{
10033 match(Set dst (ConvD2F src));
10034 format %{ "FRSP $dst, $src \t// convD2F" %}
10035 size(4);
10036 ins_encode %{
10037 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10038 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10039 %}
10040 ins_pipe(pipe_class_default);
10041 %}
10042
10043 // Integer to Float conversion.
10044 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10045 match(Set dst (ConvI2F src));
10046 predicate(!VM_Version::has_fcfids());
10047 ins_cost(DEFAULT_COST);
10048
10049 expand %{
10050 iRegLdst tmpL;
10051 stackSlotL tmpS;
10052 regD tmpD;
10053 regD tmpD2;
10054 convI2L_reg(tmpL, src); // Sign-extension int to long.
10055 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10056 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10057 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
10058 convD2F_reg(dst, tmpD2); // Convert double to float.
10059 %}
10060 %}
10061
10062 instruct convL2FRaw_regF(regF dst, regD src) %{
10063 // no match-rule, false predicate
10064 effect(DEF dst, USE src);
10065 predicate(false);
10066
10067 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10068 size(4);
10069 ins_encode %{
10070 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10071 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10072 %}
10073 ins_pipe(pipe_class_default);
10074 %}
10075
10076 // Integer to Float conversion. Special version for Power7.
10077 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10078 match(Set dst (ConvI2F src));
10079 predicate(VM_Version::has_fcfids());
10080 ins_cost(DEFAULT_COST);
10081
10082 expand %{
10083 iRegLdst tmpL;
10084 stackSlotL tmpS;
10085 regD tmpD;
10086 convI2L_reg(tmpL, src); // Sign-extension int to long.
10087 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10088 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10089 convL2FRaw_regF(dst, tmpD); // Convert to float.
10090 %}
10091 %}
10092
10093 // L2F to avoid runtime call.
10094 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10095 match(Set dst (ConvL2F src));
10096 predicate(VM_Version::has_fcfids());
10097 ins_cost(DEFAULT_COST);
10098
10099 expand %{
10100 stackSlotL tmpS;
10101 regD tmpD;
10102 regL_to_stkL(tmpS, src); // Store long to stack.
10103 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10104 convL2FRaw_regF(dst, tmpD); // Convert to float.
10105 %}
10106 %}
10107
10108 // Moved up as used in expand.
10109 //instruct convD2F_reg(regF dst, regD src) %{%}
10110
10111 // Convert to Double
10112
10113 // Integer to Double conversion.
10114 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10115 match(Set dst (ConvI2D src));
10116 ins_cost(DEFAULT_COST);
10117
10118 expand %{
10119 iRegLdst tmpL;
10120 stackSlotL tmpS;
10121 regD tmpD;
10122 convI2L_reg(tmpL, src); // Sign-extension int to long.
10123 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10124 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10125 convL2DRaw_regD(dst, tmpD); // Convert to double.
10126 %}
10127 %}
10128
10129 // Long to Double conversion
10130 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10131 match(Set dst (ConvL2D src));
10132 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10133
10134 expand %{
10135 regD tmpD;
10136 moveL2D_stack_reg(tmpD, src);
10137 convL2DRaw_regD(dst, tmpD);
10138 %}
10139 %}
10140
10141 instruct convF2D_reg(regD dst, regF src) %{
10142 match(Set dst (ConvF2D src));
10143 format %{ "FMR $dst, $src \t// float->double" %}
10144 // variable size, 0 or 4
10145 ins_encode %{
10146 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10147 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10148 %}
10149 ins_pipe(pipe_class_default);
10150 %}
10151
10152 //----------Control Flow Instructions------------------------------------------
10153 // Compare Instructions
10154
10155 // Compare Integers
10156 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10157 match(Set crx (CmpI src1 src2));
10158 size(4);
10159 format %{ "CMPW $crx, $src1, $src2" %}
10160 ins_encode %{
10161 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10162 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10163 %}
10164 ins_pipe(pipe_class_compare);
10165 %}
10166
10167 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10168 match(Set crx (CmpI src1 src2));
10169 format %{ "CMPWI $crx, $src1, $src2" %}
10170 size(4);
10171 ins_encode %{
10172 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10173 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10174 %}
10175 ins_pipe(pipe_class_compare);
10176 %}
10177
10178 // (src1 & src2) == 0?
10179 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10180 match(Set cr0 (CmpI (AndI src1 src2) zero));
10181 // r0 is killed
10182 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10183 size(4);
10184 ins_encode %{
10185 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10186 // FIXME: avoid andi_ ?
10187 __ andi_(R0, $src1$$Register, $src2$$constant);
10188 %}
10189 ins_pipe(pipe_class_compare);
10190 %}
10191
10192 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10193 match(Set crx (CmpL src1 src2));
10194 format %{ "CMPD $crx, $src1, $src2" %}
10195 size(4);
10196 ins_encode %{
10197 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10198 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10199 %}
10200 ins_pipe(pipe_class_compare);
10201 %}
10202
10203 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10204 match(Set crx (CmpL src1 src2));
10205 format %{ "CMPDI $crx, $src1, $src2" %}
10206 size(4);
10207 ins_encode %{
10208 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10209 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10210 %}
10211 ins_pipe(pipe_class_compare);
10212 %}
10213
10214 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10215 match(Set cr0 (CmpL (AndL src1 src2) zero));
10216 // r0 is killed
10217 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10218 size(4);
10219 ins_encode %{
10220 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10221 __ and_(R0, $src1$$Register, $src2$$Register);
10222 %}
10223 ins_pipe(pipe_class_compare);
10224 %}
10225
10226 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10227 match(Set cr0 (CmpL (AndL src1 src2) zero));
10228 // r0 is killed
10229 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10230 size(4);
10231 ins_encode %{
10232 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10233 // FIXME: avoid andi_ ?
10234 __ andi_(R0, $src1$$Register, $src2$$constant);
10235 %}
10236 ins_pipe(pipe_class_compare);
10237 %}
10238
10239 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{
10240 // no match-rule, false predicate
10241 effect(DEF dst, USE crx);
10242 predicate(false);
10243
10244 ins_variable_size_depending_on_alignment(true);
10245
10246 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10247 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10248 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10249 ins_encode %{
10250 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10251 Label done;
10252 // li(Rdst, 0); // equal -> 0
10253 __ beq($crx$$CondRegister, done);
10254 __ li($dst$$Register, 1); // greater -> +1
10255 __ bgt($crx$$CondRegister, done);
10256 __ li($dst$$Register, -1); // unordered or less -> -1
10257 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10258 __ bind(done);
10259 %}
10260 ins_pipe(pipe_class_compare);
10261 %}
10262
10263 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{
10264 // no match-rule, false predicate
10265 effect(DEF dst, USE crx);
10266 predicate(false);
10267
10268 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10269 postalloc_expand %{
10270 //
10271 // replaces
10272 //
10273 // region crx
10274 // \ |
10275 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10276 //
10277 // with
10278 //
10279 // region
10280 // \
10281 // dst=loadConI16(0)
10282 // |
10283 // ^ region crx
10284 // | \ |
10285 // dst=cmovI_conIvalueMinus1_conIvalue1
10286 //
10287
10288 // Create new nodes.
10289 MachNode *m1 = new loadConI16Node();
10290 MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
10291
10292 // inputs for new nodes
10293 m1->add_req(n_region);
10294 m2->add_req(n_region, n_crx);
10295 m2->add_prec(m1);
10296
10297 // operands for new nodes
10298 m1->_opnds[0] = op_dst;
10299 m1->_opnds[1] = new immI16Oper(0);
10300 m2->_opnds[0] = op_dst;
10301 m2->_opnds[1] = op_crx;
10302
10303 // registers for new nodes
10304 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10305 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10306
10307 // Insert new nodes.
10308 nodes->push(m1);
10309 nodes->push(m2);
10310 %}
10311 %}
10312
10313 // Manifest a CmpL3 result in an integer register. Very painful.
10314 // This is the test to avoid.
10315 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10316 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10317 match(Set dst (CmpL3 src1 src2));
10318 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10319
10320 expand %{
10321 flagsReg tmp1;
10322 cmpL_reg_reg(tmp1, src1, src2);
10323 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10324 %}
10325 %}
10326
10327 // Implicit range checks.
10328 // A range check in the ideal world has one of the following shapes:
10329 // - (If le (CmpU length index)), (IfTrue throw exception)
10330 // - (If lt (CmpU index length)), (IfFalse throw exception)
10331 //
10332 // Match range check 'If le (CmpU length index)'.
10333 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10334 match(If cmp (CmpU src_length index));
10335 effect(USE labl);
10336 predicate(TrapBasedRangeChecks &&
10337 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10338 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10339 (Matcher::branches_to_uncommon_trap(_leaf)));
10340
10341 ins_is_TrapBasedCheckNode(true);
10342
10343 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10344 size(4);
10345 ins_encode %{
10346 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10347 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10348 __ trap_range_check_le($src_length$$Register, $index$$constant);
10349 } else {
10350 // Both successors are uncommon traps, probability is 0.
10351 // Node got flipped during fixup flow.
10352 assert($cmp$$cmpcode == 0x9, "must be greater");
10353 __ trap_range_check_g($src_length$$Register, $index$$constant);
10354 }
10355 %}
10356 ins_pipe(pipe_class_trap);
10357 %}
10358
10359 // Match range check 'If lt (CmpU index length)'.
10360 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10361 match(If cmp (CmpU src_index src_length));
10362 effect(USE labl);
10363 predicate(TrapBasedRangeChecks &&
10364 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10365 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10366 (Matcher::branches_to_uncommon_trap(_leaf)));
10367
10368 ins_is_TrapBasedCheckNode(true);
10369
10370 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10371 size(4);
10372 ins_encode %{
10373 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10374 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10375 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10376 } else {
10377 // Both successors are uncommon traps, probability is 0.
10378 // Node got flipped during fixup flow.
10379 assert($cmp$$cmpcode == 0x8, "must be less");
10380 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10381 }
10382 %}
10383 ins_pipe(pipe_class_trap);
10384 %}
10385
10386 // Match range check 'If lt (CmpU index length)'.
10387 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10388 match(If cmp (CmpU src_index length));
10389 effect(USE labl);
10390 predicate(TrapBasedRangeChecks &&
10391 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10392 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10393 (Matcher::branches_to_uncommon_trap(_leaf)));
10394
10395 ins_is_TrapBasedCheckNode(true);
10396
10397 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10398 size(4);
10399 ins_encode %{
10400 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10401 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10402 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10403 } else {
10404 // Both successors are uncommon traps, probability is 0.
10405 // Node got flipped during fixup flow.
10406 assert($cmp$$cmpcode == 0x8, "must be less");
10407 __ trap_range_check_l($src_index$$Register, $length$$constant);
10408 }
10409 %}
10410 ins_pipe(pipe_class_trap);
10411 %}
10412
10413 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10414 match(Set crx (CmpU src1 src2));
10415 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10416 size(4);
10417 ins_encode %{
10418 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10419 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10420 %}
10421 ins_pipe(pipe_class_compare);
10422 %}
10423
10424 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10425 match(Set crx (CmpU src1 src2));
10426 size(4);
10427 format %{ "CMPLWI $crx, $src1, $src2" %}
10428 ins_encode %{
10429 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10430 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10431 %}
10432 ins_pipe(pipe_class_compare);
10433 %}
10434
10435 // Implicit zero checks (more implicit null checks).
10436 // No constant pool entries required.
10437 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10438 match(If cmp (CmpN value zero));
10439 effect(USE labl);
10440 predicate(TrapBasedNullChecks &&
10441 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10442 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10443 Matcher::branches_to_uncommon_trap(_leaf));
10444 ins_cost(1);
10445
10446 ins_is_TrapBasedCheckNode(true);
10447
10448 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10449 size(4);
10450 ins_encode %{
10451 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10452 if ($cmp$$cmpcode == 0xA) {
10453 __ trap_null_check($value$$Register);
10454 } else {
10455 // Both successors are uncommon traps, probability is 0.
10456 // Node got flipped during fixup flow.
10457 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10458 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10459 }
10460 %}
10461 ins_pipe(pipe_class_trap);
10462 %}
10463
10464 // Compare narrow oops.
10465 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10466 match(Set crx (CmpN src1 src2));
10467
10468 size(4);
10469 ins_cost(DEFAULT_COST);
10470 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10471 ins_encode %{
10472 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10473 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10474 %}
10475 ins_pipe(pipe_class_compare);
10476 %}
10477
10478 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10479 match(Set crx (CmpN src1 src2));
10480 // Make this more expensive than zeroCheckN_iReg_imm0.
10481 ins_cost(DEFAULT_COST);
10482
10483 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10484 size(4);
10485 ins_encode %{
10486 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10487 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10488 %}
10489 ins_pipe(pipe_class_compare);
10490 %}
10491
10492 // Implicit zero checks (more implicit null checks).
10493 // No constant pool entries required.
10494 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10495 match(If cmp (CmpP value zero));
10496 effect(USE labl);
10497 predicate(TrapBasedNullChecks &&
10498 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10499 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10500 Matcher::branches_to_uncommon_trap(_leaf));
10501
10502 ins_is_TrapBasedCheckNode(true);
10503
10504 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10505 size(4);
10506 ins_encode %{
10507 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10508 if ($cmp$$cmpcode == 0xA) {
10509 __ trap_null_check($value$$Register);
10510 } else {
10511 // Both successors are uncommon traps, probability is 0.
10512 // Node got flipped during fixup flow.
10513 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10514 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10515 }
10516 %}
10517 ins_pipe(pipe_class_trap);
10518 %}
10519
10520 // Compare Pointers
10521 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10522 match(Set crx (CmpP src1 src2));
10523 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10524 size(4);
10525 ins_encode %{
10526 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10527 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10528 %}
10529 ins_pipe(pipe_class_compare);
10530 %}
10531
10532 // Used in postalloc expand.
10533 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10534 // This match rule prevents reordering of node before a safepoint.
10535 // This only makes sense if this instructions is used exclusively
10536 // for the expansion of EncodeP!
10537 match(Set crx (CmpP src1 src2));
10538 predicate(false);
10539
10540 format %{ "CMPDI $crx, $src1, $src2" %}
10541 size(4);
10542 ins_encode %{
10543 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10544 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10545 %}
10546 ins_pipe(pipe_class_compare);
10547 %}
10548
10549 //----------Float Compares----------------------------------------------------
10550
10551 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10552 // no match-rule, false predicate
10553 effect(DEF crx, USE src1, USE src2);
10554 predicate(false);
10555
10556 format %{ "cmpFUrd $crx, $src1, $src2" %}
10557 size(4);
10558 ins_encode %{
10559 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10560 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10561 %}
10562 ins_pipe(pipe_class_default);
10563 %}
10564
10565 instruct cmov_bns_less(flagsReg crx) %{
10566 // no match-rule, false predicate
10567 effect(DEF crx);
10568 predicate(false);
10569
10570 ins_variable_size_depending_on_alignment(true);
10571
10572 format %{ "cmov $crx" %}
10573 // Worst case is branch + move + stop, no stop without scheduler.
10574 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10575 ins_encode %{
10576 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10577 Label done;
10578 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10579 __ li(R0, 0);
10580 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10581 // TODO PPC port __ endgroup_if_needed(_size == 16);
10582 __ bind(done);
10583 %}
10584 ins_pipe(pipe_class_default);
10585 %}
10586
10587 // Compare floating, generate condition code.
10588 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10589 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10590 //
10591 // The following code sequence occurs a lot in mpegaudio:
10592 //
10593 // block BXX:
10594 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10595 // cmpFUrd CCR6, F11, F9
10596 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10597 // cmov CCR6
10598 // 8: instruct branchConSched:
10599 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10600 match(Set crx (CmpF src1 src2));
10601 ins_cost(DEFAULT_COST+BRANCH_COST);
10602
10603 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10604 postalloc_expand %{
10605 //
10606 // replaces
10607 //
10608 // region src1 src2
10609 // \ | |
10610 // crx=cmpF_reg_reg
10611 //
10612 // with
10613 //
10614 // region src1 src2
10615 // \ | |
10616 // crx=cmpFUnordered_reg_reg
10617 // |
10618 // ^ region
10619 // | \
10620 // crx=cmov_bns_less
10621 //
10622
10623 // Create new nodes.
10624 MachNode *m1 = new cmpFUnordered_reg_regNode();
10625 MachNode *m2 = new cmov_bns_lessNode();
10626
10627 // inputs for new nodes
10628 m1->add_req(n_region, n_src1, n_src2);
10629 m2->add_req(n_region);
10630 m2->add_prec(m1);
10631
10632 // operands for new nodes
10633 m1->_opnds[0] = op_crx;
10634 m1->_opnds[1] = op_src1;
10635 m1->_opnds[2] = op_src2;
10636 m2->_opnds[0] = op_crx;
10637
10638 // registers for new nodes
10639 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10640 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10641
10642 // Insert new nodes.
10643 nodes->push(m1);
10644 nodes->push(m2);
10645 %}
10646 %}
10647
10648 // Compare float, generate -1,0,1
10649 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10650 match(Set dst (CmpF3 src1 src2));
10651 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10652
10653 expand %{
10654 flagsReg tmp1;
10655 cmpFUnordered_reg_reg(tmp1, src1, src2);
10656 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10657 %}
10658 %}
10659
10660 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10661 // no match-rule, false predicate
10662 effect(DEF crx, USE src1, USE src2);
10663 predicate(false);
10664
10665 format %{ "cmpFUrd $crx, $src1, $src2" %}
10666 size(4);
10667 ins_encode %{
10668 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10669 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10670 %}
10671 ins_pipe(pipe_class_default);
10672 %}
10673
10674 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10675 match(Set crx (CmpD src1 src2));
10676 ins_cost(DEFAULT_COST+BRANCH_COST);
10677
10678 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10679 postalloc_expand %{
10680 //
10681 // replaces
10682 //
10683 // region src1 src2
10684 // \ | |
10685 // crx=cmpD_reg_reg
10686 //
10687 // with
10688 //
10689 // region src1 src2
10690 // \ | |
10691 // crx=cmpDUnordered_reg_reg
10692 // |
10693 // ^ region
10694 // | \
10695 // crx=cmov_bns_less
10696 //
10697
10698 // create new nodes
10699 MachNode *m1 = new cmpDUnordered_reg_regNode();
10700 MachNode *m2 = new cmov_bns_lessNode();
10701
10702 // inputs for new nodes
10703 m1->add_req(n_region, n_src1, n_src2);
10704 m2->add_req(n_region);
10705 m2->add_prec(m1);
10706
10707 // operands for new nodes
10708 m1->_opnds[0] = op_crx;
10709 m1->_opnds[1] = op_src1;
10710 m1->_opnds[2] = op_src2;
10711 m2->_opnds[0] = op_crx;
10712
10713 // registers for new nodes
10714 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10715 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10716
10717 // Insert new nodes.
10718 nodes->push(m1);
10719 nodes->push(m2);
10720 %}
10721 %}
10722
10723 // Compare double, generate -1,0,1
10724 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10725 match(Set dst (CmpD3 src1 src2));
10726 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10727
10728 expand %{
10729 flagsReg tmp1;
10730 cmpDUnordered_reg_reg(tmp1, src1, src2);
10731 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10732 %}
10733 %}
10734
10735 //----------Branches---------------------------------------------------------
10736 // Jump
10737
10738 // Direct Branch.
10739 instruct branch(label labl) %{
10740 match(Goto);
10741 effect(USE labl);
10742 ins_cost(BRANCH_COST);
10743
10744 format %{ "B $labl" %}
10745 size(4);
10746 ins_encode %{
10747 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10748 Label d; // dummy
10749 __ bind(d);
10750 Label* p = $labl$$label;
10751 // `p' is `NULL' when this encoding class is used only to
10752 // determine the size of the encoded instruction.
10753 Label& l = (NULL == p)? d : *(p);
10754 __ b(l);
10755 %}
10756 ins_pipe(pipe_class_default);
10757 %}
10758
10759 // Conditional Near Branch
10760 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{
10761 // Same match rule as `branchConFar'.
10762 match(If cmp crx);
10763 effect(USE lbl);
10764 ins_cost(BRANCH_COST);
10765
10766 // If set to 1 this indicates that the current instruction is a
10767 // short variant of a long branch. This avoids using this
10768 // instruction in first-pass matching. It will then only be used in
10769 // the `Shorten_branches' pass.
10770 ins_short_branch(1);
10771
10772 format %{ "B$cmp $crx, $lbl" %}
10773 size(4);
10774 ins_encode( enc_bc(crx, cmp, lbl) );
10775 ins_pipe(pipe_class_default);
10776 %}
10777
10778 // This is for cases when the ppc64 `bc' instruction does not
10779 // reach far enough. So we emit a far branch here, which is more
10780 // expensive.
10781 //
10782 // Conditional Far Branch
10783 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{
10784 // Same match rule as `branchCon'.
10785 match(If cmp crx);
10786 effect(USE crx, USE lbl);
10787 predicate(!false /* TODO: PPC port HB_Schedule*/);
10788 // Higher cost than `branchCon'.
10789 ins_cost(5*BRANCH_COST);
10790
10791 // This is not a short variant of a branch, but the long variant.
10792 ins_short_branch(0);
10793
10794 format %{ "B_FAR$cmp $crx, $lbl" %}
10795 size(8);
10796 ins_encode( enc_bc_far(crx, cmp, lbl) );
10797 ins_pipe(pipe_class_default);
10798 %}
10799
10800 // Conditional Branch used with Power6 scheduler (can be far or short).
10801 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{
10802 // Same match rule as `branchCon'.
10803 match(If cmp crx);
10804 effect(USE crx, USE lbl);
10805 predicate(false /* TODO: PPC port HB_Schedule*/);
10806 // Higher cost than `branchCon'.
10807 ins_cost(5*BRANCH_COST);
10808
10809 // Actually size doesn't depend on alignment but on shortening.
10810 ins_variable_size_depending_on_alignment(true);
10811 // long variant.
10812 ins_short_branch(0);
10813
10814 format %{ "B_FAR$cmp $crx, $lbl" %}
10815 size(8); // worst case
10816 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10817 ins_pipe(pipe_class_default);
10818 %}
10819
10820 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{
10821 match(CountedLoopEnd cmp crx);
10822 effect(USE labl);
10823 ins_cost(BRANCH_COST);
10824
10825 // short variant.
10826 ins_short_branch(1);
10827
10828 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10829 size(4);
10830 ins_encode( enc_bc(crx, cmp, labl) );
10831 ins_pipe(pipe_class_default);
10832 %}
10833
10834 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{
10835 match(CountedLoopEnd cmp crx);
10836 effect(USE labl);
10837 predicate(!false /* TODO: PPC port HB_Schedule */);
10838 ins_cost(BRANCH_COST);
10839
10840 // Long variant.
10841 ins_short_branch(0);
10842
10843 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10844 size(8);
10845 ins_encode( enc_bc_far(crx, cmp, labl) );
10846 ins_pipe(pipe_class_default);
10847 %}
10848
10849 // Conditional Branch used with Power6 scheduler (can be far or short).
10850 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{
10851 match(CountedLoopEnd cmp crx);
10852 effect(USE labl);
10853 predicate(false /* TODO: PPC port HB_Schedule */);
10854 // Higher cost than `branchCon'.
10855 ins_cost(5*BRANCH_COST);
10856
10857 // Actually size doesn't depend on alignment but on shortening.
10858 ins_variable_size_depending_on_alignment(true);
10859 // Long variant.
10860 ins_short_branch(0);
10861
10862 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10863 size(8); // worst case
10864 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10865 ins_pipe(pipe_class_default);
10866 %}
10867
10868 // ============================================================================
10869 // Java runtime operations, intrinsics and other complex operations.
10870
10871 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10872 // array for an instance of the superklass. Set a hidden internal cache on a
10873 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10874 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10875 //
10876 // GL TODO: Improve this.
10877 // - result should not be a TEMP
10878 // - Add match rule as on sparc avoiding additional Cmp.
10879 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10880 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10881 match(Set result (PartialSubtypeCheck subklass superklass));
10882 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr);
10883 ins_cost(DEFAULT_COST*10);
10884
10885 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10886 ins_encode %{
10887 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10888 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10889 $tmp_klass$$Register, NULL, $result$$Register);
10890 %}
10891 ins_pipe(pipe_class_default);
10892 %}
10893
10894 // inlined locking and unlocking
10895
10896 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10897 match(Set crx (FastLock oop box));
10898 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10899 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking);
10900
10901 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10902 ins_encode %{
10903 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10904 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10905 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10906 // If locking was successfull, crx should indicate 'EQ'.
10907 // The compiler generates a branch to the runtime call to
10908 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10909 %}
10910 ins_pipe(pipe_class_compare);
10911 %}
10912
10913 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10914 match(Set crx (FastUnlock oop box));
10915 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10916
10917 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10918 ins_encode %{
10919 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10920 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10921 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10922 // If unlocking was successfull, crx should indicate 'EQ'.
10923 // The compiler generates a branch to the runtime call to
10924 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10925 %}
10926 ins_pipe(pipe_class_compare);
10927 %}
10928
10929 // Align address.
10930 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
10931 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
10932
10933 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
10934 size(4);
10935 ins_encode %{
10936 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10937 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
10938 %}
10939 ins_pipe(pipe_class_default);
10940 %}
10941
10942 // Array size computation.
10943 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
10944 match(Set dst (SubL (CastP2X end) (CastP2X start)));
10945
10946 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
10947 size(4);
10948 ins_encode %{
10949 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
10950 __ subf($dst$$Register, $start$$Register, $end$$Register);
10951 %}
10952 ins_pipe(pipe_class_default);
10953 %}
10954
10955 // Clear-array with dynamic array-size.
10956 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
10957 match(Set dummy (ClearArray cnt base));
10958 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
10959 ins_cost(MEMORY_REF_COST);
10960
10961 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10962
10963 format %{ "ClearArray $cnt, $base" %}
10964 ins_encode %{
10965 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10966 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
10967 %}
10968 ins_pipe(pipe_class_default);
10969 %}
10970
10971 // String_IndexOf for needle of length 1.
10972 //
10973 // Match needle into immediate operands: no loadConP node needed. Saves one
10974 // register and two instructions over string_indexOf_imm1Node.
10975 //
10976 // Assumes register result differs from all input registers.
10977 //
10978 // Preserves registers haystack, haycnt
10979 // Kills registers tmp1, tmp2
10980 // Defines registers result
10981 //
10982 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10983 //
10984 // Unfortunately this does not match too often. In many situations the AddP is used
10985 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
10986 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10987 immP needleImm, immL offsetImm, immI_1 needlecntImm,
10988 iRegIdst tmp1, iRegIdst tmp2,
10989 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
10990 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
10991 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
10992
10993 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
10994
10995 ins_cost(150);
10996 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
10997 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
10998
10999 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11000 ins_encode %{
11001 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11002 immPOper *needleOper = (immPOper *)$needleImm;
11003 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11004 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11005
11006 __ string_indexof_1($result$$Register,
11007 $haystack$$Register, $haycnt$$Register,
11008 R0, needle_values->char_at(0),
11009 $tmp1$$Register, $tmp2$$Register);
11010 %}
11011 ins_pipe(pipe_class_compare);
11012 %}
11013
11014 // String_IndexOf for needle of length 1.
11015 //
11016 // Special case requires less registers and emits less instructions.
11017 //
11018 // Assumes register result differs from all input registers.
11019 //
11020 // Preserves registers haystack, haycnt
11021 // Kills registers tmp1, tmp2, needle
11022 // Defines registers result
11023 //
11024 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11025 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11026 rscratch2RegP needle, immI_1 needlecntImm,
11027 iRegIdst tmp1, iRegIdst tmp2,
11028 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11029 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11030 effect(USE_KILL needle, /* TDEF needle, */ TEMP result,
11031 TEMP tmp1, TEMP tmp2);
11032 // Required for EA: check if it is still a type_array.
11033 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11034 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11035 ins_cost(180);
11036
11037 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11038
11039 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11040 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11041 ins_encode %{
11042 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11043 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11044 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11045 guarantee(needle_values, "sanity");
11046 if (needle_values != NULL) {
11047 __ string_indexof_1($result$$Register,
11048 $haystack$$Register, $haycnt$$Register,
11049 R0, needle_values->char_at(0),
11050 $tmp1$$Register, $tmp2$$Register);
11051 } else {
11052 __ string_indexof_1($result$$Register,
11053 $haystack$$Register, $haycnt$$Register,
11054 $needle$$Register, 0,
11055 $tmp1$$Register, $tmp2$$Register);
11056 }
11057 %}
11058 ins_pipe(pipe_class_compare);
11059 %}
11060
11061 // String_IndexOf.
11062 //
11063 // Length of needle as immediate. This saves instruction loading constant needle
11064 // length.
11065 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11066 // completely or do it in vector instruction. This should save registers for
11067 // needlecnt and needle.
11068 //
11069 // Assumes register result differs from all input registers.
11070 // Overwrites haycnt, needlecnt.
11071 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11072 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11073 iRegPsrc needle, uimmI15 needlecntImm,
11074 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11075 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11076 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11077 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result,
11078 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11079 // Required for EA: check if it is still a type_array.
11080 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11081 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11082 ins_cost(250);
11083
11084 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11085
11086 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11087 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11088 ins_encode %{
11089 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11090 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11091 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11092
11093 __ string_indexof($result$$Register,
11094 $haystack$$Register, $haycnt$$Register,
11095 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11096 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11097 %}
11098 ins_pipe(pipe_class_compare);
11099 %}
11100
11101 // StrIndexOf node.
11102 //
11103 // Assumes register result differs from all input registers.
11104 // Overwrites haycnt, needlecnt.
11105 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11106 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11107 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11108 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11109 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11110 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11111 TEMP result,
11112 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11113 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11114 ins_cost(300);
11115
11116 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11117
11118 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11119 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11120 ins_encode %{
11121 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11122 __ string_indexof($result$$Register,
11123 $haystack$$Register, $haycnt$$Register,
11124 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11125 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11126 %}
11127 ins_pipe(pipe_class_compare);
11128 %}
11129
11130 // String equals with immediate.
11131 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11132 iRegPdst tmp1, iRegPdst tmp2,
11133 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11134 match(Set result (StrEquals (Binary str1 str2) cntImm));
11135 effect(TEMP result, TEMP tmp1, TEMP tmp2,
11136 KILL cr0, KILL cr6, KILL ctr);
11137 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11138 ins_cost(250);
11139
11140 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11141
11142 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11143 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11144 ins_encode %{
11145 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11146 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11147 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11148 %}
11149 ins_pipe(pipe_class_compare);
11150 %}
11151
11152 // String equals.
11153 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11154 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11155 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11156 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11157 match(Set result (StrEquals (Binary str1 str2) cnt));
11158 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11159 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11160 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11161 ins_cost(300);
11162
11163 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11164
11165 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11166 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11167 ins_encode %{
11168 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11169 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11170 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11171 %}
11172 ins_pipe(pipe_class_compare);
11173 %}
11174
11175 // String compare.
11176 // Char[] pointers are passed in.
11177 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11178 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11179 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11180 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11181 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr);
11182 ins_cost(300);
11183
11184 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11185
11186 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11187 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11188 ins_encode %{
11189 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11190 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11191 $result$$Register, $tmp$$Register);
11192 %}
11193 ins_pipe(pipe_class_compare);
11194 %}
11195
11196 //---------- Min/Max Instructions ---------------------------------------------
11197
11198 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11199 match(Set dst (MinI src1 src2));
11200 ins_cost(DEFAULT_COST*6);
11201
11202 expand %{
11203 iRegLdst src1s;
11204 iRegLdst src2s;
11205 iRegLdst diff;
11206 iRegLdst sm;
11207 iRegLdst doz; // difference or zero
11208 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11209 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11210 subL_reg_reg(diff, src2s, src1s);
11211 // Need to consider >=33 bit result, therefore we need signmaskL.
11212 signmask64L_regL(sm, diff);
11213 andL_reg_reg(doz, diff, sm); // <=0
11214 addI_regL_regL(dst, doz, src1s);
11215 %}
11216 %}
11217
11218 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11219 match(Set dst (MaxI src1 src2));
11220 ins_cost(DEFAULT_COST*6);
11221
11222 expand %{
11223 iRegLdst src1s;
11224 iRegLdst src2s;
11225 iRegLdst diff;
11226 iRegLdst sm;
11227 iRegLdst doz; // difference or zero
11228 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11229 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11230 subL_reg_reg(diff, src2s, src1s);
11231 // Need to consider >=33 bit result, therefore we need signmaskL.
11232 signmask64L_regL(sm, diff);
11233 andcL_reg_reg(doz, diff, sm); // >=0
11234 addI_regL_regL(dst, doz, src1s);
11235 %}
11236 %}
11237
11238 //---------- Population Count Instructions ------------------------------------
11239
11240 // Popcnt for Power7.
11241 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11242 match(Set dst (PopCountI src));
11243 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11244 ins_cost(DEFAULT_COST);
11245
11246 format %{ "POPCNTW $dst, $src" %}
11247 size(4);
11248 ins_encode %{
11249 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11250 __ popcntw($dst$$Register, $src$$Register);
11251 %}
11252 ins_pipe(pipe_class_default);
11253 %}
11254
11255 // Popcnt for Power7.
11256 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11257 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11258 match(Set dst (PopCountL src));
11259 ins_cost(DEFAULT_COST);
11260
11261 format %{ "POPCNTD $dst, $src" %}
11262 size(4);
11263 ins_encode %{
11264 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11265 __ popcntd($dst$$Register, $src$$Register);
11266 %}
11267 ins_pipe(pipe_class_default);
11268 %}
11269
11270 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11271 match(Set dst (CountLeadingZerosI src));
11272 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11273 ins_cost(DEFAULT_COST);
11274
11275 format %{ "CNTLZW $dst, $src" %}
11276 size(4);
11277 ins_encode %{
11278 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11279 __ cntlzw($dst$$Register, $src$$Register);
11280 %}
11281 ins_pipe(pipe_class_default);
11282 %}
11283
11284 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11285 match(Set dst (CountLeadingZerosL src));
11286 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11287 ins_cost(DEFAULT_COST);
11288
11289 format %{ "CNTLZD $dst, $src" %}
11290 size(4);
11291 ins_encode %{
11292 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11293 __ cntlzd($dst$$Register, $src$$Register);
11294 %}
11295 ins_pipe(pipe_class_default);
11296 %}
11297
11298 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11299 // no match-rule, false predicate
11300 effect(DEF dst, USE src);
11301 predicate(false);
11302
11303 format %{ "CNTLZD $dst, $src" %}
11304 size(4);
11305 ins_encode %{
11306 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11307 __ cntlzd($dst$$Register, $src$$Register);
11308 %}
11309 ins_pipe(pipe_class_default);
11310 %}
11311
11312 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11313 match(Set dst (CountTrailingZerosI src));
11314 predicate(UseCountLeadingZerosInstructionsPPC64);
11315 ins_cost(DEFAULT_COST);
11316
11317 expand %{
11318 immI16 imm1 %{ (int)-1 %}
11319 immI16 imm2 %{ (int)32 %}
11320 immI_minus1 m1 %{ -1 %}
11321 iRegIdst tmpI1;
11322 iRegIdst tmpI2;
11323 iRegIdst tmpI3;
11324 addI_reg_imm16(tmpI1, src, imm1);
11325 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11326 countLeadingZerosI(tmpI3, tmpI2);
11327 subI_imm16_reg(dst, imm2, tmpI3);
11328 %}
11329 %}
11330
11331 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11332 match(Set dst (CountTrailingZerosL src));
11333 predicate(UseCountLeadingZerosInstructionsPPC64);
11334 ins_cost(DEFAULT_COST);
11335
11336 expand %{
11337 immL16 imm1 %{ (long)-1 %}
11338 immI16 imm2 %{ (int)64 %}
11339 iRegLdst tmpL1;
11340 iRegLdst tmpL2;
11341 iRegIdst tmpL3;
11342 addL_reg_imm16(tmpL1, src, imm1);
11343 andcL_reg_reg(tmpL2, tmpL1, src);
11344 countLeadingZerosL(tmpL3, tmpL2);
11345 subI_imm16_reg(dst, imm2, tmpL3);
11346 %}
11347 %}
11348
11349 // Expand nodes for byte_reverse_int.
11350 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11351 effect(DEF dst, USE src, USE pos, USE shift);
11352 predicate(false);
11353
11354 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11355 size(4);
11356 ins_encode %{
11357 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11358 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11359 %}
11360 ins_pipe(pipe_class_default);
11361 %}
11362
11363 // As insrwi_a, but with USE_DEF.
11364 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11365 effect(USE_DEF dst, USE src, USE pos, USE shift);
11366 predicate(false);
11367
11368 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11369 size(4);
11370 ins_encode %{
11371 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11372 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11373 %}
11374 ins_pipe(pipe_class_default);
11375 %}
11376
11377 // Just slightly faster than java implementation.
11378 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11379 match(Set dst (ReverseBytesI src));
11380 predicate(UseCountLeadingZerosInstructionsPPC64);
11381 ins_cost(DEFAULT_COST);
11382
11383 expand %{
11384 immI16 imm24 %{ (int) 24 %}
11385 immI16 imm16 %{ (int) 16 %}
11386 immI16 imm8 %{ (int) 8 %}
11387 immI16 imm4 %{ (int) 4 %}
11388 immI16 imm0 %{ (int) 0 %}
11389 iRegLdst tmpI1;
11390 iRegLdst tmpI2;
11391 iRegLdst tmpI3;
11392
11393 urShiftI_reg_imm(tmpI1, src, imm24);
11394 insrwi_a(dst, tmpI1, imm24, imm8);
11395 urShiftI_reg_imm(tmpI2, src, imm16);
11396 insrwi(dst, tmpI2, imm8, imm16);
11397 urShiftI_reg_imm(tmpI3, src, imm8);
11398 insrwi(dst, tmpI3, imm8, imm8);
11399 insrwi(dst, src, imm0, imm8);
11400 %}
11401 %}
11402
11403 //---------- Replicate Vector Instructions ------------------------------------
11404
11405 // Insrdi does replicate if src == dst.
11406 instruct repl32(iRegLdst dst) %{
11407 predicate(false);
11408 effect(USE_DEF dst);
11409
11410 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11411 size(4);
11412 ins_encode %{
11413 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11414 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11415 %}
11416 ins_pipe(pipe_class_default);
11417 %}
11418
11419 // Insrdi does replicate if src == dst.
11420 instruct repl48(iRegLdst dst) %{
11421 predicate(false);
11422 effect(USE_DEF dst);
11423
11424 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11425 size(4);
11426 ins_encode %{
11427 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11428 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11429 %}
11430 ins_pipe(pipe_class_default);
11431 %}
11432
11433 // Insrdi does replicate if src == dst.
11434 instruct repl56(iRegLdst dst) %{
11435 predicate(false);
11436 effect(USE_DEF dst);
11437
11438 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11439 size(4);
11440 ins_encode %{
11441 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11442 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11443 %}
11444 ins_pipe(pipe_class_default);
11445 %}
11446
11447 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11448 match(Set dst (ReplicateB src));
11449 predicate(n->as_Vector()->length() == 8);
11450 expand %{
11451 moveReg(dst, src);
11452 repl56(dst);
11453 repl48(dst);
11454 repl32(dst);
11455 %}
11456 %}
11457
11458 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11459 match(Set dst (ReplicateB zero));
11460 predicate(n->as_Vector()->length() == 8);
11461 format %{ "LI $dst, #0 \t// replicate8B" %}
11462 size(4);
11463 ins_encode %{
11464 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11465 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11466 %}
11467 ins_pipe(pipe_class_default);
11468 %}
11469
11470 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11471 match(Set dst (ReplicateB src));
11472 predicate(n->as_Vector()->length() == 8);
11473 format %{ "LI $dst, #-1 \t// replicate8B" %}
11474 size(4);
11475 ins_encode %{
11476 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11477 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11478 %}
11479 ins_pipe(pipe_class_default);
11480 %}
11481
11482 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11483 match(Set dst (ReplicateS src));
11484 predicate(n->as_Vector()->length() == 4);
11485 expand %{
11486 moveReg(dst, src);
11487 repl48(dst);
11488 repl32(dst);
11489 %}
11490 %}
11491
11492 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11493 match(Set dst (ReplicateS zero));
11494 predicate(n->as_Vector()->length() == 4);
11495 format %{ "LI $dst, #0 \t// replicate4C" %}
11496 size(4);
11497 ins_encode %{
11498 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11499 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11500 %}
11501 ins_pipe(pipe_class_default);
11502 %}
11503
11504 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11505 match(Set dst (ReplicateS src));
11506 predicate(n->as_Vector()->length() == 4);
11507 format %{ "LI $dst, -1 \t// replicate4C" %}
11508 size(4);
11509 ins_encode %{
11510 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11511 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11512 %}
11513 ins_pipe(pipe_class_default);
11514 %}
11515
11516 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11517 match(Set dst (ReplicateI src));
11518 predicate(n->as_Vector()->length() == 2);
11519 ins_cost(2 * DEFAULT_COST);
11520 expand %{
11521 moveReg(dst, src);
11522 repl32(dst);
11523 %}
11524 %}
11525
11526 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11527 match(Set dst (ReplicateI zero));
11528 predicate(n->as_Vector()->length() == 2);
11529 format %{ "LI $dst, #0 \t// replicate4C" %}
11530 size(4);
11531 ins_encode %{
11532 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11533 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11534 %}
11535 ins_pipe(pipe_class_default);
11536 %}
11537
11538 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11539 match(Set dst (ReplicateI src));
11540 predicate(n->as_Vector()->length() == 2);
11541 format %{ "LI $dst, -1 \t// replicate4C" %}
11542 size(4);
11543 ins_encode %{
11544 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11545 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11546 %}
11547 ins_pipe(pipe_class_default);
11548 %}
11549
11550 // Move float to int register via stack, replicate.
11551 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11552 match(Set dst (ReplicateF src));
11553 predicate(n->as_Vector()->length() == 2);
11554 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11555 expand %{
11556 stackSlotL tmpS;
11557 iRegIdst tmpI;
11558 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11559 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11560 moveReg(dst, tmpI); // Move int to long reg.
11561 repl32(dst); // Replicate bitpattern.
11562 %}
11563 %}
11564
11565 // Replicate scalar constant to packed float values in Double register
11566 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11567 match(Set dst (ReplicateF src));
11568 predicate(n->as_Vector()->length() == 2);
11569 ins_cost(5 * DEFAULT_COST);
11570
11571 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11572 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11573 %}
11574
11575 // Replicate scalar zero constant to packed float values in Double register
11576 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11577 match(Set dst (ReplicateF zero));
11578 predicate(n->as_Vector()->length() == 2);
11579
11580 format %{ "LI $dst, #0 \t// replicate2F" %}
11581 ins_encode %{
11582 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11583 __ li($dst$$Register, 0x0);
11584 %}
11585 ins_pipe(pipe_class_default);
11586 %}
11587
11588 // ============================================================================
11589 // Safepoint Instruction
11590
11591 instruct safePoint_poll(iRegPdst poll) %{
11592 match(SafePoint poll);
11593 predicate(LoadPollAddressFromThread);
11594
11595 // It caused problems to add the effect that r0 is killed, but this
11596 // effect no longer needs to be mentioned, since r0 is not contained
11597 // in a reg_class.
11598
11599 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11600 size(4);
11601 ins_encode( enc_poll(0x0, poll) );
11602 ins_pipe(pipe_class_default);
11603 %}
11604
11605 // Safepoint without per-thread support. Load address of page to poll
11606 // as constant.
11607 // Rscratch2RegP is R12.
11608 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11609 // a seperate node so that the oop map is at the right location.
11610 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11611 match(SafePoint poll);
11612 predicate(!LoadPollAddressFromThread);
11613
11614 // It caused problems to add the effect that r0 is killed, but this
11615 // effect no longer needs to be mentioned, since r0 is not contained
11616 // in a reg_class.
11617
11618 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11619 ins_encode( enc_poll(0x0, poll) );
11620 ins_pipe(pipe_class_default);
11621 %}
11622
11623 // ============================================================================
11624 // Call Instructions
11625
11626 // Call Java Static Instruction
11627
11628 // Schedulable version of call static node.
11629 instruct CallStaticJavaDirect(method meth) %{
11630 match(CallStaticJava);
11631 effect(USE meth);
11632 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11633 ins_cost(CALL_COST);
11634
11635 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11636
11637 format %{ "CALL,static $meth \t// ==> " %}
11638 size(4);
11639 ins_encode( enc_java_static_call(meth) );
11640 ins_pipe(pipe_class_call);
11641 %}
11642
11643 // Schedulable version of call static node.
11644 instruct CallStaticJavaDirectHandle(method meth) %{
11645 match(CallStaticJava);
11646 effect(USE meth);
11647 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11648 ins_cost(CALL_COST);
11649
11650 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11651
11652 format %{ "CALL,static $meth \t// ==> " %}
11653 ins_encode( enc_java_handle_call(meth) );
11654 ins_pipe(pipe_class_call);
11655 %}
11656
11657 // Call Java Dynamic Instruction
11658
11659 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11660 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11661 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11662 // The call destination must still be placed in the constant pool.
11663 instruct CallDynamicJavaDirectSched(method meth) %{
11664 match(CallDynamicJava); // To get all the data fields we need ...
11665 effect(USE meth);
11666 predicate(false); // ... but never match.
11667
11668 ins_field_load_ic_hi_node(loadConL_hiNode*);
11669 ins_field_load_ic_node(loadConLNode*);
11670 ins_num_consts(1 /* 1 patchable constant: call destination */);
11671
11672 format %{ "BL \t// dynamic $meth ==> " %}
11673 size(4);
11674 ins_encode( enc_java_dynamic_call_sched(meth) );
11675 ins_pipe(pipe_class_call);
11676 %}
11677
11678 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11679 // We use postalloc expanded calls if we use inline caches
11680 // and do not update method data.
11681 //
11682 // This instruction has two constants: inline cache (IC) and call destination.
11683 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11684 // one constant.
11685 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11686 match(CallDynamicJava);
11687 effect(USE meth);
11688 predicate(UseInlineCaches);
11689 ins_cost(CALL_COST);
11690
11691 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11692
11693 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11694 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11695 %}
11696
11697 // Compound version of call dynamic java
11698 // We use postalloc expanded calls if we use inline caches
11699 // and do not update method data.
11700 instruct CallDynamicJavaDirect(method meth) %{
11701 match(CallDynamicJava);
11702 effect(USE meth);
11703 predicate(!UseInlineCaches);
11704 ins_cost(CALL_COST);
11705
11706 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11707 ins_num_consts(4);
11708
11709 format %{ "CALL,dynamic $meth \t// ==> " %}
11710 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11711 ins_pipe(pipe_class_call);
11712 %}
11713
11714 // Call Runtime Instruction
11715
11716 instruct CallRuntimeDirect(method meth) %{
11717 match(CallRuntime);
11718 effect(USE meth);
11719 ins_cost(CALL_COST);
11720
11721 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11722 // env for callee, C-toc.
11723 ins_num_consts(3);
11724
11725 format %{ "CALL,runtime" %}
11726 ins_encode( enc_java_to_runtime_call(meth) );
11727 ins_pipe(pipe_class_call);
11728 %}
11729
11730 // Call Leaf
11731
11732 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11733 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11734 effect(DEF dst, USE src);
11735
11736 ins_num_consts(1);
11737
11738 format %{ "MTCTR $src" %}
11739 size(4);
11740 ins_encode( enc_leaf_call_mtctr(src) );
11741 ins_pipe(pipe_class_default);
11742 %}
11743
11744 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11745 instruct CallLeafDirect(method meth) %{
11746 match(CallLeaf); // To get the data all the data fields we need ...
11747 effect(USE meth);
11748 predicate(false); // but never match.
11749
11750 format %{ "BCTRL \t// leaf call $meth ==> " %}
11751 size(4);
11752 ins_encode %{
11753 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11754 __ bctrl();
11755 %}
11756 ins_pipe(pipe_class_call);
11757 %}
11758
11759 // postalloc expand of CallLeafDirect.
11760 // Load adress to call from TOC, then bl to it.
11761 instruct CallLeafDirect_Ex(method meth) %{
11762 match(CallLeaf);
11763 effect(USE meth);
11764 ins_cost(CALL_COST);
11765
11766 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11767 // env for callee, C-toc.
11768 ins_num_consts(3);
11769
11770 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11771 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11772 %}
11773
11774 // Call runtime without safepoint - same as CallLeaf.
11775 // postalloc expand of CallLeafNoFPDirect.
11776 // Load adress to call from TOC, then bl to it.
11777 instruct CallLeafNoFPDirect_Ex(method meth) %{
11778 match(CallLeafNoFP);
11779 effect(USE meth);
11780 ins_cost(CALL_COST);
11781
11782 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11783 // env for callee, C-toc.
11784 ins_num_consts(3);
11785
11786 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11787 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11788 %}
11789
11790 // Tail Call; Jump from runtime stub to Java code.
11791 // Also known as an 'interprocedural jump'.
11792 // Target of jump will eventually return to caller.
11793 // TailJump below removes the return address.
11794 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11795 match(TailCall jump_target method_oop);
11796 ins_cost(CALL_COST);
11797
11798 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11799 "BCTR \t// tail call" %}
11800 size(8);
11801 ins_encode %{
11802 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11803 __ mtctr($jump_target$$Register);
11804 __ bctr();
11805 %}
11806 ins_pipe(pipe_class_call);
11807 %}
11808
11809 // Return Instruction
11810 instruct Ret() %{
11811 match(Return);
11812 format %{ "BLR \t// branch to link register" %}
11813 size(4);
11814 ins_encode %{
11815 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11816 // LR is restored in MachEpilogNode. Just do the RET here.
11817 __ blr();
11818 %}
11819 ins_pipe(pipe_class_default);
11820 %}
11821
11822 // Tail Jump; remove the return address; jump to target.
11823 // TailCall above leaves the return address around.
11824 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11825 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11826 // "restore" before this instruction (in Epilogue), we need to materialize it
11827 // in %i0.
11828 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11829 match(TailJump jump_target ex_oop);
11830 ins_cost(CALL_COST);
11831
11832 format %{ "LD R4_ARG2 = LR\n\t"
11833 "MTCTR $jump_target\n\t"
11834 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11835 size(12);
11836 ins_encode %{
11837 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11838 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11839 __ mtctr($jump_target$$Register);
11840 __ bctr();
11841 %}
11842 ins_pipe(pipe_class_call);
11843 %}
11844
11845 // Create exception oop: created by stack-crawling runtime code.
11846 // Created exception is now available to this handler, and is setup
11847 // just prior to jumping to this handler. No code emitted.
11848 instruct CreateException(rarg1RegP ex_oop) %{
11849 match(Set ex_oop (CreateEx));
11850 ins_cost(0);
11851
11852 format %{ " -- \t// exception oop; no code emitted" %}
11853 size(0);
11854 ins_encode( /*empty*/ );
11855 ins_pipe(pipe_class_default);
11856 %}
11857
11858 // Rethrow exception: The exception oop will come in the first
11859 // argument position. Then JUMP (not call) to the rethrow stub code.
11860 instruct RethrowException() %{
11861 match(Rethrow);
11862 ins_cost(CALL_COST);
11863
11864 format %{ "Jmp rethrow_stub" %}
11865 ins_encode %{
11866 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11867 cbuf.set_insts_mark();
11868 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
11869 %}
11870 ins_pipe(pipe_class_call);
11871 %}
11872
11873 // Die now.
11874 instruct ShouldNotReachHere() %{
11875 match(Halt);
11876 ins_cost(CALL_COST);
11877
11878 format %{ "ShouldNotReachHere" %}
11879 size(4);
11880 ins_encode %{
11881 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11882 __ trap_should_not_reach_here();
11883 %}
11884 ins_pipe(pipe_class_default);
11885 %}
11886
11887 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
11888 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
11889 // Get a DEF on threadRegP, no costs, no encoding, use
11890 // 'ins_should_rematerialize(true)' to avoid spilling.
11891 instruct tlsLoadP(threadRegP dst) %{
11892 match(Set dst (ThreadLocal));
11893 ins_cost(0);
11894
11895 ins_should_rematerialize(true);
11896
11897 format %{ " -- \t// $dst=Thread::current(), empty" %}
11898 size(0);
11899 ins_encode( /*empty*/ );
11900 ins_pipe(pipe_class_empty);
11901 %}
11902
11903 //---Some PPC specific nodes---------------------------------------------------
11904
11905 // Stop a group.
11906 instruct endGroup() %{
11907 ins_cost(0);
11908
11909 ins_is_nop(true);
11910
11911 format %{ "End Bundle (ori r1, r1, 0)" %}
11912 size(4);
11913 ins_encode %{
11914 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
11915 __ endgroup();
11916 %}
11917 ins_pipe(pipe_class_default);
11918 %}
11919
11920 // Nop instructions
11921
11922 instruct fxNop() %{
11923 ins_cost(0);
11924
11925 ins_is_nop(true);
11926
11927 format %{ "fxNop" %}
11928 size(4);
11929 ins_encode %{
11930 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11931 __ nop();
11932 %}
11933 ins_pipe(pipe_class_default);
11934 %}
11935
11936 instruct fpNop0() %{
11937 ins_cost(0);
11938
11939 ins_is_nop(true);
11940
11941 format %{ "fpNop0" %}
11942 size(4);
11943 ins_encode %{
11944 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11945 __ fpnop0();
11946 %}
11947 ins_pipe(pipe_class_default);
11948 %}
11949
11950 instruct fpNop1() %{
11951 ins_cost(0);
11952
11953 ins_is_nop(true);
11954
11955 format %{ "fpNop1" %}
11956 size(4);
11957 ins_encode %{
11958 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11959 __ fpnop1();
11960 %}
11961 ins_pipe(pipe_class_default);
11962 %}
11963
11964 instruct brNop0() %{
11965 ins_cost(0);
11966 size(4);
11967 format %{ "brNop0" %}
11968 ins_encode %{
11969 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11970 __ brnop0();
11971 %}
11972 ins_is_nop(true);
11973 ins_pipe(pipe_class_default);
11974 %}
11975
11976 instruct brNop1() %{
11977 ins_cost(0);
11978
11979 ins_is_nop(true);
11980
11981 format %{ "brNop1" %}
11982 size(4);
11983 ins_encode %{
11984 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11985 __ brnop1();
11986 %}
11987 ins_pipe(pipe_class_default);
11988 %}
11989
11990 instruct brNop2() %{
11991 ins_cost(0);
11992
11993 ins_is_nop(true);
11994
11995 format %{ "brNop2" %}
11996 size(4);
11997 ins_encode %{
11998 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11999 __ brnop2();
12000 %}
12001 ins_pipe(pipe_class_default);
12002 %}
12003
12004 //----------PEEPHOLE RULES-----------------------------------------------------
12005 // These must follow all instruction definitions as they use the names
12006 // defined in the instructions definitions.
12007 //
12008 // peepmatch ( root_instr_name [preceeding_instruction]* );
12009 //
12010 // peepconstraint %{
12011 // (instruction_number.operand_name relational_op instruction_number.operand_name
12012 // [, ...] );
12013 // // instruction numbers are zero-based using left to right order in peepmatch
12014 //
12015 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12016 // // provide an instruction_number.operand_name for each operand that appears
12017 // // in the replacement instruction's match rule
12018 //
12019 // ---------VM FLAGS---------------------------------------------------------
12020 //
12021 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12022 //
12023 // Each peephole rule is given an identifying number starting with zero and
12024 // increasing by one in the order seen by the parser. An individual peephole
12025 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12026 // on the command-line.
12027 //
12028 // ---------CURRENT LIMITATIONS----------------------------------------------
12029 //
12030 // Only match adjacent instructions in same basic block
12031 // Only equality constraints
12032 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12033 // Only one replacement instruction
12034 //
12035 // ---------EXAMPLE----------------------------------------------------------
12036 //
12037 // // pertinent parts of existing instructions in architecture description
12038 // instruct movI(eRegI dst, eRegI src) %{
12039 // match(Set dst (CopyI src));
12040 // %}
12041 //
12042 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12043 // match(Set dst (AddI dst src));
12044 // effect(KILL cr);
12045 // %}
12046 //
12047 // // Change (inc mov) to lea
12048 // peephole %{
12049 // // increment preceeded by register-register move
12050 // peepmatch ( incI_eReg movI );
12051 // // require that the destination register of the increment
12052 // // match the destination register of the move
12053 // peepconstraint ( 0.dst == 1.dst );
12054 // // construct a replacement instruction that sets
12055 // // the destination to ( move's source register + one )
12056 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12057 // %}
12058 //
12059 // Implementation no longer uses movX instructions since
12060 // machine-independent system no longer uses CopyX nodes.
12061 //
12062 // peephole %{
12063 // peepmatch ( incI_eReg movI );
12064 // peepconstraint ( 0.dst == 1.dst );
12065 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12066 // %}
12067 //
12068 // peephole %{
12069 // peepmatch ( decI_eReg movI );
12070 // peepconstraint ( 0.dst == 1.dst );
12071 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12072 // %}
12073 //
12074 // peephole %{
12075 // peepmatch ( addI_eReg_imm movI );
12076 // peepconstraint ( 0.dst == 1.dst );
12077 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12078 // %}
12079 //
12080 // peephole %{
12081 // peepmatch ( addP_eReg_imm movP );
12082 // peepconstraint ( 0.dst == 1.dst );
12083 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12084 // %}
12085
12086 // // Change load of spilled value to only a spill
12087 // instruct storeI(memory mem, eRegI src) %{
12088 // match(Set mem (StoreI mem src));
12089 // %}
12090 //
12091 // instruct loadI(eRegI dst, memory mem) %{
12092 // match(Set dst (LoadI mem));
12093 // %}
12094 //
12095 peephole %{
12096 peepmatch ( loadI storeI );
12097 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12098 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12099 %}
12100
12101 peephole %{
12102 peepmatch ( loadL storeL );
12103 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12104 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12105 %}
12106
12107 peephole %{
12108 peepmatch ( loadP storeP );
12109 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12110 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12111 %}
12112
12113 //----------SMARTSPILL RULES---------------------------------------------------
12114 // These must follow all instruction definitions as they use the names
12115 // defined in the instructions definitions.