3587 disp(0x0);
3588 %}
3589 %}
3590
3591 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3592 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3593 %{
3594 constraint(ALLOC_IN_RC(ptr_reg));
3595 match(AddP (AddP reg (LShiftL lreg scale)) off);
3596
3597 op_cost(10);
3598 format %{"[$reg + $off + $lreg << $scale]" %}
3599 interface(MEMORY_INTER) %{
3600 base($reg);
3601 index($lreg);
3602 scale($scale);
3603 disp($off);
3604 %}
3605 %}
3606
3607 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3608 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3609 %{
3610 constraint(ALLOC_IN_RC(ptr_reg));
3611 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3612 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3613
3614 op_cost(10);
3615 format %{"[$reg + $off + $idx << $scale]" %}
3616 interface(MEMORY_INTER) %{
3617 base($reg);
3618 index($idx);
3619 scale($scale);
3620 disp($off);
3621 %}
3622 %}
3623
3624 // Indirect Narrow Oop Plus Offset Operand
3625 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3626 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3738 %}
3739 %}
3740
3741 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3742 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3743 %{
3744 predicate(Universe::narrow_oop_shift() == 0);
3745 constraint(ALLOC_IN_RC(ptr_reg));
3746 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3747
3748 op_cost(10);
3749 format %{"[$reg + $off + $lreg << $scale]" %}
3750 interface(MEMORY_INTER) %{
3751 base($reg);
3752 index($lreg);
3753 scale($scale);
3754 disp($off);
3755 %}
3756 %}
3757
3758 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3759 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3760 %{
3761 constraint(ALLOC_IN_RC(ptr_reg));
3762 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3763 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
3764
3765 op_cost(10);
3766 format %{"[$reg + $off + $idx << $scale]" %}
3767 interface(MEMORY_INTER) %{
3768 base($reg);
3769 index($idx);
3770 scale($scale);
3771 disp($off);
3772 %}
3773 %}
3774
3775 //----------Special Memory Operands--------------------------------------------
3776 // Stack Slot Operand - This operand is used for loading and storing temporary
3777 // values on the stack where a match requires a value to
3929 equal(0x4, "e");
3930 not_equal(0x5, "ne");
3931 less(0x2, "b");
3932 greater_equal(0x3, "nb");
3933 less_equal(0x6, "be");
3934 greater(0x7, "nbe");
3935 overflow(0x0, "o");
3936 no_overflow(0x1, "no");
3937 %}
3938 %}
3939
3940
3941 //----------OPERAND CLASSES----------------------------------------------------
3942 // Operand Classes are groups of operands that are used as to simplify
3943 // instruction definitions by not requiring the AD writer to specify separate
3944 // instructions for every form of operand when the instruction accepts
3945 // multiple operand types with the same basic encoding and format. The classic
3946 // case of this is memory operands.
3947
3948 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
3949 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
3950 indCompressedOopOffset,
3951 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
3952 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
3953 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
3954
3955 //----------PIPELINE-----------------------------------------------------------
3956 // Rules which define the behavior of the target architectures pipeline.
3957 pipeline %{
3958
3959 //----------ATTRIBUTES---------------------------------------------------------
3960 attributes %{
3961 variable_size_instructions; // Fixed size instructions
3962 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
3963 instruction_unit_size = 1; // An instruction is 1 bytes long
3964 instruction_fetch_unit_size = 16; // The processor fetches one line
3965 instruction_fetch_units = 1; // of 16 bytes
3966
3967 // List of nop instructions
3968 nops( MachNop );
3969 %}
3970
3971 //----------RESOURCES----------------------------------------------------------
3972 // Resources are the functional units available to the machine
3973
4967 match(Set dst mem);
4968
4969 ins_cost(110);
4970 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
4971 opcode(0x8D);
4972 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4973 ins_pipe(ialu_reg_reg_fat);
4974 %}
4975
4976 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
4977 %{
4978 match(Set dst mem);
4979
4980 ins_cost(110);
4981 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
4982 opcode(0x8D);
4983 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4984 ins_pipe(ialu_reg_reg_fat);
4985 %}
4986
4987 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
4988 %{
4989 match(Set dst mem);
4990
4991 ins_cost(110);
4992 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
4993 opcode(0x8D);
4994 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4995 ins_pipe(ialu_reg_reg_fat);
4996 %}
4997
4998 // Load Effective Address which uses Narrow (32-bits) oop
4999 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5000 %{
5001 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5002 match(Set dst mem);
5003
5004 ins_cost(110);
5005 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5006 opcode(0x8D);
5046
5047 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5048 %{
5049 predicate(Universe::narrow_oop_shift() == 0);
5050 match(Set dst mem);
5051
5052 ins_cost(110);
5053 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5054 opcode(0x8D);
5055 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5056 ins_pipe(ialu_reg_reg_fat);
5057 %}
5058
5059 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5060 %{
5061 predicate(Universe::narrow_oop_shift() == 0);
5062 match(Set dst mem);
5063
5064 ins_cost(110);
5065 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5066 opcode(0x8D);
5067 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5068 ins_pipe(ialu_reg_reg_fat);
5069 %}
5070
5071 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5072 %{
5073 predicate(Universe::narrow_oop_shift() == 0);
5074 match(Set dst mem);
5075
5076 ins_cost(110);
5077 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5078 opcode(0x8D);
5079 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5080 ins_pipe(ialu_reg_reg_fat);
5081 %}
5082
5083 instruct loadConI(rRegI dst, immI src)
5084 %{
5085 match(Set dst src);
|
3587 disp(0x0);
3588 %}
3589 %}
3590
3591 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3592 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3593 %{
3594 constraint(ALLOC_IN_RC(ptr_reg));
3595 match(AddP (AddP reg (LShiftL lreg scale)) off);
3596
3597 op_cost(10);
3598 format %{"[$reg + $off + $lreg << $scale]" %}
3599 interface(MEMORY_INTER) %{
3600 base($reg);
3601 index($lreg);
3602 scale($scale);
3603 disp($off);
3604 %}
3605 %}
3606
3607 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3608 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3609 %{
3610 constraint(ALLOC_IN_RC(ptr_reg));
3611 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3612 match(AddP (AddP reg (ConvI2L idx)) off);
3613
3614 op_cost(10);
3615 format %{"[$reg + $off + $idx]" %}
3616 interface(MEMORY_INTER) %{
3617 base($reg);
3618 index($idx);
3619 scale(0x0);
3620 disp($off);
3621 %}
3622 %}
3623
3624 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3625 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3626 %{
3627 constraint(ALLOC_IN_RC(ptr_reg));
3628 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3629 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3630
3631 op_cost(10);
3632 format %{"[$reg + $off + $idx << $scale]" %}
3633 interface(MEMORY_INTER) %{
3634 base($reg);
3635 index($idx);
3636 scale($scale);
3637 disp($off);
3638 %}
3639 %}
3640
3641 // Indirect Narrow Oop Plus Offset Operand
3642 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3643 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3755 %}
3756 %}
3757
3758 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3759 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3760 %{
3761 predicate(Universe::narrow_oop_shift() == 0);
3762 constraint(ALLOC_IN_RC(ptr_reg));
3763 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3764
3765 op_cost(10);
3766 format %{"[$reg + $off + $lreg << $scale]" %}
3767 interface(MEMORY_INTER) %{
3768 base($reg);
3769 index($lreg);
3770 scale($scale);
3771 disp($off);
3772 %}
3773 %}
3774
3775 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
3776 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
3777 %{
3778 constraint(ALLOC_IN_RC(ptr_reg));
3779 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3780 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
3781
3782 op_cost(10);
3783 format %{"[$reg + $off + $idx]" %}
3784 interface(MEMORY_INTER) %{
3785 base($reg);
3786 index($idx);
3787 scale(0x0);
3788 disp($off);
3789 %}
3790 %}
3791
3792 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3793 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3794 %{
3795 constraint(ALLOC_IN_RC(ptr_reg));
3796 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3797 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
3798
3799 op_cost(10);
3800 format %{"[$reg + $off + $idx << $scale]" %}
3801 interface(MEMORY_INTER) %{
3802 base($reg);
3803 index($idx);
3804 scale($scale);
3805 disp($off);
3806 %}
3807 %}
3808
3809 //----------Special Memory Operands--------------------------------------------
3810 // Stack Slot Operand - This operand is used for loading and storing temporary
3811 // values on the stack where a match requires a value to
3963 equal(0x4, "e");
3964 not_equal(0x5, "ne");
3965 less(0x2, "b");
3966 greater_equal(0x3, "nb");
3967 less_equal(0x6, "be");
3968 greater(0x7, "nbe");
3969 overflow(0x0, "o");
3970 no_overflow(0x1, "no");
3971 %}
3972 %}
3973
3974
3975 //----------OPERAND CLASSES----------------------------------------------------
3976 // Operand Classes are groups of operands that are used as to simplify
3977 // instruction definitions by not requiring the AD writer to specify separate
3978 // instructions for every form of operand when the instruction accepts
3979 // multiple operand types with the same basic encoding and format. The classic
3980 // case of this is memory operands.
3981
3982 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
3983 indIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
3984 indCompressedOopOffset,
3985 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
3986 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
3987 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
3988
3989 //----------PIPELINE-----------------------------------------------------------
3990 // Rules which define the behavior of the target architectures pipeline.
3991 pipeline %{
3992
3993 //----------ATTRIBUTES---------------------------------------------------------
3994 attributes %{
3995 variable_size_instructions; // Fixed size instructions
3996 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
3997 instruction_unit_size = 1; // An instruction is 1 bytes long
3998 instruction_fetch_unit_size = 16; // The processor fetches one line
3999 instruction_fetch_units = 1; // of 16 bytes
4000
4001 // List of nop instructions
4002 nops( MachNop );
4003 %}
4004
4005 //----------RESOURCES----------------------------------------------------------
4006 // Resources are the functional units available to the machine
4007
5001 match(Set dst mem);
5002
5003 ins_cost(110);
5004 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5005 opcode(0x8D);
5006 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5007 ins_pipe(ialu_reg_reg_fat);
5008 %}
5009
5010 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5011 %{
5012 match(Set dst mem);
5013
5014 ins_cost(110);
5015 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5016 opcode(0x8D);
5017 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5018 ins_pipe(ialu_reg_reg_fat);
5019 %}
5020
5021 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5022 %{
5023 match(Set dst mem);
5024
5025 ins_cost(110);
5026 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5027 opcode(0x8D);
5028 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5029 ins_pipe(ialu_reg_reg_fat);
5030 %}
5031
5032 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5033 %{
5034 match(Set dst mem);
5035
5036 ins_cost(110);
5037 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5038 opcode(0x8D);
5039 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5040 ins_pipe(ialu_reg_reg_fat);
5041 %}
5042
5043 // Load Effective Address which uses Narrow (32-bits) oop
5044 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5045 %{
5046 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5047 match(Set dst mem);
5048
5049 ins_cost(110);
5050 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5051 opcode(0x8D);
5091
5092 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5093 %{
5094 predicate(Universe::narrow_oop_shift() == 0);
5095 match(Set dst mem);
5096
5097 ins_cost(110);
5098 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5099 opcode(0x8D);
5100 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5101 ins_pipe(ialu_reg_reg_fat);
5102 %}
5103
5104 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5105 %{
5106 predicate(Universe::narrow_oop_shift() == 0);
5107 match(Set dst mem);
5108
5109 ins_cost(110);
5110 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5111 opcode(0x8D);
5112 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5113 ins_pipe(ialu_reg_reg_fat);
5114 %}
5115
5116 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5117 %{
5118 predicate(Universe::narrow_oop_shift() == 0);
5119 match(Set dst mem);
5120
5121 ins_cost(110);
5122 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5123 opcode(0x8D);
5124 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5125 ins_pipe(ialu_reg_reg_fat);
5126 %}
5127
5128 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5129 %{
5130 predicate(Universe::narrow_oop_shift() == 0);
5131 match(Set dst mem);
5132
5133 ins_cost(110);
5134 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5135 opcode(0x8D);
5136 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5137 ins_pipe(ialu_reg_reg_fat);
5138 %}
5139
5140 instruct loadConI(rRegI dst, immI src)
5141 %{
5142 match(Set dst src);
|