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src/cpu/aarch64/vm/aarch64.ad
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@@ -1816,10 +1816,12 @@
switch (opcode) {
case INDINDEXSCALEDOFFSETI2L:
case INDINDEXSCALEDI2L:
case INDINDEXSCALEDOFFSETI2LN:
case INDINDEXSCALEDI2LN:
+ case INDINDEXOFFSETI2L:
+ case INDINDEXOFFSETI2LN:
scale = Address::sxtw(size);
break;
default:
scale = Address::lsl(size);
}
@@ -4262,10 +4264,24 @@
scale($scale);
disp($off);
%}
%}
+operand indIndexOffsetI2L(iRegP reg, iRegI ireg, immLU12 off)
+%{
+ constraint(ALLOC_IN_RC(ptr_reg));
+ match(AddP (AddP reg (ConvI2L ireg)) off);
+ op_cost(INSN_COST);
+ format %{ "$reg, $ireg, $off I2L" %}
+ interface(MEMORY_INTER) %{
+ base($reg);
+ index($ireg);
+ scale(0x0);
+ disp($off);
+ %}
+%}
+
operand indIndexScaledOffsetI2L(iRegP reg, iRegI ireg, immIScale scale, immLU12 off)
%{
constraint(ALLOC_IN_RC(ptr_reg));
match(AddP (AddP reg (LShiftL (ConvI2L ireg) scale)) off);
op_cost(INSN_COST);
@@ -4392,10 +4408,25 @@
scale($scale);
disp($off);
%}
%}
+operand indIndexOffsetI2LN(iRegN reg, iRegI ireg, immLU12 off)
+%{
+ predicate(Universe::narrow_oop_shift() == 0);
+ constraint(ALLOC_IN_RC(ptr_reg));
+ match(AddP (AddP (DecodeN reg) (ConvI2L ireg)) off);
+ op_cost(INSN_COST);
+ format %{ "$reg, $ireg, $off I2L\t# narrow" %}
+ interface(MEMORY_INTER) %{
+ base($reg);
+ index($ireg);
+ scale(0x0);
+ disp($off);
+ %}
+%}
+
operand indIndexScaledOffsetI2LN(iRegN reg, iRegI ireg, immIScale scale, immLU12 off)
%{
predicate(Universe::narrow_oop_shift() == 0);
constraint(ALLOC_IN_RC(ptr_reg));
match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L ireg) scale)) off);
@@ -4654,12 +4685,12 @@
// encoding and format. The classic case of this is memory operands.
// memory is used to define read/write location for load/store
// instruction defs. we can turn a memory op into an Address
-opclass memory(indirect, indIndexScaledOffsetI, indIndexScaledOffsetL, indIndexScaledOffsetI2L, indIndexScaled, indIndexScaledI2L, indIndex, indOffI, indOffL,
- indirectN, indIndexScaledOffsetIN, indIndexScaledOffsetLN, indIndexScaledOffsetI2LN, indIndexScaledN, indIndexScaledI2LN, indIndexN, indOffIN, indOffLN);
+opclass memory(indirect, indIndexScaledOffsetI, indIndexScaledOffsetL, indIndexOffsetI2L, indIndexScaledOffsetI2L, indIndexScaled, indIndexScaledI2L, indIndex, indOffI, indOffL,
+ indirectN, indIndexScaledOffsetIN, indIndexScaledOffsetLN, indIndexOffsetI2LN, indIndexScaledOffsetI2LN, indIndexScaledN, indIndexScaledI2LN, indIndexN, indOffIN, indOffLN);
// iRegIorL2I is used for src inputs in rules for 32 bit int (I)
// operations. it allows the src to be either an iRegI or a (ConvL2I
// iRegL). in the latter case the l2i normally planted for a ConvL2I
@@ -7521,11 +7552,11 @@
%}
instruct addP_reg_reg_ext(iRegPNoSp dst, iRegP src1, iRegIorL2I src2) %{
match(Set dst (AddP src1 (ConvI2L src2)));
- ins_cost(INSN_COST);
+ ins_cost(1.9 * INSN_COST);
format %{ "add $dst, $src1, $src2, sxtw\t# ptr" %}
ins_encode %{
__ add(as_Register($dst$$reg),
as_Register($src1$$reg),
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