src/cpu/x86/vm/x86_64.ad

*** 3602,3611 ****
--- 3602,3628 ----
      scale($scale);
      disp($off);
    %}
  %}
  
+ // Indirect Memory Plus Positive Index Register Plus Offset Operand
+ operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
+ %{
+   constraint(ALLOC_IN_RC(ptr_reg));
+   predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
+   match(AddP (AddP reg (ConvI2L idx)) off);
+ 
+   op_cost(10);
+   format %{"[$reg + $off + $idx]" %}
+   interface(MEMORY_INTER) %{
+     base($reg);
+     index($idx);
+     scale(0x0);
+     disp($off);
+   %}
+ %}
+ 
  // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
  operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
  %{
    constraint(ALLOC_IN_RC(ptr_reg));
    predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
*** 3753,3762 ****
--- 3770,3796 ----
      scale($scale);
      disp($off);
    %}
  %}
  
+ // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
+ operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
+ %{
+   constraint(ALLOC_IN_RC(ptr_reg));
+   predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
+   match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
+ 
+   op_cost(10);
+   format %{"[$reg + $off + $idx]" %}
+   interface(MEMORY_INTER) %{
+     base($reg);
+     index($idx);
+     scale(0x0);
+     disp($off);
+   %}
+ %}
+ 
  // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
  operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
  %{
    constraint(ALLOC_IN_RC(ptr_reg));
    predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
*** 3944,3958 ****
  // instructions for every form of operand when the instruction accepts
  // multiple operand types with the same basic encoding and format.  The classic
  // case of this is memory operands.
  
  opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
!                indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
                 indCompressedOopOffset,
                 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
                 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
!                indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
  
  //----------PIPELINE-----------------------------------------------------------
  // Rules which define the behavior of the target architectures pipeline.
  pipeline %{
  
--- 3978,3992 ----
  // instructions for every form of operand when the instruction accepts
  // multiple operand types with the same basic encoding and format.  The classic
  // case of this is memory operands.
  
  opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
!                indIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
                 indCompressedOopOffset,
                 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
                 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
!                indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
  
  //----------PIPELINE-----------------------------------------------------------
  // Rules which define the behavior of the target architectures pipeline.
  pipeline %{
  
*** 4982,4991 ****
--- 5016,5036 ----
    opcode(0x8D);
    ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
    ins_pipe(ialu_reg_reg_fat);
  %}
  
+ instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
+ %{
+   match(Set dst mem);
+ 
+   ins_cost(110);
+   format %{ "leaq    $dst, $mem\t# ptr posidxoff" %}
+   opcode(0x8D);
+   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
+   ins_pipe(ialu_reg_reg_fat);
+ %}
+ 
  instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
  %{
    match(Set dst mem);
  
    ins_cost(110);
*** 5066,5075 ****
--- 5111,5132 ----
    opcode(0x8D);
    ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
    ins_pipe(ialu_reg_reg_fat);
  %}
  
+ instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
+ %{
+   predicate(Universe::narrow_oop_shift() == 0);
+   match(Set dst mem);
+ 
+   ins_cost(110);
+   format %{ "leaq    $dst, $mem\t# ptr posidxoffnarrow" %}
+   opcode(0x8D);
+   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
+   ins_pipe(ialu_reg_reg_fat);
+ %}
+ 
  instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
  %{
    predicate(Universe::narrow_oop_shift() == 0);
    match(Set dst mem);