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src/cpu/aarch64/vm/aarch64.ad

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4307 %}
4308 
4309 operand indIndex(iRegP reg, iRegL lreg)
4310 %{
4311   constraint(ALLOC_IN_RC(ptr_reg));
4312   match(AddP reg lreg);
4313   op_cost(0);
4314   format %{ "$reg, $lreg" %}
4315   interface(MEMORY_INTER) %{
4316     base($reg);
4317     index($lreg);
4318     scale(0x0);
4319     disp(0x0);
4320   %}
4321 %}
4322 
4323 operand indOffI(iRegP reg, immIOffset off)
4324 %{
4325   constraint(ALLOC_IN_RC(ptr_reg));
4326   match(AddP reg off);
4327   op_cost(INSN_COST);
4328   format %{ "[$reg, $off]" %}
4329   interface(MEMORY_INTER) %{
4330     base($reg);
4331     index(0xffffffff);
4332     scale(0x0);
4333     disp($off);
4334   %}
4335 %}
4336 
4337 operand indOffL(iRegP reg, immLoffset off)
4338 %{
4339   constraint(ALLOC_IN_RC(ptr_reg));
4340   match(AddP reg off);
4341   op_cost(0);
4342   format %{ "[$reg, $off]" %}
4343   interface(MEMORY_INTER) %{
4344     base($reg);
4345     index(0xffffffff);
4346     scale(0x0);
4347     disp($off);




4307 %}
4308 
4309 operand indIndex(iRegP reg, iRegL lreg)
4310 %{
4311   constraint(ALLOC_IN_RC(ptr_reg));
4312   match(AddP reg lreg);
4313   op_cost(0);
4314   format %{ "$reg, $lreg" %}
4315   interface(MEMORY_INTER) %{
4316     base($reg);
4317     index($lreg);
4318     scale(0x0);
4319     disp(0x0);
4320   %}
4321 %}
4322 
4323 operand indOffI(iRegP reg, immIOffset off)
4324 %{
4325   constraint(ALLOC_IN_RC(ptr_reg));
4326   match(AddP reg off);
4327   op_cost(0);
4328   format %{ "[$reg, $off]" %}
4329   interface(MEMORY_INTER) %{
4330     base($reg);
4331     index(0xffffffff);
4332     scale(0x0);
4333     disp($off);
4334   %}
4335 %}
4336 
4337 operand indOffL(iRegP reg, immLoffset off)
4338 %{
4339   constraint(ALLOC_IN_RC(ptr_reg));
4340   match(AddP reg off);
4341   op_cost(0);
4342   format %{ "[$reg, $off]" %}
4343   interface(MEMORY_INTER) %{
4344     base($reg);
4345     index(0xffffffff);
4346     scale(0x0);
4347     disp($off);


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