1 // 2 // Copyright (c) 1998, 2015, Oracle and/or its affiliates. All rights reserved. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // 5 // This code is free software; you can redistribute it and/or modify it 6 // under the terms of the GNU General Public License version 2 only, as 7 // published by the Free Software Foundation. 8 // 9 // This code is distributed in the hope that it will be useful, but WITHOUT 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 // version 2 for more details (a copy is included in the LICENSE file that 13 // accompanied this code). 14 // 15 // You should have received a copy of the GNU General Public License version 16 // 2 along with this work; if not, write to the Free Software Foundation, 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 // 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 // or visit www.oracle.com if you need additional information or have any 21 // questions. 22 // 23 // 24 25 // SPARC Architecture Description File 26 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ 28 // This information is used by the matcher and the register allocator to 29 // describe individual registers and classes of registers within the target 30 // archtecture. 31 register %{ 32 //----------Architecture Description Register Definitions---------------------- 33 // General Registers 34 // "reg_def" name ( register save type, C convention save type, 35 // ideal register type, encoding, vm name ); 36 // Register Save Types: 37 // 38 // NS = No-Save: The register allocator assumes that these registers 39 // can be used without saving upon entry to the method, & 40 // that they do not need to be saved at call sites. 41 // 42 // SOC = Save-On-Call: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, 44 // but that they must be saved at call sites. 45 // 46 // SOE = Save-On-Entry: The register allocator assumes that these registers 47 // must be saved before using them upon entry to the 48 // method, but they do not need to be saved at call 49 // sites. 50 // 51 // AS = Always-Save: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, & that they must be saved at call sites. 54 // 55 // Ideal Register Type is used to determine how to save & restore a 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 58 // 59 // The encoding number is the actual bit-pattern placed into the opcodes. 60 61 62 // ---------------------------- 63 // Integer/Long Registers 64 // ---------------------------- 65 66 // Need to expose the hi/lo aspect of 64-bit registers 67 // This register set is used for both the 64-bit build and 68 // the 32-bit build with 1-register longs. 69 70 // Global Registers 0-7 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 87 88 // Output Registers 0-7 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 105 106 // Local Registers 0-7 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 123 124 // Input Registers 0-7 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 141 142 // ---------------------------- 143 // Float/Double Registers 144 // ---------------------------- 145 146 // Float Registers 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 179 180 // Double Registers 181 // The rules of ADL require that double registers be defined in pairs. 182 // Each pair must be two 32-bit values, but not necessarily a pair of 183 // single float registers. In each pair, ADLC-assigned register numbers 184 // must be adjacent, with the lower number even. Finally, when the 185 // CPU stores such a register pair to memory, the word associated with 186 // the lower ADLC-assigned number must be stored to the lower address. 187 188 // These definitions specify the actual bit encodings of the sparc 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp 190 // wants 0-63, so we have to convert every time we want to use fp regs 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). 192 // 255 is a flag meaning "don't go here". 193 // I believe we can't handle callee-save doubles D32 and up until 194 // the place in the sparc stack crawler that asserts on the 255 is 195 // fixed up. 196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); 198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); 200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); 202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); 204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); 228 229 230 // ---------------------------- 231 // Special Registers 232 // Condition Codes Flag Registers 233 // I tried to break out ICC and XCC but it's not very pretty. 234 // Every Sparc instruction which defs/kills one also kills the other. 235 // Hence every compare instruction which defs one kind of flags ends 236 // up needing a kill of the other. 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 238 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 243 244 // ---------------------------- 245 // Specify the enum values for the registers. These enums are only used by the 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed 247 // for visibility to the rest of the vm. The order of this enum influences the 248 // register allocator so having the freedom to set this order and not be stuck 249 // with the order that is natural for the rest of the vm is worth it. 250 alloc_class chunk0( 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 255 256 // Note that a register is not allocatable unless it is also mentioned 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 258 259 alloc_class chunk1( 260 // The first registers listed here are those most likely to be used 261 // as temporaries. We move F0..F7 away from the front of the list, 262 // to reduce the likelihood of interferences with parameters and 263 // return values. Likewise, we avoid using F0/F1 for parameters, 264 // since they are used for return values. 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 274 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 276 277 //----------Architecture Description Register Classes-------------------------- 278 // Several register classes are automatically defined based upon information in 279 // this architecture description. 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 283 // 284 285 // G0 is not included in integer class since it has special meaning. 286 reg_class g0_reg(R_G0); 287 288 // ---------------------------- 289 // Integer Register Classes 290 // ---------------------------- 291 // Exclusions from i_reg: 292 // R_G0: hardwired zero 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) 294 // R_G6: reserved by Solaris ABI to tools 295 // R_G7: reserved by Solaris ABI to libthread 296 // R_O7: Used as a temp in many encodings 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 298 299 // Class for all integer registers, except the G registers. This is used for 300 // encodings which use G registers as temps. The regular inputs to such 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator 302 // will not put an input into a temp register. 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 304 305 reg_class g1_regI(R_G1); 306 reg_class g3_regI(R_G3); 307 reg_class g4_regI(R_G4); 308 reg_class o0_regI(R_O0); 309 reg_class o7_regI(R_O7); 310 311 // ---------------------------- 312 // Pointer Register Classes 313 // ---------------------------- 314 #ifdef _LP64 315 // 64-bit build means 64-bit pointers means hi/lo pairs 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 320 // Lock encodings use G3 and G4 internally 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 325 // Special class for storeP instructions, which can store SP or RPC to TLS. 326 // It is also used for memory addressing, allowing direct TLS addressing. 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register 332 // We use it to save R_G2 across calls out of Java. 333 reg_class l7_regP(R_L7H,R_L7); 334 335 // Other special pointer regs 336 reg_class g1_regP(R_G1H,R_G1); 337 reg_class g2_regP(R_G2H,R_G2); 338 reg_class g3_regP(R_G3H,R_G3); 339 reg_class g4_regP(R_G4H,R_G4); 340 reg_class g5_regP(R_G5H,R_G5); 341 reg_class i0_regP(R_I0H,R_I0); 342 reg_class o0_regP(R_O0H,R_O0); 343 reg_class o1_regP(R_O1H,R_O1); 344 reg_class o2_regP(R_O2H,R_O2); 345 reg_class o7_regP(R_O7H,R_O7); 346 347 #else // _LP64 348 // 32-bit build means 32-bit pointers means 1 register. 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 353 // Lock encodings use G3 and G4 internally 354 reg_class lock_ptr_reg(R_G1, R_G5, 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 358 // Special class for storeP instructions, which can store SP or RPC to TLS. 359 // It is also used for memory addressing, allowing direct TLS addressing. 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register 365 // We use it to save R_G2 across calls out of Java. 366 reg_class l7_regP(R_L7); 367 368 // Other special pointer regs 369 reg_class g1_regP(R_G1); 370 reg_class g2_regP(R_G2); 371 reg_class g3_regP(R_G3); 372 reg_class g4_regP(R_G4); 373 reg_class g5_regP(R_G5); 374 reg_class i0_regP(R_I0); 375 reg_class o0_regP(R_O0); 376 reg_class o1_regP(R_O1); 377 reg_class o2_regP(R_O2); 378 reg_class o7_regP(R_O7); 379 #endif // _LP64 380 381 382 // ---------------------------- 383 // Long Register Classes 384 // ---------------------------- 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 389 #ifdef _LP64 390 // 64-bit, longs in 1 register: use all 64-bit integer registers 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 394 #endif // _LP64 395 ); 396 397 reg_class g1_regL(R_G1H,R_G1); 398 reg_class g3_regL(R_G3H,R_G3); 399 reg_class o2_regL(R_O2H,R_O2); 400 reg_class o7_regL(R_O7H,R_O7); 401 402 // ---------------------------- 403 // Special Class for Condition Code Flags Register 404 reg_class int_flags(CCR); 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); 406 reg_class float_flag0(FCC0); 407 408 409 // ---------------------------- 410 // Float Point Register Classes 411 // ---------------------------- 412 // Skip F30/F31, they are reserved for mem-mem copies 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 414 415 // Paired floating point registers--they show up in the same order as the floats, 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 419 /* Use extra V9 double registers; this AD file does not support V8 */ 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 422 ); 423 424 // Paired floating point registers--they show up in the same order as the floats, 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 426 // This class is usable for mis-aligned loads as happen in I2C adapters. 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 429 %} 430 431 //----------DEFINITION BLOCK--------------------------------------------------- 432 // Define name --> value mappings to inform the ADLC of an integer valued name 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] 434 // Format: 435 // int_def <name> ( <int_value>, <expression>); 436 // Generated Code in ad_<arch>.hpp 437 // #define <name> (<expression>) 438 // // value == <int_value> 439 // Generated code in ad_<arch>.cpp adlc_verification() 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 441 // 442 definitions %{ 443 // The default cost (of an ALU instruction). 444 int_def DEFAULT_COST ( 100, 100); 445 int_def HUGE_COST (1000000, 1000000); 446 447 // Memory refs are twice as expensive as run-of-the-mill. 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 449 450 // Branches are even more expensive. 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); 453 %} 454 455 456 //----------SOURCE BLOCK------------------------------------------------------- 457 // This is a block of C++ code which provides values, functions, and 458 // definitions necessary in the rest of the architecture description 459 source_hpp %{ 460 // Header information of the source block. 461 // Method declarations/definitions which are used outside 462 // the ad-scope can conveniently be defined here. 463 // 464 // To keep related declarations/definitions/uses close together, 465 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 466 467 // Must be visible to the DFA in dfa_sparc.cpp 468 extern bool can_branch_register( Node *bol, Node *cmp ); 469 470 extern bool use_block_zeroing(Node* count); 471 472 // Macros to extract hi & lo halves from a long pair. 473 // G0 is not part of any long pair, so assert on that. 474 // Prevents accidentally using G1 instead of G0. 475 #define LONG_HI_REG(x) (x) 476 #define LONG_LO_REG(x) (x) 477 478 class CallStubImpl { 479 480 //-------------------------------------------------------------- 481 //---< Used for optimization in Compile::Shorten_branches >--- 482 //-------------------------------------------------------------- 483 484 public: 485 // Size of call trampoline stub. 486 static uint size_call_trampoline() { 487 return 0; // no call trampolines on this platform 488 } 489 490 // number of relocations needed by a call trampoline stub 491 static uint reloc_call_trampoline() { 492 return 0; // no call trampolines on this platform 493 } 494 }; 495 496 class HandlerImpl { 497 498 public: 499 500 static int emit_exception_handler(CodeBuffer &cbuf); 501 static int emit_deopt_handler(CodeBuffer& cbuf); 502 503 static uint size_exception_handler() { 504 if (TraceJumps) { 505 return (400); // just a guess 506 } 507 return ( NativeJump::instruction_size ); // sethi;jmp;nop 508 } 509 510 static uint size_deopt_handler() { 511 if (TraceJumps) { 512 return (400); // just a guess 513 } 514 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 515 } 516 }; 517 518 %} 519 520 source %{ 521 #define __ _masm. 522 523 // tertiary op of a LoadP or StoreP encoding 524 #define REGP_OP true 525 526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 528 static Register reg_to_register_object(int register_encoding); 529 530 // Used by the DFA in dfa_sparc.cpp. 531 // Check for being able to use a V9 branch-on-register. Requires a 532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 533 // extended. Doesn't work following an integer ADD, for example, because of 534 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On 535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 536 // replace them with zero, which could become sign-extension in a different OS 537 // release. There's no obvious reason why an interrupt will ever fill these 538 // bits with non-zero junk (the registers are reloaded with standard LD 539 // instructions which either zero-fill or sign-fill). 540 bool can_branch_register( Node *bol, Node *cmp ) { 541 if( !BranchOnRegister ) return false; 542 #ifdef _LP64 543 if( cmp->Opcode() == Op_CmpP ) 544 return true; // No problems with pointer compares 545 #endif 546 if( cmp->Opcode() == Op_CmpL ) 547 return true; // No problems with long compares 548 549 if( !SparcV9RegsHiBitsZero ) return false; 550 if( bol->as_Bool()->_test._test != BoolTest::ne && 551 bol->as_Bool()->_test._test != BoolTest::eq ) 552 return false; 553 554 // Check for comparing against a 'safe' value. Any operation which 555 // clears out the high word is safe. Thus, loads and certain shifts 556 // are safe, as are non-negative constants. Any operation which 557 // preserves zero bits in the high word is safe as long as each of its 558 // inputs are safe. Thus, phis and bitwise booleans are safe if their 559 // inputs are safe. At present, the only important case to recognize 560 // seems to be loads. Constants should fold away, and shifts & 561 // logicals can use the 'cc' forms. 562 Node *x = cmp->in(1); 563 if( x->is_Load() ) return true; 564 if( x->is_Phi() ) { 565 for( uint i = 1; i < x->req(); i++ ) 566 if( !x->in(i)->is_Load() ) 567 return false; 568 return true; 569 } 570 return false; 571 } 572 573 bool use_block_zeroing(Node* count) { 574 // Use BIS for zeroing if count is not constant 575 // or it is >= BlockZeroingLowLimit. 576 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); 577 } 578 579 // **************************************************************************** 580 581 // REQUIRED FUNCTIONALITY 582 583 // !!!!! Special hack to get all type of calls to specify the byte offset 584 // from the start of the call to the point where the return address 585 // will point. 586 // The "return address" is the address of the call instruction, plus 8. 587 588 int MachCallStaticJavaNode::ret_addr_offset() { 589 int offset = NativeCall::instruction_size; // call; delay slot 590 if (_method_handle_invoke) 591 offset += 4; // restore SP 592 return offset; 593 } 594 595 int MachCallDynamicJavaNode::ret_addr_offset() { 596 int vtable_index = this->_vtable_index; 597 if (vtable_index < 0) { 598 // must be invalid_vtable_index, not nonvirtual_vtable_index 599 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 600 return (NativeMovConstReg::instruction_size + 601 NativeCall::instruction_size); // sethi; setlo; call; delay slot 602 } else { 603 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 604 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 605 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 606 int klass_load_size; 607 if (UseCompressedClassPointers) { 608 assert(Universe::heap() != NULL, "java heap should be initialized"); 609 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 610 } else { 611 klass_load_size = 1*BytesPerInstWord; 612 } 613 if (Assembler::is_simm13(v_off)) { 614 return klass_load_size + 615 (2*BytesPerInstWord + // ld_ptr, ld_ptr 616 NativeCall::instruction_size); // call; delay slot 617 } else { 618 return klass_load_size + 619 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 620 NativeCall::instruction_size); // call; delay slot 621 } 622 } 623 } 624 625 int MachCallRuntimeNode::ret_addr_offset() { 626 #ifdef _LP64 627 if (MacroAssembler::is_far_target(entry_point())) { 628 return NativeFarCall::instruction_size; 629 } else { 630 return NativeCall::instruction_size; 631 } 632 #else 633 return NativeCall::instruction_size; // call; delay slot 634 #endif 635 } 636 637 // Indicate if the safepoint node needs the polling page as an input. 638 // Since Sparc does not have absolute addressing, it does. 639 bool SafePointNode::needs_polling_address_input() { 640 return true; 641 } 642 643 // emit an interrupt that is caught by the debugger (for debugging compiler) 644 void emit_break(CodeBuffer &cbuf) { 645 MacroAssembler _masm(&cbuf); 646 __ breakpoint_trap(); 647 } 648 649 #ifndef PRODUCT 650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 651 st->print("TA"); 652 } 653 #endif 654 655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 656 emit_break(cbuf); 657 } 658 659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 660 return MachNode::size(ra_); 661 } 662 663 // Traceable jump 664 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { 665 MacroAssembler _masm(&cbuf); 666 Register rdest = reg_to_register_object(jump_target); 667 __ JMP(rdest, 0); 668 __ delayed()->nop(); 669 } 670 671 // Traceable jump and set exception pc 672 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 673 MacroAssembler _masm(&cbuf); 674 Register rdest = reg_to_register_object(jump_target); 675 __ JMP(rdest, 0); 676 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 677 } 678 679 void emit_nop(CodeBuffer &cbuf) { 680 MacroAssembler _masm(&cbuf); 681 __ nop(); 682 } 683 684 void emit_illtrap(CodeBuffer &cbuf) { 685 MacroAssembler _masm(&cbuf); 686 __ illtrap(0); 687 } 688 689 690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 691 assert(n->rule() != loadUB_rule, ""); 692 693 intptr_t offset = 0; 694 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 695 const Node* addr = n->get_base_and_disp(offset, adr_type); 696 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 697 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 698 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 699 atype = atype->add_offset(offset); 700 assert(disp32 == offset, "wrong disp32"); 701 return atype->_offset; 702 } 703 704 705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 706 assert(n->rule() != loadUB_rule, ""); 707 708 intptr_t offset = 0; 709 Node* addr = n->in(2); 710 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 711 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 712 Node* a = addr->in(2/*AddPNode::Address*/); 713 Node* o = addr->in(3/*AddPNode::Offset*/); 714 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 715 atype = a->bottom_type()->is_ptr()->add_offset(offset); 716 assert(atype->isa_oop_ptr(), "still an oop"); 717 } 718 offset = atype->is_ptr()->_offset; 719 if (offset != Type::OffsetBot) offset += disp32; 720 return offset; 721 } 722 723 static inline jdouble replicate_immI(int con, int count, int width) { 724 // Load a constant replicated "count" times with width "width" 725 assert(count*width == 8 && width <= 4, "sanity"); 726 int bit_width = width * 8; 727 jlong val = con; 728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits 729 for (int i = 0; i < count - 1; i++) { 730 val |= (val << bit_width); 731 } 732 jdouble dval = *((jdouble*) &val); // coerce to double type 733 return dval; 734 } 735 736 static inline jdouble replicate_immF(float con) { 737 // Replicate float con 2 times and pack into vector. 738 int val = *((int*)&con); 739 jlong lval = val; 740 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 741 jdouble dval = *((jdouble*) &lval); // coerce to double type 742 return dval; 743 } 744 745 // Standard Sparc opcode form2 field breakdown 746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 747 f0 &= (1<<19)-1; // Mask displacement to 19 bits 748 int op = (f30 << 30) | 749 (f29 << 29) | 750 (f25 << 25) | 751 (f22 << 22) | 752 (f20 << 20) | 753 (f19 << 19) | 754 (f0 << 0); 755 cbuf.insts()->emit_int32(op); 756 } 757 758 // Standard Sparc opcode form2 field breakdown 759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 760 f0 >>= 10; // Drop 10 bits 761 f0 &= (1<<22)-1; // Mask displacement to 22 bits 762 int op = (f30 << 30) | 763 (f25 << 25) | 764 (f22 << 22) | 765 (f0 << 0); 766 cbuf.insts()->emit_int32(op); 767 } 768 769 // Standard Sparc opcode form3 field breakdown 770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 771 int op = (f30 << 30) | 772 (f25 << 25) | 773 (f19 << 19) | 774 (f14 << 14) | 775 (f5 << 5) | 776 (f0 << 0); 777 cbuf.insts()->emit_int32(op); 778 } 779 780 // Standard Sparc opcode form3 field breakdown 781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 782 simm13 &= (1<<13)-1; // Mask to 13 bits 783 int op = (f30 << 30) | 784 (f25 << 25) | 785 (f19 << 19) | 786 (f14 << 14) | 787 (1 << 13) | // bit to indicate immediate-mode 788 (simm13<<0); 789 cbuf.insts()->emit_int32(op); 790 } 791 792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 793 simm10 &= (1<<10)-1; // Mask to 10 bits 794 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 795 } 796 797 #ifdef ASSERT 798 // Helper function for VerifyOops in emit_form3_mem_reg 799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 800 warning("VerifyOops encountered unexpected instruction:"); 801 n->dump(2); 802 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 803 } 804 #endif 805 806 807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary, 808 int src1_enc, int disp32, int src2_enc, int dst_enc) { 809 810 #ifdef ASSERT 811 // The following code implements the +VerifyOops feature. 812 // It verifies oop values which are loaded into or stored out of 813 // the current method activation. +VerifyOops complements techniques 814 // like ScavengeALot, because it eagerly inspects oops in transit, 815 // as they enter or leave the stack, as opposed to ScavengeALot, 816 // which inspects oops "at rest", in the stack or heap, at safepoints. 817 // For this reason, +VerifyOops can sometimes detect bugs very close 818 // to their point of creation. It can also serve as a cross-check 819 // on the validity of oop maps, when used toegether with ScavengeALot. 820 821 // It would be good to verify oops at other points, especially 822 // when an oop is used as a base pointer for a load or store. 823 // This is presently difficult, because it is hard to know when 824 // a base address is biased or not. (If we had such information, 825 // it would be easy and useful to make a two-argument version of 826 // verify_oop which unbiases the base, and performs verification.) 827 828 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 829 bool is_verified_oop_base = false; 830 bool is_verified_oop_load = false; 831 bool is_verified_oop_store = false; 832 int tmp_enc = -1; 833 if (VerifyOops && src1_enc != R_SP_enc) { 834 // classify the op, mainly for an assert check 835 int st_op = 0, ld_op = 0; 836 switch (primary) { 837 case Assembler::stb_op3: st_op = Op_StoreB; break; 838 case Assembler::sth_op3: st_op = Op_StoreC; break; 839 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 840 case Assembler::stw_op3: st_op = Op_StoreI; break; 841 case Assembler::std_op3: st_op = Op_StoreL; break; 842 case Assembler::stf_op3: st_op = Op_StoreF; break; 843 case Assembler::stdf_op3: st_op = Op_StoreD; break; 844 845 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 846 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; 847 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; 848 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 849 case Assembler::ldx_op3: // may become LoadP or stay LoadI 850 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 851 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 852 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 853 case Assembler::ldf_op3: ld_op = Op_LoadF; break; 854 case Assembler::lddf_op3: ld_op = Op_LoadD; break; 855 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 856 857 default: ShouldNotReachHere(); 858 } 859 if (tertiary == REGP_OP) { 860 if (st_op == Op_StoreI) st_op = Op_StoreP; 861 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 862 else ShouldNotReachHere(); 863 if (st_op) { 864 // a store 865 // inputs are (0:control, 1:memory, 2:address, 3:value) 866 Node* n2 = n->in(3); 867 if (n2 != NULL) { 868 const Type* t = n2->bottom_type(); 869 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 870 } 871 } else { 872 // a load 873 const Type* t = n->bottom_type(); 874 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 875 } 876 } 877 878 if (ld_op) { 879 // a Load 880 // inputs are (0:control, 1:memory, 2:address) 881 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 882 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 883 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 884 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 885 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 886 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 887 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 888 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 889 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 890 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 891 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 892 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && 893 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && 894 !(n->rule() == loadUB_rule)) { 895 verify_oops_warning(n, n->ideal_Opcode(), ld_op); 896 } 897 } else if (st_op) { 898 // a Store 899 // inputs are (0:control, 1:memory, 2:address, 3:value) 900 if (!(n->ideal_Opcode()==st_op) && // Following are special cases 901 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 902 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 903 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 904 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 905 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && 906 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 907 verify_oops_warning(n, n->ideal_Opcode(), st_op); 908 } 909 } 910 911 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 912 Node* addr = n->in(2); 913 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 914 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 915 if (atype != NULL) { 916 intptr_t offset = get_offset_from_base(n, atype, disp32); 917 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 918 if (offset != offset_2) { 919 get_offset_from_base(n, atype, disp32); 920 get_offset_from_base_2(n, atype, disp32); 921 } 922 assert(offset == offset_2, "different offsets"); 923 if (offset == disp32) { 924 // we now know that src1 is a true oop pointer 925 is_verified_oop_base = true; 926 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 927 if( primary == Assembler::ldd_op3 ) { 928 is_verified_oop_base = false; // Cannot 'ldd' into O7 929 } else { 930 tmp_enc = dst_enc; 931 dst_enc = R_O7_enc; // Load into O7; preserve source oop 932 assert(src1_enc != dst_enc, ""); 933 } 934 } 935 } 936 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 937 || offset == oopDesc::mark_offset_in_bytes())) { 938 // loading the mark should not be allowed either, but 939 // we don't check this since it conflicts with InlineObjectHash 940 // usage of LoadINode to get the mark. We could keep the 941 // check if we create a new LoadMarkNode 942 // but do not verify the object before its header is initialized 943 ShouldNotReachHere(); 944 } 945 } 946 } 947 } 948 } 949 #endif 950 951 uint instr; 952 instr = (Assembler::ldst_op << 30) 953 | (dst_enc << 25) 954 | (primary << 19) 955 | (src1_enc << 14); 956 957 uint index = src2_enc; 958 int disp = disp32; 959 960 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) { 961 disp += STACK_BIAS; 962 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not 963 if (!Assembler::is_simm13(disp)) { 964 ra->C->record_method_not_compilable("unable to handle large constant offsets"); 965 return; 966 } 967 } 968 969 // We should have a compiler bailout here rather than a guarantee. 970 // Better yet would be some mechanism to handle variable-size matches correctly. 971 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 972 973 if( disp == 0 ) { 974 // use reg-reg form 975 // bit 13 is already zero 976 instr |= index; 977 } else { 978 // use reg-imm form 979 instr |= 0x00002000; // set bit 13 to one 980 instr |= disp & 0x1FFF; 981 } 982 983 cbuf.insts()->emit_int32(instr); 984 985 #ifdef ASSERT 986 { 987 MacroAssembler _masm(&cbuf); 988 if (is_verified_oop_base) { 989 __ verify_oop(reg_to_register_object(src1_enc)); 990 } 991 if (is_verified_oop_store) { 992 __ verify_oop(reg_to_register_object(dst_enc)); 993 } 994 if (tmp_enc != -1) { 995 __ mov(O7, reg_to_register_object(tmp_enc)); 996 } 997 if (is_verified_oop_load) { 998 __ verify_oop(reg_to_register_object(dst_enc)); 999 } 1000 } 1001 #endif 1002 } 1003 1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { 1005 // The method which records debug information at every safepoint 1006 // expects the call to be the first instruction in the snippet as 1007 // it creates a PcDesc structure which tracks the offset of a call 1008 // from the start of the codeBlob. This offset is computed as 1009 // code_end() - code_begin() of the code which has been emitted 1010 // so far. 1011 // In this particular case we have skirted around the problem by 1012 // putting the "mov" instruction in the delay slot but the problem 1013 // may bite us again at some other point and a cleaner/generic 1014 // solution using relocations would be needed. 1015 MacroAssembler _masm(&cbuf); 1016 __ set_inst_mark(); 1017 1018 // We flush the current window just so that there is a valid stack copy 1019 // the fact that the current window becomes active again instantly is 1020 // not a problem there is nothing live in it. 1021 1022 #ifdef ASSERT 1023 int startpos = __ offset(); 1024 #endif /* ASSERT */ 1025 1026 __ call((address)entry_point, rtype); 1027 1028 if (preserve_g2) __ delayed()->mov(G2, L7); 1029 else __ delayed()->nop(); 1030 1031 if (preserve_g2) __ mov(L7, G2); 1032 1033 #ifdef ASSERT 1034 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 1035 #ifdef _LP64 1036 // Trash argument dump slots. 1037 __ set(0xb0b8ac0db0b8ac0d, G1); 1038 __ mov(G1, G5); 1039 __ stx(G1, SP, STACK_BIAS + 0x80); 1040 __ stx(G1, SP, STACK_BIAS + 0x88); 1041 __ stx(G1, SP, STACK_BIAS + 0x90); 1042 __ stx(G1, SP, STACK_BIAS + 0x98); 1043 __ stx(G1, SP, STACK_BIAS + 0xA0); 1044 __ stx(G1, SP, STACK_BIAS + 0xA8); 1045 #else // _LP64 1046 // this is also a native call, so smash the first 7 stack locations, 1047 // and the various registers 1048 1049 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], 1050 // while [SP+0x44..0x58] are the argument dump slots. 1051 __ set((intptr_t)0xbaadf00d, G1); 1052 __ mov(G1, G5); 1053 __ sllx(G1, 32, G1); 1054 __ or3(G1, G5, G1); 1055 __ mov(G1, G5); 1056 __ stx(G1, SP, 0x40); 1057 __ stx(G1, SP, 0x48); 1058 __ stx(G1, SP, 0x50); 1059 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot 1060 #endif // _LP64 1061 } 1062 #endif /*ASSERT*/ 1063 } 1064 1065 //============================================================================= 1066 // REQUIRED FUNCTIONALITY for encoding 1067 void emit_lo(CodeBuffer &cbuf, int val) { } 1068 void emit_hi(CodeBuffer &cbuf, int val) { } 1069 1070 1071 //============================================================================= 1072 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); 1073 1074 int Compile::ConstantTable::calculate_table_base_offset() const { 1075 if (UseRDPCForConstantTableBase) { 1076 // The table base offset might be less but then it fits into 1077 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). 1078 return Assembler::min_simm13(); 1079 } else { 1080 int offset = -(size() / 2); 1081 if (!Assembler::is_simm13(offset)) { 1082 offset = Assembler::min_simm13(); 1083 } 1084 return offset; 1085 } 1086 } 1087 1088 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } 1089 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1090 ShouldNotReachHere(); 1091 } 1092 1093 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1094 Compile* C = ra_->C; 1095 Compile::ConstantTable& constant_table = C->constant_table(); 1096 MacroAssembler _masm(&cbuf); 1097 1098 Register r = as_Register(ra_->get_encode(this)); 1099 CodeSection* consts_section = __ code()->consts(); 1100 int consts_size = consts_section->align_at_start(consts_section->size()); 1101 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); 1102 1103 if (UseRDPCForConstantTableBase) { 1104 // For the following RDPC logic to work correctly the consts 1105 // section must be allocated right before the insts section. This 1106 // assert checks for that. The layout and the SECT_* constants 1107 // are defined in src/share/vm/asm/codeBuffer.hpp. 1108 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); 1109 int insts_offset = __ offset(); 1110 1111 // Layout: 1112 // 1113 // |----------- consts section ------------|----------- insts section -----------... 1114 // |------ constant table -----|- padding -|------------------x---- 1115 // \ current PC (RDPC instruction) 1116 // |<------------- consts_size ----------->|<- insts_offset ->| 1117 // \ table base 1118 // The table base offset is later added to the load displacement 1119 // so it has to be negative. 1120 int table_base_offset = -(consts_size + insts_offset); 1121 int disp; 1122 1123 // If the displacement from the current PC to the constant table 1124 // base fits into simm13 we set the constant table base to the 1125 // current PC. 1126 if (Assembler::is_simm13(table_base_offset)) { 1127 constant_table.set_table_base_offset(table_base_offset); 1128 disp = 0; 1129 } else { 1130 // Otherwise we set the constant table base offset to the 1131 // maximum negative displacement of load instructions to keep 1132 // the disp as small as possible: 1133 // 1134 // |<------------- consts_size ----------->|<- insts_offset ->| 1135 // |<--------- min_simm13 --------->|<-------- disp --------->| 1136 // \ table base 1137 table_base_offset = Assembler::min_simm13(); 1138 constant_table.set_table_base_offset(table_base_offset); 1139 disp = (consts_size + insts_offset) + table_base_offset; 1140 } 1141 1142 __ rdpc(r); 1143 1144 if (disp != 0) { 1145 assert(r != O7, "need temporary"); 1146 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); 1147 } 1148 } 1149 else { 1150 // Materialize the constant table base. 1151 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); 1152 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); 1153 AddressLiteral base(baseaddr, rspec); 1154 __ set(base, r); 1155 } 1156 } 1157 1158 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { 1159 if (UseRDPCForConstantTableBase) { 1160 // This is really the worst case but generally it's only 1 instruction. 1161 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; 1162 } else { 1163 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; 1164 } 1165 } 1166 1167 #ifndef PRODUCT 1168 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1169 char reg[128]; 1170 ra_->dump_register(this, reg); 1171 if (UseRDPCForConstantTableBase) { 1172 st->print("RDPC %s\t! constant table base", reg); 1173 } else { 1174 st->print("SET &constanttable,%s\t! constant table base", reg); 1175 } 1176 } 1177 #endif 1178 1179 1180 //============================================================================= 1181 1182 #ifndef PRODUCT 1183 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1184 Compile* C = ra_->C; 1185 1186 for (int i = 0; i < OptoPrologueNops; i++) { 1187 st->print_cr("NOP"); st->print("\t"); 1188 } 1189 1190 if( VerifyThread ) { 1191 st->print_cr("Verify_Thread"); st->print("\t"); 1192 } 1193 1194 size_t framesize = C->frame_size_in_bytes(); 1195 int bangsize = C->bang_size_in_bytes(); 1196 1197 // Calls to C2R adapters often do not accept exceptional returns. 1198 // We require that their callers must bang for them. But be careful, because 1199 // some VM calls (such as call site linkage) can use several kilobytes of 1200 // stack. But the stack safety zone should account for that. 1201 // See bugs 4446381, 4468289, 4497237. 1202 if (C->need_stack_bang(bangsize)) { 1203 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t"); 1204 } 1205 1206 if (Assembler::is_simm13(-framesize)) { 1207 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize); 1208 } else { 1209 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); 1210 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); 1211 st->print ("SAVE R_SP,R_G3,R_SP"); 1212 } 1213 1214 } 1215 #endif 1216 1217 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1218 Compile* C = ra_->C; 1219 MacroAssembler _masm(&cbuf); 1220 1221 for (int i = 0; i < OptoPrologueNops; i++) { 1222 __ nop(); 1223 } 1224 1225 __ verify_thread(); 1226 1227 size_t framesize = C->frame_size_in_bytes(); 1228 assert(framesize >= 16*wordSize, "must have room for reg. save area"); 1229 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 1230 int bangsize = C->bang_size_in_bytes(); 1231 1232 // Calls to C2R adapters often do not accept exceptional returns. 1233 // We require that their callers must bang for them. But be careful, because 1234 // some VM calls (such as call site linkage) can use several kilobytes of 1235 // stack. But the stack safety zone should account for that. 1236 // See bugs 4446381, 4468289, 4497237. 1237 if (C->need_stack_bang(bangsize)) { 1238 __ generate_stack_overflow_check(bangsize); 1239 } 1240 1241 if (Assembler::is_simm13(-framesize)) { 1242 __ save(SP, -framesize, SP); 1243 } else { 1244 __ sethi(-framesize & ~0x3ff, G3); 1245 __ add(G3, -framesize & 0x3ff, G3); 1246 __ save(SP, G3, SP); 1247 } 1248 C->set_frame_complete( __ offset() ); 1249 1250 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { 1251 // NOTE: We set the table base offset here because users might be 1252 // emitted before MachConstantBaseNode. 1253 Compile::ConstantTable& constant_table = C->constant_table(); 1254 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 1255 } 1256 } 1257 1258 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1259 return MachNode::size(ra_); 1260 } 1261 1262 int MachPrologNode::reloc() const { 1263 return 10; // a large enough number 1264 } 1265 1266 //============================================================================= 1267 #ifndef PRODUCT 1268 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1269 Compile* C = ra_->C; 1270 1271 if(do_polling() && ra_->C->is_method_compilation()) { 1272 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 1273 #ifdef _LP64 1274 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 1275 #else 1276 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); 1277 #endif 1278 } 1279 1280 if(do_polling()) { 1281 if (UseCBCond && !ra_->C->is_method_compilation()) { 1282 st->print("NOP\n\t"); 1283 } 1284 st->print("RET\n\t"); 1285 } 1286 1287 st->print("RESTORE"); 1288 } 1289 #endif 1290 1291 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1292 MacroAssembler _masm(&cbuf); 1293 Compile* C = ra_->C; 1294 1295 __ verify_thread(); 1296 1297 // If this does safepoint polling, then do it here 1298 if(do_polling() && ra_->C->is_method_compilation()) { 1299 AddressLiteral polling_page(os::get_polling_page()); 1300 __ sethi(polling_page, L0); 1301 __ relocate(relocInfo::poll_return_type); 1302 __ ld_ptr(L0, 0, G0); 1303 } 1304 1305 // If this is a return, then stuff the restore in the delay slot 1306 if(do_polling()) { 1307 if (UseCBCond && !ra_->C->is_method_compilation()) { 1308 // Insert extra padding for the case when the epilogue is preceded by 1309 // a cbcond jump, which can't be followed by a CTI instruction 1310 __ nop(); 1311 } 1312 __ ret(); 1313 __ delayed()->restore(); 1314 } else { 1315 __ restore(); 1316 } 1317 } 1318 1319 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1320 return MachNode::size(ra_); 1321 } 1322 1323 int MachEpilogNode::reloc() const { 1324 return 16; // a large enough number 1325 } 1326 1327 const Pipeline * MachEpilogNode::pipeline() const { 1328 return MachNode::pipeline_class(); 1329 } 1330 1331 int MachEpilogNode::safepoint_offset() const { 1332 assert( do_polling(), "no return for this epilog node"); 1333 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; 1334 } 1335 1336 //============================================================================= 1337 1338 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack 1339 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1340 static enum RC rc_class( OptoReg::Name reg ) { 1341 if( !OptoReg::is_valid(reg) ) return rc_bad; 1342 if (OptoReg::is_stack(reg)) return rc_stack; 1343 VMReg r = OptoReg::as_VMReg(reg); 1344 if (r->is_Register()) return rc_int; 1345 assert(r->is_FloatRegister(), "must be"); 1346 return rc_float; 1347 } 1348 1349 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { 1350 if (cbuf) { 1351 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 1352 } 1353 #ifndef PRODUCT 1354 else if (!do_size) { 1355 if (size != 0) st->print("\n\t"); 1356 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); 1357 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); 1358 } 1359 #endif 1360 return size+4; 1361 } 1362 1363 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { 1364 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); 1365 #ifndef PRODUCT 1366 else if( !do_size ) { 1367 if( size != 0 ) st->print("\n\t"); 1368 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); 1369 } 1370 #endif 1371 return size+4; 1372 } 1373 1374 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, 1375 PhaseRegAlloc *ra_, 1376 bool do_size, 1377 outputStream* st ) const { 1378 // Get registers to move 1379 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 1380 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 1381 OptoReg::Name dst_second = ra_->get_reg_second(this ); 1382 OptoReg::Name dst_first = ra_->get_reg_first(this ); 1383 1384 enum RC src_second_rc = rc_class(src_second); 1385 enum RC src_first_rc = rc_class(src_first); 1386 enum RC dst_second_rc = rc_class(dst_second); 1387 enum RC dst_first_rc = rc_class(dst_first); 1388 1389 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 1390 1391 // Generate spill code! 1392 int size = 0; 1393 1394 if( src_first == dst_first && src_second == dst_second ) 1395 return size; // Self copy, no move 1396 1397 // -------------------------------------- 1398 // Check for mem-mem move. Load into unused float registers and fall into 1399 // the float-store case. 1400 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 1401 int offset = ra_->reg2offset(src_first); 1402 // Further check for aligned-adjacent pair, so we can use a double load 1403 if( (src_first&1)==0 && src_first+1 == src_second ) { 1404 src_second = OptoReg::Name(R_F31_num); 1405 src_second_rc = rc_float; 1406 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); 1407 } else { 1408 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); 1409 } 1410 src_first = OptoReg::Name(R_F30_num); 1411 src_first_rc = rc_float; 1412 } 1413 1414 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 1415 int offset = ra_->reg2offset(src_second); 1416 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); 1417 src_second = OptoReg::Name(R_F31_num); 1418 src_second_rc = rc_float; 1419 } 1420 1421 // -------------------------------------- 1422 // Check for float->int copy; requires a trip through memory 1423 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { 1424 int offset = frame::register_save_words*wordSize; 1425 if (cbuf) { 1426 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); 1427 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1428 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1429 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); 1430 } 1431 #ifndef PRODUCT 1432 else if (!do_size) { 1433 if (size != 0) st->print("\n\t"); 1434 st->print( "SUB R_SP,16,R_SP\n"); 1435 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1436 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1437 st->print("\tADD R_SP,16,R_SP\n"); 1438 } 1439 #endif 1440 size += 16; 1441 } 1442 1443 // Check for float->int copy on T4 1444 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { 1445 // Further check for aligned-adjacent pair, so we can use a double move 1446 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) 1447 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st); 1448 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st); 1449 } 1450 // Check for int->float copy on T4 1451 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { 1452 // Further check for aligned-adjacent pair, so we can use a double move 1453 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) 1454 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st); 1455 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st); 1456 } 1457 1458 // -------------------------------------- 1459 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 1460 // In such cases, I have to do the big-endian swap. For aligned targets, the 1461 // hardware does the flop for me. Doubles are always aligned, so no problem 1462 // there. Misaligned sources only come from native-long-returns (handled 1463 // special below). 1464 #ifndef _LP64 1465 if( src_first_rc == rc_int && // source is already big-endian 1466 src_second_rc != rc_bad && // 64-bit move 1467 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst 1468 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); 1469 // Do the big-endian flop. 1470 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; 1471 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; 1472 } 1473 #endif 1474 1475 // -------------------------------------- 1476 // Check for integer reg-reg copy 1477 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { 1478 #ifndef _LP64 1479 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case 1480 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1481 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1482 // operand contains the least significant word of the 64-bit value and vice versa. 1483 OptoReg::Name tmp = OptoReg::Name(R_O7_num); 1484 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); 1485 // Shift O0 left in-place, zero-extend O1, then OR them into the dst 1486 if( cbuf ) { 1487 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); 1488 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); 1489 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); 1490 #ifndef PRODUCT 1491 } else if( !do_size ) { 1492 if( size != 0 ) st->print("\n\t"); 1493 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); 1494 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); 1495 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); 1496 #endif 1497 } 1498 return size+12; 1499 } 1500 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { 1501 // returning a long value in I0/I1 1502 // a SpillCopy must be able to target a return instruction's reg_class 1503 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1504 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1505 // operand contains the least significant word of the 64-bit value and vice versa. 1506 OptoReg::Name tdest = dst_first; 1507 1508 if (src_first == dst_first) { 1509 tdest = OptoReg::Name(R_O7_num); 1510 size += 4; 1511 } 1512 1513 if( cbuf ) { 1514 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); 1515 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 1516 // ShrL_reg_imm6 1517 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); 1518 // ShrR_reg_imm6 src, 0, dst 1519 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); 1520 if (tdest != dst_first) { 1521 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); 1522 } 1523 } 1524 #ifndef PRODUCT 1525 else if( !do_size ) { 1526 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! 1527 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); 1528 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); 1529 if (tdest != dst_first) { 1530 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); 1531 } 1532 } 1533 #endif // PRODUCT 1534 return size+8; 1535 } 1536 #endif // !_LP64 1537 // Else normal reg-reg copy 1538 assert( src_second != dst_first, "smashed second before evacuating it" ); 1539 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); 1540 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); 1541 // This moves an aligned adjacent pair. 1542 // See if we are done. 1543 if( src_first+1 == src_second && dst_first+1 == dst_second ) 1544 return size; 1545 } 1546 1547 // Check for integer store 1548 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { 1549 int offset = ra_->reg2offset(dst_first); 1550 // Further check for aligned-adjacent pair, so we can use a double store 1551 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1552 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); 1553 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); 1554 } 1555 1556 // Check for integer load 1557 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { 1558 int offset = ra_->reg2offset(src_first); 1559 // Further check for aligned-adjacent pair, so we can use a double load 1560 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1561 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); 1562 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1563 } 1564 1565 // Check for float reg-reg copy 1566 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 1567 // Further check for aligned-adjacent pair, so we can use a double move 1568 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1569 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); 1570 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); 1571 } 1572 1573 // Check for float store 1574 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 1575 int offset = ra_->reg2offset(dst_first); 1576 // Further check for aligned-adjacent pair, so we can use a double store 1577 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1578 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); 1579 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1580 } 1581 1582 // Check for float load 1583 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 1584 int offset = ra_->reg2offset(src_first); 1585 // Further check for aligned-adjacent pair, so we can use a double load 1586 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1587 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); 1588 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); 1589 } 1590 1591 // -------------------------------------------------------------------- 1592 // Check for hi bits still needing moving. Only happens for misaligned 1593 // arguments to native calls. 1594 if( src_second == dst_second ) 1595 return size; // Self copy; no move 1596 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1597 1598 #ifndef _LP64 1599 // In the LP64 build, all registers can be moved as aligned/adjacent 1600 // pairs, so there's never any need to move the high bits separately. 1601 // The 32-bit builds have to deal with the 32-bit ABI which can force 1602 // all sorts of silly alignment problems. 1603 1604 // Check for integer reg-reg copy. Hi bits are stuck up in the top 1605 // 32-bits of a 64-bit register, but are needed in low bits of another 1606 // register (else it's a hi-bits-to-hi-bits copy which should have 1607 // happened already as part of a 64-bit move) 1608 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { 1609 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); 1610 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); 1611 // Shift src_second down to dst_second's low bits. 1612 if( cbuf ) { 1613 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1614 #ifndef PRODUCT 1615 } else if( !do_size ) { 1616 if( size != 0 ) st->print("\n\t"); 1617 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); 1618 #endif 1619 } 1620 return size+4; 1621 } 1622 1623 // Check for high word integer store. Must down-shift the hi bits 1624 // into a temp register, then fall into the case of storing int bits. 1625 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { 1626 // Shift src_second down to dst_second's low bits. 1627 if( cbuf ) { 1628 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1629 #ifndef PRODUCT 1630 } else if( !do_size ) { 1631 if( size != 0 ) st->print("\n\t"); 1632 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); 1633 #endif 1634 } 1635 size+=4; 1636 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! 1637 } 1638 1639 // Check for high word integer load 1640 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1641 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); 1642 1643 // Check for high word integer store 1644 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1645 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); 1646 1647 // Check for high word float store 1648 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) 1649 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); 1650 1651 #endif // !_LP64 1652 1653 Unimplemented(); 1654 } 1655 1656 #ifndef PRODUCT 1657 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1658 implementation( NULL, ra_, false, st ); 1659 } 1660 #endif 1661 1662 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1663 implementation( &cbuf, ra_, false, NULL ); 1664 } 1665 1666 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1667 return implementation( NULL, ra_, true, NULL ); 1668 } 1669 1670 //============================================================================= 1671 #ifndef PRODUCT 1672 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { 1673 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1674 } 1675 #endif 1676 1677 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { 1678 MacroAssembler _masm(&cbuf); 1679 for(int i = 0; i < _count; i += 1) { 1680 __ nop(); 1681 } 1682 } 1683 1684 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1685 return 4 * _count; 1686 } 1687 1688 1689 //============================================================================= 1690 #ifndef PRODUCT 1691 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1692 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1693 int reg = ra_->get_reg_first(this); 1694 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1695 } 1696 #endif 1697 1698 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1699 MacroAssembler _masm(&cbuf); 1700 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1701 int reg = ra_->get_encode(this); 1702 1703 if (Assembler::is_simm13(offset)) { 1704 __ add(SP, offset, reg_to_register_object(reg)); 1705 } else { 1706 __ set(offset, O7); 1707 __ add(SP, O7, reg_to_register_object(reg)); 1708 } 1709 } 1710 1711 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1712 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1713 assert(ra_ == ra_->C->regalloc(), "sanity"); 1714 return ra_->C->scratch_emit_size(this); 1715 } 1716 1717 //============================================================================= 1718 #ifndef PRODUCT 1719 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1720 st->print_cr("\nUEP:"); 1721 #ifdef _LP64 1722 if (UseCompressedClassPointers) { 1723 assert(Universe::heap() != NULL, "java heap should be initialized"); 1724 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1725 if (Universe::narrow_klass_base() != 0) { 1726 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base"); 1727 if (Universe::narrow_klass_shift() != 0) { 1728 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1729 } 1730 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1731 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base"); 1732 } else { 1733 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1734 } 1735 } else { 1736 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1737 } 1738 st->print_cr("\tCMP R_G5,R_G3" ); 1739 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1740 #else // _LP64 1741 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1742 st->print_cr("\tCMP R_G5,R_G3" ); 1743 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1744 #endif // _LP64 1745 } 1746 #endif 1747 1748 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1749 MacroAssembler _masm(&cbuf); 1750 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1751 Register temp_reg = G3; 1752 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1753 1754 // Load klass from receiver 1755 __ load_klass(O0, temp_reg); 1756 // Compare against expected klass 1757 __ cmp(temp_reg, G5_ic_reg); 1758 // Branch to miss code, checks xcc or icc depending 1759 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1760 } 1761 1762 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1763 return MachNode::size(ra_); 1764 } 1765 1766 1767 //============================================================================= 1768 1769 1770 // Emit exception handler code. 1771 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) { 1772 Register temp_reg = G3; 1773 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); 1774 MacroAssembler _masm(&cbuf); 1775 1776 address base = 1777 __ start_a_stub(size_exception_handler()); 1778 if (base == NULL) return 0; // CodeBuffer::expand failed 1779 1780 int offset = __ offset(); 1781 1782 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp 1783 __ delayed()->nop(); 1784 1785 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1786 1787 __ end_a_stub(); 1788 1789 return offset; 1790 } 1791 1792 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 1793 // Can't use any of the current frame's registers as we may have deopted 1794 // at a poll and everything (including G3) can be live. 1795 Register temp_reg = L0; 1796 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 1797 MacroAssembler _masm(&cbuf); 1798 1799 address base = 1800 __ start_a_stub(size_deopt_handler()); 1801 if (base == NULL) return 0; // CodeBuffer::expand failed 1802 1803 int offset = __ offset(); 1804 __ save_frame(0); 1805 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp 1806 __ delayed()->restore(); 1807 1808 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1809 1810 __ end_a_stub(); 1811 return offset; 1812 1813 } 1814 1815 // Given a register encoding, produce a Integer Register object 1816 static Register reg_to_register_object(int register_encoding) { 1817 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1818 return as_Register(register_encoding); 1819 } 1820 1821 // Given a register encoding, produce a single-precision Float Register object 1822 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1823 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1824 return as_SingleFloatRegister(register_encoding); 1825 } 1826 1827 // Given a register encoding, produce a double-precision Float Register object 1828 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1829 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1830 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1831 return as_DoubleFloatRegister(register_encoding); 1832 } 1833 1834 const bool Matcher::match_rule_supported(int opcode) { 1835 if (!has_match_rule(opcode)) 1836 return false; 1837 1838 switch (opcode) { 1839 case Op_CountLeadingZerosI: 1840 case Op_CountLeadingZerosL: 1841 case Op_CountTrailingZerosI: 1842 case Op_CountTrailingZerosL: 1843 case Op_PopCountI: 1844 case Op_PopCountL: 1845 if (!UsePopCountInstruction) 1846 return false; 1847 case Op_CompareAndSwapL: 1848 #ifdef _LP64 1849 case Op_CompareAndSwapP: 1850 #endif 1851 if (!VM_Version::supports_cx8()) 1852 return false; 1853 break; 1854 } 1855 1856 return true; // Per default match rules are supported. 1857 } 1858 1859 int Matcher::regnum_to_fpu_offset(int regnum) { 1860 return regnum - 32; // The FP registers are in the second chunk 1861 } 1862 1863 #ifdef ASSERT 1864 address last_rethrow = NULL; // debugging aid for Rethrow encoding 1865 #endif 1866 1867 // Vector width in bytes 1868 const int Matcher::vector_width_in_bytes(BasicType bt) { 1869 assert(MaxVectorSize == 8, ""); 1870 return 8; 1871 } 1872 1873 // Vector ideal reg 1874 const int Matcher::vector_ideal_reg(int size) { 1875 assert(MaxVectorSize == 8, ""); 1876 return Op_RegD; 1877 } 1878 1879 const int Matcher::vector_shift_count_ideal_reg(int size) { 1880 fatal("vector shift is not supported"); 1881 return Node::NotAMachineReg; 1882 } 1883 1884 // Limits on vector size (number of elements) loaded into vector. 1885 const int Matcher::max_vector_size(const BasicType bt) { 1886 assert(is_java_primitive(bt), "only primitive type vectors"); 1887 return vector_width_in_bytes(bt)/type2aelembytes(bt); 1888 } 1889 1890 const int Matcher::min_vector_size(const BasicType bt) { 1891 return max_vector_size(bt); // Same as max. 1892 } 1893 1894 // SPARC doesn't support misaligned vectors store/load. 1895 const bool Matcher::misaligned_vectors_ok() { 1896 return false; 1897 } 1898 1899 // Current (2013) SPARC platforms need to read original key 1900 // to construct decryption expanded key 1901 const bool Matcher::pass_original_key_for_aes() { 1902 return true; 1903 } 1904 1905 // USII supports fxtof through the whole range of number, USIII doesn't 1906 const bool Matcher::convL2FSupported(void) { 1907 return VM_Version::has_fast_fxtof(); 1908 } 1909 1910 // Is this branch offset short enough that a short branch can be used? 1911 // 1912 // NOTE: If the platform does not provide any short branch variants, then 1913 // this method should return false for offset 0. 1914 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1915 // The passed offset is relative to address of the branch. 1916 // Don't need to adjust the offset. 1917 return UseCBCond && Assembler::is_simm12(offset); 1918 } 1919 1920 const bool Matcher::isSimpleConstant64(jlong value) { 1921 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1922 // Depends on optimizations in MacroAssembler::setx. 1923 int hi = (int)(value >> 32); 1924 int lo = (int)(value & ~0); 1925 return (hi == 0) || (hi == -1) || (lo == 0); 1926 } 1927 1928 // No scaling for the parameter the ClearArray node. 1929 const bool Matcher::init_array_count_is_in_bytes = true; 1930 1931 // Threshold size for cleararray. 1932 const int Matcher::init_array_short_size = 8 * BytesPerLong; 1933 1934 // No additional cost for CMOVL. 1935 const int Matcher::long_cmove_cost() { return 0; } 1936 1937 // CMOVF/CMOVD are expensive on T4 and on SPARC64. 1938 const int Matcher::float_cmove_cost() { 1939 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; 1940 } 1941 1942 // Does the CPU require late expand (see block.cpp for description of late expand)? 1943 const bool Matcher::require_postalloc_expand = false; 1944 1945 // Should the Matcher clone shifts on addressing modes, expecting them to 1946 // be subsumed into complex addressing expressions or compute them into 1947 // registers? True for Intel but false for most RISCs 1948 const bool Matcher::clone_shift_expressions = false; 1949 1950 // Do we need to mask the count passed to shift instructions or does 1951 // the cpu only look at the lower 5/6 bits anyway? 1952 const bool Matcher::need_masked_shift_count = false; 1953 1954 bool Matcher::narrow_oop_use_complex_address() { 1955 NOT_LP64(ShouldNotCallThis()); 1956 assert(UseCompressedOops, "only for compressed oops code"); 1957 return false; 1958 } 1959 1960 bool Matcher::narrow_klass_use_complex_address() { 1961 NOT_LP64(ShouldNotCallThis()); 1962 assert(UseCompressedClassPointers, "only for compressed klass code"); 1963 return false; 1964 } 1965 1966 // Is it better to copy float constants, or load them directly from memory? 1967 // Intel can load a float constant from a direct address, requiring no 1968 // extra registers. Most RISCs will have to materialize an address into a 1969 // register first, so they would do better to copy the constant from stack. 1970 const bool Matcher::rematerialize_float_constants = false; 1971 1972 // If CPU can load and store mis-aligned doubles directly then no fixup is 1973 // needed. Else we split the double into 2 integer pieces and move it 1974 // piece-by-piece. Only happens when passing doubles into C code as the 1975 // Java calling convention forces doubles to be aligned. 1976 #ifdef _LP64 1977 const bool Matcher::misaligned_doubles_ok = true; 1978 #else 1979 const bool Matcher::misaligned_doubles_ok = false; 1980 #endif 1981 1982 // No-op on SPARC. 1983 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1984 } 1985 1986 // Advertise here if the CPU requires explicit rounding operations 1987 // to implement the UseStrictFP mode. 1988 const bool Matcher::strict_fp_requires_explicit_rounding = false; 1989 1990 // Are floats converted to double when stored to stack during deoptimization? 1991 // Sparc does not handle callee-save floats. 1992 bool Matcher::float_in_double() { return false; } 1993 1994 // Do ints take an entire long register or just half? 1995 // Note that we if-def off of _LP64. 1996 // The relevant question is how the int is callee-saved. In _LP64 1997 // the whole long is written but de-opt'ing will have to extract 1998 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 1999 #ifdef _LP64 2000 const bool Matcher::int_in_long = true; 2001 #else 2002 const bool Matcher::int_in_long = false; 2003 #endif 2004 2005 // Return whether or not this register is ever used as an argument. This 2006 // function is used on startup to build the trampoline stubs in generateOptoStub. 2007 // Registers not mentioned will be killed by the VM call in the trampoline, and 2008 // arguments in those registers not be available to the callee. 2009 bool Matcher::can_be_java_arg( int reg ) { 2010 // Standard sparc 6 args in registers 2011 if( reg == R_I0_num || 2012 reg == R_I1_num || 2013 reg == R_I2_num || 2014 reg == R_I3_num || 2015 reg == R_I4_num || 2016 reg == R_I5_num ) return true; 2017 #ifdef _LP64 2018 // 64-bit builds can pass 64-bit pointers and longs in 2019 // the high I registers 2020 if( reg == R_I0H_num || 2021 reg == R_I1H_num || 2022 reg == R_I2H_num || 2023 reg == R_I3H_num || 2024 reg == R_I4H_num || 2025 reg == R_I5H_num ) return true; 2026 2027 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 2028 return true; 2029 } 2030 2031 #else 2032 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. 2033 // Longs cannot be passed in O regs, because O regs become I regs 2034 // after a 'save' and I regs get their high bits chopped off on 2035 // interrupt. 2036 if( reg == R_G1H_num || reg == R_G1_num ) return true; 2037 if( reg == R_G4H_num || reg == R_G4_num ) return true; 2038 #endif 2039 // A few float args in registers 2040 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 2041 2042 return false; 2043 } 2044 2045 bool Matcher::is_spillable_arg( int reg ) { 2046 return can_be_java_arg(reg); 2047 } 2048 2049 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { 2050 // Use hardware SDIVX instruction when it is 2051 // faster than a code which use multiply. 2052 return VM_Version::has_fast_idiv(); 2053 } 2054 2055 // Register for DIVI projection of divmodI 2056 RegMask Matcher::divI_proj_mask() { 2057 ShouldNotReachHere(); 2058 return RegMask(); 2059 } 2060 2061 // Register for MODI projection of divmodI 2062 RegMask Matcher::modI_proj_mask() { 2063 ShouldNotReachHere(); 2064 return RegMask(); 2065 } 2066 2067 // Register for DIVL projection of divmodL 2068 RegMask Matcher::divL_proj_mask() { 2069 ShouldNotReachHere(); 2070 return RegMask(); 2071 } 2072 2073 // Register for MODL projection of divmodL 2074 RegMask Matcher::modL_proj_mask() { 2075 ShouldNotReachHere(); 2076 return RegMask(); 2077 } 2078 2079 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 2080 return L7_REGP_mask(); 2081 } 2082 2083 %} 2084 2085 2086 // The intptr_t operand types, defined by textual substitution. 2087 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 2088 #ifdef _LP64 2089 #define immX immL 2090 #define immX13 immL13 2091 #define immX13m7 immL13m7 2092 #define iRegX iRegL 2093 #define g1RegX g1RegL 2094 #else 2095 #define immX immI 2096 #define immX13 immI13 2097 #define immX13m7 immI13m7 2098 #define iRegX iRegI 2099 #define g1RegX g1RegI 2100 #endif 2101 2102 //----------ENCODING BLOCK----------------------------------------------------- 2103 // This block specifies the encoding classes used by the compiler to output 2104 // byte streams. Encoding classes are parameterized macros used by 2105 // Machine Instruction Nodes in order to generate the bit encoding of the 2106 // instruction. Operands specify their base encoding interface with the 2107 // interface keyword. There are currently supported four interfaces, 2108 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 2109 // operand to generate a function which returns its register number when 2110 // queried. CONST_INTER causes an operand to generate a function which 2111 // returns the value of the constant when queried. MEMORY_INTER causes an 2112 // operand to generate four functions which return the Base Register, the 2113 // Index Register, the Scale Value, and the Offset Value of the operand when 2114 // queried. COND_INTER causes an operand to generate six functions which 2115 // return the encoding code (ie - encoding bits for the instruction) 2116 // associated with each basic boolean condition for a conditional instruction. 2117 // 2118 // Instructions specify two basic values for encoding. Again, a function 2119 // is available to check if the constant displacement is an oop. They use the 2120 // ins_encode keyword to specify their encoding classes (which must be 2121 // a sequence of enc_class names, and their parameters, specified in 2122 // the encoding block), and they use the 2123 // opcode keyword to specify, in order, their primary, secondary, and 2124 // tertiary opcode. Only the opcode sections which a particular instruction 2125 // needs for encoding need to be specified. 2126 encode %{ 2127 enc_class enc_untested %{ 2128 #ifdef ASSERT 2129 MacroAssembler _masm(&cbuf); 2130 __ untested("encoding"); 2131 #endif 2132 %} 2133 2134 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 2135 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary, 2136 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2137 %} 2138 2139 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 2140 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2141 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2142 %} 2143 2144 enc_class form3_mem_prefetch_read( memory mem ) %{ 2145 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2146 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 2147 %} 2148 2149 enc_class form3_mem_prefetch_write( memory mem ) %{ 2150 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2151 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 2152 %} 2153 2154 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 2155 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2156 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2157 guarantee($mem$$index == R_G0_enc, "double index?"); 2158 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 2159 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 2160 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 2161 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 2162 %} 2163 2164 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 2165 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2166 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2167 guarantee($mem$$index == R_G0_enc, "double index?"); 2168 // Load long with 2 instructions 2169 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 2170 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 2171 %} 2172 2173 //%%% form3_mem_plus_4_reg is a hack--get rid of it 2174 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 2175 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 2176 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 2177 %} 2178 2179 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 2180 // Encode a reg-reg copy. If it is useless, then empty encoding. 2181 if( $rs2$$reg != $rd$$reg ) 2182 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 2183 %} 2184 2185 // Target lo half of long 2186 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 2187 // Encode a reg-reg copy. If it is useless, then empty encoding. 2188 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 2189 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 2190 %} 2191 2192 // Source lo half of long 2193 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 2194 // Encode a reg-reg copy. If it is useless, then empty encoding. 2195 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 2196 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 2197 %} 2198 2199 // Target hi half of long 2200 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 2201 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 2202 %} 2203 2204 // Source lo half of long, and leave it sign extended. 2205 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 2206 // Sign extend low half 2207 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 2208 %} 2209 2210 // Source hi half of long, and leave it sign extended. 2211 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 2212 // Shift high half to low half 2213 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2214 %} 2215 2216 // Source hi half of long 2217 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2218 // Encode a reg-reg copy. If it is useless, then empty encoding. 2219 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2220 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2221 %} 2222 2223 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2224 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2225 %} 2226 2227 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2228 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2229 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2230 %} 2231 2232 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2233 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2234 // clear if nothing else is happening 2235 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2236 // blt,a,pn done 2237 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2238 // mov dst,-1 in delay slot 2239 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2240 %} 2241 2242 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2243 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2244 %} 2245 2246 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2247 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2248 %} 2249 2250 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2251 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2252 %} 2253 2254 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2255 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2256 %} 2257 2258 enc_class move_return_pc_to_o1() %{ 2259 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2260 %} 2261 2262 #ifdef _LP64 2263 /* %%% merge with enc_to_bool */ 2264 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2265 MacroAssembler _masm(&cbuf); 2266 2267 Register src_reg = reg_to_register_object($src$$reg); 2268 Register dst_reg = reg_to_register_object($dst$$reg); 2269 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2270 %} 2271 #endif 2272 2273 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2274 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2275 MacroAssembler _masm(&cbuf); 2276 2277 Register p_reg = reg_to_register_object($p$$reg); 2278 Register q_reg = reg_to_register_object($q$$reg); 2279 Register y_reg = reg_to_register_object($y$$reg); 2280 Register tmp_reg = reg_to_register_object($tmp$$reg); 2281 2282 __ subcc( p_reg, q_reg, p_reg ); 2283 __ add ( p_reg, y_reg, tmp_reg ); 2284 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2285 %} 2286 2287 enc_class form_d2i_helper(regD src, regF dst) %{ 2288 // fcmp %fcc0,$src,$src 2289 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2290 // branch %fcc0 not-nan, predict taken 2291 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2292 // fdtoi $src,$dst 2293 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2294 // fitos $dst,$dst (if nan) 2295 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2296 // clear $dst (if nan) 2297 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2298 // carry on here... 2299 %} 2300 2301 enc_class form_d2l_helper(regD src, regD dst) %{ 2302 // fcmp %fcc0,$src,$src check for NAN 2303 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2304 // branch %fcc0 not-nan, predict taken 2305 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2306 // fdtox $src,$dst convert in delay slot 2307 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2308 // fxtod $dst,$dst (if nan) 2309 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2310 // clear $dst (if nan) 2311 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2312 // carry on here... 2313 %} 2314 2315 enc_class form_f2i_helper(regF src, regF dst) %{ 2316 // fcmps %fcc0,$src,$src 2317 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2318 // branch %fcc0 not-nan, predict taken 2319 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2320 // fstoi $src,$dst 2321 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2322 // fitos $dst,$dst (if nan) 2323 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2324 // clear $dst (if nan) 2325 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2326 // carry on here... 2327 %} 2328 2329 enc_class form_f2l_helper(regF src, regD dst) %{ 2330 // fcmps %fcc0,$src,$src 2331 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2332 // branch %fcc0 not-nan, predict taken 2333 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2334 // fstox $src,$dst 2335 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2336 // fxtod $dst,$dst (if nan) 2337 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2338 // clear $dst (if nan) 2339 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2340 // carry on here... 2341 %} 2342 2343 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2344 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2345 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2346 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2347 2348 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2349 2350 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2351 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2352 2353 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2354 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2355 %} 2356 2357 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2358 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2359 %} 2360 2361 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2362 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2363 %} 2364 2365 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2366 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2367 %} 2368 2369 enc_class form3_convI2F(regF rs2, regF rd) %{ 2370 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2371 %} 2372 2373 // Encloding class for traceable jumps 2374 enc_class form_jmpl(g3RegP dest) %{ 2375 emit_jmpl(cbuf, $dest$$reg); 2376 %} 2377 2378 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2379 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2380 %} 2381 2382 enc_class form2_nop() %{ 2383 emit_nop(cbuf); 2384 %} 2385 2386 enc_class form2_illtrap() %{ 2387 emit_illtrap(cbuf); 2388 %} 2389 2390 2391 // Compare longs and convert into -1, 0, 1. 2392 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2393 // CMP $src1,$src2 2394 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2395 // blt,a,pn done 2396 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2397 // mov dst,-1 in delay slot 2398 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2399 // bgt,a,pn done 2400 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2401 // mov dst,1 in delay slot 2402 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2403 // CLR $dst 2404 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2405 %} 2406 2407 enc_class enc_PartialSubtypeCheck() %{ 2408 MacroAssembler _masm(&cbuf); 2409 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2410 __ delayed()->nop(); 2411 %} 2412 2413 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ 2414 MacroAssembler _masm(&cbuf); 2415 Label* L = $labl$$label; 2416 Assembler::Predict predict_taken = 2417 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2418 2419 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 2420 __ delayed()->nop(); 2421 %} 2422 2423 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2424 MacroAssembler _masm(&cbuf); 2425 Label* L = $labl$$label; 2426 Assembler::Predict predict_taken = 2427 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2428 2429 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); 2430 __ delayed()->nop(); 2431 %} 2432 2433 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2434 int op = (Assembler::arith_op << 30) | 2435 ($dst$$reg << 25) | 2436 (Assembler::movcc_op3 << 19) | 2437 (1 << 18) | // cc2 bit for 'icc' 2438 ($cmp$$cmpcode << 14) | 2439 (0 << 13) | // select register move 2440 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2441 ($src$$reg << 0); 2442 cbuf.insts()->emit_int32(op); 2443 %} 2444 2445 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2446 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2447 int op = (Assembler::arith_op << 30) | 2448 ($dst$$reg << 25) | 2449 (Assembler::movcc_op3 << 19) | 2450 (1 << 18) | // cc2 bit for 'icc' 2451 ($cmp$$cmpcode << 14) | 2452 (1 << 13) | // select immediate move 2453 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2454 (simm11 << 0); 2455 cbuf.insts()->emit_int32(op); 2456 %} 2457 2458 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2459 int op = (Assembler::arith_op << 30) | 2460 ($dst$$reg << 25) | 2461 (Assembler::movcc_op3 << 19) | 2462 (0 << 18) | // cc2 bit for 'fccX' 2463 ($cmp$$cmpcode << 14) | 2464 (0 << 13) | // select register move 2465 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2466 ($src$$reg << 0); 2467 cbuf.insts()->emit_int32(op); 2468 %} 2469 2470 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2471 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2472 int op = (Assembler::arith_op << 30) | 2473 ($dst$$reg << 25) | 2474 (Assembler::movcc_op3 << 19) | 2475 (0 << 18) | // cc2 bit for 'fccX' 2476 ($cmp$$cmpcode << 14) | 2477 (1 << 13) | // select immediate move 2478 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2479 (simm11 << 0); 2480 cbuf.insts()->emit_int32(op); 2481 %} 2482 2483 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2484 int op = (Assembler::arith_op << 30) | 2485 ($dst$$reg << 25) | 2486 (Assembler::fpop2_op3 << 19) | 2487 (0 << 18) | 2488 ($cmp$$cmpcode << 14) | 2489 (1 << 13) | // select register move 2490 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2491 ($primary << 5) | // select single, double or quad 2492 ($src$$reg << 0); 2493 cbuf.insts()->emit_int32(op); 2494 %} 2495 2496 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2497 int op = (Assembler::arith_op << 30) | 2498 ($dst$$reg << 25) | 2499 (Assembler::fpop2_op3 << 19) | 2500 (0 << 18) | 2501 ($cmp$$cmpcode << 14) | 2502 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2503 ($primary << 5) | // select single, double or quad 2504 ($src$$reg << 0); 2505 cbuf.insts()->emit_int32(op); 2506 %} 2507 2508 // Used by the MIN/MAX encodings. Same as a CMOV, but 2509 // the condition comes from opcode-field instead of an argument. 2510 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2511 int op = (Assembler::arith_op << 30) | 2512 ($dst$$reg << 25) | 2513 (Assembler::movcc_op3 << 19) | 2514 (1 << 18) | // cc2 bit for 'icc' 2515 ($primary << 14) | 2516 (0 << 13) | // select register move 2517 (0 << 11) | // cc1, cc0 bits for 'icc' 2518 ($src$$reg << 0); 2519 cbuf.insts()->emit_int32(op); 2520 %} 2521 2522 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2523 int op = (Assembler::arith_op << 30) | 2524 ($dst$$reg << 25) | 2525 (Assembler::movcc_op3 << 19) | 2526 (6 << 16) | // cc2 bit for 'xcc' 2527 ($primary << 14) | 2528 (0 << 13) | // select register move 2529 (0 << 11) | // cc1, cc0 bits for 'icc' 2530 ($src$$reg << 0); 2531 cbuf.insts()->emit_int32(op); 2532 %} 2533 2534 enc_class Set13( immI13 src, iRegI rd ) %{ 2535 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2536 %} 2537 2538 enc_class SetHi22( immI src, iRegI rd ) %{ 2539 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2540 %} 2541 2542 enc_class Set32( immI src, iRegI rd ) %{ 2543 MacroAssembler _masm(&cbuf); 2544 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2545 %} 2546 2547 enc_class call_epilog %{ 2548 if( VerifyStackAtCalls ) { 2549 MacroAssembler _masm(&cbuf); 2550 int framesize = ra_->C->frame_size_in_bytes(); 2551 Register temp_reg = G3; 2552 __ add(SP, framesize, temp_reg); 2553 __ cmp(temp_reg, FP); 2554 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2555 } 2556 %} 2557 2558 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2559 // to G1 so the register allocator will not have to deal with the misaligned register 2560 // pair. 2561 enc_class adjust_long_from_native_call %{ 2562 #ifndef _LP64 2563 if (returns_long()) { 2564 // sllx O0,32,O0 2565 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); 2566 // srl O1,0,O1 2567 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); 2568 // or O0,O1,G1 2569 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); 2570 } 2571 #endif 2572 %} 2573 2574 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2575 // CALL directly to the runtime 2576 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2577 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, 2578 /*preserve_g2=*/true); 2579 %} 2580 2581 enc_class preserve_SP %{ 2582 MacroAssembler _masm(&cbuf); 2583 __ mov(SP, L7_mh_SP_save); 2584 %} 2585 2586 enc_class restore_SP %{ 2587 MacroAssembler _masm(&cbuf); 2588 __ mov(L7_mh_SP_save, SP); 2589 %} 2590 2591 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2592 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2593 // who we intended to call. 2594 if (!_method) { 2595 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); 2596 } else if (_optimized_virtual) { 2597 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); 2598 } else { 2599 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); 2600 } 2601 if (_method) { // Emit stub for static call. 2602 CompiledStaticCall::emit_to_interp_stub(cbuf); 2603 if (Compile::current()->env()->failing()) { return; } // CodeCache is full 2604 } 2605 %} 2606 2607 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2608 MacroAssembler _masm(&cbuf); 2609 __ set_inst_mark(); 2610 int vtable_index = this->_vtable_index; 2611 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2612 if (vtable_index < 0) { 2613 // must be invalid_vtable_index, not nonvirtual_vtable_index 2614 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 2615 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2616 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2617 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2618 __ ic_call((address)$meth$$method); 2619 } else { 2620 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2621 // Just go thru the vtable 2622 // get receiver klass (receiver already checked for non-null) 2623 // If we end up going thru a c2i adapter interpreter expects method in G5 2624 int off = __ offset(); 2625 __ load_klass(O0, G3_scratch); 2626 int klass_load_size; 2627 if (UseCompressedClassPointers) { 2628 assert(Universe::heap() != NULL, "java heap should be initialized"); 2629 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 2630 } else { 2631 klass_load_size = 1*BytesPerInstWord; 2632 } 2633 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 2634 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 2635 if (Assembler::is_simm13(v_off)) { 2636 __ ld_ptr(G3, v_off, G5_method); 2637 } else { 2638 // Generate 2 instructions 2639 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2640 __ or3(G5_method, v_off & 0x3ff, G5_method); 2641 // ld_ptr, set_hi, set 2642 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2643 "Unexpected instruction size(s)"); 2644 __ ld_ptr(G3, G5_method, G5_method); 2645 } 2646 // NOTE: for vtable dispatches, the vtable entry will never be null. 2647 // However it may very well end up in handle_wrong_method if the 2648 // method is abstract for the particular class. 2649 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); 2650 // jump to target (either compiled code or c2iadapter) 2651 __ jmpl(G3_scratch, G0, O7); 2652 __ delayed()->nop(); 2653 } 2654 %} 2655 2656 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2657 MacroAssembler _masm(&cbuf); 2658 2659 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2660 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2661 // we might be calling a C2I adapter which needs it. 2662 2663 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2664 // Load nmethod 2665 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); 2666 2667 // CALL to compiled java, indirect the contents of G3 2668 __ set_inst_mark(); 2669 __ callr(temp_reg, G0); 2670 __ delayed()->nop(); 2671 %} 2672 2673 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2674 MacroAssembler _masm(&cbuf); 2675 Register Rdividend = reg_to_register_object($src1$$reg); 2676 Register Rdivisor = reg_to_register_object($src2$$reg); 2677 Register Rresult = reg_to_register_object($dst$$reg); 2678 2679 __ sra(Rdivisor, 0, Rdivisor); 2680 __ sra(Rdividend, 0, Rdividend); 2681 __ sdivx(Rdividend, Rdivisor, Rresult); 2682 %} 2683 2684 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2685 MacroAssembler _masm(&cbuf); 2686 2687 Register Rdividend = reg_to_register_object($src1$$reg); 2688 int divisor = $imm$$constant; 2689 Register Rresult = reg_to_register_object($dst$$reg); 2690 2691 __ sra(Rdividend, 0, Rdividend); 2692 __ sdivx(Rdividend, divisor, Rresult); 2693 %} 2694 2695 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2696 MacroAssembler _masm(&cbuf); 2697 Register Rsrc1 = reg_to_register_object($src1$$reg); 2698 Register Rsrc2 = reg_to_register_object($src2$$reg); 2699 Register Rdst = reg_to_register_object($dst$$reg); 2700 2701 __ sra( Rsrc1, 0, Rsrc1 ); 2702 __ sra( Rsrc2, 0, Rsrc2 ); 2703 __ mulx( Rsrc1, Rsrc2, Rdst ); 2704 __ srlx( Rdst, 32, Rdst ); 2705 %} 2706 2707 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2708 MacroAssembler _masm(&cbuf); 2709 Register Rdividend = reg_to_register_object($src1$$reg); 2710 Register Rdivisor = reg_to_register_object($src2$$reg); 2711 Register Rresult = reg_to_register_object($dst$$reg); 2712 Register Rscratch = reg_to_register_object($scratch$$reg); 2713 2714 assert(Rdividend != Rscratch, ""); 2715 assert(Rdivisor != Rscratch, ""); 2716 2717 __ sra(Rdividend, 0, Rdividend); 2718 __ sra(Rdivisor, 0, Rdivisor); 2719 __ sdivx(Rdividend, Rdivisor, Rscratch); 2720 __ mulx(Rscratch, Rdivisor, Rscratch); 2721 __ sub(Rdividend, Rscratch, Rresult); 2722 %} 2723 2724 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2725 MacroAssembler _masm(&cbuf); 2726 2727 Register Rdividend = reg_to_register_object($src1$$reg); 2728 int divisor = $imm$$constant; 2729 Register Rresult = reg_to_register_object($dst$$reg); 2730 Register Rscratch = reg_to_register_object($scratch$$reg); 2731 2732 assert(Rdividend != Rscratch, ""); 2733 2734 __ sra(Rdividend, 0, Rdividend); 2735 __ sdivx(Rdividend, divisor, Rscratch); 2736 __ mulx(Rscratch, divisor, Rscratch); 2737 __ sub(Rdividend, Rscratch, Rresult); 2738 %} 2739 2740 enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2741 MacroAssembler _masm(&cbuf); 2742 2743 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2744 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2745 2746 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2747 %} 2748 2749 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2750 MacroAssembler _masm(&cbuf); 2751 2752 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2753 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2754 2755 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2756 %} 2757 2758 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2759 MacroAssembler _masm(&cbuf); 2760 2761 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2762 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2763 2764 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2765 %} 2766 2767 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2768 MacroAssembler _masm(&cbuf); 2769 2770 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2771 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2772 2773 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2774 %} 2775 2776 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2777 MacroAssembler _masm(&cbuf); 2778 2779 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2780 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2781 2782 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2783 %} 2784 2785 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2786 MacroAssembler _masm(&cbuf); 2787 2788 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2789 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2790 2791 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2792 %} 2793 2794 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2795 MacroAssembler _masm(&cbuf); 2796 2797 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2798 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2799 2800 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2801 %} 2802 2803 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2804 MacroAssembler _masm(&cbuf); 2805 2806 Register Roop = reg_to_register_object($oop$$reg); 2807 Register Rbox = reg_to_register_object($box$$reg); 2808 Register Rscratch = reg_to_register_object($scratch$$reg); 2809 Register Rmark = reg_to_register_object($scratch2$$reg); 2810 2811 assert(Roop != Rscratch, ""); 2812 assert(Roop != Rmark, ""); 2813 assert(Rbox != Rscratch, ""); 2814 assert(Rbox != Rmark, ""); 2815 2816 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); 2817 %} 2818 2819 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2820 MacroAssembler _masm(&cbuf); 2821 2822 Register Roop = reg_to_register_object($oop$$reg); 2823 Register Rbox = reg_to_register_object($box$$reg); 2824 Register Rscratch = reg_to_register_object($scratch$$reg); 2825 Register Rmark = reg_to_register_object($scratch2$$reg); 2826 2827 assert(Roop != Rscratch, ""); 2828 assert(Roop != Rmark, ""); 2829 assert(Rbox != Rscratch, ""); 2830 assert(Rbox != Rmark, ""); 2831 2832 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); 2833 %} 2834 2835 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2836 MacroAssembler _masm(&cbuf); 2837 Register Rmem = reg_to_register_object($mem$$reg); 2838 Register Rold = reg_to_register_object($old$$reg); 2839 Register Rnew = reg_to_register_object($new$$reg); 2840 2841 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold 2842 __ cmp( Rold, Rnew ); 2843 %} 2844 2845 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2846 Register Rmem = reg_to_register_object($mem$$reg); 2847 Register Rold = reg_to_register_object($old$$reg); 2848 Register Rnew = reg_to_register_object($new$$reg); 2849 2850 MacroAssembler _masm(&cbuf); 2851 __ mov(Rnew, O7); 2852 __ casx(Rmem, Rold, O7); 2853 __ cmp( Rold, O7 ); 2854 %} 2855 2856 // raw int cas, used for compareAndSwap 2857 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2858 Register Rmem = reg_to_register_object($mem$$reg); 2859 Register Rold = reg_to_register_object($old$$reg); 2860 Register Rnew = reg_to_register_object($new$$reg); 2861 2862 MacroAssembler _masm(&cbuf); 2863 __ mov(Rnew, O7); 2864 __ cas(Rmem, Rold, O7); 2865 __ cmp( Rold, O7 ); 2866 %} 2867 2868 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2869 Register Rres = reg_to_register_object($res$$reg); 2870 2871 MacroAssembler _masm(&cbuf); 2872 __ mov(1, Rres); 2873 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2874 %} 2875 2876 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2877 Register Rres = reg_to_register_object($res$$reg); 2878 2879 MacroAssembler _masm(&cbuf); 2880 __ mov(1, Rres); 2881 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2882 %} 2883 2884 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2885 MacroAssembler _masm(&cbuf); 2886 Register Rdst = reg_to_register_object($dst$$reg); 2887 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2888 : reg_to_DoubleFloatRegister_object($src1$$reg); 2889 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2890 : reg_to_DoubleFloatRegister_object($src2$$reg); 2891 2892 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2893 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2894 %} 2895 2896 2897 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ 2898 Label Ldone, Lloop; 2899 MacroAssembler _masm(&cbuf); 2900 2901 Register str1_reg = reg_to_register_object($str1$$reg); 2902 Register str2_reg = reg_to_register_object($str2$$reg); 2903 Register cnt1_reg = reg_to_register_object($cnt1$$reg); 2904 Register cnt2_reg = reg_to_register_object($cnt2$$reg); 2905 Register result_reg = reg_to_register_object($result$$reg); 2906 2907 assert(result_reg != str1_reg && 2908 result_reg != str2_reg && 2909 result_reg != cnt1_reg && 2910 result_reg != cnt2_reg , 2911 "need different registers"); 2912 2913 // Compute the minimum of the string lengths(str1_reg) and the 2914 // difference of the string lengths (stack) 2915 2916 // See if the lengths are different, and calculate min in str1_reg. 2917 // Stash diff in O7 in case we need it for a tie-breaker. 2918 Label Lskip; 2919 __ subcc(cnt1_reg, cnt2_reg, O7); 2920 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit 2921 __ br(Assembler::greater, true, Assembler::pt, Lskip); 2922 // cnt2 is shorter, so use its count: 2923 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit 2924 __ bind(Lskip); 2925 2926 // reallocate cnt1_reg, cnt2_reg, result_reg 2927 // Note: limit_reg holds the string length pre-scaled by 2 2928 Register limit_reg = cnt1_reg; 2929 Register chr2_reg = cnt2_reg; 2930 Register chr1_reg = result_reg; 2931 // str{12} are the base pointers 2932 2933 // Is the minimum length zero? 2934 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity 2935 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2936 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2937 2938 // Load first characters 2939 __ lduh(str1_reg, 0, chr1_reg); 2940 __ lduh(str2_reg, 0, chr2_reg); 2941 2942 // Compare first characters 2943 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2944 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2945 assert(chr1_reg == result_reg, "result must be pre-placed"); 2946 __ delayed()->nop(); 2947 2948 { 2949 // Check after comparing first character to see if strings are equivalent 2950 Label LSkip2; 2951 // Check if the strings start at same location 2952 __ cmp(str1_reg, str2_reg); 2953 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); 2954 __ delayed()->nop(); 2955 2956 // Check if the length difference is zero (in O7) 2957 __ cmp(G0, O7); 2958 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2959 __ delayed()->mov(G0, result_reg); // result is zero 2960 2961 // Strings might not be equal 2962 __ bind(LSkip2); 2963 } 2964 2965 // We have no guarantee that on 64 bit the higher half of limit_reg is 0 2966 __ signx(limit_reg); 2967 2968 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); 2969 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2970 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2971 2972 // Shift str1_reg and str2_reg to the end of the arrays, negate limit 2973 __ add(str1_reg, limit_reg, str1_reg); 2974 __ add(str2_reg, limit_reg, str2_reg); 2975 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) 2976 2977 // Compare the rest of the characters 2978 __ lduh(str1_reg, limit_reg, chr1_reg); 2979 __ bind(Lloop); 2980 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2981 __ lduh(str2_reg, limit_reg, chr2_reg); 2982 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2983 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2984 assert(chr1_reg == result_reg, "result must be pre-placed"); 2985 __ delayed()->inccc(limit_reg, sizeof(jchar)); 2986 // annul LDUH if branch is not taken to prevent access past end of string 2987 __ br(Assembler::notZero, true, Assembler::pt, Lloop); 2988 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2989 2990 // If strings are equal up to min length, return the length difference. 2991 __ mov(O7, result_reg); 2992 2993 // Otherwise, return the difference between the first mismatched chars. 2994 __ bind(Ldone); 2995 %} 2996 2997 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ 2998 Label Lchar, Lchar_loop, Ldone; 2999 MacroAssembler _masm(&cbuf); 3000 3001 Register str1_reg = reg_to_register_object($str1$$reg); 3002 Register str2_reg = reg_to_register_object($str2$$reg); 3003 Register cnt_reg = reg_to_register_object($cnt$$reg); 3004 Register tmp1_reg = O7; 3005 Register result_reg = reg_to_register_object($result$$reg); 3006 3007 assert(result_reg != str1_reg && 3008 result_reg != str2_reg && 3009 result_reg != cnt_reg && 3010 result_reg != tmp1_reg , 3011 "need different registers"); 3012 3013 __ cmp(str1_reg, str2_reg); //same char[] ? 3014 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 3015 __ delayed()->add(G0, 1, result_reg); 3016 3017 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn); 3018 __ delayed()->add(G0, 1, result_reg); // count == 0 3019 3020 //rename registers 3021 Register limit_reg = cnt_reg; 3022 Register chr1_reg = result_reg; 3023 Register chr2_reg = tmp1_reg; 3024 3025 // We have no guarantee that on 64 bit the higher half of limit_reg is 0 3026 __ signx(limit_reg); 3027 3028 //check for alignment and position the pointers to the ends 3029 __ or3(str1_reg, str2_reg, chr1_reg); 3030 __ andcc(chr1_reg, 0x3, chr1_reg); 3031 // notZero means at least one not 4-byte aligned. 3032 // We could optimize the case when both arrays are not aligned 3033 // but it is not frequent case and it requires additional checks. 3034 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare 3035 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count 3036 3037 // Compare char[] arrays aligned to 4 bytes. 3038 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, 3039 chr1_reg, chr2_reg, Ldone); 3040 __ ba(Ldone); 3041 __ delayed()->add(G0, 1, result_reg); 3042 3043 // char by char compare 3044 __ bind(Lchar); 3045 __ add(str1_reg, limit_reg, str1_reg); 3046 __ add(str2_reg, limit_reg, str2_reg); 3047 __ neg(limit_reg); //negate count 3048 3049 __ lduh(str1_reg, limit_reg, chr1_reg); 3050 // Lchar_loop 3051 __ bind(Lchar_loop); 3052 __ lduh(str2_reg, limit_reg, chr2_reg); 3053 __ cmp(chr1_reg, chr2_reg); 3054 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 3055 __ delayed()->mov(G0, result_reg); //not equal 3056 __ inccc(limit_reg, sizeof(jchar)); 3057 // annul LDUH if branch is not taken to prevent access past end of string 3058 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); 3059 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted 3060 3061 __ add(G0, 1, result_reg); //equal 3062 3063 __ bind(Ldone); 3064 %} 3065 3066 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ 3067 Label Lvector, Ldone, Lloop; 3068 MacroAssembler _masm(&cbuf); 3069 3070 Register ary1_reg = reg_to_register_object($ary1$$reg); 3071 Register ary2_reg = reg_to_register_object($ary2$$reg); 3072 Register tmp1_reg = reg_to_register_object($tmp1$$reg); 3073 Register tmp2_reg = O7; 3074 Register result_reg = reg_to_register_object($result$$reg); 3075 3076 int length_offset = arrayOopDesc::length_offset_in_bytes(); 3077 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 3078 3079 // return true if the same array 3080 __ cmp(ary1_reg, ary2_reg); 3081 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 3082 __ delayed()->add(G0, 1, result_reg); // equal 3083 3084 __ br_null(ary1_reg, true, Assembler::pn, Ldone); 3085 __ delayed()->mov(G0, result_reg); // not equal 3086 3087 __ br_null(ary2_reg, true, Assembler::pn, Ldone); 3088 __ delayed()->mov(G0, result_reg); // not equal 3089 3090 //load the lengths of arrays 3091 __ ld(Address(ary1_reg, length_offset), tmp1_reg); 3092 __ ld(Address(ary2_reg, length_offset), tmp2_reg); 3093 3094 // return false if the two arrays are not equal length 3095 __ cmp(tmp1_reg, tmp2_reg); 3096 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); 3097 __ delayed()->mov(G0, result_reg); // not equal 3098 3099 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn); 3100 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal 3101 3102 // load array addresses 3103 __ add(ary1_reg, base_offset, ary1_reg); 3104 __ add(ary2_reg, base_offset, ary2_reg); 3105 3106 // renaming registers 3107 Register chr1_reg = result_reg; // for characters in ary1 3108 Register chr2_reg = tmp2_reg; // for characters in ary2 3109 Register limit_reg = tmp1_reg; // length 3110 3111 // set byte count 3112 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); 3113 3114 // Compare char[] arrays aligned to 4 bytes. 3115 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, 3116 chr1_reg, chr2_reg, Ldone); 3117 __ add(G0, 1, result_reg); // equals 3118 3119 __ bind(Ldone); 3120 %} 3121 3122 enc_class enc_rethrow() %{ 3123 cbuf.set_insts_mark(); 3124 Register temp_reg = G3; 3125 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 3126 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 3127 MacroAssembler _masm(&cbuf); 3128 #ifdef ASSERT 3129 __ save_frame(0); 3130 AddressLiteral last_rethrow_addrlit(&last_rethrow); 3131 __ sethi(last_rethrow_addrlit, L1); 3132 Address addr(L1, last_rethrow_addrlit.low10()); 3133 __ rdpc(L2); 3134 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 3135 __ st_ptr(L2, addr); 3136 __ restore(); 3137 #endif 3138 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp 3139 __ delayed()->nop(); 3140 %} 3141 3142 enc_class emit_mem_nop() %{ 3143 // Generates the instruction LDUXA [o6,g0],#0x82,g0 3144 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); 3145 %} 3146 3147 enc_class emit_fadd_nop() %{ 3148 // Generates the instruction FMOVS f31,f31 3149 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); 3150 %} 3151 3152 enc_class emit_br_nop() %{ 3153 // Generates the instruction BPN,PN . 3154 cbuf.insts()->emit_int32((unsigned int) 0x00400000); 3155 %} 3156 3157 enc_class enc_membar_acquire %{ 3158 MacroAssembler _masm(&cbuf); 3159 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 3160 %} 3161 3162 enc_class enc_membar_release %{ 3163 MacroAssembler _masm(&cbuf); 3164 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 3165 %} 3166 3167 enc_class enc_membar_volatile %{ 3168 MacroAssembler _masm(&cbuf); 3169 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3170 %} 3171 3172 %} 3173 3174 //----------FRAME-------------------------------------------------------------- 3175 // Definition of frame structure and management information. 3176 // 3177 // S T A C K L A Y O U T Allocators stack-slot number 3178 // | (to get allocators register number 3179 // G Owned by | | v add VMRegImpl::stack0) 3180 // r CALLER | | 3181 // o | +--------+ pad to even-align allocators stack-slot 3182 // w V | pad0 | numbers; owned by CALLER 3183 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned 3184 // h ^ | in | 5 3185 // | | args | 4 Holes in incoming args owned by SELF 3186 // | | | | 3 3187 // | | +--------+ 3188 // V | | old out| Empty on Intel, window on Sparc 3189 // | old |preserve| Must be even aligned. 3190 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 3191 // | | in | 3 area for Intel ret address 3192 // Owned by |preserve| Empty on Sparc. 3193 // SELF +--------+ 3194 // | | pad2 | 2 pad to align old SP 3195 // | +--------+ 1 3196 // | | locks | 0 3197 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 3198 // | | pad1 | 11 pad to align new SP 3199 // | +--------+ 3200 // | | | 10 3201 // | | spills | 9 spills 3202 // V | | 8 (pad0 slot for callee) 3203 // -----------+--------+----> Matcher::_out_arg_limit, unaligned 3204 // ^ | out | 7 3205 // | | args | 6 Holes in outgoing args owned by CALLEE 3206 // Owned by +--------+ 3207 // CALLEE | new out| 6 Empty on Intel, window on Sparc 3208 // | new |preserve| Must be even-aligned. 3209 // | SP-+--------+----> Matcher::_new_SP, even aligned 3210 // | | | 3211 // 3212 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 3213 // known from SELF's arguments and the Java calling convention. 3214 // Region 6-7 is determined per call site. 3215 // Note 2: If the calling convention leaves holes in the incoming argument 3216 // area, those holes are owned by SELF. Holes in the outgoing area 3217 // are owned by the CALLEE. Holes should not be nessecary in the 3218 // incoming area, as the Java calling convention is completely under 3219 // the control of the AD file. Doubles can be sorted and packed to 3220 // avoid holes. Holes in the outgoing arguments may be necessary for 3221 // varargs C calling conventions. 3222 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 3223 // even aligned with pad0 as needed. 3224 // Region 6 is even aligned. Region 6-7 is NOT even aligned; 3225 // region 6-11 is even aligned; it may be padded out more so that 3226 // the region from SP to FP meets the minimum stack alignment. 3227 3228 frame %{ 3229 // What direction does stack grow in (assumed to be same for native & Java) 3230 stack_direction(TOWARDS_LOW); 3231 3232 // These two registers define part of the calling convention 3233 // between compiled code and the interpreter. 3234 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C 3235 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 3236 3237 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 3238 cisc_spilling_operand_name(indOffset); 3239 3240 // Number of stack slots consumed by a Monitor enter 3241 #ifdef _LP64 3242 sync_stack_slots(2); 3243 #else 3244 sync_stack_slots(1); 3245 #endif 3246 3247 // Compiled code's Frame Pointer 3248 frame_pointer(R_SP); 3249 3250 // Stack alignment requirement 3251 stack_alignment(StackAlignmentInBytes); 3252 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 3253 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 3254 3255 // Number of stack slots between incoming argument block and the start of 3256 // a new frame. The PROLOG must add this many slots to the stack. The 3257 // EPILOG must remove this many slots. 3258 in_preserve_stack_slots(0); 3259 3260 // Number of outgoing stack slots killed above the out_preserve_stack_slots 3261 // for calls to C. Supports the var-args backing area for register parms. 3262 // ADLC doesn't support parsing expressions, so I folded the math by hand. 3263 #ifdef _LP64 3264 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 3265 varargs_C_out_slots_killed(12); 3266 #else 3267 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word 3268 varargs_C_out_slots_killed( 7); 3269 #endif 3270 3271 // The after-PROLOG location of the return address. Location of 3272 // return address specifies a type (REG or STACK) and a number 3273 // representing the register number (i.e. - use a register name) or 3274 // stack slot. 3275 return_addr(REG R_I7); // Ret Addr is in register I7 3276 3277 // Body of function which returns an OptoRegs array locating 3278 // arguments either in registers or in stack slots for calling 3279 // java 3280 calling_convention %{ 3281 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 3282 3283 %} 3284 3285 // Body of function which returns an OptoRegs array locating 3286 // arguments either in registers or in stack slots for calling 3287 // C. 3288 c_calling_convention %{ 3289 // This is obviously always outgoing 3290 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 3291 %} 3292 3293 // Location of native (C/C++) and interpreter return values. This is specified to 3294 // be the same as Java. In the 32-bit VM, long values are actually returned from 3295 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 3296 // to and from the register pairs is done by the appropriate call and epilog 3297 // opcodes. This simplifies the register allocator. 3298 c_return_value %{ 3299 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3300 #ifdef _LP64 3301 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3302 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3303 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3304 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3305 #else // !_LP64 3306 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3307 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3308 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3309 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3310 #endif 3311 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3312 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3313 %} 3314 3315 // Location of compiled Java return values. Same as C 3316 return_value %{ 3317 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3318 #ifdef _LP64 3319 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3320 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3321 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3322 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3323 #else // !_LP64 3324 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3325 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3326 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3327 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3328 #endif 3329 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3330 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3331 %} 3332 3333 %} 3334 3335 3336 //----------ATTRIBUTES--------------------------------------------------------- 3337 //----------Operand Attributes------------------------------------------------- 3338 op_attrib op_cost(1); // Required cost attribute 3339 3340 //----------Instruction Attributes--------------------------------------------- 3341 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 3342 ins_attrib ins_size(32); // Required size attribute (in bits) 3343 3344 // avoid_back_to_back attribute is an expression that must return 3345 // one of the following values defined in MachNode: 3346 // AVOID_NONE - instruction can be placed anywhere 3347 // AVOID_BEFORE - instruction cannot be placed after an 3348 // instruction with MachNode::AVOID_AFTER 3349 // AVOID_AFTER - the next instruction cannot be the one 3350 // with MachNode::AVOID_BEFORE 3351 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at 3352 // the same time 3353 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE); 3354 3355 ins_attrib ins_short_branch(0); // Required flag: is this instruction a 3356 // non-matching short branch variant of some 3357 // long branch? 3358 3359 //----------OPERANDS----------------------------------------------------------- 3360 // Operand definitions must precede instruction definitions for correct parsing 3361 // in the ADLC because operands constitute user defined types which are used in 3362 // instruction definitions. 3363 3364 //----------Simple Operands---------------------------------------------------- 3365 // Immediate Operands 3366 // Integer Immediate: 32-bit 3367 operand immI() %{ 3368 match(ConI); 3369 3370 op_cost(0); 3371 // formats are generated automatically for constants and base registers 3372 format %{ %} 3373 interface(CONST_INTER); 3374 %} 3375 3376 // Integer Immediate: 0-bit 3377 operand immI0() %{ 3378 predicate(n->get_int() == 0); 3379 match(ConI); 3380 op_cost(0); 3381 3382 format %{ %} 3383 interface(CONST_INTER); 3384 %} 3385 3386 // Integer Immediate: 5-bit 3387 operand immI5() %{ 3388 predicate(Assembler::is_simm5(n->get_int())); 3389 match(ConI); 3390 op_cost(0); 3391 format %{ %} 3392 interface(CONST_INTER); 3393 %} 3394 3395 // Integer Immediate: 8-bit 3396 operand immI8() %{ 3397 predicate(Assembler::is_simm8(n->get_int())); 3398 match(ConI); 3399 op_cost(0); 3400 format %{ %} 3401 interface(CONST_INTER); 3402 %} 3403 3404 // Integer Immediate: the value 10 3405 operand immI10() %{ 3406 predicate(n->get_int() == 10); 3407 match(ConI); 3408 op_cost(0); 3409 3410 format %{ %} 3411 interface(CONST_INTER); 3412 %} 3413 3414 // Integer Immediate: 11-bit 3415 operand immI11() %{ 3416 predicate(Assembler::is_simm11(n->get_int())); 3417 match(ConI); 3418 op_cost(0); 3419 format %{ %} 3420 interface(CONST_INTER); 3421 %} 3422 3423 // Integer Immediate: 13-bit 3424 operand immI13() %{ 3425 predicate(Assembler::is_simm13(n->get_int())); 3426 match(ConI); 3427 op_cost(0); 3428 3429 format %{ %} 3430 interface(CONST_INTER); 3431 %} 3432 3433 // Integer Immediate: 13-bit minus 7 3434 operand immI13m7() %{ 3435 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); 3436 match(ConI); 3437 op_cost(0); 3438 3439 format %{ %} 3440 interface(CONST_INTER); 3441 %} 3442 3443 // Integer Immediate: 16-bit 3444 operand immI16() %{ 3445 predicate(Assembler::is_simm16(n->get_int())); 3446 match(ConI); 3447 op_cost(0); 3448 format %{ %} 3449 interface(CONST_INTER); 3450 %} 3451 3452 // Integer Immediate: the values 1-31 3453 operand immI_1_31() %{ 3454 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3455 match(ConI); 3456 op_cost(0); 3457 3458 format %{ %} 3459 interface(CONST_INTER); 3460 %} 3461 3462 // Integer Immediate: the values 32-63 3463 operand immI_32_63() %{ 3464 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3465 match(ConI); 3466 op_cost(0); 3467 3468 format %{ %} 3469 interface(CONST_INTER); 3470 %} 3471 3472 // Immediates for special shifts (sign extend) 3473 3474 // Integer Immediate: the value 16 3475 operand immI_16() %{ 3476 predicate(n->get_int() == 16); 3477 match(ConI); 3478 op_cost(0); 3479 3480 format %{ %} 3481 interface(CONST_INTER); 3482 %} 3483 3484 // Integer Immediate: the value 24 3485 operand immI_24() %{ 3486 predicate(n->get_int() == 24); 3487 match(ConI); 3488 op_cost(0); 3489 3490 format %{ %} 3491 interface(CONST_INTER); 3492 %} 3493 // Integer Immediate: the value 255 3494 operand immI_255() %{ 3495 predicate( n->get_int() == 255 ); 3496 match(ConI); 3497 op_cost(0); 3498 3499 format %{ %} 3500 interface(CONST_INTER); 3501 %} 3502 3503 // Integer Immediate: the value 65535 3504 operand immI_65535() %{ 3505 predicate(n->get_int() == 65535); 3506 match(ConI); 3507 op_cost(0); 3508 3509 format %{ %} 3510 interface(CONST_INTER); 3511 %} 3512 3513 // Integer Immediate: the values 0-31 3514 operand immU5() %{ 3515 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3516 match(ConI); 3517 op_cost(0); 3518 3519 format %{ %} 3520 interface(CONST_INTER); 3521 %} 3522 3523 // Integer Immediate: 6-bit 3524 operand immU6() %{ 3525 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3526 match(ConI); 3527 op_cost(0); 3528 format %{ %} 3529 interface(CONST_INTER); 3530 %} 3531 3532 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) 3533 operand immU12() %{ 3534 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3535 match(ConI); 3536 op_cost(0); 3537 3538 format %{ %} 3539 interface(CONST_INTER); 3540 %} 3541 3542 // Integer Immediate non-negative 3543 operand immU31() 3544 %{ 3545 predicate(n->get_int() >= 0); 3546 match(ConI); 3547 3548 op_cost(0); 3549 format %{ %} 3550 interface(CONST_INTER); 3551 %} 3552 3553 // Long Immediate: the value FF 3554 operand immL_FF() %{ 3555 predicate( n->get_long() == 0xFFL ); 3556 match(ConL); 3557 op_cost(0); 3558 3559 format %{ %} 3560 interface(CONST_INTER); 3561 %} 3562 3563 // Long Immediate: the value FFFF 3564 operand immL_FFFF() %{ 3565 predicate( n->get_long() == 0xFFFFL ); 3566 match(ConL); 3567 op_cost(0); 3568 3569 format %{ %} 3570 interface(CONST_INTER); 3571 %} 3572 3573 // Pointer Immediate: 32 or 64-bit 3574 operand immP() %{ 3575 match(ConP); 3576 3577 op_cost(5); 3578 // formats are generated automatically for constants and base registers 3579 format %{ %} 3580 interface(CONST_INTER); 3581 %} 3582 3583 #ifdef _LP64 3584 // Pointer Immediate: 64-bit 3585 operand immP_set() %{ 3586 predicate(!VM_Version::is_niagara_plus()); 3587 match(ConP); 3588 3589 op_cost(5); 3590 // formats are generated automatically for constants and base registers 3591 format %{ %} 3592 interface(CONST_INTER); 3593 %} 3594 3595 // Pointer Immediate: 64-bit 3596 // From Niagara2 processors on a load should be better than materializing. 3597 operand immP_load() %{ 3598 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); 3599 match(ConP); 3600 3601 op_cost(5); 3602 // formats are generated automatically for constants and base registers 3603 format %{ %} 3604 interface(CONST_INTER); 3605 %} 3606 3607 // Pointer Immediate: 64-bit 3608 operand immP_no_oop_cheap() %{ 3609 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); 3610 match(ConP); 3611 3612 op_cost(5); 3613 // formats are generated automatically for constants and base registers 3614 format %{ %} 3615 interface(CONST_INTER); 3616 %} 3617 #endif 3618 3619 operand immP13() %{ 3620 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3621 match(ConP); 3622 op_cost(0); 3623 3624 format %{ %} 3625 interface(CONST_INTER); 3626 %} 3627 3628 operand immP0() %{ 3629 predicate(n->get_ptr() == 0); 3630 match(ConP); 3631 op_cost(0); 3632 3633 format %{ %} 3634 interface(CONST_INTER); 3635 %} 3636 3637 operand immP_poll() %{ 3638 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3639 match(ConP); 3640 3641 // formats are generated automatically for constants and base registers 3642 format %{ %} 3643 interface(CONST_INTER); 3644 %} 3645 3646 // Pointer Immediate 3647 operand immN() 3648 %{ 3649 match(ConN); 3650 3651 op_cost(10); 3652 format %{ %} 3653 interface(CONST_INTER); 3654 %} 3655 3656 operand immNKlass() 3657 %{ 3658 match(ConNKlass); 3659 3660 op_cost(10); 3661 format %{ %} 3662 interface(CONST_INTER); 3663 %} 3664 3665 // NULL Pointer Immediate 3666 operand immN0() 3667 %{ 3668 predicate(n->get_narrowcon() == 0); 3669 match(ConN); 3670 3671 op_cost(0); 3672 format %{ %} 3673 interface(CONST_INTER); 3674 %} 3675 3676 operand immL() %{ 3677 match(ConL); 3678 op_cost(40); 3679 // formats are generated automatically for constants and base registers 3680 format %{ %} 3681 interface(CONST_INTER); 3682 %} 3683 3684 operand immL0() %{ 3685 predicate(n->get_long() == 0L); 3686 match(ConL); 3687 op_cost(0); 3688 // formats are generated automatically for constants and base registers 3689 format %{ %} 3690 interface(CONST_INTER); 3691 %} 3692 3693 // Integer Immediate: 5-bit 3694 operand immL5() %{ 3695 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); 3696 match(ConL); 3697 op_cost(0); 3698 format %{ %} 3699 interface(CONST_INTER); 3700 %} 3701 3702 // Long Immediate: 13-bit 3703 operand immL13() %{ 3704 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3705 match(ConL); 3706 op_cost(0); 3707 3708 format %{ %} 3709 interface(CONST_INTER); 3710 %} 3711 3712 // Long Immediate: 13-bit minus 7 3713 operand immL13m7() %{ 3714 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); 3715 match(ConL); 3716 op_cost(0); 3717 3718 format %{ %} 3719 interface(CONST_INTER); 3720 %} 3721 3722 // Long Immediate: low 32-bit mask 3723 operand immL_32bits() %{ 3724 predicate(n->get_long() == 0xFFFFFFFFL); 3725 match(ConL); 3726 op_cost(0); 3727 3728 format %{ %} 3729 interface(CONST_INTER); 3730 %} 3731 3732 // Long Immediate: cheap (materialize in <= 3 instructions) 3733 operand immL_cheap() %{ 3734 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); 3735 match(ConL); 3736 op_cost(0); 3737 3738 format %{ %} 3739 interface(CONST_INTER); 3740 %} 3741 3742 // Long Immediate: expensive (materialize in > 3 instructions) 3743 operand immL_expensive() %{ 3744 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); 3745 match(ConL); 3746 op_cost(0); 3747 3748 format %{ %} 3749 interface(CONST_INTER); 3750 %} 3751 3752 // Double Immediate 3753 operand immD() %{ 3754 match(ConD); 3755 3756 op_cost(40); 3757 format %{ %} 3758 interface(CONST_INTER); 3759 %} 3760 3761 // Double Immediate: +0.0d 3762 operand immD0() %{ 3763 predicate(jlong_cast(n->getd()) == 0); 3764 match(ConD); 3765 3766 op_cost(0); 3767 format %{ %} 3768 interface(CONST_INTER); 3769 %} 3770 3771 // Float Immediate 3772 operand immF() %{ 3773 match(ConF); 3774 3775 op_cost(20); 3776 format %{ %} 3777 interface(CONST_INTER); 3778 %} 3779 3780 // Float Immediate: +0.0f 3781 operand immF0() %{ 3782 predicate(jint_cast(n->getf()) == 0); 3783 match(ConF); 3784 3785 op_cost(0); 3786 format %{ %} 3787 interface(CONST_INTER); 3788 %} 3789 3790 // Integer Register Operands 3791 // Integer Register 3792 operand iRegI() %{ 3793 constraint(ALLOC_IN_RC(int_reg)); 3794 match(RegI); 3795 3796 match(notemp_iRegI); 3797 match(g1RegI); 3798 match(o0RegI); 3799 match(iRegIsafe); 3800 3801 format %{ %} 3802 interface(REG_INTER); 3803 %} 3804 3805 operand notemp_iRegI() %{ 3806 constraint(ALLOC_IN_RC(notemp_int_reg)); 3807 match(RegI); 3808 3809 match(o0RegI); 3810 3811 format %{ %} 3812 interface(REG_INTER); 3813 %} 3814 3815 operand o0RegI() %{ 3816 constraint(ALLOC_IN_RC(o0_regI)); 3817 match(iRegI); 3818 3819 format %{ %} 3820 interface(REG_INTER); 3821 %} 3822 3823 // Pointer Register 3824 operand iRegP() %{ 3825 constraint(ALLOC_IN_RC(ptr_reg)); 3826 match(RegP); 3827 3828 match(lock_ptr_RegP); 3829 match(g1RegP); 3830 match(g2RegP); 3831 match(g3RegP); 3832 match(g4RegP); 3833 match(i0RegP); 3834 match(o0RegP); 3835 match(o1RegP); 3836 match(l7RegP); 3837 3838 format %{ %} 3839 interface(REG_INTER); 3840 %} 3841 3842 operand sp_ptr_RegP() %{ 3843 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3844 match(RegP); 3845 match(iRegP); 3846 3847 format %{ %} 3848 interface(REG_INTER); 3849 %} 3850 3851 operand lock_ptr_RegP() %{ 3852 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3853 match(RegP); 3854 match(i0RegP); 3855 match(o0RegP); 3856 match(o1RegP); 3857 match(l7RegP); 3858 3859 format %{ %} 3860 interface(REG_INTER); 3861 %} 3862 3863 operand g1RegP() %{ 3864 constraint(ALLOC_IN_RC(g1_regP)); 3865 match(iRegP); 3866 3867 format %{ %} 3868 interface(REG_INTER); 3869 %} 3870 3871 operand g2RegP() %{ 3872 constraint(ALLOC_IN_RC(g2_regP)); 3873 match(iRegP); 3874 3875 format %{ %} 3876 interface(REG_INTER); 3877 %} 3878 3879 operand g3RegP() %{ 3880 constraint(ALLOC_IN_RC(g3_regP)); 3881 match(iRegP); 3882 3883 format %{ %} 3884 interface(REG_INTER); 3885 %} 3886 3887 operand g1RegI() %{ 3888 constraint(ALLOC_IN_RC(g1_regI)); 3889 match(iRegI); 3890 3891 format %{ %} 3892 interface(REG_INTER); 3893 %} 3894 3895 operand g3RegI() %{ 3896 constraint(ALLOC_IN_RC(g3_regI)); 3897 match(iRegI); 3898 3899 format %{ %} 3900 interface(REG_INTER); 3901 %} 3902 3903 operand g4RegI() %{ 3904 constraint(ALLOC_IN_RC(g4_regI)); 3905 match(iRegI); 3906 3907 format %{ %} 3908 interface(REG_INTER); 3909 %} 3910 3911 operand g4RegP() %{ 3912 constraint(ALLOC_IN_RC(g4_regP)); 3913 match(iRegP); 3914 3915 format %{ %} 3916 interface(REG_INTER); 3917 %} 3918 3919 operand i0RegP() %{ 3920 constraint(ALLOC_IN_RC(i0_regP)); 3921 match(iRegP); 3922 3923 format %{ %} 3924 interface(REG_INTER); 3925 %} 3926 3927 operand o0RegP() %{ 3928 constraint(ALLOC_IN_RC(o0_regP)); 3929 match(iRegP); 3930 3931 format %{ %} 3932 interface(REG_INTER); 3933 %} 3934 3935 operand o1RegP() %{ 3936 constraint(ALLOC_IN_RC(o1_regP)); 3937 match(iRegP); 3938 3939 format %{ %} 3940 interface(REG_INTER); 3941 %} 3942 3943 operand o2RegP() %{ 3944 constraint(ALLOC_IN_RC(o2_regP)); 3945 match(iRegP); 3946 3947 format %{ %} 3948 interface(REG_INTER); 3949 %} 3950 3951 operand o7RegP() %{ 3952 constraint(ALLOC_IN_RC(o7_regP)); 3953 match(iRegP); 3954 3955 format %{ %} 3956 interface(REG_INTER); 3957 %} 3958 3959 operand l7RegP() %{ 3960 constraint(ALLOC_IN_RC(l7_regP)); 3961 match(iRegP); 3962 3963 format %{ %} 3964 interface(REG_INTER); 3965 %} 3966 3967 operand o7RegI() %{ 3968 constraint(ALLOC_IN_RC(o7_regI)); 3969 match(iRegI); 3970 3971 format %{ %} 3972 interface(REG_INTER); 3973 %} 3974 3975 operand iRegN() %{ 3976 constraint(ALLOC_IN_RC(int_reg)); 3977 match(RegN); 3978 3979 format %{ %} 3980 interface(REG_INTER); 3981 %} 3982 3983 // Long Register 3984 operand iRegL() %{ 3985 constraint(ALLOC_IN_RC(long_reg)); 3986 match(RegL); 3987 3988 format %{ %} 3989 interface(REG_INTER); 3990 %} 3991 3992 operand o2RegL() %{ 3993 constraint(ALLOC_IN_RC(o2_regL)); 3994 match(iRegL); 3995 3996 format %{ %} 3997 interface(REG_INTER); 3998 %} 3999 4000 operand o7RegL() %{ 4001 constraint(ALLOC_IN_RC(o7_regL)); 4002 match(iRegL); 4003 4004 format %{ %} 4005 interface(REG_INTER); 4006 %} 4007 4008 operand g1RegL() %{ 4009 constraint(ALLOC_IN_RC(g1_regL)); 4010 match(iRegL); 4011 4012 format %{ %} 4013 interface(REG_INTER); 4014 %} 4015 4016 operand g3RegL() %{ 4017 constraint(ALLOC_IN_RC(g3_regL)); 4018 match(iRegL); 4019 4020 format %{ %} 4021 interface(REG_INTER); 4022 %} 4023 4024 // Int Register safe 4025 // This is 64bit safe 4026 operand iRegIsafe() %{ 4027 constraint(ALLOC_IN_RC(long_reg)); 4028 4029 match(iRegI); 4030 4031 format %{ %} 4032 interface(REG_INTER); 4033 %} 4034 4035 // Condition Code Flag Register 4036 operand flagsReg() %{ 4037 constraint(ALLOC_IN_RC(int_flags)); 4038 match(RegFlags); 4039 4040 format %{ "ccr" %} // both ICC and XCC 4041 interface(REG_INTER); 4042 %} 4043 4044 // Condition Code Register, unsigned comparisons. 4045 operand flagsRegU() %{ 4046 constraint(ALLOC_IN_RC(int_flags)); 4047 match(RegFlags); 4048 4049 format %{ "icc_U" %} 4050 interface(REG_INTER); 4051 %} 4052 4053 // Condition Code Register, pointer comparisons. 4054 operand flagsRegP() %{ 4055 constraint(ALLOC_IN_RC(int_flags)); 4056 match(RegFlags); 4057 4058 #ifdef _LP64 4059 format %{ "xcc_P" %} 4060 #else 4061 format %{ "icc_P" %} 4062 #endif 4063 interface(REG_INTER); 4064 %} 4065 4066 // Condition Code Register, long comparisons. 4067 operand flagsRegL() %{ 4068 constraint(ALLOC_IN_RC(int_flags)); 4069 match(RegFlags); 4070 4071 format %{ "xcc_L" %} 4072 interface(REG_INTER); 4073 %} 4074 4075 // Condition Code Register, floating comparisons, unordered same as "less". 4076 operand flagsRegF() %{ 4077 constraint(ALLOC_IN_RC(float_flags)); 4078 match(RegFlags); 4079 match(flagsRegF0); 4080 4081 format %{ %} 4082 interface(REG_INTER); 4083 %} 4084 4085 operand flagsRegF0() %{ 4086 constraint(ALLOC_IN_RC(float_flag0)); 4087 match(RegFlags); 4088 4089 format %{ %} 4090 interface(REG_INTER); 4091 %} 4092 4093 4094 // Condition Code Flag Register used by long compare 4095 operand flagsReg_long_LTGE() %{ 4096 constraint(ALLOC_IN_RC(int_flags)); 4097 match(RegFlags); 4098 format %{ "icc_LTGE" %} 4099 interface(REG_INTER); 4100 %} 4101 operand flagsReg_long_EQNE() %{ 4102 constraint(ALLOC_IN_RC(int_flags)); 4103 match(RegFlags); 4104 format %{ "icc_EQNE" %} 4105 interface(REG_INTER); 4106 %} 4107 operand flagsReg_long_LEGT() %{ 4108 constraint(ALLOC_IN_RC(int_flags)); 4109 match(RegFlags); 4110 format %{ "icc_LEGT" %} 4111 interface(REG_INTER); 4112 %} 4113 4114 4115 operand regD() %{ 4116 constraint(ALLOC_IN_RC(dflt_reg)); 4117 match(RegD); 4118 4119 match(regD_low); 4120 4121 format %{ %} 4122 interface(REG_INTER); 4123 %} 4124 4125 operand regF() %{ 4126 constraint(ALLOC_IN_RC(sflt_reg)); 4127 match(RegF); 4128 4129 format %{ %} 4130 interface(REG_INTER); 4131 %} 4132 4133 operand regD_low() %{ 4134 constraint(ALLOC_IN_RC(dflt_low_reg)); 4135 match(regD); 4136 4137 format %{ %} 4138 interface(REG_INTER); 4139 %} 4140 4141 // Special Registers 4142 4143 // Method Register 4144 operand inline_cache_regP(iRegP reg) %{ 4145 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 4146 match(reg); 4147 format %{ %} 4148 interface(REG_INTER); 4149 %} 4150 4151 operand interpreter_method_oop_regP(iRegP reg) %{ 4152 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 4153 match(reg); 4154 format %{ %} 4155 interface(REG_INTER); 4156 %} 4157 4158 4159 //----------Complex Operands--------------------------------------------------- 4160 // Indirect Memory Reference 4161 operand indirect(sp_ptr_RegP reg) %{ 4162 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4163 match(reg); 4164 4165 op_cost(100); 4166 format %{ "[$reg]" %} 4167 interface(MEMORY_INTER) %{ 4168 base($reg); 4169 index(0x0); 4170 scale(0x0); 4171 disp(0x0); 4172 %} 4173 %} 4174 4175 // Indirect with simm13 Offset 4176 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 4177 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4178 match(AddP reg offset); 4179 4180 op_cost(100); 4181 format %{ "[$reg + $offset]" %} 4182 interface(MEMORY_INTER) %{ 4183 base($reg); 4184 index(0x0); 4185 scale(0x0); 4186 disp($offset); 4187 %} 4188 %} 4189 4190 // Indirect with simm13 Offset minus 7 4191 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ 4192 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4193 match(AddP reg offset); 4194 4195 op_cost(100); 4196 format %{ "[$reg + $offset]" %} 4197 interface(MEMORY_INTER) %{ 4198 base($reg); 4199 index(0x0); 4200 scale(0x0); 4201 disp($offset); 4202 %} 4203 %} 4204 4205 // Note: Intel has a swapped version also, like this: 4206 //operand indOffsetX(iRegI reg, immP offset) %{ 4207 // constraint(ALLOC_IN_RC(int_reg)); 4208 // match(AddP offset reg); 4209 // 4210 // op_cost(100); 4211 // format %{ "[$reg + $offset]" %} 4212 // interface(MEMORY_INTER) %{ 4213 // base($reg); 4214 // index(0x0); 4215 // scale(0x0); 4216 // disp($offset); 4217 // %} 4218 //%} 4219 //// However, it doesn't make sense for SPARC, since 4220 // we have no particularly good way to embed oops in 4221 // single instructions. 4222 4223 // Indirect with Register Index 4224 operand indIndex(iRegP addr, iRegX index) %{ 4225 constraint(ALLOC_IN_RC(ptr_reg)); 4226 match(AddP addr index); 4227 4228 op_cost(100); 4229 format %{ "[$addr + $index]" %} 4230 interface(MEMORY_INTER) %{ 4231 base($addr); 4232 index($index); 4233 scale(0x0); 4234 disp(0x0); 4235 %} 4236 %} 4237 4238 //----------Special Memory Operands-------------------------------------------- 4239 // Stack Slot Operand - This operand is used for loading and storing temporary 4240 // values on the stack where a match requires a value to 4241 // flow through memory. 4242 operand stackSlotI(sRegI reg) %{ 4243 constraint(ALLOC_IN_RC(stack_slots)); 4244 op_cost(100); 4245 //match(RegI); 4246 format %{ "[$reg]" %} 4247 interface(MEMORY_INTER) %{ 4248 base(0xE); // R_SP 4249 index(0x0); 4250 scale(0x0); 4251 disp($reg); // Stack Offset 4252 %} 4253 %} 4254 4255 operand stackSlotP(sRegP reg) %{ 4256 constraint(ALLOC_IN_RC(stack_slots)); 4257 op_cost(100); 4258 //match(RegP); 4259 format %{ "[$reg]" %} 4260 interface(MEMORY_INTER) %{ 4261 base(0xE); // R_SP 4262 index(0x0); 4263 scale(0x0); 4264 disp($reg); // Stack Offset 4265 %} 4266 %} 4267 4268 operand stackSlotF(sRegF reg) %{ 4269 constraint(ALLOC_IN_RC(stack_slots)); 4270 op_cost(100); 4271 //match(RegF); 4272 format %{ "[$reg]" %} 4273 interface(MEMORY_INTER) %{ 4274 base(0xE); // R_SP 4275 index(0x0); 4276 scale(0x0); 4277 disp($reg); // Stack Offset 4278 %} 4279 %} 4280 operand stackSlotD(sRegD reg) %{ 4281 constraint(ALLOC_IN_RC(stack_slots)); 4282 op_cost(100); 4283 //match(RegD); 4284 format %{ "[$reg]" %} 4285 interface(MEMORY_INTER) %{ 4286 base(0xE); // R_SP 4287 index(0x0); 4288 scale(0x0); 4289 disp($reg); // Stack Offset 4290 %} 4291 %} 4292 operand stackSlotL(sRegL reg) %{ 4293 constraint(ALLOC_IN_RC(stack_slots)); 4294 op_cost(100); 4295 //match(RegL); 4296 format %{ "[$reg]" %} 4297 interface(MEMORY_INTER) %{ 4298 base(0xE); // R_SP 4299 index(0x0); 4300 scale(0x0); 4301 disp($reg); // Stack Offset 4302 %} 4303 %} 4304 4305 // Operands for expressing Control Flow 4306 // NOTE: Label is a predefined operand which should not be redefined in 4307 // the AD file. It is generically handled within the ADLC. 4308 4309 //----------Conditional Branch Operands---------------------------------------- 4310 // Comparison Op - This is the operation of the comparison, and is limited to 4311 // the following set of codes: 4312 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 4313 // 4314 // Other attributes of the comparison, such as unsignedness, are specified 4315 // by the comparison instruction that sets a condition code flags register. 4316 // That result is represented by a flags operand whose subtype is appropriate 4317 // to the unsignedness (etc.) of the comparison. 4318 // 4319 // Later, the instruction which matches both the Comparison Op (a Bool) and 4320 // the flags (produced by the Cmp) specifies the coding of the comparison op 4321 // by matching a specific subtype of Bool operand below, such as cmpOpU. 4322 4323 operand cmpOp() %{ 4324 match(Bool); 4325 4326 format %{ "" %} 4327 interface(COND_INTER) %{ 4328 equal(0x1); 4329 not_equal(0x9); 4330 less(0x3); 4331 greater_equal(0xB); 4332 less_equal(0x2); 4333 greater(0xA); 4334 overflow(0x7); 4335 no_overflow(0xF); 4336 %} 4337 %} 4338 4339 // Comparison Op, unsigned 4340 operand cmpOpU() %{ 4341 match(Bool); 4342 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4343 n->as_Bool()->_test._test != BoolTest::no_overflow); 4344 4345 format %{ "u" %} 4346 interface(COND_INTER) %{ 4347 equal(0x1); 4348 not_equal(0x9); 4349 less(0x5); 4350 greater_equal(0xD); 4351 less_equal(0x4); 4352 greater(0xC); 4353 overflow(0x7); 4354 no_overflow(0xF); 4355 %} 4356 %} 4357 4358 // Comparison Op, pointer (same as unsigned) 4359 operand cmpOpP() %{ 4360 match(Bool); 4361 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4362 n->as_Bool()->_test._test != BoolTest::no_overflow); 4363 4364 format %{ "p" %} 4365 interface(COND_INTER) %{ 4366 equal(0x1); 4367 not_equal(0x9); 4368 less(0x5); 4369 greater_equal(0xD); 4370 less_equal(0x4); 4371 greater(0xC); 4372 overflow(0x7); 4373 no_overflow(0xF); 4374 %} 4375 %} 4376 4377 // Comparison Op, branch-register encoding 4378 operand cmpOp_reg() %{ 4379 match(Bool); 4380 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4381 n->as_Bool()->_test._test != BoolTest::no_overflow); 4382 4383 format %{ "" %} 4384 interface(COND_INTER) %{ 4385 equal (0x1); 4386 not_equal (0x5); 4387 less (0x3); 4388 greater_equal(0x7); 4389 less_equal (0x2); 4390 greater (0x6); 4391 overflow(0x7); // not supported 4392 no_overflow(0xF); // not supported 4393 %} 4394 %} 4395 4396 // Comparison Code, floating, unordered same as less 4397 operand cmpOpF() %{ 4398 match(Bool); 4399 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4400 n->as_Bool()->_test._test != BoolTest::no_overflow); 4401 4402 format %{ "fl" %} 4403 interface(COND_INTER) %{ 4404 equal(0x9); 4405 not_equal(0x1); 4406 less(0x3); 4407 greater_equal(0xB); 4408 less_equal(0xE); 4409 greater(0x6); 4410 4411 overflow(0x7); // not supported 4412 no_overflow(0xF); // not supported 4413 %} 4414 %} 4415 4416 // Used by long compare 4417 operand cmpOp_commute() %{ 4418 match(Bool); 4419 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4420 n->as_Bool()->_test._test != BoolTest::no_overflow); 4421 4422 format %{ "" %} 4423 interface(COND_INTER) %{ 4424 equal(0x1); 4425 not_equal(0x9); 4426 less(0xA); 4427 greater_equal(0x2); 4428 less_equal(0xB); 4429 greater(0x3); 4430 overflow(0x7); 4431 no_overflow(0xF); 4432 %} 4433 %} 4434 4435 //----------OPERAND CLASSES---------------------------------------------------- 4436 // Operand Classes are groups of operands that are used to simplify 4437 // instruction definitions by not requiring the AD writer to specify separate 4438 // instructions for every form of operand when the instruction accepts 4439 // multiple operand types with the same basic encoding and format. The classic 4440 // case of this is memory operands. 4441 opclass memory( indirect, indOffset13, indIndex ); 4442 opclass indIndexMemory( indIndex ); 4443 4444 //----------PIPELINE----------------------------------------------------------- 4445 pipeline %{ 4446 4447 //----------ATTRIBUTES--------------------------------------------------------- 4448 attributes %{ 4449 fixed_size_instructions; // Fixed size instructions 4450 branch_has_delay_slot; // Branch has delay slot following 4451 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4452 instruction_unit_size = 4; // An instruction is 4 bytes long 4453 instruction_fetch_unit_size = 16; // The processor fetches one line 4454 instruction_fetch_units = 1; // of 16 bytes 4455 4456 // List of nop instructions 4457 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4458 %} 4459 4460 //----------RESOURCES---------------------------------------------------------- 4461 // Resources are the functional units available to the machine 4462 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4463 4464 //----------PIPELINE DESCRIPTION----------------------------------------------- 4465 // Pipeline Description specifies the stages in the machine's pipeline 4466 4467 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4468 4469 //----------PIPELINE CLASSES--------------------------------------------------- 4470 // Pipeline Classes describe the stages in which input and output are 4471 // referenced by the hardware pipeline. 4472 4473 // Integer ALU reg-reg operation 4474 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4475 single_instruction; 4476 dst : E(write); 4477 src1 : R(read); 4478 src2 : R(read); 4479 IALU : R; 4480 %} 4481 4482 // Integer ALU reg-reg long operation 4483 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4484 instruction_count(2); 4485 dst : E(write); 4486 src1 : R(read); 4487 src2 : R(read); 4488 IALU : R; 4489 IALU : R; 4490 %} 4491 4492 // Integer ALU reg-reg long dependent operation 4493 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4494 instruction_count(1); multiple_bundles; 4495 dst : E(write); 4496 src1 : R(read); 4497 src2 : R(read); 4498 cr : E(write); 4499 IALU : R(2); 4500 %} 4501 4502 // Integer ALU reg-imm operaion 4503 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4504 single_instruction; 4505 dst : E(write); 4506 src1 : R(read); 4507 IALU : R; 4508 %} 4509 4510 // Integer ALU reg-reg operation with condition code 4511 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4512 single_instruction; 4513 dst : E(write); 4514 cr : E(write); 4515 src1 : R(read); 4516 src2 : R(read); 4517 IALU : R; 4518 %} 4519 4520 // Integer ALU reg-imm operation with condition code 4521 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4522 single_instruction; 4523 dst : E(write); 4524 cr : E(write); 4525 src1 : R(read); 4526 IALU : R; 4527 %} 4528 4529 // Integer ALU zero-reg operation 4530 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4531 single_instruction; 4532 dst : E(write); 4533 src2 : R(read); 4534 IALU : R; 4535 %} 4536 4537 // Integer ALU zero-reg operation with condition code only 4538 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4539 single_instruction; 4540 cr : E(write); 4541 src : R(read); 4542 IALU : R; 4543 %} 4544 4545 // Integer ALU reg-reg operation with condition code only 4546 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4547 single_instruction; 4548 cr : E(write); 4549 src1 : R(read); 4550 src2 : R(read); 4551 IALU : R; 4552 %} 4553 4554 // Integer ALU reg-imm operation with condition code only 4555 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4556 single_instruction; 4557 cr : E(write); 4558 src1 : R(read); 4559 IALU : R; 4560 %} 4561 4562 // Integer ALU reg-reg-zero operation with condition code only 4563 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4564 single_instruction; 4565 cr : E(write); 4566 src1 : R(read); 4567 src2 : R(read); 4568 IALU : R; 4569 %} 4570 4571 // Integer ALU reg-imm-zero operation with condition code only 4572 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4573 single_instruction; 4574 cr : E(write); 4575 src1 : R(read); 4576 IALU : R; 4577 %} 4578 4579 // Integer ALU reg-reg operation with condition code, src1 modified 4580 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4581 single_instruction; 4582 cr : E(write); 4583 src1 : E(write); 4584 src1 : R(read); 4585 src2 : R(read); 4586 IALU : R; 4587 %} 4588 4589 // Integer ALU reg-imm operation with condition code, src1 modified 4590 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4591 single_instruction; 4592 cr : E(write); 4593 src1 : E(write); 4594 src1 : R(read); 4595 IALU : R; 4596 %} 4597 4598 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4599 multiple_bundles; 4600 dst : E(write)+4; 4601 cr : E(write); 4602 src1 : R(read); 4603 src2 : R(read); 4604 IALU : R(3); 4605 BR : R(2); 4606 %} 4607 4608 // Integer ALU operation 4609 pipe_class ialu_none(iRegI dst) %{ 4610 single_instruction; 4611 dst : E(write); 4612 IALU : R; 4613 %} 4614 4615 // Integer ALU reg operation 4616 pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4617 single_instruction; may_have_no_code; 4618 dst : E(write); 4619 src : R(read); 4620 IALU : R; 4621 %} 4622 4623 // Integer ALU reg conditional operation 4624 // This instruction has a 1 cycle stall, and cannot execute 4625 // in the same cycle as the instruction setting the condition 4626 // code. We kludge this by pretending to read the condition code 4627 // 1 cycle earlier, and by marking the functional units as busy 4628 // for 2 cycles with the result available 1 cycle later than 4629 // is really the case. 4630 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4631 single_instruction; 4632 op2_out : C(write); 4633 op1 : R(read); 4634 cr : R(read); // This is really E, with a 1 cycle stall 4635 BR : R(2); 4636 MS : R(2); 4637 %} 4638 4639 #ifdef _LP64 4640 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4641 instruction_count(1); multiple_bundles; 4642 dst : C(write)+1; 4643 src : R(read)+1; 4644 IALU : R(1); 4645 BR : E(2); 4646 MS : E(2); 4647 %} 4648 #endif 4649 4650 // Integer ALU reg operation 4651 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4652 single_instruction; may_have_no_code; 4653 dst : E(write); 4654 src : R(read); 4655 IALU : R; 4656 %} 4657 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4658 single_instruction; may_have_no_code; 4659 dst : E(write); 4660 src : R(read); 4661 IALU : R; 4662 %} 4663 4664 // Two integer ALU reg operations 4665 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4666 instruction_count(2); 4667 dst : E(write); 4668 src : R(read); 4669 A0 : R; 4670 A1 : R; 4671 %} 4672 4673 // Two integer ALU reg operations 4674 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4675 instruction_count(2); may_have_no_code; 4676 dst : E(write); 4677 src : R(read); 4678 A0 : R; 4679 A1 : R; 4680 %} 4681 4682 // Integer ALU imm operation 4683 pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4684 single_instruction; 4685 dst : E(write); 4686 IALU : R; 4687 %} 4688 4689 // Integer ALU reg-reg with carry operation 4690 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4691 single_instruction; 4692 dst : E(write); 4693 src1 : R(read); 4694 src2 : R(read); 4695 IALU : R; 4696 %} 4697 4698 // Integer ALU cc operation 4699 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4700 single_instruction; 4701 dst : E(write); 4702 cc : R(read); 4703 IALU : R; 4704 %} 4705 4706 // Integer ALU cc / second IALU operation 4707 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4708 instruction_count(1); multiple_bundles; 4709 dst : E(write)+1; 4710 src : R(read); 4711 IALU : R; 4712 %} 4713 4714 // Integer ALU cc / second IALU operation 4715 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4716 instruction_count(1); multiple_bundles; 4717 dst : E(write)+1; 4718 p : R(read); 4719 q : R(read); 4720 IALU : R; 4721 %} 4722 4723 // Integer ALU hi-lo-reg operation 4724 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4725 instruction_count(1); multiple_bundles; 4726 dst : E(write)+1; 4727 IALU : R(2); 4728 %} 4729 4730 // Float ALU hi-lo-reg operation (with temp) 4731 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4732 instruction_count(1); multiple_bundles; 4733 dst : E(write)+1; 4734 IALU : R(2); 4735 %} 4736 4737 // Long Constant 4738 pipe_class loadConL( iRegL dst, immL src ) %{ 4739 instruction_count(2); multiple_bundles; 4740 dst : E(write)+1; 4741 IALU : R(2); 4742 IALU : R(2); 4743 %} 4744 4745 // Pointer Constant 4746 pipe_class loadConP( iRegP dst, immP src ) %{ 4747 instruction_count(0); multiple_bundles; 4748 fixed_latency(6); 4749 %} 4750 4751 // Polling Address 4752 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4753 #ifdef _LP64 4754 instruction_count(0); multiple_bundles; 4755 fixed_latency(6); 4756 #else 4757 dst : E(write); 4758 IALU : R; 4759 #endif 4760 %} 4761 4762 // Long Constant small 4763 pipe_class loadConLlo( iRegL dst, immL src ) %{ 4764 instruction_count(2); 4765 dst : E(write); 4766 IALU : R; 4767 IALU : R; 4768 %} 4769 4770 // [PHH] This is wrong for 64-bit. See LdImmF/D. 4771 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4772 instruction_count(1); multiple_bundles; 4773 src : R(read); 4774 dst : M(write)+1; 4775 IALU : R; 4776 MS : E; 4777 %} 4778 4779 // Integer ALU nop operation 4780 pipe_class ialu_nop() %{ 4781 single_instruction; 4782 IALU : R; 4783 %} 4784 4785 // Integer ALU nop operation 4786 pipe_class ialu_nop_A0() %{ 4787 single_instruction; 4788 A0 : R; 4789 %} 4790 4791 // Integer ALU nop operation 4792 pipe_class ialu_nop_A1() %{ 4793 single_instruction; 4794 A1 : R; 4795 %} 4796 4797 // Integer Multiply reg-reg operation 4798 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4799 single_instruction; 4800 dst : E(write); 4801 src1 : R(read); 4802 src2 : R(read); 4803 MS : R(5); 4804 %} 4805 4806 // Integer Multiply reg-imm operation 4807 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4808 single_instruction; 4809 dst : E(write); 4810 src1 : R(read); 4811 MS : R(5); 4812 %} 4813 4814 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4815 single_instruction; 4816 dst : E(write)+4; 4817 src1 : R(read); 4818 src2 : R(read); 4819 MS : R(6); 4820 %} 4821 4822 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4823 single_instruction; 4824 dst : E(write)+4; 4825 src1 : R(read); 4826 MS : R(6); 4827 %} 4828 4829 // Integer Divide reg-reg 4830 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4831 instruction_count(1); multiple_bundles; 4832 dst : E(write); 4833 temp : E(write); 4834 src1 : R(read); 4835 src2 : R(read); 4836 temp : R(read); 4837 MS : R(38); 4838 %} 4839 4840 // Integer Divide reg-imm 4841 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4842 instruction_count(1); multiple_bundles; 4843 dst : E(write); 4844 temp : E(write); 4845 src1 : R(read); 4846 temp : R(read); 4847 MS : R(38); 4848 %} 4849 4850 // Long Divide 4851 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4852 dst : E(write)+71; 4853 src1 : R(read); 4854 src2 : R(read)+1; 4855 MS : R(70); 4856 %} 4857 4858 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4859 dst : E(write)+71; 4860 src1 : R(read); 4861 MS : R(70); 4862 %} 4863 4864 // Floating Point Add Float 4865 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4866 single_instruction; 4867 dst : X(write); 4868 src1 : E(read); 4869 src2 : E(read); 4870 FA : R; 4871 %} 4872 4873 // Floating Point Add Double 4874 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4875 single_instruction; 4876 dst : X(write); 4877 src1 : E(read); 4878 src2 : E(read); 4879 FA : R; 4880 %} 4881 4882 // Floating Point Conditional Move based on integer flags 4883 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4884 single_instruction; 4885 dst : X(write); 4886 src : E(read); 4887 cr : R(read); 4888 FA : R(2); 4889 BR : R(2); 4890 %} 4891 4892 // Floating Point Conditional Move based on integer flags 4893 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4894 single_instruction; 4895 dst : X(write); 4896 src : E(read); 4897 cr : R(read); 4898 FA : R(2); 4899 BR : R(2); 4900 %} 4901 4902 // Floating Point Multiply Float 4903 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4904 single_instruction; 4905 dst : X(write); 4906 src1 : E(read); 4907 src2 : E(read); 4908 FM : R; 4909 %} 4910 4911 // Floating Point Multiply Double 4912 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4913 single_instruction; 4914 dst : X(write); 4915 src1 : E(read); 4916 src2 : E(read); 4917 FM : R; 4918 %} 4919 4920 // Floating Point Divide Float 4921 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4922 single_instruction; 4923 dst : X(write); 4924 src1 : E(read); 4925 src2 : E(read); 4926 FM : R; 4927 FDIV : C(14); 4928 %} 4929 4930 // Floating Point Divide Double 4931 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4932 single_instruction; 4933 dst : X(write); 4934 src1 : E(read); 4935 src2 : E(read); 4936 FM : R; 4937 FDIV : C(17); 4938 %} 4939 4940 // Floating Point Move/Negate/Abs Float 4941 pipe_class faddF_reg(regF dst, regF src) %{ 4942 single_instruction; 4943 dst : W(write); 4944 src : E(read); 4945 FA : R(1); 4946 %} 4947 4948 // Floating Point Move/Negate/Abs Double 4949 pipe_class faddD_reg(regD dst, regD src) %{ 4950 single_instruction; 4951 dst : W(write); 4952 src : E(read); 4953 FA : R; 4954 %} 4955 4956 // Floating Point Convert F->D 4957 pipe_class fcvtF2D(regD dst, regF src) %{ 4958 single_instruction; 4959 dst : X(write); 4960 src : E(read); 4961 FA : R; 4962 %} 4963 4964 // Floating Point Convert I->D 4965 pipe_class fcvtI2D(regD dst, regF src) %{ 4966 single_instruction; 4967 dst : X(write); 4968 src : E(read); 4969 FA : R; 4970 %} 4971 4972 // Floating Point Convert LHi->D 4973 pipe_class fcvtLHi2D(regD dst, regD src) %{ 4974 single_instruction; 4975 dst : X(write); 4976 src : E(read); 4977 FA : R; 4978 %} 4979 4980 // Floating Point Convert L->D 4981 pipe_class fcvtL2D(regD dst, regF src) %{ 4982 single_instruction; 4983 dst : X(write); 4984 src : E(read); 4985 FA : R; 4986 %} 4987 4988 // Floating Point Convert L->F 4989 pipe_class fcvtL2F(regD dst, regF src) %{ 4990 single_instruction; 4991 dst : X(write); 4992 src : E(read); 4993 FA : R; 4994 %} 4995 4996 // Floating Point Convert D->F 4997 pipe_class fcvtD2F(regD dst, regF src) %{ 4998 single_instruction; 4999 dst : X(write); 5000 src : E(read); 5001 FA : R; 5002 %} 5003 5004 // Floating Point Convert I->L 5005 pipe_class fcvtI2L(regD dst, regF src) %{ 5006 single_instruction; 5007 dst : X(write); 5008 src : E(read); 5009 FA : R; 5010 %} 5011 5012 // Floating Point Convert D->F 5013 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 5014 instruction_count(1); multiple_bundles; 5015 dst : X(write)+6; 5016 src : E(read); 5017 FA : R; 5018 %} 5019 5020 // Floating Point Convert D->L 5021 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 5022 instruction_count(1); multiple_bundles; 5023 dst : X(write)+6; 5024 src : E(read); 5025 FA : R; 5026 %} 5027 5028 // Floating Point Convert F->I 5029 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 5030 instruction_count(1); multiple_bundles; 5031 dst : X(write)+6; 5032 src : E(read); 5033 FA : R; 5034 %} 5035 5036 // Floating Point Convert F->L 5037 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 5038 instruction_count(1); multiple_bundles; 5039 dst : X(write)+6; 5040 src : E(read); 5041 FA : R; 5042 %} 5043 5044 // Floating Point Convert I->F 5045 pipe_class fcvtI2F(regF dst, regF src) %{ 5046 single_instruction; 5047 dst : X(write); 5048 src : E(read); 5049 FA : R; 5050 %} 5051 5052 // Floating Point Compare 5053 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 5054 single_instruction; 5055 cr : X(write); 5056 src1 : E(read); 5057 src2 : E(read); 5058 FA : R; 5059 %} 5060 5061 // Floating Point Compare 5062 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 5063 single_instruction; 5064 cr : X(write); 5065 src1 : E(read); 5066 src2 : E(read); 5067 FA : R; 5068 %} 5069 5070 // Floating Add Nop 5071 pipe_class fadd_nop() %{ 5072 single_instruction; 5073 FA : R; 5074 %} 5075 5076 // Integer Store to Memory 5077 pipe_class istore_mem_reg(memory mem, iRegI src) %{ 5078 single_instruction; 5079 mem : R(read); 5080 src : C(read); 5081 MS : R; 5082 %} 5083 5084 // Integer Store to Memory 5085 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 5086 single_instruction; 5087 mem : R(read); 5088 src : C(read); 5089 MS : R; 5090 %} 5091 5092 // Integer Store Zero to Memory 5093 pipe_class istore_mem_zero(memory mem, immI0 src) %{ 5094 single_instruction; 5095 mem : R(read); 5096 MS : R; 5097 %} 5098 5099 // Special Stack Slot Store 5100 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 5101 single_instruction; 5102 stkSlot : R(read); 5103 src : C(read); 5104 MS : R; 5105 %} 5106 5107 // Special Stack Slot Store 5108 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 5109 instruction_count(2); multiple_bundles; 5110 stkSlot : R(read); 5111 src : C(read); 5112 MS : R(2); 5113 %} 5114 5115 // Float Store 5116 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 5117 single_instruction; 5118 mem : R(read); 5119 src : C(read); 5120 MS : R; 5121 %} 5122 5123 // Float Store 5124 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 5125 single_instruction; 5126 mem : R(read); 5127 MS : R; 5128 %} 5129 5130 // Double Store 5131 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 5132 instruction_count(1); 5133 mem : R(read); 5134 src : C(read); 5135 MS : R; 5136 %} 5137 5138 // Double Store 5139 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 5140 single_instruction; 5141 mem : R(read); 5142 MS : R; 5143 %} 5144 5145 // Special Stack Slot Float Store 5146 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 5147 single_instruction; 5148 stkSlot : R(read); 5149 src : C(read); 5150 MS : R; 5151 %} 5152 5153 // Special Stack Slot Double Store 5154 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 5155 single_instruction; 5156 stkSlot : R(read); 5157 src : C(read); 5158 MS : R; 5159 %} 5160 5161 // Integer Load (when sign bit propagation not needed) 5162 pipe_class iload_mem(iRegI dst, memory mem) %{ 5163 single_instruction; 5164 mem : R(read); 5165 dst : C(write); 5166 MS : R; 5167 %} 5168 5169 // Integer Load from stack operand 5170 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 5171 single_instruction; 5172 mem : R(read); 5173 dst : C(write); 5174 MS : R; 5175 %} 5176 5177 // Integer Load (when sign bit propagation or masking is needed) 5178 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 5179 single_instruction; 5180 mem : R(read); 5181 dst : M(write); 5182 MS : R; 5183 %} 5184 5185 // Float Load 5186 pipe_class floadF_mem(regF dst, memory mem) %{ 5187 single_instruction; 5188 mem : R(read); 5189 dst : M(write); 5190 MS : R; 5191 %} 5192 5193 // Float Load 5194 pipe_class floadD_mem(regD dst, memory mem) %{ 5195 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 5196 mem : R(read); 5197 dst : M(write); 5198 MS : R; 5199 %} 5200 5201 // Float Load 5202 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 5203 single_instruction; 5204 stkSlot : R(read); 5205 dst : M(write); 5206 MS : R; 5207 %} 5208 5209 // Float Load 5210 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 5211 single_instruction; 5212 stkSlot : R(read); 5213 dst : M(write); 5214 MS : R; 5215 %} 5216 5217 // Memory Nop 5218 pipe_class mem_nop() %{ 5219 single_instruction; 5220 MS : R; 5221 %} 5222 5223 pipe_class sethi(iRegP dst, immI src) %{ 5224 single_instruction; 5225 dst : E(write); 5226 IALU : R; 5227 %} 5228 5229 pipe_class loadPollP(iRegP poll) %{ 5230 single_instruction; 5231 poll : R(read); 5232 MS : R; 5233 %} 5234 5235 pipe_class br(Universe br, label labl) %{ 5236 single_instruction_with_delay_slot; 5237 BR : R; 5238 %} 5239 5240 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 5241 single_instruction_with_delay_slot; 5242 cr : E(read); 5243 BR : R; 5244 %} 5245 5246 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 5247 single_instruction_with_delay_slot; 5248 op1 : E(read); 5249 BR : R; 5250 MS : R; 5251 %} 5252 5253 // Compare and branch 5254 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 5255 instruction_count(2); has_delay_slot; 5256 cr : E(write); 5257 src1 : R(read); 5258 src2 : R(read); 5259 IALU : R; 5260 BR : R; 5261 %} 5262 5263 // Compare and branch 5264 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ 5265 instruction_count(2); has_delay_slot; 5266 cr : E(write); 5267 src1 : R(read); 5268 IALU : R; 5269 BR : R; 5270 %} 5271 5272 // Compare and branch using cbcond 5273 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ 5274 single_instruction; 5275 src1 : E(read); 5276 src2 : E(read); 5277 IALU : R; 5278 BR : R; 5279 %} 5280 5281 // Compare and branch using cbcond 5282 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ 5283 single_instruction; 5284 src1 : E(read); 5285 IALU : R; 5286 BR : R; 5287 %} 5288 5289 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 5290 single_instruction_with_delay_slot; 5291 cr : E(read); 5292 BR : R; 5293 %} 5294 5295 pipe_class br_nop() %{ 5296 single_instruction; 5297 BR : R; 5298 %} 5299 5300 pipe_class simple_call(method meth) %{ 5301 instruction_count(2); multiple_bundles; force_serialization; 5302 fixed_latency(100); 5303 BR : R(1); 5304 MS : R(1); 5305 A0 : R(1); 5306 %} 5307 5308 pipe_class compiled_call(method meth) %{ 5309 instruction_count(1); multiple_bundles; force_serialization; 5310 fixed_latency(100); 5311 MS : R(1); 5312 %} 5313 5314 pipe_class call(method meth) %{ 5315 instruction_count(0); multiple_bundles; force_serialization; 5316 fixed_latency(100); 5317 %} 5318 5319 pipe_class tail_call(Universe ignore, label labl) %{ 5320 single_instruction; has_delay_slot; 5321 fixed_latency(100); 5322 BR : R(1); 5323 MS : R(1); 5324 %} 5325 5326 pipe_class ret(Universe ignore) %{ 5327 single_instruction; has_delay_slot; 5328 BR : R(1); 5329 MS : R(1); 5330 %} 5331 5332 pipe_class ret_poll(g3RegP poll) %{ 5333 instruction_count(3); has_delay_slot; 5334 poll : E(read); 5335 MS : R; 5336 %} 5337 5338 // The real do-nothing guy 5339 pipe_class empty( ) %{ 5340 instruction_count(0); 5341 %} 5342 5343 pipe_class long_memory_op() %{ 5344 instruction_count(0); multiple_bundles; force_serialization; 5345 fixed_latency(25); 5346 MS : R(1); 5347 %} 5348 5349 // Check-cast 5350 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 5351 array : R(read); 5352 match : R(read); 5353 IALU : R(2); 5354 BR : R(2); 5355 MS : R; 5356 %} 5357 5358 // Convert FPU flags into +1,0,-1 5359 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 5360 src1 : E(read); 5361 src2 : E(read); 5362 dst : E(write); 5363 FA : R; 5364 MS : R(2); 5365 BR : R(2); 5366 %} 5367 5368 // Compare for p < q, and conditionally add y 5369 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 5370 p : E(read); 5371 q : E(read); 5372 y : E(read); 5373 IALU : R(3) 5374 %} 5375 5376 // Perform a compare, then move conditionally in a branch delay slot. 5377 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 5378 src2 : E(read); 5379 srcdst : E(read); 5380 IALU : R; 5381 BR : R; 5382 %} 5383 5384 // Define the class for the Nop node 5385 define %{ 5386 MachNop = ialu_nop; 5387 %} 5388 5389 %} 5390 5391 //----------INSTRUCTIONS------------------------------------------------------- 5392 5393 //------------Special Stack Slot instructions - no match rules----------------- 5394 instruct stkI_to_regF(regF dst, stackSlotI src) %{ 5395 // No match rule to avoid chain rule match. 5396 effect(DEF dst, USE src); 5397 ins_cost(MEMORY_REF_COST); 5398 size(4); 5399 format %{ "LDF $src,$dst\t! stkI to regF" %} 5400 opcode(Assembler::ldf_op3); 5401 ins_encode(simple_form3_mem_reg(src, dst)); 5402 ins_pipe(floadF_stk); 5403 %} 5404 5405 instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5406 // No match rule to avoid chain rule match. 5407 effect(DEF dst, USE src); 5408 ins_cost(MEMORY_REF_COST); 5409 size(4); 5410 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5411 opcode(Assembler::lddf_op3); 5412 ins_encode(simple_form3_mem_reg(src, dst)); 5413 ins_pipe(floadD_stk); 5414 %} 5415 5416 instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5417 // No match rule to avoid chain rule match. 5418 effect(DEF dst, USE src); 5419 ins_cost(MEMORY_REF_COST); 5420 size(4); 5421 format %{ "STF $src,$dst\t! regF to stkI" %} 5422 opcode(Assembler::stf_op3); 5423 ins_encode(simple_form3_mem_reg(dst, src)); 5424 ins_pipe(fstoreF_stk_reg); 5425 %} 5426 5427 instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5428 // No match rule to avoid chain rule match. 5429 effect(DEF dst, USE src); 5430 ins_cost(MEMORY_REF_COST); 5431 size(4); 5432 format %{ "STDF $src,$dst\t! regD to stkL" %} 5433 opcode(Assembler::stdf_op3); 5434 ins_encode(simple_form3_mem_reg(dst, src)); 5435 ins_pipe(fstoreD_stk_reg); 5436 %} 5437 5438 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5439 effect(DEF dst, USE src); 5440 ins_cost(MEMORY_REF_COST*2); 5441 size(8); 5442 format %{ "STW $src,$dst.hi\t! long\n\t" 5443 "STW R_G0,$dst.lo" %} 5444 opcode(Assembler::stw_op3); 5445 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5446 ins_pipe(lstoreI_stk_reg); 5447 %} 5448 5449 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5450 // No match rule to avoid chain rule match. 5451 effect(DEF dst, USE src); 5452 ins_cost(MEMORY_REF_COST); 5453 size(4); 5454 format %{ "STX $src,$dst\t! regL to stkD" %} 5455 opcode(Assembler::stx_op3); 5456 ins_encode(simple_form3_mem_reg( dst, src ) ); 5457 ins_pipe(istore_stk_reg); 5458 %} 5459 5460 //---------- Chain stack slots between similar types -------- 5461 5462 // Load integer from stack slot 5463 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5464 match(Set dst src); 5465 ins_cost(MEMORY_REF_COST); 5466 5467 size(4); 5468 format %{ "LDUW $src,$dst\t!stk" %} 5469 opcode(Assembler::lduw_op3); 5470 ins_encode(simple_form3_mem_reg( src, dst ) ); 5471 ins_pipe(iload_mem); 5472 %} 5473 5474 // Store integer to stack slot 5475 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5476 match(Set dst src); 5477 ins_cost(MEMORY_REF_COST); 5478 5479 size(4); 5480 format %{ "STW $src,$dst\t!stk" %} 5481 opcode(Assembler::stw_op3); 5482 ins_encode(simple_form3_mem_reg( dst, src ) ); 5483 ins_pipe(istore_mem_reg); 5484 %} 5485 5486 // Load long from stack slot 5487 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5488 match(Set dst src); 5489 5490 ins_cost(MEMORY_REF_COST); 5491 size(4); 5492 format %{ "LDX $src,$dst\t! long" %} 5493 opcode(Assembler::ldx_op3); 5494 ins_encode(simple_form3_mem_reg( src, dst ) ); 5495 ins_pipe(iload_mem); 5496 %} 5497 5498 // Store long to stack slot 5499 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5500 match(Set dst src); 5501 5502 ins_cost(MEMORY_REF_COST); 5503 size(4); 5504 format %{ "STX $src,$dst\t! long" %} 5505 opcode(Assembler::stx_op3); 5506 ins_encode(simple_form3_mem_reg( dst, src ) ); 5507 ins_pipe(istore_mem_reg); 5508 %} 5509 5510 #ifdef _LP64 5511 // Load pointer from stack slot, 64-bit encoding 5512 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5513 match(Set dst src); 5514 ins_cost(MEMORY_REF_COST); 5515 size(4); 5516 format %{ "LDX $src,$dst\t!ptr" %} 5517 opcode(Assembler::ldx_op3); 5518 ins_encode(simple_form3_mem_reg( src, dst ) ); 5519 ins_pipe(iload_mem); 5520 %} 5521 5522 // Store pointer to stack slot 5523 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5524 match(Set dst src); 5525 ins_cost(MEMORY_REF_COST); 5526 size(4); 5527 format %{ "STX $src,$dst\t!ptr" %} 5528 opcode(Assembler::stx_op3); 5529 ins_encode(simple_form3_mem_reg( dst, src ) ); 5530 ins_pipe(istore_mem_reg); 5531 %} 5532 #else // _LP64 5533 // Load pointer from stack slot, 32-bit encoding 5534 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5535 match(Set dst src); 5536 ins_cost(MEMORY_REF_COST); 5537 format %{ "LDUW $src,$dst\t!ptr" %} 5538 opcode(Assembler::lduw_op3, Assembler::ldst_op); 5539 ins_encode(simple_form3_mem_reg( src, dst ) ); 5540 ins_pipe(iload_mem); 5541 %} 5542 5543 // Store pointer to stack slot 5544 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5545 match(Set dst src); 5546 ins_cost(MEMORY_REF_COST); 5547 format %{ "STW $src,$dst\t!ptr" %} 5548 opcode(Assembler::stw_op3, Assembler::ldst_op); 5549 ins_encode(simple_form3_mem_reg( dst, src ) ); 5550 ins_pipe(istore_mem_reg); 5551 %} 5552 #endif // _LP64 5553 5554 //------------Special Nop instructions for bundling - no match rules----------- 5555 // Nop using the A0 functional unit 5556 instruct Nop_A0() %{ 5557 ins_cost(0); 5558 5559 format %{ "NOP ! Alu Pipeline" %} 5560 opcode(Assembler::or_op3, Assembler::arith_op); 5561 ins_encode( form2_nop() ); 5562 ins_pipe(ialu_nop_A0); 5563 %} 5564 5565 // Nop using the A1 functional unit 5566 instruct Nop_A1( ) %{ 5567 ins_cost(0); 5568 5569 format %{ "NOP ! Alu Pipeline" %} 5570 opcode(Assembler::or_op3, Assembler::arith_op); 5571 ins_encode( form2_nop() ); 5572 ins_pipe(ialu_nop_A1); 5573 %} 5574 5575 // Nop using the memory functional unit 5576 instruct Nop_MS( ) %{ 5577 ins_cost(0); 5578 5579 format %{ "NOP ! Memory Pipeline" %} 5580 ins_encode( emit_mem_nop ); 5581 ins_pipe(mem_nop); 5582 %} 5583 5584 // Nop using the floating add functional unit 5585 instruct Nop_FA( ) %{ 5586 ins_cost(0); 5587 5588 format %{ "NOP ! Floating Add Pipeline" %} 5589 ins_encode( emit_fadd_nop ); 5590 ins_pipe(fadd_nop); 5591 %} 5592 5593 // Nop using the branch functional unit 5594 instruct Nop_BR( ) %{ 5595 ins_cost(0); 5596 5597 format %{ "NOP ! Branch Pipeline" %} 5598 ins_encode( emit_br_nop ); 5599 ins_pipe(br_nop); 5600 %} 5601 5602 //----------Load/Store/Move Instructions--------------------------------------- 5603 //----------Load Instructions-------------------------------------------------- 5604 // Load Byte (8bit signed) 5605 instruct loadB(iRegI dst, memory mem) %{ 5606 match(Set dst (LoadB mem)); 5607 ins_cost(MEMORY_REF_COST); 5608 5609 size(4); 5610 format %{ "LDSB $mem,$dst\t! byte" %} 5611 ins_encode %{ 5612 __ ldsb($mem$$Address, $dst$$Register); 5613 %} 5614 ins_pipe(iload_mask_mem); 5615 %} 5616 5617 // Load Byte (8bit signed) into a Long Register 5618 instruct loadB2L(iRegL dst, memory mem) %{ 5619 match(Set dst (ConvI2L (LoadB mem))); 5620 ins_cost(MEMORY_REF_COST); 5621 5622 size(4); 5623 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5624 ins_encode %{ 5625 __ ldsb($mem$$Address, $dst$$Register); 5626 %} 5627 ins_pipe(iload_mask_mem); 5628 %} 5629 5630 // Load Unsigned Byte (8bit UNsigned) into an int reg 5631 instruct loadUB(iRegI dst, memory mem) %{ 5632 match(Set dst (LoadUB mem)); 5633 ins_cost(MEMORY_REF_COST); 5634 5635 size(4); 5636 format %{ "LDUB $mem,$dst\t! ubyte" %} 5637 ins_encode %{ 5638 __ ldub($mem$$Address, $dst$$Register); 5639 %} 5640 ins_pipe(iload_mem); 5641 %} 5642 5643 // Load Unsigned Byte (8bit UNsigned) into a Long Register 5644 instruct loadUB2L(iRegL dst, memory mem) %{ 5645 match(Set dst (ConvI2L (LoadUB mem))); 5646 ins_cost(MEMORY_REF_COST); 5647 5648 size(4); 5649 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5650 ins_encode %{ 5651 __ ldub($mem$$Address, $dst$$Register); 5652 %} 5653 ins_pipe(iload_mem); 5654 %} 5655 5656 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register 5657 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{ 5658 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5659 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5660 5661 size(2*4); 5662 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t" 5663 "AND $dst,right_n_bits($mask, 8),$dst" %} 5664 ins_encode %{ 5665 __ ldub($mem$$Address, $dst$$Register); 5666 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register); 5667 %} 5668 ins_pipe(iload_mem); 5669 %} 5670 5671 // Load Short (16bit signed) 5672 instruct loadS(iRegI dst, memory mem) %{ 5673 match(Set dst (LoadS mem)); 5674 ins_cost(MEMORY_REF_COST); 5675 5676 size(4); 5677 format %{ "LDSH $mem,$dst\t! short" %} 5678 ins_encode %{ 5679 __ ldsh($mem$$Address, $dst$$Register); 5680 %} 5681 ins_pipe(iload_mask_mem); 5682 %} 5683 5684 // Load Short (16 bit signed) to Byte (8 bit signed) 5685 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5686 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5687 ins_cost(MEMORY_REF_COST); 5688 5689 size(4); 5690 5691 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} 5692 ins_encode %{ 5693 __ ldsb($mem$$Address, $dst$$Register, 1); 5694 %} 5695 ins_pipe(iload_mask_mem); 5696 %} 5697 5698 // Load Short (16bit signed) into a Long Register 5699 instruct loadS2L(iRegL dst, memory mem) %{ 5700 match(Set dst (ConvI2L (LoadS mem))); 5701 ins_cost(MEMORY_REF_COST); 5702 5703 size(4); 5704 format %{ "LDSH $mem,$dst\t! short -> long" %} 5705 ins_encode %{ 5706 __ ldsh($mem$$Address, $dst$$Register); 5707 %} 5708 ins_pipe(iload_mask_mem); 5709 %} 5710 5711 // Load Unsigned Short/Char (16bit UNsigned) 5712 instruct loadUS(iRegI dst, memory mem) %{ 5713 match(Set dst (LoadUS mem)); 5714 ins_cost(MEMORY_REF_COST); 5715 5716 size(4); 5717 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5718 ins_encode %{ 5719 __ lduh($mem$$Address, $dst$$Register); 5720 %} 5721 ins_pipe(iload_mem); 5722 %} 5723 5724 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 5725 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5726 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 5727 ins_cost(MEMORY_REF_COST); 5728 5729 size(4); 5730 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} 5731 ins_encode %{ 5732 __ ldsb($mem$$Address, $dst$$Register, 1); 5733 %} 5734 ins_pipe(iload_mask_mem); 5735 %} 5736 5737 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5738 instruct loadUS2L(iRegL dst, memory mem) %{ 5739 match(Set dst (ConvI2L (LoadUS mem))); 5740 ins_cost(MEMORY_REF_COST); 5741 5742 size(4); 5743 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5744 ins_encode %{ 5745 __ lduh($mem$$Address, $dst$$Register); 5746 %} 5747 ins_pipe(iload_mem); 5748 %} 5749 5750 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register 5751 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5752 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5753 ins_cost(MEMORY_REF_COST); 5754 5755 size(4); 5756 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} 5757 ins_encode %{ 5758 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE 5759 %} 5760 ins_pipe(iload_mem); 5761 %} 5762 5763 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register 5764 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5765 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5766 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5767 5768 size(2*4); 5769 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" 5770 "AND $dst,$mask,$dst" %} 5771 ins_encode %{ 5772 Register Rdst = $dst$$Register; 5773 __ lduh($mem$$Address, Rdst); 5774 __ and3(Rdst, $mask$$constant, Rdst); 5775 %} 5776 ins_pipe(iload_mem); 5777 %} 5778 5779 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register 5780 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5781 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5782 effect(TEMP dst, TEMP tmp); 5783 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5784 5785 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t" 5786 "SET right_n_bits($mask, 16),$tmp\n\t" 5787 "AND $dst,$tmp,$dst" %} 5788 ins_encode %{ 5789 Register Rdst = $dst$$Register; 5790 Register Rtmp = $tmp$$Register; 5791 __ lduh($mem$$Address, Rdst); 5792 __ set($mask$$constant & right_n_bits(16), Rtmp); 5793 __ and3(Rdst, Rtmp, Rdst); 5794 %} 5795 ins_pipe(iload_mem); 5796 %} 5797 5798 // Load Integer 5799 instruct loadI(iRegI dst, memory mem) %{ 5800 match(Set dst (LoadI mem)); 5801 ins_cost(MEMORY_REF_COST); 5802 5803 size(4); 5804 format %{ "LDUW $mem,$dst\t! int" %} 5805 ins_encode %{ 5806 __ lduw($mem$$Address, $dst$$Register); 5807 %} 5808 ins_pipe(iload_mem); 5809 %} 5810 5811 // Load Integer to Byte (8 bit signed) 5812 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5813 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 5814 ins_cost(MEMORY_REF_COST); 5815 5816 size(4); 5817 5818 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} 5819 ins_encode %{ 5820 __ ldsb($mem$$Address, $dst$$Register, 3); 5821 %} 5822 ins_pipe(iload_mask_mem); 5823 %} 5824 5825 // Load Integer to Unsigned Byte (8 bit UNsigned) 5826 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ 5827 match(Set dst (AndI (LoadI mem) mask)); 5828 ins_cost(MEMORY_REF_COST); 5829 5830 size(4); 5831 5832 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} 5833 ins_encode %{ 5834 __ ldub($mem$$Address, $dst$$Register, 3); 5835 %} 5836 ins_pipe(iload_mask_mem); 5837 %} 5838 5839 // Load Integer to Short (16 bit signed) 5840 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ 5841 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 5842 ins_cost(MEMORY_REF_COST); 5843 5844 size(4); 5845 5846 format %{ "LDSH $mem+2,$dst\t! int -> short" %} 5847 ins_encode %{ 5848 __ ldsh($mem$$Address, $dst$$Register, 2); 5849 %} 5850 ins_pipe(iload_mask_mem); 5851 %} 5852 5853 // Load Integer to Unsigned Short (16 bit UNsigned) 5854 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ 5855 match(Set dst (AndI (LoadI mem) mask)); 5856 ins_cost(MEMORY_REF_COST); 5857 5858 size(4); 5859 5860 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} 5861 ins_encode %{ 5862 __ lduh($mem$$Address, $dst$$Register, 2); 5863 %} 5864 ins_pipe(iload_mask_mem); 5865 %} 5866 5867 // Load Integer into a Long Register 5868 instruct loadI2L(iRegL dst, memory mem) %{ 5869 match(Set dst (ConvI2L (LoadI mem))); 5870 ins_cost(MEMORY_REF_COST); 5871 5872 size(4); 5873 format %{ "LDSW $mem,$dst\t! int -> long" %} 5874 ins_encode %{ 5875 __ ldsw($mem$$Address, $dst$$Register); 5876 %} 5877 ins_pipe(iload_mask_mem); 5878 %} 5879 5880 // Load Integer with mask 0xFF into a Long Register 5881 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5882 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5883 ins_cost(MEMORY_REF_COST); 5884 5885 size(4); 5886 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} 5887 ins_encode %{ 5888 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE 5889 %} 5890 ins_pipe(iload_mem); 5891 %} 5892 5893 // Load Integer with mask 0xFFFF into a Long Register 5894 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ 5895 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5896 ins_cost(MEMORY_REF_COST); 5897 5898 size(4); 5899 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} 5900 ins_encode %{ 5901 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5902 %} 5903 ins_pipe(iload_mem); 5904 %} 5905 5906 // Load Integer with a 12-bit mask into a Long Register 5907 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ 5908 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5909 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5910 5911 size(2*4); 5912 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" 5913 "AND $dst,$mask,$dst" %} 5914 ins_encode %{ 5915 Register Rdst = $dst$$Register; 5916 __ lduw($mem$$Address, Rdst); 5917 __ and3(Rdst, $mask$$constant, Rdst); 5918 %} 5919 ins_pipe(iload_mem); 5920 %} 5921 5922 // Load Integer with a 31-bit mask into a Long Register 5923 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ 5924 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5925 effect(TEMP dst, TEMP tmp); 5926 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5927 5928 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" 5929 "SET $mask,$tmp\n\t" 5930 "AND $dst,$tmp,$dst" %} 5931 ins_encode %{ 5932 Register Rdst = $dst$$Register; 5933 Register Rtmp = $tmp$$Register; 5934 __ lduw($mem$$Address, Rdst); 5935 __ set($mask$$constant, Rtmp); 5936 __ and3(Rdst, Rtmp, Rdst); 5937 %} 5938 ins_pipe(iload_mem); 5939 %} 5940 5941 // Load Unsigned Integer into a Long Register 5942 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{ 5943 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5944 ins_cost(MEMORY_REF_COST); 5945 5946 size(4); 5947 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5948 ins_encode %{ 5949 __ lduw($mem$$Address, $dst$$Register); 5950 %} 5951 ins_pipe(iload_mem); 5952 %} 5953 5954 // Load Long - aligned 5955 instruct loadL(iRegL dst, memory mem ) %{ 5956 match(Set dst (LoadL mem)); 5957 ins_cost(MEMORY_REF_COST); 5958 5959 size(4); 5960 format %{ "LDX $mem,$dst\t! long" %} 5961 ins_encode %{ 5962 __ ldx($mem$$Address, $dst$$Register); 5963 %} 5964 ins_pipe(iload_mem); 5965 %} 5966 5967 // Load Long - UNaligned 5968 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5969 match(Set dst (LoadL_unaligned mem)); 5970 effect(KILL tmp); 5971 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5972 size(16); 5973 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5974 "\tLDUW $mem ,$dst\n" 5975 "\tSLLX #32, $dst, $dst\n" 5976 "\tOR $dst, R_O7, $dst" %} 5977 opcode(Assembler::lduw_op3); 5978 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); 5979 ins_pipe(iload_mem); 5980 %} 5981 5982 // Load Range 5983 instruct loadRange(iRegI dst, memory mem) %{ 5984 match(Set dst (LoadRange mem)); 5985 ins_cost(MEMORY_REF_COST); 5986 5987 size(4); 5988 format %{ "LDUW $mem,$dst\t! range" %} 5989 opcode(Assembler::lduw_op3); 5990 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5991 ins_pipe(iload_mem); 5992 %} 5993 5994 // Load Integer into %f register (for fitos/fitod) 5995 instruct loadI_freg(regF dst, memory mem) %{ 5996 match(Set dst (LoadI mem)); 5997 ins_cost(MEMORY_REF_COST); 5998 size(4); 5999 6000 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 6001 opcode(Assembler::ldf_op3); 6002 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6003 ins_pipe(floadF_mem); 6004 %} 6005 6006 // Load Pointer 6007 instruct loadP(iRegP dst, memory mem) %{ 6008 match(Set dst (LoadP mem)); 6009 ins_cost(MEMORY_REF_COST); 6010 size(4); 6011 6012 #ifndef _LP64 6013 format %{ "LDUW $mem,$dst\t! ptr" %} 6014 ins_encode %{ 6015 __ lduw($mem$$Address, $dst$$Register); 6016 %} 6017 #else 6018 format %{ "LDX $mem,$dst\t! ptr" %} 6019 ins_encode %{ 6020 __ ldx($mem$$Address, $dst$$Register); 6021 %} 6022 #endif 6023 ins_pipe(iload_mem); 6024 %} 6025 6026 // Load Compressed Pointer 6027 instruct loadN(iRegN dst, memory mem) %{ 6028 match(Set dst (LoadN mem)); 6029 ins_cost(MEMORY_REF_COST); 6030 size(4); 6031 6032 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 6033 ins_encode %{ 6034 __ lduw($mem$$Address, $dst$$Register); 6035 %} 6036 ins_pipe(iload_mem); 6037 %} 6038 6039 // Load Klass Pointer 6040 instruct loadKlass(iRegP dst, memory mem) %{ 6041 match(Set dst (LoadKlass mem)); 6042 ins_cost(MEMORY_REF_COST); 6043 size(4); 6044 6045 #ifndef _LP64 6046 format %{ "LDUW $mem,$dst\t! klass ptr" %} 6047 ins_encode %{ 6048 __ lduw($mem$$Address, $dst$$Register); 6049 %} 6050 #else 6051 format %{ "LDX $mem,$dst\t! klass ptr" %} 6052 ins_encode %{ 6053 __ ldx($mem$$Address, $dst$$Register); 6054 %} 6055 #endif 6056 ins_pipe(iload_mem); 6057 %} 6058 6059 // Load narrow Klass Pointer 6060 instruct loadNKlass(iRegN dst, memory mem) %{ 6061 match(Set dst (LoadNKlass mem)); 6062 ins_cost(MEMORY_REF_COST); 6063 size(4); 6064 6065 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 6066 ins_encode %{ 6067 __ lduw($mem$$Address, $dst$$Register); 6068 %} 6069 ins_pipe(iload_mem); 6070 %} 6071 6072 // Load Double 6073 instruct loadD(regD dst, memory mem) %{ 6074 match(Set dst (LoadD mem)); 6075 ins_cost(MEMORY_REF_COST); 6076 6077 size(4); 6078 format %{ "LDDF $mem,$dst" %} 6079 opcode(Assembler::lddf_op3); 6080 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6081 ins_pipe(floadD_mem); 6082 %} 6083 6084 // Load Double - UNaligned 6085 instruct loadD_unaligned(regD_low dst, memory mem ) %{ 6086 match(Set dst (LoadD_unaligned mem)); 6087 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 6088 size(8); 6089 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 6090 "\tLDF $mem+4,$dst.lo\t!" %} 6091 opcode(Assembler::ldf_op3); 6092 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 6093 ins_pipe(iload_mem); 6094 %} 6095 6096 // Load Float 6097 instruct loadF(regF dst, memory mem) %{ 6098 match(Set dst (LoadF mem)); 6099 ins_cost(MEMORY_REF_COST); 6100 6101 size(4); 6102 format %{ "LDF $mem,$dst" %} 6103 opcode(Assembler::ldf_op3); 6104 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6105 ins_pipe(floadF_mem); 6106 %} 6107 6108 // Load Constant 6109 instruct loadConI( iRegI dst, immI src ) %{ 6110 match(Set dst src); 6111 ins_cost(DEFAULT_COST * 3/2); 6112 format %{ "SET $src,$dst" %} 6113 ins_encode( Set32(src, dst) ); 6114 ins_pipe(ialu_hi_lo_reg); 6115 %} 6116 6117 instruct loadConI13( iRegI dst, immI13 src ) %{ 6118 match(Set dst src); 6119 6120 size(4); 6121 format %{ "MOV $src,$dst" %} 6122 ins_encode( Set13( src, dst ) ); 6123 ins_pipe(ialu_imm); 6124 %} 6125 6126 #ifndef _LP64 6127 instruct loadConP(iRegP dst, immP con) %{ 6128 match(Set dst con); 6129 ins_cost(DEFAULT_COST * 3/2); 6130 format %{ "SET $con,$dst\t!ptr" %} 6131 ins_encode %{ 6132 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); 6133 intptr_t val = $con$$constant; 6134 if (constant_reloc == relocInfo::oop_type) { 6135 __ set_oop_constant((jobject) val, $dst$$Register); 6136 } else if (constant_reloc == relocInfo::metadata_type) { 6137 __ set_metadata_constant((Metadata*)val, $dst$$Register); 6138 } else { // non-oop pointers, e.g. card mark base, heap top 6139 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); 6140 __ set(val, $dst$$Register); 6141 } 6142 %} 6143 ins_pipe(loadConP); 6144 %} 6145 #else 6146 instruct loadConP_set(iRegP dst, immP_set con) %{ 6147 match(Set dst con); 6148 ins_cost(DEFAULT_COST * 3/2); 6149 format %{ "SET $con,$dst\t! ptr" %} 6150 ins_encode %{ 6151 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); 6152 intptr_t val = $con$$constant; 6153 if (constant_reloc == relocInfo::oop_type) { 6154 __ set_oop_constant((jobject) val, $dst$$Register); 6155 } else if (constant_reloc == relocInfo::metadata_type) { 6156 __ set_metadata_constant((Metadata*)val, $dst$$Register); 6157 } else { // non-oop pointers, e.g. card mark base, heap top 6158 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); 6159 __ set(val, $dst$$Register); 6160 } 6161 %} 6162 ins_pipe(loadConP); 6163 %} 6164 6165 instruct loadConP_load(iRegP dst, immP_load con) %{ 6166 match(Set dst con); 6167 ins_cost(MEMORY_REF_COST); 6168 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} 6169 ins_encode %{ 6170 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 6171 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); 6172 %} 6173 ins_pipe(loadConP); 6174 %} 6175 6176 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ 6177 match(Set dst con); 6178 ins_cost(DEFAULT_COST * 3/2); 6179 format %{ "SET $con,$dst\t! non-oop ptr" %} 6180 ins_encode %{ 6181 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) { 6182 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register); 6183 } else { 6184 __ set($con$$constant, $dst$$Register); 6185 } 6186 %} 6187 ins_pipe(loadConP); 6188 %} 6189 #endif // _LP64 6190 6191 instruct loadConP0(iRegP dst, immP0 src) %{ 6192 match(Set dst src); 6193 6194 size(4); 6195 format %{ "CLR $dst\t!ptr" %} 6196 ins_encode %{ 6197 __ clr($dst$$Register); 6198 %} 6199 ins_pipe(ialu_imm); 6200 %} 6201 6202 instruct loadConP_poll(iRegP dst, immP_poll src) %{ 6203 match(Set dst src); 6204 ins_cost(DEFAULT_COST); 6205 format %{ "SET $src,$dst\t!ptr" %} 6206 ins_encode %{ 6207 AddressLiteral polling_page(os::get_polling_page()); 6208 __ sethi(polling_page, reg_to_register_object($dst$$reg)); 6209 %} 6210 ins_pipe(loadConP_poll); 6211 %} 6212 6213 instruct loadConN0(iRegN dst, immN0 src) %{ 6214 match(Set dst src); 6215 6216 size(4); 6217 format %{ "CLR $dst\t! compressed NULL ptr" %} 6218 ins_encode %{ 6219 __ clr($dst$$Register); 6220 %} 6221 ins_pipe(ialu_imm); 6222 %} 6223 6224 instruct loadConN(iRegN dst, immN src) %{ 6225 match(Set dst src); 6226 ins_cost(DEFAULT_COST * 3/2); 6227 format %{ "SET $src,$dst\t! compressed ptr" %} 6228 ins_encode %{ 6229 Register dst = $dst$$Register; 6230 __ set_narrow_oop((jobject)$src$$constant, dst); 6231 %} 6232 ins_pipe(ialu_hi_lo_reg); 6233 %} 6234 6235 instruct loadConNKlass(iRegN dst, immNKlass src) %{ 6236 match(Set dst src); 6237 ins_cost(DEFAULT_COST * 3/2); 6238 format %{ "SET $src,$dst\t! compressed klass ptr" %} 6239 ins_encode %{ 6240 Register dst = $dst$$Register; 6241 __ set_narrow_klass((Klass*)$src$$constant, dst); 6242 %} 6243 ins_pipe(ialu_hi_lo_reg); 6244 %} 6245 6246 // Materialize long value (predicated by immL_cheap). 6247 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ 6248 match(Set dst con); 6249 effect(KILL tmp); 6250 ins_cost(DEFAULT_COST * 3); 6251 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} 6252 ins_encode %{ 6253 __ set64($con$$constant, $dst$$Register, $tmp$$Register); 6254 %} 6255 ins_pipe(loadConL); 6256 %} 6257 6258 // Load long value from constant table (predicated by immL_expensive). 6259 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ 6260 match(Set dst con); 6261 ins_cost(MEMORY_REF_COST); 6262 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} 6263 ins_encode %{ 6264 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 6265 __ ldx($constanttablebase, con_offset, $dst$$Register); 6266 %} 6267 ins_pipe(loadConL); 6268 %} 6269 6270 instruct loadConL0( iRegL dst, immL0 src ) %{ 6271 match(Set dst src); 6272 ins_cost(DEFAULT_COST); 6273 size(4); 6274 format %{ "CLR $dst\t! long" %} 6275 ins_encode( Set13( src, dst ) ); 6276 ins_pipe(ialu_imm); 6277 %} 6278 6279 instruct loadConL13( iRegL dst, immL13 src ) %{ 6280 match(Set dst src); 6281 ins_cost(DEFAULT_COST * 2); 6282 6283 size(4); 6284 format %{ "MOV $src,$dst\t! long" %} 6285 ins_encode( Set13( src, dst ) ); 6286 ins_pipe(ialu_imm); 6287 %} 6288 6289 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ 6290 match(Set dst con); 6291 effect(KILL tmp); 6292 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} 6293 ins_encode %{ 6294 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 6295 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); 6296 %} 6297 ins_pipe(loadConFD); 6298 %} 6299 6300 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ 6301 match(Set dst con); 6302 effect(KILL tmp); 6303 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} 6304 ins_encode %{ 6305 // XXX This is a quick fix for 6833573. 6306 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); 6307 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 6308 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 6309 %} 6310 ins_pipe(loadConFD); 6311 %} 6312 6313 // Prefetch instructions for allocation. 6314 // Must be safe to execute with invalid address (cannot fault). 6315 6316 instruct prefetchAlloc( memory mem ) %{ 6317 predicate(AllocatePrefetchInstr == 0); 6318 match( PrefetchAllocation mem ); 6319 ins_cost(MEMORY_REF_COST); 6320 size(4); 6321 6322 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} 6323 opcode(Assembler::prefetch_op3); 6324 ins_encode( form3_mem_prefetch_write( mem ) ); 6325 ins_pipe(iload_mem); 6326 %} 6327 6328 // Use BIS instruction to prefetch for allocation. 6329 // Could fault, need space at the end of TLAB. 6330 instruct prefetchAlloc_bis( iRegP dst ) %{ 6331 predicate(AllocatePrefetchInstr == 1); 6332 match( PrefetchAllocation dst ); 6333 ins_cost(MEMORY_REF_COST); 6334 size(4); 6335 6336 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} 6337 ins_encode %{ 6338 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); 6339 %} 6340 ins_pipe(istore_mem_reg); 6341 %} 6342 6343 // Next code is used for finding next cache line address to prefetch. 6344 #ifndef _LP64 6345 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{ 6346 match(Set dst (CastX2P (AndI (CastP2X src) mask))); 6347 ins_cost(DEFAULT_COST); 6348 size(4); 6349 6350 format %{ "AND $src,$mask,$dst\t! next cache line address" %} 6351 ins_encode %{ 6352 __ and3($src$$Register, $mask$$constant, $dst$$Register); 6353 %} 6354 ins_pipe(ialu_reg_imm); 6355 %} 6356 #else 6357 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ 6358 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 6359 ins_cost(DEFAULT_COST); 6360 size(4); 6361 6362 format %{ "AND $src,$mask,$dst\t! next cache line address" %} 6363 ins_encode %{ 6364 __ and3($src$$Register, $mask$$constant, $dst$$Register); 6365 %} 6366 ins_pipe(ialu_reg_imm); 6367 %} 6368 #endif 6369 6370 //----------Store Instructions------------------------------------------------- 6371 // Store Byte 6372 instruct storeB(memory mem, iRegI src) %{ 6373 match(Set mem (StoreB mem src)); 6374 ins_cost(MEMORY_REF_COST); 6375 6376 size(4); 6377 format %{ "STB $src,$mem\t! byte" %} 6378 opcode(Assembler::stb_op3); 6379 ins_encode(simple_form3_mem_reg( mem, src ) ); 6380 ins_pipe(istore_mem_reg); 6381 %} 6382 6383 instruct storeB0(memory mem, immI0 src) %{ 6384 match(Set mem (StoreB mem src)); 6385 ins_cost(MEMORY_REF_COST); 6386 6387 size(4); 6388 format %{ "STB $src,$mem\t! byte" %} 6389 opcode(Assembler::stb_op3); 6390 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6391 ins_pipe(istore_mem_zero); 6392 %} 6393 6394 instruct storeCM0(memory mem, immI0 src) %{ 6395 match(Set mem (StoreCM mem src)); 6396 ins_cost(MEMORY_REF_COST); 6397 6398 size(4); 6399 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 6400 opcode(Assembler::stb_op3); 6401 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6402 ins_pipe(istore_mem_zero); 6403 %} 6404 6405 // Store Char/Short 6406 instruct storeC(memory mem, iRegI src) %{ 6407 match(Set mem (StoreC mem src)); 6408 ins_cost(MEMORY_REF_COST); 6409 6410 size(4); 6411 format %{ "STH $src,$mem\t! short" %} 6412 opcode(Assembler::sth_op3); 6413 ins_encode(simple_form3_mem_reg( mem, src ) ); 6414 ins_pipe(istore_mem_reg); 6415 %} 6416 6417 instruct storeC0(memory mem, immI0 src) %{ 6418 match(Set mem (StoreC mem src)); 6419 ins_cost(MEMORY_REF_COST); 6420 6421 size(4); 6422 format %{ "STH $src,$mem\t! short" %} 6423 opcode(Assembler::sth_op3); 6424 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6425 ins_pipe(istore_mem_zero); 6426 %} 6427 6428 // Store Integer 6429 instruct storeI(memory mem, iRegI src) %{ 6430 match(Set mem (StoreI mem src)); 6431 ins_cost(MEMORY_REF_COST); 6432 6433 size(4); 6434 format %{ "STW $src,$mem" %} 6435 opcode(Assembler::stw_op3); 6436 ins_encode(simple_form3_mem_reg( mem, src ) ); 6437 ins_pipe(istore_mem_reg); 6438 %} 6439 6440 // Store Long 6441 instruct storeL(memory mem, iRegL src) %{ 6442 match(Set mem (StoreL mem src)); 6443 ins_cost(MEMORY_REF_COST); 6444 size(4); 6445 format %{ "STX $src,$mem\t! long" %} 6446 opcode(Assembler::stx_op3); 6447 ins_encode(simple_form3_mem_reg( mem, src ) ); 6448 ins_pipe(istore_mem_reg); 6449 %} 6450 6451 instruct storeI0(memory mem, immI0 src) %{ 6452 match(Set mem (StoreI mem src)); 6453 ins_cost(MEMORY_REF_COST); 6454 6455 size(4); 6456 format %{ "STW $src,$mem" %} 6457 opcode(Assembler::stw_op3); 6458 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6459 ins_pipe(istore_mem_zero); 6460 %} 6461 6462 instruct storeL0(memory mem, immL0 src) %{ 6463 match(Set mem (StoreL mem src)); 6464 ins_cost(MEMORY_REF_COST); 6465 6466 size(4); 6467 format %{ "STX $src,$mem" %} 6468 opcode(Assembler::stx_op3); 6469 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6470 ins_pipe(istore_mem_zero); 6471 %} 6472 6473 // Store Integer from float register (used after fstoi) 6474 instruct storeI_Freg(memory mem, regF src) %{ 6475 match(Set mem (StoreI mem src)); 6476 ins_cost(MEMORY_REF_COST); 6477 6478 size(4); 6479 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 6480 opcode(Assembler::stf_op3); 6481 ins_encode(simple_form3_mem_reg( mem, src ) ); 6482 ins_pipe(fstoreF_mem_reg); 6483 %} 6484 6485 // Store Pointer 6486 instruct storeP(memory dst, sp_ptr_RegP src) %{ 6487 match(Set dst (StoreP dst src)); 6488 ins_cost(MEMORY_REF_COST); 6489 size(4); 6490 6491 #ifndef _LP64 6492 format %{ "STW $src,$dst\t! ptr" %} 6493 opcode(Assembler::stw_op3, 0, REGP_OP); 6494 #else 6495 format %{ "STX $src,$dst\t! ptr" %} 6496 opcode(Assembler::stx_op3, 0, REGP_OP); 6497 #endif 6498 ins_encode( form3_mem_reg( dst, src ) ); 6499 ins_pipe(istore_mem_spORreg); 6500 %} 6501 6502 instruct storeP0(memory dst, immP0 src) %{ 6503 match(Set dst (StoreP dst src)); 6504 ins_cost(MEMORY_REF_COST); 6505 size(4); 6506 6507 #ifndef _LP64 6508 format %{ "STW $src,$dst\t! ptr" %} 6509 opcode(Assembler::stw_op3, 0, REGP_OP); 6510 #else 6511 format %{ "STX $src,$dst\t! ptr" %} 6512 opcode(Assembler::stx_op3, 0, REGP_OP); 6513 #endif 6514 ins_encode( form3_mem_reg( dst, R_G0 ) ); 6515 ins_pipe(istore_mem_zero); 6516 %} 6517 6518 // Store Compressed Pointer 6519 instruct storeN(memory dst, iRegN src) %{ 6520 match(Set dst (StoreN dst src)); 6521 ins_cost(MEMORY_REF_COST); 6522 size(4); 6523 6524 format %{ "STW $src,$dst\t! compressed ptr" %} 6525 ins_encode %{ 6526 Register base = as_Register($dst$$base); 6527 Register index = as_Register($dst$$index); 6528 Register src = $src$$Register; 6529 if (index != G0) { 6530 __ stw(src, base, index); 6531 } else { 6532 __ stw(src, base, $dst$$disp); 6533 } 6534 %} 6535 ins_pipe(istore_mem_spORreg); 6536 %} 6537 6538 instruct storeNKlass(memory dst, iRegN src) %{ 6539 match(Set dst (StoreNKlass dst src)); 6540 ins_cost(MEMORY_REF_COST); 6541 size(4); 6542 6543 format %{ "STW $src,$dst\t! compressed klass ptr" %} 6544 ins_encode %{ 6545 Register base = as_Register($dst$$base); 6546 Register index = as_Register($dst$$index); 6547 Register src = $src$$Register; 6548 if (index != G0) { 6549 __ stw(src, base, index); 6550 } else { 6551 __ stw(src, base, $dst$$disp); 6552 } 6553 %} 6554 ins_pipe(istore_mem_spORreg); 6555 %} 6556 6557 instruct storeN0(memory dst, immN0 src) %{ 6558 match(Set dst (StoreN dst src)); 6559 ins_cost(MEMORY_REF_COST); 6560 size(4); 6561 6562 format %{ "STW $src,$dst\t! compressed ptr" %} 6563 ins_encode %{ 6564 Register base = as_Register($dst$$base); 6565 Register index = as_Register($dst$$index); 6566 if (index != G0) { 6567 __ stw(0, base, index); 6568 } else { 6569 __ stw(0, base, $dst$$disp); 6570 } 6571 %} 6572 ins_pipe(istore_mem_zero); 6573 %} 6574 6575 // Store Double 6576 instruct storeD( memory mem, regD src) %{ 6577 match(Set mem (StoreD mem src)); 6578 ins_cost(MEMORY_REF_COST); 6579 6580 size(4); 6581 format %{ "STDF $src,$mem" %} 6582 opcode(Assembler::stdf_op3); 6583 ins_encode(simple_form3_mem_reg( mem, src ) ); 6584 ins_pipe(fstoreD_mem_reg); 6585 %} 6586 6587 instruct storeD0( memory mem, immD0 src) %{ 6588 match(Set mem (StoreD mem src)); 6589 ins_cost(MEMORY_REF_COST); 6590 6591 size(4); 6592 format %{ "STX $src,$mem" %} 6593 opcode(Assembler::stx_op3); 6594 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6595 ins_pipe(fstoreD_mem_zero); 6596 %} 6597 6598 // Store Float 6599 instruct storeF( memory mem, regF src) %{ 6600 match(Set mem (StoreF mem src)); 6601 ins_cost(MEMORY_REF_COST); 6602 6603 size(4); 6604 format %{ "STF $src,$mem" %} 6605 opcode(Assembler::stf_op3); 6606 ins_encode(simple_form3_mem_reg( mem, src ) ); 6607 ins_pipe(fstoreF_mem_reg); 6608 %} 6609 6610 instruct storeF0( memory mem, immF0 src) %{ 6611 match(Set mem (StoreF mem src)); 6612 ins_cost(MEMORY_REF_COST); 6613 6614 size(4); 6615 format %{ "STW $src,$mem\t! storeF0" %} 6616 opcode(Assembler::stw_op3); 6617 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6618 ins_pipe(fstoreF_mem_zero); 6619 %} 6620 6621 // Convert oop pointer into compressed form 6622 instruct encodeHeapOop(iRegN dst, iRegP src) %{ 6623 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6624 match(Set dst (EncodeP src)); 6625 format %{ "encode_heap_oop $src, $dst" %} 6626 ins_encode %{ 6627 __ encode_heap_oop($src$$Register, $dst$$Register); 6628 %} 6629 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE); 6630 ins_pipe(ialu_reg); 6631 %} 6632 6633 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 6634 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6635 match(Set dst (EncodeP src)); 6636 format %{ "encode_heap_oop_not_null $src, $dst" %} 6637 ins_encode %{ 6638 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 6639 %} 6640 ins_pipe(ialu_reg); 6641 %} 6642 6643 instruct decodeHeapOop(iRegP dst, iRegN src) %{ 6644 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6645 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 6646 match(Set dst (DecodeN src)); 6647 format %{ "decode_heap_oop $src, $dst" %} 6648 ins_encode %{ 6649 __ decode_heap_oop($src$$Register, $dst$$Register); 6650 %} 6651 ins_pipe(ialu_reg); 6652 %} 6653 6654 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 6655 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6656 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 6657 match(Set dst (DecodeN src)); 6658 format %{ "decode_heap_oop_not_null $src, $dst" %} 6659 ins_encode %{ 6660 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 6661 %} 6662 ins_pipe(ialu_reg); 6663 %} 6664 6665 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{ 6666 match(Set dst (EncodePKlass src)); 6667 format %{ "encode_klass_not_null $src, $dst" %} 6668 ins_encode %{ 6669 __ encode_klass_not_null($src$$Register, $dst$$Register); 6670 %} 6671 ins_pipe(ialu_reg); 6672 %} 6673 6674 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{ 6675 match(Set dst (DecodeNKlass src)); 6676 format %{ "decode_klass_not_null $src, $dst" %} 6677 ins_encode %{ 6678 __ decode_klass_not_null($src$$Register, $dst$$Register); 6679 %} 6680 ins_pipe(ialu_reg); 6681 %} 6682 6683 //----------MemBar Instructions----------------------------------------------- 6684 // Memory barrier flavors 6685 6686 instruct membar_acquire() %{ 6687 match(MemBarAcquire); 6688 match(LoadFence); 6689 ins_cost(4*MEMORY_REF_COST); 6690 6691 size(0); 6692 format %{ "MEMBAR-acquire" %} 6693 ins_encode( enc_membar_acquire ); 6694 ins_pipe(long_memory_op); 6695 %} 6696 6697 instruct membar_acquire_lock() %{ 6698 match(MemBarAcquireLock); 6699 ins_cost(0); 6700 6701 size(0); 6702 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6703 ins_encode( ); 6704 ins_pipe(empty); 6705 %} 6706 6707 instruct membar_release() %{ 6708 match(MemBarRelease); 6709 match(StoreFence); 6710 ins_cost(4*MEMORY_REF_COST); 6711 6712 size(0); 6713 format %{ "MEMBAR-release" %} 6714 ins_encode( enc_membar_release ); 6715 ins_pipe(long_memory_op); 6716 %} 6717 6718 instruct membar_release_lock() %{ 6719 match(MemBarReleaseLock); 6720 ins_cost(0); 6721 6722 size(0); 6723 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6724 ins_encode( ); 6725 ins_pipe(empty); 6726 %} 6727 6728 instruct membar_volatile() %{ 6729 match(MemBarVolatile); 6730 ins_cost(4*MEMORY_REF_COST); 6731 6732 size(4); 6733 format %{ "MEMBAR-volatile" %} 6734 ins_encode( enc_membar_volatile ); 6735 ins_pipe(long_memory_op); 6736 %} 6737 6738 instruct unnecessary_membar_volatile() %{ 6739 match(MemBarVolatile); 6740 predicate(Matcher::post_store_load_barrier(n)); 6741 ins_cost(0); 6742 6743 size(0); 6744 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6745 ins_encode( ); 6746 ins_pipe(empty); 6747 %} 6748 6749 instruct membar_storestore() %{ 6750 match(MemBarStoreStore); 6751 ins_cost(0); 6752 6753 size(0); 6754 format %{ "!MEMBAR-storestore (empty encoding)" %} 6755 ins_encode( ); 6756 ins_pipe(empty); 6757 %} 6758 6759 //----------Register Move Instructions----------------------------------------- 6760 instruct roundDouble_nop(regD dst) %{ 6761 match(Set dst (RoundDouble dst)); 6762 ins_cost(0); 6763 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6764 ins_encode( ); 6765 ins_pipe(empty); 6766 %} 6767 6768 6769 instruct roundFloat_nop(regF dst) %{ 6770 match(Set dst (RoundFloat dst)); 6771 ins_cost(0); 6772 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6773 ins_encode( ); 6774 ins_pipe(empty); 6775 %} 6776 6777 6778 // Cast Index to Pointer for unsafe natives 6779 instruct castX2P(iRegX src, iRegP dst) %{ 6780 match(Set dst (CastX2P src)); 6781 6782 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6783 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6784 ins_pipe(ialu_reg); 6785 %} 6786 6787 // Cast Pointer to Index for unsafe natives 6788 instruct castP2X(iRegP src, iRegX dst) %{ 6789 match(Set dst (CastP2X src)); 6790 6791 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6792 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6793 ins_pipe(ialu_reg); 6794 %} 6795 6796 instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6797 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6798 match(Set stkSlot src); // chain rule 6799 ins_cost(MEMORY_REF_COST); 6800 format %{ "STDF $src,$stkSlot\t!stk" %} 6801 opcode(Assembler::stdf_op3); 6802 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6803 ins_pipe(fstoreD_stk_reg); 6804 %} 6805 6806 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6807 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6808 match(Set dst stkSlot); // chain rule 6809 ins_cost(MEMORY_REF_COST); 6810 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6811 opcode(Assembler::lddf_op3); 6812 ins_encode(simple_form3_mem_reg(stkSlot, dst)); 6813 ins_pipe(floadD_stk); 6814 %} 6815 6816 instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6817 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6818 match(Set stkSlot src); // chain rule 6819 ins_cost(MEMORY_REF_COST); 6820 format %{ "STF $src,$stkSlot\t!stk" %} 6821 opcode(Assembler::stf_op3); 6822 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6823 ins_pipe(fstoreF_stk_reg); 6824 %} 6825 6826 //----------Conditional Move--------------------------------------------------- 6827 // Conditional move 6828 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6829 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6830 ins_cost(150); 6831 format %{ "MOV$cmp $pcc,$src,$dst" %} 6832 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6833 ins_pipe(ialu_reg); 6834 %} 6835 6836 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6837 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6838 ins_cost(140); 6839 format %{ "MOV$cmp $pcc,$src,$dst" %} 6840 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6841 ins_pipe(ialu_imm); 6842 %} 6843 6844 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6845 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6846 ins_cost(150); 6847 size(4); 6848 format %{ "MOV$cmp $icc,$src,$dst" %} 6849 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6850 ins_pipe(ialu_reg); 6851 %} 6852 6853 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6854 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6855 ins_cost(140); 6856 size(4); 6857 format %{ "MOV$cmp $icc,$src,$dst" %} 6858 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6859 ins_pipe(ialu_imm); 6860 %} 6861 6862 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6863 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6864 ins_cost(150); 6865 size(4); 6866 format %{ "MOV$cmp $icc,$src,$dst" %} 6867 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6868 ins_pipe(ialu_reg); 6869 %} 6870 6871 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6872 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6873 ins_cost(140); 6874 size(4); 6875 format %{ "MOV$cmp $icc,$src,$dst" %} 6876 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6877 ins_pipe(ialu_imm); 6878 %} 6879 6880 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6881 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6882 ins_cost(150); 6883 size(4); 6884 format %{ "MOV$cmp $fcc,$src,$dst" %} 6885 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6886 ins_pipe(ialu_reg); 6887 %} 6888 6889 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6890 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6891 ins_cost(140); 6892 size(4); 6893 format %{ "MOV$cmp $fcc,$src,$dst" %} 6894 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6895 ins_pipe(ialu_imm); 6896 %} 6897 6898 // Conditional move for RegN. Only cmov(reg,reg). 6899 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6900 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6901 ins_cost(150); 6902 format %{ "MOV$cmp $pcc,$src,$dst" %} 6903 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6904 ins_pipe(ialu_reg); 6905 %} 6906 6907 // This instruction also works with CmpN so we don't need cmovNN_reg. 6908 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6909 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6910 ins_cost(150); 6911 size(4); 6912 format %{ "MOV$cmp $icc,$src,$dst" %} 6913 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6914 ins_pipe(ialu_reg); 6915 %} 6916 6917 // This instruction also works with CmpN so we don't need cmovNN_reg. 6918 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ 6919 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6920 ins_cost(150); 6921 size(4); 6922 format %{ "MOV$cmp $icc,$src,$dst" %} 6923 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6924 ins_pipe(ialu_reg); 6925 %} 6926 6927 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6928 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6929 ins_cost(150); 6930 size(4); 6931 format %{ "MOV$cmp $fcc,$src,$dst" %} 6932 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6933 ins_pipe(ialu_reg); 6934 %} 6935 6936 // Conditional move 6937 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6938 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6939 ins_cost(150); 6940 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6941 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6942 ins_pipe(ialu_reg); 6943 %} 6944 6945 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6946 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6947 ins_cost(140); 6948 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6949 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6950 ins_pipe(ialu_imm); 6951 %} 6952 6953 // This instruction also works with CmpN so we don't need cmovPN_reg. 6954 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6955 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6956 ins_cost(150); 6957 6958 size(4); 6959 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6960 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6961 ins_pipe(ialu_reg); 6962 %} 6963 6964 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ 6965 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6966 ins_cost(150); 6967 6968 size(4); 6969 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6970 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6971 ins_pipe(ialu_reg); 6972 %} 6973 6974 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6975 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6976 ins_cost(140); 6977 6978 size(4); 6979 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6980 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6981 ins_pipe(ialu_imm); 6982 %} 6983 6984 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ 6985 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6986 ins_cost(140); 6987 6988 size(4); 6989 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6990 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6991 ins_pipe(ialu_imm); 6992 %} 6993 6994 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 6995 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6996 ins_cost(150); 6997 size(4); 6998 format %{ "MOV$cmp $fcc,$src,$dst" %} 6999 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 7000 ins_pipe(ialu_imm); 7001 %} 7002 7003 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 7004 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 7005 ins_cost(140); 7006 size(4); 7007 format %{ "MOV$cmp $fcc,$src,$dst" %} 7008 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 7009 ins_pipe(ialu_imm); 7010 %} 7011 7012 // Conditional move 7013 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 7014 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 7015 ins_cost(150); 7016 opcode(0x101); 7017 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 7018 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 7019 ins_pipe(int_conditional_float_move); 7020 %} 7021 7022 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 7023 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 7024 ins_cost(150); 7025 7026 size(4); 7027 format %{ "FMOVS$cmp $icc,$src,$dst" %} 7028 opcode(0x101); 7029 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 7030 ins_pipe(int_conditional_float_move); 7031 %} 7032 7033 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ 7034 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 7035 ins_cost(150); 7036 7037 size(4); 7038 format %{ "FMOVS$cmp $icc,$src,$dst" %} 7039 opcode(0x101); 7040 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 7041 ins_pipe(int_conditional_float_move); 7042 %} 7043 7044 // Conditional move, 7045 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 7046 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 7047 ins_cost(150); 7048 size(4); 7049 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 7050 opcode(0x1); 7051 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 7052 ins_pipe(int_conditional_double_move); 7053 %} 7054 7055 // Conditional move 7056 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 7057 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 7058 ins_cost(150); 7059 size(4); 7060 opcode(0x102); 7061 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 7062 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 7063 ins_pipe(int_conditional_double_move); 7064 %} 7065 7066 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 7067 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 7068 ins_cost(150); 7069 7070 size(4); 7071 format %{ "FMOVD$cmp $icc,$src,$dst" %} 7072 opcode(0x102); 7073 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 7074 ins_pipe(int_conditional_double_move); 7075 %} 7076 7077 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ 7078 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 7079 ins_cost(150); 7080 7081 size(4); 7082 format %{ "FMOVD$cmp $icc,$src,$dst" %} 7083 opcode(0x102); 7084 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 7085 ins_pipe(int_conditional_double_move); 7086 %} 7087 7088 // Conditional move, 7089 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 7090 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 7091 ins_cost(150); 7092 size(4); 7093 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 7094 opcode(0x2); 7095 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 7096 ins_pipe(int_conditional_double_move); 7097 %} 7098 7099 // Conditional move 7100 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 7101 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 7102 ins_cost(150); 7103 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 7104 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 7105 ins_pipe(ialu_reg); 7106 %} 7107 7108 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 7109 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 7110 ins_cost(140); 7111 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 7112 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 7113 ins_pipe(ialu_imm); 7114 %} 7115 7116 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 7117 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 7118 ins_cost(150); 7119 7120 size(4); 7121 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 7122 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 7123 ins_pipe(ialu_reg); 7124 %} 7125 7126 7127 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ 7128 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 7129 ins_cost(150); 7130 7131 size(4); 7132 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 7133 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 7134 ins_pipe(ialu_reg); 7135 %} 7136 7137 7138 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 7139 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 7140 ins_cost(150); 7141 7142 size(4); 7143 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 7144 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 7145 ins_pipe(ialu_reg); 7146 %} 7147 7148 7149 7150 //----------OS and Locking Instructions---------------------------------------- 7151 7152 // This name is KNOWN by the ADLC and cannot be changed. 7153 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 7154 // for this guy. 7155 instruct tlsLoadP(g2RegP dst) %{ 7156 match(Set dst (ThreadLocal)); 7157 7158 size(0); 7159 ins_cost(0); 7160 format %{ "# TLS is in G2" %} 7161 ins_encode( /*empty encoding*/ ); 7162 ins_pipe(ialu_none); 7163 %} 7164 7165 instruct checkCastPP( iRegP dst ) %{ 7166 match(Set dst (CheckCastPP dst)); 7167 7168 size(0); 7169 format %{ "# checkcastPP of $dst" %} 7170 ins_encode( /*empty encoding*/ ); 7171 ins_pipe(empty); 7172 %} 7173 7174 7175 instruct castPP( iRegP dst ) %{ 7176 match(Set dst (CastPP dst)); 7177 format %{ "# castPP of $dst" %} 7178 ins_encode( /*empty encoding*/ ); 7179 ins_pipe(empty); 7180 %} 7181 7182 instruct castII( iRegI dst ) %{ 7183 match(Set dst (CastII dst)); 7184 format %{ "# castII of $dst" %} 7185 ins_encode( /*empty encoding*/ ); 7186 ins_cost(0); 7187 ins_pipe(empty); 7188 %} 7189 7190 //----------Arithmetic Instructions-------------------------------------------- 7191 // Addition Instructions 7192 // Register Addition 7193 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7194 match(Set dst (AddI src1 src2)); 7195 7196 size(4); 7197 format %{ "ADD $src1,$src2,$dst" %} 7198 ins_encode %{ 7199 __ add($src1$$Register, $src2$$Register, $dst$$Register); 7200 %} 7201 ins_pipe(ialu_reg_reg); 7202 %} 7203 7204 // Immediate Addition 7205 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7206 match(Set dst (AddI src1 src2)); 7207 7208 size(4); 7209 format %{ "ADD $src1,$src2,$dst" %} 7210 opcode(Assembler::add_op3, Assembler::arith_op); 7211 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7212 ins_pipe(ialu_reg_imm); 7213 %} 7214 7215 // Pointer Register Addition 7216 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 7217 match(Set dst (AddP src1 src2)); 7218 7219 size(4); 7220 format %{ "ADD $src1,$src2,$dst" %} 7221 opcode(Assembler::add_op3, Assembler::arith_op); 7222 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7223 ins_pipe(ialu_reg_reg); 7224 %} 7225 7226 // Pointer Immediate Addition 7227 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 7228 match(Set dst (AddP src1 src2)); 7229 7230 size(4); 7231 format %{ "ADD $src1,$src2,$dst" %} 7232 opcode(Assembler::add_op3, Assembler::arith_op); 7233 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7234 ins_pipe(ialu_reg_imm); 7235 %} 7236 7237 // Long Addition 7238 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7239 match(Set dst (AddL src1 src2)); 7240 7241 size(4); 7242 format %{ "ADD $src1,$src2,$dst\t! long" %} 7243 opcode(Assembler::add_op3, Assembler::arith_op); 7244 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7245 ins_pipe(ialu_reg_reg); 7246 %} 7247 7248 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7249 match(Set dst (AddL src1 con)); 7250 7251 size(4); 7252 format %{ "ADD $src1,$con,$dst" %} 7253 opcode(Assembler::add_op3, Assembler::arith_op); 7254 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7255 ins_pipe(ialu_reg_imm); 7256 %} 7257 7258 //----------Conditional_store-------------------------------------------------- 7259 // Conditional-store of the updated heap-top. 7260 // Used during allocation of the shared heap. 7261 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7262 7263 // LoadP-locked. Same as a regular pointer load when used with a compare-swap 7264 instruct loadPLocked(iRegP dst, memory mem) %{ 7265 match(Set dst (LoadPLocked mem)); 7266 ins_cost(MEMORY_REF_COST); 7267 7268 #ifndef _LP64 7269 size(4); 7270 format %{ "LDUW $mem,$dst\t! ptr" %} 7271 opcode(Assembler::lduw_op3, 0, REGP_OP); 7272 #else 7273 format %{ "LDX $mem,$dst\t! ptr" %} 7274 opcode(Assembler::ldx_op3, 0, REGP_OP); 7275 #endif 7276 ins_encode( form3_mem_reg( mem, dst ) ); 7277 ins_pipe(iload_mem); 7278 %} 7279 7280 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 7281 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 7282 effect( KILL newval ); 7283 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 7284 "CMP R_G3,$oldval\t\t! See if we made progress" %} 7285 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 7286 ins_pipe( long_memory_op ); 7287 %} 7288 7289 // Conditional-store of an int value. 7290 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ 7291 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); 7292 effect( KILL newval ); 7293 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7294 "CMP $oldval,$newval\t\t! See if we made progress" %} 7295 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7296 ins_pipe( long_memory_op ); 7297 %} 7298 7299 // Conditional-store of a long value. 7300 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ 7301 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); 7302 effect( KILL newval ); 7303 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7304 "CMP $oldval,$newval\t\t! See if we made progress" %} 7305 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7306 ins_pipe( long_memory_op ); 7307 %} 7308 7309 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7310 7311 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7312 predicate(VM_Version::supports_cx8()); 7313 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 7314 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7315 format %{ 7316 "MOV $newval,O7\n\t" 7317 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7318 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7319 "MOV 1,$res\n\t" 7320 "MOVne xcc,R_G0,$res" 7321 %} 7322 ins_encode( enc_casx(mem_ptr, oldval, newval), 7323 enc_lflags_ne_to_boolean(res) ); 7324 ins_pipe( long_memory_op ); 7325 %} 7326 7327 7328 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7329 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 7330 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7331 format %{ 7332 "MOV $newval,O7\n\t" 7333 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7334 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7335 "MOV 1,$res\n\t" 7336 "MOVne icc,R_G0,$res" 7337 %} 7338 ins_encode( enc_casi(mem_ptr, oldval, newval), 7339 enc_iflags_ne_to_boolean(res) ); 7340 ins_pipe( long_memory_op ); 7341 %} 7342 7343 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7344 #ifdef _LP64 7345 predicate(VM_Version::supports_cx8()); 7346 #endif 7347 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 7348 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7349 format %{ 7350 "MOV $newval,O7\n\t" 7351 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7352 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7353 "MOV 1,$res\n\t" 7354 "MOVne xcc,R_G0,$res" 7355 %} 7356 #ifdef _LP64 7357 ins_encode( enc_casx(mem_ptr, oldval, newval), 7358 enc_lflags_ne_to_boolean(res) ); 7359 #else 7360 ins_encode( enc_casi(mem_ptr, oldval, newval), 7361 enc_iflags_ne_to_boolean(res) ); 7362 #endif 7363 ins_pipe( long_memory_op ); 7364 %} 7365 7366 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7367 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 7368 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7369 format %{ 7370 "MOV $newval,O7\n\t" 7371 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7372 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7373 "MOV 1,$res\n\t" 7374 "MOVne icc,R_G0,$res" 7375 %} 7376 ins_encode( enc_casi(mem_ptr, oldval, newval), 7377 enc_iflags_ne_to_boolean(res) ); 7378 ins_pipe( long_memory_op ); 7379 %} 7380 7381 instruct xchgI( memory mem, iRegI newval) %{ 7382 match(Set newval (GetAndSetI mem newval)); 7383 format %{ "SWAP [$mem],$newval" %} 7384 size(4); 7385 ins_encode %{ 7386 __ swap($mem$$Address, $newval$$Register); 7387 %} 7388 ins_pipe( long_memory_op ); 7389 %} 7390 7391 #ifndef _LP64 7392 instruct xchgP( memory mem, iRegP newval) %{ 7393 match(Set newval (GetAndSetP mem newval)); 7394 format %{ "SWAP [$mem],$newval" %} 7395 size(4); 7396 ins_encode %{ 7397 __ swap($mem$$Address, $newval$$Register); 7398 %} 7399 ins_pipe( long_memory_op ); 7400 %} 7401 #endif 7402 7403 instruct xchgN( memory mem, iRegN newval) %{ 7404 match(Set newval (GetAndSetN mem newval)); 7405 format %{ "SWAP [$mem],$newval" %} 7406 size(4); 7407 ins_encode %{ 7408 __ swap($mem$$Address, $newval$$Register); 7409 %} 7410 ins_pipe( long_memory_op ); 7411 %} 7412 7413 //--------------------- 7414 // Subtraction Instructions 7415 // Register Subtraction 7416 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7417 match(Set dst (SubI src1 src2)); 7418 7419 size(4); 7420 format %{ "SUB $src1,$src2,$dst" %} 7421 opcode(Assembler::sub_op3, Assembler::arith_op); 7422 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7423 ins_pipe(ialu_reg_reg); 7424 %} 7425 7426 // Immediate Subtraction 7427 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7428 match(Set dst (SubI src1 src2)); 7429 7430 size(4); 7431 format %{ "SUB $src1,$src2,$dst" %} 7432 opcode(Assembler::sub_op3, Assembler::arith_op); 7433 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7434 ins_pipe(ialu_reg_imm); 7435 %} 7436 7437 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 7438 match(Set dst (SubI zero src2)); 7439 7440 size(4); 7441 format %{ "NEG $src2,$dst" %} 7442 opcode(Assembler::sub_op3, Assembler::arith_op); 7443 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7444 ins_pipe(ialu_zero_reg); 7445 %} 7446 7447 // Long subtraction 7448 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7449 match(Set dst (SubL src1 src2)); 7450 7451 size(4); 7452 format %{ "SUB $src1,$src2,$dst\t! long" %} 7453 opcode(Assembler::sub_op3, Assembler::arith_op); 7454 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7455 ins_pipe(ialu_reg_reg); 7456 %} 7457 7458 // Immediate Subtraction 7459 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7460 match(Set dst (SubL src1 con)); 7461 7462 size(4); 7463 format %{ "SUB $src1,$con,$dst\t! long" %} 7464 opcode(Assembler::sub_op3, Assembler::arith_op); 7465 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7466 ins_pipe(ialu_reg_imm); 7467 %} 7468 7469 // Long negation 7470 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 7471 match(Set dst (SubL zero src2)); 7472 7473 size(4); 7474 format %{ "NEG $src2,$dst\t! long" %} 7475 opcode(Assembler::sub_op3, Assembler::arith_op); 7476 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7477 ins_pipe(ialu_zero_reg); 7478 %} 7479 7480 // Multiplication Instructions 7481 // Integer Multiplication 7482 // Register Multiplication 7483 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7484 match(Set dst (MulI src1 src2)); 7485 7486 size(4); 7487 format %{ "MULX $src1,$src2,$dst" %} 7488 opcode(Assembler::mulx_op3, Assembler::arith_op); 7489 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7490 ins_pipe(imul_reg_reg); 7491 %} 7492 7493 // Immediate Multiplication 7494 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7495 match(Set dst (MulI src1 src2)); 7496 7497 size(4); 7498 format %{ "MULX $src1,$src2,$dst" %} 7499 opcode(Assembler::mulx_op3, Assembler::arith_op); 7500 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7501 ins_pipe(imul_reg_imm); 7502 %} 7503 7504 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7505 match(Set dst (MulL src1 src2)); 7506 ins_cost(DEFAULT_COST * 5); 7507 size(4); 7508 format %{ "MULX $src1,$src2,$dst\t! long" %} 7509 opcode(Assembler::mulx_op3, Assembler::arith_op); 7510 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7511 ins_pipe(mulL_reg_reg); 7512 %} 7513 7514 // Immediate Multiplication 7515 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7516 match(Set dst (MulL src1 src2)); 7517 ins_cost(DEFAULT_COST * 5); 7518 size(4); 7519 format %{ "MULX $src1,$src2,$dst" %} 7520 opcode(Assembler::mulx_op3, Assembler::arith_op); 7521 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7522 ins_pipe(mulL_reg_imm); 7523 %} 7524 7525 // Integer Division 7526 // Register Division 7527 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 7528 match(Set dst (DivI src1 src2)); 7529 ins_cost((2+71)*DEFAULT_COST); 7530 7531 format %{ "SRA $src2,0,$src2\n\t" 7532 "SRA $src1,0,$src1\n\t" 7533 "SDIVX $src1,$src2,$dst" %} 7534 ins_encode( idiv_reg( src1, src2, dst ) ); 7535 ins_pipe(sdiv_reg_reg); 7536 %} 7537 7538 // Immediate Division 7539 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 7540 match(Set dst (DivI src1 src2)); 7541 ins_cost((2+71)*DEFAULT_COST); 7542 7543 format %{ "SRA $src1,0,$src1\n\t" 7544 "SDIVX $src1,$src2,$dst" %} 7545 ins_encode( idiv_imm( src1, src2, dst ) ); 7546 ins_pipe(sdiv_reg_imm); 7547 %} 7548 7549 //----------Div-By-10-Expansion------------------------------------------------ 7550 // Extract hi bits of a 32x32->64 bit multiply. 7551 // Expand rule only, not matched 7552 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 7553 effect( DEF dst, USE src1, USE src2 ); 7554 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 7555 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 7556 ins_encode( enc_mul_hi(dst,src1,src2)); 7557 ins_pipe(sdiv_reg_reg); 7558 %} 7559 7560 // Magic constant, reciprocal of 10 7561 instruct loadConI_x66666667(iRegIsafe dst) %{ 7562 effect( DEF dst ); 7563 7564 size(8); 7565 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 7566 ins_encode( Set32(0x66666667, dst) ); 7567 ins_pipe(ialu_hi_lo_reg); 7568 %} 7569 7570 // Register Shift Right Arithmetic Long by 32-63 7571 instruct sra_31( iRegI dst, iRegI src ) %{ 7572 effect( DEF dst, USE src ); 7573 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 7574 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 7575 ins_pipe(ialu_reg_reg); 7576 %} 7577 7578 // Arithmetic Shift Right by 8-bit immediate 7579 instruct sra_reg_2( iRegI dst, iRegI src ) %{ 7580 effect( DEF dst, USE src ); 7581 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 7582 opcode(Assembler::sra_op3, Assembler::arith_op); 7583 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 7584 ins_pipe(ialu_reg_imm); 7585 %} 7586 7587 // Integer DIV with 10 7588 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 7589 match(Set dst (DivI src div)); 7590 ins_cost((6+6)*DEFAULT_COST); 7591 expand %{ 7592 iRegIsafe tmp1; // Killed temps; 7593 iRegIsafe tmp2; // Killed temps; 7594 iRegI tmp3; // Killed temps; 7595 iRegI tmp4; // Killed temps; 7596 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 7597 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 7598 sra_31( tmp3, src ); // SRA src,31 -> tmp3 7599 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 7600 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 7601 %} 7602 %} 7603 7604 // Register Long Division 7605 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7606 match(Set dst (DivL src1 src2)); 7607 ins_cost(DEFAULT_COST*71); 7608 size(4); 7609 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7610 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7611 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7612 ins_pipe(divL_reg_reg); 7613 %} 7614 7615 // Register Long Division 7616 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7617 match(Set dst (DivL src1 src2)); 7618 ins_cost(DEFAULT_COST*71); 7619 size(4); 7620 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7621 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7622 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7623 ins_pipe(divL_reg_imm); 7624 %} 7625 7626 // Integer Remainder 7627 // Register Remainder 7628 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 7629 match(Set dst (ModI src1 src2)); 7630 effect( KILL ccr, KILL temp); 7631 7632 format %{ "SREM $src1,$src2,$dst" %} 7633 ins_encode( irem_reg(src1, src2, dst, temp) ); 7634 ins_pipe(sdiv_reg_reg); 7635 %} 7636 7637 // Immediate Remainder 7638 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 7639 match(Set dst (ModI src1 src2)); 7640 effect( KILL ccr, KILL temp); 7641 7642 format %{ "SREM $src1,$src2,$dst" %} 7643 ins_encode( irem_imm(src1, src2, dst, temp) ); 7644 ins_pipe(sdiv_reg_imm); 7645 %} 7646 7647 // Register Long Remainder 7648 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7649 effect(DEF dst, USE src1, USE src2); 7650 size(4); 7651 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7652 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7653 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7654 ins_pipe(divL_reg_reg); 7655 %} 7656 7657 // Register Long Division 7658 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7659 effect(DEF dst, USE src1, USE src2); 7660 size(4); 7661 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7662 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7663 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7664 ins_pipe(divL_reg_imm); 7665 %} 7666 7667 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7668 effect(DEF dst, USE src1, USE src2); 7669 size(4); 7670 format %{ "MULX $src1,$src2,$dst\t! long" %} 7671 opcode(Assembler::mulx_op3, Assembler::arith_op); 7672 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7673 ins_pipe(mulL_reg_reg); 7674 %} 7675 7676 // Immediate Multiplication 7677 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7678 effect(DEF dst, USE src1, USE src2); 7679 size(4); 7680 format %{ "MULX $src1,$src2,$dst" %} 7681 opcode(Assembler::mulx_op3, Assembler::arith_op); 7682 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7683 ins_pipe(mulL_reg_imm); 7684 %} 7685 7686 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7687 effect(DEF dst, USE src1, USE src2); 7688 size(4); 7689 format %{ "SUB $src1,$src2,$dst\t! long" %} 7690 opcode(Assembler::sub_op3, Assembler::arith_op); 7691 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7692 ins_pipe(ialu_reg_reg); 7693 %} 7694 7695 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 7696 effect(DEF dst, USE src1, USE src2); 7697 size(4); 7698 format %{ "SUB $src1,$src2,$dst\t! long" %} 7699 opcode(Assembler::sub_op3, Assembler::arith_op); 7700 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7701 ins_pipe(ialu_reg_reg); 7702 %} 7703 7704 // Register Long Remainder 7705 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7706 match(Set dst (ModL src1 src2)); 7707 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7708 expand %{ 7709 iRegL tmp1; 7710 iRegL tmp2; 7711 divL_reg_reg_1(tmp1, src1, src2); 7712 mulL_reg_reg_1(tmp2, tmp1, src2); 7713 subL_reg_reg_1(dst, src1, tmp2); 7714 %} 7715 %} 7716 7717 // Register Long Remainder 7718 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7719 match(Set dst (ModL src1 src2)); 7720 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7721 expand %{ 7722 iRegL tmp1; 7723 iRegL tmp2; 7724 divL_reg_imm13_1(tmp1, src1, src2); 7725 mulL_reg_imm13_1(tmp2, tmp1, src2); 7726 subL_reg_reg_2 (dst, src1, tmp2); 7727 %} 7728 %} 7729 7730 // Integer Shift Instructions 7731 // Register Shift Left 7732 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7733 match(Set dst (LShiftI src1 src2)); 7734 7735 size(4); 7736 format %{ "SLL $src1,$src2,$dst" %} 7737 opcode(Assembler::sll_op3, Assembler::arith_op); 7738 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7739 ins_pipe(ialu_reg_reg); 7740 %} 7741 7742 // Register Shift Left Immediate 7743 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7744 match(Set dst (LShiftI src1 src2)); 7745 7746 size(4); 7747 format %{ "SLL $src1,$src2,$dst" %} 7748 opcode(Assembler::sll_op3, Assembler::arith_op); 7749 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7750 ins_pipe(ialu_reg_imm); 7751 %} 7752 7753 // Register Shift Left 7754 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7755 match(Set dst (LShiftL src1 src2)); 7756 7757 size(4); 7758 format %{ "SLLX $src1,$src2,$dst" %} 7759 opcode(Assembler::sllx_op3, Assembler::arith_op); 7760 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7761 ins_pipe(ialu_reg_reg); 7762 %} 7763 7764 // Register Shift Left Immediate 7765 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7766 match(Set dst (LShiftL src1 src2)); 7767 7768 size(4); 7769 format %{ "SLLX $src1,$src2,$dst" %} 7770 opcode(Assembler::sllx_op3, Assembler::arith_op); 7771 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7772 ins_pipe(ialu_reg_imm); 7773 %} 7774 7775 // Register Arithmetic Shift Right 7776 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7777 match(Set dst (RShiftI src1 src2)); 7778 size(4); 7779 format %{ "SRA $src1,$src2,$dst" %} 7780 opcode(Assembler::sra_op3, Assembler::arith_op); 7781 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7782 ins_pipe(ialu_reg_reg); 7783 %} 7784 7785 // Register Arithmetic Shift Right Immediate 7786 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7787 match(Set dst (RShiftI src1 src2)); 7788 7789 size(4); 7790 format %{ "SRA $src1,$src2,$dst" %} 7791 opcode(Assembler::sra_op3, Assembler::arith_op); 7792 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7793 ins_pipe(ialu_reg_imm); 7794 %} 7795 7796 // Register Shift Right Arithmatic Long 7797 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7798 match(Set dst (RShiftL src1 src2)); 7799 7800 size(4); 7801 format %{ "SRAX $src1,$src2,$dst" %} 7802 opcode(Assembler::srax_op3, Assembler::arith_op); 7803 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7804 ins_pipe(ialu_reg_reg); 7805 %} 7806 7807 // Register Shift Left Immediate 7808 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7809 match(Set dst (RShiftL src1 src2)); 7810 7811 size(4); 7812 format %{ "SRAX $src1,$src2,$dst" %} 7813 opcode(Assembler::srax_op3, Assembler::arith_op); 7814 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7815 ins_pipe(ialu_reg_imm); 7816 %} 7817 7818 // Register Shift Right 7819 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7820 match(Set dst (URShiftI src1 src2)); 7821 7822 size(4); 7823 format %{ "SRL $src1,$src2,$dst" %} 7824 opcode(Assembler::srl_op3, Assembler::arith_op); 7825 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7826 ins_pipe(ialu_reg_reg); 7827 %} 7828 7829 // Register Shift Right Immediate 7830 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7831 match(Set dst (URShiftI src1 src2)); 7832 7833 size(4); 7834 format %{ "SRL $src1,$src2,$dst" %} 7835 opcode(Assembler::srl_op3, Assembler::arith_op); 7836 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7837 ins_pipe(ialu_reg_imm); 7838 %} 7839 7840 // Register Shift Right 7841 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7842 match(Set dst (URShiftL src1 src2)); 7843 7844 size(4); 7845 format %{ "SRLX $src1,$src2,$dst" %} 7846 opcode(Assembler::srlx_op3, Assembler::arith_op); 7847 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7848 ins_pipe(ialu_reg_reg); 7849 %} 7850 7851 // Register Shift Right Immediate 7852 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7853 match(Set dst (URShiftL src1 src2)); 7854 7855 size(4); 7856 format %{ "SRLX $src1,$src2,$dst" %} 7857 opcode(Assembler::srlx_op3, Assembler::arith_op); 7858 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7859 ins_pipe(ialu_reg_imm); 7860 %} 7861 7862 // Register Shift Right Immediate with a CastP2X 7863 #ifdef _LP64 7864 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7865 match(Set dst (URShiftL (CastP2X src1) src2)); 7866 size(4); 7867 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7868 opcode(Assembler::srlx_op3, Assembler::arith_op); 7869 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7870 ins_pipe(ialu_reg_imm); 7871 %} 7872 #else 7873 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ 7874 match(Set dst (URShiftI (CastP2X src1) src2)); 7875 size(4); 7876 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} 7877 opcode(Assembler::srl_op3, Assembler::arith_op); 7878 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7879 ins_pipe(ialu_reg_imm); 7880 %} 7881 #endif 7882 7883 7884 //----------Floating Point Arithmetic Instructions----------------------------- 7885 7886 // Add float single precision 7887 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7888 match(Set dst (AddF src1 src2)); 7889 7890 size(4); 7891 format %{ "FADDS $src1,$src2,$dst" %} 7892 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7893 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7894 ins_pipe(faddF_reg_reg); 7895 %} 7896 7897 // Add float double precision 7898 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7899 match(Set dst (AddD src1 src2)); 7900 7901 size(4); 7902 format %{ "FADDD $src1,$src2,$dst" %} 7903 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7904 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7905 ins_pipe(faddD_reg_reg); 7906 %} 7907 7908 // Sub float single precision 7909 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7910 match(Set dst (SubF src1 src2)); 7911 7912 size(4); 7913 format %{ "FSUBS $src1,$src2,$dst" %} 7914 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7915 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7916 ins_pipe(faddF_reg_reg); 7917 %} 7918 7919 // Sub float double precision 7920 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7921 match(Set dst (SubD src1 src2)); 7922 7923 size(4); 7924 format %{ "FSUBD $src1,$src2,$dst" %} 7925 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7926 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7927 ins_pipe(faddD_reg_reg); 7928 %} 7929 7930 // Mul float single precision 7931 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7932 match(Set dst (MulF src1 src2)); 7933 7934 size(4); 7935 format %{ "FMULS $src1,$src2,$dst" %} 7936 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7937 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7938 ins_pipe(fmulF_reg_reg); 7939 %} 7940 7941 // Mul float double precision 7942 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7943 match(Set dst (MulD src1 src2)); 7944 7945 size(4); 7946 format %{ "FMULD $src1,$src2,$dst" %} 7947 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7948 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7949 ins_pipe(fmulD_reg_reg); 7950 %} 7951 7952 // Div float single precision 7953 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7954 match(Set dst (DivF src1 src2)); 7955 7956 size(4); 7957 format %{ "FDIVS $src1,$src2,$dst" %} 7958 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7959 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7960 ins_pipe(fdivF_reg_reg); 7961 %} 7962 7963 // Div float double precision 7964 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7965 match(Set dst (DivD src1 src2)); 7966 7967 size(4); 7968 format %{ "FDIVD $src1,$src2,$dst" %} 7969 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7970 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7971 ins_pipe(fdivD_reg_reg); 7972 %} 7973 7974 // Absolute float double precision 7975 instruct absD_reg(regD dst, regD src) %{ 7976 match(Set dst (AbsD src)); 7977 7978 format %{ "FABSd $src,$dst" %} 7979 ins_encode(fabsd(dst, src)); 7980 ins_pipe(faddD_reg); 7981 %} 7982 7983 // Absolute float single precision 7984 instruct absF_reg(regF dst, regF src) %{ 7985 match(Set dst (AbsF src)); 7986 7987 format %{ "FABSs $src,$dst" %} 7988 ins_encode(fabss(dst, src)); 7989 ins_pipe(faddF_reg); 7990 %} 7991 7992 instruct negF_reg(regF dst, regF src) %{ 7993 match(Set dst (NegF src)); 7994 7995 size(4); 7996 format %{ "FNEGs $src,$dst" %} 7997 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 7998 ins_encode(form3_opf_rs2F_rdF(src, dst)); 7999 ins_pipe(faddF_reg); 8000 %} 8001 8002 instruct negD_reg(regD dst, regD src) %{ 8003 match(Set dst (NegD src)); 8004 8005 format %{ "FNEGd $src,$dst" %} 8006 ins_encode(fnegd(dst, src)); 8007 ins_pipe(faddD_reg); 8008 %} 8009 8010 // Sqrt float double precision 8011 instruct sqrtF_reg_reg(regF dst, regF src) %{ 8012 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 8013 8014 size(4); 8015 format %{ "FSQRTS $src,$dst" %} 8016 ins_encode(fsqrts(dst, src)); 8017 ins_pipe(fdivF_reg_reg); 8018 %} 8019 8020 // Sqrt float double precision 8021 instruct sqrtD_reg_reg(regD dst, regD src) %{ 8022 match(Set dst (SqrtD src)); 8023 8024 size(4); 8025 format %{ "FSQRTD $src,$dst" %} 8026 ins_encode(fsqrtd(dst, src)); 8027 ins_pipe(fdivD_reg_reg); 8028 %} 8029 8030 //----------Logical Instructions----------------------------------------------- 8031 // And Instructions 8032 // Register And 8033 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 8034 match(Set dst (AndI src1 src2)); 8035 8036 size(4); 8037 format %{ "AND $src1,$src2,$dst" %} 8038 opcode(Assembler::and_op3, Assembler::arith_op); 8039 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8040 ins_pipe(ialu_reg_reg); 8041 %} 8042 8043 // Immediate And 8044 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 8045 match(Set dst (AndI src1 src2)); 8046 8047 size(4); 8048 format %{ "AND $src1,$src2,$dst" %} 8049 opcode(Assembler::and_op3, Assembler::arith_op); 8050 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 8051 ins_pipe(ialu_reg_imm); 8052 %} 8053 8054 // Register And Long 8055 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 8056 match(Set dst (AndL src1 src2)); 8057 8058 ins_cost(DEFAULT_COST); 8059 size(4); 8060 format %{ "AND $src1,$src2,$dst\t! long" %} 8061 opcode(Assembler::and_op3, Assembler::arith_op); 8062 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8063 ins_pipe(ialu_reg_reg); 8064 %} 8065 8066 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 8067 match(Set dst (AndL src1 con)); 8068 8069 ins_cost(DEFAULT_COST); 8070 size(4); 8071 format %{ "AND $src1,$con,$dst\t! long" %} 8072 opcode(Assembler::and_op3, Assembler::arith_op); 8073 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8074 ins_pipe(ialu_reg_imm); 8075 %} 8076 8077 // Or Instructions 8078 // Register Or 8079 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 8080 match(Set dst (OrI src1 src2)); 8081 8082 size(4); 8083 format %{ "OR $src1,$src2,$dst" %} 8084 opcode(Assembler::or_op3, Assembler::arith_op); 8085 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8086 ins_pipe(ialu_reg_reg); 8087 %} 8088 8089 // Immediate Or 8090 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 8091 match(Set dst (OrI src1 src2)); 8092 8093 size(4); 8094 format %{ "OR $src1,$src2,$dst" %} 8095 opcode(Assembler::or_op3, Assembler::arith_op); 8096 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 8097 ins_pipe(ialu_reg_imm); 8098 %} 8099 8100 // Register Or Long 8101 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 8102 match(Set dst (OrL src1 src2)); 8103 8104 ins_cost(DEFAULT_COST); 8105 size(4); 8106 format %{ "OR $src1,$src2,$dst\t! long" %} 8107 opcode(Assembler::or_op3, Assembler::arith_op); 8108 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8109 ins_pipe(ialu_reg_reg); 8110 %} 8111 8112 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 8113 match(Set dst (OrL src1 con)); 8114 ins_cost(DEFAULT_COST*2); 8115 8116 ins_cost(DEFAULT_COST); 8117 size(4); 8118 format %{ "OR $src1,$con,$dst\t! long" %} 8119 opcode(Assembler::or_op3, Assembler::arith_op); 8120 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8121 ins_pipe(ialu_reg_imm); 8122 %} 8123 8124 #ifndef _LP64 8125 8126 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. 8127 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ 8128 match(Set dst (OrI src1 (CastP2X src2))); 8129 8130 size(4); 8131 format %{ "OR $src1,$src2,$dst" %} 8132 opcode(Assembler::or_op3, Assembler::arith_op); 8133 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8134 ins_pipe(ialu_reg_reg); 8135 %} 8136 8137 #else 8138 8139 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ 8140 match(Set dst (OrL src1 (CastP2X src2))); 8141 8142 ins_cost(DEFAULT_COST); 8143 size(4); 8144 format %{ "OR $src1,$src2,$dst\t! long" %} 8145 opcode(Assembler::or_op3, Assembler::arith_op); 8146 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8147 ins_pipe(ialu_reg_reg); 8148 %} 8149 8150 #endif 8151 8152 // Xor Instructions 8153 // Register Xor 8154 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 8155 match(Set dst (XorI src1 src2)); 8156 8157 size(4); 8158 format %{ "XOR $src1,$src2,$dst" %} 8159 opcode(Assembler::xor_op3, Assembler::arith_op); 8160 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8161 ins_pipe(ialu_reg_reg); 8162 %} 8163 8164 // Immediate Xor 8165 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 8166 match(Set dst (XorI src1 src2)); 8167 8168 size(4); 8169 format %{ "XOR $src1,$src2,$dst" %} 8170 opcode(Assembler::xor_op3, Assembler::arith_op); 8171 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 8172 ins_pipe(ialu_reg_imm); 8173 %} 8174 8175 // Register Xor Long 8176 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 8177 match(Set dst (XorL src1 src2)); 8178 8179 ins_cost(DEFAULT_COST); 8180 size(4); 8181 format %{ "XOR $src1,$src2,$dst\t! long" %} 8182 opcode(Assembler::xor_op3, Assembler::arith_op); 8183 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8184 ins_pipe(ialu_reg_reg); 8185 %} 8186 8187 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 8188 match(Set dst (XorL src1 con)); 8189 8190 ins_cost(DEFAULT_COST); 8191 size(4); 8192 format %{ "XOR $src1,$con,$dst\t! long" %} 8193 opcode(Assembler::xor_op3, Assembler::arith_op); 8194 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8195 ins_pipe(ialu_reg_imm); 8196 %} 8197 8198 //----------Convert to Boolean------------------------------------------------- 8199 // Nice hack for 32-bit tests but doesn't work for 8200 // 64-bit pointers. 8201 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 8202 match(Set dst (Conv2B src)); 8203 effect( KILL ccr ); 8204 ins_cost(DEFAULT_COST*2); 8205 format %{ "CMP R_G0,$src\n\t" 8206 "ADDX R_G0,0,$dst" %} 8207 ins_encode( enc_to_bool( src, dst ) ); 8208 ins_pipe(ialu_reg_ialu); 8209 %} 8210 8211 #ifndef _LP64 8212 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ 8213 match(Set dst (Conv2B src)); 8214 effect( KILL ccr ); 8215 ins_cost(DEFAULT_COST*2); 8216 format %{ "CMP R_G0,$src\n\t" 8217 "ADDX R_G0,0,$dst" %} 8218 ins_encode( enc_to_bool( src, dst ) ); 8219 ins_pipe(ialu_reg_ialu); 8220 %} 8221 #else 8222 instruct convP2B( iRegI dst, iRegP src ) %{ 8223 match(Set dst (Conv2B src)); 8224 ins_cost(DEFAULT_COST*2); 8225 format %{ "MOV $src,$dst\n\t" 8226 "MOVRNZ $src,1,$dst" %} 8227 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 8228 ins_pipe(ialu_clr_and_mover); 8229 %} 8230 #endif 8231 8232 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ 8233 match(Set dst (CmpLTMask src zero)); 8234 effect(KILL ccr); 8235 size(4); 8236 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} 8237 ins_encode %{ 8238 __ sra($src$$Register, 31, $dst$$Register); 8239 %} 8240 ins_pipe(ialu_reg_imm); 8241 %} 8242 8243 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 8244 match(Set dst (CmpLTMask p q)); 8245 effect( KILL ccr ); 8246 ins_cost(DEFAULT_COST*4); 8247 format %{ "CMP $p,$q\n\t" 8248 "MOV #0,$dst\n\t" 8249 "BLT,a .+8\n\t" 8250 "MOV #-1,$dst" %} 8251 ins_encode( enc_ltmask(p,q,dst) ); 8252 ins_pipe(ialu_reg_reg_ialu); 8253 %} 8254 8255 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 8256 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 8257 effect(KILL ccr, TEMP tmp); 8258 ins_cost(DEFAULT_COST*3); 8259 8260 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 8261 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 8262 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} 8263 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp)); 8264 ins_pipe(cadd_cmpltmask); 8265 %} 8266 8267 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{ 8268 match(Set p (AndI (CmpLTMask p q) y)); 8269 effect(KILL ccr); 8270 ins_cost(DEFAULT_COST*3); 8271 8272 format %{ "CMP $p,$q\n\t" 8273 "MOV $y,$p\n\t" 8274 "MOVge G0,$p" %} 8275 ins_encode %{ 8276 __ cmp($p$$Register, $q$$Register); 8277 __ mov($y$$Register, $p$$Register); 8278 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register); 8279 %} 8280 ins_pipe(ialu_reg_reg_ialu); 8281 %} 8282 8283 //----------------------------------------------------------------- 8284 // Direct raw moves between float and general registers using VIS3. 8285 8286 // ins_pipe(faddF_reg); 8287 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ 8288 predicate(UseVIS >= 3); 8289 match(Set dst (MoveF2I src)); 8290 8291 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} 8292 ins_encode %{ 8293 __ movstouw($src$$FloatRegister, $dst$$Register); 8294 %} 8295 ins_pipe(ialu_reg_reg); 8296 %} 8297 8298 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ 8299 predicate(UseVIS >= 3); 8300 match(Set dst (MoveI2F src)); 8301 8302 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} 8303 ins_encode %{ 8304 __ movwtos($src$$Register, $dst$$FloatRegister); 8305 %} 8306 ins_pipe(ialu_reg_reg); 8307 %} 8308 8309 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ 8310 predicate(UseVIS >= 3); 8311 match(Set dst (MoveD2L src)); 8312 8313 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} 8314 ins_encode %{ 8315 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); 8316 %} 8317 ins_pipe(ialu_reg_reg); 8318 %} 8319 8320 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ 8321 predicate(UseVIS >= 3); 8322 match(Set dst (MoveL2D src)); 8323 8324 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} 8325 ins_encode %{ 8326 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); 8327 %} 8328 ins_pipe(ialu_reg_reg); 8329 %} 8330 8331 8332 // Raw moves between float and general registers using stack. 8333 8334 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 8335 match(Set dst (MoveF2I src)); 8336 effect(DEF dst, USE src); 8337 ins_cost(MEMORY_REF_COST); 8338 8339 size(4); 8340 format %{ "LDUW $src,$dst\t! MoveF2I" %} 8341 opcode(Assembler::lduw_op3); 8342 ins_encode(simple_form3_mem_reg( src, dst ) ); 8343 ins_pipe(iload_mem); 8344 %} 8345 8346 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 8347 match(Set dst (MoveI2F src)); 8348 effect(DEF dst, USE src); 8349 ins_cost(MEMORY_REF_COST); 8350 8351 size(4); 8352 format %{ "LDF $src,$dst\t! MoveI2F" %} 8353 opcode(Assembler::ldf_op3); 8354 ins_encode(simple_form3_mem_reg(src, dst)); 8355 ins_pipe(floadF_stk); 8356 %} 8357 8358 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 8359 match(Set dst (MoveD2L src)); 8360 effect(DEF dst, USE src); 8361 ins_cost(MEMORY_REF_COST); 8362 8363 size(4); 8364 format %{ "LDX $src,$dst\t! MoveD2L" %} 8365 opcode(Assembler::ldx_op3); 8366 ins_encode(simple_form3_mem_reg( src, dst ) ); 8367 ins_pipe(iload_mem); 8368 %} 8369 8370 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8371 match(Set dst (MoveL2D src)); 8372 effect(DEF dst, USE src); 8373 ins_cost(MEMORY_REF_COST); 8374 8375 size(4); 8376 format %{ "LDDF $src,$dst\t! MoveL2D" %} 8377 opcode(Assembler::lddf_op3); 8378 ins_encode(simple_form3_mem_reg(src, dst)); 8379 ins_pipe(floadD_stk); 8380 %} 8381 8382 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 8383 match(Set dst (MoveF2I src)); 8384 effect(DEF dst, USE src); 8385 ins_cost(MEMORY_REF_COST); 8386 8387 size(4); 8388 format %{ "STF $src,$dst\t! MoveF2I" %} 8389 opcode(Assembler::stf_op3); 8390 ins_encode(simple_form3_mem_reg(dst, src)); 8391 ins_pipe(fstoreF_stk_reg); 8392 %} 8393 8394 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8395 match(Set dst (MoveI2F src)); 8396 effect(DEF dst, USE src); 8397 ins_cost(MEMORY_REF_COST); 8398 8399 size(4); 8400 format %{ "STW $src,$dst\t! MoveI2F" %} 8401 opcode(Assembler::stw_op3); 8402 ins_encode(simple_form3_mem_reg( dst, src ) ); 8403 ins_pipe(istore_mem_reg); 8404 %} 8405 8406 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8407 match(Set dst (MoveD2L src)); 8408 effect(DEF dst, USE src); 8409 ins_cost(MEMORY_REF_COST); 8410 8411 size(4); 8412 format %{ "STDF $src,$dst\t! MoveD2L" %} 8413 opcode(Assembler::stdf_op3); 8414 ins_encode(simple_form3_mem_reg(dst, src)); 8415 ins_pipe(fstoreD_stk_reg); 8416 %} 8417 8418 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8419 match(Set dst (MoveL2D src)); 8420 effect(DEF dst, USE src); 8421 ins_cost(MEMORY_REF_COST); 8422 8423 size(4); 8424 format %{ "STX $src,$dst\t! MoveL2D" %} 8425 opcode(Assembler::stx_op3); 8426 ins_encode(simple_form3_mem_reg( dst, src ) ); 8427 ins_pipe(istore_mem_reg); 8428 %} 8429 8430 8431 //----------Arithmetic Conversion Instructions--------------------------------- 8432 // The conversions operations are all Alpha sorted. Please keep it that way! 8433 8434 instruct convD2F_reg(regF dst, regD src) %{ 8435 match(Set dst (ConvD2F src)); 8436 size(4); 8437 format %{ "FDTOS $src,$dst" %} 8438 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 8439 ins_encode(form3_opf_rs2D_rdF(src, dst)); 8440 ins_pipe(fcvtD2F); 8441 %} 8442 8443 8444 // Convert a double to an int in a float register. 8445 // If the double is a NAN, stuff a zero in instead. 8446 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 8447 effect(DEF dst, USE src, KILL fcc0); 8448 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8449 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8450 "FDTOI $src,$dst\t! convert in delay slot\n\t" 8451 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8452 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8453 "skip:" %} 8454 ins_encode(form_d2i_helper(src,dst)); 8455 ins_pipe(fcvtD2I); 8456 %} 8457 8458 instruct convD2I_stk(stackSlotI dst, regD src) %{ 8459 match(Set dst (ConvD2I src)); 8460 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8461 expand %{ 8462 regF tmp; 8463 convD2I_helper(tmp, src); 8464 regF_to_stkI(dst, tmp); 8465 %} 8466 %} 8467 8468 instruct convD2I_reg(iRegI dst, regD src) %{ 8469 predicate(UseVIS >= 3); 8470 match(Set dst (ConvD2I src)); 8471 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8472 expand %{ 8473 regF tmp; 8474 convD2I_helper(tmp, src); 8475 MoveF2I_reg_reg(dst, tmp); 8476 %} 8477 %} 8478 8479 8480 // Convert a double to a long in a double register. 8481 // If the double is a NAN, stuff a zero in instead. 8482 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 8483 effect(DEF dst, USE src, KILL fcc0); 8484 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8485 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8486 "FDTOX $src,$dst\t! convert in delay slot\n\t" 8487 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8488 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8489 "skip:" %} 8490 ins_encode(form_d2l_helper(src,dst)); 8491 ins_pipe(fcvtD2L); 8492 %} 8493 8494 instruct convD2L_stk(stackSlotL dst, regD src) %{ 8495 match(Set dst (ConvD2L src)); 8496 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8497 expand %{ 8498 regD tmp; 8499 convD2L_helper(tmp, src); 8500 regD_to_stkL(dst, tmp); 8501 %} 8502 %} 8503 8504 instruct convD2L_reg(iRegL dst, regD src) %{ 8505 predicate(UseVIS >= 3); 8506 match(Set dst (ConvD2L src)); 8507 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8508 expand %{ 8509 regD tmp; 8510 convD2L_helper(tmp, src); 8511 MoveD2L_reg_reg(dst, tmp); 8512 %} 8513 %} 8514 8515 8516 instruct convF2D_reg(regD dst, regF src) %{ 8517 match(Set dst (ConvF2D src)); 8518 format %{ "FSTOD $src,$dst" %} 8519 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 8520 ins_encode(form3_opf_rs2F_rdD(src, dst)); 8521 ins_pipe(fcvtF2D); 8522 %} 8523 8524 8525 // Convert a float to an int in a float register. 8526 // If the float is a NAN, stuff a zero in instead. 8527 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 8528 effect(DEF dst, USE src, KILL fcc0); 8529 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8530 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8531 "FSTOI $src,$dst\t! convert in delay slot\n\t" 8532 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8533 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8534 "skip:" %} 8535 ins_encode(form_f2i_helper(src,dst)); 8536 ins_pipe(fcvtF2I); 8537 %} 8538 8539 instruct convF2I_stk(stackSlotI dst, regF src) %{ 8540 match(Set dst (ConvF2I src)); 8541 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8542 expand %{ 8543 regF tmp; 8544 convF2I_helper(tmp, src); 8545 regF_to_stkI(dst, tmp); 8546 %} 8547 %} 8548 8549 instruct convF2I_reg(iRegI dst, regF src) %{ 8550 predicate(UseVIS >= 3); 8551 match(Set dst (ConvF2I src)); 8552 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8553 expand %{ 8554 regF tmp; 8555 convF2I_helper(tmp, src); 8556 MoveF2I_reg_reg(dst, tmp); 8557 %} 8558 %} 8559 8560 8561 // Convert a float to a long in a float register. 8562 // If the float is a NAN, stuff a zero in instead. 8563 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 8564 effect(DEF dst, USE src, KILL fcc0); 8565 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8566 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8567 "FSTOX $src,$dst\t! convert in delay slot\n\t" 8568 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8569 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8570 "skip:" %} 8571 ins_encode(form_f2l_helper(src,dst)); 8572 ins_pipe(fcvtF2L); 8573 %} 8574 8575 instruct convF2L_stk(stackSlotL dst, regF src) %{ 8576 match(Set dst (ConvF2L src)); 8577 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8578 expand %{ 8579 regD tmp; 8580 convF2L_helper(tmp, src); 8581 regD_to_stkL(dst, tmp); 8582 %} 8583 %} 8584 8585 instruct convF2L_reg(iRegL dst, regF src) %{ 8586 predicate(UseVIS >= 3); 8587 match(Set dst (ConvF2L src)); 8588 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8589 expand %{ 8590 regD tmp; 8591 convF2L_helper(tmp, src); 8592 MoveD2L_reg_reg(dst, tmp); 8593 %} 8594 %} 8595 8596 8597 instruct convI2D_helper(regD dst, regF tmp) %{ 8598 effect(USE tmp, DEF dst); 8599 format %{ "FITOD $tmp,$dst" %} 8600 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8601 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 8602 ins_pipe(fcvtI2D); 8603 %} 8604 8605 instruct convI2D_stk(stackSlotI src, regD dst) %{ 8606 match(Set dst (ConvI2D src)); 8607 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8608 expand %{ 8609 regF tmp; 8610 stkI_to_regF(tmp, src); 8611 convI2D_helper(dst, tmp); 8612 %} 8613 %} 8614 8615 instruct convI2D_reg(regD_low dst, iRegI src) %{ 8616 predicate(UseVIS >= 3); 8617 match(Set dst (ConvI2D src)); 8618 expand %{ 8619 regF tmp; 8620 MoveI2F_reg_reg(tmp, src); 8621 convI2D_helper(dst, tmp); 8622 %} 8623 %} 8624 8625 instruct convI2D_mem(regD_low dst, memory mem) %{ 8626 match(Set dst (ConvI2D (LoadI mem))); 8627 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8628 size(8); 8629 format %{ "LDF $mem,$dst\n\t" 8630 "FITOD $dst,$dst" %} 8631 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 8632 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8633 ins_pipe(floadF_mem); 8634 %} 8635 8636 8637 instruct convI2F_helper(regF dst, regF tmp) %{ 8638 effect(DEF dst, USE tmp); 8639 format %{ "FITOS $tmp,$dst" %} 8640 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 8641 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 8642 ins_pipe(fcvtI2F); 8643 %} 8644 8645 instruct convI2F_stk(regF dst, stackSlotI src) %{ 8646 match(Set dst (ConvI2F src)); 8647 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8648 expand %{ 8649 regF tmp; 8650 stkI_to_regF(tmp,src); 8651 convI2F_helper(dst, tmp); 8652 %} 8653 %} 8654 8655 instruct convI2F_reg(regF dst, iRegI src) %{ 8656 predicate(UseVIS >= 3); 8657 match(Set dst (ConvI2F src)); 8658 ins_cost(DEFAULT_COST); 8659 expand %{ 8660 regF tmp; 8661 MoveI2F_reg_reg(tmp, src); 8662 convI2F_helper(dst, tmp); 8663 %} 8664 %} 8665 8666 instruct convI2F_mem( regF dst, memory mem ) %{ 8667 match(Set dst (ConvI2F (LoadI mem))); 8668 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8669 size(8); 8670 format %{ "LDF $mem,$dst\n\t" 8671 "FITOS $dst,$dst" %} 8672 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 8673 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8674 ins_pipe(floadF_mem); 8675 %} 8676 8677 8678 instruct convI2L_reg(iRegL dst, iRegI src) %{ 8679 match(Set dst (ConvI2L src)); 8680 size(4); 8681 format %{ "SRA $src,0,$dst\t! int->long" %} 8682 opcode(Assembler::sra_op3, Assembler::arith_op); 8683 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8684 ins_pipe(ialu_reg_reg); 8685 %} 8686 8687 // Zero-extend convert int to long 8688 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 8689 match(Set dst (AndL (ConvI2L src) mask) ); 8690 size(4); 8691 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 8692 opcode(Assembler::srl_op3, Assembler::arith_op); 8693 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8694 ins_pipe(ialu_reg_reg); 8695 %} 8696 8697 // Zero-extend long 8698 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 8699 match(Set dst (AndL src mask) ); 8700 size(4); 8701 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 8702 opcode(Assembler::srl_op3, Assembler::arith_op); 8703 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8704 ins_pipe(ialu_reg_reg); 8705 %} 8706 8707 8708 //----------- 8709 // Long to Double conversion using V8 opcodes. 8710 // Still useful because cheetah traps and becomes 8711 // amazingly slow for some common numbers. 8712 8713 // Magic constant, 0x43300000 8714 instruct loadConI_x43300000(iRegI dst) %{ 8715 effect(DEF dst); 8716 size(4); 8717 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 8718 ins_encode(SetHi22(0x43300000, dst)); 8719 ins_pipe(ialu_none); 8720 %} 8721 8722 // Magic constant, 0x41f00000 8723 instruct loadConI_x41f00000(iRegI dst) %{ 8724 effect(DEF dst); 8725 size(4); 8726 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 8727 ins_encode(SetHi22(0x41f00000, dst)); 8728 ins_pipe(ialu_none); 8729 %} 8730 8731 // Construct a double from two float halves 8732 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 8733 effect(DEF dst, USE src1, USE src2); 8734 size(8); 8735 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 8736 "FMOVS $src2.lo,$dst.lo" %} 8737 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 8738 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 8739 ins_pipe(faddD_reg_reg); 8740 %} 8741 8742 // Convert integer in high half of a double register (in the lower half of 8743 // the double register file) to double 8744 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 8745 effect(DEF dst, USE src); 8746 size(4); 8747 format %{ "FITOD $src,$dst" %} 8748 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8749 ins_encode(form3_opf_rs2D_rdD(src, dst)); 8750 ins_pipe(fcvtLHi2D); 8751 %} 8752 8753 // Add float double precision 8754 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 8755 effect(DEF dst, USE src1, USE src2); 8756 size(4); 8757 format %{ "FADDD $src1,$src2,$dst" %} 8758 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 8759 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8760 ins_pipe(faddD_reg_reg); 8761 %} 8762 8763 // Sub float double precision 8764 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 8765 effect(DEF dst, USE src1, USE src2); 8766 size(4); 8767 format %{ "FSUBD $src1,$src2,$dst" %} 8768 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 8769 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8770 ins_pipe(faddD_reg_reg); 8771 %} 8772 8773 // Mul float double precision 8774 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 8775 effect(DEF dst, USE src1, USE src2); 8776 size(4); 8777 format %{ "FMULD $src1,$src2,$dst" %} 8778 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 8779 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8780 ins_pipe(fmulD_reg_reg); 8781 %} 8782 8783 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ 8784 match(Set dst (ConvL2D src)); 8785 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); 8786 8787 expand %{ 8788 regD_low tmpsrc; 8789 iRegI ix43300000; 8790 iRegI ix41f00000; 8791 stackSlotL lx43300000; 8792 stackSlotL lx41f00000; 8793 regD_low dx43300000; 8794 regD dx41f00000; 8795 regD tmp1; 8796 regD_low tmp2; 8797 regD tmp3; 8798 regD tmp4; 8799 8800 stkL_to_regD(tmpsrc, src); 8801 8802 loadConI_x43300000(ix43300000); 8803 loadConI_x41f00000(ix41f00000); 8804 regI_to_stkLHi(lx43300000, ix43300000); 8805 regI_to_stkLHi(lx41f00000, ix41f00000); 8806 stkL_to_regD(dx43300000, lx43300000); 8807 stkL_to_regD(dx41f00000, lx41f00000); 8808 8809 convI2D_regDHi_regD(tmp1, tmpsrc); 8810 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); 8811 subD_regD_regD(tmp3, tmp2, dx43300000); 8812 mulD_regD_regD(tmp4, tmp1, dx41f00000); 8813 addD_regD_regD(dst, tmp3, tmp4); 8814 %} 8815 %} 8816 8817 // Long to Double conversion using fast fxtof 8818 instruct convL2D_helper(regD dst, regD tmp) %{ 8819 effect(DEF dst, USE tmp); 8820 size(4); 8821 format %{ "FXTOD $tmp,$dst" %} 8822 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 8823 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 8824 ins_pipe(fcvtL2D); 8825 %} 8826 8827 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ 8828 predicate(VM_Version::has_fast_fxtof()); 8829 match(Set dst (ConvL2D src)); 8830 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 8831 expand %{ 8832 regD tmp; 8833 stkL_to_regD(tmp, src); 8834 convL2D_helper(dst, tmp); 8835 %} 8836 %} 8837 8838 instruct convL2D_reg(regD dst, iRegL src) %{ 8839 predicate(UseVIS >= 3); 8840 match(Set dst (ConvL2D src)); 8841 expand %{ 8842 regD tmp; 8843 MoveL2D_reg_reg(tmp, src); 8844 convL2D_helper(dst, tmp); 8845 %} 8846 %} 8847 8848 // Long to Float conversion using fast fxtof 8849 instruct convL2F_helper(regF dst, regD tmp) %{ 8850 effect(DEF dst, USE tmp); 8851 size(4); 8852 format %{ "FXTOS $tmp,$dst" %} 8853 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 8854 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 8855 ins_pipe(fcvtL2F); 8856 %} 8857 8858 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ 8859 match(Set dst (ConvL2F src)); 8860 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8861 expand %{ 8862 regD tmp; 8863 stkL_to_regD(tmp, src); 8864 convL2F_helper(dst, tmp); 8865 %} 8866 %} 8867 8868 instruct convL2F_reg(regF dst, iRegL src) %{ 8869 predicate(UseVIS >= 3); 8870 match(Set dst (ConvL2F src)); 8871 ins_cost(DEFAULT_COST); 8872 expand %{ 8873 regD tmp; 8874 MoveL2D_reg_reg(tmp, src); 8875 convL2F_helper(dst, tmp); 8876 %} 8877 %} 8878 8879 //----------- 8880 8881 instruct convL2I_reg(iRegI dst, iRegL src) %{ 8882 match(Set dst (ConvL2I src)); 8883 #ifndef _LP64 8884 format %{ "MOV $src.lo,$dst\t! long->int" %} 8885 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); 8886 ins_pipe(ialu_move_reg_I_to_L); 8887 #else 8888 size(4); 8889 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 8890 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 8891 ins_pipe(ialu_reg); 8892 #endif 8893 %} 8894 8895 // Register Shift Right Immediate 8896 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8897 match(Set dst (ConvL2I (RShiftL src cnt))); 8898 8899 size(4); 8900 format %{ "SRAX $src,$cnt,$dst" %} 8901 opcode(Assembler::srax_op3, Assembler::arith_op); 8902 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8903 ins_pipe(ialu_reg_imm); 8904 %} 8905 8906 //----------Control Flow Instructions------------------------------------------ 8907 // Compare Instructions 8908 // Compare Integers 8909 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8910 match(Set icc (CmpI op1 op2)); 8911 effect( DEF icc, USE op1, USE op2 ); 8912 8913 size(4); 8914 format %{ "CMP $op1,$op2" %} 8915 opcode(Assembler::subcc_op3, Assembler::arith_op); 8916 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8917 ins_pipe(ialu_cconly_reg_reg); 8918 %} 8919 8920 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8921 match(Set icc (CmpU op1 op2)); 8922 8923 size(4); 8924 format %{ "CMP $op1,$op2\t! unsigned" %} 8925 opcode(Assembler::subcc_op3, Assembler::arith_op); 8926 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8927 ins_pipe(ialu_cconly_reg_reg); 8928 %} 8929 8930 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8931 match(Set icc (CmpI op1 op2)); 8932 effect( DEF icc, USE op1 ); 8933 8934 size(4); 8935 format %{ "CMP $op1,$op2" %} 8936 opcode(Assembler::subcc_op3, Assembler::arith_op); 8937 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8938 ins_pipe(ialu_cconly_reg_imm); 8939 %} 8940 8941 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 8942 match(Set icc (CmpI (AndI op1 op2) zero)); 8943 8944 size(4); 8945 format %{ "BTST $op2,$op1" %} 8946 opcode(Assembler::andcc_op3, Assembler::arith_op); 8947 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8948 ins_pipe(ialu_cconly_reg_reg_zero); 8949 %} 8950 8951 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 8952 match(Set icc (CmpI (AndI op1 op2) zero)); 8953 8954 size(4); 8955 format %{ "BTST $op2,$op1" %} 8956 opcode(Assembler::andcc_op3, Assembler::arith_op); 8957 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8958 ins_pipe(ialu_cconly_reg_imm_zero); 8959 %} 8960 8961 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 8962 match(Set xcc (CmpL op1 op2)); 8963 effect( DEF xcc, USE op1, USE op2 ); 8964 8965 size(4); 8966 format %{ "CMP $op1,$op2\t\t! long" %} 8967 opcode(Assembler::subcc_op3, Assembler::arith_op); 8968 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8969 ins_pipe(ialu_cconly_reg_reg); 8970 %} 8971 8972 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 8973 match(Set xcc (CmpL op1 con)); 8974 effect( DEF xcc, USE op1, USE con ); 8975 8976 size(4); 8977 format %{ "CMP $op1,$con\t\t! long" %} 8978 opcode(Assembler::subcc_op3, Assembler::arith_op); 8979 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8980 ins_pipe(ialu_cconly_reg_reg); 8981 %} 8982 8983 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 8984 match(Set xcc (CmpL (AndL op1 op2) zero)); 8985 effect( DEF xcc, USE op1, USE op2 ); 8986 8987 size(4); 8988 format %{ "BTST $op1,$op2\t\t! long" %} 8989 opcode(Assembler::andcc_op3, Assembler::arith_op); 8990 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8991 ins_pipe(ialu_cconly_reg_reg); 8992 %} 8993 8994 // useful for checking the alignment of a pointer: 8995 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 8996 match(Set xcc (CmpL (AndL op1 con) zero)); 8997 effect( DEF xcc, USE op1, USE con ); 8998 8999 size(4); 9000 format %{ "BTST $op1,$con\t\t! long" %} 9001 opcode(Assembler::andcc_op3, Assembler::arith_op); 9002 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 9003 ins_pipe(ialu_cconly_reg_reg); 9004 %} 9005 9006 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ 9007 match(Set icc (CmpU op1 op2)); 9008 9009 size(4); 9010 format %{ "CMP $op1,$op2\t! unsigned" %} 9011 opcode(Assembler::subcc_op3, Assembler::arith_op); 9012 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 9013 ins_pipe(ialu_cconly_reg_imm); 9014 %} 9015 9016 // Compare Pointers 9017 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 9018 match(Set pcc (CmpP op1 op2)); 9019 9020 size(4); 9021 format %{ "CMP $op1,$op2\t! ptr" %} 9022 opcode(Assembler::subcc_op3, Assembler::arith_op); 9023 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 9024 ins_pipe(ialu_cconly_reg_reg); 9025 %} 9026 9027 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 9028 match(Set pcc (CmpP op1 op2)); 9029 9030 size(4); 9031 format %{ "CMP $op1,$op2\t! ptr" %} 9032 opcode(Assembler::subcc_op3, Assembler::arith_op); 9033 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 9034 ins_pipe(ialu_cconly_reg_imm); 9035 %} 9036 9037 // Compare Narrow oops 9038 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 9039 match(Set icc (CmpN op1 op2)); 9040 9041 size(4); 9042 format %{ "CMP $op1,$op2\t! compressed ptr" %} 9043 opcode(Assembler::subcc_op3, Assembler::arith_op); 9044 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 9045 ins_pipe(ialu_cconly_reg_reg); 9046 %} 9047 9048 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 9049 match(Set icc (CmpN op1 op2)); 9050 9051 size(4); 9052 format %{ "CMP $op1,$op2\t! compressed ptr" %} 9053 opcode(Assembler::subcc_op3, Assembler::arith_op); 9054 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 9055 ins_pipe(ialu_cconly_reg_imm); 9056 %} 9057 9058 //----------Max and Min-------------------------------------------------------- 9059 // Min Instructions 9060 // Conditional move for min 9061 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 9062 effect( USE_DEF op2, USE op1, USE icc ); 9063 9064 size(4); 9065 format %{ "MOVlt icc,$op1,$op2\t! min" %} 9066 opcode(Assembler::less); 9067 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 9068 ins_pipe(ialu_reg_flags); 9069 %} 9070 9071 // Min Register with Register. 9072 instruct minI_eReg(iRegI op1, iRegI op2) %{ 9073 match(Set op2 (MinI op1 op2)); 9074 ins_cost(DEFAULT_COST*2); 9075 expand %{ 9076 flagsReg icc; 9077 compI_iReg(icc,op1,op2); 9078 cmovI_reg_lt(op2,op1,icc); 9079 %} 9080 %} 9081 9082 // Max Instructions 9083 // Conditional move for max 9084 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 9085 effect( USE_DEF op2, USE op1, USE icc ); 9086 format %{ "MOVgt icc,$op1,$op2\t! max" %} 9087 opcode(Assembler::greater); 9088 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 9089 ins_pipe(ialu_reg_flags); 9090 %} 9091 9092 // Max Register with Register 9093 instruct maxI_eReg(iRegI op1, iRegI op2) %{ 9094 match(Set op2 (MaxI op1 op2)); 9095 ins_cost(DEFAULT_COST*2); 9096 expand %{ 9097 flagsReg icc; 9098 compI_iReg(icc,op1,op2); 9099 cmovI_reg_gt(op2,op1,icc); 9100 %} 9101 %} 9102 9103 9104 //----------Float Compares---------------------------------------------------- 9105 // Compare floating, generate condition code 9106 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 9107 match(Set fcc (CmpF src1 src2)); 9108 9109 size(4); 9110 format %{ "FCMPs $fcc,$src1,$src2" %} 9111 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 9112 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 9113 ins_pipe(faddF_fcc_reg_reg_zero); 9114 %} 9115 9116 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 9117 match(Set fcc (CmpD src1 src2)); 9118 9119 size(4); 9120 format %{ "FCMPd $fcc,$src1,$src2" %} 9121 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 9122 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 9123 ins_pipe(faddD_fcc_reg_reg_zero); 9124 %} 9125 9126 9127 // Compare floating, generate -1,0,1 9128 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 9129 match(Set dst (CmpF3 src1 src2)); 9130 effect(KILL fcc0); 9131 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 9132 format %{ "fcmpl $dst,$src1,$src2" %} 9133 // Primary = float 9134 opcode( true ); 9135 ins_encode( floating_cmp( dst, src1, src2 ) ); 9136 ins_pipe( floating_cmp ); 9137 %} 9138 9139 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 9140 match(Set dst (CmpD3 src1 src2)); 9141 effect(KILL fcc0); 9142 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 9143 format %{ "dcmpl $dst,$src1,$src2" %} 9144 // Primary = double (not float) 9145 opcode( false ); 9146 ins_encode( floating_cmp( dst, src1, src2 ) ); 9147 ins_pipe( floating_cmp ); 9148 %} 9149 9150 //----------Branches--------------------------------------------------------- 9151 // Jump 9152 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 9153 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 9154 match(Jump switch_val); 9155 effect(TEMP table); 9156 9157 ins_cost(350); 9158 9159 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" 9160 "LD [O7 + $switch_val], O7\n\t" 9161 "JUMP O7" %} 9162 ins_encode %{ 9163 // Calculate table address into a register. 9164 Register table_reg; 9165 Register label_reg = O7; 9166 // If we are calculating the size of this instruction don't trust 9167 // zero offsets because they might change when 9168 // MachConstantBaseNode decides to optimize the constant table 9169 // base. 9170 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { 9171 table_reg = $constanttablebase; 9172 } else { 9173 table_reg = O7; 9174 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); 9175 __ add($constanttablebase, con_offset, table_reg); 9176 } 9177 9178 // Jump to base address + switch value 9179 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); 9180 __ jmp(label_reg, G0); 9181 __ delayed()->nop(); 9182 %} 9183 ins_pipe(ialu_reg_reg); 9184 %} 9185 9186 // Direct Branch. Use V8 version with longer range. 9187 instruct branch(label labl) %{ 9188 match(Goto); 9189 effect(USE labl); 9190 9191 size(8); 9192 ins_cost(BRANCH_COST); 9193 format %{ "BA $labl" %} 9194 ins_encode %{ 9195 Label* L = $labl$$label; 9196 __ ba(*L); 9197 __ delayed()->nop(); 9198 %} 9199 ins_avoid_back_to_back(AVOID_BEFORE); 9200 ins_pipe(br); 9201 %} 9202 9203 // Direct Branch, short with no delay slot 9204 instruct branch_short(label labl) %{ 9205 match(Goto); 9206 predicate(UseCBCond); 9207 effect(USE labl); 9208 9209 size(4); 9210 ins_cost(BRANCH_COST); 9211 format %{ "BA $labl\t! short branch" %} 9212 ins_encode %{ 9213 Label* L = $labl$$label; 9214 assert(__ use_cbcond(*L), "back to back cbcond"); 9215 __ ba_short(*L); 9216 %} 9217 ins_short_branch(1); 9218 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9219 ins_pipe(cbcond_reg_imm); 9220 %} 9221 9222 // Conditional Direct Branch 9223 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 9224 match(If cmp icc); 9225 effect(USE labl); 9226 9227 size(8); 9228 ins_cost(BRANCH_COST); 9229 format %{ "BP$cmp $icc,$labl" %} 9230 // Prim = bits 24-22, Secnd = bits 31-30 9231 ins_encode( enc_bp( labl, cmp, icc ) ); 9232 ins_avoid_back_to_back(AVOID_BEFORE); 9233 ins_pipe(br_cc); 9234 %} 9235 9236 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9237 match(If cmp icc); 9238 effect(USE labl); 9239 9240 ins_cost(BRANCH_COST); 9241 format %{ "BP$cmp $icc,$labl" %} 9242 // Prim = bits 24-22, Secnd = bits 31-30 9243 ins_encode( enc_bp( labl, cmp, icc ) ); 9244 ins_avoid_back_to_back(AVOID_BEFORE); 9245 ins_pipe(br_cc); 9246 %} 9247 9248 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 9249 match(If cmp pcc); 9250 effect(USE labl); 9251 9252 size(8); 9253 ins_cost(BRANCH_COST); 9254 format %{ "BP$cmp $pcc,$labl" %} 9255 ins_encode %{ 9256 Label* L = $labl$$label; 9257 Assembler::Predict predict_taken = 9258 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9259 9260 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9261 __ delayed()->nop(); 9262 %} 9263 ins_avoid_back_to_back(AVOID_BEFORE); 9264 ins_pipe(br_cc); 9265 %} 9266 9267 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 9268 match(If cmp fcc); 9269 effect(USE labl); 9270 9271 size(8); 9272 ins_cost(BRANCH_COST); 9273 format %{ "FBP$cmp $fcc,$labl" %} 9274 ins_encode %{ 9275 Label* L = $labl$$label; 9276 Assembler::Predict predict_taken = 9277 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9278 9279 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); 9280 __ delayed()->nop(); 9281 %} 9282 ins_avoid_back_to_back(AVOID_BEFORE); 9283 ins_pipe(br_fcc); 9284 %} 9285 9286 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 9287 match(CountedLoopEnd cmp icc); 9288 effect(USE labl); 9289 9290 size(8); 9291 ins_cost(BRANCH_COST); 9292 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9293 // Prim = bits 24-22, Secnd = bits 31-30 9294 ins_encode( enc_bp( labl, cmp, icc ) ); 9295 ins_avoid_back_to_back(AVOID_BEFORE); 9296 ins_pipe(br_cc); 9297 %} 9298 9299 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9300 match(CountedLoopEnd cmp icc); 9301 effect(USE labl); 9302 9303 size(8); 9304 ins_cost(BRANCH_COST); 9305 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9306 // Prim = bits 24-22, Secnd = bits 31-30 9307 ins_encode( enc_bp( labl, cmp, icc ) ); 9308 ins_avoid_back_to_back(AVOID_BEFORE); 9309 ins_pipe(br_cc); 9310 %} 9311 9312 // Compare and branch instructions 9313 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9314 match(If cmp (CmpI op1 op2)); 9315 effect(USE labl, KILL icc); 9316 9317 size(12); 9318 ins_cost(BRANCH_COST); 9319 format %{ "CMP $op1,$op2\t! int\n\t" 9320 "BP$cmp $labl" %} 9321 ins_encode %{ 9322 Label* L = $labl$$label; 9323 Assembler::Predict predict_taken = 9324 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9325 __ cmp($op1$$Register, $op2$$Register); 9326 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9327 __ delayed()->nop(); 9328 %} 9329 ins_pipe(cmp_br_reg_reg); 9330 %} 9331 9332 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9333 match(If cmp (CmpI op1 op2)); 9334 effect(USE labl, KILL icc); 9335 9336 size(12); 9337 ins_cost(BRANCH_COST); 9338 format %{ "CMP $op1,$op2\t! int\n\t" 9339 "BP$cmp $labl" %} 9340 ins_encode %{ 9341 Label* L = $labl$$label; 9342 Assembler::Predict predict_taken = 9343 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9344 __ cmp($op1$$Register, $op2$$constant); 9345 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9346 __ delayed()->nop(); 9347 %} 9348 ins_pipe(cmp_br_reg_imm); 9349 %} 9350 9351 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9352 match(If cmp (CmpU op1 op2)); 9353 effect(USE labl, KILL icc); 9354 9355 size(12); 9356 ins_cost(BRANCH_COST); 9357 format %{ "CMP $op1,$op2\t! unsigned\n\t" 9358 "BP$cmp $labl" %} 9359 ins_encode %{ 9360 Label* L = $labl$$label; 9361 Assembler::Predict predict_taken = 9362 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9363 __ cmp($op1$$Register, $op2$$Register); 9364 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9365 __ delayed()->nop(); 9366 %} 9367 ins_pipe(cmp_br_reg_reg); 9368 %} 9369 9370 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9371 match(If cmp (CmpU op1 op2)); 9372 effect(USE labl, KILL icc); 9373 9374 size(12); 9375 ins_cost(BRANCH_COST); 9376 format %{ "CMP $op1,$op2\t! unsigned\n\t" 9377 "BP$cmp $labl" %} 9378 ins_encode %{ 9379 Label* L = $labl$$label; 9380 Assembler::Predict predict_taken = 9381 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9382 __ cmp($op1$$Register, $op2$$constant); 9383 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9384 __ delayed()->nop(); 9385 %} 9386 ins_pipe(cmp_br_reg_imm); 9387 %} 9388 9389 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9390 match(If cmp (CmpL op1 op2)); 9391 effect(USE labl, KILL xcc); 9392 9393 size(12); 9394 ins_cost(BRANCH_COST); 9395 format %{ "CMP $op1,$op2\t! long\n\t" 9396 "BP$cmp $labl" %} 9397 ins_encode %{ 9398 Label* L = $labl$$label; 9399 Assembler::Predict predict_taken = 9400 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9401 __ cmp($op1$$Register, $op2$$Register); 9402 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9403 __ delayed()->nop(); 9404 %} 9405 ins_pipe(cmp_br_reg_reg); 9406 %} 9407 9408 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9409 match(If cmp (CmpL op1 op2)); 9410 effect(USE labl, KILL xcc); 9411 9412 size(12); 9413 ins_cost(BRANCH_COST); 9414 format %{ "CMP $op1,$op2\t! long\n\t" 9415 "BP$cmp $labl" %} 9416 ins_encode %{ 9417 Label* L = $labl$$label; 9418 Assembler::Predict predict_taken = 9419 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9420 __ cmp($op1$$Register, $op2$$constant); 9421 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9422 __ delayed()->nop(); 9423 %} 9424 ins_pipe(cmp_br_reg_imm); 9425 %} 9426 9427 // Compare Pointers and branch 9428 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9429 match(If cmp (CmpP op1 op2)); 9430 effect(USE labl, KILL pcc); 9431 9432 size(12); 9433 ins_cost(BRANCH_COST); 9434 format %{ "CMP $op1,$op2\t! ptr\n\t" 9435 "B$cmp $labl" %} 9436 ins_encode %{ 9437 Label* L = $labl$$label; 9438 Assembler::Predict predict_taken = 9439 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9440 __ cmp($op1$$Register, $op2$$Register); 9441 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9442 __ delayed()->nop(); 9443 %} 9444 ins_pipe(cmp_br_reg_reg); 9445 %} 9446 9447 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9448 match(If cmp (CmpP op1 null)); 9449 effect(USE labl, KILL pcc); 9450 9451 size(12); 9452 ins_cost(BRANCH_COST); 9453 format %{ "CMP $op1,0\t! ptr\n\t" 9454 "B$cmp $labl" %} 9455 ins_encode %{ 9456 Label* L = $labl$$label; 9457 Assembler::Predict predict_taken = 9458 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9459 __ cmp($op1$$Register, G0); 9460 // bpr() is not used here since it has shorter distance. 9461 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9462 __ delayed()->nop(); 9463 %} 9464 ins_pipe(cmp_br_reg_reg); 9465 %} 9466 9467 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9468 match(If cmp (CmpN op1 op2)); 9469 effect(USE labl, KILL icc); 9470 9471 size(12); 9472 ins_cost(BRANCH_COST); 9473 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" 9474 "BP$cmp $labl" %} 9475 ins_encode %{ 9476 Label* L = $labl$$label; 9477 Assembler::Predict predict_taken = 9478 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9479 __ cmp($op1$$Register, $op2$$Register); 9480 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9481 __ delayed()->nop(); 9482 %} 9483 ins_pipe(cmp_br_reg_reg); 9484 %} 9485 9486 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9487 match(If cmp (CmpN op1 null)); 9488 effect(USE labl, KILL icc); 9489 9490 size(12); 9491 ins_cost(BRANCH_COST); 9492 format %{ "CMP $op1,0\t! compressed ptr\n\t" 9493 "BP$cmp $labl" %} 9494 ins_encode %{ 9495 Label* L = $labl$$label; 9496 Assembler::Predict predict_taken = 9497 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9498 __ cmp($op1$$Register, G0); 9499 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9500 __ delayed()->nop(); 9501 %} 9502 ins_pipe(cmp_br_reg_reg); 9503 %} 9504 9505 // Loop back branch 9506 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9507 match(CountedLoopEnd cmp (CmpI op1 op2)); 9508 effect(USE labl, KILL icc); 9509 9510 size(12); 9511 ins_cost(BRANCH_COST); 9512 format %{ "CMP $op1,$op2\t! int\n\t" 9513 "BP$cmp $labl\t! Loop end" %} 9514 ins_encode %{ 9515 Label* L = $labl$$label; 9516 Assembler::Predict predict_taken = 9517 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9518 __ cmp($op1$$Register, $op2$$Register); 9519 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9520 __ delayed()->nop(); 9521 %} 9522 ins_pipe(cmp_br_reg_reg); 9523 %} 9524 9525 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9526 match(CountedLoopEnd cmp (CmpI op1 op2)); 9527 effect(USE labl, KILL icc); 9528 9529 size(12); 9530 ins_cost(BRANCH_COST); 9531 format %{ "CMP $op1,$op2\t! int\n\t" 9532 "BP$cmp $labl\t! Loop end" %} 9533 ins_encode %{ 9534 Label* L = $labl$$label; 9535 Assembler::Predict predict_taken = 9536 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9537 __ cmp($op1$$Register, $op2$$constant); 9538 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9539 __ delayed()->nop(); 9540 %} 9541 ins_pipe(cmp_br_reg_imm); 9542 %} 9543 9544 // Short compare and branch instructions 9545 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9546 match(If cmp (CmpI op1 op2)); 9547 predicate(UseCBCond); 9548 effect(USE labl, KILL icc); 9549 9550 size(4); 9551 ins_cost(BRANCH_COST); 9552 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 9553 ins_encode %{ 9554 Label* L = $labl$$label; 9555 assert(__ use_cbcond(*L), "back to back cbcond"); 9556 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9557 %} 9558 ins_short_branch(1); 9559 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9560 ins_pipe(cbcond_reg_reg); 9561 %} 9562 9563 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9564 match(If cmp (CmpI op1 op2)); 9565 predicate(UseCBCond); 9566 effect(USE labl, KILL icc); 9567 9568 size(4); 9569 ins_cost(BRANCH_COST); 9570 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 9571 ins_encode %{ 9572 Label* L = $labl$$label; 9573 assert(__ use_cbcond(*L), "back to back cbcond"); 9574 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9575 %} 9576 ins_short_branch(1); 9577 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9578 ins_pipe(cbcond_reg_imm); 9579 %} 9580 9581 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9582 match(If cmp (CmpU op1 op2)); 9583 predicate(UseCBCond); 9584 effect(USE labl, KILL icc); 9585 9586 size(4); 9587 ins_cost(BRANCH_COST); 9588 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9589 ins_encode %{ 9590 Label* L = $labl$$label; 9591 assert(__ use_cbcond(*L), "back to back cbcond"); 9592 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9593 %} 9594 ins_short_branch(1); 9595 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9596 ins_pipe(cbcond_reg_reg); 9597 %} 9598 9599 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9600 match(If cmp (CmpU op1 op2)); 9601 predicate(UseCBCond); 9602 effect(USE labl, KILL icc); 9603 9604 size(4); 9605 ins_cost(BRANCH_COST); 9606 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9607 ins_encode %{ 9608 Label* L = $labl$$label; 9609 assert(__ use_cbcond(*L), "back to back cbcond"); 9610 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9611 %} 9612 ins_short_branch(1); 9613 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9614 ins_pipe(cbcond_reg_imm); 9615 %} 9616 9617 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9618 match(If cmp (CmpL op1 op2)); 9619 predicate(UseCBCond); 9620 effect(USE labl, KILL xcc); 9621 9622 size(4); 9623 ins_cost(BRANCH_COST); 9624 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9625 ins_encode %{ 9626 Label* L = $labl$$label; 9627 assert(__ use_cbcond(*L), "back to back cbcond"); 9628 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); 9629 %} 9630 ins_short_branch(1); 9631 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9632 ins_pipe(cbcond_reg_reg); 9633 %} 9634 9635 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9636 match(If cmp (CmpL op1 op2)); 9637 predicate(UseCBCond); 9638 effect(USE labl, KILL xcc); 9639 9640 size(4); 9641 ins_cost(BRANCH_COST); 9642 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9643 ins_encode %{ 9644 Label* L = $labl$$label; 9645 assert(__ use_cbcond(*L), "back to back cbcond"); 9646 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); 9647 %} 9648 ins_short_branch(1); 9649 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9650 ins_pipe(cbcond_reg_imm); 9651 %} 9652 9653 // Compare Pointers and branch 9654 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9655 match(If cmp (CmpP op1 op2)); 9656 predicate(UseCBCond); 9657 effect(USE labl, KILL pcc); 9658 9659 size(4); 9660 ins_cost(BRANCH_COST); 9661 #ifdef _LP64 9662 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} 9663 #else 9664 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} 9665 #endif 9666 ins_encode %{ 9667 Label* L = $labl$$label; 9668 assert(__ use_cbcond(*L), "back to back cbcond"); 9669 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); 9670 %} 9671 ins_short_branch(1); 9672 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9673 ins_pipe(cbcond_reg_reg); 9674 %} 9675 9676 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9677 match(If cmp (CmpP op1 null)); 9678 predicate(UseCBCond); 9679 effect(USE labl, KILL pcc); 9680 9681 size(4); 9682 ins_cost(BRANCH_COST); 9683 #ifdef _LP64 9684 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} 9685 #else 9686 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} 9687 #endif 9688 ins_encode %{ 9689 Label* L = $labl$$label; 9690 assert(__ use_cbcond(*L), "back to back cbcond"); 9691 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); 9692 %} 9693 ins_short_branch(1); 9694 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9695 ins_pipe(cbcond_reg_reg); 9696 %} 9697 9698 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9699 match(If cmp (CmpN op1 op2)); 9700 predicate(UseCBCond); 9701 effect(USE labl, KILL icc); 9702 9703 size(4); 9704 ins_cost(BRANCH_COST); 9705 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %} 9706 ins_encode %{ 9707 Label* L = $labl$$label; 9708 assert(__ use_cbcond(*L), "back to back cbcond"); 9709 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9710 %} 9711 ins_short_branch(1); 9712 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9713 ins_pipe(cbcond_reg_reg); 9714 %} 9715 9716 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9717 match(If cmp (CmpN op1 null)); 9718 predicate(UseCBCond); 9719 effect(USE labl, KILL icc); 9720 9721 size(4); 9722 ins_cost(BRANCH_COST); 9723 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} 9724 ins_encode %{ 9725 Label* L = $labl$$label; 9726 assert(__ use_cbcond(*L), "back to back cbcond"); 9727 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); 9728 %} 9729 ins_short_branch(1); 9730 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9731 ins_pipe(cbcond_reg_reg); 9732 %} 9733 9734 // Loop back branch 9735 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9736 match(CountedLoopEnd cmp (CmpI op1 op2)); 9737 predicate(UseCBCond); 9738 effect(USE labl, KILL icc); 9739 9740 size(4); 9741 ins_cost(BRANCH_COST); 9742 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9743 ins_encode %{ 9744 Label* L = $labl$$label; 9745 assert(__ use_cbcond(*L), "back to back cbcond"); 9746 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9747 %} 9748 ins_short_branch(1); 9749 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9750 ins_pipe(cbcond_reg_reg); 9751 %} 9752 9753 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9754 match(CountedLoopEnd cmp (CmpI op1 op2)); 9755 predicate(UseCBCond); 9756 effect(USE labl, KILL icc); 9757 9758 size(4); 9759 ins_cost(BRANCH_COST); 9760 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9761 ins_encode %{ 9762 Label* L = $labl$$label; 9763 assert(__ use_cbcond(*L), "back to back cbcond"); 9764 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9765 %} 9766 ins_short_branch(1); 9767 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9768 ins_pipe(cbcond_reg_imm); 9769 %} 9770 9771 // Branch-on-register tests all 64 bits. We assume that values 9772 // in 64-bit registers always remains zero or sign extended 9773 // unless our code munges the high bits. Interrupts can chop 9774 // the high order bits to zero or sign at any time. 9775 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 9776 match(If cmp (CmpI op1 zero)); 9777 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9778 effect(USE labl); 9779 9780 size(8); 9781 ins_cost(BRANCH_COST); 9782 format %{ "BR$cmp $op1,$labl" %} 9783 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9784 ins_avoid_back_to_back(AVOID_BEFORE); 9785 ins_pipe(br_reg); 9786 %} 9787 9788 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 9789 match(If cmp (CmpP op1 null)); 9790 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9791 effect(USE labl); 9792 9793 size(8); 9794 ins_cost(BRANCH_COST); 9795 format %{ "BR$cmp $op1,$labl" %} 9796 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9797 ins_avoid_back_to_back(AVOID_BEFORE); 9798 ins_pipe(br_reg); 9799 %} 9800 9801 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 9802 match(If cmp (CmpL op1 zero)); 9803 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9804 effect(USE labl); 9805 9806 size(8); 9807 ins_cost(BRANCH_COST); 9808 format %{ "BR$cmp $op1,$labl" %} 9809 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9810 ins_avoid_back_to_back(AVOID_BEFORE); 9811 ins_pipe(br_reg); 9812 %} 9813 9814 9815 // ============================================================================ 9816 // Long Compare 9817 // 9818 // Currently we hold longs in 2 registers. Comparing such values efficiently 9819 // is tricky. The flavor of compare used depends on whether we are testing 9820 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 9821 // The GE test is the negated LT test. The LE test can be had by commuting 9822 // the operands (yielding a GE test) and then negating; negate again for the 9823 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the 9824 // NE test is negated from that. 9825 9826 // Due to a shortcoming in the ADLC, it mixes up expressions like: 9827 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9828 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9829 // are collapsed internally in the ADLC's dfa-gen code. The match for 9830 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9831 // foo match ends up with the wrong leaf. One fix is to not match both 9832 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 9833 // both forms beat the trinary form of long-compare and both are very useful 9834 // on Intel which has so few registers. 9835 9836 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 9837 match(If cmp xcc); 9838 effect(USE labl); 9839 9840 size(8); 9841 ins_cost(BRANCH_COST); 9842 format %{ "BP$cmp $xcc,$labl" %} 9843 ins_encode %{ 9844 Label* L = $labl$$label; 9845 Assembler::Predict predict_taken = 9846 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9847 9848 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9849 __ delayed()->nop(); 9850 %} 9851 ins_avoid_back_to_back(AVOID_BEFORE); 9852 ins_pipe(br_cc); 9853 %} 9854 9855 // Manifest a CmpL3 result in an integer register. Very painful. 9856 // This is the test to avoid. 9857 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 9858 match(Set dst (CmpL3 src1 src2) ); 9859 effect( KILL ccr ); 9860 ins_cost(6*DEFAULT_COST); 9861 size(24); 9862 format %{ "CMP $src1,$src2\t\t! long\n" 9863 "\tBLT,a,pn done\n" 9864 "\tMOV -1,$dst\t! delay slot\n" 9865 "\tBGT,a,pn done\n" 9866 "\tMOV 1,$dst\t! delay slot\n" 9867 "\tCLR $dst\n" 9868 "done:" %} 9869 ins_encode( cmpl_flag(src1,src2,dst) ); 9870 ins_pipe(cmpL_reg); 9871 %} 9872 9873 // Conditional move 9874 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 9875 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9876 ins_cost(150); 9877 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9878 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9879 ins_pipe(ialu_reg); 9880 %} 9881 9882 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 9883 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9884 ins_cost(140); 9885 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9886 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9887 ins_pipe(ialu_imm); 9888 %} 9889 9890 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 9891 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9892 ins_cost(150); 9893 format %{ "MOV$cmp $xcc,$src,$dst" %} 9894 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9895 ins_pipe(ialu_reg); 9896 %} 9897 9898 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 9899 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9900 ins_cost(140); 9901 format %{ "MOV$cmp $xcc,$src,$dst" %} 9902 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9903 ins_pipe(ialu_imm); 9904 %} 9905 9906 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 9907 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 9908 ins_cost(150); 9909 format %{ "MOV$cmp $xcc,$src,$dst" %} 9910 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9911 ins_pipe(ialu_reg); 9912 %} 9913 9914 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 9915 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9916 ins_cost(150); 9917 format %{ "MOV$cmp $xcc,$src,$dst" %} 9918 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9919 ins_pipe(ialu_reg); 9920 %} 9921 9922 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 9923 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9924 ins_cost(140); 9925 format %{ "MOV$cmp $xcc,$src,$dst" %} 9926 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9927 ins_pipe(ialu_imm); 9928 %} 9929 9930 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 9931 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 9932 ins_cost(150); 9933 opcode(0x101); 9934 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 9935 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9936 ins_pipe(int_conditional_float_move); 9937 %} 9938 9939 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 9940 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 9941 ins_cost(150); 9942 opcode(0x102); 9943 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 9944 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9945 ins_pipe(int_conditional_float_move); 9946 %} 9947 9948 // ============================================================================ 9949 // Safepoint Instruction 9950 instruct safePoint_poll(iRegP poll) %{ 9951 match(SafePoint poll); 9952 effect(USE poll); 9953 9954 size(4); 9955 #ifdef _LP64 9956 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 9957 #else 9958 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} 9959 #endif 9960 ins_encode %{ 9961 __ relocate(relocInfo::poll_type); 9962 __ ld_ptr($poll$$Register, 0, G0); 9963 %} 9964 ins_pipe(loadPollP); 9965 %} 9966 9967 // ============================================================================ 9968 // Call Instructions 9969 // Call Java Static Instruction 9970 instruct CallStaticJavaDirect( method meth ) %{ 9971 match(CallStaticJava); 9972 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9973 effect(USE meth); 9974 9975 size(8); 9976 ins_cost(CALL_COST); 9977 format %{ "CALL,static ; NOP ==> " %} 9978 ins_encode( Java_Static_Call( meth ), call_epilog ); 9979 ins_avoid_back_to_back(AVOID_BEFORE); 9980 ins_pipe(simple_call); 9981 %} 9982 9983 // Call Java Static Instruction (method handle version) 9984 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ 9985 match(CallStaticJava); 9986 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9987 effect(USE meth, KILL l7_mh_SP_save); 9988 9989 size(16); 9990 ins_cost(CALL_COST); 9991 format %{ "CALL,static/MethodHandle" %} 9992 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); 9993 ins_pipe(simple_call); 9994 %} 9995 9996 // Call Java Dynamic Instruction 9997 instruct CallDynamicJavaDirect( method meth ) %{ 9998 match(CallDynamicJava); 9999 effect(USE meth); 10000 10001 ins_cost(CALL_COST); 10002 format %{ "SET (empty),R_G5\n\t" 10003 "CALL,dynamic ; NOP ==> " %} 10004 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 10005 ins_pipe(call); 10006 %} 10007 10008 // Call Runtime Instruction 10009 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 10010 match(CallRuntime); 10011 effect(USE meth, KILL l7); 10012 ins_cost(CALL_COST); 10013 format %{ "CALL,runtime" %} 10014 ins_encode( Java_To_Runtime( meth ), 10015 call_epilog, adjust_long_from_native_call ); 10016 ins_avoid_back_to_back(AVOID_BEFORE); 10017 ins_pipe(simple_call); 10018 %} 10019 10020 // Call runtime without safepoint - same as CallRuntime 10021 instruct CallLeafDirect(method meth, l7RegP l7) %{ 10022 match(CallLeaf); 10023 effect(USE meth, KILL l7); 10024 ins_cost(CALL_COST); 10025 format %{ "CALL,runtime leaf" %} 10026 ins_encode( Java_To_Runtime( meth ), 10027 call_epilog, 10028 adjust_long_from_native_call ); 10029 ins_avoid_back_to_back(AVOID_BEFORE); 10030 ins_pipe(simple_call); 10031 %} 10032 10033 // Call runtime without safepoint - same as CallLeaf 10034 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 10035 match(CallLeafNoFP); 10036 effect(USE meth, KILL l7); 10037 ins_cost(CALL_COST); 10038 format %{ "CALL,runtime leaf nofp" %} 10039 ins_encode( Java_To_Runtime( meth ), 10040 call_epilog, 10041 adjust_long_from_native_call ); 10042 ins_avoid_back_to_back(AVOID_BEFORE); 10043 ins_pipe(simple_call); 10044 %} 10045 10046 // Tail Call; Jump from runtime stub to Java code. 10047 // Also known as an 'interprocedural jump'. 10048 // Target of jump will eventually return to caller. 10049 // TailJump below removes the return address. 10050 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 10051 match(TailCall jump_target method_oop ); 10052 10053 ins_cost(CALL_COST); 10054 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 10055 ins_encode(form_jmpl(jump_target)); 10056 ins_avoid_back_to_back(AVOID_BEFORE); 10057 ins_pipe(tail_call); 10058 %} 10059 10060 10061 // Return Instruction 10062 instruct Ret() %{ 10063 match(Return); 10064 10065 // The epilogue node did the ret already. 10066 size(0); 10067 format %{ "! return" %} 10068 ins_encode(); 10069 ins_pipe(empty); 10070 %} 10071 10072 10073 // Tail Jump; remove the return address; jump to target. 10074 // TailCall above leaves the return address around. 10075 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 10076 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 10077 // "restore" before this instruction (in Epilogue), we need to materialize it 10078 // in %i0. 10079 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 10080 match( TailJump jump_target ex_oop ); 10081 ins_cost(CALL_COST); 10082 format %{ "! discard R_O7\n\t" 10083 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 10084 ins_encode(form_jmpl_set_exception_pc(jump_target)); 10085 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 10086 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 10087 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 10088 ins_avoid_back_to_back(AVOID_BEFORE); 10089 ins_pipe(tail_call); 10090 %} 10091 10092 // Create exception oop: created by stack-crawling runtime code. 10093 // Created exception is now available to this handler, and is setup 10094 // just prior to jumping to this handler. No code emitted. 10095 instruct CreateException( o0RegP ex_oop ) 10096 %{ 10097 match(Set ex_oop (CreateEx)); 10098 ins_cost(0); 10099 10100 size(0); 10101 // use the following format syntax 10102 format %{ "! exception oop is in R_O0; no code emitted" %} 10103 ins_encode(); 10104 ins_pipe(empty); 10105 %} 10106 10107 10108 // Rethrow exception: 10109 // The exception oop will come in the first argument position. 10110 // Then JUMP (not call) to the rethrow stub code. 10111 instruct RethrowException() 10112 %{ 10113 match(Rethrow); 10114 ins_cost(CALL_COST); 10115 10116 // use the following format syntax 10117 format %{ "Jmp rethrow_stub" %} 10118 ins_encode(enc_rethrow); 10119 ins_avoid_back_to_back(AVOID_BEFORE); 10120 ins_pipe(tail_call); 10121 %} 10122 10123 10124 // Die now 10125 instruct ShouldNotReachHere( ) 10126 %{ 10127 match(Halt); 10128 ins_cost(CALL_COST); 10129 10130 size(4); 10131 // Use the following format syntax 10132 format %{ "ILLTRAP ; ShouldNotReachHere" %} 10133 ins_encode( form2_illtrap() ); 10134 ins_pipe(tail_call); 10135 %} 10136 10137 // ============================================================================ 10138 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 10139 // array for an instance of the superklass. Set a hidden internal cache on a 10140 // hit (cache is checked with exposed code in gen_subtype_check()). Return 10141 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 10142 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 10143 match(Set index (PartialSubtypeCheck sub super)); 10144 effect( KILL pcc, KILL o7 ); 10145 ins_cost(DEFAULT_COST*10); 10146 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 10147 ins_encode( enc_PartialSubtypeCheck() ); 10148 ins_avoid_back_to_back(AVOID_BEFORE); 10149 ins_pipe(partial_subtype_check_pipe); 10150 %} 10151 10152 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 10153 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 10154 effect( KILL idx, KILL o7 ); 10155 ins_cost(DEFAULT_COST*10); 10156 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 10157 ins_encode( enc_PartialSubtypeCheck() ); 10158 ins_avoid_back_to_back(AVOID_BEFORE); 10159 ins_pipe(partial_subtype_check_pipe); 10160 %} 10161 10162 10163 // ============================================================================ 10164 // inlined locking and unlocking 10165 10166 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 10167 match(Set pcc (FastLock object box)); 10168 10169 effect(TEMP scratch2, USE_KILL box, KILL scratch); 10170 ins_cost(100); 10171 10172 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 10173 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 10174 ins_pipe(long_memory_op); 10175 %} 10176 10177 10178 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 10179 match(Set pcc (FastUnlock object box)); 10180 effect(TEMP scratch2, USE_KILL box, KILL scratch); 10181 ins_cost(100); 10182 10183 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 10184 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 10185 ins_pipe(long_memory_op); 10186 %} 10187 10188 // The encodings are generic. 10189 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 10190 predicate(!use_block_zeroing(n->in(2)) ); 10191 match(Set dummy (ClearArray cnt base)); 10192 effect(TEMP temp, KILL ccr); 10193 ins_cost(300); 10194 format %{ "MOV $cnt,$temp\n" 10195 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 10196 " BRge loop\t\t! Clearing loop\n" 10197 " STX G0,[$base+$temp]\t! delay slot" %} 10198 10199 ins_encode %{ 10200 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 10201 Register nof_bytes_arg = $cnt$$Register; 10202 Register nof_bytes_tmp = $temp$$Register; 10203 Register base_pointer_arg = $base$$Register; 10204 10205 Label loop; 10206 __ mov(nof_bytes_arg, nof_bytes_tmp); 10207 10208 // Loop and clear, walking backwards through the array. 10209 // nof_bytes_tmp (if >0) is always the number of bytes to zero 10210 __ bind(loop); 10211 __ deccc(nof_bytes_tmp, 8); 10212 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 10213 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 10214 // %%%% this mini-loop must not cross a cache boundary! 10215 %} 10216 ins_pipe(long_memory_op); 10217 %} 10218 10219 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ 10220 predicate(use_block_zeroing(n->in(2))); 10221 match(Set dummy (ClearArray cnt base)); 10222 effect(USE_KILL cnt, USE_KILL base, KILL ccr); 10223 ins_cost(300); 10224 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 10225 10226 ins_encode %{ 10227 10228 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 10229 Register to = $base$$Register; 10230 Register count = $cnt$$Register; 10231 10232 Label Ldone; 10233 __ nop(); // Separate short branches 10234 // Use BIS for zeroing (temp is not used). 10235 __ bis_zeroing(to, count, G0, Ldone); 10236 __ bind(Ldone); 10237 10238 %} 10239 ins_pipe(long_memory_op); 10240 %} 10241 10242 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ 10243 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); 10244 match(Set dummy (ClearArray cnt base)); 10245 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); 10246 ins_cost(300); 10247 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 10248 10249 ins_encode %{ 10250 10251 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 10252 Register to = $base$$Register; 10253 Register count = $cnt$$Register; 10254 Register temp = $tmp$$Register; 10255 10256 Label Ldone; 10257 __ nop(); // Separate short branches 10258 // Use BIS for zeroing 10259 __ bis_zeroing(to, count, temp, Ldone); 10260 __ bind(Ldone); 10261 10262 %} 10263 ins_pipe(long_memory_op); 10264 %} 10265 10266 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 10267 o7RegI tmp, flagsReg ccr) %{ 10268 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10269 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 10270 ins_cost(300); 10271 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 10272 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); 10273 ins_pipe(long_memory_op); 10274 %} 10275 10276 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 10277 o7RegI tmp, flagsReg ccr) %{ 10278 match(Set result (StrEquals (Binary str1 str2) cnt)); 10279 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 10280 ins_cost(300); 10281 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} 10282 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); 10283 ins_pipe(long_memory_op); 10284 %} 10285 10286 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 10287 o7RegI tmp2, flagsReg ccr) %{ 10288 match(Set result (AryEq ary1 ary2)); 10289 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 10290 ins_cost(300); 10291 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 10292 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); 10293 ins_pipe(long_memory_op); 10294 %} 10295 10296 10297 //---------- Zeros Count Instructions ------------------------------------------ 10298 10299 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{ 10300 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10301 match(Set dst (CountLeadingZerosI src)); 10302 effect(TEMP dst, TEMP tmp, KILL cr); 10303 10304 // x |= (x >> 1); 10305 // x |= (x >> 2); 10306 // x |= (x >> 4); 10307 // x |= (x >> 8); 10308 // x |= (x >> 16); 10309 // return (WORDBITS - popc(x)); 10310 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" 10311 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" 10312 "OR $dst,$tmp,$dst\n\t" 10313 "SRL $dst,2,$tmp\n\t" 10314 "OR $dst,$tmp,$dst\n\t" 10315 "SRL $dst,4,$tmp\n\t" 10316 "OR $dst,$tmp,$dst\n\t" 10317 "SRL $dst,8,$tmp\n\t" 10318 "OR $dst,$tmp,$dst\n\t" 10319 "SRL $dst,16,$tmp\n\t" 10320 "OR $dst,$tmp,$dst\n\t" 10321 "POPC $dst,$dst\n\t" 10322 "MOV 32,$tmp\n\t" 10323 "SUB $tmp,$dst,$dst" %} 10324 ins_encode %{ 10325 Register Rdst = $dst$$Register; 10326 Register Rsrc = $src$$Register; 10327 Register Rtmp = $tmp$$Register; 10328 __ srl(Rsrc, 1, Rtmp); 10329 __ srl(Rsrc, 0, Rdst); 10330 __ or3(Rdst, Rtmp, Rdst); 10331 __ srl(Rdst, 2, Rtmp); 10332 __ or3(Rdst, Rtmp, Rdst); 10333 __ srl(Rdst, 4, Rtmp); 10334 __ or3(Rdst, Rtmp, Rdst); 10335 __ srl(Rdst, 8, Rtmp); 10336 __ or3(Rdst, Rtmp, Rdst); 10337 __ srl(Rdst, 16, Rtmp); 10338 __ or3(Rdst, Rtmp, Rdst); 10339 __ popc(Rdst, Rdst); 10340 __ mov(BitsPerInt, Rtmp); 10341 __ sub(Rtmp, Rdst, Rdst); 10342 %} 10343 ins_pipe(ialu_reg); 10344 %} 10345 10346 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ 10347 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10348 match(Set dst (CountLeadingZerosL src)); 10349 effect(TEMP dst, TEMP tmp, KILL cr); 10350 10351 // x |= (x >> 1); 10352 // x |= (x >> 2); 10353 // x |= (x >> 4); 10354 // x |= (x >> 8); 10355 // x |= (x >> 16); 10356 // x |= (x >> 32); 10357 // return (WORDBITS - popc(x)); 10358 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" 10359 "OR $src,$tmp,$dst\n\t" 10360 "SRLX $dst,2,$tmp\n\t" 10361 "OR $dst,$tmp,$dst\n\t" 10362 "SRLX $dst,4,$tmp\n\t" 10363 "OR $dst,$tmp,$dst\n\t" 10364 "SRLX $dst,8,$tmp\n\t" 10365 "OR $dst,$tmp,$dst\n\t" 10366 "SRLX $dst,16,$tmp\n\t" 10367 "OR $dst,$tmp,$dst\n\t" 10368 "SRLX $dst,32,$tmp\n\t" 10369 "OR $dst,$tmp,$dst\n\t" 10370 "POPC $dst,$dst\n\t" 10371 "MOV 64,$tmp\n\t" 10372 "SUB $tmp,$dst,$dst" %} 10373 ins_encode %{ 10374 Register Rdst = $dst$$Register; 10375 Register Rsrc = $src$$Register; 10376 Register Rtmp = $tmp$$Register; 10377 __ srlx(Rsrc, 1, Rtmp); 10378 __ or3( Rsrc, Rtmp, Rdst); 10379 __ srlx(Rdst, 2, Rtmp); 10380 __ or3( Rdst, Rtmp, Rdst); 10381 __ srlx(Rdst, 4, Rtmp); 10382 __ or3( Rdst, Rtmp, Rdst); 10383 __ srlx(Rdst, 8, Rtmp); 10384 __ or3( Rdst, Rtmp, Rdst); 10385 __ srlx(Rdst, 16, Rtmp); 10386 __ or3( Rdst, Rtmp, Rdst); 10387 __ srlx(Rdst, 32, Rtmp); 10388 __ or3( Rdst, Rtmp, Rdst); 10389 __ popc(Rdst, Rdst); 10390 __ mov(BitsPerLong, Rtmp); 10391 __ sub(Rtmp, Rdst, Rdst); 10392 %} 10393 ins_pipe(ialu_reg); 10394 %} 10395 10396 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{ 10397 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10398 match(Set dst (CountTrailingZerosI src)); 10399 effect(TEMP dst, KILL cr); 10400 10401 // return popc(~x & (x - 1)); 10402 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" 10403 "ANDN $dst,$src,$dst\n\t" 10404 "SRL $dst,R_G0,$dst\n\t" 10405 "POPC $dst,$dst" %} 10406 ins_encode %{ 10407 Register Rdst = $dst$$Register; 10408 Register Rsrc = $src$$Register; 10409 __ sub(Rsrc, 1, Rdst); 10410 __ andn(Rdst, Rsrc, Rdst); 10411 __ srl(Rdst, G0, Rdst); 10412 __ popc(Rdst, Rdst); 10413 %} 10414 ins_pipe(ialu_reg); 10415 %} 10416 10417 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ 10418 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10419 match(Set dst (CountTrailingZerosL src)); 10420 effect(TEMP dst, KILL cr); 10421 10422 // return popc(~x & (x - 1)); 10423 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" 10424 "ANDN $dst,$src,$dst\n\t" 10425 "POPC $dst,$dst" %} 10426 ins_encode %{ 10427 Register Rdst = $dst$$Register; 10428 Register Rsrc = $src$$Register; 10429 __ sub(Rsrc, 1, Rdst); 10430 __ andn(Rdst, Rsrc, Rdst); 10431 __ popc(Rdst, Rdst); 10432 %} 10433 ins_pipe(ialu_reg); 10434 %} 10435 10436 10437 //---------- Population Count Instructions ------------------------------------- 10438 10439 instruct popCountI(iRegIsafe dst, iRegI src) %{ 10440 predicate(UsePopCountInstruction); 10441 match(Set dst (PopCountI src)); 10442 10443 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t" 10444 "POPC $dst, $dst" %} 10445 ins_encode %{ 10446 __ srl($src$$Register, G0, $dst$$Register); 10447 __ popc($dst$$Register, $dst$$Register); 10448 %} 10449 ins_pipe(ialu_reg); 10450 %} 10451 10452 // Note: Long.bitCount(long) returns an int. 10453 instruct popCountL(iRegIsafe dst, iRegL src) %{ 10454 predicate(UsePopCountInstruction); 10455 match(Set dst (PopCountL src)); 10456 10457 format %{ "POPC $src, $dst" %} 10458 ins_encode %{ 10459 __ popc($src$$Register, $dst$$Register); 10460 %} 10461 ins_pipe(ialu_reg); 10462 %} 10463 10464 10465 // ============================================================================ 10466 //------------Bytes reverse-------------------------------------------------- 10467 10468 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 10469 match(Set dst (ReverseBytesI src)); 10470 10471 // Op cost is artificially doubled to make sure that load or store 10472 // instructions are preferred over this one which requires a spill 10473 // onto a stack slot. 10474 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10475 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10476 10477 ins_encode %{ 10478 __ set($src$$disp + STACK_BIAS, O7); 10479 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10480 %} 10481 ins_pipe( iload_mem ); 10482 %} 10483 10484 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 10485 match(Set dst (ReverseBytesL src)); 10486 10487 // Op cost is artificially doubled to make sure that load or store 10488 // instructions are preferred over this one which requires a spill 10489 // onto a stack slot. 10490 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10491 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10492 10493 ins_encode %{ 10494 __ set($src$$disp + STACK_BIAS, O7); 10495 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10496 %} 10497 ins_pipe( iload_mem ); 10498 %} 10499 10500 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ 10501 match(Set dst (ReverseBytesUS src)); 10502 10503 // Op cost is artificially doubled to make sure that load or store 10504 // instructions are preferred over this one which requires a spill 10505 // onto a stack slot. 10506 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10507 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} 10508 10509 ins_encode %{ 10510 // the value was spilled as an int so bias the load 10511 __ set($src$$disp + STACK_BIAS + 2, O7); 10512 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10513 %} 10514 ins_pipe( iload_mem ); 10515 %} 10516 10517 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ 10518 match(Set dst (ReverseBytesS src)); 10519 10520 // Op cost is artificially doubled to make sure that load or store 10521 // instructions are preferred over this one which requires a spill 10522 // onto a stack slot. 10523 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10524 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} 10525 10526 ins_encode %{ 10527 // the value was spilled as an int so bias the load 10528 __ set($src$$disp + STACK_BIAS + 2, O7); 10529 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10530 %} 10531 ins_pipe( iload_mem ); 10532 %} 10533 10534 // Load Integer reversed byte order 10535 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ 10536 match(Set dst (ReverseBytesI (LoadI src))); 10537 10538 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10539 size(4); 10540 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10541 10542 ins_encode %{ 10543 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10544 %} 10545 ins_pipe(iload_mem); 10546 %} 10547 10548 // Load Long - aligned and reversed 10549 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ 10550 match(Set dst (ReverseBytesL (LoadL src))); 10551 10552 ins_cost(MEMORY_REF_COST); 10553 size(4); 10554 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10555 10556 ins_encode %{ 10557 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10558 %} 10559 ins_pipe(iload_mem); 10560 %} 10561 10562 // Load unsigned short / char reversed byte order 10563 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ 10564 match(Set dst (ReverseBytesUS (LoadUS src))); 10565 10566 ins_cost(MEMORY_REF_COST); 10567 size(4); 10568 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} 10569 10570 ins_encode %{ 10571 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10572 %} 10573 ins_pipe(iload_mem); 10574 %} 10575 10576 // Load short reversed byte order 10577 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ 10578 match(Set dst (ReverseBytesS (LoadS src))); 10579 10580 ins_cost(MEMORY_REF_COST); 10581 size(4); 10582 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} 10583 10584 ins_encode %{ 10585 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10586 %} 10587 ins_pipe(iload_mem); 10588 %} 10589 10590 // Store Integer reversed byte order 10591 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ 10592 match(Set dst (StoreI dst (ReverseBytesI src))); 10593 10594 ins_cost(MEMORY_REF_COST); 10595 size(4); 10596 format %{ "STWA $src, $dst\t!asi=primary_little" %} 10597 10598 ins_encode %{ 10599 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10600 %} 10601 ins_pipe(istore_mem_reg); 10602 %} 10603 10604 // Store Long reversed byte order 10605 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ 10606 match(Set dst (StoreL dst (ReverseBytesL src))); 10607 10608 ins_cost(MEMORY_REF_COST); 10609 size(4); 10610 format %{ "STXA $src, $dst\t!asi=primary_little" %} 10611 10612 ins_encode %{ 10613 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10614 %} 10615 ins_pipe(istore_mem_reg); 10616 %} 10617 10618 // Store unsighed short/char reversed byte order 10619 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ 10620 match(Set dst (StoreC dst (ReverseBytesUS src))); 10621 10622 ins_cost(MEMORY_REF_COST); 10623 size(4); 10624 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10625 10626 ins_encode %{ 10627 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10628 %} 10629 ins_pipe(istore_mem_reg); 10630 %} 10631 10632 // Store short reversed byte order 10633 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ 10634 match(Set dst (StoreC dst (ReverseBytesS src))); 10635 10636 ins_cost(MEMORY_REF_COST); 10637 size(4); 10638 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10639 10640 ins_encode %{ 10641 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10642 %} 10643 ins_pipe(istore_mem_reg); 10644 %} 10645 10646 // ====================VECTOR INSTRUCTIONS===================================== 10647 10648 // Load Aligned Packed values into a Double Register 10649 instruct loadV8(regD dst, memory mem) %{ 10650 predicate(n->as_LoadVector()->memory_size() == 8); 10651 match(Set dst (LoadVector mem)); 10652 ins_cost(MEMORY_REF_COST); 10653 size(4); 10654 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} 10655 ins_encode %{ 10656 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); 10657 %} 10658 ins_pipe(floadD_mem); 10659 %} 10660 10661 // Store Vector in Double register to memory 10662 instruct storeV8(memory mem, regD src) %{ 10663 predicate(n->as_StoreVector()->memory_size() == 8); 10664 match(Set mem (StoreVector mem src)); 10665 ins_cost(MEMORY_REF_COST); 10666 size(4); 10667 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} 10668 ins_encode %{ 10669 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); 10670 %} 10671 ins_pipe(fstoreD_mem_reg); 10672 %} 10673 10674 // Store Zero into vector in memory 10675 instruct storeV8B_zero(memory mem, immI0 zero) %{ 10676 predicate(n->as_StoreVector()->memory_size() == 8); 10677 match(Set mem (StoreVector mem (ReplicateB zero))); 10678 ins_cost(MEMORY_REF_COST); 10679 size(4); 10680 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} 10681 ins_encode %{ 10682 __ stx(G0, $mem$$Address); 10683 %} 10684 ins_pipe(fstoreD_mem_zero); 10685 %} 10686 10687 instruct storeV4S_zero(memory mem, immI0 zero) %{ 10688 predicate(n->as_StoreVector()->memory_size() == 8); 10689 match(Set mem (StoreVector mem (ReplicateS zero))); 10690 ins_cost(MEMORY_REF_COST); 10691 size(4); 10692 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} 10693 ins_encode %{ 10694 __ stx(G0, $mem$$Address); 10695 %} 10696 ins_pipe(fstoreD_mem_zero); 10697 %} 10698 10699 instruct storeV2I_zero(memory mem, immI0 zero) %{ 10700 predicate(n->as_StoreVector()->memory_size() == 8); 10701 match(Set mem (StoreVector mem (ReplicateI zero))); 10702 ins_cost(MEMORY_REF_COST); 10703 size(4); 10704 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} 10705 ins_encode %{ 10706 __ stx(G0, $mem$$Address); 10707 %} 10708 ins_pipe(fstoreD_mem_zero); 10709 %} 10710 10711 instruct storeV2F_zero(memory mem, immF0 zero) %{ 10712 predicate(n->as_StoreVector()->memory_size() == 8); 10713 match(Set mem (StoreVector mem (ReplicateF zero))); 10714 ins_cost(MEMORY_REF_COST); 10715 size(4); 10716 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} 10717 ins_encode %{ 10718 __ stx(G0, $mem$$Address); 10719 %} 10720 ins_pipe(fstoreD_mem_zero); 10721 %} 10722 10723 // Replicate scalar to packed byte values into Double register 10724 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10725 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); 10726 match(Set dst (ReplicateB src)); 10727 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10728 format %{ "SLLX $src,56,$tmp\n\t" 10729 "SRLX $tmp, 8,$tmp2\n\t" 10730 "OR $tmp,$tmp2,$tmp\n\t" 10731 "SRLX $tmp,16,$tmp2\n\t" 10732 "OR $tmp,$tmp2,$tmp\n\t" 10733 "SRLX $tmp,32,$tmp2\n\t" 10734 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10735 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10736 ins_encode %{ 10737 Register Rsrc = $src$$Register; 10738 Register Rtmp = $tmp$$Register; 10739 Register Rtmp2 = $tmp2$$Register; 10740 __ sllx(Rsrc, 56, Rtmp); 10741 __ srlx(Rtmp, 8, Rtmp2); 10742 __ or3 (Rtmp, Rtmp2, Rtmp); 10743 __ srlx(Rtmp, 16, Rtmp2); 10744 __ or3 (Rtmp, Rtmp2, Rtmp); 10745 __ srlx(Rtmp, 32, Rtmp2); 10746 __ or3 (Rtmp, Rtmp2, Rtmp); 10747 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10748 %} 10749 ins_pipe(ialu_reg); 10750 %} 10751 10752 // Replicate scalar to packed byte values into Double stack 10753 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10754 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); 10755 match(Set dst (ReplicateB src)); 10756 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10757 format %{ "SLLX $src,56,$tmp\n\t" 10758 "SRLX $tmp, 8,$tmp2\n\t" 10759 "OR $tmp,$tmp2,$tmp\n\t" 10760 "SRLX $tmp,16,$tmp2\n\t" 10761 "OR $tmp,$tmp2,$tmp\n\t" 10762 "SRLX $tmp,32,$tmp2\n\t" 10763 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10764 "STX $tmp,$dst\t! regL to stkD" %} 10765 ins_encode %{ 10766 Register Rsrc = $src$$Register; 10767 Register Rtmp = $tmp$$Register; 10768 Register Rtmp2 = $tmp2$$Register; 10769 __ sllx(Rsrc, 56, Rtmp); 10770 __ srlx(Rtmp, 8, Rtmp2); 10771 __ or3 (Rtmp, Rtmp2, Rtmp); 10772 __ srlx(Rtmp, 16, Rtmp2); 10773 __ or3 (Rtmp, Rtmp2, Rtmp); 10774 __ srlx(Rtmp, 32, Rtmp2); 10775 __ or3 (Rtmp, Rtmp2, Rtmp); 10776 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10777 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10778 %} 10779 ins_pipe(ialu_reg); 10780 %} 10781 10782 // Replicate scalar constant to packed byte values in Double register 10783 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ 10784 predicate(n->as_Vector()->length() == 8); 10785 match(Set dst (ReplicateB con)); 10786 effect(KILL tmp); 10787 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} 10788 ins_encode %{ 10789 // XXX This is a quick fix for 6833573. 10790 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); 10791 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); 10792 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10793 %} 10794 ins_pipe(loadConFD); 10795 %} 10796 10797 // Replicate scalar to packed char/short values into Double register 10798 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10799 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); 10800 match(Set dst (ReplicateS src)); 10801 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10802 format %{ "SLLX $src,48,$tmp\n\t" 10803 "SRLX $tmp,16,$tmp2\n\t" 10804 "OR $tmp,$tmp2,$tmp\n\t" 10805 "SRLX $tmp,32,$tmp2\n\t" 10806 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10807 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10808 ins_encode %{ 10809 Register Rsrc = $src$$Register; 10810 Register Rtmp = $tmp$$Register; 10811 Register Rtmp2 = $tmp2$$Register; 10812 __ sllx(Rsrc, 48, Rtmp); 10813 __ srlx(Rtmp, 16, Rtmp2); 10814 __ or3 (Rtmp, Rtmp2, Rtmp); 10815 __ srlx(Rtmp, 32, Rtmp2); 10816 __ or3 (Rtmp, Rtmp2, Rtmp); 10817 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10818 %} 10819 ins_pipe(ialu_reg); 10820 %} 10821 10822 // Replicate scalar to packed char/short values into Double stack 10823 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10824 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); 10825 match(Set dst (ReplicateS src)); 10826 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10827 format %{ "SLLX $src,48,$tmp\n\t" 10828 "SRLX $tmp,16,$tmp2\n\t" 10829 "OR $tmp,$tmp2,$tmp\n\t" 10830 "SRLX $tmp,32,$tmp2\n\t" 10831 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10832 "STX $tmp,$dst\t! regL to stkD" %} 10833 ins_encode %{ 10834 Register Rsrc = $src$$Register; 10835 Register Rtmp = $tmp$$Register; 10836 Register Rtmp2 = $tmp2$$Register; 10837 __ sllx(Rsrc, 48, Rtmp); 10838 __ srlx(Rtmp, 16, Rtmp2); 10839 __ or3 (Rtmp, Rtmp2, Rtmp); 10840 __ srlx(Rtmp, 32, Rtmp2); 10841 __ or3 (Rtmp, Rtmp2, Rtmp); 10842 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10843 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10844 %} 10845 ins_pipe(ialu_reg); 10846 %} 10847 10848 // Replicate scalar constant to packed char/short values in Double register 10849 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ 10850 predicate(n->as_Vector()->length() == 4); 10851 match(Set dst (ReplicateS con)); 10852 effect(KILL tmp); 10853 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} 10854 ins_encode %{ 10855 // XXX This is a quick fix for 6833573. 10856 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); 10857 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); 10858 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10859 %} 10860 ins_pipe(loadConFD); 10861 %} 10862 10863 // Replicate scalar to packed int values into Double register 10864 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10865 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); 10866 match(Set dst (ReplicateI src)); 10867 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10868 format %{ "SLLX $src,32,$tmp\n\t" 10869 "SRLX $tmp,32,$tmp2\n\t" 10870 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10871 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10872 ins_encode %{ 10873 Register Rsrc = $src$$Register; 10874 Register Rtmp = $tmp$$Register; 10875 Register Rtmp2 = $tmp2$$Register; 10876 __ sllx(Rsrc, 32, Rtmp); 10877 __ srlx(Rtmp, 32, Rtmp2); 10878 __ or3 (Rtmp, Rtmp2, Rtmp); 10879 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10880 %} 10881 ins_pipe(ialu_reg); 10882 %} 10883 10884 // Replicate scalar to packed int values into Double stack 10885 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10886 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); 10887 match(Set dst (ReplicateI src)); 10888 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10889 format %{ "SLLX $src,32,$tmp\n\t" 10890 "SRLX $tmp,32,$tmp2\n\t" 10891 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10892 "STX $tmp,$dst\t! regL to stkD" %} 10893 ins_encode %{ 10894 Register Rsrc = $src$$Register; 10895 Register Rtmp = $tmp$$Register; 10896 Register Rtmp2 = $tmp2$$Register; 10897 __ sllx(Rsrc, 32, Rtmp); 10898 __ srlx(Rtmp, 32, Rtmp2); 10899 __ or3 (Rtmp, Rtmp2, Rtmp); 10900 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10901 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10902 %} 10903 ins_pipe(ialu_reg); 10904 %} 10905 10906 // Replicate scalar zero constant to packed int values in Double register 10907 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ 10908 predicate(n->as_Vector()->length() == 2); 10909 match(Set dst (ReplicateI con)); 10910 effect(KILL tmp); 10911 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} 10912 ins_encode %{ 10913 // XXX This is a quick fix for 6833573. 10914 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); 10915 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); 10916 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10917 %} 10918 ins_pipe(loadConFD); 10919 %} 10920 10921 // Replicate scalar to packed float values into Double stack 10922 instruct Repl2F_stk(stackSlotD dst, regF src) %{ 10923 predicate(n->as_Vector()->length() == 2); 10924 match(Set dst (ReplicateF src)); 10925 ins_cost(MEMORY_REF_COST*2); 10926 format %{ "STF $src,$dst.hi\t! packed2F\n\t" 10927 "STF $src,$dst.lo" %} 10928 opcode(Assembler::stf_op3); 10929 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); 10930 ins_pipe(fstoreF_stk_reg); 10931 %} 10932 10933 // Replicate scalar zero constant to packed float values in Double register 10934 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ 10935 predicate(n->as_Vector()->length() == 2); 10936 match(Set dst (ReplicateF con)); 10937 effect(KILL tmp); 10938 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} 10939 ins_encode %{ 10940 // XXX This is a quick fix for 6833573. 10941 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); 10942 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); 10943 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10944 %} 10945 ins_pipe(loadConFD); 10946 %} 10947 10948 //----------PEEPHOLE RULES----------------------------------------------------- 10949 // These must follow all instruction definitions as they use the names 10950 // defined in the instructions definitions. 10951 // 10952 // peepmatch ( root_instr_name [preceding_instruction]* ); 10953 // 10954 // peepconstraint %{ 10955 // (instruction_number.operand_name relational_op instruction_number.operand_name 10956 // [, ...] ); 10957 // // instruction numbers are zero-based using left to right order in peepmatch 10958 // 10959 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 10960 // // provide an instruction_number.operand_name for each operand that appears 10961 // // in the replacement instruction's match rule 10962 // 10963 // ---------VM FLAGS--------------------------------------------------------- 10964 // 10965 // All peephole optimizations can be turned off using -XX:-OptoPeephole 10966 // 10967 // Each peephole rule is given an identifying number starting with zero and 10968 // increasing by one in the order seen by the parser. An individual peephole 10969 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 10970 // on the command-line. 10971 // 10972 // ---------CURRENT LIMITATIONS---------------------------------------------- 10973 // 10974 // Only match adjacent instructions in same basic block 10975 // Only equality constraints 10976 // Only constraints between operands, not (0.dest_reg == EAX_enc) 10977 // Only one replacement instruction 10978 // 10979 // ---------EXAMPLE---------------------------------------------------------- 10980 // 10981 // // pertinent parts of existing instructions in architecture description 10982 // instruct movI(eRegI dst, eRegI src) %{ 10983 // match(Set dst (CopyI src)); 10984 // %} 10985 // 10986 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 10987 // match(Set dst (AddI dst src)); 10988 // effect(KILL cr); 10989 // %} 10990 // 10991 // // Change (inc mov) to lea 10992 // peephole %{ 10993 // // increment preceeded by register-register move 10994 // peepmatch ( incI_eReg movI ); 10995 // // require that the destination register of the increment 10996 // // match the destination register of the move 10997 // peepconstraint ( 0.dst == 1.dst ); 10998 // // construct a replacement instruction that sets 10999 // // the destination to ( move's source register + one ) 11000 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 11001 // %} 11002 // 11003 11004 // // Change load of spilled value to only a spill 11005 // instruct storeI(memory mem, eRegI src) %{ 11006 // match(Set mem (StoreI mem src)); 11007 // %} 11008 // 11009 // instruct loadI(eRegI dst, memory mem) %{ 11010 // match(Set dst (LoadI mem)); 11011 // %} 11012 // 11013 // peephole %{ 11014 // peepmatch ( loadI storeI ); 11015 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 11016 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 11017 // %} 11018 11019 //----------SMARTSPILL RULES--------------------------------------------------- 11020 // These must follow all instruction definitions as they use the names 11021 // defined in the instructions definitions. 11022 // 11023 // SPARC will probably not have any of these rules due to RISC instruction set. 11024 11025 //----------PIPELINE----------------------------------------------------------- 11026 // Rules which define the behavior of the target architectures pipeline.