641 if (UseSSE > 2) {
642 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
643 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
644 }
645 } else {
646 // The AES intrinsic stubs require AES instruction support (of course)
647 // but also require sse3 mode or higher for instructions it use.
648 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
649 warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
650 }
651 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
652 }
653
654 // --AES-CTR begins--
655 if (!UseAESIntrinsics) {
656 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
657 warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
658 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
659 }
660 } else {
661 if(supports_sse4_1() && UseSSE >= 4) {
662 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
663 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
664 }
665 } else {
666 // The AES-CTR intrinsic stubs require AES instruction support (of course)
667 // but also require sse4.1 mode or higher for instructions it use.
668 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
669 warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
670 }
671 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
672 }
673 }
674 // --AES-CTR ends--
675 }
676 } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
677 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
678 warning("AES instructions are not available on this CPU");
679 FLAG_SET_DEFAULT(UseAES, false);
680 }
681 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
953 if( supports_sse4a() ) {
954 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
955 } else {
956 UseXmmRegToRegMoveAll = false;
957 }
958 }
959 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
960 if( supports_sse4a() ) {
961 UseXmmI2F = true;
962 } else {
963 UseXmmI2F = false;
964 }
965 }
966 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
967 if( supports_sse4a() ) {
968 UseXmmI2D = true;
969 } else {
970 UseXmmI2D = false;
971 }
972 }
973 if (supports_sse4_2() && UseSSE >= 4) {
974 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
975 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
976 }
977 } else {
978 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
979 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
980 }
981 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
982 }
983
984 // some defaults for AMD family 15h
985 if ( cpu_family() == 0x15 ) {
986 // On family 15h processors default is no sw prefetch
987 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
988 AllocatePrefetchStyle = 0;
989 }
990 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
991 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
992 AllocatePrefetchInstr = 3;
993 }
1033 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1034 // For new Intel cpus do the next optimization:
1035 // don't align the beginning of a loop if there are enough instructions
1036 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1037 // in current fetch line (OptoLoopAlignment) or the padding
1038 // is big (> MaxLoopPad).
1039 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1040 // generated NOP instructions. 11 is the largest size of one
1041 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1042 MaxLoopPad = 11;
1043 }
1044 #endif // COMPILER2
1045 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1046 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1047 }
1048 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
1049 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1050 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1051 }
1052 }
1053 if (supports_sse4_2() && UseSSE >= 4) {
1054 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1055 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1056 }
1057 } else {
1058 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1059 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1060 }
1061 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1062 }
1063 }
1064 if ((cpu_family() == 0x06) &&
1065 ((extended_cpu_model() == 0x36) || // Centerton
1066 (extended_cpu_model() == 0x37) || // Silvermont
1067 (extended_cpu_model() == 0x4D))) {
1068 #ifdef COMPILER2
1069 if (FLAG_IS_DEFAULT(OptoScheduling)) {
1070 OptoScheduling = true;
1071 }
1072 #endif
1073 if (supports_sse4_2()) { // Silvermont
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641 if (UseSSE > 2) {
642 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
643 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
644 }
645 } else {
646 // The AES intrinsic stubs require AES instruction support (of course)
647 // but also require sse3 mode or higher for instructions it use.
648 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
649 warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
650 }
651 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
652 }
653
654 // --AES-CTR begins--
655 if (!UseAESIntrinsics) {
656 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
657 warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
658 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
659 }
660 } else {
661 if(supports_sse4_1()) {
662 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
663 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
664 }
665 } else {
666 // The AES-CTR intrinsic stubs require AES instruction support (of course)
667 // but also require sse4.1 mode or higher for instructions it use.
668 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
669 warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
670 }
671 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
672 }
673 }
674 // --AES-CTR ends--
675 }
676 } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
677 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
678 warning("AES instructions are not available on this CPU");
679 FLAG_SET_DEFAULT(UseAES, false);
680 }
681 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
953 if( supports_sse4a() ) {
954 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
955 } else {
956 UseXmmRegToRegMoveAll = false;
957 }
958 }
959 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
960 if( supports_sse4a() ) {
961 UseXmmI2F = true;
962 } else {
963 UseXmmI2F = false;
964 }
965 }
966 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
967 if( supports_sse4a() ) {
968 UseXmmI2D = true;
969 } else {
970 UseXmmI2D = false;
971 }
972 }
973 if (supports_sse4_2()) {
974 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
975 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
976 }
977 } else {
978 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
979 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
980 }
981 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
982 }
983
984 // some defaults for AMD family 15h
985 if ( cpu_family() == 0x15 ) {
986 // On family 15h processors default is no sw prefetch
987 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
988 AllocatePrefetchStyle = 0;
989 }
990 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
991 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
992 AllocatePrefetchInstr = 3;
993 }
1033 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1034 // For new Intel cpus do the next optimization:
1035 // don't align the beginning of a loop if there are enough instructions
1036 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1037 // in current fetch line (OptoLoopAlignment) or the padding
1038 // is big (> MaxLoopPad).
1039 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1040 // generated NOP instructions. 11 is the largest size of one
1041 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1042 MaxLoopPad = 11;
1043 }
1044 #endif // COMPILER2
1045 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1046 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1047 }
1048 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
1049 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1050 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1051 }
1052 }
1053 if (supports_sse4_2()) {
1054 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1055 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1056 }
1057 } else {
1058 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1059 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1060 }
1061 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1062 }
1063 }
1064 if ((cpu_family() == 0x06) &&
1065 ((extended_cpu_model() == 0x36) || // Centerton
1066 (extended_cpu_model() == 0x37) || // Silvermont
1067 (extended_cpu_model() == 0x4D))) {
1068 #ifdef COMPILER2
1069 if (FLAG_IS_DEFAULT(OptoScheduling)) {
1070 OptoScheduling = true;
1071 }
1072 #endif
1073 if (supports_sse4_2()) { // Silvermont
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