11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef SHARE_VM_C1_C1_LIR_HPP
26 #define SHARE_VM_C1_C1_LIR_HPP
27
28 #include "c1/c1_Defs.hpp"
29 #include "c1/c1_ValueType.hpp"
30 #include "oops/method.hpp"
31
32 class BlockBegin;
33 class BlockList;
34 class LIR_Assembler;
35 class CodeEmitInfo;
36 class CodeStub;
37 class CodeStubList;
38 class ArrayCopyStub;
39 class LIR_Op;
40 class ciType;
41 class ValueType;
42 class LIR_OpVisitState;
43 class FpuStackSim;
44
45 //---------------------------------------------------------------------
46 // LIR Operands
47 // LIR_OprDesc
48 // LIR_OprPtr
49 // LIR_Const
50 // LIR_Address
421 int vreg_number() const { assert(is_virtual(), "type check"); return (RegNr)data(); }
422
423 LIR_OprPtr* pointer() const { assert(is_pointer(), "type check"); return (LIR_OprPtr*)this; }
424 LIR_Const* as_constant_ptr() const { return pointer()->as_constant(); }
425 LIR_Address* as_address_ptr() const { return pointer()->as_address(); }
426
427 Register as_register() const;
428 Register as_register_lo() const;
429 Register as_register_hi() const;
430
431 Register as_pointer_register() {
432 #ifdef _LP64
433 if (is_double_cpu()) {
434 assert(as_register_lo() == as_register_hi(), "should be a single register");
435 return as_register_lo();
436 }
437 #endif
438 return as_register();
439 }
440
441 #ifdef X86
442 XMMRegister as_xmm_float_reg() const;
443 XMMRegister as_xmm_double_reg() const;
444 // for compatibility with RInfo
445 int fpu () const { return lo_reg_half(); }
446 #endif
447 #if defined(SPARC) || defined(ARM) || defined(PPC) || defined(AARCH64)
448 FloatRegister as_float_reg () const;
449 FloatRegister as_double_reg () const;
450 #endif
451
452 jint as_jint() const { return as_constant_ptr()->as_jint(); }
453 jlong as_jlong() const { return as_constant_ptr()->as_jlong(); }
454 jfloat as_jfloat() const { return as_constant_ptr()->as_jfloat(); }
455 jdouble as_jdouble() const { return as_constant_ptr()->as_jdouble(); }
456 jobject as_jobject() const { return as_constant_ptr()->as_jobject(); }
457
458 void print() const PRODUCT_RETURN;
459 void print(outputStream* out) const PRODUCT_RETURN;
460 };
461
462
463 inline LIR_OprDesc::OprType as_OprType(BasicType type) {
464 switch (type) {
465 case T_INT: return LIR_OprDesc::int_type;
466 case T_LONG: return LIR_OprDesc::long_type;
467 case T_FLOAT: return LIR_OprDesc::float_type;
468 case T_DOUBLE: return LIR_OprDesc::double_type;
469 case T_OBJECT:
517 _base(base)
518 , _index(index)
519 , _scale(times_1)
520 , _type(type)
521 , _disp(0) { verify(); }
522
523 LIR_Address(LIR_Opr base, intx disp, BasicType type):
524 _base(base)
525 , _index(LIR_OprDesc::illegalOpr())
526 , _scale(times_1)
527 , _type(type)
528 , _disp(disp) { verify(); }
529
530 LIR_Address(LIR_Opr base, BasicType type):
531 _base(base)
532 , _index(LIR_OprDesc::illegalOpr())
533 , _scale(times_1)
534 , _type(type)
535 , _disp(0) { verify(); }
536
537 #if defined(X86) || defined(ARM) || defined(AARCH64)
538 LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type):
539 _base(base)
540 , _index(index)
541 , _scale(scale)
542 , _type(type)
543 , _disp(disp) { verify(); }
544 #endif // X86 || ARM
545
546 LIR_Opr base() const { return _base; }
547 LIR_Opr index() const { return _index; }
548 Scale scale() const { return _scale; }
549 intx disp() const { return _disp; }
550
551 bool equals(LIR_Address* other) const { return base() == other->base() && index() == other->index() && disp() == other->disp() && scale() == other->scale(); }
552
553 virtual LIR_Address* as_address() { return this; }
554 virtual BasicType type() const { return _type; }
555 virtual void print_value_on(outputStream* out) const PRODUCT_RETURN;
556
557 void verify0() const PRODUCT_RETURN;
558 #if defined(LIR_ADDRESS_PD_VERIFY) && !defined(PRODUCT)
559 void pd_verify() const;
560 void verify() const { pd_verify(); }
561 #else
562 void verify() const { verify0(); }
563 #endif
564
565 static Scale scale(BasicType type);
566 };
567
568
569 // operand factory
570 class LIR_OprFact: public AllStatic {
571 public:
572
573 static LIR_Opr illegalOpr;
574
575 static LIR_Opr single_cpu(int reg) {
576 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
577 LIR_OprDesc::int_type |
578 LIR_OprDesc::cpu_register |
579 LIR_OprDesc::single_size);
580 }
581 static LIR_Opr single_cpu_oop(int reg) {
582 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
583 LIR_OprDesc::object_type |
588 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
589 LIR_OprDesc::address_type |
590 LIR_OprDesc::cpu_register |
591 LIR_OprDesc::single_size);
592 }
593 static LIR_Opr single_cpu_metadata(int reg) {
594 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
595 LIR_OprDesc::metadata_type |
596 LIR_OprDesc::cpu_register |
597 LIR_OprDesc::single_size);
598 }
599 static LIR_Opr double_cpu(int reg1, int reg2) {
600 LP64_ONLY(assert(reg1 == reg2, "must be identical"));
601 return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
602 (reg2 << LIR_OprDesc::reg2_shift) |
603 LIR_OprDesc::long_type |
604 LIR_OprDesc::cpu_register |
605 LIR_OprDesc::double_size);
606 }
607
608 static LIR_Opr single_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
609 LIR_OprDesc::float_type |
610 LIR_OprDesc::fpu_register |
611 LIR_OprDesc::single_size); }
612 #if defined(ARM32)
613 static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); }
614 static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) | LIR_OprDesc::float_type | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); }
615 static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::cpu_register | LIR_OprDesc::double_size); }
616 #endif
617 #ifdef SPARC
618 static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
619 (reg2 << LIR_OprDesc::reg2_shift) |
620 LIR_OprDesc::double_type |
621 LIR_OprDesc::fpu_register |
622 LIR_OprDesc::double_size); }
623 #endif
624 #if defined(X86) || defined(AARCH64)
625 static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
626 (reg << LIR_OprDesc::reg2_shift) |
627 LIR_OprDesc::double_type |
628 LIR_OprDesc::fpu_register |
629 LIR_OprDesc::double_size); }
630
631 static LIR_Opr single_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
632 LIR_OprDesc::float_type |
633 LIR_OprDesc::fpu_register |
634 LIR_OprDesc::single_size |
635 LIR_OprDesc::is_xmm_mask); }
636 static LIR_Opr double_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
637 (reg << LIR_OprDesc::reg2_shift) |
638 LIR_OprDesc::double_type |
639 LIR_OprDesc::fpu_register |
640 LIR_OprDesc::double_size |
641 LIR_OprDesc::is_xmm_mask); }
642 #endif // X86
643 #if defined(PPC)
644 static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
645 (reg << LIR_OprDesc::reg2_shift) |
646 LIR_OprDesc::double_type |
647 LIR_OprDesc::fpu_register |
648 LIR_OprDesc::double_size); }
649 #endif
650 #ifdef PPC32
651 static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) |
652 LIR_OprDesc::float_type |
653 LIR_OprDesc::cpu_register |
654 LIR_OprDesc::single_size); }
655 static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg2 << LIR_OprDesc::reg1_shift) |
656 (reg1 << LIR_OprDesc::reg2_shift) |
657 LIR_OprDesc::double_type |
658 LIR_OprDesc::cpu_register |
659 LIR_OprDesc::double_size); }
660 #endif // PPC32
661
662 static LIR_Opr virtual_register(int index, BasicType type) {
663 LIR_Opr res;
664 switch (type) {
665 case T_OBJECT: // fall through
666 case T_ARRAY:
667 res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
668 LIR_OprDesc::object_type |
669 LIR_OprDesc::cpu_register |
670 LIR_OprDesc::single_size |
671 LIR_OprDesc::virtual_mask);
672 break;
673
674 case T_METADATA:
675 res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
676 LIR_OprDesc::metadata_type|
677 LIR_OprDesc::cpu_register |
678 LIR_OprDesc::single_size |
679 LIR_OprDesc::virtual_mask);
680 break;
1450 CodeStub* stub() const { return _stub; }
1451
1452 void change_block(BlockBegin* b);
1453 void change_ublock(BlockBegin* b);
1454 void negate_cond();
1455
1456 virtual void emit_code(LIR_Assembler* masm);
1457 virtual LIR_OpBranch* as_OpBranch() { return this; }
1458 virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1459 };
1460
1461
1462 class ConversionStub;
1463
1464 class LIR_OpConvert: public LIR_Op1 {
1465 friend class LIR_OpVisitState;
1466
1467 private:
1468 Bytecodes::Code _bytecode;
1469 ConversionStub* _stub;
1470 #ifdef PPC32
1471 LIR_Opr _tmp1;
1472 LIR_Opr _tmp2;
1473 #endif
1474
1475 public:
1476 LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub)
1477 : LIR_Op1(lir_convert, opr, result)
1478 , _stub(stub)
1479 #ifdef PPC32
1480 , _tmp1(LIR_OprDesc::illegalOpr())
1481 , _tmp2(LIR_OprDesc::illegalOpr())
1482 #endif
1483 , _bytecode(code) {}
1484
1485 #ifdef PPC32
1486 LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub
1487 ,LIR_Opr tmp1, LIR_Opr tmp2)
1488 : LIR_Op1(lir_convert, opr, result)
1489 , _stub(stub)
1490 , _tmp1(tmp1)
1491 , _tmp2(tmp2)
1492 , _bytecode(code) {}
1493 #endif
1494
1495 Bytecodes::Code bytecode() const { return _bytecode; }
1496 ConversionStub* stub() const { return _stub; }
1497 #ifdef PPC32
1498 LIR_Opr tmp1() const { return _tmp1; }
1499 LIR_Opr tmp2() const { return _tmp2; }
1500 #endif
1501
1502 virtual void emit_code(LIR_Assembler* masm);
1503 virtual LIR_OpConvert* as_OpConvert() { return this; }
1504 virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1505
1506 static void print_bytecode(outputStream* out, Bytecodes::Code code) PRODUCT_RETURN;
1507 };
1508
1509
1510 // LIR_OpAllocObj
1511 class LIR_OpAllocObj : public LIR_Op1 {
1512 friend class LIR_OpVisitState;
1513
1514 private:
1515 LIR_Opr _tmp1;
1516 LIR_Opr _tmp2;
1517 LIR_Opr _tmp3;
1518 LIR_Opr _tmp4;
1519 int _hdr_size;
1520 int _obj_size;
2119 }
2120 void move_wide(LIR_Opr src, LIR_Address* dst, CodeEmitInfo* info = NULL) {
2121 if (UseCompressedOops) {
2122 append(new LIR_Op1(lir_move, src, LIR_OprFact::address(dst), dst->type(), lir_patch_none, info, lir_move_wide));
2123 } else {
2124 move(src, dst, info);
2125 }
2126 }
2127 void volatile_move(LIR_Opr src, LIR_Opr dst, BasicType type, CodeEmitInfo* info = NULL, LIR_PatchCode patch_code = lir_patch_none) { append(new LIR_Op1(lir_move, src, dst, type, patch_code, info, lir_move_volatile)); }
2128
2129 void oop2reg (jobject o, LIR_Opr reg) { assert(reg->type() == T_OBJECT, "bad reg"); append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg)); }
2130 void oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info);
2131
2132 void metadata2reg (Metadata* o, LIR_Opr reg) { assert(reg->type() == T_METADATA, "bad reg"); append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg)); }
2133 void klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info);
2134
2135 void return_op(LIR_Opr result) { append(new LIR_Op1(lir_return, result)); }
2136
2137 void safepoint(LIR_Opr tmp, CodeEmitInfo* info) { append(new LIR_Op1(lir_safepoint, tmp, info)); }
2138
2139 #ifdef PPC32
2140 void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_OpConvert(code, left, dst, NULL, tmp1, tmp2)); }
2141 #endif
2142 void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); }
2143
2144 void logical_and (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_and, left, right, dst)); }
2145 void logical_or (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_or, left, right, dst)); }
2146 void logical_xor (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_xor, left, right, dst)); }
2147
2148 void pack64(LIR_Opr src, LIR_Opr dst) { append(new LIR_Op1(lir_pack64, src, dst, T_LONG, lir_patch_none, NULL)); }
2149 void unpack64(LIR_Opr src, LIR_Opr dst) { append(new LIR_Op1(lir_unpack64, src, dst, T_LONG, lir_patch_none, NULL)); }
2150
2151 void null_check(LIR_Opr opr, CodeEmitInfo* info) { append(new LIR_Op1(lir_null_check, opr, info)); }
2152 void throw_exception(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2153 append(new LIR_Op2(lir_throw, exceptionPC, exceptionOop, LIR_OprFact::illegalOpr, info));
2154 }
2155 void unwind_exception(LIR_Opr exceptionOop) {
2156 append(new LIR_Op1(lir_unwind, exceptionOop));
2157 }
2158
2159 void compare_to (LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2160 append(new LIR_Op2(lir_compare_to, left, right, dst));
2161 }
|
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef SHARE_VM_C1_C1_LIR_HPP
26 #define SHARE_VM_C1_C1_LIR_HPP
27
28 #include "c1/c1_Defs.hpp"
29 #include "c1/c1_ValueType.hpp"
30 #include "oops/method.hpp"
31 #include "utilities/globalDefinitions.hpp"
32
33 class BlockBegin;
34 class BlockList;
35 class LIR_Assembler;
36 class CodeEmitInfo;
37 class CodeStub;
38 class CodeStubList;
39 class ArrayCopyStub;
40 class LIR_Op;
41 class ciType;
42 class ValueType;
43 class LIR_OpVisitState;
44 class FpuStackSim;
45
46 //---------------------------------------------------------------------
47 // LIR Operands
48 // LIR_OprDesc
49 // LIR_OprPtr
50 // LIR_Const
51 // LIR_Address
422 int vreg_number() const { assert(is_virtual(), "type check"); return (RegNr)data(); }
423
424 LIR_OprPtr* pointer() const { assert(is_pointer(), "type check"); return (LIR_OprPtr*)this; }
425 LIR_Const* as_constant_ptr() const { return pointer()->as_constant(); }
426 LIR_Address* as_address_ptr() const { return pointer()->as_address(); }
427
428 Register as_register() const;
429 Register as_register_lo() const;
430 Register as_register_hi() const;
431
432 Register as_pointer_register() {
433 #ifdef _LP64
434 if (is_double_cpu()) {
435 assert(as_register_lo() == as_register_hi(), "should be a single register");
436 return as_register_lo();
437 }
438 #endif
439 return as_register();
440 }
441
442 FloatRegister as_float_reg () const;
443 FloatRegister as_double_reg () const;
444 #ifdef X86
445 XMMRegister as_xmm_float_reg () const;
446 XMMRegister as_xmm_double_reg() const;
447 // for compatibility with RInfo
448 int fpu() const { return lo_reg_half(); }
449 #endif
450
451 jint as_jint() const { return as_constant_ptr()->as_jint(); }
452 jlong as_jlong() const { return as_constant_ptr()->as_jlong(); }
453 jfloat as_jfloat() const { return as_constant_ptr()->as_jfloat(); }
454 jdouble as_jdouble() const { return as_constant_ptr()->as_jdouble(); }
455 jobject as_jobject() const { return as_constant_ptr()->as_jobject(); }
456
457 void print() const PRODUCT_RETURN;
458 void print(outputStream* out) const PRODUCT_RETURN;
459 };
460
461
462 inline LIR_OprDesc::OprType as_OprType(BasicType type) {
463 switch (type) {
464 case T_INT: return LIR_OprDesc::int_type;
465 case T_LONG: return LIR_OprDesc::long_type;
466 case T_FLOAT: return LIR_OprDesc::float_type;
467 case T_DOUBLE: return LIR_OprDesc::double_type;
468 case T_OBJECT:
516 _base(base)
517 , _index(index)
518 , _scale(times_1)
519 , _type(type)
520 , _disp(0) { verify(); }
521
522 LIR_Address(LIR_Opr base, intx disp, BasicType type):
523 _base(base)
524 , _index(LIR_OprDesc::illegalOpr())
525 , _scale(times_1)
526 , _type(type)
527 , _disp(disp) { verify(); }
528
529 LIR_Address(LIR_Opr base, BasicType type):
530 _base(base)
531 , _index(LIR_OprDesc::illegalOpr())
532 , _scale(times_1)
533 , _type(type)
534 , _disp(0) { verify(); }
535
536 LIR_Address(LIR_Opr base, LIR_Opr index, intx disp, BasicType type):
537 _base(base)
538 , _index(index)
539 , _scale(times_1)
540 , _type(type)
541 , _disp(disp) { verify(); }
542
543 LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type):
544 _base(base)
545 , _index(index)
546 , _scale(scale)
547 , _type(type)
548 , _disp(disp) { verify(); }
549
550 LIR_Opr base() const { return _base; }
551 LIR_Opr index() const { return _index; }
552 Scale scale() const { return _scale; }
553 intx disp() const { return _disp; }
554
555 bool equals(LIR_Address* other) const { return base() == other->base() && index() == other->index() && disp() == other->disp() && scale() == other->scale(); }
556
557 virtual LIR_Address* as_address() { return this; }
558 virtual BasicType type() const { return _type; }
559 virtual void print_value_on(outputStream* out) const PRODUCT_RETURN;
560
561 void verify() const PRODUCT_RETURN;
562
563 static Scale scale(BasicType type);
564 };
565
566
567 // operand factory
568 class LIR_OprFact: public AllStatic {
569 public:
570
571 static LIR_Opr illegalOpr;
572
573 static LIR_Opr single_cpu(int reg) {
574 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
575 LIR_OprDesc::int_type |
576 LIR_OprDesc::cpu_register |
577 LIR_OprDesc::single_size);
578 }
579 static LIR_Opr single_cpu_oop(int reg) {
580 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
581 LIR_OprDesc::object_type |
586 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
587 LIR_OprDesc::address_type |
588 LIR_OprDesc::cpu_register |
589 LIR_OprDesc::single_size);
590 }
591 static LIR_Opr single_cpu_metadata(int reg) {
592 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
593 LIR_OprDesc::metadata_type |
594 LIR_OprDesc::cpu_register |
595 LIR_OprDesc::single_size);
596 }
597 static LIR_Opr double_cpu(int reg1, int reg2) {
598 LP64_ONLY(assert(reg1 == reg2, "must be identical"));
599 return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
600 (reg2 << LIR_OprDesc::reg2_shift) |
601 LIR_OprDesc::long_type |
602 LIR_OprDesc::cpu_register |
603 LIR_OprDesc::double_size);
604 }
605
606 static LIR_Opr single_fpu(int reg) {
607 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
608 LIR_OprDesc::float_type |
609 LIR_OprDesc::fpu_register |
610 LIR_OprDesc::single_size);
611 }
612
613 // Platform dependant.
614 static LIR_Opr double_fpu(int reg1, int reg2 = -1 /*fnoreg*/);
615
616 #ifdef __SOFTFP__
617 static LIR_Opr single_softfp(int reg) {
618 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
619 LIR_OprDesc::float_type |
620 LIR_OprDesc::cpu_register |
621 LIR_OprDesc::single_size);
622 }
623 static LIR_Opr double_softfp(int reg1, int reg2) {
624 return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
625 (reg2 << LIR_OprDesc::reg2_shift) |
626 LIR_OprDesc::double_type |
627 LIR_OprDesc::cpu_register |
628 LIR_OprDesc::double_size);
629 }
630 #endif // __SOFTFP__
631
632 #if defined(X86)
633 static LIR_Opr single_xmm(int reg) {
634 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
635 LIR_OprDesc::float_type |
636 LIR_OprDesc::fpu_register |
637 LIR_OprDesc::single_size |
638 LIR_OprDesc::is_xmm_mask);
639 }
640 static LIR_Opr double_xmm(int reg) {
641 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
642 (reg << LIR_OprDesc::reg2_shift) |
643 LIR_OprDesc::double_type |
644 LIR_OprDesc::fpu_register |
645 LIR_OprDesc::double_size |
646 LIR_OprDesc::is_xmm_mask);
647 }
648 #endif // X86
649
650 static LIR_Opr virtual_register(int index, BasicType type) {
651 LIR_Opr res;
652 switch (type) {
653 case T_OBJECT: // fall through
654 case T_ARRAY:
655 res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
656 LIR_OprDesc::object_type |
657 LIR_OprDesc::cpu_register |
658 LIR_OprDesc::single_size |
659 LIR_OprDesc::virtual_mask);
660 break;
661
662 case T_METADATA:
663 res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
664 LIR_OprDesc::metadata_type|
665 LIR_OprDesc::cpu_register |
666 LIR_OprDesc::single_size |
667 LIR_OprDesc::virtual_mask);
668 break;
1438 CodeStub* stub() const { return _stub; }
1439
1440 void change_block(BlockBegin* b);
1441 void change_ublock(BlockBegin* b);
1442 void negate_cond();
1443
1444 virtual void emit_code(LIR_Assembler* masm);
1445 virtual LIR_OpBranch* as_OpBranch() { return this; }
1446 virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1447 };
1448
1449
1450 class ConversionStub;
1451
1452 class LIR_OpConvert: public LIR_Op1 {
1453 friend class LIR_OpVisitState;
1454
1455 private:
1456 Bytecodes::Code _bytecode;
1457 ConversionStub* _stub;
1458
1459 public:
1460 LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub)
1461 : LIR_Op1(lir_convert, opr, result)
1462 , _stub(stub)
1463 , _bytecode(code) {}
1464
1465 Bytecodes::Code bytecode() const { return _bytecode; }
1466 ConversionStub* stub() const { return _stub; }
1467
1468 virtual void emit_code(LIR_Assembler* masm);
1469 virtual LIR_OpConvert* as_OpConvert() { return this; }
1470 virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1471
1472 static void print_bytecode(outputStream* out, Bytecodes::Code code) PRODUCT_RETURN;
1473 };
1474
1475
1476 // LIR_OpAllocObj
1477 class LIR_OpAllocObj : public LIR_Op1 {
1478 friend class LIR_OpVisitState;
1479
1480 private:
1481 LIR_Opr _tmp1;
1482 LIR_Opr _tmp2;
1483 LIR_Opr _tmp3;
1484 LIR_Opr _tmp4;
1485 int _hdr_size;
1486 int _obj_size;
2085 }
2086 void move_wide(LIR_Opr src, LIR_Address* dst, CodeEmitInfo* info = NULL) {
2087 if (UseCompressedOops) {
2088 append(new LIR_Op1(lir_move, src, LIR_OprFact::address(dst), dst->type(), lir_patch_none, info, lir_move_wide));
2089 } else {
2090 move(src, dst, info);
2091 }
2092 }
2093 void volatile_move(LIR_Opr src, LIR_Opr dst, BasicType type, CodeEmitInfo* info = NULL, LIR_PatchCode patch_code = lir_patch_none) { append(new LIR_Op1(lir_move, src, dst, type, patch_code, info, lir_move_volatile)); }
2094
2095 void oop2reg (jobject o, LIR_Opr reg) { assert(reg->type() == T_OBJECT, "bad reg"); append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg)); }
2096 void oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info);
2097
2098 void metadata2reg (Metadata* o, LIR_Opr reg) { assert(reg->type() == T_METADATA, "bad reg"); append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg)); }
2099 void klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info);
2100
2101 void return_op(LIR_Opr result) { append(new LIR_Op1(lir_return, result)); }
2102
2103 void safepoint(LIR_Opr tmp, CodeEmitInfo* info) { append(new LIR_Op1(lir_safepoint, tmp, info)); }
2104
2105 void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); }
2106
2107 void logical_and (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_and, left, right, dst)); }
2108 void logical_or (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_or, left, right, dst)); }
2109 void logical_xor (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_xor, left, right, dst)); }
2110
2111 void pack64(LIR_Opr src, LIR_Opr dst) { append(new LIR_Op1(lir_pack64, src, dst, T_LONG, lir_patch_none, NULL)); }
2112 void unpack64(LIR_Opr src, LIR_Opr dst) { append(new LIR_Op1(lir_unpack64, src, dst, T_LONG, lir_patch_none, NULL)); }
2113
2114 void null_check(LIR_Opr opr, CodeEmitInfo* info) { append(new LIR_Op1(lir_null_check, opr, info)); }
2115 void throw_exception(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2116 append(new LIR_Op2(lir_throw, exceptionPC, exceptionOop, LIR_OprFact::illegalOpr, info));
2117 }
2118 void unwind_exception(LIR_Opr exceptionOop) {
2119 append(new LIR_Op1(lir_unwind, exceptionOop));
2120 }
2121
2122 void compare_to (LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2123 append(new LIR_Op2(lir_compare_to, left, right, dst));
2124 }
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