--- old/src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp	2016-07-12 14:03:56.468565646 +0200
+++ new/src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp	2016-07-12 14:03:56.408565644 +0200
@@ -808,7 +808,6 @@
   } else {
     a = new LIR_Address(obj.result(),
                         offset.result(),
-                        LIR_Address::times_1,
                         0,
                         as_BasicType(type));
   }
@@ -1002,7 +1001,6 @@
 
       LIR_Address* a = new LIR_Address(base_op,
                                        index,
-                                       LIR_Address::times_1,
                                        offset,
                                        T_BYTE);
       BasicTypeList signature(3);
--- old/src/cpu/aarch64/vm/c1_LIR_aarch64.cpp	2016-07-12 14:03:56.708565653 +0200
+++ new/src/cpu/aarch64/vm/c1_LIR_aarch64.cpp	2016-07-12 14:03:56.648565651 +0200
@@ -36,7 +36,7 @@
 
 // Reg2 unused.
 LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
-  assert(reg2 == fnoreg->encoding(), "Not used on this platform");
+  assert(as_FloatRegister(reg2) == fnoreg, "Not used on this platform");
   return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
                              (reg1 << LIR_OprDesc::reg2_shift) |
                              LIR_OprDesc::double_type          |
--- old/src/cpu/ppc/vm/register_ppc.hpp	2016-07-12 14:03:56.940565660 +0200
+++ new/src/cpu/ppc/vm/register_ppc.hpp	2016-07-12 14:03:56.884565658 +0200
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2014 SAP SE. All rights reserved.
+ * Copyright (c) 2000, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- old/src/cpu/ppc/vm/templateInterpreterGenerator_ppc.cpp	2016-07-12 14:03:57.200565668 +0200
+++ new/src/cpu/ppc/vm/templateInterpreterGenerator_ppc.cpp	2016-07-12 14:03:57.136565666 +0200
@@ -1563,7 +1563,6 @@
     // Don't check for exceptions since we're still in the i2n frame. Do that
     // manually afterwards.
     __ unlock_object(R26_monitor, false); // Can also unlock methods.
-
   }
 
   // Reset active handles after returning from native.
--- old/src/cpu/sparc/vm/c1_LIR_sparc.cpp	2016-07-12 14:03:57.456565675 +0200
+++ new/src/cpu/sparc/vm/c1_LIR_sparc.cpp	2016-07-12 14:03:57.396565673 +0200
@@ -36,7 +36,7 @@
 }
 
 LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
-  assert(reg2 != fnoreg->encoding(), "Sparc holds double in two regs.");
+  assert(as_FloatRegister(reg2) != fnoreg, "Sparc holds double in two regs.");
   return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
                              (reg2 << LIR_OprDesc::reg2_shift) |
                              LIR_OprDesc::double_type          |
--- old/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp	2016-07-12 14:03:57.696565682 +0200
+++ new/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp	2016-07-12 14:03:57.632565680 +0200
@@ -761,7 +761,6 @@
   } else {
     a = new LIR_Address(obj.result(),
                         offset.result(),
-                        LIR_Address::times_1,
                         0,
                         as_BasicType(type));
   }
--- old/src/cpu/x86/vm/register_definitions_x86.cpp	2016-07-12 14:03:57.956565690 +0200
+++ new/src/cpu/x86/vm/register_definitions_x86.cpp	2016-07-12 14:03:57.892565688 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2002, 2016, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- old/src/cpu/x86/vm/register_x86.hpp	2016-07-12 14:03:58.220565698 +0200
+++ new/src/cpu/x86/vm/register_x86.hpp	2016-07-12 14:03:58.156565696 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2016, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- old/src/share/vm/c1/c1_LIR.cpp	2016-07-12 14:03:58.492565706 +0200
+++ new/src/share/vm/c1/c1_LIR.cpp	2016-07-12 14:03:58.416565704 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2016, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -42,73 +42,6 @@
   return FrameMap::cpu_rnr2reg(cpu_regnrHi());
 }
 
-#ifdef PPC32
-FloatRegister LIR_OprDesc::as_float_reg() const {
-  return FrameMap::nr2floatreg(fpu_regnr());
-}
-
-FloatRegister LIR_OprDesc::as_double_reg() const {
-  return FrameMap::nr2floatreg(fpu_regnrHi());
-}
-// Reg2 unused.
-LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
-  assert(reg2 == -1 /*fnoreg*/, "Not used on this platform");
-  return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
-                             (reg << LIR_OprDesc::reg2_shift) |
-                             LIR_OprDesc::double_type         |
-                             LIR_OprDesc::fpu_register        |
-                             LIR_OprDesc::double_size);
-}
-#ifndef PRODUCT
-#if defined(LIR_ADDRESS_PD_VERIFY)
-  void LIR_Address::verify() const { pd_verify(); }
-#else
-void LIR_Address::verify() const {
-  assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
-  assert(disp() == 0 || index()->is_illegal(), "can't have both");
-  assert(base()->is_single_cpu(), "wrong base operand");
-  assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
-  assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
-         "wrong type for addresses");
-}
-#endif // (LIR_ADDRESS_PD_VERIFY
-#endif // PRODUCT
-#endif // PPC32
-
-#ifdef ARM
-FloatRegister LIR_OprDesc::as_float_reg() const {
-  return as_FloatRegister(fpu_regnr());
-}
-FloatRegister LIR_OprDesc::as_double_reg() const {
-  return as_FloatRegister(fpu_regnrLo());
-}
-#ifndef PRODUCT
-#if defined(LIR_ADDRESS_PD_VERIFY)
-  void verify() const { pd_verify(); }
-#else
-void LIR_Address::verify() const {
-  assert(base()->is_single_cpu(), "wrong base operand");
-  assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
-  assert(scale() == times_1, "Scaled addressing mode not available on PPC and should not be used");
-  assert(disp() == 0 || index()->is_illegal(), "can't have both");
-  assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
-         "wrong type for addresses");
-}
-#endif // LIR_ADDRESS_PD_VERIFY
-#endif // PRODUCT
-#endif // ARM
-#ifdef ARM32
-LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
-  assert(reg2 != -1 /*fnoreg*/, "Arm32 holds double in two regs.");
-  return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
-                             (reg2 << LIR_OprDesc::reg2_shift) |
-                             LIR_OprDesc::double_type          |
-                             LIR_OprDesc::fpu_register         |
-                             LIR_OprDesc::double_size);
-}
-#endif // ARM32
-
-
 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
 
 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
--- old/src/share/vm/c1/c1_LIR.hpp	2016-07-12 14:03:58.736565713 +0200
+++ new/src/share/vm/c1/c1_LIR.hpp	2016-07-12 14:03:58.676565711 +0200
@@ -621,7 +621,6 @@
                                LIR_OprDesc::single_size);
   }
   static LIR_Opr double_softfp(int reg1, int reg2) {
-    PPC32_ONLY(swap(reg1, reg2);)
     return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
                                (reg2 << LIR_OprDesc::reg2_shift) |
                                LIR_OprDesc::double_type          |
@@ -1456,37 +1455,15 @@
  private:
    Bytecodes::Code _bytecode;
    ConversionStub* _stub;
-#ifdef PPC32
-  LIR_Opr _tmp1;
-  LIR_Opr _tmp2;
-#endif
 
  public:
    LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub)
      : LIR_Op1(lir_convert, opr, result)
      , _stub(stub)
-#ifdef PPC32
-     , _tmp1(LIR_OprDesc::illegalOpr())
-     , _tmp2(LIR_OprDesc::illegalOpr())
-#endif
      , _bytecode(code)                           {}
 
-#ifdef PPC32
-   LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub
-                 ,LIR_Opr tmp1, LIR_Opr tmp2)
-     : LIR_Op1(lir_convert, opr, result)
-     , _stub(stub)
-     , _tmp1(tmp1)
-     , _tmp2(tmp2)
-     , _bytecode(code)                           {}
-#endif
-
   Bytecodes::Code bytecode() const               { return _bytecode; }
   ConversionStub* stub() const                   { return _stub; }
-#ifdef PPC32
-  LIR_Opr tmp1() const                           { return _tmp1; }
-  LIR_Opr tmp2() const                           { return _tmp2; }
-#endif
 
   virtual void emit_code(LIR_Assembler* masm);
   virtual LIR_OpConvert* as_OpConvert() { return this; }
@@ -2125,9 +2102,6 @@
 
   void safepoint(LIR_Opr tmp, CodeEmitInfo* info)  { append(new LIR_Op1(lir_safepoint, tmp, info)); }
 
-#ifdef PPC32
-  void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_OpConvert(code, left, dst, NULL, tmp1, tmp2)); }
-#endif
   void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); }
 
   void logical_and (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_and,  left, right, dst)); }
--- old/src/share/vm/c1/c1_globals.hpp	2016-07-12 14:03:59.008565721 +0200
+++ new/src/share/vm/c1/c1_globals.hpp	2016-07-12 14:03:58.944565719 +0200
@@ -303,9 +303,9 @@
   develop(bool, InstallMethods, true,                                       \
           "Install methods at the end of successful compilations")          \
                                                                             \
-  develop(intx, NMethodSizeLimit, NOT_PPC32(2*)(32*K)*wordSize,             \
+  develop(intx, NMethodSizeLimit, (64*K)*wordSize,                          \
           "Maximum size of a compiled method.")                             \
-           range(0, NOT_PPC32(max_jint) PPC32_ONLY(32*K))                   \
+          range(0, max_jint)                                                \
                                                                             \
   develop(bool, TraceFPUStack, false,                                       \
           "Trace emulation of the FPU stack (intel only)")                  \