1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_InstructionPrinter.hpp"
27 #include "c1/c1_LIR.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_ValueStack.hpp"
30 #include "ci/ciInstance.hpp"
31 #include "runtime/sharedRuntime.hpp"
32
33 Register LIR_OprDesc::as_register() const {
34 return FrameMap::cpu_rnr2reg(cpu_regnr());
35 }
36
37 Register LIR_OprDesc::as_register_lo() const {
38 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
39 }
40
41 Register LIR_OprDesc::as_register_hi() const {
42 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
43 }
44
45 #ifdef PPC32
46 FloatRegister LIR_OprDesc::as_float_reg() const {
47 return FrameMap::nr2floatreg(fpu_regnr());
48 }
49
50 FloatRegister LIR_OprDesc::as_double_reg() const {
51 return FrameMap::nr2floatreg(fpu_regnrHi());
52 }
53 // Reg2 unused.
54 LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
55 assert(reg2 == -1 /*fnoreg*/, "Not used on this platform");
56 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
57 (reg << LIR_OprDesc::reg2_shift) |
58 LIR_OprDesc::double_type |
59 LIR_OprDesc::fpu_register |
60 LIR_OprDesc::double_size);
61 }
62 #ifndef PRODUCT
63 #if defined(LIR_ADDRESS_PD_VERIFY)
64 void LIR_Address::verify() const { pd_verify(); }
65 #else
66 void LIR_Address::verify() const {
67 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
68 assert(disp() == 0 || index()->is_illegal(), "can't have both");
69 assert(base()->is_single_cpu(), "wrong base operand");
70 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
71 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
72 "wrong type for addresses");
73 }
74 #endif // (LIR_ADDRESS_PD_VERIFY
75 #endif // PRODUCT
76 #endif // PPC32
77
78 #ifdef ARM
79 FloatRegister LIR_OprDesc::as_float_reg() const {
80 return as_FloatRegister(fpu_regnr());
81 }
82 FloatRegister LIR_OprDesc::as_double_reg() const {
83 return as_FloatRegister(fpu_regnrLo());
84 }
85 #ifndef PRODUCT
86 #if defined(LIR_ADDRESS_PD_VERIFY)
87 void verify() const { pd_verify(); }
88 #else
89 void LIR_Address::verify() const {
90 assert(base()->is_single_cpu(), "wrong base operand");
91 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
92 assert(scale() == times_1, "Scaled addressing mode not available on PPC and should not be used");
93 assert(disp() == 0 || index()->is_illegal(), "can't have both");
94 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
95 "wrong type for addresses");
96 }
97 #endif // LIR_ADDRESS_PD_VERIFY
98 #endif // PRODUCT
99 #endif // ARM
100 #ifdef ARM32
101 LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
102 assert(reg2 != -1 /*fnoreg*/, "Arm32 holds double in two regs.");
103 return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
104 (reg2 << LIR_OprDesc::reg2_shift) |
105 LIR_OprDesc::double_type |
106 LIR_OprDesc::fpu_register |
107 LIR_OprDesc::double_size);
108 }
109 #endif // ARM32
110
111
112 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
113
114 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
115 ValueTag tag = type->tag();
116 switch (tag) {
117 case metaDataTag : {
118 ClassConstant* c = type->as_ClassConstant();
119 if (c != NULL && !c->value()->is_loaded()) {
120 return LIR_OprFact::metadataConst(NULL);
121 } else if (c != NULL) {
122 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
123 } else {
124 MethodConstant* m = type->as_MethodConstant();
125 assert (m != NULL, "not a class or a method?");
126 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
127 }
128 }
129 case objectTag : {
130 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
131 }
132 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
133 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
134 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
135 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
136 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
137 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
138 }
139 }
140
141
142 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
143 switch (type->tag()) {
144 case objectTag: return LIR_OprFact::oopConst(NULL);
145 case addressTag:return LIR_OprFact::addressConst(0);
146 case intTag: return LIR_OprFact::intConst(0);
147 case floatTag: return LIR_OprFact::floatConst(0.0);
148 case longTag: return LIR_OprFact::longConst(0);
149 case doubleTag: return LIR_OprFact::doubleConst(0.0);
150 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
151 }
152 return illegalOpr;
153 }
154
155
156
157 //---------------------------------------------------
158
159
160 LIR_Address::Scale LIR_Address::scale(BasicType type) {
161 int elem_size = type2aelembytes(type);
162 switch (elem_size) {
163 case 1: return LIR_Address::times_1;
164 case 2: return LIR_Address::times_2;
165 case 4: return LIR_Address::times_4;
166 case 8: return LIR_Address::times_8;
167 }
168 ShouldNotReachHere();
169 return LIR_Address::times_1;
170 }
171
172 //---------------------------------------------------
173
174 char LIR_OprDesc::type_char(BasicType t) {
175 switch (t) {
176 case T_ARRAY:
177 t = T_OBJECT;
178 case T_BOOLEAN:
179 case T_CHAR:
180 case T_FLOAT:
181 case T_DOUBLE:
182 case T_BYTE:
183 case T_SHORT:
184 case T_INT:
185 case T_LONG:
186 case T_OBJECT:
187 case T_ADDRESS:
188 case T_VOID:
189 return ::type2char(t);
190 case T_METADATA:
191 return 'M';
192 case T_ILLEGAL:
193 return '?';
194
195 default:
196 ShouldNotReachHere();
197 return '?';
198 }
199 }
200
201 #ifndef PRODUCT
202 void LIR_OprDesc::validate_type() const {
203
204 #ifdef ASSERT
205 if (!is_pointer() && !is_illegal()) {
206 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
207 switch (as_BasicType(type_field())) {
208 case T_LONG:
209 assert((kindfield == cpu_register || kindfield == stack_value) &&
210 size_field() == double_size, "must match");
211 break;
212 case T_FLOAT:
213 // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI)
214 assert((kindfield == fpu_register || kindfield == stack_value
215 ARM_ONLY(|| kindfield == cpu_register)
216 PPC32_ONLY(|| kindfield == cpu_register) ) &&
217 size_field() == single_size, "must match");
218 break;
219 case T_DOUBLE:
220 // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI)
221 assert((kindfield == fpu_register || kindfield == stack_value
222 ARM_ONLY(|| kindfield == cpu_register)
223 PPC32_ONLY(|| kindfield == cpu_register) ) &&
224 size_field() == double_size, "must match");
225 break;
226 case T_BOOLEAN:
227 case T_CHAR:
228 case T_BYTE:
229 case T_SHORT:
230 case T_INT:
231 case T_ADDRESS:
232 case T_OBJECT:
233 case T_METADATA:
234 case T_ARRAY:
235 assert((kindfield == cpu_register || kindfield == stack_value) &&
236 size_field() == single_size, "must match");
237 break;
238
239 case T_ILLEGAL:
240 // XXX TKR also means unknown right now
241 // assert(is_illegal(), "must match");
242 break;
243
244 default:
245 ShouldNotReachHere();
246 }
247 }
248 #endif
249
250 }
251 #endif // PRODUCT
252
253
254 bool LIR_OprDesc::is_oop() const {
255 if (is_pointer()) {
256 return pointer()->is_oop_pointer();
257 } else {
258 OprType t= type_field();
259 assert(t != unknown_type, "not set");
260 return t == object_type;
261 }
262 }
263
264
265
266 void LIR_Op2::verify() const {
267 #ifdef ASSERT
268 switch (code()) {
269 case lir_cmove:
270 case lir_xchg:
271 break;
272
273 default:
274 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
275 "can't produce oops from arith");
276 }
277
278 if (TwoOperandLIRForm) {
279 switch (code()) {
280 case lir_add:
281 case lir_sub:
282 case lir_mul:
283 case lir_mul_strictfp:
284 case lir_div:
285 case lir_div_strictfp:
286 case lir_rem:
287 case lir_logic_and:
288 case lir_logic_or:
289 case lir_logic_xor:
290 case lir_shl:
291 case lir_shr:
292 assert(in_opr1() == result_opr(), "opr1 and result must match");
293 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
294 break;
295
296 // special handling for lir_ushr because of write barriers
297 case lir_ushr:
298 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
299 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
300 break;
301
302 }
303 }
304 #endif
305 }
306
307
308 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
309 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
310 , _cond(cond)
311 , _type(type)
312 , _label(block->label())
313 , _block(block)
314 , _ublock(NULL)
315 , _stub(NULL) {
316 }
317
318 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
319 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
320 , _cond(cond)
321 , _type(type)
322 , _label(stub->entry())
323 , _block(NULL)
324 , _ublock(NULL)
325 , _stub(stub) {
326 }
327
328 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
329 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
330 , _cond(cond)
331 , _type(type)
332 , _label(block->label())
333 , _block(block)
334 , _ublock(ublock)
335 , _stub(NULL)
336 {
337 }
338
339 void LIR_OpBranch::change_block(BlockBegin* b) {
340 assert(_block != NULL, "must have old block");
341 assert(_block->label() == label(), "must be equal");
342
343 _block = b;
344 _label = b->label();
345 }
346
347 void LIR_OpBranch::change_ublock(BlockBegin* b) {
348 assert(_ublock != NULL, "must have old block");
349 _ublock = b;
350 }
351
352 void LIR_OpBranch::negate_cond() {
353 switch (_cond) {
354 case lir_cond_equal: _cond = lir_cond_notEqual; break;
355 case lir_cond_notEqual: _cond = lir_cond_equal; break;
356 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
357 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
358 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
359 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
360 default: ShouldNotReachHere();
361 }
362 }
363
364
365 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
366 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
367 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
368 CodeStub* stub)
369
370 : LIR_Op(code, result, NULL)
371 , _object(object)
372 , _array(LIR_OprFact::illegalOpr)
373 , _klass(klass)
374 , _tmp1(tmp1)
375 , _tmp2(tmp2)
376 , _tmp3(tmp3)
377 , _fast_check(fast_check)
378 , _stub(stub)
379 , _info_for_patch(info_for_patch)
380 , _info_for_exception(info_for_exception)
381 , _profiled_method(NULL)
382 , _profiled_bci(-1)
383 , _should_profile(false)
384 {
385 if (code == lir_checkcast) {
386 assert(info_for_exception != NULL, "checkcast throws exceptions");
387 } else if (code == lir_instanceof) {
388 assert(info_for_exception == NULL, "instanceof throws no exceptions");
389 } else {
390 ShouldNotReachHere();
391 }
392 }
393
394
395
396 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
397 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
398 , _object(object)
399 , _array(array)
400 , _klass(NULL)
401 , _tmp1(tmp1)
402 , _tmp2(tmp2)
403 , _tmp3(tmp3)
404 , _fast_check(false)
405 , _stub(NULL)
406 , _info_for_patch(NULL)
407 , _info_for_exception(info_for_exception)
408 , _profiled_method(NULL)
409 , _profiled_bci(-1)
410 , _should_profile(false)
411 {
412 if (code == lir_store_check) {
413 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
414 assert(info_for_exception != NULL, "store_check throws exceptions");
415 } else {
416 ShouldNotReachHere();
417 }
418 }
419
420
421 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
422 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
423 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
424 , _tmp(tmp)
425 , _src(src)
426 , _src_pos(src_pos)
427 , _dst(dst)
428 , _dst_pos(dst_pos)
429 , _flags(flags)
430 , _expected_type(expected_type)
431 , _length(length) {
432 _stub = new ArrayCopyStub(this);
433 }
434
435 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
436 : LIR_Op(lir_updatecrc32, res, NULL)
437 , _crc(crc)
438 , _val(val) {
439 }
440
441 //-------------------verify--------------------------
442
443 void LIR_Op1::verify() const {
444 switch(code()) {
445 case lir_move:
446 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
447 break;
448 case lir_null_check:
449 assert(in_opr()->is_register(), "must be");
450 break;
451 case lir_return:
452 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
453 break;
454 }
455 }
456
457 void LIR_OpRTCall::verify() const {
458 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
459 }
460
461 //-------------------visits--------------------------
462
463 // complete rework of LIR instruction visitor.
464 // The virtual call for each instruction type is replaced by a big
465 // switch that adds the operands for each instruction
466
467 void LIR_OpVisitState::visit(LIR_Op* op) {
468 // copy information from the LIR_Op
469 reset();
470 set_op(op);
471
472 switch (op->code()) {
473
474 // LIR_Op0
475 case lir_word_align: // result and info always invalid
476 case lir_backwardbranch_target: // result and info always invalid
477 case lir_build_frame: // result and info always invalid
478 case lir_fpop_raw: // result and info always invalid
479 case lir_24bit_FPU: // result and info always invalid
480 case lir_reset_FPU: // result and info always invalid
481 case lir_breakpoint: // result and info always invalid
482 case lir_membar: // result and info always invalid
483 case lir_membar_acquire: // result and info always invalid
484 case lir_membar_release: // result and info always invalid
485 case lir_membar_loadload: // result and info always invalid
486 case lir_membar_storestore: // result and info always invalid
487 case lir_membar_loadstore: // result and info always invalid
488 case lir_membar_storeload: // result and info always invalid
489 case lir_on_spin_wait:
490 {
491 assert(op->as_Op0() != NULL, "must be");
492 assert(op->_info == NULL, "info not used by this instruction");
493 assert(op->_result->is_illegal(), "not used");
494 break;
495 }
496
497 case lir_nop: // may have info, result always invalid
498 case lir_std_entry: // may have result, info always invalid
499 case lir_osr_entry: // may have result, info always invalid
500 case lir_get_thread: // may have result, info always invalid
501 {
502 assert(op->as_Op0() != NULL, "must be");
503 if (op->_info != NULL) do_info(op->_info);
504 if (op->_result->is_valid()) do_output(op->_result);
505 break;
506 }
507
508
509 // LIR_OpLabel
510 case lir_label: // result and info always invalid
511 {
512 assert(op->as_OpLabel() != NULL, "must be");
513 assert(op->_info == NULL, "info not used by this instruction");
514 assert(op->_result->is_illegal(), "not used");
515 break;
516 }
517
518
519 // LIR_Op1
520 case lir_fxch: // input always valid, result and info always invalid
521 case lir_fld: // input always valid, result and info always invalid
522 case lir_ffree: // input always valid, result and info always invalid
523 case lir_push: // input always valid, result and info always invalid
524 case lir_pop: // input always valid, result and info always invalid
525 case lir_return: // input always valid, result and info always invalid
526 case lir_leal: // input and result always valid, info always invalid
527 case lir_neg: // input and result always valid, info always invalid
528 case lir_monaddr: // input and result always valid, info always invalid
529 case lir_null_check: // input and info always valid, result always invalid
530 case lir_move: // input and result always valid, may have info
531 case lir_pack64: // input and result always valid
532 case lir_unpack64: // input and result always valid
533 {
534 assert(op->as_Op1() != NULL, "must be");
535 LIR_Op1* op1 = (LIR_Op1*)op;
536
537 if (op1->_info) do_info(op1->_info);
538 if (op1->_opr->is_valid()) do_input(op1->_opr);
539 if (op1->_result->is_valid()) do_output(op1->_result);
540
541 break;
542 }
543
544 case lir_safepoint:
545 {
546 assert(op->as_Op1() != NULL, "must be");
547 LIR_Op1* op1 = (LIR_Op1*)op;
548
549 assert(op1->_info != NULL, ""); do_info(op1->_info);
550 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
551 assert(op1->_result->is_illegal(), "safepoint does not produce value");
552
553 break;
554 }
555
556 // LIR_OpConvert;
557 case lir_convert: // input and result always valid, info always invalid
558 {
559 assert(op->as_OpConvert() != NULL, "must be");
560 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
561
562 assert(opConvert->_info == NULL, "must be");
563 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
564 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
565 #ifdef PPC32
566 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
567 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
568 #endif
569 do_stub(opConvert->_stub);
570
571 break;
572 }
573
574 // LIR_OpBranch;
575 case lir_branch: // may have info, input and result register always invalid
576 case lir_cond_float_branch: // may have info, input and result register always invalid
577 {
578 assert(op->as_OpBranch() != NULL, "must be");
579 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
580
581 if (opBranch->_info != NULL) do_info(opBranch->_info);
582 assert(opBranch->_result->is_illegal(), "not used");
583 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
584
585 break;
586 }
587
588
589 // LIR_OpAllocObj
590 case lir_alloc_object:
591 {
592 assert(op->as_OpAllocObj() != NULL, "must be");
593 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
594
595 if (opAllocObj->_info) do_info(opAllocObj->_info);
596 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
597 do_temp(opAllocObj->_opr);
598 }
599 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
600 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
601 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
602 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
603 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
604 do_stub(opAllocObj->_stub);
605 break;
606 }
607
608
609 // LIR_OpRoundFP;
610 case lir_roundfp: {
611 assert(op->as_OpRoundFP() != NULL, "must be");
612 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
613
614 assert(op->_info == NULL, "info not used by this instruction");
615 assert(opRoundFP->_tmp->is_illegal(), "not used");
616 do_input(opRoundFP->_opr);
617 do_output(opRoundFP->_result);
618
619 break;
620 }
621
622
623 // LIR_Op2
624 case lir_cmp:
625 case lir_cmp_l2i:
626 case lir_ucmp_fd2i:
627 case lir_cmp_fd2i:
628 case lir_add:
629 case lir_sub:
630 case lir_mul:
631 case lir_div:
632 case lir_rem:
633 case lir_sqrt:
634 case lir_abs:
635 case lir_logic_and:
636 case lir_logic_or:
637 case lir_logic_xor:
638 case lir_shl:
639 case lir_shr:
640 case lir_ushr:
641 case lir_xadd:
642 case lir_xchg:
643 case lir_assert:
644 {
645 assert(op->as_Op2() != NULL, "must be");
646 LIR_Op2* op2 = (LIR_Op2*)op;
647 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
648 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
649
650 if (op2->_info) do_info(op2->_info);
651 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
652 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
653 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
654 if (op2->_result->is_valid()) do_output(op2->_result);
655 if (op->code() == lir_xchg || op->code() == lir_xadd) {
656 // on ARM and PPC, return value is loaded first so could
657 // destroy inputs. On other platforms that implement those
658 // (x86, sparc), the extra constrainsts are harmless.
659 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
660 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
661 }
662
663 break;
664 }
665
666 // special handling for cmove: right input operand must not be equal
667 // to the result operand, otherwise the backend fails
668 case lir_cmove:
669 {
670 assert(op->as_Op2() != NULL, "must be");
671 LIR_Op2* op2 = (LIR_Op2*)op;
672
673 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
674 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
675 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
676
677 do_input(op2->_opr1);
678 do_input(op2->_opr2);
679 do_temp(op2->_opr2);
680 do_output(op2->_result);
681
682 break;
683 }
684
685 // vspecial handling for strict operations: register input operands
686 // as temp to guarantee that they do not overlap with other
687 // registers
688 case lir_mul_strictfp:
689 case lir_div_strictfp:
690 {
691 assert(op->as_Op2() != NULL, "must be");
692 LIR_Op2* op2 = (LIR_Op2*)op;
693
694 assert(op2->_info == NULL, "not used");
695 assert(op2->_opr1->is_valid(), "used");
696 assert(op2->_opr2->is_valid(), "used");
697 assert(op2->_result->is_valid(), "used");
698 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
699 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
700
701 do_input(op2->_opr1); do_temp(op2->_opr1);
702 do_input(op2->_opr2); do_temp(op2->_opr2);
703 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
704 do_output(op2->_result);
705
706 break;
707 }
708
709 case lir_throw: {
710 assert(op->as_Op2() != NULL, "must be");
711 LIR_Op2* op2 = (LIR_Op2*)op;
712
713 if (op2->_info) do_info(op2->_info);
714 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
715 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
716 assert(op2->_result->is_illegal(), "no result");
717 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
718 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
719
720 break;
721 }
722
723 case lir_unwind: {
724 assert(op->as_Op1() != NULL, "must be");
725 LIR_Op1* op1 = (LIR_Op1*)op;
726
727 assert(op1->_info == NULL, "no info");
728 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
729 assert(op1->_result->is_illegal(), "no result");
730
731 break;
732 }
733
734 // LIR_Op3
735 case lir_idiv:
736 case lir_irem: {
737 assert(op->as_Op3() != NULL, "must be");
738 LIR_Op3* op3= (LIR_Op3*)op;
739
740 if (op3->_info) do_info(op3->_info);
741 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
742
743 // second operand is input and temp, so ensure that second operand
744 // and third operand get not the same register
745 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
746 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
747 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
748
749 if (op3->_result->is_valid()) do_output(op3->_result);
750
751 break;
752 }
753
754
755 // LIR_OpJavaCall
756 case lir_static_call:
757 case lir_optvirtual_call:
758 case lir_icvirtual_call:
759 case lir_virtual_call:
760 case lir_dynamic_call: {
761 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
762 assert(opJavaCall != NULL, "must be");
763
764 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
765
766 // only visit register parameters
767 int n = opJavaCall->_arguments->length();
768 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
769 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
770 do_input(*opJavaCall->_arguments->adr_at(i));
771 }
772 }
773
774 if (opJavaCall->_info) do_info(opJavaCall->_info);
775 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
776 opJavaCall->is_method_handle_invoke()) {
777 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
778 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
779 }
780 do_call();
781 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
782
783 break;
784 }
785
786
787 // LIR_OpRTCall
788 case lir_rtcall: {
789 assert(op->as_OpRTCall() != NULL, "must be");
790 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
791
792 // only visit register parameters
793 int n = opRTCall->_arguments->length();
794 for (int i = 0; i < n; i++) {
795 if (!opRTCall->_arguments->at(i)->is_pointer()) {
796 do_input(*opRTCall->_arguments->adr_at(i));
797 }
798 }
799 if (opRTCall->_info) do_info(opRTCall->_info);
800 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
801 do_call();
802 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
803
804 break;
805 }
806
807
808 // LIR_OpArrayCopy
809 case lir_arraycopy: {
810 assert(op->as_OpArrayCopy() != NULL, "must be");
811 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
812
813 assert(opArrayCopy->_result->is_illegal(), "unused");
814 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
815 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
816 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
817 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
818 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
819 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
820 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
821
822 // the implementation of arraycopy always has a call into the runtime
823 do_call();
824
825 break;
826 }
827
828
829 // LIR_OpUpdateCRC32
830 case lir_updatecrc32: {
831 assert(op->as_OpUpdateCRC32() != NULL, "must be");
832 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
833
834 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
835 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
836 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
837 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
838
839 break;
840 }
841
842
843 // LIR_OpLock
844 case lir_lock:
845 case lir_unlock: {
846 assert(op->as_OpLock() != NULL, "must be");
847 LIR_OpLock* opLock = (LIR_OpLock*)op;
848
849 if (opLock->_info) do_info(opLock->_info);
850
851 // TODO: check if these operands really have to be temp
852 // (or if input is sufficient). This may have influence on the oop map!
853 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
854 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
855 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
856
857 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
858 assert(opLock->_result->is_illegal(), "unused");
859
860 do_stub(opLock->_stub);
861
862 break;
863 }
864
865
866 // LIR_OpDelay
867 case lir_delay_slot: {
868 assert(op->as_OpDelay() != NULL, "must be");
869 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
870
871 visit(opDelay->delay_op());
872 break;
873 }
874
875 // LIR_OpTypeCheck
876 case lir_instanceof:
877 case lir_checkcast:
878 case lir_store_check: {
879 assert(op->as_OpTypeCheck() != NULL, "must be");
880 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
881
882 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
883 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
884 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
885 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
886 do_temp(opTypeCheck->_object);
887 }
888 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
889 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
890 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
891 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
892 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
893 do_stub(opTypeCheck->_stub);
894 break;
895 }
896
897 // LIR_OpCompareAndSwap
898 case lir_cas_long:
899 case lir_cas_obj:
900 case lir_cas_int: {
901 assert(op->as_OpCompareAndSwap() != NULL, "must be");
902 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
903
904 assert(opCompareAndSwap->_addr->is_valid(), "used");
905 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
906 assert(opCompareAndSwap->_new_value->is_valid(), "used");
907 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
908 do_input(opCompareAndSwap->_addr);
909 do_temp(opCompareAndSwap->_addr);
910 do_input(opCompareAndSwap->_cmp_value);
911 do_temp(opCompareAndSwap->_cmp_value);
912 do_input(opCompareAndSwap->_new_value);
913 do_temp(opCompareAndSwap->_new_value);
914 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
915 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
916 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
917
918 break;
919 }
920
921
922 // LIR_OpAllocArray;
923 case lir_alloc_array: {
924 assert(op->as_OpAllocArray() != NULL, "must be");
925 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
926
927 if (opAllocArray->_info) do_info(opAllocArray->_info);
928 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
929 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
930 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
931 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
932 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
933 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
934 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
935 do_stub(opAllocArray->_stub);
936 break;
937 }
938
939 // LIR_OpProfileCall:
940 case lir_profile_call: {
941 assert(op->as_OpProfileCall() != NULL, "must be");
942 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
943
944 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
945 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
946 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
947 break;
948 }
949
950 // LIR_OpProfileType:
951 case lir_profile_type: {
952 assert(op->as_OpProfileType() != NULL, "must be");
953 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
954
955 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
956 do_input(opProfileType->_obj);
957 do_temp(opProfileType->_tmp);
958 break;
959 }
960 default:
961 ShouldNotReachHere();
962 }
963 }
964
965
966 void LIR_OpVisitState::do_stub(CodeStub* stub) {
967 if (stub != NULL) {
968 stub->visit(this);
969 }
970 }
971
972 XHandlers* LIR_OpVisitState::all_xhandler() {
973 XHandlers* result = NULL;
974
975 int i;
976 for (i = 0; i < info_count(); i++) {
977 if (info_at(i)->exception_handlers() != NULL) {
978 result = info_at(i)->exception_handlers();
979 break;
980 }
981 }
982
983 #ifdef ASSERT
984 for (i = 0; i < info_count(); i++) {
985 assert(info_at(i)->exception_handlers() == NULL ||
986 info_at(i)->exception_handlers() == result,
987 "only one xhandler list allowed per LIR-operation");
988 }
989 #endif
990
991 if (result != NULL) {
992 return result;
993 } else {
994 return new XHandlers();
995 }
996
997 return result;
998 }
999
1000
1001 #ifdef ASSERT
1002 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1003 visit(op);
1004
1005 return opr_count(inputMode) == 0 &&
1006 opr_count(outputMode) == 0 &&
1007 opr_count(tempMode) == 0 &&
1008 info_count() == 0 &&
1009 !has_call() &&
1010 !has_slow_case();
1011 }
1012 #endif
1013
1014 //---------------------------------------------------
1015
1016
1017 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1018 masm->emit_call(this);
1019 }
1020
1021 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1022 masm->emit_rtcall(this);
1023 }
1024
1025 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1026 masm->emit_opLabel(this);
1027 }
1028
1029 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1030 masm->emit_arraycopy(this);
1031 masm->append_code_stub(stub());
1032 }
1033
1034 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1035 masm->emit_updatecrc32(this);
1036 }
1037
1038 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1039 masm->emit_op0(this);
1040 }
1041
1042 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1043 masm->emit_op1(this);
1044 }
1045
1046 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1047 masm->emit_alloc_obj(this);
1048 masm->append_code_stub(stub());
1049 }
1050
1051 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1052 masm->emit_opBranch(this);
1053 if (stub()) {
1054 masm->append_code_stub(stub());
1055 }
1056 }
1057
1058 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1059 masm->emit_opConvert(this);
1060 if (stub() != NULL) {
1061 masm->append_code_stub(stub());
1062 }
1063 }
1064
1065 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1066 masm->emit_op2(this);
1067 }
1068
1069 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1070 masm->emit_alloc_array(this);
1071 masm->append_code_stub(stub());
1072 }
1073
1074 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1075 masm->emit_opTypeCheck(this);
1076 if (stub()) {
1077 masm->append_code_stub(stub());
1078 }
1079 }
1080
1081 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1082 masm->emit_compare_and_swap(this);
1083 }
1084
1085 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1086 masm->emit_op3(this);
1087 }
1088
1089 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1090 masm->emit_lock(this);
1091 if (stub()) {
1092 masm->append_code_stub(stub());
1093 }
1094 }
1095
1096 #ifdef ASSERT
1097 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1098 masm->emit_assert(this);
1099 }
1100 #endif
1101
1102 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1103 masm->emit_delay(this);
1104 }
1105
1106 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1107 masm->emit_profile_call(this);
1108 }
1109
1110 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1111 masm->emit_profile_type(this);
1112 }
1113
1114 // LIR_List
1115 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1116 : _operations(8)
1117 , _compilation(compilation)
1118 #ifndef PRODUCT
1119 , _block(block)
1120 #endif
1121 #ifdef ASSERT
1122 , _file(NULL)
1123 , _line(0)
1124 #endif
1125 { }
1126
1127
1128 #ifdef ASSERT
1129 void LIR_List::set_file_and_line(const char * file, int line) {
1130 const char * f = strrchr(file, '/');
1131 if (f == NULL) f = strrchr(file, '\\');
1132 if (f == NULL) {
1133 f = file;
1134 } else {
1135 f++;
1136 }
1137 _file = f;
1138 _line = line;
1139 }
1140 #endif
1141
1142
1143 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1144 assert(this == buffer->lir_list(), "wrong lir list");
1145 const int n = _operations.length();
1146
1147 if (buffer->number_of_ops() > 0) {
1148 // increase size of instructions list
1149 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1150 // insert ops from buffer into instructions list
1151 int op_index = buffer->number_of_ops() - 1;
1152 int ip_index = buffer->number_of_insertion_points() - 1;
1153 int from_index = n - 1;
1154 int to_index = _operations.length() - 1;
1155 for (; ip_index >= 0; ip_index --) {
1156 int index = buffer->index_at(ip_index);
1157 // make room after insertion point
1158 while (index < from_index) {
1159 _operations.at_put(to_index --, _operations.at(from_index --));
1160 }
1161 // insert ops from buffer
1162 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1163 _operations.at_put(to_index --, buffer->op_at(op_index --));
1164 }
1165 }
1166 }
1167
1168 buffer->finish();
1169 }
1170
1171
1172 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1173 assert(reg->type() == T_OBJECT, "bad reg");
1174 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1175 }
1176
1177 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1178 assert(reg->type() == T_METADATA, "bad reg");
1179 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1180 }
1181
1182 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1183 append(new LIR_Op1(
1184 lir_move,
1185 LIR_OprFact::address(addr),
1186 src,
1187 addr->type(),
1188 patch_code,
1189 info));
1190 }
1191
1192
1193 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1194 append(new LIR_Op1(
1195 lir_move,
1196 LIR_OprFact::address(address),
1197 dst,
1198 address->type(),
1199 patch_code,
1200 info, lir_move_volatile));
1201 }
1202
1203 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1204 append(new LIR_Op1(
1205 lir_move,
1206 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1207 dst,
1208 type,
1209 patch_code,
1210 info, lir_move_volatile));
1211 }
1212
1213
1214 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1215 append(new LIR_Op1(
1216 lir_move,
1217 LIR_OprFact::intConst(v),
1218 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1219 type,
1220 patch_code,
1221 info));
1222 }
1223
1224
1225 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1226 append(new LIR_Op1(
1227 lir_move,
1228 LIR_OprFact::oopConst(o),
1229 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1230 type,
1231 patch_code,
1232 info));
1233 }
1234
1235
1236 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1237 append(new LIR_Op1(
1238 lir_move,
1239 src,
1240 LIR_OprFact::address(addr),
1241 addr->type(),
1242 patch_code,
1243 info));
1244 }
1245
1246
1247 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1248 append(new LIR_Op1(
1249 lir_move,
1250 src,
1251 LIR_OprFact::address(addr),
1252 addr->type(),
1253 patch_code,
1254 info,
1255 lir_move_volatile));
1256 }
1257
1258 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1259 append(new LIR_Op1(
1260 lir_move,
1261 src,
1262 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1263 type,
1264 patch_code,
1265 info, lir_move_volatile));
1266 }
1267
1268
1269 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1270 append(new LIR_Op3(
1271 lir_idiv,
1272 left,
1273 right,
1274 tmp,
1275 res,
1276 info));
1277 }
1278
1279
1280 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1281 append(new LIR_Op3(
1282 lir_idiv,
1283 left,
1284 LIR_OprFact::intConst(right),
1285 tmp,
1286 res,
1287 info));
1288 }
1289
1290
1291 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1292 append(new LIR_Op3(
1293 lir_irem,
1294 left,
1295 right,
1296 tmp,
1297 res,
1298 info));
1299 }
1300
1301
1302 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1303 append(new LIR_Op3(
1304 lir_irem,
1305 left,
1306 LIR_OprFact::intConst(right),
1307 tmp,
1308 res,
1309 info));
1310 }
1311
1312
1313 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1314 append(new LIR_Op2(
1315 lir_cmp,
1316 condition,
1317 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1318 LIR_OprFact::intConst(c),
1319 info));
1320 }
1321
1322
1323 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1324 append(new LIR_Op2(
1325 lir_cmp,
1326 condition,
1327 reg,
1328 LIR_OprFact::address(addr),
1329 info));
1330 }
1331
1332 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1333 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1334 append(new LIR_OpAllocObj(
1335 klass,
1336 dst,
1337 t1,
1338 t2,
1339 t3,
1340 t4,
1341 header_size,
1342 object_size,
1343 init_check,
1344 stub));
1345 }
1346
1347 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1348 append(new LIR_OpAllocArray(
1349 klass,
1350 len,
1351 dst,
1352 t1,
1353 t2,
1354 t3,
1355 t4,
1356 type,
1357 stub));
1358 }
1359
1360 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1361 append(new LIR_Op2(
1362 lir_shl,
1363 value,
1364 count,
1365 dst,
1366 tmp));
1367 }
1368
1369 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1370 append(new LIR_Op2(
1371 lir_shr,
1372 value,
1373 count,
1374 dst,
1375 tmp));
1376 }
1377
1378
1379 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1380 append(new LIR_Op2(
1381 lir_ushr,
1382 value,
1383 count,
1384 dst,
1385 tmp));
1386 }
1387
1388 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1389 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1390 left,
1391 right,
1392 dst));
1393 }
1394
1395 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1396 append(new LIR_OpLock(
1397 lir_lock,
1398 hdr,
1399 obj,
1400 lock,
1401 scratch,
1402 stub,
1403 info));
1404 }
1405
1406 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1407 append(new LIR_OpLock(
1408 lir_unlock,
1409 hdr,
1410 obj,
1411 lock,
1412 scratch,
1413 stub,
1414 NULL));
1415 }
1416
1417
1418 void check_LIR() {
1419 // cannot do the proper checking as PRODUCT and other modes return different results
1420 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1421 }
1422
1423
1424
1425 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1426 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1427 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1428 ciMethod* profiled_method, int profiled_bci) {
1429 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1430 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1431 if (profiled_method != NULL) {
1432 c->set_profiled_method(profiled_method);
1433 c->set_profiled_bci(profiled_bci);
1434 c->set_should_profile(true);
1435 }
1436 append(c);
1437 }
1438
1439 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1440 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1441 if (profiled_method != NULL) {
1442 c->set_profiled_method(profiled_method);
1443 c->set_profiled_bci(profiled_bci);
1444 c->set_should_profile(true);
1445 }
1446 append(c);
1447 }
1448
1449
1450 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1451 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1452 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1453 if (profiled_method != NULL) {
1454 c->set_profiled_method(profiled_method);
1455 c->set_profiled_bci(profiled_bci);
1456 c->set_should_profile(true);
1457 }
1458 append(c);
1459 }
1460
1461
1462 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1463 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1464 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1465 }
1466
1467 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1468 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1469 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1470 }
1471
1472 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1473 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1474 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1475 }
1476
1477
1478 #ifdef PRODUCT
1479
1480 void print_LIR(BlockList* blocks) {
1481 }
1482
1483 #else
1484 // LIR_OprDesc
1485 void LIR_OprDesc::print() const {
1486 print(tty);
1487 }
1488
1489 void LIR_OprDesc::print(outputStream* out) const {
1490 if (is_illegal()) {
1491 return;
1492 }
1493
1494 out->print("[");
1495 if (is_pointer()) {
1496 pointer()->print_value_on(out);
1497 } else if (is_single_stack()) {
1498 out->print("stack:%d", single_stack_ix());
1499 } else if (is_double_stack()) {
1500 out->print("dbl_stack:%d",double_stack_ix());
1501 } else if (is_virtual()) {
1502 out->print("R%d", vreg_number());
1503 } else if (is_single_cpu()) {
1504 out->print("%s", as_register()->name());
1505 } else if (is_double_cpu()) {
1506 out->print("%s", as_register_hi()->name());
1507 out->print("%s", as_register_lo()->name());
1508 #if defined(X86)
1509 } else if (is_single_xmm()) {
1510 out->print("%s", as_xmm_float_reg()->name());
1511 } else if (is_double_xmm()) {
1512 out->print("%s", as_xmm_double_reg()->name());
1513 } else if (is_single_fpu()) {
1514 out->print("fpu%d", fpu_regnr());
1515 } else if (is_double_fpu()) {
1516 out->print("fpu%d", fpu_regnrLo());
1517 #elif defined(AARCH64)
1518 } else if (is_single_fpu()) {
1519 out->print("fpu%d", fpu_regnr());
1520 } else if (is_double_fpu()) {
1521 out->print("fpu%d", fpu_regnrLo());
1522 #elif defined(ARM)
1523 } else if (is_single_fpu()) {
1524 out->print("s%d", fpu_regnr());
1525 } else if (is_double_fpu()) {
1526 out->print("d%d", fpu_regnrLo() >> 1);
1527 #else
1528 } else if (is_single_fpu()) {
1529 out->print("%s", as_float_reg()->name());
1530 } else if (is_double_fpu()) {
1531 out->print("%s", as_double_reg()->name());
1532 #endif
1533
1534 } else if (is_illegal()) {
1535 out->print("-");
1536 } else {
1537 out->print("Unknown Operand");
1538 }
1539 if (!is_illegal()) {
1540 out->print("|%c", type_char());
1541 }
1542 if (is_register() && is_last_use()) {
1543 out->print("(last_use)");
1544 }
1545 out->print("]");
1546 }
1547
1548
1549 // LIR_Address
1550 void LIR_Const::print_value_on(outputStream* out) const {
1551 switch (type()) {
1552 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1553 case T_INT: out->print("int:%d", as_jint()); break;
1554 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1555 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1556 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1557 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break;
1558 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1559 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1560 }
1561 }
1562
1563 // LIR_Address
1564 void LIR_Address::print_value_on(outputStream* out) const {
1565 out->print("Base:"); _base->print(out);
1566 if (!_index->is_illegal()) {
1567 out->print(" Index:"); _index->print(out);
1568 switch (scale()) {
1569 case times_1: break;
1570 case times_2: out->print(" * 2"); break;
1571 case times_4: out->print(" * 4"); break;
1572 case times_8: out->print(" * 8"); break;
1573 }
1574 }
1575 out->print(" Disp: " INTX_FORMAT, _disp);
1576 }
1577
1578 // debug output of block header without InstructionPrinter
1579 // (because phi functions are not necessary for LIR)
1580 static void print_block(BlockBegin* x) {
1581 // print block id
1582 BlockEnd* end = x->end();
1583 tty->print("B%d ", x->block_id());
1584
1585 // print flags
1586 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1587 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1588 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1589 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1590 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1591 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1592 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1593
1594 // print block bci range
1595 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1596
1597 // print predecessors and successors
1598 if (x->number_of_preds() > 0) {
1599 tty->print("preds: ");
1600 for (int i = 0; i < x->number_of_preds(); i ++) {
1601 tty->print("B%d ", x->pred_at(i)->block_id());
1602 }
1603 }
1604
1605 if (x->number_of_sux() > 0) {
1606 tty->print("sux: ");
1607 for (int i = 0; i < x->number_of_sux(); i ++) {
1608 tty->print("B%d ", x->sux_at(i)->block_id());
1609 }
1610 }
1611
1612 // print exception handlers
1613 if (x->number_of_exception_handlers() > 0) {
1614 tty->print("xhandler: ");
1615 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1616 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1617 }
1618 }
1619
1620 tty->cr();
1621 }
1622
1623 void print_LIR(BlockList* blocks) {
1624 tty->print_cr("LIR:");
1625 int i;
1626 for (i = 0; i < blocks->length(); i++) {
1627 BlockBegin* bb = blocks->at(i);
1628 print_block(bb);
1629 tty->print("__id_Instruction___________________________________________"); tty->cr();
1630 bb->lir()->print_instructions();
1631 }
1632 }
1633
1634 void LIR_List::print_instructions() {
1635 for (int i = 0; i < _operations.length(); i++) {
1636 _operations.at(i)->print(); tty->cr();
1637 }
1638 tty->cr();
1639 }
1640
1641 // LIR_Ops printing routines
1642 // LIR_Op
1643 void LIR_Op::print_on(outputStream* out) const {
1644 if (id() != -1 || PrintCFGToFile) {
1645 out->print("%4d ", id());
1646 } else {
1647 out->print(" ");
1648 }
1649 out->print("%s ", name());
1650 print_instr(out);
1651 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1652 #ifdef ASSERT
1653 if (Verbose && _file != NULL) {
1654 out->print(" (%s:%d)", _file, _line);
1655 }
1656 #endif
1657 }
1658
1659 const char * LIR_Op::name() const {
1660 const char* s = NULL;
1661 switch(code()) {
1662 // LIR_Op0
1663 case lir_membar: s = "membar"; break;
1664 case lir_membar_acquire: s = "membar_acquire"; break;
1665 case lir_membar_release: s = "membar_release"; break;
1666 case lir_membar_loadload: s = "membar_loadload"; break;
1667 case lir_membar_storestore: s = "membar_storestore"; break;
1668 case lir_membar_loadstore: s = "membar_loadstore"; break;
1669 case lir_membar_storeload: s = "membar_storeload"; break;
1670 case lir_word_align: s = "word_align"; break;
1671 case lir_label: s = "label"; break;
1672 case lir_nop: s = "nop"; break;
1673 case lir_on_spin_wait: s = "on_spin_wait"; break;
1674 case lir_backwardbranch_target: s = "backbranch"; break;
1675 case lir_std_entry: s = "std_entry"; break;
1676 case lir_osr_entry: s = "osr_entry"; break;
1677 case lir_build_frame: s = "build_frm"; break;
1678 case lir_fpop_raw: s = "fpop_raw"; break;
1679 case lir_24bit_FPU: s = "24bit_FPU"; break;
1680 case lir_reset_FPU: s = "reset_FPU"; break;
1681 case lir_breakpoint: s = "breakpoint"; break;
1682 case lir_get_thread: s = "get_thread"; break;
1683 // LIR_Op1
1684 case lir_fxch: s = "fxch"; break;
1685 case lir_fld: s = "fld"; break;
1686 case lir_ffree: s = "ffree"; break;
1687 case lir_push: s = "push"; break;
1688 case lir_pop: s = "pop"; break;
1689 case lir_null_check: s = "null_check"; break;
1690 case lir_return: s = "return"; break;
1691 case lir_safepoint: s = "safepoint"; break;
1692 case lir_neg: s = "neg"; break;
1693 case lir_leal: s = "leal"; break;
1694 case lir_branch: s = "branch"; break;
1695 case lir_cond_float_branch: s = "flt_cond_br"; break;
1696 case lir_move: s = "move"; break;
1697 case lir_roundfp: s = "roundfp"; break;
1698 case lir_rtcall: s = "rtcall"; break;
1699 case lir_throw: s = "throw"; break;
1700 case lir_unwind: s = "unwind"; break;
1701 case lir_convert: s = "convert"; break;
1702 case lir_alloc_object: s = "alloc_obj"; break;
1703 case lir_monaddr: s = "mon_addr"; break;
1704 case lir_pack64: s = "pack64"; break;
1705 case lir_unpack64: s = "unpack64"; break;
1706 // LIR_Op2
1707 case lir_cmp: s = "cmp"; break;
1708 case lir_cmp_l2i: s = "cmp_l2i"; break;
1709 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1710 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1711 case lir_cmove: s = "cmove"; break;
1712 case lir_add: s = "add"; break;
1713 case lir_sub: s = "sub"; break;
1714 case lir_mul: s = "mul"; break;
1715 case lir_mul_strictfp: s = "mul_strictfp"; break;
1716 case lir_div: s = "div"; break;
1717 case lir_div_strictfp: s = "div_strictfp"; break;
1718 case lir_rem: s = "rem"; break;
1719 case lir_abs: s = "abs"; break;
1720 case lir_sqrt: s = "sqrt"; break;
1721 case lir_logic_and: s = "logic_and"; break;
1722 case lir_logic_or: s = "logic_or"; break;
1723 case lir_logic_xor: s = "logic_xor"; break;
1724 case lir_shl: s = "shift_left"; break;
1725 case lir_shr: s = "shift_right"; break;
1726 case lir_ushr: s = "ushift_right"; break;
1727 case lir_alloc_array: s = "alloc_array"; break;
1728 case lir_xadd: s = "xadd"; break;
1729 case lir_xchg: s = "xchg"; break;
1730 // LIR_Op3
1731 case lir_idiv: s = "idiv"; break;
1732 case lir_irem: s = "irem"; break;
1733 // LIR_OpJavaCall
1734 case lir_static_call: s = "static"; break;
1735 case lir_optvirtual_call: s = "optvirtual"; break;
1736 case lir_icvirtual_call: s = "icvirtual"; break;
1737 case lir_virtual_call: s = "virtual"; break;
1738 case lir_dynamic_call: s = "dynamic"; break;
1739 // LIR_OpArrayCopy
1740 case lir_arraycopy: s = "arraycopy"; break;
1741 // LIR_OpUpdateCRC32
1742 case lir_updatecrc32: s = "updatecrc32"; break;
1743 // LIR_OpLock
1744 case lir_lock: s = "lock"; break;
1745 case lir_unlock: s = "unlock"; break;
1746 // LIR_OpDelay
1747 case lir_delay_slot: s = "delay"; break;
1748 // LIR_OpTypeCheck
1749 case lir_instanceof: s = "instanceof"; break;
1750 case lir_checkcast: s = "checkcast"; break;
1751 case lir_store_check: s = "store_check"; break;
1752 // LIR_OpCompareAndSwap
1753 case lir_cas_long: s = "cas_long"; break;
1754 case lir_cas_obj: s = "cas_obj"; break;
1755 case lir_cas_int: s = "cas_int"; break;
1756 // LIR_OpProfileCall
1757 case lir_profile_call: s = "profile_call"; break;
1758 // LIR_OpProfileType
1759 case lir_profile_type: s = "profile_type"; break;
1760 // LIR_OpAssert
1761 #ifdef ASSERT
1762 case lir_assert: s = "assert"; break;
1763 #endif
1764 case lir_none: ShouldNotReachHere();break;
1765 default: s = "illegal_op"; break;
1766 }
1767 return s;
1768 }
1769
1770 // LIR_OpJavaCall
1771 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1772 out->print("call: ");
1773 out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
1774 if (receiver()->is_valid()) {
1775 out->print(" [recv: "); receiver()->print(out); out->print("]");
1776 }
1777 if (result_opr()->is_valid()) {
1778 out->print(" [result: "); result_opr()->print(out); out->print("]");
1779 }
1780 }
1781
1782 // LIR_OpLabel
1783 void LIR_OpLabel::print_instr(outputStream* out) const {
1784 out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
1785 }
1786
1787 // LIR_OpArrayCopy
1788 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1789 src()->print(out); out->print(" ");
1790 src_pos()->print(out); out->print(" ");
1791 dst()->print(out); out->print(" ");
1792 dst_pos()->print(out); out->print(" ");
1793 length()->print(out); out->print(" ");
1794 tmp()->print(out); out->print(" ");
1795 }
1796
1797 // LIR_OpUpdateCRC32
1798 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
1799 crc()->print(out); out->print(" ");
1800 val()->print(out); out->print(" ");
1801 result_opr()->print(out); out->print(" ");
1802 }
1803
1804 // LIR_OpCompareAndSwap
1805 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1806 addr()->print(out); out->print(" ");
1807 cmp_value()->print(out); out->print(" ");
1808 new_value()->print(out); out->print(" ");
1809 tmp1()->print(out); out->print(" ");
1810 tmp2()->print(out); out->print(" ");
1811
1812 }
1813
1814 // LIR_Op0
1815 void LIR_Op0::print_instr(outputStream* out) const {
1816 result_opr()->print(out);
1817 }
1818
1819 // LIR_Op1
1820 const char * LIR_Op1::name() const {
1821 if (code() == lir_move) {
1822 switch (move_kind()) {
1823 case lir_move_normal:
1824 return "move";
1825 case lir_move_unaligned:
1826 return "unaligned move";
1827 case lir_move_volatile:
1828 return "volatile_move";
1829 case lir_move_wide:
1830 return "wide_move";
1831 default:
1832 ShouldNotReachHere();
1833 return "illegal_op";
1834 }
1835 } else {
1836 return LIR_Op::name();
1837 }
1838 }
1839
1840
1841 void LIR_Op1::print_instr(outputStream* out) const {
1842 _opr->print(out); out->print(" ");
1843 result_opr()->print(out); out->print(" ");
1844 print_patch_code(out, patch_code());
1845 }
1846
1847
1848 // LIR_Op1
1849 void LIR_OpRTCall::print_instr(outputStream* out) const {
1850 intx a = (intx)addr();
1851 out->print("%s", Runtime1::name_for_address(addr()));
1852 out->print(" ");
1853 tmp()->print(out);
1854 }
1855
1856 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1857 switch(code) {
1858 case lir_patch_none: break;
1859 case lir_patch_low: out->print("[patch_low]"); break;
1860 case lir_patch_high: out->print("[patch_high]"); break;
1861 case lir_patch_normal: out->print("[patch_normal]"); break;
1862 default: ShouldNotReachHere();
1863 }
1864 }
1865
1866 // LIR_OpBranch
1867 void LIR_OpBranch::print_instr(outputStream* out) const {
1868 print_condition(out, cond()); out->print(" ");
1869 if (block() != NULL) {
1870 out->print("[B%d] ", block()->block_id());
1871 } else if (stub() != NULL) {
1872 out->print("[");
1873 stub()->print_name(out);
1874 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
1875 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1876 } else {
1877 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
1878 }
1879 if (ublock() != NULL) {
1880 out->print("unordered: [B%d] ", ublock()->block_id());
1881 }
1882 }
1883
1884 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1885 switch(cond) {
1886 case lir_cond_equal: out->print("[EQ]"); break;
1887 case lir_cond_notEqual: out->print("[NE]"); break;
1888 case lir_cond_less: out->print("[LT]"); break;
1889 case lir_cond_lessEqual: out->print("[LE]"); break;
1890 case lir_cond_greaterEqual: out->print("[GE]"); break;
1891 case lir_cond_greater: out->print("[GT]"); break;
1892 case lir_cond_belowEqual: out->print("[BE]"); break;
1893 case lir_cond_aboveEqual: out->print("[AE]"); break;
1894 case lir_cond_always: out->print("[AL]"); break;
1895 default: out->print("[%d]",cond); break;
1896 }
1897 }
1898
1899 // LIR_OpConvert
1900 void LIR_OpConvert::print_instr(outputStream* out) const {
1901 print_bytecode(out, bytecode());
1902 in_opr()->print(out); out->print(" ");
1903 result_opr()->print(out); out->print(" ");
1904 #ifdef PPC32
1905 if(tmp1()->is_valid()) {
1906 tmp1()->print(out); out->print(" ");
1907 tmp2()->print(out); out->print(" ");
1908 }
1909 #endif
1910 }
1911
1912 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1913 switch(code) {
1914 case Bytecodes::_d2f: out->print("[d2f] "); break;
1915 case Bytecodes::_d2i: out->print("[d2i] "); break;
1916 case Bytecodes::_d2l: out->print("[d2l] "); break;
1917 case Bytecodes::_f2d: out->print("[f2d] "); break;
1918 case Bytecodes::_f2i: out->print("[f2i] "); break;
1919 case Bytecodes::_f2l: out->print("[f2l] "); break;
1920 case Bytecodes::_i2b: out->print("[i2b] "); break;
1921 case Bytecodes::_i2c: out->print("[i2c] "); break;
1922 case Bytecodes::_i2d: out->print("[i2d] "); break;
1923 case Bytecodes::_i2f: out->print("[i2f] "); break;
1924 case Bytecodes::_i2l: out->print("[i2l] "); break;
1925 case Bytecodes::_i2s: out->print("[i2s] "); break;
1926 case Bytecodes::_l2i: out->print("[l2i] "); break;
1927 case Bytecodes::_l2f: out->print("[l2f] "); break;
1928 case Bytecodes::_l2d: out->print("[l2d] "); break;
1929 default:
1930 out->print("[?%d]",code);
1931 break;
1932 }
1933 }
1934
1935 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1936 klass()->print(out); out->print(" ");
1937 obj()->print(out); out->print(" ");
1938 tmp1()->print(out); out->print(" ");
1939 tmp2()->print(out); out->print(" ");
1940 tmp3()->print(out); out->print(" ");
1941 tmp4()->print(out); out->print(" ");
1942 out->print("[hdr:%d]", header_size()); out->print(" ");
1943 out->print("[obj:%d]", object_size()); out->print(" ");
1944 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
1945 }
1946
1947 void LIR_OpRoundFP::print_instr(outputStream* out) const {
1948 _opr->print(out); out->print(" ");
1949 tmp()->print(out); out->print(" ");
1950 result_opr()->print(out); out->print(" ");
1951 }
1952
1953 // LIR_Op2
1954 void LIR_Op2::print_instr(outputStream* out) const {
1955 if (code() == lir_cmove || code() == lir_cmp) {
1956 print_condition(out, condition()); out->print(" ");
1957 }
1958 in_opr1()->print(out); out->print(" ");
1959 in_opr2()->print(out); out->print(" ");
1960 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
1961 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
1962 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
1963 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
1964 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
1965 result_opr()->print(out);
1966 }
1967
1968 void LIR_OpAllocArray::print_instr(outputStream* out) const {
1969 klass()->print(out); out->print(" ");
1970 len()->print(out); out->print(" ");
1971 obj()->print(out); out->print(" ");
1972 tmp1()->print(out); out->print(" ");
1973 tmp2()->print(out); out->print(" ");
1974 tmp3()->print(out); out->print(" ");
1975 tmp4()->print(out); out->print(" ");
1976 out->print("[type:0x%x]", type()); out->print(" ");
1977 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
1978 }
1979
1980
1981 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
1982 object()->print(out); out->print(" ");
1983 if (code() == lir_store_check) {
1984 array()->print(out); out->print(" ");
1985 }
1986 if (code() != lir_store_check) {
1987 klass()->print_name_on(out); out->print(" ");
1988 if (fast_check()) out->print("fast_check ");
1989 }
1990 tmp1()->print(out); out->print(" ");
1991 tmp2()->print(out); out->print(" ");
1992 tmp3()->print(out); out->print(" ");
1993 result_opr()->print(out); out->print(" ");
1994 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
1995 }
1996
1997
1998 // LIR_Op3
1999 void LIR_Op3::print_instr(outputStream* out) const {
2000 in_opr1()->print(out); out->print(" ");
2001 in_opr2()->print(out); out->print(" ");
2002 in_opr3()->print(out); out->print(" ");
2003 result_opr()->print(out);
2004 }
2005
2006
2007 void LIR_OpLock::print_instr(outputStream* out) const {
2008 hdr_opr()->print(out); out->print(" ");
2009 obj_opr()->print(out); out->print(" ");
2010 lock_opr()->print(out); out->print(" ");
2011 if (_scratch->is_valid()) {
2012 _scratch->print(out); out->print(" ");
2013 }
2014 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2015 }
2016
2017 #ifdef ASSERT
2018 void LIR_OpAssert::print_instr(outputStream* out) const {
2019 print_condition(out, condition()); out->print(" ");
2020 in_opr1()->print(out); out->print(" ");
2021 in_opr2()->print(out); out->print(", \"");
2022 out->print("%s", msg()); out->print("\"");
2023 }
2024 #endif
2025
2026
2027 void LIR_OpDelay::print_instr(outputStream* out) const {
2028 _op->print_on(out);
2029 }
2030
2031
2032 // LIR_OpProfileCall
2033 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2034 profiled_method()->name()->print_symbol_on(out);
2035 out->print(".");
2036 profiled_method()->holder()->name()->print_symbol_on(out);
2037 out->print(" @ %d ", profiled_bci());
2038 mdo()->print(out); out->print(" ");
2039 recv()->print(out); out->print(" ");
2040 tmp1()->print(out); out->print(" ");
2041 }
2042
2043 // LIR_OpProfileType
2044 void LIR_OpProfileType::print_instr(outputStream* out) const {
2045 out->print("exact = ");
2046 if (exact_klass() == NULL) {
2047 out->print("unknown");
2048 } else {
2049 exact_klass()->print_name_on(out);
2050 }
2051 out->print(" current = "); ciTypeEntries::print_ciklass(out, current_klass());
2052 out->print(" ");
2053 mdp()->print(out); out->print(" ");
2054 obj()->print(out); out->print(" ");
2055 tmp()->print(out); out->print(" ");
2056 }
2057
2058 #endif // PRODUCT
2059
2060 // Implementation of LIR_InsertionBuffer
2061
2062 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2063 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2064
2065 int i = number_of_insertion_points() - 1;
2066 if (i < 0 || index_at(i) < index) {
2067 append_new(index, 1);
2068 } else {
2069 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2070 assert(count_at(i) > 0, "check");
2071 set_count_at(i, count_at(i) + 1);
2072 }
2073 _ops.push(op);
2074
2075 DEBUG_ONLY(verify());
2076 }
2077
2078 #ifdef ASSERT
2079 void LIR_InsertionBuffer::verify() {
2080 int sum = 0;
2081 int prev_idx = -1;
2082
2083 for (int i = 0; i < number_of_insertion_points(); i++) {
2084 assert(prev_idx < index_at(i), "index must be ordered ascending");
2085 sum += count_at(i);
2086 }
2087 assert(sum == number_of_ops(), "wrong total sum");
2088 }
2089 #endif