1 //
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   3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4 //
   5 // This code is free software; you can redistribute it and/or modify it
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   7 // published by the Free Software Foundation.
   8 //
   9 // This code is distributed in the hope that it will be useful, but WITHOUT
  10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12 // version 2 for more details (a copy is included in the LICENSE file that
  13 // accompanied this code).
  14 //
  15 // You should have received a copy of the GNU General Public License version
  16 // 2 along with this work; if not, write to the Free Software Foundation,
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  18 //
  19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20 // or visit www.oracle.com if you need additional information or have any
  21 // questions.
  22 //
  23 //
  24 
  25 // SPARC Architecture Description File
  26 
  27 //----------REGISTER DEFINITION BLOCK------------------------------------------
  28 // This information is used by the matcher and the register allocator to
  29 // describe individual registers and classes of registers within the target
  30 // archtecture.
  31 register %{
  32 //----------Architecture Description Register Definitions----------------------
  33 // General Registers
  34 // "reg_def"  name ( register save type, C convention save type,
  35 //                   ideal register type, encoding, vm name );
  36 // Register Save Types:
  37 //
  38 // NS  = No-Save:       The register allocator assumes that these registers
  39 //                      can be used without saving upon entry to the method, &
  40 //                      that they do not need to be saved at call sites.
  41 //
  42 // SOC = Save-On-Call:  The register allocator assumes that these registers
  43 //                      can be used without saving upon entry to the method,
  44 //                      but that they must be saved at call sites.
  45 //
  46 // SOE = Save-On-Entry: The register allocator assumes that these registers
  47 //                      must be saved before using them upon entry to the
  48 //                      method, but they do not need to be saved at call
  49 //                      sites.
  50 //
  51 // AS  = Always-Save:   The register allocator assumes that these registers
  52 //                      must be saved before using them upon entry to the
  53 //                      method, & that they must be saved at call sites.
  54 //
  55 // Ideal Register Type is used to determine how to save & restore a
  56 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  57 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
  58 //
  59 // The encoding number is the actual bit-pattern placed into the opcodes.
  60 
  61 
  62 // ----------------------------
  63 // Integer/Long Registers
  64 // ----------------------------
  65 
  66 // Need to expose the hi/lo aspect of 64-bit registers
  67 // This register set is used for both the 64-bit build and
  68 // the 32-bit build with 1-register longs.
  69 
  70 // Global Registers 0-7
  71 reg_def R_G0H( NS,  NS, Op_RegI,128, G0->as_VMReg()->next());
  72 reg_def R_G0 ( NS,  NS, Op_RegI,  0, G0->as_VMReg());
  73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
  74 reg_def R_G1 (SOC, SOC, Op_RegI,  1, G1->as_VMReg());
  75 reg_def R_G2H( NS,  NS, Op_RegI,130, G2->as_VMReg()->next());
  76 reg_def R_G2 ( NS,  NS, Op_RegI,  2, G2->as_VMReg());
  77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
  78 reg_def R_G3 (SOC, SOC, Op_RegI,  3, G3->as_VMReg());
  79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
  80 reg_def R_G4 (SOC, SOC, Op_RegI,  4, G4->as_VMReg());
  81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
  82 reg_def R_G5 (SOC, SOC, Op_RegI,  5, G5->as_VMReg());
  83 reg_def R_G6H( NS,  NS, Op_RegI,134, G6->as_VMReg()->next());
  84 reg_def R_G6 ( NS,  NS, Op_RegI,  6, G6->as_VMReg());
  85 reg_def R_G7H( NS,  NS, Op_RegI,135, G7->as_VMReg()->next());
  86 reg_def R_G7 ( NS,  NS, Op_RegI,  7, G7->as_VMReg());
  87 
  88 // Output Registers 0-7
  89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
  90 reg_def R_O0 (SOC, SOC, Op_RegI,  8, O0->as_VMReg());
  91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
  92 reg_def R_O1 (SOC, SOC, Op_RegI,  9, O1->as_VMReg());
  93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
  94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
  95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
  96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
  97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
  98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
  99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
 101 reg_def R_SPH( NS,  NS, Op_RegI,142, SP->as_VMReg()->next());
 102 reg_def R_SP ( NS,  NS, Op_RegI, 14, SP->as_VMReg());
 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
 105 
 106 // Local Registers 0-7
 107 reg_def R_L0H( NS,  NS, Op_RegI,144, L0->as_VMReg()->next());
 108 reg_def R_L0 ( NS,  NS, Op_RegI, 16, L0->as_VMReg());
 109 reg_def R_L1H( NS,  NS, Op_RegI,145, L1->as_VMReg()->next());
 110 reg_def R_L1 ( NS,  NS, Op_RegI, 17, L1->as_VMReg());
 111 reg_def R_L2H( NS,  NS, Op_RegI,146, L2->as_VMReg()->next());
 112 reg_def R_L2 ( NS,  NS, Op_RegI, 18, L2->as_VMReg());
 113 reg_def R_L3H( NS,  NS, Op_RegI,147, L3->as_VMReg()->next());
 114 reg_def R_L3 ( NS,  NS, Op_RegI, 19, L3->as_VMReg());
 115 reg_def R_L4H( NS,  NS, Op_RegI,148, L4->as_VMReg()->next());
 116 reg_def R_L4 ( NS,  NS, Op_RegI, 20, L4->as_VMReg());
 117 reg_def R_L5H( NS,  NS, Op_RegI,149, L5->as_VMReg()->next());
 118 reg_def R_L5 ( NS,  NS, Op_RegI, 21, L5->as_VMReg());
 119 reg_def R_L6H( NS,  NS, Op_RegI,150, L6->as_VMReg()->next());
 120 reg_def R_L6 ( NS,  NS, Op_RegI, 22, L6->as_VMReg());
 121 reg_def R_L7H( NS,  NS, Op_RegI,151, L7->as_VMReg()->next());
 122 reg_def R_L7 ( NS,  NS, Op_RegI, 23, L7->as_VMReg());
 123 
 124 // Input Registers 0-7
 125 reg_def R_I0H( NS,  NS, Op_RegI,152, I0->as_VMReg()->next());
 126 reg_def R_I0 ( NS,  NS, Op_RegI, 24, I0->as_VMReg());
 127 reg_def R_I1H( NS,  NS, Op_RegI,153, I1->as_VMReg()->next());
 128 reg_def R_I1 ( NS,  NS, Op_RegI, 25, I1->as_VMReg());
 129 reg_def R_I2H( NS,  NS, Op_RegI,154, I2->as_VMReg()->next());
 130 reg_def R_I2 ( NS,  NS, Op_RegI, 26, I2->as_VMReg());
 131 reg_def R_I3H( NS,  NS, Op_RegI,155, I3->as_VMReg()->next());
 132 reg_def R_I3 ( NS,  NS, Op_RegI, 27, I3->as_VMReg());
 133 reg_def R_I4H( NS,  NS, Op_RegI,156, I4->as_VMReg()->next());
 134 reg_def R_I4 ( NS,  NS, Op_RegI, 28, I4->as_VMReg());
 135 reg_def R_I5H( NS,  NS, Op_RegI,157, I5->as_VMReg()->next());
 136 reg_def R_I5 ( NS,  NS, Op_RegI, 29, I5->as_VMReg());
 137 reg_def R_FPH( NS,  NS, Op_RegI,158, FP->as_VMReg()->next());
 138 reg_def R_FP ( NS,  NS, Op_RegI, 30, FP->as_VMReg());
 139 reg_def R_I7H( NS,  NS, Op_RegI,159, I7->as_VMReg()->next());
 140 reg_def R_I7 ( NS,  NS, Op_RegI, 31, I7->as_VMReg());
 141 
 142 // ----------------------------
 143 // Float/Double Registers
 144 // ----------------------------
 145 
 146 // Float Registers
 147 reg_def R_F0 ( SOC, SOC, Op_RegF,  0, F0->as_VMReg());
 148 reg_def R_F1 ( SOC, SOC, Op_RegF,  1, F1->as_VMReg());
 149 reg_def R_F2 ( SOC, SOC, Op_RegF,  2, F2->as_VMReg());
 150 reg_def R_F3 ( SOC, SOC, Op_RegF,  3, F3->as_VMReg());
 151 reg_def R_F4 ( SOC, SOC, Op_RegF,  4, F4->as_VMReg());
 152 reg_def R_F5 ( SOC, SOC, Op_RegF,  5, F5->as_VMReg());
 153 reg_def R_F6 ( SOC, SOC, Op_RegF,  6, F6->as_VMReg());
 154 reg_def R_F7 ( SOC, SOC, Op_RegF,  7, F7->as_VMReg());
 155 reg_def R_F8 ( SOC, SOC, Op_RegF,  8, F8->as_VMReg());
 156 reg_def R_F9 ( SOC, SOC, Op_RegF,  9, F9->as_VMReg());
 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
 179 
 180 // Double Registers
 181 // The rules of ADL require that double registers be defined in pairs.
 182 // Each pair must be two 32-bit values, but not necessarily a pair of
 183 // single float registers.  In each pair, ADLC-assigned register numbers
 184 // must be adjacent, with the lower number even.  Finally, when the
 185 // CPU stores such a register pair to memory, the word associated with
 186 // the lower ADLC-assigned number must be stored to the lower address.
 187 
 188 // These definitions specify the actual bit encodings of the sparc
 189 // double fp register numbers.  FloatRegisterImpl in register_sparc.hpp
 190 // wants 0-63, so we have to convert every time we want to use fp regs
 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
 192 // 255 is a flag meaning "don't go here".
 193 // I believe we can't handle callee-save doubles D32 and up until
 194 // the place in the sparc stack crawler that asserts on the 255 is
 195 // fixed up.
 196 reg_def R_D32 (SOC, SOC, Op_RegD,  1, F32->as_VMReg());
 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
 198 reg_def R_D34 (SOC, SOC, Op_RegD,  3, F34->as_VMReg());
 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
 200 reg_def R_D36 (SOC, SOC, Op_RegD,  5, F36->as_VMReg());
 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
 202 reg_def R_D38 (SOC, SOC, Op_RegD,  7, F38->as_VMReg());
 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
 204 reg_def R_D40 (SOC, SOC, Op_RegD,  9, F40->as_VMReg());
 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
 228 
 229 
 230 // ----------------------------
 231 // Special Registers
 232 // Condition Codes Flag Registers
 233 // I tried to break out ICC and XCC but it's not very pretty.
 234 // Every Sparc instruction which defs/kills one also kills the other.
 235 // Hence every compare instruction which defs one kind of flags ends
 236 // up needing a kill of the other.
 237 reg_def CCR (SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());
 238 
 239 reg_def FCC0(SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());
 240 reg_def FCC1(SOC, SOC,  Op_RegFlags, 1, VMRegImpl::Bad());
 241 reg_def FCC2(SOC, SOC,  Op_RegFlags, 2, VMRegImpl::Bad());
 242 reg_def FCC3(SOC, SOC,  Op_RegFlags, 3, VMRegImpl::Bad());
 243 
 244 // ----------------------------
 245 // Specify the enum values for the registers.  These enums are only used by the
 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
 247 // for visibility to the rest of the vm. The order of this enum influences the
 248 // register allocator so having the freedom to set this order and not be stuck
 249 // with the order that is natural for the rest of the vm is worth it.
 250 alloc_class chunk0(
 251   R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
 252   R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
 253   R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
 254   R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
 255 
 256 // Note that a register is not allocatable unless it is also mentioned
 257 // in a widely-used reg_class below.  Thus, R_G7 and R_G0 are outside i_reg.
 258 
 259 alloc_class chunk1(
 260   // The first registers listed here are those most likely to be used
 261   // as temporaries.  We move F0..F7 away from the front of the list,
 262   // to reduce the likelihood of interferences with parameters and
 263   // return values.  Likewise, we avoid using F0/F1 for parameters,
 264   // since they are used for return values.
 265   // This FPU fine-tuning is worth about 1% on the SPEC geomean.
 266   R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 267   R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
 268   R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
 269   R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
 270   R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
 271   R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
 272   R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
 273   R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
 274 
 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
 276 
 277 //----------Architecture Description Register Classes--------------------------
 278 // Several register classes are automatically defined based upon information in
 279 // this architecture description.
 280 // 1) reg_class inline_cache_reg           ( as defined in frame section )
 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 283 //
 284 
 285 // G0 is not included in integer class since it has special meaning.
 286 reg_class g0_reg(R_G0);
 287 
 288 // ----------------------------
 289 // Integer Register Classes
 290 // ----------------------------
 291 // Exclusions from i_reg:
 292 // R_G0: hardwired zero
 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
 294 // R_G6: reserved by Solaris ABI to tools
 295 // R_G7: reserved by Solaris ABI to libthread
 296 // R_O7: Used as a temp in many encodings
 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 298 
 299 // Class for all integer registers, except the G registers.  This is used for
 300 // encodings which use G registers as temps.  The regular inputs to such
 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
 302 // will not put an input into a temp register.
 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 304 
 305 reg_class g1_regI(R_G1);
 306 reg_class g3_regI(R_G3);
 307 reg_class g4_regI(R_G4);
 308 reg_class o0_regI(R_O0);
 309 reg_class o7_regI(R_O7);
 310 
 311 // ----------------------------
 312 // Pointer Register Classes
 313 // ----------------------------
 314 #ifdef _LP64
 315 // 64-bit build means 64-bit pointers means hi/lo pairs
 316 reg_class ptr_reg(            R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
 317                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
 318                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 319                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
 320 // Lock encodings use G3 and G4 internally
 321 reg_class lock_ptr_reg(       R_G1H,R_G1,                                     R_G5H,R_G5,
 322                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
 323                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 324                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
 325 // Special class for storeP instructions, which can store SP or RPC to TLS.
 326 // It is also used for memory addressing, allowing direct TLS addressing.
 327 reg_class sp_ptr_reg(         R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
 328                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
 329                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 330                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
 332 // We use it to save R_G2 across calls out of Java.
 333 reg_class l7_regP(R_L7H,R_L7);
 334 
 335 // Other special pointer regs
 336 reg_class g1_regP(R_G1H,R_G1);
 337 reg_class g2_regP(R_G2H,R_G2);
 338 reg_class g3_regP(R_G3H,R_G3);
 339 reg_class g4_regP(R_G4H,R_G4);
 340 reg_class g5_regP(R_G5H,R_G5);
 341 reg_class i0_regP(R_I0H,R_I0);
 342 reg_class o0_regP(R_O0H,R_O0);
 343 reg_class o1_regP(R_O1H,R_O1);
 344 reg_class o2_regP(R_O2H,R_O2);
 345 reg_class o7_regP(R_O7H,R_O7);
 346 
 347 #else // _LP64
 348 // 32-bit build means 32-bit pointers means 1 register.
 349 reg_class ptr_reg(     R_G1,     R_G3,R_G4,R_G5,
 350                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
 351                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 352                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 353 // Lock encodings use G3 and G4 internally
 354 reg_class lock_ptr_reg(R_G1,               R_G5,
 355                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
 356                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 357                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 358 // Special class for storeP instructions, which can store SP or RPC to TLS.
 359 // It is also used for memory addressing, allowing direct TLS addressing.
 360 reg_class sp_ptr_reg(  R_G1,R_G2,R_G3,R_G4,R_G5,
 361                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
 362                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 363                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
 365 // We use it to save R_G2 across calls out of Java.
 366 reg_class l7_regP(R_L7);
 367 
 368 // Other special pointer regs
 369 reg_class g1_regP(R_G1);
 370 reg_class g2_regP(R_G2);
 371 reg_class g3_regP(R_G3);
 372 reg_class g4_regP(R_G4);
 373 reg_class g5_regP(R_G5);
 374 reg_class i0_regP(R_I0);
 375 reg_class o0_regP(R_O0);
 376 reg_class o1_regP(R_O1);
 377 reg_class o2_regP(R_O2);
 378 reg_class o7_regP(R_O7);
 379 #endif // _LP64
 380 
 381 
 382 // ----------------------------
 383 // Long Register Classes
 384 // ----------------------------
 385 // Longs in 1 register.  Aligned adjacent hi/lo pairs.
 386 // Note:  O7 is never in this class; it is sometimes used as an encoding temp.
 387 reg_class long_reg(             R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
 388                    ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
 389 #ifdef _LP64
 390 // 64-bit, longs in 1 register: use all 64-bit integer registers
 391 // 32-bit, longs in 1 register: cannot use I's and L's.  Restrict to O's and G's.
 392                    ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
 393                    ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
 394 #endif // _LP64
 395                   );
 396 
 397 reg_class g1_regL(R_G1H,R_G1);
 398 reg_class g3_regL(R_G3H,R_G3);
 399 reg_class o2_regL(R_O2H,R_O2);
 400 reg_class o7_regL(R_O7H,R_O7);
 401 
 402 // ----------------------------
 403 // Special Class for Condition Code Flags Register
 404 reg_class int_flags(CCR);
 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
 406 reg_class float_flag0(FCC0);
 407 
 408 
 409 // ----------------------------
 410 // Float Point Register Classes
 411 // ----------------------------
 412 // Skip F30/F31, they are reserved for mem-mem copies
 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
 414 
 415 // Paired floating point registers--they show up in the same order as the floats,
 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 418                    R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
 419                    /* Use extra V9 double registers; this AD file does not support V8 */
 420                    R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
 421                    R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
 422                    );
 423 
 424 // Paired floating point registers--they show up in the same order as the floats,
 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
 426 // This class is usable for mis-aligned loads as happen in I2C adapters.
 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 428                    R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
 429 %}
 430 
 431 //----------DEFINITION BLOCK---------------------------------------------------
 432 // Define name --> value mappings to inform the ADLC of an integer valued name
 433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
 434 // Format:
 435 //        int_def  <name>         ( <int_value>, <expression>);
 436 // Generated Code in ad_<arch>.hpp
 437 //        #define  <name>   (<expression>)
 438 //        // value == <int_value>
 439 // Generated code in ad_<arch>.cpp adlc_verification()
 440 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 441 //
 442 definitions %{
 443 // The default cost (of an ALU instruction).
 444   int_def DEFAULT_COST      (    100,     100);
 445   int_def HUGE_COST         (1000000, 1000000);
 446 
 447 // Memory refs are twice as expensive as run-of-the-mill.
 448   int_def MEMORY_REF_COST   (    200, DEFAULT_COST * 2);
 449 
 450 // Branches are even more expensive.
 451   int_def BRANCH_COST       (    300, DEFAULT_COST * 3);
 452   int_def CALL_COST         (    300, DEFAULT_COST * 3);
 453 %}
 454 
 455 
 456 //----------SOURCE BLOCK-------------------------------------------------------
 457 // This is a block of C++ code which provides values, functions, and
 458 // definitions necessary in the rest of the architecture description
 459 source_hpp %{
 460 // Header information of the source block.
 461 // Method declarations/definitions which are used outside
 462 // the ad-scope can conveniently be defined here.
 463 //
 464 // To keep related declarations/definitions/uses close together,
 465 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
 466 
 467 // Must be visible to the DFA in dfa_sparc.cpp
 468 extern bool can_branch_register( Node *bol, Node *cmp );
 469 
 470 extern bool use_block_zeroing(Node* count);
 471 
 472 // Macros to extract hi & lo halves from a long pair.
 473 // G0 is not part of any long pair, so assert on that.
 474 // Prevents accidentally using G1 instead of G0.
 475 #define LONG_HI_REG(x) (x)
 476 #define LONG_LO_REG(x) (x)
 477 
 478 class CallStubImpl {
 479 
 480   //--------------------------------------------------------------
 481   //---<  Used for optimization in Compile::Shorten_branches  >---
 482   //--------------------------------------------------------------
 483 
 484  public:
 485   // Size of call trampoline stub.
 486   static uint size_call_trampoline() {
 487     return 0; // no call trampolines on this platform
 488   }
 489 
 490   // number of relocations needed by a call trampoline stub
 491   static uint reloc_call_trampoline() {
 492     return 0; // no call trampolines on this platform
 493   }
 494 };
 495 
 496 class HandlerImpl {
 497 
 498  public:
 499 
 500   static int emit_exception_handler(CodeBuffer &cbuf);
 501   static int emit_deopt_handler(CodeBuffer& cbuf);
 502 
 503   static uint size_exception_handler() {
 504     if (TraceJumps) {
 505       return (400); // just a guess
 506     }
 507     return ( NativeJump::instruction_size ); // sethi;jmp;nop
 508   }
 509 
 510   static uint size_deopt_handler() {
 511     if (TraceJumps) {
 512       return (400); // just a guess
 513     }
 514     return ( 4+  NativeJump::instruction_size ); // save;sethi;jmp;restore
 515   }
 516 };
 517 
 518 %}
 519 
 520 source %{
 521 #define __ _masm.
 522 
 523 // tertiary op of a LoadP or StoreP encoding
 524 #define REGP_OP true
 525 
 526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
 527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
 528 static Register reg_to_register_object(int register_encoding);
 529 
 530 // Used by the DFA in dfa_sparc.cpp.
 531 // Check for being able to use a V9 branch-on-register.  Requires a
 532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
 533 // extended.  Doesn't work following an integer ADD, for example, because of
 534 // overflow (-1 incremented yields 0 plus a carry in the high-order word).  On
 535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
 536 // replace them with zero, which could become sign-extension in a different OS
 537 // release.  There's no obvious reason why an interrupt will ever fill these
 538 // bits with non-zero junk (the registers are reloaded with standard LD
 539 // instructions which either zero-fill or sign-fill).
 540 bool can_branch_register( Node *bol, Node *cmp ) {
 541   if( !BranchOnRegister ) return false;
 542 #ifdef _LP64
 543   if( cmp->Opcode() == Op_CmpP )
 544     return true;  // No problems with pointer compares
 545 #endif
 546   if( cmp->Opcode() == Op_CmpL )
 547     return true;  // No problems with long compares
 548 
 549   if( !SparcV9RegsHiBitsZero ) return false;
 550   if( bol->as_Bool()->_test._test != BoolTest::ne &&
 551       bol->as_Bool()->_test._test != BoolTest::eq )
 552      return false;
 553 
 554   // Check for comparing against a 'safe' value.  Any operation which
 555   // clears out the high word is safe.  Thus, loads and certain shifts
 556   // are safe, as are non-negative constants.  Any operation which
 557   // preserves zero bits in the high word is safe as long as each of its
 558   // inputs are safe.  Thus, phis and bitwise booleans are safe if their
 559   // inputs are safe.  At present, the only important case to recognize
 560   // seems to be loads.  Constants should fold away, and shifts &
 561   // logicals can use the 'cc' forms.
 562   Node *x = cmp->in(1);
 563   if( x->is_Load() ) return true;
 564   if( x->is_Phi() ) {
 565     for( uint i = 1; i < x->req(); i++ )
 566       if( !x->in(i)->is_Load() )
 567         return false;
 568     return true;
 569   }
 570   return false;
 571 }
 572 
 573 bool use_block_zeroing(Node* count) {
 574   // Use BIS for zeroing if count is not constant
 575   // or it is >= BlockZeroingLowLimit.
 576   return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
 577 }
 578 
 579 // ****************************************************************************
 580 
 581 // REQUIRED FUNCTIONALITY
 582 
 583 // !!!!! Special hack to get all type of calls to specify the byte offset
 584 //       from the start of the call to the point where the return address
 585 //       will point.
 586 //       The "return address" is the address of the call instruction, plus 8.
 587 
 588 int MachCallStaticJavaNode::ret_addr_offset() {
 589   int offset = NativeCall::instruction_size;  // call; delay slot
 590   if (_method_handle_invoke)
 591     offset += 4;  // restore SP
 592   return offset;
 593 }
 594 
 595 int MachCallDynamicJavaNode::ret_addr_offset() {
 596   int vtable_index = this->_vtable_index;
 597   if (vtable_index < 0) {
 598     // must be invalid_vtable_index, not nonvirtual_vtable_index
 599     assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
 600     return (NativeMovConstReg::instruction_size +
 601            NativeCall::instruction_size);  // sethi; setlo; call; delay slot
 602   } else {
 603     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 604     int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
 605     int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
 606     int klass_load_size;
 607     if (UseCompressedClassPointers) {
 608       assert(Universe::heap() != NULL, "java heap should be initialized");
 609       klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
 610     } else {
 611       klass_load_size = 1*BytesPerInstWord;
 612     }
 613     if (Assembler::is_simm13(v_off)) {
 614       return klass_load_size +
 615              (2*BytesPerInstWord +           // ld_ptr, ld_ptr
 616              NativeCall::instruction_size);  // call; delay slot
 617     } else {
 618       return klass_load_size +
 619              (4*BytesPerInstWord +           // set_hi, set, ld_ptr, ld_ptr
 620              NativeCall::instruction_size);  // call; delay slot
 621     }
 622   }
 623 }
 624 
 625 int MachCallRuntimeNode::ret_addr_offset() {
 626 #ifdef _LP64
 627   if (MacroAssembler::is_far_target(entry_point())) {
 628     return NativeFarCall::instruction_size;
 629   } else {
 630     return NativeCall::instruction_size;
 631   }
 632 #else
 633   return NativeCall::instruction_size;  // call; delay slot
 634 #endif
 635 }
 636 
 637 // Indicate if the safepoint node needs the polling page as an input.
 638 // Since Sparc does not have absolute addressing, it does.
 639 bool SafePointNode::needs_polling_address_input() {
 640   return true;
 641 }
 642 
 643 // emit an interrupt that is caught by the debugger (for debugging compiler)
 644 void emit_break(CodeBuffer &cbuf) {
 645   MacroAssembler _masm(&cbuf);
 646   __ breakpoint_trap();
 647 }
 648 
 649 #ifndef PRODUCT
 650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
 651   st->print("TA");
 652 }
 653 #endif
 654 
 655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 656   emit_break(cbuf);
 657 }
 658 
 659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 660   return MachNode::size(ra_);
 661 }
 662 
 663 // Traceable jump
 664 void  emit_jmpl(CodeBuffer &cbuf, int jump_target) {
 665   MacroAssembler _masm(&cbuf);
 666   Register rdest = reg_to_register_object(jump_target);
 667   __ JMP(rdest, 0);
 668   __ delayed()->nop();
 669 }
 670 
 671 // Traceable jump and set exception pc
 672 void  emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
 673   MacroAssembler _masm(&cbuf);
 674   Register rdest = reg_to_register_object(jump_target);
 675   __ JMP(rdest, 0);
 676   __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
 677 }
 678 
 679 void emit_nop(CodeBuffer &cbuf) {
 680   MacroAssembler _masm(&cbuf);
 681   __ nop();
 682 }
 683 
 684 void emit_illtrap(CodeBuffer &cbuf) {
 685   MacroAssembler _masm(&cbuf);
 686   __ illtrap(0);
 687 }
 688 
 689 
 690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
 691   assert(n->rule() != loadUB_rule, "");
 692 
 693   intptr_t offset = 0;
 694   const TypePtr *adr_type = TYPE_PTR_SENTINAL;  // Check for base==RegI, disp==immP
 695   const Node* addr = n->get_base_and_disp(offset, adr_type);
 696   assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
 697   assert(addr != NULL && addr != (Node*)-1, "invalid addr");
 698   assert(addr->bottom_type()->isa_oopptr() == atype, "");
 699   atype = atype->add_offset(offset);
 700   assert(disp32 == offset, "wrong disp32");
 701   return atype->_offset;
 702 }
 703 
 704 
 705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
 706   assert(n->rule() != loadUB_rule, "");
 707 
 708   intptr_t offset = 0;
 709   Node* addr = n->in(2);
 710   assert(addr->bottom_type()->isa_oopptr() == atype, "");
 711   if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
 712     Node* a = addr->in(2/*AddPNode::Address*/);
 713     Node* o = addr->in(3/*AddPNode::Offset*/);
 714     offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
 715     atype = a->bottom_type()->is_ptr()->add_offset(offset);
 716     assert(atype->isa_oop_ptr(), "still an oop");
 717   }
 718   offset = atype->is_ptr()->_offset;
 719   if (offset != Type::OffsetBot)  offset += disp32;
 720   return offset;
 721 }
 722 
 723 static inline jlong replicate_immI(int con, int count, int width) {
 724   // Load a constant replicated "count" times with width "width"
 725   assert(count*width == 8 && width <= 4, "sanity");
 726   int bit_width = width * 8;
 727   jlong val = con;
 728   val &= (((jlong) 1) << bit_width) - 1;  // mask off sign bits
 729   for (int i = 0; i < count - 1; i++) {
 730     val |= (val << bit_width);
 731   }
 732   return val;
 733 }
 734 
 735 static inline jlong replicate_immF(float con) {
 736   // Replicate float con 2 times and pack into vector.
 737   int val = *((int*)&con);
 738   jlong lval = val;
 739   lval = (lval << 32) | (lval & 0xFFFFFFFFl);
 740   return lval;
 741 }
 742 
 743 // Standard Sparc opcode form2 field breakdown
 744 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
 745   f0 &= (1<<19)-1;     // Mask displacement to 19 bits
 746   int op = (f30 << 30) |
 747            (f29 << 29) |
 748            (f25 << 25) |
 749            (f22 << 22) |
 750            (f20 << 20) |
 751            (f19 << 19) |
 752            (f0  <<  0);
 753   cbuf.insts()->emit_int32(op);
 754 }
 755 
 756 // Standard Sparc opcode form2 field breakdown
 757 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
 758   f0 >>= 10;           // Drop 10 bits
 759   f0 &= (1<<22)-1;     // Mask displacement to 22 bits
 760   int op = (f30 << 30) |
 761            (f25 << 25) |
 762            (f22 << 22) |
 763            (f0  <<  0);
 764   cbuf.insts()->emit_int32(op);
 765 }
 766 
 767 // Standard Sparc opcode form3 field breakdown
 768 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
 769   int op = (f30 << 30) |
 770            (f25 << 25) |
 771            (f19 << 19) |
 772            (f14 << 14) |
 773            (f5  <<  5) |
 774            (f0  <<  0);
 775   cbuf.insts()->emit_int32(op);
 776 }
 777 
 778 // Standard Sparc opcode form3 field breakdown
 779 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
 780   simm13 &= (1<<13)-1; // Mask to 13 bits
 781   int op = (f30 << 30) |
 782            (f25 << 25) |
 783            (f19 << 19) |
 784            (f14 << 14) |
 785            (1   << 13) | // bit to indicate immediate-mode
 786            (simm13<<0);
 787   cbuf.insts()->emit_int32(op);
 788 }
 789 
 790 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
 791   simm10 &= (1<<10)-1; // Mask to 10 bits
 792   emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
 793 }
 794 
 795 #ifdef ASSERT
 796 // Helper function for VerifyOops in emit_form3_mem_reg
 797 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
 798   warning("VerifyOops encountered unexpected instruction:");
 799   n->dump(2);
 800   warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
 801 }
 802 #endif
 803 
 804 
 805 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
 806                         int src1_enc, int disp32, int src2_enc, int dst_enc) {
 807 
 808 #ifdef ASSERT
 809   // The following code implements the +VerifyOops feature.
 810   // It verifies oop values which are loaded into or stored out of
 811   // the current method activation.  +VerifyOops complements techniques
 812   // like ScavengeALot, because it eagerly inspects oops in transit,
 813   // as they enter or leave the stack, as opposed to ScavengeALot,
 814   // which inspects oops "at rest", in the stack or heap, at safepoints.
 815   // For this reason, +VerifyOops can sometimes detect bugs very close
 816   // to their point of creation.  It can also serve as a cross-check
 817   // on the validity of oop maps, when used toegether with ScavengeALot.
 818 
 819   // It would be good to verify oops at other points, especially
 820   // when an oop is used as a base pointer for a load or store.
 821   // This is presently difficult, because it is hard to know when
 822   // a base address is biased or not.  (If we had such information,
 823   // it would be easy and useful to make a two-argument version of
 824   // verify_oop which unbiases the base, and performs verification.)
 825 
 826   assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
 827   bool is_verified_oop_base  = false;
 828   bool is_verified_oop_load  = false;
 829   bool is_verified_oop_store = false;
 830   int tmp_enc = -1;
 831   if (VerifyOops && src1_enc != R_SP_enc) {
 832     // classify the op, mainly for an assert check
 833     int st_op = 0, ld_op = 0;
 834     switch (primary) {
 835     case Assembler::stb_op3:  st_op = Op_StoreB; break;
 836     case Assembler::sth_op3:  st_op = Op_StoreC; break;
 837     case Assembler::stx_op3:  // may become StoreP or stay StoreI or StoreD0
 838     case Assembler::stw_op3:  st_op = Op_StoreI; break;
 839     case Assembler::std_op3:  st_op = Op_StoreL; break;
 840     case Assembler::stf_op3:  st_op = Op_StoreF; break;
 841     case Assembler::stdf_op3: st_op = Op_StoreD; break;
 842 
 843     case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
 844     case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
 845     case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
 846     case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
 847     case Assembler::ldx_op3:  // may become LoadP or stay LoadI
 848     case Assembler::ldsw_op3: // may become LoadP or stay LoadI
 849     case Assembler::lduw_op3: ld_op = Op_LoadI; break;
 850     case Assembler::ldd_op3:  ld_op = Op_LoadL; break;
 851     case Assembler::ldf_op3:  ld_op = Op_LoadF; break;
 852     case Assembler::lddf_op3: ld_op = Op_LoadD; break;
 853     case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
 854 
 855     default: ShouldNotReachHere();
 856     }
 857     if (tertiary == REGP_OP) {
 858       if      (st_op == Op_StoreI)  st_op = Op_StoreP;
 859       else if (ld_op == Op_LoadI)   ld_op = Op_LoadP;
 860       else                          ShouldNotReachHere();
 861       if (st_op) {
 862         // a store
 863         // inputs are (0:control, 1:memory, 2:address, 3:value)
 864         Node* n2 = n->in(3);
 865         if (n2 != NULL) {
 866           const Type* t = n2->bottom_type();
 867           is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
 868         }
 869       } else {
 870         // a load
 871         const Type* t = n->bottom_type();
 872         is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
 873       }
 874     }
 875 
 876     if (ld_op) {
 877       // a Load
 878       // inputs are (0:control, 1:memory, 2:address)
 879       if (!(n->ideal_Opcode()==ld_op)       && // Following are special cases
 880           !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
 881           !(n->ideal_Opcode()==Op_LoadI     && ld_op==Op_LoadF) &&
 882           !(n->ideal_Opcode()==Op_LoadF     && ld_op==Op_LoadI) &&
 883           !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
 884           !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
 885           !(n->ideal_Opcode()==Op_LoadL     && ld_op==Op_LoadI) &&
 886           !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
 887           !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
 888           !(n->ideal_Opcode()==Op_ConvI2F   && ld_op==Op_LoadF) &&
 889           !(n->ideal_Opcode()==Op_ConvI2D   && ld_op==Op_LoadF) &&
 890           !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
 891           !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
 892           !(n->rule() == loadUB_rule)) {
 893         verify_oops_warning(n, n->ideal_Opcode(), ld_op);
 894       }
 895     } else if (st_op) {
 896       // a Store
 897       // inputs are (0:control, 1:memory, 2:address, 3:value)
 898       if (!(n->ideal_Opcode()==st_op)    && // Following are special cases
 899           !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
 900           !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
 901           !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
 902           !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
 903           !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
 904           !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
 905         verify_oops_warning(n, n->ideal_Opcode(), st_op);
 906       }
 907     }
 908 
 909     if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
 910       Node* addr = n->in(2);
 911       if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
 912         const TypeOopPtr* atype = addr->bottom_type()->isa_instptr();  // %%% oopptr?
 913         if (atype != NULL) {
 914           intptr_t offset = get_offset_from_base(n, atype, disp32);
 915           intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
 916           if (offset != offset_2) {
 917             get_offset_from_base(n, atype, disp32);
 918             get_offset_from_base_2(n, atype, disp32);
 919           }
 920           assert(offset == offset_2, "different offsets");
 921           if (offset == disp32) {
 922             // we now know that src1 is a true oop pointer
 923             is_verified_oop_base = true;
 924             if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
 925               if( primary == Assembler::ldd_op3 ) {
 926                 is_verified_oop_base = false; // Cannot 'ldd' into O7
 927               } else {
 928                 tmp_enc = dst_enc;
 929                 dst_enc = R_O7_enc; // Load into O7; preserve source oop
 930                 assert(src1_enc != dst_enc, "");
 931               }
 932             }
 933           }
 934           if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
 935                        || offset == oopDesc::mark_offset_in_bytes())) {
 936                       // loading the mark should not be allowed either, but
 937                       // we don't check this since it conflicts with InlineObjectHash
 938                       // usage of LoadINode to get the mark. We could keep the
 939                       // check if we create a new LoadMarkNode
 940             // but do not verify the object before its header is initialized
 941             ShouldNotReachHere();
 942           }
 943         }
 944       }
 945     }
 946   }
 947 #endif
 948 
 949   uint instr = (Assembler::ldst_op << 30)
 950              | (dst_enc        << 25)
 951              | (primary        << 19)
 952              | (src1_enc       << 14);
 953 
 954   uint index = src2_enc;
 955   int disp = disp32;
 956 
 957   if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
 958     disp += STACK_BIAS;
 959     // Check that stack offset fits, load into O7 if not
 960     if (!Assembler::is_simm13(disp)) {
 961       MacroAssembler _masm(&cbuf);
 962       __ set(disp, O7);
 963       if (index != R_G0_enc) {
 964         __ add(O7, reg_to_register_object(index), O7);
 965       }
 966       index = R_O7_enc;
 967       disp = 0;
 968     }
 969   }
 970 
 971   if( disp == 0 ) {
 972     // use reg-reg form
 973     // bit 13 is already zero
 974     instr |= index;
 975   } else {
 976     // use reg-imm form
 977     instr |= 0x00002000;          // set bit 13 to one
 978     instr |= disp & 0x1FFF;
 979   }
 980 
 981   cbuf.insts()->emit_int32(instr);
 982 
 983 #ifdef ASSERT
 984   if (VerifyOops) {
 985     MacroAssembler _masm(&cbuf);
 986     if (is_verified_oop_base) {
 987       __ verify_oop(reg_to_register_object(src1_enc));
 988     }
 989     if (is_verified_oop_store) {
 990       __ verify_oop(reg_to_register_object(dst_enc));
 991     }
 992     if (tmp_enc != -1) {
 993       __ mov(O7, reg_to_register_object(tmp_enc));
 994     }
 995     if (is_verified_oop_load) {
 996       __ verify_oop(reg_to_register_object(dst_enc));
 997     }
 998   }
 999 #endif
1000 }
1001 
1002 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) {
1003   // The method which records debug information at every safepoint
1004   // expects the call to be the first instruction in the snippet as
1005   // it creates a PcDesc structure which tracks the offset of a call
1006   // from the start of the codeBlob. This offset is computed as
1007   // code_end() - code_begin() of the code which has been emitted
1008   // so far.
1009   // In this particular case we have skirted around the problem by
1010   // putting the "mov" instruction in the delay slot but the problem
1011   // may bite us again at some other point and a cleaner/generic
1012   // solution using relocations would be needed.
1013   MacroAssembler _masm(&cbuf);
1014   __ set_inst_mark();
1015 
1016   // We flush the current window just so that there is a valid stack copy
1017   // the fact that the current window becomes active again instantly is
1018   // not a problem there is nothing live in it.
1019 
1020 #ifdef ASSERT
1021   int startpos = __ offset();
1022 #endif /* ASSERT */
1023 
1024   __ call((address)entry_point, rspec);
1025 
1026   if (preserve_g2)   __ delayed()->mov(G2, L7);
1027   else __ delayed()->nop();
1028 
1029   if (preserve_g2)   __ mov(L7, G2);
1030 
1031 #ifdef ASSERT
1032   if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1033 #ifdef _LP64
1034     // Trash argument dump slots.
1035     __ set(0xb0b8ac0db0b8ac0d, G1);
1036     __ mov(G1, G5);
1037     __ stx(G1, SP, STACK_BIAS + 0x80);
1038     __ stx(G1, SP, STACK_BIAS + 0x88);
1039     __ stx(G1, SP, STACK_BIAS + 0x90);
1040     __ stx(G1, SP, STACK_BIAS + 0x98);
1041     __ stx(G1, SP, STACK_BIAS + 0xA0);
1042     __ stx(G1, SP, STACK_BIAS + 0xA8);
1043 #else // _LP64
1044     // this is also a native call, so smash the first 7 stack locations,
1045     // and the various registers
1046 
1047     // Note:  [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1048     // while [SP+0x44..0x58] are the argument dump slots.
1049     __ set((intptr_t)0xbaadf00d, G1);
1050     __ mov(G1, G5);
1051     __ sllx(G1, 32, G1);
1052     __ or3(G1, G5, G1);
1053     __ mov(G1, G5);
1054     __ stx(G1, SP, 0x40);
1055     __ stx(G1, SP, 0x48);
1056     __ stx(G1, SP, 0x50);
1057     __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1058 #endif // _LP64
1059   }
1060 #endif /*ASSERT*/
1061 }
1062 
1063 //=============================================================================
1064 // REQUIRED FUNCTIONALITY for encoding
1065 void emit_lo(CodeBuffer &cbuf, int val) {  }
1066 void emit_hi(CodeBuffer &cbuf, int val) {  }
1067 
1068 
1069 //=============================================================================
1070 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1071 
1072 int Compile::ConstantTable::calculate_table_base_offset() const {
1073   if (UseRDPCForConstantTableBase) {
1074     // The table base offset might be less but then it fits into
1075     // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1076     return Assembler::min_simm13();
1077   } else {
1078     int offset = -(size() / 2);
1079     if (!Assembler::is_simm13(offset)) {
1080       offset = Assembler::min_simm13();
1081     }
1082     return offset;
1083   }
1084 }
1085 
1086 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1087 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1088   ShouldNotReachHere();
1089 }
1090 
1091 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1092   Compile* C = ra_->C;
1093   Compile::ConstantTable& constant_table = C->constant_table();
1094   MacroAssembler _masm(&cbuf);
1095 
1096   Register r = as_Register(ra_->get_encode(this));
1097   CodeSection* consts_section = __ code()->consts();
1098   int consts_size = consts_section->align_at_start(consts_section->size());
1099   assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1100 
1101   if (UseRDPCForConstantTableBase) {
1102     // For the following RDPC logic to work correctly the consts
1103     // section must be allocated right before the insts section.  This
1104     // assert checks for that.  The layout and the SECT_* constants
1105     // are defined in src/share/vm/asm/codeBuffer.hpp.
1106     assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1107     int insts_offset = __ offset();
1108 
1109     // Layout:
1110     //
1111     // |----------- consts section ------------|----------- insts section -----------...
1112     // |------ constant table -----|- padding -|------------------x----
1113     //                                                            \ current PC (RDPC instruction)
1114     // |<------------- consts_size ----------->|<- insts_offset ->|
1115     //                                                            \ table base
1116     // The table base offset is later added to the load displacement
1117     // so it has to be negative.
1118     int table_base_offset = -(consts_size + insts_offset);
1119     int disp;
1120 
1121     // If the displacement from the current PC to the constant table
1122     // base fits into simm13 we set the constant table base to the
1123     // current PC.
1124     if (Assembler::is_simm13(table_base_offset)) {
1125       constant_table.set_table_base_offset(table_base_offset);
1126       disp = 0;
1127     } else {
1128       // Otherwise we set the constant table base offset to the
1129       // maximum negative displacement of load instructions to keep
1130       // the disp as small as possible:
1131       //
1132       // |<------------- consts_size ----------->|<- insts_offset ->|
1133       // |<--------- min_simm13 --------->|<-------- disp --------->|
1134       //                                  \ table base
1135       table_base_offset = Assembler::min_simm13();
1136       constant_table.set_table_base_offset(table_base_offset);
1137       disp = (consts_size + insts_offset) + table_base_offset;
1138     }
1139 
1140     __ rdpc(r);
1141 
1142     if (disp != 0) {
1143       assert(r != O7, "need temporary");
1144       __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1145     }
1146   }
1147   else {
1148     // Materialize the constant table base.
1149     address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1150     RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1151     AddressLiteral base(baseaddr, rspec);
1152     __ set(base, r);
1153   }
1154 }
1155 
1156 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1157   if (UseRDPCForConstantTableBase) {
1158     // This is really the worst case but generally it's only 1 instruction.
1159     return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1160   } else {
1161     return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1162   }
1163 }
1164 
1165 #ifndef PRODUCT
1166 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1167   char reg[128];
1168   ra_->dump_register(this, reg);
1169   if (UseRDPCForConstantTableBase) {
1170     st->print("RDPC   %s\t! constant table base", reg);
1171   } else {
1172     st->print("SET    &constanttable,%s\t! constant table base", reg);
1173   }
1174 }
1175 #endif
1176 
1177 
1178 //=============================================================================
1179 
1180 #ifndef PRODUCT
1181 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1182   Compile* C = ra_->C;
1183 
1184   for (int i = 0; i < OptoPrologueNops; i++) {
1185     st->print_cr("NOP"); st->print("\t");
1186   }
1187 
1188   if( VerifyThread ) {
1189     st->print_cr("Verify_Thread"); st->print("\t");
1190   }
1191 
1192   size_t framesize = C->frame_size_in_bytes();
1193   int bangsize = C->bang_size_in_bytes();
1194 
1195   // Calls to C2R adapters often do not accept exceptional returns.
1196   // We require that their callers must bang for them.  But be careful, because
1197   // some VM calls (such as call site linkage) can use several kilobytes of
1198   // stack.  But the stack safety zone should account for that.
1199   // See bugs 4446381, 4468289, 4497237.
1200   if (C->need_stack_bang(bangsize)) {
1201     st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1202   }
1203 
1204   if (Assembler::is_simm13(-framesize)) {
1205     st->print   ("SAVE   R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1206   } else {
1207     st->print_cr("SETHI  R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1208     st->print_cr("ADD    R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1209     st->print   ("SAVE   R_SP,R_G3,R_SP");
1210   }
1211 
1212 }
1213 #endif
1214 
1215 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1216   Compile* C = ra_->C;
1217   MacroAssembler _masm(&cbuf);
1218 
1219   for (int i = 0; i < OptoPrologueNops; i++) {
1220     __ nop();
1221   }
1222 
1223   __ verify_thread();
1224 
1225   size_t framesize = C->frame_size_in_bytes();
1226   assert(framesize >= 16*wordSize, "must have room for reg. save area");
1227   assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1228   int bangsize = C->bang_size_in_bytes();
1229 
1230   // Calls to C2R adapters often do not accept exceptional returns.
1231   // We require that their callers must bang for them.  But be careful, because
1232   // some VM calls (such as call site linkage) can use several kilobytes of
1233   // stack.  But the stack safety zone should account for that.
1234   // See bugs 4446381, 4468289, 4497237.
1235   if (C->need_stack_bang(bangsize)) {
1236     __ generate_stack_overflow_check(bangsize);
1237   }
1238 
1239   if (Assembler::is_simm13(-framesize)) {
1240     __ save(SP, -framesize, SP);
1241   } else {
1242     __ sethi(-framesize & ~0x3ff, G3);
1243     __ add(G3, -framesize & 0x3ff, G3);
1244     __ save(SP, G3, SP);
1245   }
1246   C->set_frame_complete( __ offset() );
1247 
1248   if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1249     // NOTE: We set the table base offset here because users might be
1250     // emitted before MachConstantBaseNode.
1251     Compile::ConstantTable& constant_table = C->constant_table();
1252     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1253   }
1254 }
1255 
1256 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1257   return MachNode::size(ra_);
1258 }
1259 
1260 int MachPrologNode::reloc() const {
1261   return 10; // a large enough number
1262 }
1263 
1264 //=============================================================================
1265 #ifndef PRODUCT
1266 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1267   Compile* C = ra_->C;
1268 
1269   if(do_polling() && ra_->C->is_method_compilation()) {
1270     st->print("SETHI  #PollAddr,L0\t! Load Polling address\n\t");
1271 #ifdef _LP64
1272     st->print("LDX    [L0],G0\t!Poll for Safepointing\n\t");
1273 #else
1274     st->print("LDUW   [L0],G0\t!Poll for Safepointing\n\t");
1275 #endif
1276   }
1277 
1278   if(do_polling()) {
1279     if (UseCBCond && !ra_->C->is_method_compilation()) {
1280       st->print("NOP\n\t");
1281     }
1282     st->print("RET\n\t");
1283   }
1284 
1285   st->print("RESTORE");
1286 }
1287 #endif
1288 
1289 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1290   MacroAssembler _masm(&cbuf);
1291   Compile* C = ra_->C;
1292 
1293   __ verify_thread();
1294 
1295   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1296     __ reserved_stack_check();
1297   }
1298 
1299   // If this does safepoint polling, then do it here
1300   if(do_polling() && ra_->C->is_method_compilation()) {
1301     AddressLiteral polling_page(os::get_polling_page());
1302     __ sethi(polling_page, L0);
1303     __ relocate(relocInfo::poll_return_type);
1304     __ ld_ptr(L0, 0, G0);
1305   }
1306 
1307   // If this is a return, then stuff the restore in the delay slot
1308   if(do_polling()) {
1309     if (UseCBCond && !ra_->C->is_method_compilation()) {
1310       // Insert extra padding for the case when the epilogue is preceded by
1311       // a cbcond jump, which can't be followed by a CTI instruction
1312       __ nop();
1313     }
1314     __ ret();
1315     __ delayed()->restore();
1316   } else {
1317     __ restore();
1318   }
1319 }
1320 
1321 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1322   return MachNode::size(ra_);
1323 }
1324 
1325 int MachEpilogNode::reloc() const {
1326   return 16; // a large enough number
1327 }
1328 
1329 const Pipeline * MachEpilogNode::pipeline() const {
1330   return MachNode::pipeline_class();
1331 }
1332 
1333 int MachEpilogNode::safepoint_offset() const {
1334   assert( do_polling(), "no return for this epilog node");
1335   return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1336 }
1337 
1338 //=============================================================================
1339 
1340 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1341 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1342 static enum RC rc_class( OptoReg::Name reg ) {
1343   if (!OptoReg::is_valid(reg)) return rc_bad;
1344   if (OptoReg::is_stack(reg)) return rc_stack;
1345   VMReg r = OptoReg::as_VMReg(reg);
1346   if (r->is_Register()) return rc_int;
1347   assert(r->is_FloatRegister(), "must be");
1348   return rc_float;
1349 }
1350 
1351 #ifndef PRODUCT
1352 ATTRIBUTE_PRINTF(2, 3)
1353 static void print_helper(outputStream* st, const char* format, ...) {
1354   if (st->position() > 0) {
1355     st->cr();
1356     st->sp();
1357   }
1358   va_list ap;
1359   va_start(ap, format);
1360   st->vprint(format, ap);
1361   va_end(ap);
1362 }
1363 #endif // !PRODUCT
1364 
1365 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) {
1366   if (cbuf) {
1367     emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1368   }
1369 #ifndef PRODUCT
1370   else {
1371     if (is_load) {
1372       print_helper(st, "%s   [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg));
1373     } else {
1374       print_helper(st, "%s   R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset);
1375     }
1376   }
1377 #endif
1378 }
1379 
1380 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) {
1381   if (cbuf) {
1382     emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]);
1383   }
1384 #ifndef PRODUCT
1385   else {
1386     print_helper(st, "%s  R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst));
1387   }
1388 #endif
1389 }
1390 
1391 static void mach_spill_copy_implementation_helper(const MachNode* mach,
1392                                                   CodeBuffer *cbuf,
1393                                                   PhaseRegAlloc *ra_,
1394                                                   outputStream* st) {
1395   // Get registers to move
1396   OptoReg::Name src_second = ra_->get_reg_second(mach->in(1));
1397   OptoReg::Name src_first  = ra_->get_reg_first(mach->in(1));
1398   OptoReg::Name dst_second = ra_->get_reg_second(mach);
1399   OptoReg::Name dst_first  = ra_->get_reg_first(mach);
1400 
1401   enum RC src_second_rc = rc_class(src_second);
1402   enum RC src_first_rc  = rc_class(src_first);
1403   enum RC dst_second_rc = rc_class(dst_second);
1404   enum RC dst_first_rc  = rc_class(dst_first);
1405 
1406   assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register");
1407 
1408   if (src_first == dst_first && src_second == dst_second) {
1409     return; // Self copy, no move
1410   }
1411 
1412   // --------------------------------------
1413   // Check for mem-mem move.  Load into unused float registers and fall into
1414   // the float-store case.
1415   if (src_first_rc == rc_stack && dst_first_rc == rc_stack) {
1416     int offset = ra_->reg2offset(src_first);
1417     // Further check for aligned-adjacent pair, so we can use a double load
1418     if ((src_first&1) == 0 && src_first+1 == src_second) {
1419       src_second    = OptoReg::Name(R_F31_num);
1420       src_second_rc = rc_float;
1421       impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st);
1422     } else {
1423       impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st);
1424     }
1425     src_first    = OptoReg::Name(R_F30_num);
1426     src_first_rc = rc_float;
1427   }
1428 
1429   if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1430     int offset = ra_->reg2offset(src_second);
1431     impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st);
1432     src_second    = OptoReg::Name(R_F31_num);
1433     src_second_rc = rc_float;
1434   }
1435 
1436   // --------------------------------------
1437   // Check for float->int copy; requires a trip through memory
1438   if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1439     int offset = frame::register_save_words*wordSize;
1440     if (cbuf) {
1441       emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16);
1442       impl_helper(mach, cbuf, ra_, false, offset, src_first,  Assembler::stf_op3, "STF ", st);
1443       impl_helper(mach, cbuf, ra_,  true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1444       emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16);
1445     }
1446 #ifndef PRODUCT
1447     else {
1448       print_helper(st, "SUB    R_SP,16,R_SP");
1449       impl_helper(mach, cbuf, ra_, false, offset, src_first,  Assembler::stf_op3, "STF ", st);
1450       impl_helper(mach, cbuf, ra_,  true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1451       print_helper(st, "ADD    R_SP,16,R_SP");
1452     }
1453 #endif
1454   }
1455 
1456   // Check for float->int copy on T4
1457   if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1458     // Further check for aligned-adjacent pair, so we can use a double move
1459     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1460       impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st);
1461       return;
1462     }
1463     impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st);
1464   }
1465   // Check for int->float copy on T4
1466   if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1467     // Further check for aligned-adjacent pair, so we can use a double move
1468     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1469       impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st);
1470       return;
1471     }
1472     impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st);
1473   }
1474 
1475   // --------------------------------------
1476   // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1477   // In such cases, I have to do the big-endian swap.  For aligned targets, the
1478   // hardware does the flop for me.  Doubles are always aligned, so no problem
1479   // there.  Misaligned sources only come from native-long-returns (handled
1480   // special below).
1481 #ifndef _LP64
1482   if (src_first_rc == rc_int &&     // source is already big-endian
1483       src_second_rc != rc_bad &&    // 64-bit move
1484       ((dst_first & 1) != 0 || dst_second != dst_first + 1)) { // misaligned dst
1485     assert((src_first & 1) == 0 && src_second == src_first + 1, "source must be aligned");
1486     // Do the big-endian flop.
1487     OptoReg::Name tmp    = dst_first   ; dst_first    = dst_second   ; dst_second    = tmp   ;
1488     enum RC       tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1489   }
1490 #endif
1491 
1492   // --------------------------------------
1493   // Check for integer reg-reg copy
1494   if (src_first_rc == rc_int && dst_first_rc == rc_int) {
1495 #ifndef _LP64
1496     if (src_first == R_O0_num && src_second == R_O1_num) {  // Check for the evil O0/O1 native long-return case
1497       // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1498       //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second
1499       //       operand contains the least significant word of the 64-bit value and vice versa.
1500       OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1501       assert((dst_first & 1) == 0 && dst_second == dst_first + 1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1502       // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1503       if ( cbuf ) {
1504         emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020);
1505         emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000);
1506         emit3       (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second]);
1507 #ifndef PRODUCT
1508       } else {
1509         print_helper(st, "SLLX   R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1510         print_helper(st, "SRL    R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1511         print_helper(st, "OR     R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1512 #endif
1513       }
1514       return;
1515     } else if (dst_first == R_I0_num && dst_second == R_I1_num) {
1516       // returning a long value in I0/I1
1517       // a SpillCopy must be able to target a return instruction's reg_class
1518       // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1519       //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second
1520       //       operand contains the least significant word of the 64-bit value and vice versa.
1521       OptoReg::Name tdest = dst_first;
1522 
1523       if (src_first == dst_first) {
1524         tdest = OptoReg::Name(R_O7_num);
1525       }
1526 
1527       if (cbuf) {
1528         assert((src_first & 1) == 0 && (src_first + 1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1529         // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1530         // ShrL_reg_imm6
1531         emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000);
1532         // ShrR_reg_imm6  src, 0, dst
1533         emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000);
1534         if (tdest != dst_first) {
1535           emit3     (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest]);
1536         }
1537       }
1538 #ifndef PRODUCT
1539       else {
1540         print_helper(st, "SRLX   R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1541         print_helper(st, "SRL    R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1542         if (tdest != dst_first) {
1543           print_helper(st, "MOV    R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1544         }
1545       }
1546 #endif // PRODUCT
1547       return size+8;
1548     }
1549 #endif // !_LP64
1550     // Else normal reg-reg copy
1551     assert(src_second != dst_first, "smashed second before evacuating it");
1552     impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV  ", st);
1553     assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers");
1554     // This moves an aligned adjacent pair.
1555     // See if we are done.
1556     if (src_first + 1 == src_second && dst_first + 1 == dst_second) {
1557       return;
1558     }
1559   }
1560 
1561   // Check for integer store
1562   if (src_first_rc == rc_int && dst_first_rc == rc_stack) {
1563     int offset = ra_->reg2offset(dst_first);
1564     // Further check for aligned-adjacent pair, so we can use a double store
1565     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1566       impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st);
1567       return;
1568     }
1569     impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st);
1570   }
1571 
1572   // Check for integer load
1573   if (dst_first_rc == rc_int && src_first_rc == rc_stack) {
1574     int offset = ra_->reg2offset(src_first);
1575     // Further check for aligned-adjacent pair, so we can use a double load
1576     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1577       impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st);
1578       return;
1579     }
1580     impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1581   }
1582 
1583   // Check for float reg-reg copy
1584   if (src_first_rc == rc_float && dst_first_rc == rc_float) {
1585     // Further check for aligned-adjacent pair, so we can use a double move
1586     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1587       impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st);
1588       return;
1589     }
1590     impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st);
1591   }
1592 
1593   // Check for float store
1594   if (src_first_rc == rc_float && dst_first_rc == rc_stack) {
1595     int offset = ra_->reg2offset(dst_first);
1596     // Further check for aligned-adjacent pair, so we can use a double store
1597     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1598       impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st);
1599       return;
1600     }
1601     impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1602   }
1603 
1604   // Check for float load
1605   if (dst_first_rc == rc_float && src_first_rc == rc_stack) {
1606     int offset = ra_->reg2offset(src_first);
1607     // Further check for aligned-adjacent pair, so we can use a double load
1608     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1609       impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st);
1610       return;
1611     }
1612     impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st);
1613   }
1614 
1615   // --------------------------------------------------------------------
1616   // Check for hi bits still needing moving.  Only happens for misaligned
1617   // arguments to native calls.
1618   if (src_second == dst_second) {
1619     return; // Self copy; no move
1620   }
1621   assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad");
1622 
1623 #ifndef _LP64
1624   // In the LP64 build, all registers can be moved as aligned/adjacent
1625   // pairs, so there's never any need to move the high bits separately.
1626   // The 32-bit builds have to deal with the 32-bit ABI which can force
1627   // all sorts of silly alignment problems.
1628 
1629   // Check for integer reg-reg copy.  Hi bits are stuck up in the top
1630   // 32-bits of a 64-bit register, but are needed in low bits of another
1631   // register (else it's a hi-bits-to-hi-bits copy which should have
1632   // happened already as part of a 64-bit move)
1633   if (src_second_rc == rc_int && dst_second_rc == rc_int) {
1634     assert((src_second & 1) == 1, "its the evil O0/O1 native return case");
1635     assert((dst_second & 1) == 0, "should have moved with 1 64-bit move");
1636     // Shift src_second down to dst_second's low bits.
1637     if (cbuf) {
1638       emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1639 #ifndef PRODUCT
1640     } else  {
1641       print_helper(st, "SRLX   R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second - 1), OptoReg::regname(dst_second));
1642 #endif
1643     }
1644     return;
1645   }
1646 
1647   // Check for high word integer store.  Must down-shift the hi bits
1648   // into a temp register, then fall into the case of storing int bits.
1649   if (src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second & 1) == 1) {
1650     // Shift src_second down to dst_second's low bits.
1651     if (cbuf) {
1652       emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1653 #ifndef PRODUCT
1654     } else {
1655       print_helper(st, "SRLX   R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second-1), OptoReg::regname(R_O7_num));
1656 #endif
1657     }
1658     src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1659   }
1660 
1661   // Check for high word integer load
1662   if (dst_second_rc == rc_int && src_second_rc == rc_stack)
1663     return impl_helper(this, cbuf, ra_, true, ra_->reg2offset(src_second), dst_second, Assembler::lduw_op3, "LDUW", size, st);
1664 
1665   // Check for high word integer store
1666   if (src_second_rc == rc_int && dst_second_rc == rc_stack)
1667     return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stw_op3, "STW ", size, st);
1668 
1669   // Check for high word float store
1670   if (src_second_rc == rc_float && dst_second_rc == rc_stack)
1671     return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stf_op3, "STF ", size, st);
1672 
1673 #endif // !_LP64
1674 
1675   Unimplemented();
1676 }
1677 
1678 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf,
1679                                        PhaseRegAlloc *ra_,
1680                                        bool do_size,
1681                                        outputStream* st) const {
1682   assert(!do_size, "not supported");
1683   mach_spill_copy_implementation_helper(this, cbuf, ra_, st);
1684   return 0;
1685 }
1686 
1687 #ifndef PRODUCT
1688 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1689   implementation( NULL, ra_, false, st );
1690 }
1691 #endif
1692 
1693 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1694   implementation( &cbuf, ra_, false, NULL );
1695 }
1696 
1697 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1698   return MachNode::size(ra_);
1699 }
1700 
1701 //=============================================================================
1702 #ifndef PRODUCT
1703 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const {
1704   st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1705 }
1706 #endif
1707 
1708 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1709   MacroAssembler _masm(&cbuf);
1710   for (int i = 0; i < _count; i += 1) {
1711     __ nop();
1712   }
1713 }
1714 
1715 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1716   return 4 * _count;
1717 }
1718 
1719 
1720 //=============================================================================
1721 #ifndef PRODUCT
1722 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1723   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1724   int reg = ra_->get_reg_first(this);
1725   st->print("LEA    [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1726 }
1727 #endif
1728 
1729 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1730   MacroAssembler _masm(&cbuf);
1731   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1732   int reg = ra_->get_encode(this);
1733 
1734   if (Assembler::is_simm13(offset)) {
1735      __ add(SP, offset, reg_to_register_object(reg));
1736   } else {
1737      __ set(offset, O7);
1738      __ add(SP, O7, reg_to_register_object(reg));
1739   }
1740 }
1741 
1742 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1743   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1744   assert(ra_ == ra_->C->regalloc(), "sanity");
1745   return ra_->C->scratch_emit_size(this);
1746 }
1747 
1748 //=============================================================================
1749 #ifndef PRODUCT
1750 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1751   st->print_cr("\nUEP:");
1752 #ifdef    _LP64
1753   if (UseCompressedClassPointers) {
1754     assert(Universe::heap() != NULL, "java heap should be initialized");
1755     st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1756     if (Universe::narrow_klass_base() != 0) {
1757       st->print_cr("\tSET    Universe::narrow_klass_base,R_G6_heap_base");
1758       if (Universe::narrow_klass_shift() != 0) {
1759         st->print_cr("\tSLL    R_G5,Universe::narrow_klass_shift,R_G5");
1760       }
1761       st->print_cr("\tADD    R_G5,R_G6_heap_base,R_G5");
1762       st->print_cr("\tSET    Universe::narrow_ptrs_base,R_G6_heap_base");
1763     } else {
1764       st->print_cr("\tSLL    R_G5,Universe::narrow_klass_shift,R_G5");
1765     }
1766   } else {
1767     st->print_cr("\tLDX    [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1768   }
1769   st->print_cr("\tCMP    R_G5,R_G3" );
1770   st->print   ("\tTne    xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1771 #else  // _LP64
1772   st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1773   st->print_cr("\tCMP    R_G5,R_G3" );
1774   st->print   ("\tTne    icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1775 #endif // _LP64
1776 }
1777 #endif
1778 
1779 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1780   MacroAssembler _masm(&cbuf);
1781   Register G5_ic_reg  = reg_to_register_object(Matcher::inline_cache_reg_encode());
1782   Register temp_reg   = G3;
1783   assert( G5_ic_reg != temp_reg, "conflicting registers" );
1784 
1785   // Load klass from receiver
1786   __ load_klass(O0, temp_reg);
1787   // Compare against expected klass
1788   __ cmp(temp_reg, G5_ic_reg);
1789   // Branch to miss code, checks xcc or icc depending
1790   __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1791 }
1792 
1793 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1794   return MachNode::size(ra_);
1795 }
1796 
1797 
1798 //=============================================================================
1799 
1800 
1801 // Emit exception handler code.
1802 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1803   Register temp_reg = G3;
1804   AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1805   MacroAssembler _masm(&cbuf);
1806 
1807   address base = __ start_a_stub(size_exception_handler());
1808   if (base == NULL) {
1809     ciEnv::current()->record_failure("CodeCache is full");
1810     return 0;  // CodeBuffer::expand failed
1811   }
1812 
1813   int offset = __ offset();
1814 
1815   __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1816   __ delayed()->nop();
1817 
1818   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1819 
1820   __ end_a_stub();
1821 
1822   return offset;
1823 }
1824 
1825 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1826   // Can't use any of the current frame's registers as we may have deopted
1827   // at a poll and everything (including G3) can be live.
1828   Register temp_reg = L0;
1829   AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1830   MacroAssembler _masm(&cbuf);
1831 
1832   address base = __ start_a_stub(size_deopt_handler());
1833   if (base == NULL) {
1834     ciEnv::current()->record_failure("CodeCache is full");
1835     return 0;  // CodeBuffer::expand failed
1836   }
1837 
1838   int offset = __ offset();
1839   __ save_frame(0);
1840   __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1841   __ delayed()->restore();
1842 
1843   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1844 
1845   __ end_a_stub();
1846   return offset;
1847 
1848 }
1849 
1850 // Given a register encoding, produce a Integer Register object
1851 static Register reg_to_register_object(int register_encoding) {
1852   assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1853   return as_Register(register_encoding);
1854 }
1855 
1856 // Given a register encoding, produce a single-precision Float Register object
1857 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1858   assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1859   return as_SingleFloatRegister(register_encoding);
1860 }
1861 
1862 // Given a register encoding, produce a double-precision Float Register object
1863 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1864   assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1865   assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1866   return as_DoubleFloatRegister(register_encoding);
1867 }
1868 
1869 const bool Matcher::match_rule_supported(int opcode) {
1870   if (!has_match_rule(opcode))
1871     return false;
1872 
1873   switch (opcode) {
1874   case Op_CountLeadingZerosI:
1875   case Op_CountLeadingZerosL:
1876   case Op_CountTrailingZerosI:
1877   case Op_CountTrailingZerosL:
1878   case Op_PopCountI:
1879   case Op_PopCountL:
1880     if (!UsePopCountInstruction)
1881       return false;
1882   case Op_CompareAndSwapL:
1883 #ifdef _LP64
1884   case Op_CompareAndSwapP:
1885 #endif
1886     if (!VM_Version::supports_cx8())
1887       return false;
1888     break;
1889   }
1890 
1891   return true;  // Per default match rules are supported.
1892 }
1893 
1894 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1895 
1896   // TODO
1897   // identify extra cases that we might want to provide match rules for
1898   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1899   bool ret_value = match_rule_supported(opcode);
1900   // Add rules here.
1901 
1902   return ret_value;  // Per default match rules are supported.
1903 }
1904 
1905 const bool Matcher::has_predicated_vectors(void) {
1906   return false;
1907 }
1908 
1909 const int Matcher::float_pressure(int default_pressure_threshold) {
1910   return default_pressure_threshold;
1911 }
1912 
1913 int Matcher::regnum_to_fpu_offset(int regnum) {
1914   return regnum - 32; // The FP registers are in the second chunk
1915 }
1916 
1917 #ifdef ASSERT
1918 address last_rethrow = NULL;  // debugging aid for Rethrow encoding
1919 #endif
1920 
1921 // Vector width in bytes
1922 const int Matcher::vector_width_in_bytes(BasicType bt) {
1923   assert(MaxVectorSize == 8, "");
1924   return 8;
1925 }
1926 
1927 // Vector ideal reg
1928 const int Matcher::vector_ideal_reg(int size) {
1929   assert(MaxVectorSize == 8, "");
1930   return Op_RegD;
1931 }
1932 
1933 const int Matcher::vector_shift_count_ideal_reg(int size) {
1934   fatal("vector shift is not supported");
1935   return Node::NotAMachineReg;
1936 }
1937 
1938 // Limits on vector size (number of elements) loaded into vector.
1939 const int Matcher::max_vector_size(const BasicType bt) {
1940   assert(is_java_primitive(bt), "only primitive type vectors");
1941   return vector_width_in_bytes(bt)/type2aelembytes(bt);
1942 }
1943 
1944 const int Matcher::min_vector_size(const BasicType bt) {
1945   return max_vector_size(bt); // Same as max.
1946 }
1947 
1948 // SPARC doesn't support misaligned vectors store/load.
1949 const bool Matcher::misaligned_vectors_ok() {
1950   return false;
1951 }
1952 
1953 // Current (2013) SPARC platforms need to read original key
1954 // to construct decryption expanded key
1955 const bool Matcher::pass_original_key_for_aes() {
1956   return true;
1957 }
1958 
1959 // USII supports fxtof through the whole range of number, USIII doesn't
1960 const bool Matcher::convL2FSupported(void) {
1961   return VM_Version::has_fast_fxtof();
1962 }
1963 
1964 // Is this branch offset short enough that a short branch can be used?
1965 //
1966 // NOTE: If the platform does not provide any short branch variants, then
1967 //       this method should return false for offset 0.
1968 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1969   // The passed offset is relative to address of the branch.
1970   // Don't need to adjust the offset.
1971   return UseCBCond && Assembler::is_simm12(offset);
1972 }
1973 
1974 const bool Matcher::isSimpleConstant64(jlong value) {
1975   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1976   // Depends on optimizations in MacroAssembler::setx.
1977   int hi = (int)(value >> 32);
1978   int lo = (int)(value & ~0);
1979   return (hi == 0) || (hi == -1) || (lo == 0);
1980 }
1981 
1982 // No scaling for the parameter the ClearArray node.
1983 const bool Matcher::init_array_count_is_in_bytes = true;
1984 
1985 // No additional cost for CMOVL.
1986 const int Matcher::long_cmove_cost() { return 0; }
1987 
1988 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1989 const int Matcher::float_cmove_cost() {
1990   return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1991 }
1992 
1993 // Does the CPU require late expand (see block.cpp for description of late expand)?
1994 const bool Matcher::require_postalloc_expand = false;
1995 
1996 // Do we need to mask the count passed to shift instructions or does
1997 // the cpu only look at the lower 5/6 bits anyway?
1998 const bool Matcher::need_masked_shift_count = false;
1999 
2000 bool Matcher::narrow_oop_use_complex_address() {
2001   NOT_LP64(ShouldNotCallThis());
2002   assert(UseCompressedOops, "only for compressed oops code");
2003   return false;
2004 }
2005 
2006 bool Matcher::narrow_klass_use_complex_address() {
2007   NOT_LP64(ShouldNotCallThis());
2008   assert(UseCompressedClassPointers, "only for compressed klass code");
2009   return false;
2010 }
2011 
2012 // Is it better to copy float constants, or load them directly from memory?
2013 // Intel can load a float constant from a direct address, requiring no
2014 // extra registers.  Most RISCs will have to materialize an address into a
2015 // register first, so they would do better to copy the constant from stack.
2016 const bool Matcher::rematerialize_float_constants = false;
2017 
2018 // If CPU can load and store mis-aligned doubles directly then no fixup is
2019 // needed.  Else we split the double into 2 integer pieces and move it
2020 // piece-by-piece.  Only happens when passing doubles into C code as the
2021 // Java calling convention forces doubles to be aligned.
2022 #ifdef _LP64
2023 const bool Matcher::misaligned_doubles_ok = true;
2024 #else
2025 const bool Matcher::misaligned_doubles_ok = false;
2026 #endif
2027 
2028 // No-op on SPARC.
2029 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2030 }
2031 
2032 // Advertise here if the CPU requires explicit rounding operations
2033 // to implement the UseStrictFP mode.
2034 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2035 
2036 // Are floats converted to double when stored to stack during deoptimization?
2037 // Sparc does not handle callee-save floats.
2038 bool Matcher::float_in_double() { return false; }
2039 
2040 // Do ints take an entire long register or just half?
2041 // Note that we if-def off of _LP64.
2042 // The relevant question is how the int is callee-saved.  In _LP64
2043 // the whole long is written but de-opt'ing will have to extract
2044 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
2045 #ifdef _LP64
2046 const bool Matcher::int_in_long = true;
2047 #else
2048 const bool Matcher::int_in_long = false;
2049 #endif
2050 
2051 // Return whether or not this register is ever used as an argument.  This
2052 // function is used on startup to build the trampoline stubs in generateOptoStub.
2053 // Registers not mentioned will be killed by the VM call in the trampoline, and
2054 // arguments in those registers not be available to the callee.
2055 bool Matcher::can_be_java_arg( int reg ) {
2056   // Standard sparc 6 args in registers
2057   if( reg == R_I0_num ||
2058       reg == R_I1_num ||
2059       reg == R_I2_num ||
2060       reg == R_I3_num ||
2061       reg == R_I4_num ||
2062       reg == R_I5_num ) return true;
2063 #ifdef _LP64
2064   // 64-bit builds can pass 64-bit pointers and longs in
2065   // the high I registers
2066   if( reg == R_I0H_num ||
2067       reg == R_I1H_num ||
2068       reg == R_I2H_num ||
2069       reg == R_I3H_num ||
2070       reg == R_I4H_num ||
2071       reg == R_I5H_num ) return true;
2072 
2073   if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2074     return true;
2075   }
2076 
2077 #else
2078   // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2079   // Longs cannot be passed in O regs, because O regs become I regs
2080   // after a 'save' and I regs get their high bits chopped off on
2081   // interrupt.
2082   if( reg == R_G1H_num || reg == R_G1_num ) return true;
2083   if( reg == R_G4H_num || reg == R_G4_num ) return true;
2084 #endif
2085   // A few float args in registers
2086   if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2087 
2088   return false;
2089 }
2090 
2091 bool Matcher::is_spillable_arg( int reg ) {
2092   return can_be_java_arg(reg);
2093 }
2094 
2095 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2096   // Use hardware SDIVX instruction when it is
2097   // faster than a code which use multiply.
2098   return VM_Version::has_fast_idiv();
2099 }
2100 
2101 // Register for DIVI projection of divmodI
2102 RegMask Matcher::divI_proj_mask() {
2103   ShouldNotReachHere();
2104   return RegMask();
2105 }
2106 
2107 // Register for MODI projection of divmodI
2108 RegMask Matcher::modI_proj_mask() {
2109   ShouldNotReachHere();
2110   return RegMask();
2111 }
2112 
2113 // Register for DIVL projection of divmodL
2114 RegMask Matcher::divL_proj_mask() {
2115   ShouldNotReachHere();
2116   return RegMask();
2117 }
2118 
2119 // Register for MODL projection of divmodL
2120 RegMask Matcher::modL_proj_mask() {
2121   ShouldNotReachHere();
2122   return RegMask();
2123 }
2124 
2125 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2126   return L7_REGP_mask();
2127 }
2128 
2129 
2130 const bool Matcher::convi2l_type_required = true;
2131 
2132 // Should the Matcher clone shifts on addressing modes, expecting them
2133 // to be subsumed into complex addressing expressions or compute them
2134 // into registers?
2135 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2136   return clone_base_plus_offset_address(m, mstack, address_visited);
2137 }
2138 
2139 void Compile::reshape_address(AddPNode* addp) {
2140 }
2141 
2142 %}
2143 
2144 
2145 // The intptr_t operand types, defined by textual substitution.
2146 // (Cf. opto/type.hpp.  This lets us avoid many, many other ifdefs.)
2147 #ifdef _LP64
2148 #define immX      immL
2149 #define immX13    immL13
2150 #define immX13m7  immL13m7
2151 #define iRegX     iRegL
2152 #define g1RegX    g1RegL
2153 #else
2154 #define immX      immI
2155 #define immX13    immI13
2156 #define immX13m7  immI13m7
2157 #define iRegX     iRegI
2158 #define g1RegX    g1RegI
2159 #endif
2160 
2161 //----------ENCODING BLOCK-----------------------------------------------------
2162 // This block specifies the encoding classes used by the compiler to output
2163 // byte streams.  Encoding classes are parameterized macros used by
2164 // Machine Instruction Nodes in order to generate the bit encoding of the
2165 // instruction.  Operands specify their base encoding interface with the
2166 // interface keyword.  There are currently supported four interfaces,
2167 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
2168 // operand to generate a function which returns its register number when
2169 // queried.   CONST_INTER causes an operand to generate a function which
2170 // returns the value of the constant when queried.  MEMORY_INTER causes an
2171 // operand to generate four functions which return the Base Register, the
2172 // Index Register, the Scale Value, and the Offset Value of the operand when
2173 // queried.  COND_INTER causes an operand to generate six functions which
2174 // return the encoding code (ie - encoding bits for the instruction)
2175 // associated with each basic boolean condition for a conditional instruction.
2176 //
2177 // Instructions specify two basic values for encoding.  Again, a function
2178 // is available to check if the constant displacement is an oop. They use the
2179 // ins_encode keyword to specify their encoding classes (which must be
2180 // a sequence of enc_class names, and their parameters, specified in
2181 // the encoding block), and they use the
2182 // opcode keyword to specify, in order, their primary, secondary, and
2183 // tertiary opcode.  Only the opcode sections which a particular instruction
2184 // needs for encoding need to be specified.
2185 encode %{
2186   enc_class enc_untested %{
2187 #ifdef ASSERT
2188     MacroAssembler _masm(&cbuf);
2189     __ untested("encoding");
2190 #endif
2191   %}
2192 
2193   enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2194     emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2195                        $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2196   %}
2197 
2198   enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2199     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2200                        $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2201   %}
2202 
2203   enc_class form3_mem_prefetch_read( memory mem ) %{
2204     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2205                        $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2206   %}
2207 
2208   enc_class form3_mem_prefetch_write( memory mem ) %{
2209     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2210                        $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2211   %}
2212 
2213   enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2214     assert(Assembler::is_simm13($mem$$disp  ), "need disp and disp+4");
2215     assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2216     guarantee($mem$$index == R_G0_enc, "double index?");
2217     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2218     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg );
2219     emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2220     emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2221   %}
2222 
2223   enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2224     assert(Assembler::is_simm13($mem$$disp  ), "need disp and disp+4");
2225     assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2226     guarantee($mem$$index == R_G0_enc, "double index?");
2227     // Load long with 2 instructions
2228     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg+0 );
2229     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2230   %}
2231 
2232   //%%% form3_mem_plus_4_reg is a hack--get rid of it
2233   enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2234     guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2235     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2236   %}
2237 
2238   enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2239     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2240     if( $rs2$$reg != $rd$$reg )
2241       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2242   %}
2243 
2244   // Target lo half of long
2245   enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2246     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2247     if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2248       emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2249   %}
2250 
2251   // Source lo half of long
2252   enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2253     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2254     if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2255       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2256   %}
2257 
2258   // Target hi half of long
2259   enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2260     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2261   %}
2262 
2263   // Source lo half of long, and leave it sign extended.
2264   enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2265     // Sign extend low half
2266     emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2267   %}
2268 
2269   // Source hi half of long, and leave it sign extended.
2270   enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2271     // Shift high half to low half
2272     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2273   %}
2274 
2275   // Source hi half of long
2276   enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2277     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2278     if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2279       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2280   %}
2281 
2282   enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2283     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2284   %}
2285 
2286   enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2287     emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, 0, 0, $src$$reg );
2288     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2289   %}
2290 
2291   enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2292     emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2293     // clear if nothing else is happening
2294     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  0 );
2295     // blt,a,pn done
2296     emit2_19    ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2297     // mov dst,-1 in delay slot
2298     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2299   %}
2300 
2301   enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2302     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2303   %}
2304 
2305   enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2306     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2307   %}
2308 
2309   enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2310     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2311   %}
2312 
2313   enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2314     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2315   %}
2316 
2317   enc_class move_return_pc_to_o1() %{
2318     emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2319   %}
2320 
2321 #ifdef _LP64
2322   /* %%% merge with enc_to_bool */
2323   enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2324     MacroAssembler _masm(&cbuf);
2325 
2326     Register   src_reg = reg_to_register_object($src$$reg);
2327     Register   dst_reg = reg_to_register_object($dst$$reg);
2328     __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2329   %}
2330 #endif
2331 
2332   enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2333     // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2334     MacroAssembler _masm(&cbuf);
2335 
2336     Register   p_reg = reg_to_register_object($p$$reg);
2337     Register   q_reg = reg_to_register_object($q$$reg);
2338     Register   y_reg = reg_to_register_object($y$$reg);
2339     Register tmp_reg = reg_to_register_object($tmp$$reg);
2340 
2341     __ subcc( p_reg, q_reg,   p_reg );
2342     __ add  ( p_reg, y_reg, tmp_reg );
2343     __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2344   %}
2345 
2346   enc_class form_d2i_helper(regD src, regF dst) %{
2347     // fcmp %fcc0,$src,$src
2348     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2349     // branch %fcc0 not-nan, predict taken
2350     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2351     // fdtoi $src,$dst
2352     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtoi_opf, $src$$reg );
2353     // fitos $dst,$dst (if nan)
2354     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );
2355     // clear $dst (if nan)
2356     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2357     // carry on here...
2358   %}
2359 
2360   enc_class form_d2l_helper(regD src, regD dst) %{
2361     // fcmp %fcc0,$src,$src  check for NAN
2362     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2363     // branch %fcc0 not-nan, predict taken
2364     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2365     // fdtox $src,$dst   convert in delay slot
2366     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtox_opf, $src$$reg );
2367     // fxtod $dst,$dst  (if nan)
2368     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );
2369     // clear $dst (if nan)
2370     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2371     // carry on here...
2372   %}
2373 
2374   enc_class form_f2i_helper(regF src, regF dst) %{
2375     // fcmps %fcc0,$src,$src
2376     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2377     // branch %fcc0 not-nan, predict taken
2378     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2379     // fstoi $src,$dst
2380     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstoi_opf, $src$$reg );
2381     // fitos $dst,$dst (if nan)
2382     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );
2383     // clear $dst (if nan)
2384     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2385     // carry on here...
2386   %}
2387 
2388   enc_class form_f2l_helper(regF src, regD dst) %{
2389     // fcmps %fcc0,$src,$src
2390     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2391     // branch %fcc0 not-nan, predict taken
2392     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2393     // fstox $src,$dst
2394     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstox_opf, $src$$reg );
2395     // fxtod $dst,$dst (if nan)
2396     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );
2397     // clear $dst (if nan)
2398     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2399     // carry on here...
2400   %}
2401 
2402   enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2403   enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2404   enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2405   enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2406 
2407   enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2408 
2409   enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2410   enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2411 
2412   enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2413     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2414   %}
2415 
2416   enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2417     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2418   %}
2419 
2420   enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2421     emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2422   %}
2423 
2424   enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2425     emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2426   %}
2427 
2428   enc_class form3_convI2F(regF rs2, regF rd) %{
2429     emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2430   %}
2431 
2432   // Encloding class for traceable jumps
2433   enc_class form_jmpl(g3RegP dest) %{
2434     emit_jmpl(cbuf, $dest$$reg);
2435   %}
2436 
2437   enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2438     emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2439   %}
2440 
2441   enc_class form2_nop() %{
2442     emit_nop(cbuf);
2443   %}
2444 
2445   enc_class form2_illtrap() %{
2446     emit_illtrap(cbuf);
2447   %}
2448 
2449 
2450   // Compare longs and convert into -1, 0, 1.
2451   enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2452     // CMP $src1,$src2
2453     emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2454     // blt,a,pn done
2455     emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less   , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2456     // mov dst,-1 in delay slot
2457     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2458     // bgt,a,pn done
2459     emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2460     // mov dst,1 in delay slot
2461     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  1 );
2462     // CLR    $dst
2463     emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2464   %}
2465 
2466   enc_class enc_PartialSubtypeCheck() %{
2467     MacroAssembler _masm(&cbuf);
2468     __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2469     __ delayed()->nop();
2470   %}
2471 
2472   enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2473     MacroAssembler _masm(&cbuf);
2474     Label* L = $labl$$label;
2475     Assembler::Predict predict_taken =
2476       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2477 
2478     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2479     __ delayed()->nop();
2480   %}
2481 
2482   enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2483     MacroAssembler _masm(&cbuf);
2484     Label* L = $labl$$label;
2485     Assembler::Predict predict_taken =
2486       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2487 
2488     __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2489     __ delayed()->nop();
2490   %}
2491 
2492   enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2493     int op = (Assembler::arith_op << 30) |
2494              ($dst$$reg << 25) |
2495              (Assembler::movcc_op3 << 19) |
2496              (1 << 18) |                    // cc2 bit for 'icc'
2497              ($cmp$$cmpcode << 14) |
2498              (0 << 13) |                    // select register move
2499              ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc' or 'xcc'
2500              ($src$$reg << 0);
2501     cbuf.insts()->emit_int32(op);
2502   %}
2503 
2504   enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2505     int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2506     int op = (Assembler::arith_op << 30) |
2507              ($dst$$reg << 25) |
2508              (Assembler::movcc_op3 << 19) |
2509              (1 << 18) |                    // cc2 bit for 'icc'
2510              ($cmp$$cmpcode << 14) |
2511              (1 << 13) |                    // select immediate move
2512              ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc'
2513              (simm11 << 0);
2514     cbuf.insts()->emit_int32(op);
2515   %}
2516 
2517   enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2518     int op = (Assembler::arith_op << 30) |
2519              ($dst$$reg << 25) |
2520              (Assembler::movcc_op3 << 19) |
2521              (0 << 18) |                    // cc2 bit for 'fccX'
2522              ($cmp$$cmpcode << 14) |
2523              (0 << 13) |                    // select register move
2524              ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
2525              ($src$$reg << 0);
2526     cbuf.insts()->emit_int32(op);
2527   %}
2528 
2529   enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2530     int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2531     int op = (Assembler::arith_op << 30) |
2532              ($dst$$reg << 25) |
2533              (Assembler::movcc_op3 << 19) |
2534              (0 << 18) |                    // cc2 bit for 'fccX'
2535              ($cmp$$cmpcode << 14) |
2536              (1 << 13) |                    // select immediate move
2537              ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
2538              (simm11 << 0);
2539     cbuf.insts()->emit_int32(op);
2540   %}
2541 
2542   enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2543     int op = (Assembler::arith_op << 30) |
2544              ($dst$$reg << 25) |
2545              (Assembler::fpop2_op3 << 19) |
2546              (0 << 18) |
2547              ($cmp$$cmpcode << 14) |
2548              (1 << 13) |                    // select register move
2549              ($pcc$$constant << 11) |       // cc1-cc0 bits for 'icc' or 'xcc'
2550              ($primary << 5) |              // select single, double or quad
2551              ($src$$reg << 0);
2552     cbuf.insts()->emit_int32(op);
2553   %}
2554 
2555   enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2556     int op = (Assembler::arith_op << 30) |
2557              ($dst$$reg << 25) |
2558              (Assembler::fpop2_op3 << 19) |
2559              (0 << 18) |
2560              ($cmp$$cmpcode << 14) |
2561              ($fcc$$reg << 11) |            // cc2-cc0 bits for 'fccX'
2562              ($primary << 5) |              // select single, double or quad
2563              ($src$$reg << 0);
2564     cbuf.insts()->emit_int32(op);
2565   %}
2566 
2567   // Used by the MIN/MAX encodings.  Same as a CMOV, but
2568   // the condition comes from opcode-field instead of an argument.
2569   enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2570     int op = (Assembler::arith_op << 30) |
2571              ($dst$$reg << 25) |
2572              (Assembler::movcc_op3 << 19) |
2573              (1 << 18) |                    // cc2 bit for 'icc'
2574              ($primary << 14) |
2575              (0 << 13) |                    // select register move
2576              (0 << 11) |                    // cc1, cc0 bits for 'icc'
2577              ($src$$reg << 0);
2578     cbuf.insts()->emit_int32(op);
2579   %}
2580 
2581   enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2582     int op = (Assembler::arith_op << 30) |
2583              ($dst$$reg << 25) |
2584              (Assembler::movcc_op3 << 19) |
2585              (6 << 16) |                    // cc2 bit for 'xcc'
2586              ($primary << 14) |
2587              (0 << 13) |                    // select register move
2588              (0 << 11) |                    // cc1, cc0 bits for 'icc'
2589              ($src$$reg << 0);
2590     cbuf.insts()->emit_int32(op);
2591   %}
2592 
2593   enc_class Set13( immI13 src, iRegI rd ) %{
2594     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2595   %}
2596 
2597   enc_class SetHi22( immI src, iRegI rd ) %{
2598     emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2599   %}
2600 
2601   enc_class Set32( immI src, iRegI rd ) %{
2602     MacroAssembler _masm(&cbuf);
2603     __ set($src$$constant, reg_to_register_object($rd$$reg));
2604   %}
2605 
2606   enc_class call_epilog %{
2607     if( VerifyStackAtCalls ) {
2608       MacroAssembler _masm(&cbuf);
2609       int framesize = ra_->C->frame_size_in_bytes();
2610       Register temp_reg = G3;
2611       __ add(SP, framesize, temp_reg);
2612       __ cmp(temp_reg, FP);
2613       __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2614     }
2615   %}
2616 
2617   // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2618   // to G1 so the register allocator will not have to deal with the misaligned register
2619   // pair.
2620   enc_class adjust_long_from_native_call %{
2621 #ifndef _LP64
2622     if (returns_long()) {
2623       //    sllx  O0,32,O0
2624       emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2625       //    srl   O1,0,O1
2626       emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2627       //    or    O0,O1,G1
2628       emit3       ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2629     }
2630 #endif
2631   %}
2632 
2633   enc_class Java_To_Runtime (method meth) %{    // CALL Java_To_Runtime
2634     // CALL directly to the runtime
2635     // The user of this is responsible for ensuring that R_L7 is empty (killed).
2636     emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true);
2637   %}
2638 
2639   enc_class preserve_SP %{
2640     MacroAssembler _masm(&cbuf);
2641     __ mov(SP, L7_mh_SP_save);
2642   %}
2643 
2644   enc_class restore_SP %{
2645     MacroAssembler _masm(&cbuf);
2646     __ mov(L7_mh_SP_save, SP);
2647   %}
2648 
2649   enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL
2650     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
2651     // who we intended to call.
2652     if (!_method) {
2653       emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec());
2654     } else {
2655       int method_index = resolved_method_index(cbuf);
2656       RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2657                                                   : static_call_Relocation::spec(method_index);
2658       emit_call_reloc(cbuf, $meth$$method, rspec);
2659 
2660       // Emit stub for static call.
2661       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2662       // Stub does not fit into scratch buffer if TraceJumps is enabled
2663       if (stub == NULL && !(TraceJumps && Compile::current()->in_scratch_emit_size())) {
2664         ciEnv::current()->record_failure("CodeCache is full");
2665         return;
2666       }
2667     }
2668   %}
2669 
2670   enc_class Java_Dynamic_Call (method meth) %{    // JAVA DYNAMIC CALL
2671     MacroAssembler _masm(&cbuf);
2672     __ set_inst_mark();
2673     int vtable_index = this->_vtable_index;
2674     // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2675     if (vtable_index < 0) {
2676       // must be invalid_vtable_index, not nonvirtual_vtable_index
2677       assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2678       Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2679       assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2680       assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2681       __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf));
2682     } else {
2683       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2684       // Just go thru the vtable
2685       // get receiver klass (receiver already checked for non-null)
2686       // If we end up going thru a c2i adapter interpreter expects method in G5
2687       int off = __ offset();
2688       __ load_klass(O0, G3_scratch);
2689       int klass_load_size;
2690       if (UseCompressedClassPointers) {
2691         assert(Universe::heap() != NULL, "java heap should be initialized");
2692         klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2693       } else {
2694         klass_load_size = 1*BytesPerInstWord;
2695       }
2696       int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
2697       int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2698       if (Assembler::is_simm13(v_off)) {
2699         __ ld_ptr(G3, v_off, G5_method);
2700       } else {
2701         // Generate 2 instructions
2702         __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2703         __ or3(G5_method, v_off & 0x3ff, G5_method);
2704         // ld_ptr, set_hi, set
2705         assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2706                "Unexpected instruction size(s)");
2707         __ ld_ptr(G3, G5_method, G5_method);
2708       }
2709       // NOTE: for vtable dispatches, the vtable entry will never be null.
2710       // However it may very well end up in handle_wrong_method if the
2711       // method is abstract for the particular class.
2712       __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2713       // jump to target (either compiled code or c2iadapter)
2714       __ jmpl(G3_scratch, G0, O7);
2715       __ delayed()->nop();
2716     }
2717   %}
2718 
2719   enc_class Java_Compiled_Call (method meth) %{    // JAVA COMPILED CALL
2720     MacroAssembler _masm(&cbuf);
2721 
2722     Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2723     Register temp_reg = G3;   // caller must kill G3!  We cannot reuse G5_ic_reg here because
2724                               // we might be calling a C2I adapter which needs it.
2725 
2726     assert(temp_reg != G5_ic_reg, "conflicting registers");
2727     // Load nmethod
2728     __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2729 
2730     // CALL to compiled java, indirect the contents of G3
2731     __ set_inst_mark();
2732     __ callr(temp_reg, G0);
2733     __ delayed()->nop();
2734   %}
2735 
2736 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2737     MacroAssembler _masm(&cbuf);
2738     Register Rdividend = reg_to_register_object($src1$$reg);
2739     Register Rdivisor = reg_to_register_object($src2$$reg);
2740     Register Rresult = reg_to_register_object($dst$$reg);
2741 
2742     __ sra(Rdivisor, 0, Rdivisor);
2743     __ sra(Rdividend, 0, Rdividend);
2744     __ sdivx(Rdividend, Rdivisor, Rresult);
2745 %}
2746 
2747 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2748     MacroAssembler _masm(&cbuf);
2749 
2750     Register Rdividend = reg_to_register_object($src1$$reg);
2751     int divisor = $imm$$constant;
2752     Register Rresult = reg_to_register_object($dst$$reg);
2753 
2754     __ sra(Rdividend, 0, Rdividend);
2755     __ sdivx(Rdividend, divisor, Rresult);
2756 %}
2757 
2758 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2759     MacroAssembler _masm(&cbuf);
2760     Register Rsrc1 = reg_to_register_object($src1$$reg);
2761     Register Rsrc2 = reg_to_register_object($src2$$reg);
2762     Register Rdst  = reg_to_register_object($dst$$reg);
2763 
2764     __ sra( Rsrc1, 0, Rsrc1 );
2765     __ sra( Rsrc2, 0, Rsrc2 );
2766     __ mulx( Rsrc1, Rsrc2, Rdst );
2767     __ srlx( Rdst, 32, Rdst );
2768 %}
2769 
2770 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2771     MacroAssembler _masm(&cbuf);
2772     Register Rdividend = reg_to_register_object($src1$$reg);
2773     Register Rdivisor = reg_to_register_object($src2$$reg);
2774     Register Rresult = reg_to_register_object($dst$$reg);
2775     Register Rscratch = reg_to_register_object($scratch$$reg);
2776 
2777     assert(Rdividend != Rscratch, "");
2778     assert(Rdivisor  != Rscratch, "");
2779 
2780     __ sra(Rdividend, 0, Rdividend);
2781     __ sra(Rdivisor, 0, Rdivisor);
2782     __ sdivx(Rdividend, Rdivisor, Rscratch);
2783     __ mulx(Rscratch, Rdivisor, Rscratch);
2784     __ sub(Rdividend, Rscratch, Rresult);
2785 %}
2786 
2787 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2788     MacroAssembler _masm(&cbuf);
2789 
2790     Register Rdividend = reg_to_register_object($src1$$reg);
2791     int divisor = $imm$$constant;
2792     Register Rresult = reg_to_register_object($dst$$reg);
2793     Register Rscratch = reg_to_register_object($scratch$$reg);
2794 
2795     assert(Rdividend != Rscratch, "");
2796 
2797     __ sra(Rdividend, 0, Rdividend);
2798     __ sdivx(Rdividend, divisor, Rscratch);
2799     __ mulx(Rscratch, divisor, Rscratch);
2800     __ sub(Rdividend, Rscratch, Rresult);
2801 %}
2802 
2803 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2804     MacroAssembler _masm(&cbuf);
2805 
2806     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2807     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2808 
2809     __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2810 %}
2811 
2812 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2813     MacroAssembler _masm(&cbuf);
2814 
2815     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2816     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2817 
2818     __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2819 %}
2820 
2821 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2822     MacroAssembler _masm(&cbuf);
2823 
2824     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2825     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2826 
2827     __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2828 %}
2829 
2830 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2831     MacroAssembler _masm(&cbuf);
2832 
2833     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2834     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2835 
2836     __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2837 %}
2838 
2839 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2840     MacroAssembler _masm(&cbuf);
2841 
2842     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2843     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2844 
2845     __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2846 %}
2847 
2848 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2849     MacroAssembler _masm(&cbuf);
2850 
2851     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2852     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2853 
2854     __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2855 %}
2856 
2857 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2858     MacroAssembler _masm(&cbuf);
2859 
2860     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2861     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2862 
2863     __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2864 %}
2865 
2866 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2867     MacroAssembler _masm(&cbuf);
2868 
2869     Register Roop  = reg_to_register_object($oop$$reg);
2870     Register Rbox  = reg_to_register_object($box$$reg);
2871     Register Rscratch = reg_to_register_object($scratch$$reg);
2872     Register Rmark =    reg_to_register_object($scratch2$$reg);
2873 
2874     assert(Roop  != Rscratch, "");
2875     assert(Roop  != Rmark, "");
2876     assert(Rbox  != Rscratch, "");
2877     assert(Rbox  != Rmark, "");
2878 
2879     __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2880 %}
2881 
2882 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2883     MacroAssembler _masm(&cbuf);
2884 
2885     Register Roop  = reg_to_register_object($oop$$reg);
2886     Register Rbox  = reg_to_register_object($box$$reg);
2887     Register Rscratch = reg_to_register_object($scratch$$reg);
2888     Register Rmark =    reg_to_register_object($scratch2$$reg);
2889 
2890     assert(Roop  != Rscratch, "");
2891     assert(Roop  != Rmark, "");
2892     assert(Rbox  != Rscratch, "");
2893     assert(Rbox  != Rmark, "");
2894 
2895     __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2896   %}
2897 
2898   enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2899     MacroAssembler _masm(&cbuf);
2900     Register Rmem = reg_to_register_object($mem$$reg);
2901     Register Rold = reg_to_register_object($old$$reg);
2902     Register Rnew = reg_to_register_object($new$$reg);
2903 
2904     __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2905     __ cmp( Rold, Rnew );
2906   %}
2907 
2908   enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2909     Register Rmem = reg_to_register_object($mem$$reg);
2910     Register Rold = reg_to_register_object($old$$reg);
2911     Register Rnew = reg_to_register_object($new$$reg);
2912 
2913     MacroAssembler _masm(&cbuf);
2914     __ mov(Rnew, O7);
2915     __ casx(Rmem, Rold, O7);
2916     __ cmp( Rold, O7 );
2917   %}
2918 
2919   // raw int cas, used for compareAndSwap
2920   enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2921     Register Rmem = reg_to_register_object($mem$$reg);
2922     Register Rold = reg_to_register_object($old$$reg);
2923     Register Rnew = reg_to_register_object($new$$reg);
2924 
2925     MacroAssembler _masm(&cbuf);
2926     __ mov(Rnew, O7);
2927     __ cas(Rmem, Rold, O7);
2928     __ cmp( Rold, O7 );
2929   %}
2930 
2931   enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2932     Register Rres = reg_to_register_object($res$$reg);
2933 
2934     MacroAssembler _masm(&cbuf);
2935     __ mov(1, Rres);
2936     __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2937   %}
2938 
2939   enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2940     Register Rres = reg_to_register_object($res$$reg);
2941 
2942     MacroAssembler _masm(&cbuf);
2943     __ mov(1, Rres);
2944     __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2945   %}
2946 
2947   enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2948     MacroAssembler _masm(&cbuf);
2949     Register Rdst = reg_to_register_object($dst$$reg);
2950     FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2951                                      : reg_to_DoubleFloatRegister_object($src1$$reg);
2952     FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2953                                      : reg_to_DoubleFloatRegister_object($src2$$reg);
2954 
2955     // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2956     __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2957   %}
2958 
2959   enc_class enc_rethrow() %{
2960     cbuf.set_insts_mark();
2961     Register temp_reg = G3;
2962     AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
2963     assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
2964     MacroAssembler _masm(&cbuf);
2965 #ifdef ASSERT
2966     __ save_frame(0);
2967     AddressLiteral last_rethrow_addrlit(&last_rethrow);
2968     __ sethi(last_rethrow_addrlit, L1);
2969     Address addr(L1, last_rethrow_addrlit.low10());
2970     __ rdpc(L2);
2971     __ inc(L2, 3 * BytesPerInstWord);  // skip this & 2 more insns to point at jump_to
2972     __ st_ptr(L2, addr);
2973     __ restore();
2974 #endif
2975     __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
2976     __ delayed()->nop();
2977   %}
2978 
2979   enc_class emit_mem_nop() %{
2980     // Generates the instruction LDUXA [o6,g0],#0x82,g0
2981     cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
2982   %}
2983 
2984   enc_class emit_fadd_nop() %{
2985     // Generates the instruction FMOVS f31,f31
2986     cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
2987   %}
2988 
2989   enc_class emit_br_nop() %{
2990     // Generates the instruction BPN,PN .
2991     cbuf.insts()->emit_int32((unsigned int) 0x00400000);
2992   %}
2993 
2994   enc_class enc_membar_acquire %{
2995     MacroAssembler _masm(&cbuf);
2996     __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
2997   %}
2998 
2999   enc_class enc_membar_release %{
3000     MacroAssembler _masm(&cbuf);
3001     __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3002   %}
3003 
3004   enc_class enc_membar_volatile %{
3005     MacroAssembler _masm(&cbuf);
3006     __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3007   %}
3008 
3009 %}
3010 
3011 //----------FRAME--------------------------------------------------------------
3012 // Definition of frame structure and management information.
3013 //
3014 //  S T A C K   L A Y O U T    Allocators stack-slot number
3015 //                             |   (to get allocators register number
3016 //  G  Owned by    |        |  v    add VMRegImpl::stack0)
3017 //  r   CALLER     |        |
3018 //  o     |        +--------+      pad to even-align allocators stack-slot
3019 //  w     V        |  pad0  |        numbers; owned by CALLER
3020 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
3021 //  h     ^        |   in   |  5
3022 //        |        |  args  |  4   Holes in incoming args owned by SELF
3023 //  |     |        |        |  3
3024 //  |     |        +--------+
3025 //  V     |        | old out|      Empty on Intel, window on Sparc
3026 //        |    old |preserve|      Must be even aligned.
3027 //        |     SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3028 //        |        |   in   |  3   area for Intel ret address
3029 //     Owned by    |preserve|      Empty on Sparc.
3030 //       SELF      +--------+
3031 //        |        |  pad2  |  2   pad to align old SP
3032 //        |        +--------+  1
3033 //        |        | locks  |  0
3034 //        |        +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3035 //        |        |  pad1  | 11   pad to align new SP
3036 //        |        +--------+
3037 //        |        |        | 10
3038 //        |        | spills |  9   spills
3039 //        V        |        |  8   (pad0 slot for callee)
3040 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
3041 //        ^        |  out   |  7
3042 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
3043 //     Owned by    +--------+
3044 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
3045 //        |    new |preserve|      Must be even-aligned.
3046 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
3047 //        |        |        |
3048 //
3049 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
3050 //         known from SELF's arguments and the Java calling convention.
3051 //         Region 6-7 is determined per call site.
3052 // Note 2: If the calling convention leaves holes in the incoming argument
3053 //         area, those holes are owned by SELF.  Holes in the outgoing area
3054 //         are owned by the CALLEE.  Holes should not be nessecary in the
3055 //         incoming area, as the Java calling convention is completely under
3056 //         the control of the AD file.  Doubles can be sorted and packed to
3057 //         avoid holes.  Holes in the outgoing arguments may be necessary for
3058 //         varargs C calling conventions.
3059 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
3060 //         even aligned with pad0 as needed.
3061 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
3062 //         region 6-11 is even aligned; it may be padded out more so that
3063 //         the region from SP to FP meets the minimum stack alignment.
3064 
3065 frame %{
3066   // What direction does stack grow in (assumed to be same for native & Java)
3067   stack_direction(TOWARDS_LOW);
3068 
3069   // These two registers define part of the calling convention
3070   // between compiled code and the interpreter.
3071   inline_cache_reg(R_G5);                // Inline Cache Register or Method* for I2C
3072   interpreter_method_oop_reg(R_G5);      // Method Oop Register when calling interpreter
3073 
3074   // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3075   cisc_spilling_operand_name(indOffset);
3076 
3077   // Number of stack slots consumed by a Monitor enter
3078 #ifdef _LP64
3079   sync_stack_slots(2);
3080 #else
3081   sync_stack_slots(1);
3082 #endif
3083 
3084   // Compiled code's Frame Pointer
3085   frame_pointer(R_SP);
3086 
3087   // Stack alignment requirement
3088   stack_alignment(StackAlignmentInBytes);
3089   //  LP64: Alignment size in bytes (128-bit -> 16 bytes)
3090   // !LP64: Alignment size in bytes (64-bit  ->  8 bytes)
3091 
3092   // Number of stack slots between incoming argument block and the start of
3093   // a new frame.  The PROLOG must add this many slots to the stack.  The
3094   // EPILOG must remove this many slots.
3095   in_preserve_stack_slots(0);
3096 
3097   // Number of outgoing stack slots killed above the out_preserve_stack_slots
3098   // for calls to C.  Supports the var-args backing area for register parms.
3099   // ADLC doesn't support parsing expressions, so I folded the math by hand.
3100 #ifdef _LP64
3101   // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3102   varargs_C_out_slots_killed(12);
3103 #else
3104   // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3105   varargs_C_out_slots_killed( 7);
3106 #endif
3107 
3108   // The after-PROLOG location of the return address.  Location of
3109   // return address specifies a type (REG or STACK) and a number
3110   // representing the register number (i.e. - use a register name) or
3111   // stack slot.
3112   return_addr(REG R_I7);          // Ret Addr is in register I7
3113 
3114   // Body of function which returns an OptoRegs array locating
3115   // arguments either in registers or in stack slots for calling
3116   // java
3117   calling_convention %{
3118     (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3119 
3120   %}
3121 
3122   // Body of function which returns an OptoRegs array locating
3123   // arguments either in registers or in stack slots for calling
3124   // C.
3125   c_calling_convention %{
3126     // This is obviously always outgoing
3127     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3128   %}
3129 
3130   // Location of native (C/C++) and interpreter return values.  This is specified to
3131   // be the  same as Java.  In the 32-bit VM, long values are actually returned from
3132   // native calls in O0:O1 and returned to the interpreter in I0:I1.  The copying
3133   // to and from the register pairs is done by the appropriate call and epilog
3134   // opcodes.  This simplifies the register allocator.
3135   c_return_value %{
3136     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3137 #ifdef     _LP64
3138     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_O0_num };
3139     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num,    OptoReg::Bad, R_F1_num, R_O0H_num};
3140     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_I0_num };
3141     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num,    OptoReg::Bad, R_F1_num, R_I0H_num};
3142 #else  // !_LP64
3143     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_G1_num };
3144     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3145     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_G1_num };
3146     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3147 #endif
3148     return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3149                         (is_outgoing?lo_out:lo_in)[ideal_reg] );
3150   %}
3151 
3152   // Location of compiled Java return values.  Same as C
3153   return_value %{
3154     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3155 #ifdef     _LP64
3156     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_O0_num };
3157     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num,    OptoReg::Bad, R_F1_num, R_O0H_num};
3158     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_I0_num };
3159     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num,    OptoReg::Bad, R_F1_num, R_I0H_num};
3160 #else  // !_LP64
3161     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_G1_num };
3162     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3163     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_G1_num };
3164     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3165 #endif
3166     return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3167                         (is_outgoing?lo_out:lo_in)[ideal_reg] );
3168   %}
3169 
3170 %}
3171 
3172 
3173 //----------ATTRIBUTES---------------------------------------------------------
3174 //----------Operand Attributes-------------------------------------------------
3175 op_attrib op_cost(1);          // Required cost attribute
3176 
3177 //----------Instruction Attributes---------------------------------------------
3178 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3179 ins_attrib ins_size(32);           // Required size attribute (in bits)
3180 
3181 // avoid_back_to_back attribute is an expression that must return
3182 // one of the following values defined in MachNode:
3183 // AVOID_NONE   - instruction can be placed anywhere
3184 // AVOID_BEFORE - instruction cannot be placed after an
3185 //                instruction with MachNode::AVOID_AFTER
3186 // AVOID_AFTER  - the next instruction cannot be the one
3187 //                with MachNode::AVOID_BEFORE
3188 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
3189 //                          the same time
3190 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3191 
3192 ins_attrib ins_short_branch(0);    // Required flag: is this instruction a
3193                                    // non-matching short branch variant of some
3194                                                             // long branch?
3195 
3196 //----------OPERANDS-----------------------------------------------------------
3197 // Operand definitions must precede instruction definitions for correct parsing
3198 // in the ADLC because operands constitute user defined types which are used in
3199 // instruction definitions.
3200 
3201 //----------Simple Operands----------------------------------------------------
3202 // Immediate Operands
3203 // Integer Immediate: 32-bit
3204 operand immI() %{
3205   match(ConI);
3206 
3207   op_cost(0);
3208   // formats are generated automatically for constants and base registers
3209   format %{ %}
3210   interface(CONST_INTER);
3211 %}
3212 
3213 // Integer Immediate: 0-bit
3214 operand immI0() %{
3215   predicate(n->get_int() == 0);
3216   match(ConI);
3217   op_cost(0);
3218 
3219   format %{ %}
3220   interface(CONST_INTER);
3221 %}
3222 
3223 // Integer Immediate: 5-bit
3224 operand immI5() %{
3225   predicate(Assembler::is_simm5(n->get_int()));
3226   match(ConI);
3227   op_cost(0);
3228   format %{ %}
3229   interface(CONST_INTER);
3230 %}
3231 
3232 // Integer Immediate: 8-bit
3233 operand immI8() %{
3234   predicate(Assembler::is_simm8(n->get_int()));
3235   match(ConI);
3236   op_cost(0);
3237   format %{ %}
3238   interface(CONST_INTER);
3239 %}
3240 
3241 // Integer Immediate: the value 10
3242 operand immI10() %{
3243   predicate(n->get_int() == 10);
3244   match(ConI);
3245   op_cost(0);
3246 
3247   format %{ %}
3248   interface(CONST_INTER);
3249 %}
3250 
3251 // Integer Immediate: 11-bit
3252 operand immI11() %{
3253   predicate(Assembler::is_simm11(n->get_int()));
3254   match(ConI);
3255   op_cost(0);
3256   format %{ %}
3257   interface(CONST_INTER);
3258 %}
3259 
3260 // Integer Immediate: 13-bit
3261 operand immI13() %{
3262   predicate(Assembler::is_simm13(n->get_int()));
3263   match(ConI);
3264   op_cost(0);
3265 
3266   format %{ %}
3267   interface(CONST_INTER);
3268 %}
3269 
3270 // Integer Immediate: 13-bit minus 7
3271 operand immI13m7() %{
3272   predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3273   match(ConI);
3274   op_cost(0);
3275 
3276   format %{ %}
3277   interface(CONST_INTER);
3278 %}
3279 
3280 // Integer Immediate: 16-bit
3281 operand immI16() %{
3282   predicate(Assembler::is_simm16(n->get_int()));
3283   match(ConI);
3284   op_cost(0);
3285   format %{ %}
3286   interface(CONST_INTER);
3287 %}
3288 
3289 // Integer Immediate: the values 1-31
3290 operand immI_1_31() %{
3291   predicate(n->get_int() >= 1 && n->get_int() <= 31);
3292   match(ConI);
3293   op_cost(0);
3294 
3295   format %{ %}
3296   interface(CONST_INTER);
3297 %}
3298 
3299 // Integer Immediate: the values 32-63
3300 operand immI_32_63() %{
3301   predicate(n->get_int() >= 32 && n->get_int() <= 63);
3302   match(ConI);
3303   op_cost(0);
3304 
3305   format %{ %}
3306   interface(CONST_INTER);
3307 %}
3308 
3309 // Immediates for special shifts (sign extend)
3310 
3311 // Integer Immediate: the value 16
3312 operand immI_16() %{
3313   predicate(n->get_int() == 16);
3314   match(ConI);
3315   op_cost(0);
3316 
3317   format %{ %}
3318   interface(CONST_INTER);
3319 %}
3320 
3321 // Integer Immediate: the value 24
3322 operand immI_24() %{
3323   predicate(n->get_int() == 24);
3324   match(ConI);
3325   op_cost(0);
3326 
3327   format %{ %}
3328   interface(CONST_INTER);
3329 %}
3330 // Integer Immediate: the value 255
3331 operand immI_255() %{
3332   predicate( n->get_int() == 255 );
3333   match(ConI);
3334   op_cost(0);
3335 
3336   format %{ %}
3337   interface(CONST_INTER);
3338 %}
3339 
3340 // Integer Immediate: the value 65535
3341 operand immI_65535() %{
3342   predicate(n->get_int() == 65535);
3343   match(ConI);
3344   op_cost(0);
3345 
3346   format %{ %}
3347   interface(CONST_INTER);
3348 %}
3349 
3350 // Integer Immediate: the values 0-31
3351 operand immU5() %{
3352   predicate(n->get_int() >= 0 && n->get_int() <= 31);
3353   match(ConI);
3354   op_cost(0);
3355 
3356   format %{ %}
3357   interface(CONST_INTER);
3358 %}
3359 
3360 // Integer Immediate: 6-bit
3361 operand immU6() %{
3362   predicate(n->get_int() >= 0 && n->get_int() <= 63);
3363   match(ConI);
3364   op_cost(0);
3365   format %{ %}
3366   interface(CONST_INTER);
3367 %}
3368 
3369 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3370 operand immU12() %{
3371   predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3372   match(ConI);
3373   op_cost(0);
3374 
3375   format %{ %}
3376   interface(CONST_INTER);
3377 %}
3378 
3379 // Integer Immediate non-negative
3380 operand immU31()
3381 %{
3382   predicate(n->get_int() >= 0);
3383   match(ConI);
3384 
3385   op_cost(0);
3386   format %{ %}
3387   interface(CONST_INTER);
3388 %}
3389 
3390 // Long Immediate: the value FF
3391 operand immL_FF() %{
3392   predicate( n->get_long() == 0xFFL );
3393   match(ConL);
3394   op_cost(0);
3395 
3396   format %{ %}
3397   interface(CONST_INTER);
3398 %}
3399 
3400 // Long Immediate: the value FFFF
3401 operand immL_FFFF() %{
3402   predicate( n->get_long() == 0xFFFFL );
3403   match(ConL);
3404   op_cost(0);
3405 
3406   format %{ %}
3407   interface(CONST_INTER);
3408 %}
3409 
3410 // Pointer Immediate: 32 or 64-bit
3411 operand immP() %{
3412   match(ConP);
3413 
3414   op_cost(5);
3415   // formats are generated automatically for constants and base registers
3416   format %{ %}
3417   interface(CONST_INTER);
3418 %}
3419 
3420 #ifdef _LP64
3421 // Pointer Immediate: 64-bit
3422 operand immP_set() %{
3423   predicate(!VM_Version::is_niagara_plus());
3424   match(ConP);
3425 
3426   op_cost(5);
3427   // formats are generated automatically for constants and base registers
3428   format %{ %}
3429   interface(CONST_INTER);
3430 %}
3431 
3432 // Pointer Immediate: 64-bit
3433 // From Niagara2 processors on a load should be better than materializing.
3434 operand immP_load() %{
3435   predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3436   match(ConP);
3437 
3438   op_cost(5);
3439   // formats are generated automatically for constants and base registers
3440   format %{ %}
3441   interface(CONST_INTER);
3442 %}
3443 
3444 // Pointer Immediate: 64-bit
3445 operand immP_no_oop_cheap() %{
3446   predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3447   match(ConP);
3448 
3449   op_cost(5);
3450   // formats are generated automatically for constants and base registers
3451   format %{ %}
3452   interface(CONST_INTER);
3453 %}
3454 #endif
3455 
3456 operand immP13() %{
3457   predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3458   match(ConP);
3459   op_cost(0);
3460 
3461   format %{ %}
3462   interface(CONST_INTER);
3463 %}
3464 
3465 operand immP0() %{
3466   predicate(n->get_ptr() == 0);
3467   match(ConP);
3468   op_cost(0);
3469 
3470   format %{ %}
3471   interface(CONST_INTER);
3472 %}
3473 
3474 operand immP_poll() %{
3475   predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3476   match(ConP);
3477 
3478   // formats are generated automatically for constants and base registers
3479   format %{ %}
3480   interface(CONST_INTER);
3481 %}
3482 
3483 // Pointer Immediate
3484 operand immN()
3485 %{
3486   match(ConN);
3487 
3488   op_cost(10);
3489   format %{ %}
3490   interface(CONST_INTER);
3491 %}
3492 
3493 operand immNKlass()
3494 %{
3495   match(ConNKlass);
3496 
3497   op_cost(10);
3498   format %{ %}
3499   interface(CONST_INTER);
3500 %}
3501 
3502 // NULL Pointer Immediate
3503 operand immN0()
3504 %{
3505   predicate(n->get_narrowcon() == 0);
3506   match(ConN);
3507 
3508   op_cost(0);
3509   format %{ %}
3510   interface(CONST_INTER);
3511 %}
3512 
3513 operand immL() %{
3514   match(ConL);
3515   op_cost(40);
3516   // formats are generated automatically for constants and base registers
3517   format %{ %}
3518   interface(CONST_INTER);
3519 %}
3520 
3521 operand immL0() %{
3522   predicate(n->get_long() == 0L);
3523   match(ConL);
3524   op_cost(0);
3525   // formats are generated automatically for constants and base registers
3526   format %{ %}
3527   interface(CONST_INTER);
3528 %}
3529 
3530 // Integer Immediate: 5-bit
3531 operand immL5() %{
3532   predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3533   match(ConL);
3534   op_cost(0);
3535   format %{ %}
3536   interface(CONST_INTER);
3537 %}
3538 
3539 // Long Immediate: 13-bit
3540 operand immL13() %{
3541   predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3542   match(ConL);
3543   op_cost(0);
3544 
3545   format %{ %}
3546   interface(CONST_INTER);
3547 %}
3548 
3549 // Long Immediate: 13-bit minus 7
3550 operand immL13m7() %{
3551   predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3552   match(ConL);
3553   op_cost(0);
3554 
3555   format %{ %}
3556   interface(CONST_INTER);
3557 %}
3558 
3559 // Long Immediate: low 32-bit mask
3560 operand immL_32bits() %{
3561   predicate(n->get_long() == 0xFFFFFFFFL);
3562   match(ConL);
3563   op_cost(0);
3564 
3565   format %{ %}
3566   interface(CONST_INTER);
3567 %}
3568 
3569 // Long Immediate: cheap (materialize in <= 3 instructions)
3570 operand immL_cheap() %{
3571   predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3572   match(ConL);
3573   op_cost(0);
3574 
3575   format %{ %}
3576   interface(CONST_INTER);
3577 %}
3578 
3579 // Long Immediate: expensive (materialize in > 3 instructions)
3580 operand immL_expensive() %{
3581   predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3582   match(ConL);
3583   op_cost(0);
3584 
3585   format %{ %}
3586   interface(CONST_INTER);
3587 %}
3588 
3589 // Double Immediate
3590 operand immD() %{
3591   match(ConD);
3592 
3593   op_cost(40);
3594   format %{ %}
3595   interface(CONST_INTER);
3596 %}
3597 
3598 // Double Immediate: +0.0d
3599 operand immD0() %{
3600   predicate(jlong_cast(n->getd()) == 0);
3601   match(ConD);
3602 
3603   op_cost(0);
3604   format %{ %}
3605   interface(CONST_INTER);
3606 %}
3607 
3608 // Float Immediate
3609 operand immF() %{
3610   match(ConF);
3611 
3612   op_cost(20);
3613   format %{ %}
3614   interface(CONST_INTER);
3615 %}
3616 
3617 // Float Immediate: +0.0f
3618 operand immF0() %{
3619   predicate(jint_cast(n->getf()) == 0);
3620   match(ConF);
3621 
3622   op_cost(0);
3623   format %{ %}
3624   interface(CONST_INTER);
3625 %}
3626 
3627 // Integer Register Operands
3628 // Integer Register
3629 operand iRegI() %{
3630   constraint(ALLOC_IN_RC(int_reg));
3631   match(RegI);
3632 
3633   match(notemp_iRegI);
3634   match(g1RegI);
3635   match(o0RegI);
3636   match(iRegIsafe);
3637 
3638   format %{ %}
3639   interface(REG_INTER);
3640 %}
3641 
3642 operand notemp_iRegI() %{
3643   constraint(ALLOC_IN_RC(notemp_int_reg));
3644   match(RegI);
3645 
3646   match(o0RegI);
3647 
3648   format %{ %}
3649   interface(REG_INTER);
3650 %}
3651 
3652 operand o0RegI() %{
3653   constraint(ALLOC_IN_RC(o0_regI));
3654   match(iRegI);
3655 
3656   format %{ %}
3657   interface(REG_INTER);
3658 %}
3659 
3660 // Pointer Register
3661 operand iRegP() %{
3662   constraint(ALLOC_IN_RC(ptr_reg));
3663   match(RegP);
3664 
3665   match(lock_ptr_RegP);
3666   match(g1RegP);
3667   match(g2RegP);
3668   match(g3RegP);
3669   match(g4RegP);
3670   match(i0RegP);
3671   match(o0RegP);
3672   match(o1RegP);
3673   match(l7RegP);
3674 
3675   format %{ %}
3676   interface(REG_INTER);
3677 %}
3678 
3679 operand sp_ptr_RegP() %{
3680   constraint(ALLOC_IN_RC(sp_ptr_reg));
3681   match(RegP);
3682   match(iRegP);
3683 
3684   format %{ %}
3685   interface(REG_INTER);
3686 %}
3687 
3688 operand lock_ptr_RegP() %{
3689   constraint(ALLOC_IN_RC(lock_ptr_reg));
3690   match(RegP);
3691   match(i0RegP);
3692   match(o0RegP);
3693   match(o1RegP);
3694   match(l7RegP);
3695 
3696   format %{ %}
3697   interface(REG_INTER);
3698 %}
3699 
3700 operand g1RegP() %{
3701   constraint(ALLOC_IN_RC(g1_regP));
3702   match(iRegP);
3703 
3704   format %{ %}
3705   interface(REG_INTER);
3706 %}
3707 
3708 operand g2RegP() %{
3709   constraint(ALLOC_IN_RC(g2_regP));
3710   match(iRegP);
3711 
3712   format %{ %}
3713   interface(REG_INTER);
3714 %}
3715 
3716 operand g3RegP() %{
3717   constraint(ALLOC_IN_RC(g3_regP));
3718   match(iRegP);
3719 
3720   format %{ %}
3721   interface(REG_INTER);
3722 %}
3723 
3724 operand g1RegI() %{
3725   constraint(ALLOC_IN_RC(g1_regI));
3726   match(iRegI);
3727 
3728   format %{ %}
3729   interface(REG_INTER);
3730 %}
3731 
3732 operand g3RegI() %{
3733   constraint(ALLOC_IN_RC(g3_regI));
3734   match(iRegI);
3735 
3736   format %{ %}
3737   interface(REG_INTER);
3738 %}
3739 
3740 operand g4RegI() %{
3741   constraint(ALLOC_IN_RC(g4_regI));
3742   match(iRegI);
3743 
3744   format %{ %}
3745   interface(REG_INTER);
3746 %}
3747 
3748 operand g4RegP() %{
3749   constraint(ALLOC_IN_RC(g4_regP));
3750   match(iRegP);
3751 
3752   format %{ %}
3753   interface(REG_INTER);
3754 %}
3755 
3756 operand i0RegP() %{
3757   constraint(ALLOC_IN_RC(i0_regP));
3758   match(iRegP);
3759 
3760   format %{ %}
3761   interface(REG_INTER);
3762 %}
3763 
3764 operand o0RegP() %{
3765   constraint(ALLOC_IN_RC(o0_regP));
3766   match(iRegP);
3767 
3768   format %{ %}
3769   interface(REG_INTER);
3770 %}
3771 
3772 operand o1RegP() %{
3773   constraint(ALLOC_IN_RC(o1_regP));
3774   match(iRegP);
3775 
3776   format %{ %}
3777   interface(REG_INTER);
3778 %}
3779 
3780 operand o2RegP() %{
3781   constraint(ALLOC_IN_RC(o2_regP));
3782   match(iRegP);
3783 
3784   format %{ %}
3785   interface(REG_INTER);
3786 %}
3787 
3788 operand o7RegP() %{
3789   constraint(ALLOC_IN_RC(o7_regP));
3790   match(iRegP);
3791 
3792   format %{ %}
3793   interface(REG_INTER);
3794 %}
3795 
3796 operand l7RegP() %{
3797   constraint(ALLOC_IN_RC(l7_regP));
3798   match(iRegP);
3799 
3800   format %{ %}
3801   interface(REG_INTER);
3802 %}
3803 
3804 operand o7RegI() %{
3805   constraint(ALLOC_IN_RC(o7_regI));
3806   match(iRegI);
3807 
3808   format %{ %}
3809   interface(REG_INTER);
3810 %}
3811 
3812 operand iRegN() %{
3813   constraint(ALLOC_IN_RC(int_reg));
3814   match(RegN);
3815 
3816   format %{ %}
3817   interface(REG_INTER);
3818 %}
3819 
3820 // Long Register
3821 operand iRegL() %{
3822   constraint(ALLOC_IN_RC(long_reg));
3823   match(RegL);
3824 
3825   format %{ %}
3826   interface(REG_INTER);
3827 %}
3828 
3829 operand o2RegL() %{
3830   constraint(ALLOC_IN_RC(o2_regL));
3831   match(iRegL);
3832 
3833   format %{ %}
3834   interface(REG_INTER);
3835 %}
3836 
3837 operand o7RegL() %{
3838   constraint(ALLOC_IN_RC(o7_regL));
3839   match(iRegL);
3840 
3841   format %{ %}
3842   interface(REG_INTER);
3843 %}
3844 
3845 operand g1RegL() %{
3846   constraint(ALLOC_IN_RC(g1_regL));
3847   match(iRegL);
3848 
3849   format %{ %}
3850   interface(REG_INTER);
3851 %}
3852 
3853 operand g3RegL() %{
3854   constraint(ALLOC_IN_RC(g3_regL));
3855   match(iRegL);
3856 
3857   format %{ %}
3858   interface(REG_INTER);
3859 %}
3860 
3861 // Int Register safe
3862 // This is 64bit safe
3863 operand iRegIsafe() %{
3864   constraint(ALLOC_IN_RC(long_reg));
3865 
3866   match(iRegI);
3867 
3868   format %{ %}
3869   interface(REG_INTER);
3870 %}
3871 
3872 // Condition Code Flag Register
3873 operand flagsReg() %{
3874   constraint(ALLOC_IN_RC(int_flags));
3875   match(RegFlags);
3876 
3877   format %{ "ccr" %} // both ICC and XCC
3878   interface(REG_INTER);
3879 %}
3880 
3881 // Condition Code Register, unsigned comparisons.
3882 operand flagsRegU() %{
3883   constraint(ALLOC_IN_RC(int_flags));
3884   match(RegFlags);
3885 
3886   format %{ "icc_U" %}
3887   interface(REG_INTER);
3888 %}
3889 
3890 // Condition Code Register, pointer comparisons.
3891 operand flagsRegP() %{
3892   constraint(ALLOC_IN_RC(int_flags));
3893   match(RegFlags);
3894 
3895 #ifdef _LP64
3896   format %{ "xcc_P" %}
3897 #else
3898   format %{ "icc_P" %}
3899 #endif
3900   interface(REG_INTER);
3901 %}
3902 
3903 // Condition Code Register, long comparisons.
3904 operand flagsRegL() %{
3905   constraint(ALLOC_IN_RC(int_flags));
3906   match(RegFlags);
3907 
3908   format %{ "xcc_L" %}
3909   interface(REG_INTER);
3910 %}
3911 
3912 // Condition Code Register, floating comparisons, unordered same as "less".
3913 operand flagsRegF() %{
3914   constraint(ALLOC_IN_RC(float_flags));
3915   match(RegFlags);
3916   match(flagsRegF0);
3917 
3918   format %{ %}
3919   interface(REG_INTER);
3920 %}
3921 
3922 operand flagsRegF0() %{
3923   constraint(ALLOC_IN_RC(float_flag0));
3924   match(RegFlags);
3925 
3926   format %{ %}
3927   interface(REG_INTER);
3928 %}
3929 
3930 
3931 // Condition Code Flag Register used by long compare
3932 operand flagsReg_long_LTGE() %{
3933   constraint(ALLOC_IN_RC(int_flags));
3934   match(RegFlags);
3935   format %{ "icc_LTGE" %}
3936   interface(REG_INTER);
3937 %}
3938 operand flagsReg_long_EQNE() %{
3939   constraint(ALLOC_IN_RC(int_flags));
3940   match(RegFlags);
3941   format %{ "icc_EQNE" %}
3942   interface(REG_INTER);
3943 %}
3944 operand flagsReg_long_LEGT() %{
3945   constraint(ALLOC_IN_RC(int_flags));
3946   match(RegFlags);
3947   format %{ "icc_LEGT" %}
3948   interface(REG_INTER);
3949 %}
3950 
3951 
3952 operand regD() %{
3953   constraint(ALLOC_IN_RC(dflt_reg));
3954   match(RegD);
3955 
3956   match(regD_low);
3957 
3958   format %{ %}
3959   interface(REG_INTER);
3960 %}
3961 
3962 operand regF() %{
3963   constraint(ALLOC_IN_RC(sflt_reg));
3964   match(RegF);
3965 
3966   format %{ %}
3967   interface(REG_INTER);
3968 %}
3969 
3970 operand regD_low() %{
3971   constraint(ALLOC_IN_RC(dflt_low_reg));
3972   match(regD);
3973 
3974   format %{ %}
3975   interface(REG_INTER);
3976 %}
3977 
3978 // Special Registers
3979 
3980 // Method Register
3981 operand inline_cache_regP(iRegP reg) %{
3982   constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3983   match(reg);
3984   format %{ %}
3985   interface(REG_INTER);
3986 %}
3987 
3988 operand interpreter_method_oop_regP(iRegP reg) %{
3989   constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3990   match(reg);
3991   format %{ %}
3992   interface(REG_INTER);
3993 %}
3994 
3995 
3996 //----------Complex Operands---------------------------------------------------
3997 // Indirect Memory Reference
3998 operand indirect(sp_ptr_RegP reg) %{
3999   constraint(ALLOC_IN_RC(sp_ptr_reg));
4000   match(reg);
4001 
4002   op_cost(100);
4003   format %{ "[$reg]" %}
4004   interface(MEMORY_INTER) %{
4005     base($reg);
4006     index(0x0);
4007     scale(0x0);
4008     disp(0x0);
4009   %}
4010 %}
4011 
4012 // Indirect with simm13 Offset
4013 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4014   constraint(ALLOC_IN_RC(sp_ptr_reg));
4015   match(AddP reg offset);
4016 
4017   op_cost(100);
4018   format %{ "[$reg + $offset]" %}
4019   interface(MEMORY_INTER) %{
4020     base($reg);
4021     index(0x0);
4022     scale(0x0);
4023     disp($offset);
4024   %}
4025 %}
4026 
4027 // Indirect with simm13 Offset minus 7
4028 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4029   constraint(ALLOC_IN_RC(sp_ptr_reg));
4030   match(AddP reg offset);
4031 
4032   op_cost(100);
4033   format %{ "[$reg + $offset]" %}
4034   interface(MEMORY_INTER) %{
4035     base($reg);
4036     index(0x0);
4037     scale(0x0);
4038     disp($offset);
4039   %}
4040 %}
4041 
4042 // Note:  Intel has a swapped version also, like this:
4043 //operand indOffsetX(iRegI reg, immP offset) %{
4044 //  constraint(ALLOC_IN_RC(int_reg));
4045 //  match(AddP offset reg);
4046 //
4047 //  op_cost(100);
4048 //  format %{ "[$reg + $offset]" %}
4049 //  interface(MEMORY_INTER) %{
4050 //    base($reg);
4051 //    index(0x0);
4052 //    scale(0x0);
4053 //    disp($offset);
4054 //  %}
4055 //%}
4056 //// However, it doesn't make sense for SPARC, since
4057 // we have no particularly good way to embed oops in
4058 // single instructions.
4059 
4060 // Indirect with Register Index
4061 operand indIndex(iRegP addr, iRegX index) %{
4062   constraint(ALLOC_IN_RC(ptr_reg));
4063   match(AddP addr index);
4064 
4065   op_cost(100);
4066   format %{ "[$addr + $index]" %}
4067   interface(MEMORY_INTER) %{
4068     base($addr);
4069     index($index);
4070     scale(0x0);
4071     disp(0x0);
4072   %}
4073 %}
4074 
4075 //----------Special Memory Operands--------------------------------------------
4076 // Stack Slot Operand - This operand is used for loading and storing temporary
4077 //                      values on the stack where a match requires a value to
4078 //                      flow through memory.
4079 operand stackSlotI(sRegI reg) %{
4080   constraint(ALLOC_IN_RC(stack_slots));
4081   op_cost(100);
4082   //match(RegI);
4083   format %{ "[$reg]" %}
4084   interface(MEMORY_INTER) %{
4085     base(0xE);   // R_SP
4086     index(0x0);
4087     scale(0x0);
4088     disp($reg);  // Stack Offset
4089   %}
4090 %}
4091 
4092 operand stackSlotP(sRegP reg) %{
4093   constraint(ALLOC_IN_RC(stack_slots));
4094   op_cost(100);
4095   //match(RegP);
4096   format %{ "[$reg]" %}
4097   interface(MEMORY_INTER) %{
4098     base(0xE);   // R_SP
4099     index(0x0);
4100     scale(0x0);
4101     disp($reg);  // Stack Offset
4102   %}
4103 %}
4104 
4105 operand stackSlotF(sRegF reg) %{
4106   constraint(ALLOC_IN_RC(stack_slots));
4107   op_cost(100);
4108   //match(RegF);
4109   format %{ "[$reg]" %}
4110   interface(MEMORY_INTER) %{
4111     base(0xE);   // R_SP
4112     index(0x0);
4113     scale(0x0);
4114     disp($reg);  // Stack Offset
4115   %}
4116 %}
4117 operand stackSlotD(sRegD reg) %{
4118   constraint(ALLOC_IN_RC(stack_slots));
4119   op_cost(100);
4120   //match(RegD);
4121   format %{ "[$reg]" %}
4122   interface(MEMORY_INTER) %{
4123     base(0xE);   // R_SP
4124     index(0x0);
4125     scale(0x0);
4126     disp($reg);  // Stack Offset
4127   %}
4128 %}
4129 operand stackSlotL(sRegL reg) %{
4130   constraint(ALLOC_IN_RC(stack_slots));
4131   op_cost(100);
4132   //match(RegL);
4133   format %{ "[$reg]" %}
4134   interface(MEMORY_INTER) %{
4135     base(0xE);   // R_SP
4136     index(0x0);
4137     scale(0x0);
4138     disp($reg);  // Stack Offset
4139   %}
4140 %}
4141 
4142 // Operands for expressing Control Flow
4143 // NOTE:  Label is a predefined operand which should not be redefined in
4144 //        the AD file.  It is generically handled within the ADLC.
4145 
4146 //----------Conditional Branch Operands----------------------------------------
4147 // Comparison Op  - This is the operation of the comparison, and is limited to
4148 //                  the following set of codes:
4149 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4150 //
4151 // Other attributes of the comparison, such as unsignedness, are specified
4152 // by the comparison instruction that sets a condition code flags register.
4153 // That result is represented by a flags operand whose subtype is appropriate
4154 // to the unsignedness (etc.) of the comparison.
4155 //
4156 // Later, the instruction which matches both the Comparison Op (a Bool) and
4157 // the flags (produced by the Cmp) specifies the coding of the comparison op
4158 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4159 
4160 operand cmpOp() %{
4161   match(Bool);
4162 
4163   format %{ "" %}
4164   interface(COND_INTER) %{
4165     equal(0x1);
4166     not_equal(0x9);
4167     less(0x3);
4168     greater_equal(0xB);
4169     less_equal(0x2);
4170     greater(0xA);
4171     overflow(0x7);
4172     no_overflow(0xF);
4173   %}
4174 %}
4175 
4176 // Comparison Op, unsigned
4177 operand cmpOpU() %{
4178   match(Bool);
4179   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4180             n->as_Bool()->_test._test != BoolTest::no_overflow);
4181 
4182   format %{ "u" %}
4183   interface(COND_INTER) %{
4184     equal(0x1);
4185     not_equal(0x9);
4186     less(0x5);
4187     greater_equal(0xD);
4188     less_equal(0x4);
4189     greater(0xC);
4190     overflow(0x7);
4191     no_overflow(0xF);
4192   %}
4193 %}
4194 
4195 // Comparison Op, pointer (same as unsigned)
4196 operand cmpOpP() %{
4197   match(Bool);
4198   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4199             n->as_Bool()->_test._test != BoolTest::no_overflow);
4200 
4201   format %{ "p" %}
4202   interface(COND_INTER) %{
4203     equal(0x1);
4204     not_equal(0x9);
4205     less(0x5);
4206     greater_equal(0xD);
4207     less_equal(0x4);
4208     greater(0xC);
4209     overflow(0x7);
4210     no_overflow(0xF);
4211   %}
4212 %}
4213 
4214 // Comparison Op, branch-register encoding
4215 operand cmpOp_reg() %{
4216   match(Bool);
4217   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4218             n->as_Bool()->_test._test != BoolTest::no_overflow);
4219 
4220   format %{ "" %}
4221   interface(COND_INTER) %{
4222     equal        (0x1);
4223     not_equal    (0x5);
4224     less         (0x3);
4225     greater_equal(0x7);
4226     less_equal   (0x2);
4227     greater      (0x6);
4228     overflow(0x7); // not supported
4229     no_overflow(0xF); // not supported
4230   %}
4231 %}
4232 
4233 // Comparison Code, floating, unordered same as less
4234 operand cmpOpF() %{
4235   match(Bool);
4236   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4237             n->as_Bool()->_test._test != BoolTest::no_overflow);
4238 
4239   format %{ "fl" %}
4240   interface(COND_INTER) %{
4241     equal(0x9);
4242     not_equal(0x1);
4243     less(0x3);
4244     greater_equal(0xB);
4245     less_equal(0xE);
4246     greater(0x6);
4247 
4248     overflow(0x7); // not supported
4249     no_overflow(0xF); // not supported
4250   %}
4251 %}
4252 
4253 // Used by long compare
4254 operand cmpOp_commute() %{
4255   match(Bool);
4256   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4257             n->as_Bool()->_test._test != BoolTest::no_overflow);
4258 
4259   format %{ "" %}
4260   interface(COND_INTER) %{
4261     equal(0x1);
4262     not_equal(0x9);
4263     less(0xA);
4264     greater_equal(0x2);
4265     less_equal(0xB);
4266     greater(0x3);
4267     overflow(0x7);
4268     no_overflow(0xF);
4269   %}
4270 %}
4271 
4272 //----------OPERAND CLASSES----------------------------------------------------
4273 // Operand Classes are groups of operands that are used to simplify
4274 // instruction definitions by not requiring the AD writer to specify separate
4275 // instructions for every form of operand when the instruction accepts
4276 // multiple operand types with the same basic encoding and format.  The classic
4277 // case of this is memory operands.
4278 opclass memory( indirect, indOffset13, indIndex );
4279 opclass indIndexMemory( indIndex );
4280 
4281 //----------PIPELINE-----------------------------------------------------------
4282 pipeline %{
4283 
4284 //----------ATTRIBUTES---------------------------------------------------------
4285 attributes %{
4286   fixed_size_instructions;           // Fixed size instructions
4287   branch_has_delay_slot;             // Branch has delay slot following
4288   max_instructions_per_bundle = 4;   // Up to 4 instructions per bundle
4289   instruction_unit_size = 4;         // An instruction is 4 bytes long
4290   instruction_fetch_unit_size = 16;  // The processor fetches one line
4291   instruction_fetch_units = 1;       // of 16 bytes
4292 
4293   // List of nop instructions
4294   nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4295 %}
4296 
4297 //----------RESOURCES----------------------------------------------------------
4298 // Resources are the functional units available to the machine
4299 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4300 
4301 //----------PIPELINE DESCRIPTION-----------------------------------------------
4302 // Pipeline Description specifies the stages in the machine's pipeline
4303 
4304 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4305 
4306 //----------PIPELINE CLASSES---------------------------------------------------
4307 // Pipeline Classes describe the stages in which input and output are
4308 // referenced by the hardware pipeline.
4309 
4310 // Integer ALU reg-reg operation
4311 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4312     single_instruction;
4313     dst   : E(write);
4314     src1  : R(read);
4315     src2  : R(read);
4316     IALU  : R;
4317 %}
4318 
4319 // Integer ALU reg-reg long operation
4320 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4321     instruction_count(2);
4322     dst   : E(write);
4323     src1  : R(read);
4324     src2  : R(read);
4325     IALU  : R;
4326     IALU  : R;
4327 %}
4328 
4329 // Integer ALU reg-reg long dependent operation
4330 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4331     instruction_count(1); multiple_bundles;
4332     dst   : E(write);
4333     src1  : R(read);
4334     src2  : R(read);
4335     cr    : E(write);
4336     IALU  : R(2);
4337 %}
4338 
4339 // Integer ALU reg-imm operaion
4340 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4341     single_instruction;
4342     dst   : E(write);
4343     src1  : R(read);
4344     IALU  : R;
4345 %}
4346 
4347 // Integer ALU reg-reg operation with condition code
4348 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4349     single_instruction;
4350     dst   : E(write);
4351     cr    : E(write);
4352     src1  : R(read);
4353     src2  : R(read);
4354     IALU  : R;
4355 %}
4356 
4357 // Integer ALU reg-imm operation with condition code
4358 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4359     single_instruction;
4360     dst   : E(write);
4361     cr    : E(write);
4362     src1  : R(read);
4363     IALU  : R;
4364 %}
4365 
4366 // Integer ALU zero-reg operation
4367 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4368     single_instruction;
4369     dst   : E(write);
4370     src2  : R(read);
4371     IALU  : R;
4372 %}
4373 
4374 // Integer ALU zero-reg operation with condition code only
4375 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4376     single_instruction;
4377     cr    : E(write);
4378     src   : R(read);
4379     IALU  : R;
4380 %}
4381 
4382 // Integer ALU reg-reg operation with condition code only
4383 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4384     single_instruction;
4385     cr    : E(write);
4386     src1  : R(read);
4387     src2  : R(read);
4388     IALU  : R;
4389 %}
4390 
4391 // Integer ALU reg-imm operation with condition code only
4392 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4393     single_instruction;
4394     cr    : E(write);
4395     src1  : R(read);
4396     IALU  : R;
4397 %}
4398 
4399 // Integer ALU reg-reg-zero operation with condition code only
4400 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4401     single_instruction;
4402     cr    : E(write);
4403     src1  : R(read);
4404     src2  : R(read);
4405     IALU  : R;
4406 %}
4407 
4408 // Integer ALU reg-imm-zero operation with condition code only
4409 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4410     single_instruction;
4411     cr    : E(write);
4412     src1  : R(read);
4413     IALU  : R;
4414 %}
4415 
4416 // Integer ALU reg-reg operation with condition code, src1 modified
4417 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4418     single_instruction;
4419     cr    : E(write);
4420     src1  : E(write);
4421     src1  : R(read);
4422     src2  : R(read);
4423     IALU  : R;
4424 %}
4425 
4426 // Integer ALU reg-imm operation with condition code, src1 modified
4427 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4428     single_instruction;
4429     cr    : E(write);
4430     src1  : E(write);
4431     src1  : R(read);
4432     IALU  : R;
4433 %}
4434 
4435 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4436     multiple_bundles;
4437     dst   : E(write)+4;
4438     cr    : E(write);
4439     src1  : R(read);
4440     src2  : R(read);
4441     IALU  : R(3);
4442     BR    : R(2);
4443 %}
4444 
4445 // Integer ALU operation
4446 pipe_class ialu_none(iRegI dst) %{
4447     single_instruction;
4448     dst   : E(write);
4449     IALU  : R;
4450 %}
4451 
4452 // Integer ALU reg operation
4453 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4454     single_instruction; may_have_no_code;
4455     dst   : E(write);
4456     src   : R(read);
4457     IALU  : R;
4458 %}
4459 
4460 // Integer ALU reg conditional operation
4461 // This instruction has a 1 cycle stall, and cannot execute
4462 // in the same cycle as the instruction setting the condition
4463 // code. We kludge this by pretending to read the condition code
4464 // 1 cycle earlier, and by marking the functional units as busy
4465 // for 2 cycles with the result available 1 cycle later than
4466 // is really the case.
4467 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4468     single_instruction;
4469     op2_out : C(write);
4470     op1     : R(read);
4471     cr      : R(read);       // This is really E, with a 1 cycle stall
4472     BR      : R(2);
4473     MS      : R(2);
4474 %}
4475 
4476 #ifdef _LP64
4477 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4478     instruction_count(1); multiple_bundles;
4479     dst     : C(write)+1;
4480     src     : R(read)+1;
4481     IALU    : R(1);
4482     BR      : E(2);
4483     MS      : E(2);
4484 %}
4485 #endif
4486 
4487 // Integer ALU reg operation
4488 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4489     single_instruction; may_have_no_code;
4490     dst   : E(write);
4491     src   : R(read);
4492     IALU  : R;
4493 %}
4494 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4495     single_instruction; may_have_no_code;
4496     dst   : E(write);
4497     src   : R(read);
4498     IALU  : R;
4499 %}
4500 
4501 // Two integer ALU reg operations
4502 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4503     instruction_count(2);
4504     dst   : E(write);
4505     src   : R(read);
4506     A0    : R;
4507     A1    : R;
4508 %}
4509 
4510 // Two integer ALU reg operations
4511 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4512     instruction_count(2); may_have_no_code;
4513     dst   : E(write);
4514     src   : R(read);
4515     A0    : R;
4516     A1    : R;
4517 %}
4518 
4519 // Integer ALU imm operation
4520 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4521     single_instruction;
4522     dst   : E(write);
4523     IALU  : R;
4524 %}
4525 
4526 // Integer ALU reg-reg with carry operation
4527 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4528     single_instruction;
4529     dst   : E(write);
4530     src1  : R(read);
4531     src2  : R(read);
4532     IALU  : R;
4533 %}
4534 
4535 // Integer ALU cc operation
4536 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4537     single_instruction;
4538     dst   : E(write);
4539     cc    : R(read);
4540     IALU  : R;
4541 %}
4542 
4543 // Integer ALU cc / second IALU operation
4544 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4545     instruction_count(1); multiple_bundles;
4546     dst   : E(write)+1;
4547     src   : R(read);
4548     IALU  : R;
4549 %}
4550 
4551 // Integer ALU cc / second IALU operation
4552 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4553     instruction_count(1); multiple_bundles;
4554     dst   : E(write)+1;
4555     p     : R(read);
4556     q     : R(read);
4557     IALU  : R;
4558 %}
4559 
4560 // Integer ALU hi-lo-reg operation
4561 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4562     instruction_count(1); multiple_bundles;
4563     dst   : E(write)+1;
4564     IALU  : R(2);
4565 %}
4566 
4567 // Float ALU hi-lo-reg operation (with temp)
4568 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4569     instruction_count(1); multiple_bundles;
4570     dst   : E(write)+1;
4571     IALU  : R(2);
4572 %}
4573 
4574 // Long Constant
4575 pipe_class loadConL( iRegL dst, immL src ) %{
4576     instruction_count(2); multiple_bundles;
4577     dst   : E(write)+1;
4578     IALU  : R(2);
4579     IALU  : R(2);
4580 %}
4581 
4582 // Pointer Constant
4583 pipe_class loadConP( iRegP dst, immP src ) %{
4584     instruction_count(0); multiple_bundles;
4585     fixed_latency(6);
4586 %}
4587 
4588 // Polling Address
4589 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4590 #ifdef _LP64
4591     instruction_count(0); multiple_bundles;
4592     fixed_latency(6);
4593 #else
4594     dst   : E(write);
4595     IALU  : R;
4596 #endif
4597 %}
4598 
4599 // Long Constant small
4600 pipe_class loadConLlo( iRegL dst, immL src ) %{
4601     instruction_count(2);
4602     dst   : E(write);
4603     IALU  : R;
4604     IALU  : R;
4605 %}
4606 
4607 // [PHH] This is wrong for 64-bit.  See LdImmF/D.
4608 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4609     instruction_count(1); multiple_bundles;
4610     src   : R(read);
4611     dst   : M(write)+1;
4612     IALU  : R;
4613     MS    : E;
4614 %}
4615 
4616 // Integer ALU nop operation
4617 pipe_class ialu_nop() %{
4618     single_instruction;
4619     IALU  : R;
4620 %}
4621 
4622 // Integer ALU nop operation
4623 pipe_class ialu_nop_A0() %{
4624     single_instruction;
4625     A0    : R;
4626 %}
4627 
4628 // Integer ALU nop operation
4629 pipe_class ialu_nop_A1() %{
4630     single_instruction;
4631     A1    : R;
4632 %}
4633 
4634 // Integer Multiply reg-reg operation
4635 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4636     single_instruction;
4637     dst   : E(write);
4638     src1  : R(read);
4639     src2  : R(read);
4640     MS    : R(5);
4641 %}
4642 
4643 // Integer Multiply reg-imm operation
4644 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4645     single_instruction;
4646     dst   : E(write);
4647     src1  : R(read);
4648     MS    : R(5);
4649 %}
4650 
4651 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4652     single_instruction;
4653     dst   : E(write)+4;
4654     src1  : R(read);
4655     src2  : R(read);
4656     MS    : R(6);
4657 %}
4658 
4659 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4660     single_instruction;
4661     dst   : E(write)+4;
4662     src1  : R(read);
4663     MS    : R(6);
4664 %}
4665 
4666 // Integer Divide reg-reg
4667 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4668     instruction_count(1); multiple_bundles;
4669     dst   : E(write);
4670     temp  : E(write);
4671     src1  : R(read);
4672     src2  : R(read);
4673     temp  : R(read);
4674     MS    : R(38);
4675 %}
4676 
4677 // Integer Divide reg-imm
4678 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4679     instruction_count(1); multiple_bundles;
4680     dst   : E(write);
4681     temp  : E(write);
4682     src1  : R(read);
4683     temp  : R(read);
4684     MS    : R(38);
4685 %}
4686 
4687 // Long Divide
4688 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4689     dst  : E(write)+71;
4690     src1 : R(read);
4691     src2 : R(read)+1;
4692     MS   : R(70);
4693 %}
4694 
4695 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4696     dst  : E(write)+71;
4697     src1 : R(read);
4698     MS   : R(70);
4699 %}
4700 
4701 // Floating Point Add Float
4702 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4703     single_instruction;
4704     dst   : X(write);
4705     src1  : E(read);
4706     src2  : E(read);
4707     FA    : R;
4708 %}
4709 
4710 // Floating Point Add Double
4711 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4712     single_instruction;
4713     dst   : X(write);
4714     src1  : E(read);
4715     src2  : E(read);
4716     FA    : R;
4717 %}
4718 
4719 // Floating Point Conditional Move based on integer flags
4720 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4721     single_instruction;
4722     dst   : X(write);
4723     src   : E(read);
4724     cr    : R(read);
4725     FA    : R(2);
4726     BR    : R(2);
4727 %}
4728 
4729 // Floating Point Conditional Move based on integer flags
4730 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4731     single_instruction;
4732     dst   : X(write);
4733     src   : E(read);
4734     cr    : R(read);
4735     FA    : R(2);
4736     BR    : R(2);
4737 %}
4738 
4739 // Floating Point Multiply Float
4740 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4741     single_instruction;
4742     dst   : X(write);
4743     src1  : E(read);
4744     src2  : E(read);
4745     FM    : R;
4746 %}
4747 
4748 // Floating Point Multiply Double
4749 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4750     single_instruction;
4751     dst   : X(write);
4752     src1  : E(read);
4753     src2  : E(read);
4754     FM    : R;
4755 %}
4756 
4757 // Floating Point Divide Float
4758 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4759     single_instruction;
4760     dst   : X(write);
4761     src1  : E(read);
4762     src2  : E(read);
4763     FM    : R;
4764     FDIV  : C(14);
4765 %}
4766 
4767 // Floating Point Divide Double
4768 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4769     single_instruction;
4770     dst   : X(write);
4771     src1  : E(read);
4772     src2  : E(read);
4773     FM    : R;
4774     FDIV  : C(17);
4775 %}
4776 
4777 // Floating Point Move/Negate/Abs Float
4778 pipe_class faddF_reg(regF dst, regF src) %{
4779     single_instruction;
4780     dst   : W(write);
4781     src   : E(read);
4782     FA    : R(1);
4783 %}
4784 
4785 // Floating Point Move/Negate/Abs Double
4786 pipe_class faddD_reg(regD dst, regD src) %{
4787     single_instruction;
4788     dst   : W(write);
4789     src   : E(read);
4790     FA    : R;
4791 %}
4792 
4793 // Floating Point Convert F->D
4794 pipe_class fcvtF2D(regD dst, regF src) %{
4795     single_instruction;
4796     dst   : X(write);
4797     src   : E(read);
4798     FA    : R;
4799 %}
4800 
4801 // Floating Point Convert I->D
4802 pipe_class fcvtI2D(regD dst, regF src) %{
4803     single_instruction;
4804     dst   : X(write);
4805     src   : E(read);
4806     FA    : R;
4807 %}
4808 
4809 // Floating Point Convert LHi->D
4810 pipe_class fcvtLHi2D(regD dst, regD src) %{
4811     single_instruction;
4812     dst   : X(write);
4813     src   : E(read);
4814     FA    : R;
4815 %}
4816 
4817 // Floating Point Convert L->D
4818 pipe_class fcvtL2D(regD dst, regF src) %{
4819     single_instruction;
4820     dst   : X(write);
4821     src   : E(read);
4822     FA    : R;
4823 %}
4824 
4825 // Floating Point Convert L->F
4826 pipe_class fcvtL2F(regD dst, regF src) %{
4827     single_instruction;
4828     dst   : X(write);
4829     src   : E(read);
4830     FA    : R;
4831 %}
4832 
4833 // Floating Point Convert D->F
4834 pipe_class fcvtD2F(regD dst, regF src) %{
4835     single_instruction;
4836     dst   : X(write);
4837     src   : E(read);
4838     FA    : R;
4839 %}
4840 
4841 // Floating Point Convert I->L
4842 pipe_class fcvtI2L(regD dst, regF src) %{
4843     single_instruction;
4844     dst   : X(write);
4845     src   : E(read);
4846     FA    : R;
4847 %}
4848 
4849 // Floating Point Convert D->F
4850 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4851     instruction_count(1); multiple_bundles;
4852     dst   : X(write)+6;
4853     src   : E(read);
4854     FA    : R;
4855 %}
4856 
4857 // Floating Point Convert D->L
4858 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4859     instruction_count(1); multiple_bundles;
4860     dst   : X(write)+6;
4861     src   : E(read);
4862     FA    : R;
4863 %}
4864 
4865 // Floating Point Convert F->I
4866 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4867     instruction_count(1); multiple_bundles;
4868     dst   : X(write)+6;
4869     src   : E(read);
4870     FA    : R;
4871 %}
4872 
4873 // Floating Point Convert F->L
4874 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4875     instruction_count(1); multiple_bundles;
4876     dst   : X(write)+6;
4877     src   : E(read);
4878     FA    : R;
4879 %}
4880 
4881 // Floating Point Convert I->F
4882 pipe_class fcvtI2F(regF dst, regF src) %{
4883     single_instruction;
4884     dst   : X(write);
4885     src   : E(read);
4886     FA    : R;
4887 %}
4888 
4889 // Floating Point Compare
4890 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4891     single_instruction;
4892     cr    : X(write);
4893     src1  : E(read);
4894     src2  : E(read);
4895     FA    : R;
4896 %}
4897 
4898 // Floating Point Compare
4899 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4900     single_instruction;
4901     cr    : X(write);
4902     src1  : E(read);
4903     src2  : E(read);
4904     FA    : R;
4905 %}
4906 
4907 // Floating Add Nop
4908 pipe_class fadd_nop() %{
4909     single_instruction;
4910     FA  : R;
4911 %}
4912 
4913 // Integer Store to Memory
4914 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4915     single_instruction;
4916     mem   : R(read);
4917     src   : C(read);
4918     MS    : R;
4919 %}
4920 
4921 // Integer Store to Memory
4922 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4923     single_instruction;
4924     mem   : R(read);
4925     src   : C(read);
4926     MS    : R;
4927 %}
4928 
4929 // Integer Store Zero to Memory
4930 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4931     single_instruction;
4932     mem   : R(read);
4933     MS    : R;
4934 %}
4935 
4936 // Special Stack Slot Store
4937 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4938     single_instruction;
4939     stkSlot : R(read);
4940     src     : C(read);
4941     MS      : R;
4942 %}
4943 
4944 // Special Stack Slot Store
4945 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4946     instruction_count(2); multiple_bundles;
4947     stkSlot : R(read);
4948     src     : C(read);
4949     MS      : R(2);
4950 %}
4951 
4952 // Float Store
4953 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4954     single_instruction;
4955     mem : R(read);
4956     src : C(read);
4957     MS  : R;
4958 %}
4959 
4960 // Float Store
4961 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4962     single_instruction;
4963     mem : R(read);
4964     MS  : R;
4965 %}
4966 
4967 // Double Store
4968 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4969     instruction_count(1);
4970     mem : R(read);
4971     src : C(read);
4972     MS  : R;
4973 %}
4974 
4975 // Double Store
4976 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4977     single_instruction;
4978     mem : R(read);
4979     MS  : R;
4980 %}
4981 
4982 // Special Stack Slot Float Store
4983 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4984     single_instruction;
4985     stkSlot : R(read);
4986     src     : C(read);
4987     MS      : R;
4988 %}
4989 
4990 // Special Stack Slot Double Store
4991 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4992     single_instruction;
4993     stkSlot : R(read);
4994     src     : C(read);
4995     MS      : R;
4996 %}
4997 
4998 // Integer Load (when sign bit propagation not needed)
4999 pipe_class iload_mem(iRegI dst, memory mem) %{
5000     single_instruction;
5001     mem : R(read);
5002     dst : C(write);
5003     MS  : R;
5004 %}
5005 
5006 // Integer Load from stack operand
5007 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5008     single_instruction;
5009     mem : R(read);
5010     dst : C(write);
5011     MS  : R;
5012 %}
5013 
5014 // Integer Load (when sign bit propagation or masking is needed)
5015 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5016     single_instruction;
5017     mem : R(read);
5018     dst : M(write);
5019     MS  : R;
5020 %}
5021 
5022 // Float Load
5023 pipe_class floadF_mem(regF dst, memory mem) %{
5024     single_instruction;
5025     mem : R(read);
5026     dst : M(write);
5027     MS  : R;
5028 %}
5029 
5030 // Float Load
5031 pipe_class floadD_mem(regD dst, memory mem) %{
5032     instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5033     mem : R(read);
5034     dst : M(write);
5035     MS  : R;
5036 %}
5037 
5038 // Float Load
5039 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5040     single_instruction;
5041     stkSlot : R(read);
5042     dst : M(write);
5043     MS  : R;
5044 %}
5045 
5046 // Float Load
5047 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5048     single_instruction;
5049     stkSlot : R(read);
5050     dst : M(write);
5051     MS  : R;
5052 %}
5053 
5054 // Memory Nop
5055 pipe_class mem_nop() %{
5056     single_instruction;
5057     MS  : R;
5058 %}
5059 
5060 pipe_class sethi(iRegP dst, immI src) %{
5061     single_instruction;
5062     dst  : E(write);
5063     IALU : R;
5064 %}
5065 
5066 pipe_class loadPollP(iRegP poll) %{
5067     single_instruction;
5068     poll : R(read);
5069     MS   : R;
5070 %}
5071 
5072 pipe_class br(Universe br, label labl) %{
5073     single_instruction_with_delay_slot;
5074     BR  : R;
5075 %}
5076 
5077 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5078     single_instruction_with_delay_slot;
5079     cr    : E(read);
5080     BR    : R;
5081 %}
5082 
5083 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5084     single_instruction_with_delay_slot;
5085     op1 : E(read);
5086     BR  : R;
5087     MS  : R;
5088 %}
5089 
5090 // Compare and branch
5091 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5092     instruction_count(2); has_delay_slot;
5093     cr    : E(write);
5094     src1  : R(read);
5095     src2  : R(read);
5096     IALU  : R;
5097     BR    : R;
5098 %}
5099 
5100 // Compare and branch
5101 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5102     instruction_count(2); has_delay_slot;
5103     cr    : E(write);
5104     src1  : R(read);
5105     IALU  : R;
5106     BR    : R;
5107 %}
5108 
5109 // Compare and branch using cbcond
5110 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5111     single_instruction;
5112     src1  : E(read);
5113     src2  : E(read);
5114     IALU  : R;
5115     BR    : R;
5116 %}
5117 
5118 // Compare and branch using cbcond
5119 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5120     single_instruction;
5121     src1  : E(read);
5122     IALU  : R;
5123     BR    : R;
5124 %}
5125 
5126 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5127     single_instruction_with_delay_slot;
5128     cr    : E(read);
5129     BR    : R;
5130 %}
5131 
5132 pipe_class br_nop() %{
5133     single_instruction;
5134     BR  : R;
5135 %}
5136 
5137 pipe_class simple_call(method meth) %{
5138     instruction_count(2); multiple_bundles; force_serialization;
5139     fixed_latency(100);
5140     BR  : R(1);
5141     MS  : R(1);
5142     A0  : R(1);
5143 %}
5144 
5145 pipe_class compiled_call(method meth) %{
5146     instruction_count(1); multiple_bundles; force_serialization;
5147     fixed_latency(100);
5148     MS  : R(1);
5149 %}
5150 
5151 pipe_class call(method meth) %{
5152     instruction_count(0); multiple_bundles; force_serialization;
5153     fixed_latency(100);
5154 %}
5155 
5156 pipe_class tail_call(Universe ignore, label labl) %{
5157     single_instruction; has_delay_slot;
5158     fixed_latency(100);
5159     BR  : R(1);
5160     MS  : R(1);
5161 %}
5162 
5163 pipe_class ret(Universe ignore) %{
5164     single_instruction; has_delay_slot;
5165     BR  : R(1);
5166     MS  : R(1);
5167 %}
5168 
5169 pipe_class ret_poll(g3RegP poll) %{
5170     instruction_count(3); has_delay_slot;
5171     poll : E(read);
5172     MS   : R;
5173 %}
5174 
5175 // The real do-nothing guy
5176 pipe_class empty( ) %{
5177     instruction_count(0);
5178 %}
5179 
5180 pipe_class long_memory_op() %{
5181     instruction_count(0); multiple_bundles; force_serialization;
5182     fixed_latency(25);
5183     MS  : R(1);
5184 %}
5185 
5186 // Check-cast
5187 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5188     array : R(read);
5189     match  : R(read);
5190     IALU   : R(2);
5191     BR     : R(2);
5192     MS     : R;
5193 %}
5194 
5195 // Convert FPU flags into +1,0,-1
5196 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5197     src1  : E(read);
5198     src2  : E(read);
5199     dst   : E(write);
5200     FA    : R;
5201     MS    : R(2);
5202     BR    : R(2);
5203 %}
5204 
5205 // Compare for p < q, and conditionally add y
5206 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5207     p     : E(read);
5208     q     : E(read);
5209     y     : E(read);
5210     IALU  : R(3)
5211 %}
5212 
5213 // Perform a compare, then move conditionally in a branch delay slot.
5214 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5215     src2   : E(read);
5216     srcdst : E(read);
5217     IALU   : R;
5218     BR     : R;
5219 %}
5220 
5221 // Define the class for the Nop node
5222 define %{
5223    MachNop = ialu_nop;
5224 %}
5225 
5226 %}
5227 
5228 //----------INSTRUCTIONS-------------------------------------------------------
5229 
5230 //------------Special Stack Slot instructions - no match rules-----------------
5231 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5232   // No match rule to avoid chain rule match.
5233   effect(DEF dst, USE src);
5234   ins_cost(MEMORY_REF_COST);
5235   format %{ "LDF    $src,$dst\t! stkI to regF" %}
5236   opcode(Assembler::ldf_op3);
5237   ins_encode(simple_form3_mem_reg(src, dst));
5238   ins_pipe(floadF_stk);
5239 %}
5240 
5241 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5242   // No match rule to avoid chain rule match.
5243   effect(DEF dst, USE src);
5244   ins_cost(MEMORY_REF_COST);
5245   format %{ "LDDF   $src,$dst\t! stkL to regD" %}
5246   opcode(Assembler::lddf_op3);
5247   ins_encode(simple_form3_mem_reg(src, dst));
5248   ins_pipe(floadD_stk);
5249 %}
5250 
5251 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5252   // No match rule to avoid chain rule match.
5253   effect(DEF dst, USE src);
5254   ins_cost(MEMORY_REF_COST);
5255   format %{ "STF    $src,$dst\t! regF to stkI" %}
5256   opcode(Assembler::stf_op3);
5257   ins_encode(simple_form3_mem_reg(dst, src));
5258   ins_pipe(fstoreF_stk_reg);
5259 %}
5260 
5261 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5262   // No match rule to avoid chain rule match.
5263   effect(DEF dst, USE src);
5264   ins_cost(MEMORY_REF_COST);
5265   format %{ "STDF   $src,$dst\t! regD to stkL" %}
5266   opcode(Assembler::stdf_op3);
5267   ins_encode(simple_form3_mem_reg(dst, src));
5268   ins_pipe(fstoreD_stk_reg);
5269 %}
5270 
5271 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5272   effect(DEF dst, USE src);
5273   ins_cost(MEMORY_REF_COST*2);
5274   format %{ "STW    $src,$dst.hi\t! long\n\t"
5275             "STW    R_G0,$dst.lo" %}
5276   opcode(Assembler::stw_op3);
5277   ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5278   ins_pipe(lstoreI_stk_reg);
5279 %}
5280 
5281 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5282   // No match rule to avoid chain rule match.
5283   effect(DEF dst, USE src);
5284   ins_cost(MEMORY_REF_COST);
5285   format %{ "STX    $src,$dst\t! regL to stkD" %}
5286   opcode(Assembler::stx_op3);
5287   ins_encode(simple_form3_mem_reg( dst, src ) );
5288   ins_pipe(istore_stk_reg);
5289 %}
5290 
5291 //---------- Chain stack slots between similar types --------
5292 
5293 // Load integer from stack slot
5294 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5295   match(Set dst src);
5296   ins_cost(MEMORY_REF_COST);
5297 
5298   format %{ "LDUW   $src,$dst\t!stk" %}
5299   opcode(Assembler::lduw_op3);
5300   ins_encode(simple_form3_mem_reg( src, dst ) );
5301   ins_pipe(iload_mem);
5302 %}
5303 
5304 // Store integer to stack slot
5305 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5306   match(Set dst src);
5307   ins_cost(MEMORY_REF_COST);
5308 
5309   format %{ "STW    $src,$dst\t!stk" %}
5310   opcode(Assembler::stw_op3);
5311   ins_encode(simple_form3_mem_reg( dst, src ) );
5312   ins_pipe(istore_mem_reg);
5313 %}
5314 
5315 // Load long from stack slot
5316 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5317   match(Set dst src);
5318 
5319   ins_cost(MEMORY_REF_COST);
5320   format %{ "LDX    $src,$dst\t! long" %}
5321   opcode(Assembler::ldx_op3);
5322   ins_encode(simple_form3_mem_reg( src, dst ) );
5323   ins_pipe(iload_mem);
5324 %}
5325 
5326 // Store long to stack slot
5327 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5328   match(Set dst src);
5329 
5330   ins_cost(MEMORY_REF_COST);
5331   format %{ "STX    $src,$dst\t! long" %}
5332   opcode(Assembler::stx_op3);
5333   ins_encode(simple_form3_mem_reg( dst, src ) );
5334   ins_pipe(istore_mem_reg);
5335 %}
5336 
5337 #ifdef _LP64
5338 // Load pointer from stack slot, 64-bit encoding
5339 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5340   match(Set dst src);
5341   ins_cost(MEMORY_REF_COST);
5342   format %{ "LDX    $src,$dst\t!ptr" %}
5343   opcode(Assembler::ldx_op3);
5344   ins_encode(simple_form3_mem_reg( src, dst ) );
5345   ins_pipe(iload_mem);
5346 %}
5347 
5348 // Store pointer to stack slot
5349 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5350   match(Set dst src);
5351   ins_cost(MEMORY_REF_COST);
5352   format %{ "STX    $src,$dst\t!ptr" %}
5353   opcode(Assembler::stx_op3);
5354   ins_encode(simple_form3_mem_reg( dst, src ) );
5355   ins_pipe(istore_mem_reg);
5356 %}
5357 #else // _LP64
5358 // Load pointer from stack slot, 32-bit encoding
5359 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5360   match(Set dst src);
5361   ins_cost(MEMORY_REF_COST);
5362   format %{ "LDUW   $src,$dst\t!ptr" %}
5363   opcode(Assembler::lduw_op3, Assembler::ldst_op);
5364   ins_encode(simple_form3_mem_reg( src, dst ) );
5365   ins_pipe(iload_mem);
5366 %}
5367 
5368 // Store pointer to stack slot
5369 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5370   match(Set dst src);
5371   ins_cost(MEMORY_REF_COST);
5372   format %{ "STW    $src,$dst\t!ptr" %}
5373   opcode(Assembler::stw_op3, Assembler::ldst_op);
5374   ins_encode(simple_form3_mem_reg( dst, src ) );
5375   ins_pipe(istore_mem_reg);
5376 %}
5377 #endif // _LP64
5378 
5379 //------------Special Nop instructions for bundling - no match rules-----------
5380 // Nop using the A0 functional unit
5381 instruct Nop_A0() %{
5382   ins_cost(0);
5383 
5384   format %{ "NOP    ! Alu Pipeline" %}
5385   opcode(Assembler::or_op3, Assembler::arith_op);
5386   ins_encode( form2_nop() );
5387   ins_pipe(ialu_nop_A0);
5388 %}
5389 
5390 // Nop using the A1 functional unit
5391 instruct Nop_A1( ) %{
5392   ins_cost(0);
5393 
5394   format %{ "NOP    ! Alu Pipeline" %}
5395   opcode(Assembler::or_op3, Assembler::arith_op);
5396   ins_encode( form2_nop() );
5397   ins_pipe(ialu_nop_A1);
5398 %}
5399 
5400 // Nop using the memory functional unit
5401 instruct Nop_MS( ) %{
5402   ins_cost(0);
5403 
5404   format %{ "NOP    ! Memory Pipeline" %}
5405   ins_encode( emit_mem_nop );
5406   ins_pipe(mem_nop);
5407 %}
5408 
5409 // Nop using the floating add functional unit
5410 instruct Nop_FA( ) %{
5411   ins_cost(0);
5412 
5413   format %{ "NOP    ! Floating Add Pipeline" %}
5414   ins_encode( emit_fadd_nop );
5415   ins_pipe(fadd_nop);
5416 %}
5417 
5418 // Nop using the branch functional unit
5419 instruct Nop_BR( ) %{
5420   ins_cost(0);
5421 
5422   format %{ "NOP    ! Branch Pipeline" %}
5423   ins_encode( emit_br_nop );
5424   ins_pipe(br_nop);
5425 %}
5426 
5427 //----------Load/Store/Move Instructions---------------------------------------
5428 //----------Load Instructions--------------------------------------------------
5429 // Load Byte (8bit signed)
5430 instruct loadB(iRegI dst, memory mem) %{
5431   match(Set dst (LoadB mem));
5432   ins_cost(MEMORY_REF_COST);
5433 
5434   size(4);
5435   format %{ "LDSB   $mem,$dst\t! byte" %}
5436   ins_encode %{
5437     __ ldsb($mem$$Address, $dst$$Register);
5438   %}
5439   ins_pipe(iload_mask_mem);
5440 %}
5441 
5442 // Load Byte (8bit signed) into a Long Register
5443 instruct loadB2L(iRegL dst, memory mem) %{
5444   match(Set dst (ConvI2L (LoadB mem)));
5445   ins_cost(MEMORY_REF_COST);
5446 
5447   size(4);
5448   format %{ "LDSB   $mem,$dst\t! byte -> long" %}
5449   ins_encode %{
5450     __ ldsb($mem$$Address, $dst$$Register);
5451   %}
5452   ins_pipe(iload_mask_mem);
5453 %}
5454 
5455 // Load Unsigned Byte (8bit UNsigned) into an int reg
5456 instruct loadUB(iRegI dst, memory mem) %{
5457   match(Set dst (LoadUB mem));
5458   ins_cost(MEMORY_REF_COST);
5459 
5460   size(4);
5461   format %{ "LDUB   $mem,$dst\t! ubyte" %}
5462   ins_encode %{
5463     __ ldub($mem$$Address, $dst$$Register);
5464   %}
5465   ins_pipe(iload_mem);
5466 %}
5467 
5468 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5469 instruct loadUB2L(iRegL dst, memory mem) %{
5470   match(Set dst (ConvI2L (LoadUB mem)));
5471   ins_cost(MEMORY_REF_COST);
5472 
5473   size(4);
5474   format %{ "LDUB   $mem,$dst\t! ubyte -> long" %}
5475   ins_encode %{
5476     __ ldub($mem$$Address, $dst$$Register);
5477   %}
5478   ins_pipe(iload_mem);
5479 %}
5480 
5481 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5482 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5483   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5484   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5485 
5486   size(2*4);
5487   format %{ "LDUB   $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5488             "AND    $dst,right_n_bits($mask, 8),$dst" %}
5489   ins_encode %{
5490     __ ldub($mem$$Address, $dst$$Register);
5491     __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5492   %}
5493   ins_pipe(iload_mem);
5494 %}
5495 
5496 // Load Short (16bit signed)
5497 instruct loadS(iRegI dst, memory mem) %{
5498   match(Set dst (LoadS mem));
5499   ins_cost(MEMORY_REF_COST);
5500 
5501   size(4);
5502   format %{ "LDSH   $mem,$dst\t! short" %}
5503   ins_encode %{
5504     __ ldsh($mem$$Address, $dst$$Register);
5505   %}
5506   ins_pipe(iload_mask_mem);
5507 %}
5508 
5509 // Load Short (16 bit signed) to Byte (8 bit signed)
5510 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5511   match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5512   ins_cost(MEMORY_REF_COST);
5513 
5514   size(4);
5515 
5516   format %{ "LDSB   $mem+1,$dst\t! short -> byte" %}
5517   ins_encode %{
5518     __ ldsb($mem$$Address, $dst$$Register, 1);
5519   %}
5520   ins_pipe(iload_mask_mem);
5521 %}
5522 
5523 // Load Short (16bit signed) into a Long Register
5524 instruct loadS2L(iRegL dst, memory mem) %{
5525   match(Set dst (ConvI2L (LoadS mem)));
5526   ins_cost(MEMORY_REF_COST);
5527 
5528   size(4);
5529   format %{ "LDSH   $mem,$dst\t! short -> long" %}
5530   ins_encode %{
5531     __ ldsh($mem$$Address, $dst$$Register);
5532   %}
5533   ins_pipe(iload_mask_mem);
5534 %}
5535 
5536 // Load Unsigned Short/Char (16bit UNsigned)
5537 instruct loadUS(iRegI dst, memory mem) %{
5538   match(Set dst (LoadUS mem));
5539   ins_cost(MEMORY_REF_COST);
5540 
5541   size(4);
5542   format %{ "LDUH   $mem,$dst\t! ushort/char" %}
5543   ins_encode %{
5544     __ lduh($mem$$Address, $dst$$Register);
5545   %}
5546   ins_pipe(iload_mem);
5547 %}
5548 
5549 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5550 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5551   match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5552   ins_cost(MEMORY_REF_COST);
5553 
5554   size(4);
5555   format %{ "LDSB   $mem+1,$dst\t! ushort -> byte" %}
5556   ins_encode %{
5557     __ ldsb($mem$$Address, $dst$$Register, 1);
5558   %}
5559   ins_pipe(iload_mask_mem);
5560 %}
5561 
5562 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5563 instruct loadUS2L(iRegL dst, memory mem) %{
5564   match(Set dst (ConvI2L (LoadUS mem)));
5565   ins_cost(MEMORY_REF_COST);
5566 
5567   size(4);
5568   format %{ "LDUH   $mem,$dst\t! ushort/char -> long" %}
5569   ins_encode %{
5570     __ lduh($mem$$Address, $dst$$Register);
5571   %}
5572   ins_pipe(iload_mem);
5573 %}
5574 
5575 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5576 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5577   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5578   ins_cost(MEMORY_REF_COST);
5579 
5580   size(4);
5581   format %{ "LDUB   $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5582   ins_encode %{
5583     __ ldub($mem$$Address, $dst$$Register, 1);  // LSB is index+1 on BE
5584   %}
5585   ins_pipe(iload_mem);
5586 %}
5587 
5588 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5589 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5590   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5591   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5592 
5593   size(2*4);
5594   format %{ "LDUH   $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5595             "AND    $dst,$mask,$dst" %}
5596   ins_encode %{
5597     Register Rdst = $dst$$Register;
5598     __ lduh($mem$$Address, Rdst);
5599     __ and3(Rdst, $mask$$constant, Rdst);
5600   %}
5601   ins_pipe(iload_mem);
5602 %}
5603 
5604 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5605 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5606   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5607   effect(TEMP dst, TEMP tmp);
5608   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5609 
5610   format %{ "LDUH   $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5611             "SET    right_n_bits($mask, 16),$tmp\n\t"
5612             "AND    $dst,$tmp,$dst" %}
5613   ins_encode %{
5614     Register Rdst = $dst$$Register;
5615     Register Rtmp = $tmp$$Register;
5616     __ lduh($mem$$Address, Rdst);
5617     __ set($mask$$constant & right_n_bits(16), Rtmp);
5618     __ and3(Rdst, Rtmp, Rdst);
5619   %}
5620   ins_pipe(iload_mem);
5621 %}
5622 
5623 // Load Integer
5624 instruct loadI(iRegI dst, memory mem) %{
5625   match(Set dst (LoadI mem));
5626   ins_cost(MEMORY_REF_COST);
5627 
5628   size(4);
5629   format %{ "LDUW   $mem,$dst\t! int" %}
5630   ins_encode %{
5631     __ lduw($mem$$Address, $dst$$Register);
5632   %}
5633   ins_pipe(iload_mem);
5634 %}
5635 
5636 // Load Integer to Byte (8 bit signed)
5637 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5638   match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5639   ins_cost(MEMORY_REF_COST);
5640 
5641   size(4);
5642 
5643   format %{ "LDSB   $mem+3,$dst\t! int -> byte" %}
5644   ins_encode %{
5645     __ ldsb($mem$$Address, $dst$$Register, 3);
5646   %}
5647   ins_pipe(iload_mask_mem);
5648 %}
5649 
5650 // Load Integer to Unsigned Byte (8 bit UNsigned)
5651 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5652   match(Set dst (AndI (LoadI mem) mask));
5653   ins_cost(MEMORY_REF_COST);
5654 
5655   size(4);
5656 
5657   format %{ "LDUB   $mem+3,$dst\t! int -> ubyte" %}
5658   ins_encode %{
5659     __ ldub($mem$$Address, $dst$$Register, 3);
5660   %}
5661   ins_pipe(iload_mask_mem);
5662 %}
5663 
5664 // Load Integer to Short (16 bit signed)
5665 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5666   match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5667   ins_cost(MEMORY_REF_COST);
5668 
5669   size(4);
5670 
5671   format %{ "LDSH   $mem+2,$dst\t! int -> short" %}
5672   ins_encode %{
5673     __ ldsh($mem$$Address, $dst$$Register, 2);
5674   %}
5675   ins_pipe(iload_mask_mem);
5676 %}
5677 
5678 // Load Integer to Unsigned Short (16 bit UNsigned)
5679 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5680   match(Set dst (AndI (LoadI mem) mask));
5681   ins_cost(MEMORY_REF_COST);
5682 
5683   size(4);
5684 
5685   format %{ "LDUH   $mem+2,$dst\t! int -> ushort/char" %}
5686   ins_encode %{
5687     __ lduh($mem$$Address, $dst$$Register, 2);
5688   %}
5689   ins_pipe(iload_mask_mem);
5690 %}
5691 
5692 // Load Integer into a Long Register
5693 instruct loadI2L(iRegL dst, memory mem) %{
5694   match(Set dst (ConvI2L (LoadI mem)));
5695   ins_cost(MEMORY_REF_COST);
5696 
5697   size(4);
5698   format %{ "LDSW   $mem,$dst\t! int -> long" %}
5699   ins_encode %{
5700     __ ldsw($mem$$Address, $dst$$Register);
5701   %}
5702   ins_pipe(iload_mask_mem);
5703 %}
5704 
5705 // Load Integer with mask 0xFF into a Long Register
5706 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5707   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5708   ins_cost(MEMORY_REF_COST);
5709 
5710   size(4);
5711   format %{ "LDUB   $mem+3,$dst\t! int & 0xFF -> long" %}
5712   ins_encode %{
5713     __ ldub($mem$$Address, $dst$$Register, 3);  // LSB is index+3 on BE
5714   %}
5715   ins_pipe(iload_mem);
5716 %}
5717 
5718 // Load Integer with mask 0xFFFF into a Long Register
5719 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5720   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5721   ins_cost(MEMORY_REF_COST);
5722 
5723   size(4);
5724   format %{ "LDUH   $mem+2,$dst\t! int & 0xFFFF -> long" %}
5725   ins_encode %{
5726     __ lduh($mem$$Address, $dst$$Register, 2);  // LSW is index+2 on BE
5727   %}
5728   ins_pipe(iload_mem);
5729 %}
5730 
5731 // Load Integer with a 12-bit mask into a Long Register
5732 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5733   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5734   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5735 
5736   size(2*4);
5737   format %{ "LDUW   $mem,$dst\t! int & 12-bit mask -> long\n\t"
5738             "AND    $dst,$mask,$dst" %}
5739   ins_encode %{
5740     Register Rdst = $dst$$Register;
5741     __ lduw($mem$$Address, Rdst);
5742     __ and3(Rdst, $mask$$constant, Rdst);
5743   %}
5744   ins_pipe(iload_mem);
5745 %}
5746 
5747 // Load Integer with a 31-bit mask into a Long Register
5748 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5749   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5750   effect(TEMP dst, TEMP tmp);
5751   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5752 
5753   format %{ "LDUW   $mem,$dst\t! int & 31-bit mask -> long\n\t"
5754             "SET    $mask,$tmp\n\t"
5755             "AND    $dst,$tmp,$dst" %}
5756   ins_encode %{
5757     Register Rdst = $dst$$Register;
5758     Register Rtmp = $tmp$$Register;
5759     __ lduw($mem$$Address, Rdst);
5760     __ set($mask$$constant, Rtmp);
5761     __ and3(Rdst, Rtmp, Rdst);
5762   %}
5763   ins_pipe(iload_mem);
5764 %}
5765 
5766 // Load Unsigned Integer into a Long Register
5767 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5768   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5769   ins_cost(MEMORY_REF_COST);
5770 
5771   size(4);
5772   format %{ "LDUW   $mem,$dst\t! uint -> long" %}
5773   ins_encode %{
5774     __ lduw($mem$$Address, $dst$$Register);
5775   %}
5776   ins_pipe(iload_mem);
5777 %}
5778 
5779 // Load Long - aligned
5780 instruct loadL(iRegL dst, memory mem ) %{
5781   match(Set dst (LoadL mem));
5782   ins_cost(MEMORY_REF_COST);
5783 
5784   size(4);
5785   format %{ "LDX    $mem,$dst\t! long" %}
5786   ins_encode %{
5787     __ ldx($mem$$Address, $dst$$Register);
5788   %}
5789   ins_pipe(iload_mem);
5790 %}
5791 
5792 // Load Long - UNaligned
5793 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5794   match(Set dst (LoadL_unaligned mem));
5795   effect(KILL tmp);
5796   ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5797   format %{ "LDUW   $mem+4,R_O7\t! misaligned long\n"
5798           "\tLDUW   $mem  ,$dst\n"
5799           "\tSLLX   #32, $dst, $dst\n"
5800           "\tOR     $dst, R_O7, $dst" %}
5801   opcode(Assembler::lduw_op3);
5802   ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5803   ins_pipe(iload_mem);
5804 %}
5805 
5806 // Load Range
5807 instruct loadRange(iRegI dst, memory mem) %{
5808   match(Set dst (LoadRange mem));
5809   ins_cost(MEMORY_REF_COST);
5810 
5811   format %{ "LDUW   $mem,$dst\t! range" %}
5812   opcode(Assembler::lduw_op3);
5813   ins_encode(simple_form3_mem_reg( mem, dst ) );
5814   ins_pipe(iload_mem);
5815 %}
5816 
5817 // Load Integer into %f register (for fitos/fitod)
5818 instruct loadI_freg(regF dst, memory mem) %{
5819   match(Set dst (LoadI mem));
5820   ins_cost(MEMORY_REF_COST);
5821 
5822   format %{ "LDF    $mem,$dst\t! for fitos/fitod" %}
5823   opcode(Assembler::ldf_op3);
5824   ins_encode(simple_form3_mem_reg( mem, dst ) );
5825   ins_pipe(floadF_mem);
5826 %}
5827 
5828 // Load Pointer
5829 instruct loadP(iRegP dst, memory mem) %{
5830   match(Set dst (LoadP mem));
5831   ins_cost(MEMORY_REF_COST);
5832   size(4);
5833 
5834 #ifndef _LP64
5835   format %{ "LDUW   $mem,$dst\t! ptr" %}
5836   ins_encode %{
5837     __ lduw($mem$$Address, $dst$$Register);
5838   %}
5839 #else
5840   format %{ "LDX    $mem,$dst\t! ptr" %}
5841   ins_encode %{
5842     __ ldx($mem$$Address, $dst$$Register);
5843   %}
5844 #endif
5845   ins_pipe(iload_mem);
5846 %}
5847 
5848 // Load Compressed Pointer
5849 instruct loadN(iRegN dst, memory mem) %{
5850   match(Set dst (LoadN mem));
5851   ins_cost(MEMORY_REF_COST);
5852   size(4);
5853 
5854   format %{ "LDUW   $mem,$dst\t! compressed ptr" %}
5855   ins_encode %{
5856     __ lduw($mem$$Address, $dst$$Register);
5857   %}
5858   ins_pipe(iload_mem);
5859 %}
5860 
5861 // Load Klass Pointer
5862 instruct loadKlass(iRegP dst, memory mem) %{
5863   match(Set dst (LoadKlass mem));
5864   ins_cost(MEMORY_REF_COST);
5865   size(4);
5866 
5867 #ifndef _LP64
5868   format %{ "LDUW   $mem,$dst\t! klass ptr" %}
5869   ins_encode %{
5870     __ lduw($mem$$Address, $dst$$Register);
5871   %}
5872 #else
5873   format %{ "LDX    $mem,$dst\t! klass ptr" %}
5874   ins_encode %{
5875     __ ldx($mem$$Address, $dst$$Register);
5876   %}
5877 #endif
5878   ins_pipe(iload_mem);
5879 %}
5880 
5881 // Load narrow Klass Pointer
5882 instruct loadNKlass(iRegN dst, memory mem) %{
5883   match(Set dst (LoadNKlass mem));
5884   ins_cost(MEMORY_REF_COST);
5885   size(4);
5886 
5887   format %{ "LDUW   $mem,$dst\t! compressed klass ptr" %}
5888   ins_encode %{
5889     __ lduw($mem$$Address, $dst$$Register);
5890   %}
5891   ins_pipe(iload_mem);
5892 %}
5893 
5894 // Load Double
5895 instruct loadD(regD dst, memory mem) %{
5896   match(Set dst (LoadD mem));
5897   ins_cost(MEMORY_REF_COST);
5898 
5899   format %{ "LDDF   $mem,$dst" %}
5900   opcode(Assembler::lddf_op3);
5901   ins_encode(simple_form3_mem_reg( mem, dst ) );
5902   ins_pipe(floadD_mem);
5903 %}
5904 
5905 // Load Double - UNaligned
5906 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5907   match(Set dst (LoadD_unaligned mem));
5908   ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5909   format %{ "LDF    $mem  ,$dst.hi\t! misaligned double\n"
5910           "\tLDF    $mem+4,$dst.lo\t!" %}
5911   opcode(Assembler::ldf_op3);
5912   ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5913   ins_pipe(iload_mem);
5914 %}
5915 
5916 // Load Float
5917 instruct loadF(regF dst, memory mem) %{
5918   match(Set dst (LoadF mem));
5919   ins_cost(MEMORY_REF_COST);
5920 
5921   format %{ "LDF    $mem,$dst" %}
5922   opcode(Assembler::ldf_op3);
5923   ins_encode(simple_form3_mem_reg( mem, dst ) );
5924   ins_pipe(floadF_mem);
5925 %}
5926 
5927 // Load Constant
5928 instruct loadConI( iRegI dst, immI src ) %{
5929   match(Set dst src);
5930   ins_cost(DEFAULT_COST * 3/2);
5931   format %{ "SET    $src,$dst" %}
5932   ins_encode( Set32(src, dst) );
5933   ins_pipe(ialu_hi_lo_reg);
5934 %}
5935 
5936 instruct loadConI13( iRegI dst, immI13 src ) %{
5937   match(Set dst src);
5938 
5939   size(4);
5940   format %{ "MOV    $src,$dst" %}
5941   ins_encode( Set13( src, dst ) );
5942   ins_pipe(ialu_imm);
5943 %}
5944 
5945 #ifndef _LP64
5946 instruct loadConP(iRegP dst, immP con) %{
5947   match(Set dst con);
5948   ins_cost(DEFAULT_COST * 3/2);
5949   format %{ "SET    $con,$dst\t!ptr" %}
5950   ins_encode %{
5951     relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5952       intptr_t val = $con$$constant;
5953     if (constant_reloc == relocInfo::oop_type) {
5954       __ set_oop_constant((jobject) val, $dst$$Register);
5955     } else if (constant_reloc == relocInfo::metadata_type) {
5956       __ set_metadata_constant((Metadata*)val, $dst$$Register);
5957     } else {          // non-oop pointers, e.g. card mark base, heap top
5958       assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5959       __ set(val, $dst$$Register);
5960     }
5961   %}
5962   ins_pipe(loadConP);
5963 %}
5964 #else
5965 instruct loadConP_set(iRegP dst, immP_set con) %{
5966   match(Set dst con);
5967   ins_cost(DEFAULT_COST * 3/2);
5968   format %{ "SET    $con,$dst\t! ptr" %}
5969   ins_encode %{
5970     relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5971       intptr_t val = $con$$constant;
5972     if (constant_reloc == relocInfo::oop_type) {
5973       __ set_oop_constant((jobject) val, $dst$$Register);
5974     } else if (constant_reloc == relocInfo::metadata_type) {
5975       __ set_metadata_constant((Metadata*)val, $dst$$Register);
5976     } else {          // non-oop pointers, e.g. card mark base, heap top
5977       assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5978       __ set(val, $dst$$Register);
5979     }
5980   %}
5981   ins_pipe(loadConP);
5982 %}
5983 
5984 instruct loadConP_load(iRegP dst, immP_load con) %{
5985   match(Set dst con);
5986   ins_cost(MEMORY_REF_COST);
5987   format %{ "LD     [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
5988   ins_encode %{
5989     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5990     __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
5991   %}
5992   ins_pipe(loadConP);
5993 %}
5994 
5995 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
5996   match(Set dst con);
5997   ins_cost(DEFAULT_COST * 3/2);
5998   format %{ "SET    $con,$dst\t! non-oop ptr" %}
5999   ins_encode %{
6000     if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
6001       __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
6002     } else {
6003       __ set($con$$constant, $dst$$Register);
6004     }
6005   %}
6006   ins_pipe(loadConP);
6007 %}
6008 #endif // _LP64
6009 
6010 instruct loadConP0(iRegP dst, immP0 src) %{
6011   match(Set dst src);
6012 
6013   size(4);
6014   format %{ "CLR    $dst\t!ptr" %}
6015   ins_encode %{
6016     __ clr($dst$$Register);
6017   %}
6018   ins_pipe(ialu_imm);
6019 %}
6020 
6021 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6022   match(Set dst src);
6023   ins_cost(DEFAULT_COST);
6024   format %{ "SET    $src,$dst\t!ptr" %}
6025   ins_encode %{
6026     AddressLiteral polling_page(os::get_polling_page());
6027     __ sethi(polling_page, reg_to_register_object($dst$$reg));
6028   %}
6029   ins_pipe(loadConP_poll);
6030 %}
6031 
6032 instruct loadConN0(iRegN dst, immN0 src) %{
6033   match(Set dst src);
6034 
6035   size(4);
6036   format %{ "CLR    $dst\t! compressed NULL ptr" %}
6037   ins_encode %{
6038     __ clr($dst$$Register);
6039   %}
6040   ins_pipe(ialu_imm);
6041 %}
6042 
6043 instruct loadConN(iRegN dst, immN src) %{
6044   match(Set dst src);
6045   ins_cost(DEFAULT_COST * 3/2);
6046   format %{ "SET    $src,$dst\t! compressed ptr" %}
6047   ins_encode %{
6048     Register dst = $dst$$Register;
6049     __ set_narrow_oop((jobject)$src$$constant, dst);
6050   %}
6051   ins_pipe(ialu_hi_lo_reg);
6052 %}
6053 
6054 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6055   match(Set dst src);
6056   ins_cost(DEFAULT_COST * 3/2);
6057   format %{ "SET    $src,$dst\t! compressed klass ptr" %}
6058   ins_encode %{
6059     Register dst = $dst$$Register;
6060     __ set_narrow_klass((Klass*)$src$$constant, dst);
6061   %}
6062   ins_pipe(ialu_hi_lo_reg);
6063 %}
6064 
6065 // Materialize long value (predicated by immL_cheap).
6066 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6067   match(Set dst con);
6068   effect(KILL tmp);
6069   ins_cost(DEFAULT_COST * 3);
6070   format %{ "SET64   $con,$dst KILL $tmp\t! cheap long" %}
6071   ins_encode %{
6072     __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6073   %}
6074   ins_pipe(loadConL);
6075 %}
6076 
6077 // Load long value from constant table (predicated by immL_expensive).
6078 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6079   match(Set dst con);
6080   ins_cost(MEMORY_REF_COST);
6081   format %{ "LDX     [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6082   ins_encode %{
6083       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6084     __ ldx($constanttablebase, con_offset, $dst$$Register);
6085   %}
6086   ins_pipe(loadConL);
6087 %}
6088 
6089 instruct loadConL0( iRegL dst, immL0 src ) %{
6090   match(Set dst src);
6091   ins_cost(DEFAULT_COST);
6092   size(4);
6093   format %{ "CLR    $dst\t! long" %}
6094   ins_encode( Set13( src, dst ) );
6095   ins_pipe(ialu_imm);
6096 %}
6097 
6098 instruct loadConL13( iRegL dst, immL13 src ) %{
6099   match(Set dst src);
6100   ins_cost(DEFAULT_COST * 2);
6101 
6102   size(4);
6103   format %{ "MOV    $src,$dst\t! long" %}
6104   ins_encode( Set13( src, dst ) );
6105   ins_pipe(ialu_imm);
6106 %}
6107 
6108 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6109   match(Set dst con);
6110   effect(KILL tmp);
6111   format %{ "LDF    [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6112   ins_encode %{
6113       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6114     __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6115   %}
6116   ins_pipe(loadConFD);
6117 %}
6118 
6119 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6120   match(Set dst con);
6121   effect(KILL tmp);
6122   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6123   ins_encode %{
6124     // XXX This is a quick fix for 6833573.
6125     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6126     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6127     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6128   %}
6129   ins_pipe(loadConFD);
6130 %}
6131 
6132 // Prefetch instructions for allocation.
6133 // Must be safe to execute with invalid address (cannot fault).
6134 
6135 instruct prefetchAlloc( memory mem ) %{
6136   predicate(AllocatePrefetchInstr == 0);
6137   match( PrefetchAllocation mem );
6138   ins_cost(MEMORY_REF_COST);
6139 
6140   format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6141   opcode(Assembler::prefetch_op3);
6142   ins_encode( form3_mem_prefetch_write( mem ) );
6143   ins_pipe(iload_mem);
6144 %}
6145 
6146 // Use BIS instruction to prefetch for allocation.
6147 // Could fault, need space at the end of TLAB.
6148 instruct prefetchAlloc_bis( iRegP dst ) %{
6149   predicate(AllocatePrefetchInstr == 1);
6150   match( PrefetchAllocation dst );
6151   ins_cost(MEMORY_REF_COST);
6152   size(4);
6153 
6154   format %{ "STXA   [$dst]\t! // Prefetch allocation using BIS" %}
6155   ins_encode %{
6156     __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6157   %}
6158   ins_pipe(istore_mem_reg);
6159 %}
6160 
6161 // Next code is used for finding next cache line address to prefetch.
6162 #ifndef _LP64
6163 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6164   match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6165   ins_cost(DEFAULT_COST);
6166   size(4);
6167 
6168   format %{ "AND    $src,$mask,$dst\t! next cache line address" %}
6169   ins_encode %{
6170     __ and3($src$$Register, $mask$$constant, $dst$$Register);
6171   %}
6172   ins_pipe(ialu_reg_imm);
6173 %}
6174 #else
6175 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6176   match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6177   ins_cost(DEFAULT_COST);
6178   size(4);
6179 
6180   format %{ "AND    $src,$mask,$dst\t! next cache line address" %}
6181   ins_encode %{
6182     __ and3($src$$Register, $mask$$constant, $dst$$Register);
6183   %}
6184   ins_pipe(ialu_reg_imm);
6185 %}
6186 #endif
6187 
6188 //----------Store Instructions-------------------------------------------------
6189 // Store Byte
6190 instruct storeB(memory mem, iRegI src) %{
6191   match(Set mem (StoreB mem src));
6192   ins_cost(MEMORY_REF_COST);
6193 
6194   format %{ "STB    $src,$mem\t! byte" %}
6195   opcode(Assembler::stb_op3);
6196   ins_encode(simple_form3_mem_reg( mem, src ) );
6197   ins_pipe(istore_mem_reg);
6198 %}
6199 
6200 instruct storeB0(memory mem, immI0 src) %{
6201   match(Set mem (StoreB mem src));
6202   ins_cost(MEMORY_REF_COST);
6203 
6204   format %{ "STB    $src,$mem\t! byte" %}
6205   opcode(Assembler::stb_op3);
6206   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6207   ins_pipe(istore_mem_zero);
6208 %}
6209 
6210 instruct storeCM0(memory mem, immI0 src) %{
6211   match(Set mem (StoreCM mem src));
6212   ins_cost(MEMORY_REF_COST);
6213 
6214   format %{ "STB    $src,$mem\t! CMS card-mark byte 0" %}
6215   opcode(Assembler::stb_op3);
6216   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6217   ins_pipe(istore_mem_zero);
6218 %}
6219 
6220 // Store Char/Short
6221 instruct storeC(memory mem, iRegI src) %{
6222   match(Set mem (StoreC mem src));
6223   ins_cost(MEMORY_REF_COST);
6224 
6225   format %{ "STH    $src,$mem\t! short" %}
6226   opcode(Assembler::sth_op3);
6227   ins_encode(simple_form3_mem_reg( mem, src ) );
6228   ins_pipe(istore_mem_reg);
6229 %}
6230 
6231 instruct storeC0(memory mem, immI0 src) %{
6232   match(Set mem (StoreC mem src));
6233   ins_cost(MEMORY_REF_COST);
6234 
6235   format %{ "STH    $src,$mem\t! short" %}
6236   opcode(Assembler::sth_op3);
6237   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6238   ins_pipe(istore_mem_zero);
6239 %}
6240 
6241 // Store Integer
6242 instruct storeI(memory mem, iRegI src) %{
6243   match(Set mem (StoreI mem src));
6244   ins_cost(MEMORY_REF_COST);
6245 
6246   format %{ "STW    $src,$mem" %}
6247   opcode(Assembler::stw_op3);
6248   ins_encode(simple_form3_mem_reg( mem, src ) );
6249   ins_pipe(istore_mem_reg);
6250 %}
6251 
6252 // Store Long
6253 instruct storeL(memory mem, iRegL src) %{
6254   match(Set mem (StoreL mem src));
6255   ins_cost(MEMORY_REF_COST);
6256   format %{ "STX    $src,$mem\t! long" %}
6257   opcode(Assembler::stx_op3);
6258   ins_encode(simple_form3_mem_reg( mem, src ) );
6259   ins_pipe(istore_mem_reg);
6260 %}
6261 
6262 instruct storeI0(memory mem, immI0 src) %{
6263   match(Set mem (StoreI mem src));
6264   ins_cost(MEMORY_REF_COST);
6265 
6266   format %{ "STW    $src,$mem" %}
6267   opcode(Assembler::stw_op3);
6268   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6269   ins_pipe(istore_mem_zero);
6270 %}
6271 
6272 instruct storeL0(memory mem, immL0 src) %{
6273   match(Set mem (StoreL mem src));
6274   ins_cost(MEMORY_REF_COST);
6275 
6276   format %{ "STX    $src,$mem" %}
6277   opcode(Assembler::stx_op3);
6278   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6279   ins_pipe(istore_mem_zero);
6280 %}
6281 
6282 // Store Integer from float register (used after fstoi)
6283 instruct storeI_Freg(memory mem, regF src) %{
6284   match(Set mem (StoreI mem src));
6285   ins_cost(MEMORY_REF_COST);
6286 
6287   format %{ "STF    $src,$mem\t! after fstoi/fdtoi" %}
6288   opcode(Assembler::stf_op3);
6289   ins_encode(simple_form3_mem_reg( mem, src ) );
6290   ins_pipe(fstoreF_mem_reg);
6291 %}
6292 
6293 // Store Pointer
6294 instruct storeP(memory dst, sp_ptr_RegP src) %{
6295   match(Set dst (StoreP dst src));
6296   ins_cost(MEMORY_REF_COST);
6297 
6298 #ifndef _LP64
6299   format %{ "STW    $src,$dst\t! ptr" %}
6300   opcode(Assembler::stw_op3, 0, REGP_OP);
6301 #else
6302   format %{ "STX    $src,$dst\t! ptr" %}
6303   opcode(Assembler::stx_op3, 0, REGP_OP);
6304 #endif
6305   ins_encode( form3_mem_reg( dst, src ) );
6306   ins_pipe(istore_mem_spORreg);
6307 %}
6308 
6309 instruct storeP0(memory dst, immP0 src) %{
6310   match(Set dst (StoreP dst src));
6311   ins_cost(MEMORY_REF_COST);
6312 
6313 #ifndef _LP64
6314   format %{ "STW    $src,$dst\t! ptr" %}
6315   opcode(Assembler::stw_op3, 0, REGP_OP);
6316 #else
6317   format %{ "STX    $src,$dst\t! ptr" %}
6318   opcode(Assembler::stx_op3, 0, REGP_OP);
6319 #endif
6320   ins_encode( form3_mem_reg( dst, R_G0 ) );
6321   ins_pipe(istore_mem_zero);
6322 %}
6323 
6324 // Store Compressed Pointer
6325 instruct storeN(memory dst, iRegN src) %{
6326    match(Set dst (StoreN dst src));
6327    ins_cost(MEMORY_REF_COST);
6328    size(4);
6329 
6330    format %{ "STW    $src,$dst\t! compressed ptr" %}
6331    ins_encode %{
6332      Register base = as_Register($dst$$base);
6333      Register index = as_Register($dst$$index);
6334      Register src = $src$$Register;
6335      if (index != G0) {
6336        __ stw(src, base, index);
6337      } else {
6338        __ stw(src, base, $dst$$disp);
6339      }
6340    %}
6341    ins_pipe(istore_mem_spORreg);
6342 %}
6343 
6344 instruct storeNKlass(memory dst, iRegN src) %{
6345    match(Set dst (StoreNKlass dst src));
6346    ins_cost(MEMORY_REF_COST);
6347    size(4);
6348 
6349    format %{ "STW    $src,$dst\t! compressed klass ptr" %}
6350    ins_encode %{
6351      Register base = as_Register($dst$$base);
6352      Register index = as_Register($dst$$index);
6353      Register src = $src$$Register;
6354      if (index != G0) {
6355        __ stw(src, base, index);
6356      } else {
6357        __ stw(src, base, $dst$$disp);
6358      }
6359    %}
6360    ins_pipe(istore_mem_spORreg);
6361 %}
6362 
6363 instruct storeN0(memory dst, immN0 src) %{
6364    match(Set dst (StoreN dst src));
6365    ins_cost(MEMORY_REF_COST);
6366    size(4);
6367 
6368    format %{ "STW    $src,$dst\t! compressed ptr" %}
6369    ins_encode %{
6370      Register base = as_Register($dst$$base);
6371      Register index = as_Register($dst$$index);
6372      if (index != G0) {
6373        __ stw(0, base, index);
6374      } else {
6375        __ stw(0, base, $dst$$disp);
6376      }
6377    %}
6378    ins_pipe(istore_mem_zero);
6379 %}
6380 
6381 // Store Double
6382 instruct storeD( memory mem, regD src) %{
6383   match(Set mem (StoreD mem src));
6384   ins_cost(MEMORY_REF_COST);
6385 
6386   format %{ "STDF   $src,$mem" %}
6387   opcode(Assembler::stdf_op3);
6388   ins_encode(simple_form3_mem_reg( mem, src ) );
6389   ins_pipe(fstoreD_mem_reg);
6390 %}
6391 
6392 instruct storeD0( memory mem, immD0 src) %{
6393   match(Set mem (StoreD mem src));
6394   ins_cost(MEMORY_REF_COST);
6395 
6396   format %{ "STX    $src,$mem" %}
6397   opcode(Assembler::stx_op3);
6398   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6399   ins_pipe(fstoreD_mem_zero);
6400 %}
6401 
6402 // Store Float
6403 instruct storeF( memory mem, regF src) %{
6404   match(Set mem (StoreF mem src));
6405   ins_cost(MEMORY_REF_COST);
6406 
6407   format %{ "STF    $src,$mem" %}
6408   opcode(Assembler::stf_op3);
6409   ins_encode(simple_form3_mem_reg( mem, src ) );
6410   ins_pipe(fstoreF_mem_reg);
6411 %}
6412 
6413 instruct storeF0( memory mem, immF0 src) %{
6414   match(Set mem (StoreF mem src));
6415   ins_cost(MEMORY_REF_COST);
6416 
6417   format %{ "STW    $src,$mem\t! storeF0" %}
6418   opcode(Assembler::stw_op3);
6419   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6420   ins_pipe(fstoreF_mem_zero);
6421 %}
6422 
6423 // Convert oop pointer into compressed form
6424 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6425   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6426   match(Set dst (EncodeP src));
6427   format %{ "encode_heap_oop $src, $dst" %}
6428   ins_encode %{
6429     __ encode_heap_oop($src$$Register, $dst$$Register);
6430   %}
6431   ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6432   ins_pipe(ialu_reg);
6433 %}
6434 
6435 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6436   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6437   match(Set dst (EncodeP src));
6438   format %{ "encode_heap_oop_not_null $src, $dst" %}
6439   ins_encode %{
6440     __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6441   %}
6442   ins_pipe(ialu_reg);
6443 %}
6444 
6445 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6446   predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6447             n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6448   match(Set dst (DecodeN src));
6449   format %{ "decode_heap_oop $src, $dst" %}
6450   ins_encode %{
6451     __ decode_heap_oop($src$$Register, $dst$$Register);
6452   %}
6453   ins_pipe(ialu_reg);
6454 %}
6455 
6456 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6457   predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6458             n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6459   match(Set dst (DecodeN src));
6460   format %{ "decode_heap_oop_not_null $src, $dst" %}
6461   ins_encode %{
6462     __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6463   %}
6464   ins_pipe(ialu_reg);
6465 %}
6466 
6467 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6468   match(Set dst (EncodePKlass src));
6469   format %{ "encode_klass_not_null $src, $dst" %}
6470   ins_encode %{
6471     __ encode_klass_not_null($src$$Register, $dst$$Register);
6472   %}
6473   ins_pipe(ialu_reg);
6474 %}
6475 
6476 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6477   match(Set dst (DecodeNKlass src));
6478   format %{ "decode_klass_not_null $src, $dst" %}
6479   ins_encode %{
6480     __ decode_klass_not_null($src$$Register, $dst$$Register);
6481   %}
6482   ins_pipe(ialu_reg);
6483 %}
6484 
6485 //----------MemBar Instructions-----------------------------------------------
6486 // Memory barrier flavors
6487 
6488 instruct membar_acquire() %{
6489   match(MemBarAcquire);
6490   match(LoadFence);
6491   ins_cost(4*MEMORY_REF_COST);
6492 
6493   size(0);
6494   format %{ "MEMBAR-acquire" %}
6495   ins_encode( enc_membar_acquire );
6496   ins_pipe(long_memory_op);
6497 %}
6498 
6499 instruct membar_acquire_lock() %{
6500   match(MemBarAcquireLock);
6501   ins_cost(0);
6502 
6503   size(0);
6504   format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6505   ins_encode( );
6506   ins_pipe(empty);
6507 %}
6508 
6509 instruct membar_release() %{
6510   match(MemBarRelease);
6511   match(StoreFence);
6512   ins_cost(4*MEMORY_REF_COST);
6513 
6514   size(0);
6515   format %{ "MEMBAR-release" %}
6516   ins_encode( enc_membar_release );
6517   ins_pipe(long_memory_op);
6518 %}
6519 
6520 instruct membar_release_lock() %{
6521   match(MemBarReleaseLock);
6522   ins_cost(0);
6523 
6524   size(0);
6525   format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6526   ins_encode( );
6527   ins_pipe(empty);
6528 %}
6529 
6530 instruct membar_volatile() %{
6531   match(MemBarVolatile);
6532   ins_cost(4*MEMORY_REF_COST);
6533 
6534   size(4);
6535   format %{ "MEMBAR-volatile" %}
6536   ins_encode( enc_membar_volatile );
6537   ins_pipe(long_memory_op);
6538 %}
6539 
6540 instruct unnecessary_membar_volatile() %{
6541   match(MemBarVolatile);
6542   predicate(Matcher::post_store_load_barrier(n));
6543   ins_cost(0);
6544 
6545   size(0);
6546   format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6547   ins_encode( );
6548   ins_pipe(empty);
6549 %}
6550 
6551 instruct membar_storestore() %{
6552   match(MemBarStoreStore);
6553   ins_cost(0);
6554 
6555   size(0);
6556   format %{ "!MEMBAR-storestore (empty encoding)" %}
6557   ins_encode( );
6558   ins_pipe(empty);
6559 %}
6560 
6561 //----------Register Move Instructions-----------------------------------------
6562 instruct roundDouble_nop(regD dst) %{
6563   match(Set dst (RoundDouble dst));
6564   ins_cost(0);
6565   // SPARC results are already "rounded" (i.e., normal-format IEEE)
6566   ins_encode( );
6567   ins_pipe(empty);
6568 %}
6569 
6570 
6571 instruct roundFloat_nop(regF dst) %{
6572   match(Set dst (RoundFloat dst));
6573   ins_cost(0);
6574   // SPARC results are already "rounded" (i.e., normal-format IEEE)
6575   ins_encode( );
6576   ins_pipe(empty);
6577 %}
6578 
6579 
6580 // Cast Index to Pointer for unsafe natives
6581 instruct castX2P(iRegX src, iRegP dst) %{
6582   match(Set dst (CastX2P src));
6583 
6584   format %{ "MOV    $src,$dst\t! IntX->Ptr" %}
6585   ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6586   ins_pipe(ialu_reg);
6587 %}
6588 
6589 // Cast Pointer to Index for unsafe natives
6590 instruct castP2X(iRegP src, iRegX dst) %{
6591   match(Set dst (CastP2X src));
6592 
6593   format %{ "MOV    $src,$dst\t! Ptr->IntX" %}
6594   ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6595   ins_pipe(ialu_reg);
6596 %}
6597 
6598 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6599   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6600   match(Set stkSlot src);   // chain rule
6601   ins_cost(MEMORY_REF_COST);
6602   format %{ "STDF   $src,$stkSlot\t!stk" %}
6603   opcode(Assembler::stdf_op3);
6604   ins_encode(simple_form3_mem_reg(stkSlot, src));
6605   ins_pipe(fstoreD_stk_reg);
6606 %}
6607 
6608 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6609   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6610   match(Set dst stkSlot);   // chain rule
6611   ins_cost(MEMORY_REF_COST);
6612   format %{ "LDDF   $stkSlot,$dst\t!stk" %}
6613   opcode(Assembler::lddf_op3);
6614   ins_encode(simple_form3_mem_reg(stkSlot, dst));
6615   ins_pipe(floadD_stk);
6616 %}
6617 
6618 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6619   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6620   match(Set stkSlot src);   // chain rule
6621   ins_cost(MEMORY_REF_COST);
6622   format %{ "STF   $src,$stkSlot\t!stk" %}
6623   opcode(Assembler::stf_op3);
6624   ins_encode(simple_form3_mem_reg(stkSlot, src));
6625   ins_pipe(fstoreF_stk_reg);
6626 %}
6627 
6628 //----------Conditional Move---------------------------------------------------
6629 // Conditional move
6630 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6631   match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6632   ins_cost(150);
6633   format %{ "MOV$cmp $pcc,$src,$dst" %}
6634   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6635   ins_pipe(ialu_reg);
6636 %}
6637 
6638 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6639   match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6640   ins_cost(140);
6641   format %{ "MOV$cmp $pcc,$src,$dst" %}
6642   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6643   ins_pipe(ialu_imm);
6644 %}
6645 
6646 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6647   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6648   ins_cost(150);
6649   size(4);
6650   format %{ "MOV$cmp  $icc,$src,$dst" %}
6651   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6652   ins_pipe(ialu_reg);
6653 %}
6654 
6655 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6656   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6657   ins_cost(140);
6658   size(4);
6659   format %{ "MOV$cmp  $icc,$src,$dst" %}
6660   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6661   ins_pipe(ialu_imm);
6662 %}
6663 
6664 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6665   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6666   ins_cost(150);
6667   size(4);
6668   format %{ "MOV$cmp  $icc,$src,$dst" %}
6669   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6670   ins_pipe(ialu_reg);
6671 %}
6672 
6673 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6674   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6675   ins_cost(140);
6676   size(4);
6677   format %{ "MOV$cmp  $icc,$src,$dst" %}
6678   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6679   ins_pipe(ialu_imm);
6680 %}
6681 
6682 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6683   match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6684   ins_cost(150);
6685   size(4);
6686   format %{ "MOV$cmp $fcc,$src,$dst" %}
6687   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6688   ins_pipe(ialu_reg);
6689 %}
6690 
6691 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6692   match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6693   ins_cost(140);
6694   size(4);
6695   format %{ "MOV$cmp $fcc,$src,$dst" %}
6696   ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6697   ins_pipe(ialu_imm);
6698 %}
6699 
6700 // Conditional move for RegN. Only cmov(reg,reg).
6701 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6702   match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6703   ins_cost(150);
6704   format %{ "MOV$cmp $pcc,$src,$dst" %}
6705   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6706   ins_pipe(ialu_reg);
6707 %}
6708 
6709 // This instruction also works with CmpN so we don't need cmovNN_reg.
6710 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6711   match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6712   ins_cost(150);
6713   size(4);
6714   format %{ "MOV$cmp  $icc,$src,$dst" %}
6715   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6716   ins_pipe(ialu_reg);
6717 %}
6718 
6719 // This instruction also works with CmpN so we don't need cmovNN_reg.
6720 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6721   match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6722   ins_cost(150);
6723   size(4);
6724   format %{ "MOV$cmp  $icc,$src,$dst" %}
6725   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6726   ins_pipe(ialu_reg);
6727 %}
6728 
6729 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6730   match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6731   ins_cost(150);
6732   size(4);
6733   format %{ "MOV$cmp $fcc,$src,$dst" %}
6734   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6735   ins_pipe(ialu_reg);
6736 %}
6737 
6738 // Conditional move
6739 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6740   match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6741   ins_cost(150);
6742   format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6743   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6744   ins_pipe(ialu_reg);
6745 %}
6746 
6747 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6748   match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6749   ins_cost(140);
6750   format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6751   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6752   ins_pipe(ialu_imm);
6753 %}
6754 
6755 // This instruction also works with CmpN so we don't need cmovPN_reg.
6756 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6757   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6758   ins_cost(150);
6759 
6760   size(4);
6761   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6762   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6763   ins_pipe(ialu_reg);
6764 %}
6765 
6766 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6767   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6768   ins_cost(150);
6769 
6770   size(4);
6771   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6772   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6773   ins_pipe(ialu_reg);
6774 %}
6775 
6776 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6777   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6778   ins_cost(140);
6779 
6780   size(4);
6781   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6782   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6783   ins_pipe(ialu_imm);
6784 %}
6785 
6786 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6787   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6788   ins_cost(140);
6789 
6790   size(4);
6791   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6792   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6793   ins_pipe(ialu_imm);
6794 %}
6795 
6796 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6797   match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6798   ins_cost(150);
6799   size(4);
6800   format %{ "MOV$cmp $fcc,$src,$dst" %}
6801   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6802   ins_pipe(ialu_imm);
6803 %}
6804 
6805 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6806   match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6807   ins_cost(140);
6808   size(4);
6809   format %{ "MOV$cmp $fcc,$src,$dst" %}
6810   ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6811   ins_pipe(ialu_imm);
6812 %}
6813 
6814 // Conditional move
6815 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6816   match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6817   ins_cost(150);
6818   opcode(0x101);
6819   format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6820   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6821   ins_pipe(int_conditional_float_move);
6822 %}
6823 
6824 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6825   match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6826   ins_cost(150);
6827 
6828   size(4);
6829   format %{ "FMOVS$cmp $icc,$src,$dst" %}
6830   opcode(0x101);
6831   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6832   ins_pipe(int_conditional_float_move);
6833 %}
6834 
6835 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6836   match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6837   ins_cost(150);
6838 
6839   size(4);
6840   format %{ "FMOVS$cmp $icc,$src,$dst" %}
6841   opcode(0x101);
6842   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6843   ins_pipe(int_conditional_float_move);
6844 %}
6845 
6846 // Conditional move,
6847 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6848   match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6849   ins_cost(150);
6850   size(4);
6851   format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6852   opcode(0x1);
6853   ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6854   ins_pipe(int_conditional_double_move);
6855 %}
6856 
6857 // Conditional move
6858 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6859   match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6860   ins_cost(150);
6861   size(4);
6862   opcode(0x102);
6863   format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6864   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6865   ins_pipe(int_conditional_double_move);
6866 %}
6867 
6868 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6869   match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6870   ins_cost(150);
6871 
6872   size(4);
6873   format %{ "FMOVD$cmp $icc,$src,$dst" %}
6874   opcode(0x102);
6875   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6876   ins_pipe(int_conditional_double_move);
6877 %}
6878 
6879 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6880   match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6881   ins_cost(150);
6882 
6883   size(4);
6884   format %{ "FMOVD$cmp $icc,$src,$dst" %}
6885   opcode(0x102);
6886   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6887   ins_pipe(int_conditional_double_move);
6888 %}
6889 
6890 // Conditional move,
6891 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6892   match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6893   ins_cost(150);
6894   size(4);
6895   format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6896   opcode(0x2);
6897   ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6898   ins_pipe(int_conditional_double_move);
6899 %}
6900 
6901 // Conditional move
6902 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6903   match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6904   ins_cost(150);
6905   format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6906   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6907   ins_pipe(ialu_reg);
6908 %}
6909 
6910 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6911   match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6912   ins_cost(140);
6913   format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6914   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6915   ins_pipe(ialu_imm);
6916 %}
6917 
6918 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6919   match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6920   ins_cost(150);
6921 
6922   size(4);
6923   format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
6924   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6925   ins_pipe(ialu_reg);
6926 %}
6927 
6928 
6929 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6930   match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6931   ins_cost(150);
6932 
6933   size(4);
6934   format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
6935   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6936   ins_pipe(ialu_reg);
6937 %}
6938 
6939 
6940 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6941   match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6942   ins_cost(150);
6943 
6944   size(4);
6945   format %{ "MOV$cmp  $fcc,$src,$dst\t! long" %}
6946   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6947   ins_pipe(ialu_reg);
6948 %}
6949 
6950 
6951 
6952 //----------OS and Locking Instructions----------------------------------------
6953 
6954 // This name is KNOWN by the ADLC and cannot be changed.
6955 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6956 // for this guy.
6957 instruct tlsLoadP(g2RegP dst) %{
6958   match(Set dst (ThreadLocal));
6959 
6960   size(0);
6961   ins_cost(0);
6962   format %{ "# TLS is in G2" %}
6963   ins_encode( /*empty encoding*/ );
6964   ins_pipe(ialu_none);
6965 %}
6966 
6967 instruct checkCastPP( iRegP dst ) %{
6968   match(Set dst (CheckCastPP dst));
6969 
6970   size(0);
6971   format %{ "# checkcastPP of $dst" %}
6972   ins_encode( /*empty encoding*/ );
6973   ins_pipe(empty);
6974 %}
6975 
6976 
6977 instruct castPP( iRegP dst ) %{
6978   match(Set dst (CastPP dst));
6979   format %{ "# castPP of $dst" %}
6980   ins_encode( /*empty encoding*/ );
6981   ins_pipe(empty);
6982 %}
6983 
6984 instruct castII( iRegI dst ) %{
6985   match(Set dst (CastII dst));
6986   format %{ "# castII of $dst" %}
6987   ins_encode( /*empty encoding*/ );
6988   ins_cost(0);
6989   ins_pipe(empty);
6990 %}
6991 
6992 //----------Arithmetic Instructions--------------------------------------------
6993 // Addition Instructions
6994 // Register Addition
6995 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6996   match(Set dst (AddI src1 src2));
6997 
6998   size(4);
6999   format %{ "ADD    $src1,$src2,$dst" %}
7000   ins_encode %{
7001     __ add($src1$$Register, $src2$$Register, $dst$$Register);
7002   %}
7003   ins_pipe(ialu_reg_reg);
7004 %}
7005 
7006 // Immediate Addition
7007 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7008   match(Set dst (AddI src1 src2));
7009 
7010   size(4);
7011   format %{ "ADD    $src1,$src2,$dst" %}
7012   opcode(Assembler::add_op3, Assembler::arith_op);
7013   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7014   ins_pipe(ialu_reg_imm);
7015 %}
7016 
7017 // Pointer Register Addition
7018 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7019   match(Set dst (AddP src1 src2));
7020 
7021   size(4);
7022   format %{ "ADD    $src1,$src2,$dst" %}
7023   opcode(Assembler::add_op3, Assembler::arith_op);
7024   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7025   ins_pipe(ialu_reg_reg);
7026 %}
7027 
7028 // Pointer Immediate Addition
7029 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7030   match(Set dst (AddP src1 src2));
7031 
7032   size(4);
7033   format %{ "ADD    $src1,$src2,$dst" %}
7034   opcode(Assembler::add_op3, Assembler::arith_op);
7035   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7036   ins_pipe(ialu_reg_imm);
7037 %}
7038 
7039 // Long Addition
7040 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7041   match(Set dst (AddL src1 src2));
7042 
7043   size(4);
7044   format %{ "ADD    $src1,$src2,$dst\t! long" %}
7045   opcode(Assembler::add_op3, Assembler::arith_op);
7046   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7047   ins_pipe(ialu_reg_reg);
7048 %}
7049 
7050 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7051   match(Set dst (AddL src1 con));
7052 
7053   size(4);
7054   format %{ "ADD    $src1,$con,$dst" %}
7055   opcode(Assembler::add_op3, Assembler::arith_op);
7056   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7057   ins_pipe(ialu_reg_imm);
7058 %}
7059 
7060 //----------Conditional_store--------------------------------------------------
7061 // Conditional-store of the updated heap-top.
7062 // Used during allocation of the shared heap.
7063 // Sets flags (EQ) on success.  Implemented with a CASA on Sparc.
7064 
7065 // LoadP-locked.  Same as a regular pointer load when used with a compare-swap
7066 instruct loadPLocked(iRegP dst, memory mem) %{
7067   match(Set dst (LoadPLocked mem));
7068   ins_cost(MEMORY_REF_COST);
7069 
7070 #ifndef _LP64
7071   format %{ "LDUW   $mem,$dst\t! ptr" %}
7072   opcode(Assembler::lduw_op3, 0, REGP_OP);
7073 #else
7074   format %{ "LDX    $mem,$dst\t! ptr" %}
7075   opcode(Assembler::ldx_op3, 0, REGP_OP);
7076 #endif
7077   ins_encode( form3_mem_reg( mem, dst ) );
7078   ins_pipe(iload_mem);
7079 %}
7080 
7081 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7082   match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7083   effect( KILL newval );
7084   format %{ "CASA   [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7085             "CMP    R_G3,$oldval\t\t! See if we made progress"  %}
7086   ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7087   ins_pipe( long_memory_op );
7088 %}
7089 
7090 // Conditional-store of an int value.
7091 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7092   match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7093   effect( KILL newval );
7094   format %{ "CASA   [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7095             "CMP    $oldval,$newval\t\t! See if we made progress"  %}
7096   ins_encode( enc_cas(mem_ptr,oldval,newval) );
7097   ins_pipe( long_memory_op );
7098 %}
7099 
7100 // Conditional-store of a long value.
7101 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7102   match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7103   effect( KILL newval );
7104   format %{ "CASXA  [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7105             "CMP    $oldval,$newval\t\t! See if we made progress"  %}
7106   ins_encode( enc_cas(mem_ptr,oldval,newval) );
7107   ins_pipe( long_memory_op );
7108 %}
7109 
7110 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7111 
7112 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7113   predicate(VM_Version::supports_cx8());
7114   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7115   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7116   format %{
7117             "MOV    $newval,O7\n\t"
7118             "CASXA  [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7119             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7120             "MOV    1,$res\n\t"
7121             "MOVne  xcc,R_G0,$res"
7122   %}
7123   ins_encode( enc_casx(mem_ptr, oldval, newval),
7124               enc_lflags_ne_to_boolean(res) );
7125   ins_pipe( long_memory_op );
7126 %}
7127 
7128 
7129 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7130   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7131   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7132   format %{
7133             "MOV    $newval,O7\n\t"
7134             "CASA   [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7135             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7136             "MOV    1,$res\n\t"
7137             "MOVne  icc,R_G0,$res"
7138   %}
7139   ins_encode( enc_casi(mem_ptr, oldval, newval),
7140               enc_iflags_ne_to_boolean(res) );
7141   ins_pipe( long_memory_op );
7142 %}
7143 
7144 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7145 #ifdef _LP64
7146   predicate(VM_Version::supports_cx8());
7147 #endif
7148   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7149   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7150   format %{
7151             "MOV    $newval,O7\n\t"
7152             "CASA_PTR  [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7153             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7154             "MOV    1,$res\n\t"
7155             "MOVne  xcc,R_G0,$res"
7156   %}
7157 #ifdef _LP64
7158   ins_encode( enc_casx(mem_ptr, oldval, newval),
7159               enc_lflags_ne_to_boolean(res) );
7160 #else
7161   ins_encode( enc_casi(mem_ptr, oldval, newval),
7162               enc_iflags_ne_to_boolean(res) );
7163 #endif
7164   ins_pipe( long_memory_op );
7165 %}
7166 
7167 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7168   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7169   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7170   format %{
7171             "MOV    $newval,O7\n\t"
7172             "CASA   [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7173             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7174             "MOV    1,$res\n\t"
7175             "MOVne  icc,R_G0,$res"
7176   %}
7177   ins_encode( enc_casi(mem_ptr, oldval, newval),
7178               enc_iflags_ne_to_boolean(res) );
7179   ins_pipe( long_memory_op );
7180 %}
7181 
7182 instruct xchgI( memory mem, iRegI newval) %{
7183   match(Set newval (GetAndSetI mem newval));
7184   format %{ "SWAP  [$mem],$newval" %}
7185   size(4);
7186   ins_encode %{
7187     __ swap($mem$$Address, $newval$$Register);
7188   %}
7189   ins_pipe( long_memory_op );
7190 %}
7191 
7192 #ifndef _LP64
7193 instruct xchgP( memory mem, iRegP newval) %{
7194   match(Set newval (GetAndSetP mem newval));
7195   format %{ "SWAP  [$mem],$newval" %}
7196   size(4);
7197   ins_encode %{
7198     __ swap($mem$$Address, $newval$$Register);
7199   %}
7200   ins_pipe( long_memory_op );
7201 %}
7202 #endif
7203 
7204 instruct xchgN( memory mem, iRegN newval) %{
7205   match(Set newval (GetAndSetN mem newval));
7206   format %{ "SWAP  [$mem],$newval" %}
7207   size(4);
7208   ins_encode %{
7209     __ swap($mem$$Address, $newval$$Register);
7210   %}
7211   ins_pipe( long_memory_op );
7212 %}
7213 
7214 //---------------------
7215 // Subtraction Instructions
7216 // Register Subtraction
7217 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7218   match(Set dst (SubI src1 src2));
7219 
7220   size(4);
7221   format %{ "SUB    $src1,$src2,$dst" %}
7222   opcode(Assembler::sub_op3, Assembler::arith_op);
7223   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7224   ins_pipe(ialu_reg_reg);
7225 %}
7226 
7227 // Immediate Subtraction
7228 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7229   match(Set dst (SubI src1 src2));
7230 
7231   size(4);
7232   format %{ "SUB    $src1,$src2,$dst" %}
7233   opcode(Assembler::sub_op3, Assembler::arith_op);
7234   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7235   ins_pipe(ialu_reg_imm);
7236 %}
7237 
7238 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7239   match(Set dst (SubI zero src2));
7240 
7241   size(4);
7242   format %{ "NEG    $src2,$dst" %}
7243   opcode(Assembler::sub_op3, Assembler::arith_op);
7244   ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7245   ins_pipe(ialu_zero_reg);
7246 %}
7247 
7248 // Long subtraction
7249 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7250   match(Set dst (SubL src1 src2));
7251 
7252   size(4);
7253   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7254   opcode(Assembler::sub_op3, Assembler::arith_op);
7255   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7256   ins_pipe(ialu_reg_reg);
7257 %}
7258 
7259 // Immediate Subtraction
7260 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7261   match(Set dst (SubL src1 con));
7262 
7263   size(4);
7264   format %{ "SUB    $src1,$con,$dst\t! long" %}
7265   opcode(Assembler::sub_op3, Assembler::arith_op);
7266   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7267   ins_pipe(ialu_reg_imm);
7268 %}
7269 
7270 // Long negation
7271 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7272   match(Set dst (SubL zero src2));
7273 
7274   size(4);
7275   format %{ "NEG    $src2,$dst\t! long" %}
7276   opcode(Assembler::sub_op3, Assembler::arith_op);
7277   ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7278   ins_pipe(ialu_zero_reg);
7279 %}
7280 
7281 // Multiplication Instructions
7282 // Integer Multiplication
7283 // Register Multiplication
7284 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7285   match(Set dst (MulI src1 src2));
7286 
7287   size(4);
7288   format %{ "MULX   $src1,$src2,$dst" %}
7289   opcode(Assembler::mulx_op3, Assembler::arith_op);
7290   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7291   ins_pipe(imul_reg_reg);
7292 %}
7293 
7294 // Immediate Multiplication
7295 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7296   match(Set dst (MulI src1 src2));
7297 
7298   size(4);
7299   format %{ "MULX   $src1,$src2,$dst" %}
7300   opcode(Assembler::mulx_op3, Assembler::arith_op);
7301   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7302   ins_pipe(imul_reg_imm);
7303 %}
7304 
7305 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7306   match(Set dst (MulL src1 src2));
7307   ins_cost(DEFAULT_COST * 5);
7308   size(4);
7309   format %{ "MULX   $src1,$src2,$dst\t! long" %}
7310   opcode(Assembler::mulx_op3, Assembler::arith_op);
7311   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7312   ins_pipe(mulL_reg_reg);
7313 %}
7314 
7315 // Immediate Multiplication
7316 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7317   match(Set dst (MulL src1 src2));
7318   ins_cost(DEFAULT_COST * 5);
7319   size(4);
7320   format %{ "MULX   $src1,$src2,$dst" %}
7321   opcode(Assembler::mulx_op3, Assembler::arith_op);
7322   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7323   ins_pipe(mulL_reg_imm);
7324 %}
7325 
7326 // Integer Division
7327 // Register Division
7328 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7329   match(Set dst (DivI src1 src2));
7330   ins_cost((2+71)*DEFAULT_COST);
7331 
7332   format %{ "SRA     $src2,0,$src2\n\t"
7333             "SRA     $src1,0,$src1\n\t"
7334             "SDIVX   $src1,$src2,$dst" %}
7335   ins_encode( idiv_reg( src1, src2, dst ) );
7336   ins_pipe(sdiv_reg_reg);
7337 %}
7338 
7339 // Immediate Division
7340 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7341   match(Set dst (DivI src1 src2));
7342   ins_cost((2+71)*DEFAULT_COST);
7343 
7344   format %{ "SRA     $src1,0,$src1\n\t"
7345             "SDIVX   $src1,$src2,$dst" %}
7346   ins_encode( idiv_imm( src1, src2, dst ) );
7347   ins_pipe(sdiv_reg_imm);
7348 %}
7349 
7350 //----------Div-By-10-Expansion------------------------------------------------
7351 // Extract hi bits of a 32x32->64 bit multiply.
7352 // Expand rule only, not matched
7353 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7354   effect( DEF dst, USE src1, USE src2 );
7355   format %{ "MULX   $src1,$src2,$dst\t! Used in div-by-10\n\t"
7356             "SRLX   $dst,#32,$dst\t\t! Extract only hi word of result" %}
7357   ins_encode( enc_mul_hi(dst,src1,src2));
7358   ins_pipe(sdiv_reg_reg);
7359 %}
7360 
7361 // Magic constant, reciprocal of 10
7362 instruct loadConI_x66666667(iRegIsafe dst) %{
7363   effect( DEF dst );
7364 
7365   size(8);
7366   format %{ "SET    0x66666667,$dst\t! Used in div-by-10" %}
7367   ins_encode( Set32(0x66666667, dst) );
7368   ins_pipe(ialu_hi_lo_reg);
7369 %}
7370 
7371 // Register Shift Right Arithmetic Long by 32-63
7372 instruct sra_31( iRegI dst, iRegI src ) %{
7373   effect( DEF dst, USE src );
7374   format %{ "SRA    $src,31,$dst\t! Used in div-by-10" %}
7375   ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7376   ins_pipe(ialu_reg_reg);
7377 %}
7378 
7379 // Arithmetic Shift Right by 8-bit immediate
7380 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7381   effect( DEF dst, USE src );
7382   format %{ "SRA    $src,2,$dst\t! Used in div-by-10" %}
7383   opcode(Assembler::sra_op3, Assembler::arith_op);
7384   ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7385   ins_pipe(ialu_reg_imm);
7386 %}
7387 
7388 // Integer DIV with 10
7389 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7390   match(Set dst (DivI src div));
7391   ins_cost((6+6)*DEFAULT_COST);
7392   expand %{
7393     iRegIsafe tmp1;               // Killed temps;
7394     iRegIsafe tmp2;               // Killed temps;
7395     iRegI tmp3;                   // Killed temps;
7396     iRegI tmp4;                   // Killed temps;
7397     loadConI_x66666667( tmp1 );   // SET  0x66666667 -> tmp1
7398     mul_hi( tmp2, src, tmp1 );    // MUL  hibits(src * tmp1) -> tmp2
7399     sra_31( tmp3, src );          // SRA  src,31 -> tmp3
7400     sra_reg_2( tmp4, tmp2 );      // SRA  tmp2,2 -> tmp4
7401     subI_reg_reg( dst,tmp4,tmp3); // SUB  tmp4 - tmp3 -> dst
7402   %}
7403 %}
7404 
7405 // Register Long Division
7406 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7407   match(Set dst (DivL src1 src2));
7408   ins_cost(DEFAULT_COST*71);
7409   size(4);
7410   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7411   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7412   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7413   ins_pipe(divL_reg_reg);
7414 %}
7415 
7416 // Register Long Division
7417 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7418   match(Set dst (DivL src1 src2));
7419   ins_cost(DEFAULT_COST*71);
7420   size(4);
7421   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7422   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7423   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7424   ins_pipe(divL_reg_imm);
7425 %}
7426 
7427 // Integer Remainder
7428 // Register Remainder
7429 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7430   match(Set dst (ModI src1 src2));
7431   effect( KILL ccr, KILL temp);
7432 
7433   format %{ "SREM   $src1,$src2,$dst" %}
7434   ins_encode( irem_reg(src1, src2, dst, temp) );
7435   ins_pipe(sdiv_reg_reg);
7436 %}
7437 
7438 // Immediate Remainder
7439 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7440   match(Set dst (ModI src1 src2));
7441   effect( KILL ccr, KILL temp);
7442 
7443   format %{ "SREM   $src1,$src2,$dst" %}
7444   ins_encode( irem_imm(src1, src2, dst, temp) );
7445   ins_pipe(sdiv_reg_imm);
7446 %}
7447 
7448 // Register Long Remainder
7449 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7450   effect(DEF dst, USE src1, USE src2);
7451   size(4);
7452   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7453   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7454   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7455   ins_pipe(divL_reg_reg);
7456 %}
7457 
7458 // Register Long Division
7459 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7460   effect(DEF dst, USE src1, USE src2);
7461   size(4);
7462   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7463   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7464   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7465   ins_pipe(divL_reg_imm);
7466 %}
7467 
7468 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7469   effect(DEF dst, USE src1, USE src2);
7470   size(4);
7471   format %{ "MULX   $src1,$src2,$dst\t! long" %}
7472   opcode(Assembler::mulx_op3, Assembler::arith_op);
7473   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7474   ins_pipe(mulL_reg_reg);
7475 %}
7476 
7477 // Immediate Multiplication
7478 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7479   effect(DEF dst, USE src1, USE src2);
7480   size(4);
7481   format %{ "MULX   $src1,$src2,$dst" %}
7482   opcode(Assembler::mulx_op3, Assembler::arith_op);
7483   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7484   ins_pipe(mulL_reg_imm);
7485 %}
7486 
7487 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7488   effect(DEF dst, USE src1, USE src2);
7489   size(4);
7490   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7491   opcode(Assembler::sub_op3, Assembler::arith_op);
7492   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7493   ins_pipe(ialu_reg_reg);
7494 %}
7495 
7496 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7497   effect(DEF dst, USE src1, USE src2);
7498   size(4);
7499   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7500   opcode(Assembler::sub_op3, Assembler::arith_op);
7501   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7502   ins_pipe(ialu_reg_reg);
7503 %}
7504 
7505 // Register Long Remainder
7506 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7507   match(Set dst (ModL src1 src2));
7508   ins_cost(DEFAULT_COST*(71 + 6 + 1));
7509   expand %{
7510     iRegL tmp1;
7511     iRegL tmp2;
7512     divL_reg_reg_1(tmp1, src1, src2);
7513     mulL_reg_reg_1(tmp2, tmp1, src2);
7514     subL_reg_reg_1(dst,  src1, tmp2);
7515   %}
7516 %}
7517 
7518 // Register Long Remainder
7519 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7520   match(Set dst (ModL src1 src2));
7521   ins_cost(DEFAULT_COST*(71 + 6 + 1));
7522   expand %{
7523     iRegL tmp1;
7524     iRegL tmp2;
7525     divL_reg_imm13_1(tmp1, src1, src2);
7526     mulL_reg_imm13_1(tmp2, tmp1, src2);
7527     subL_reg_reg_2  (dst,  src1, tmp2);
7528   %}
7529 %}
7530 
7531 // Integer Shift Instructions
7532 // Register Shift Left
7533 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7534   match(Set dst (LShiftI src1 src2));
7535 
7536   size(4);
7537   format %{ "SLL    $src1,$src2,$dst" %}
7538   opcode(Assembler::sll_op3, Assembler::arith_op);
7539   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7540   ins_pipe(ialu_reg_reg);
7541 %}
7542 
7543 // Register Shift Left Immediate
7544 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7545   match(Set dst (LShiftI src1 src2));
7546 
7547   size(4);
7548   format %{ "SLL    $src1,$src2,$dst" %}
7549   opcode(Assembler::sll_op3, Assembler::arith_op);
7550   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7551   ins_pipe(ialu_reg_imm);
7552 %}
7553 
7554 // Register Shift Left
7555 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7556   match(Set dst (LShiftL src1 src2));
7557 
7558   size(4);
7559   format %{ "SLLX   $src1,$src2,$dst" %}
7560   opcode(Assembler::sllx_op3, Assembler::arith_op);
7561   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7562   ins_pipe(ialu_reg_reg);
7563 %}
7564 
7565 // Register Shift Left Immediate
7566 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7567   match(Set dst (LShiftL src1 src2));
7568 
7569   size(4);
7570   format %{ "SLLX   $src1,$src2,$dst" %}
7571   opcode(Assembler::sllx_op3, Assembler::arith_op);
7572   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7573   ins_pipe(ialu_reg_imm);
7574 %}
7575 
7576 // Register Arithmetic Shift Right
7577 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7578   match(Set dst (RShiftI src1 src2));
7579   size(4);
7580   format %{ "SRA    $src1,$src2,$dst" %}
7581   opcode(Assembler::sra_op3, Assembler::arith_op);
7582   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7583   ins_pipe(ialu_reg_reg);
7584 %}
7585 
7586 // Register Arithmetic Shift Right Immediate
7587 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7588   match(Set dst (RShiftI src1 src2));
7589 
7590   size(4);
7591   format %{ "SRA    $src1,$src2,$dst" %}
7592   opcode(Assembler::sra_op3, Assembler::arith_op);
7593   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7594   ins_pipe(ialu_reg_imm);
7595 %}
7596 
7597 // Register Shift Right Arithmatic Long
7598 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7599   match(Set dst (RShiftL src1 src2));
7600 
7601   size(4);
7602   format %{ "SRAX   $src1,$src2,$dst" %}
7603   opcode(Assembler::srax_op3, Assembler::arith_op);
7604   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7605   ins_pipe(ialu_reg_reg);
7606 %}
7607 
7608 // Register Shift Left Immediate
7609 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7610   match(Set dst (RShiftL src1 src2));
7611 
7612   size(4);
7613   format %{ "SRAX   $src1,$src2,$dst" %}
7614   opcode(Assembler::srax_op3, Assembler::arith_op);
7615   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7616   ins_pipe(ialu_reg_imm);
7617 %}
7618 
7619 // Register Shift Right
7620 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7621   match(Set dst (URShiftI src1 src2));
7622 
7623   size(4);
7624   format %{ "SRL    $src1,$src2,$dst" %}
7625   opcode(Assembler::srl_op3, Assembler::arith_op);
7626   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7627   ins_pipe(ialu_reg_reg);
7628 %}
7629 
7630 // Register Shift Right Immediate
7631 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7632   match(Set dst (URShiftI src1 src2));
7633 
7634   size(4);
7635   format %{ "SRL    $src1,$src2,$dst" %}
7636   opcode(Assembler::srl_op3, Assembler::arith_op);
7637   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7638   ins_pipe(ialu_reg_imm);
7639 %}
7640 
7641 // Register Shift Right
7642 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7643   match(Set dst (URShiftL src1 src2));
7644 
7645   size(4);
7646   format %{ "SRLX   $src1,$src2,$dst" %}
7647   opcode(Assembler::srlx_op3, Assembler::arith_op);
7648   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7649   ins_pipe(ialu_reg_reg);
7650 %}
7651 
7652 // Register Shift Right Immediate
7653 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7654   match(Set dst (URShiftL src1 src2));
7655 
7656   size(4);
7657   format %{ "SRLX   $src1,$src2,$dst" %}
7658   opcode(Assembler::srlx_op3, Assembler::arith_op);
7659   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7660   ins_pipe(ialu_reg_imm);
7661 %}
7662 
7663 // Register Shift Right Immediate with a CastP2X
7664 #ifdef _LP64
7665 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7666   match(Set dst (URShiftL (CastP2X src1) src2));
7667   size(4);
7668   format %{ "SRLX   $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7669   opcode(Assembler::srlx_op3, Assembler::arith_op);
7670   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7671   ins_pipe(ialu_reg_imm);
7672 %}
7673 #else
7674 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7675   match(Set dst (URShiftI (CastP2X src1) src2));
7676   size(4);
7677   format %{ "SRL    $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7678   opcode(Assembler::srl_op3, Assembler::arith_op);
7679   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7680   ins_pipe(ialu_reg_imm);
7681 %}
7682 #endif
7683 
7684 
7685 //----------Floating Point Arithmetic Instructions-----------------------------
7686 
7687 //  Add float single precision
7688 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7689   match(Set dst (AddF src1 src2));
7690 
7691   size(4);
7692   format %{ "FADDS  $src1,$src2,$dst" %}
7693   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7694   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7695   ins_pipe(faddF_reg_reg);
7696 %}
7697 
7698 //  Add float double precision
7699 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7700   match(Set dst (AddD src1 src2));
7701 
7702   size(4);
7703   format %{ "FADDD  $src1,$src2,$dst" %}
7704   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7705   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7706   ins_pipe(faddD_reg_reg);
7707 %}
7708 
7709 //  Sub float single precision
7710 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7711   match(Set dst (SubF src1 src2));
7712 
7713   size(4);
7714   format %{ "FSUBS  $src1,$src2,$dst" %}
7715   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7716   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7717   ins_pipe(faddF_reg_reg);
7718 %}
7719 
7720 //  Sub float double precision
7721 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7722   match(Set dst (SubD src1 src2));
7723 
7724   size(4);
7725   format %{ "FSUBD  $src1,$src2,$dst" %}
7726   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7727   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7728   ins_pipe(faddD_reg_reg);
7729 %}
7730 
7731 //  Mul float single precision
7732 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7733   match(Set dst (MulF src1 src2));
7734 
7735   size(4);
7736   format %{ "FMULS  $src1,$src2,$dst" %}
7737   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7738   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7739   ins_pipe(fmulF_reg_reg);
7740 %}
7741 
7742 //  Mul float double precision
7743 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7744   match(Set dst (MulD src1 src2));
7745 
7746   size(4);
7747   format %{ "FMULD  $src1,$src2,$dst" %}
7748   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7749   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7750   ins_pipe(fmulD_reg_reg);
7751 %}
7752 
7753 //  Div float single precision
7754 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7755   match(Set dst (DivF src1 src2));
7756 
7757   size(4);
7758   format %{ "FDIVS  $src1,$src2,$dst" %}
7759   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7760   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7761   ins_pipe(fdivF_reg_reg);
7762 %}
7763 
7764 //  Div float double precision
7765 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7766   match(Set dst (DivD src1 src2));
7767 
7768   size(4);
7769   format %{ "FDIVD  $src1,$src2,$dst" %}
7770   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7771   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7772   ins_pipe(fdivD_reg_reg);
7773 %}
7774 
7775 //  Absolute float double precision
7776 instruct absD_reg(regD dst, regD src) %{
7777   match(Set dst (AbsD src));
7778 
7779   format %{ "FABSd  $src,$dst" %}
7780   ins_encode(fabsd(dst, src));
7781   ins_pipe(faddD_reg);
7782 %}
7783 
7784 //  Absolute float single precision
7785 instruct absF_reg(regF dst, regF src) %{
7786   match(Set dst (AbsF src));
7787 
7788   format %{ "FABSs  $src,$dst" %}
7789   ins_encode(fabss(dst, src));
7790   ins_pipe(faddF_reg);
7791 %}
7792 
7793 instruct negF_reg(regF dst, regF src) %{
7794   match(Set dst (NegF src));
7795 
7796   size(4);
7797   format %{ "FNEGs  $src,$dst" %}
7798   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7799   ins_encode(form3_opf_rs2F_rdF(src, dst));
7800   ins_pipe(faddF_reg);
7801 %}
7802 
7803 instruct negD_reg(regD dst, regD src) %{
7804   match(Set dst (NegD src));
7805 
7806   format %{ "FNEGd  $src,$dst" %}
7807   ins_encode(fnegd(dst, src));
7808   ins_pipe(faddD_reg);
7809 %}
7810 
7811 //  Sqrt float double precision
7812 instruct sqrtF_reg_reg(regF dst, regF src) %{
7813   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7814 
7815   size(4);
7816   format %{ "FSQRTS $src,$dst" %}
7817   ins_encode(fsqrts(dst, src));
7818   ins_pipe(fdivF_reg_reg);
7819 %}
7820 
7821 //  Sqrt float double precision
7822 instruct sqrtD_reg_reg(regD dst, regD src) %{
7823   match(Set dst (SqrtD src));
7824 
7825   size(4);
7826   format %{ "FSQRTD $src,$dst" %}
7827   ins_encode(fsqrtd(dst, src));
7828   ins_pipe(fdivD_reg_reg);
7829 %}
7830 
7831 //----------Logical Instructions-----------------------------------------------
7832 // And Instructions
7833 // Register And
7834 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7835   match(Set dst (AndI src1 src2));
7836 
7837   size(4);
7838   format %{ "AND    $src1,$src2,$dst" %}
7839   opcode(Assembler::and_op3, Assembler::arith_op);
7840   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7841   ins_pipe(ialu_reg_reg);
7842 %}
7843 
7844 // Immediate And
7845 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7846   match(Set dst (AndI src1 src2));
7847 
7848   size(4);
7849   format %{ "AND    $src1,$src2,$dst" %}
7850   opcode(Assembler::and_op3, Assembler::arith_op);
7851   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7852   ins_pipe(ialu_reg_imm);
7853 %}
7854 
7855 // Register And Long
7856 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7857   match(Set dst (AndL src1 src2));
7858 
7859   ins_cost(DEFAULT_COST);
7860   size(4);
7861   format %{ "AND    $src1,$src2,$dst\t! long" %}
7862   opcode(Assembler::and_op3, Assembler::arith_op);
7863   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7864   ins_pipe(ialu_reg_reg);
7865 %}
7866 
7867 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7868   match(Set dst (AndL src1 con));
7869 
7870   ins_cost(DEFAULT_COST);
7871   size(4);
7872   format %{ "AND    $src1,$con,$dst\t! long" %}
7873   opcode(Assembler::and_op3, Assembler::arith_op);
7874   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7875   ins_pipe(ialu_reg_imm);
7876 %}
7877 
7878 // Or Instructions
7879 // Register Or
7880 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7881   match(Set dst (OrI src1 src2));
7882 
7883   size(4);
7884   format %{ "OR     $src1,$src2,$dst" %}
7885   opcode(Assembler::or_op3, Assembler::arith_op);
7886   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7887   ins_pipe(ialu_reg_reg);
7888 %}
7889 
7890 // Immediate Or
7891 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7892   match(Set dst (OrI src1 src2));
7893 
7894   size(4);
7895   format %{ "OR     $src1,$src2,$dst" %}
7896   opcode(Assembler::or_op3, Assembler::arith_op);
7897   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7898   ins_pipe(ialu_reg_imm);
7899 %}
7900 
7901 // Register Or Long
7902 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7903   match(Set dst (OrL src1 src2));
7904 
7905   ins_cost(DEFAULT_COST);
7906   size(4);
7907   format %{ "OR     $src1,$src2,$dst\t! long" %}
7908   opcode(Assembler::or_op3, Assembler::arith_op);
7909   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7910   ins_pipe(ialu_reg_reg);
7911 %}
7912 
7913 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7914   match(Set dst (OrL src1 con));
7915   ins_cost(DEFAULT_COST*2);
7916 
7917   ins_cost(DEFAULT_COST);
7918   size(4);
7919   format %{ "OR     $src1,$con,$dst\t! long" %}
7920   opcode(Assembler::or_op3, Assembler::arith_op);
7921   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7922   ins_pipe(ialu_reg_imm);
7923 %}
7924 
7925 #ifndef _LP64
7926 
7927 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7928 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7929   match(Set dst (OrI src1 (CastP2X src2)));
7930 
7931   size(4);
7932   format %{ "OR     $src1,$src2,$dst" %}
7933   opcode(Assembler::or_op3, Assembler::arith_op);
7934   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7935   ins_pipe(ialu_reg_reg);
7936 %}
7937 
7938 #else
7939 
7940 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7941   match(Set dst (OrL src1 (CastP2X src2)));
7942 
7943   ins_cost(DEFAULT_COST);
7944   size(4);
7945   format %{ "OR     $src1,$src2,$dst\t! long" %}
7946   opcode(Assembler::or_op3, Assembler::arith_op);
7947   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7948   ins_pipe(ialu_reg_reg);
7949 %}
7950 
7951 #endif
7952 
7953 // Xor Instructions
7954 // Register Xor
7955 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7956   match(Set dst (XorI src1 src2));
7957 
7958   size(4);
7959   format %{ "XOR    $src1,$src2,$dst" %}
7960   opcode(Assembler::xor_op3, Assembler::arith_op);
7961   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7962   ins_pipe(ialu_reg_reg);
7963 %}
7964 
7965 // Immediate Xor
7966 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7967   match(Set dst (XorI src1 src2));
7968 
7969   size(4);
7970   format %{ "XOR    $src1,$src2,$dst" %}
7971   opcode(Assembler::xor_op3, Assembler::arith_op);
7972   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7973   ins_pipe(ialu_reg_imm);
7974 %}
7975 
7976 // Register Xor Long
7977 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7978   match(Set dst (XorL src1 src2));
7979 
7980   ins_cost(DEFAULT_COST);
7981   size(4);
7982   format %{ "XOR    $src1,$src2,$dst\t! long" %}
7983   opcode(Assembler::xor_op3, Assembler::arith_op);
7984   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7985   ins_pipe(ialu_reg_reg);
7986 %}
7987 
7988 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7989   match(Set dst (XorL src1 con));
7990 
7991   ins_cost(DEFAULT_COST);
7992   size(4);
7993   format %{ "XOR    $src1,$con,$dst\t! long" %}
7994   opcode(Assembler::xor_op3, Assembler::arith_op);
7995   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7996   ins_pipe(ialu_reg_imm);
7997 %}
7998 
7999 //----------Convert to Boolean-------------------------------------------------
8000 // Nice hack for 32-bit tests but doesn't work for
8001 // 64-bit pointers.
8002 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8003   match(Set dst (Conv2B src));
8004   effect( KILL ccr );
8005   ins_cost(DEFAULT_COST*2);
8006   format %{ "CMP    R_G0,$src\n\t"
8007             "ADDX   R_G0,0,$dst" %}
8008   ins_encode( enc_to_bool( src, dst ) );
8009   ins_pipe(ialu_reg_ialu);
8010 %}
8011 
8012 #ifndef _LP64
8013 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8014   match(Set dst (Conv2B src));
8015   effect( KILL ccr );
8016   ins_cost(DEFAULT_COST*2);
8017   format %{ "CMP    R_G0,$src\n\t"
8018             "ADDX   R_G0,0,$dst" %}
8019   ins_encode( enc_to_bool( src, dst ) );
8020   ins_pipe(ialu_reg_ialu);
8021 %}
8022 #else
8023 instruct convP2B( iRegI dst, iRegP src ) %{
8024   match(Set dst (Conv2B src));
8025   ins_cost(DEFAULT_COST*2);
8026   format %{ "MOV    $src,$dst\n\t"
8027             "MOVRNZ $src,1,$dst" %}
8028   ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8029   ins_pipe(ialu_clr_and_mover);
8030 %}
8031 #endif
8032 
8033 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8034   match(Set dst (CmpLTMask src zero));
8035   effect(KILL ccr);
8036   size(4);
8037   format %{ "SRA    $src,#31,$dst\t# cmpLTMask0" %}
8038   ins_encode %{
8039     __ sra($src$$Register, 31, $dst$$Register);
8040   %}
8041   ins_pipe(ialu_reg_imm);
8042 %}
8043 
8044 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8045   match(Set dst (CmpLTMask p q));
8046   effect( KILL ccr );
8047   ins_cost(DEFAULT_COST*4);
8048   format %{ "CMP    $p,$q\n\t"
8049             "MOV    #0,$dst\n\t"
8050             "BLT,a  .+8\n\t"
8051             "MOV    #-1,$dst" %}
8052   ins_encode( enc_ltmask(p,q,dst) );
8053   ins_pipe(ialu_reg_reg_ialu);
8054 %}
8055 
8056 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8057   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8058   effect(KILL ccr, TEMP tmp);
8059   ins_cost(DEFAULT_COST*3);
8060 
8061   format %{ "SUBcc  $p,$q,$p\t! p' = p-q\n\t"
8062             "ADD    $p,$y,$tmp\t! g3=p-q+y\n\t"
8063             "MOVlt  $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8064   ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8065   ins_pipe(cadd_cmpltmask);
8066 %}
8067 
8068 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8069   match(Set p (AndI (CmpLTMask p q) y));
8070   effect(KILL ccr);
8071   ins_cost(DEFAULT_COST*3);
8072 
8073   format %{ "CMP  $p,$q\n\t"
8074             "MOV  $y,$p\n\t"
8075             "MOVge G0,$p" %}
8076   ins_encode %{
8077     __ cmp($p$$Register, $q$$Register);
8078     __ mov($y$$Register, $p$$Register);
8079     __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8080   %}
8081   ins_pipe(ialu_reg_reg_ialu);
8082 %}
8083 
8084 //-----------------------------------------------------------------
8085 // Direct raw moves between float and general registers using VIS3.
8086 
8087 //  ins_pipe(faddF_reg);
8088 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8089   predicate(UseVIS >= 3);
8090   match(Set dst (MoveF2I src));
8091 
8092   format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8093   ins_encode %{
8094     __ movstouw($src$$FloatRegister, $dst$$Register);
8095   %}
8096   ins_pipe(ialu_reg_reg);
8097 %}
8098 
8099 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8100   predicate(UseVIS >= 3);
8101   match(Set dst (MoveI2F src));
8102 
8103   format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8104   ins_encode %{
8105     __ movwtos($src$$Register, $dst$$FloatRegister);
8106   %}
8107   ins_pipe(ialu_reg_reg);
8108 %}
8109 
8110 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8111   predicate(UseVIS >= 3);
8112   match(Set dst (MoveD2L src));
8113 
8114   format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8115   ins_encode %{
8116     __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8117   %}
8118   ins_pipe(ialu_reg_reg);
8119 %}
8120 
8121 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8122   predicate(UseVIS >= 3);
8123   match(Set dst (MoveL2D src));
8124 
8125   format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8126   ins_encode %{
8127     __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8128   %}
8129   ins_pipe(ialu_reg_reg);
8130 %}
8131 
8132 
8133 // Raw moves between float and general registers using stack.
8134 
8135 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8136   match(Set dst (MoveF2I src));
8137   effect(DEF dst, USE src);
8138   ins_cost(MEMORY_REF_COST);
8139 
8140   format %{ "LDUW   $src,$dst\t! MoveF2I" %}
8141   opcode(Assembler::lduw_op3);
8142   ins_encode(simple_form3_mem_reg( src, dst ) );
8143   ins_pipe(iload_mem);
8144 %}
8145 
8146 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8147   match(Set dst (MoveI2F src));
8148   effect(DEF dst, USE src);
8149   ins_cost(MEMORY_REF_COST);
8150 
8151   format %{ "LDF    $src,$dst\t! MoveI2F" %}
8152   opcode(Assembler::ldf_op3);
8153   ins_encode(simple_form3_mem_reg(src, dst));
8154   ins_pipe(floadF_stk);
8155 %}
8156 
8157 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8158   match(Set dst (MoveD2L src));
8159   effect(DEF dst, USE src);
8160   ins_cost(MEMORY_REF_COST);
8161 
8162   format %{ "LDX    $src,$dst\t! MoveD2L" %}
8163   opcode(Assembler::ldx_op3);
8164   ins_encode(simple_form3_mem_reg( src, dst ) );
8165   ins_pipe(iload_mem);
8166 %}
8167 
8168 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8169   match(Set dst (MoveL2D src));
8170   effect(DEF dst, USE src);
8171   ins_cost(MEMORY_REF_COST);
8172 
8173   format %{ "LDDF   $src,$dst\t! MoveL2D" %}
8174   opcode(Assembler::lddf_op3);
8175   ins_encode(simple_form3_mem_reg(src, dst));
8176   ins_pipe(floadD_stk);
8177 %}
8178 
8179 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8180   match(Set dst (MoveF2I src));
8181   effect(DEF dst, USE src);
8182   ins_cost(MEMORY_REF_COST);
8183 
8184   format %{ "STF   $src,$dst\t! MoveF2I" %}
8185   opcode(Assembler::stf_op3);
8186   ins_encode(simple_form3_mem_reg(dst, src));
8187   ins_pipe(fstoreF_stk_reg);
8188 %}
8189 
8190 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8191   match(Set dst (MoveI2F src));
8192   effect(DEF dst, USE src);
8193   ins_cost(MEMORY_REF_COST);
8194 
8195   format %{ "STW    $src,$dst\t! MoveI2F" %}
8196   opcode(Assembler::stw_op3);
8197   ins_encode(simple_form3_mem_reg( dst, src ) );
8198   ins_pipe(istore_mem_reg);
8199 %}
8200 
8201 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8202   match(Set dst (MoveD2L src));
8203   effect(DEF dst, USE src);
8204   ins_cost(MEMORY_REF_COST);
8205 
8206   format %{ "STDF   $src,$dst\t! MoveD2L" %}
8207   opcode(Assembler::stdf_op3);
8208   ins_encode(simple_form3_mem_reg(dst, src));
8209   ins_pipe(fstoreD_stk_reg);
8210 %}
8211 
8212 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8213   match(Set dst (MoveL2D src));
8214   effect(DEF dst, USE src);
8215   ins_cost(MEMORY_REF_COST);
8216 
8217   format %{ "STX    $src,$dst\t! MoveL2D" %}
8218   opcode(Assembler::stx_op3);
8219   ins_encode(simple_form3_mem_reg( dst, src ) );
8220   ins_pipe(istore_mem_reg);
8221 %}
8222 
8223 
8224 //----------Arithmetic Conversion Instructions---------------------------------
8225 // The conversions operations are all Alpha sorted.  Please keep it that way!
8226 
8227 instruct convD2F_reg(regF dst, regD src) %{
8228   match(Set dst (ConvD2F src));
8229   size(4);
8230   format %{ "FDTOS  $src,$dst" %}
8231   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8232   ins_encode(form3_opf_rs2D_rdF(src, dst));
8233   ins_pipe(fcvtD2F);
8234 %}
8235 
8236 
8237 // Convert a double to an int in a float register.
8238 // If the double is a NAN, stuff a zero in instead.
8239 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8240   effect(DEF dst, USE src, KILL fcc0);
8241   format %{ "FCMPd  fcc0,$src,$src\t! check for NAN\n\t"
8242             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8243             "FDTOI  $src,$dst\t! convert in delay slot\n\t"
8244             "FITOS  $dst,$dst\t! change NaN/max-int to valid float\n\t"
8245             "FSUBs  $dst,$dst,$dst\t! cleared only if nan\n"
8246       "skip:" %}
8247   ins_encode(form_d2i_helper(src,dst));
8248   ins_pipe(fcvtD2I);
8249 %}
8250 
8251 instruct convD2I_stk(stackSlotI dst, regD src) %{
8252   match(Set dst (ConvD2I src));
8253   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8254   expand %{
8255     regF tmp;
8256     convD2I_helper(tmp, src);
8257     regF_to_stkI(dst, tmp);
8258   %}
8259 %}
8260 
8261 instruct convD2I_reg(iRegI dst, regD src) %{
8262   predicate(UseVIS >= 3);
8263   match(Set dst (ConvD2I src));
8264   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8265   expand %{
8266     regF tmp;
8267     convD2I_helper(tmp, src);
8268     MoveF2I_reg_reg(dst, tmp);
8269   %}
8270 %}
8271 
8272 
8273 // Convert a double to a long in a double register.
8274 // If the double is a NAN, stuff a zero in instead.
8275 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8276   effect(DEF dst, USE src, KILL fcc0);
8277   format %{ "FCMPd  fcc0,$src,$src\t! check for NAN\n\t"
8278             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8279             "FDTOX  $src,$dst\t! convert in delay slot\n\t"
8280             "FXTOD  $dst,$dst\t! change NaN/max-long to valid double\n\t"
8281             "FSUBd  $dst,$dst,$dst\t! cleared only if nan\n"
8282       "skip:" %}
8283   ins_encode(form_d2l_helper(src,dst));
8284   ins_pipe(fcvtD2L);
8285 %}
8286 
8287 instruct convD2L_stk(stackSlotL dst, regD src) %{
8288   match(Set dst (ConvD2L src));
8289   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8290   expand %{
8291     regD tmp;
8292     convD2L_helper(tmp, src);
8293     regD_to_stkL(dst, tmp);
8294   %}
8295 %}
8296 
8297 instruct convD2L_reg(iRegL dst, regD src) %{
8298   predicate(UseVIS >= 3);
8299   match(Set dst (ConvD2L src));
8300   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8301   expand %{
8302     regD tmp;
8303     convD2L_helper(tmp, src);
8304     MoveD2L_reg_reg(dst, tmp);
8305   %}
8306 %}
8307 
8308 
8309 instruct convF2D_reg(regD dst, regF src) %{
8310   match(Set dst (ConvF2D src));
8311   format %{ "FSTOD  $src,$dst" %}
8312   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8313   ins_encode(form3_opf_rs2F_rdD(src, dst));
8314   ins_pipe(fcvtF2D);
8315 %}
8316 
8317 
8318 // Convert a float to an int in a float register.
8319 // If the float is a NAN, stuff a zero in instead.
8320 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8321   effect(DEF dst, USE src, KILL fcc0);
8322   format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
8323             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8324             "FSTOI  $src,$dst\t! convert in delay slot\n\t"
8325             "FITOS  $dst,$dst\t! change NaN/max-int to valid float\n\t"
8326             "FSUBs  $dst,$dst,$dst\t! cleared only if nan\n"
8327       "skip:" %}
8328   ins_encode(form_f2i_helper(src,dst));
8329   ins_pipe(fcvtF2I);
8330 %}
8331 
8332 instruct convF2I_stk(stackSlotI dst, regF src) %{
8333   match(Set dst (ConvF2I src));
8334   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8335   expand %{
8336     regF tmp;
8337     convF2I_helper(tmp, src);
8338     regF_to_stkI(dst, tmp);
8339   %}
8340 %}
8341 
8342 instruct convF2I_reg(iRegI dst, regF src) %{
8343   predicate(UseVIS >= 3);
8344   match(Set dst (ConvF2I src));
8345   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8346   expand %{
8347     regF tmp;
8348     convF2I_helper(tmp, src);
8349     MoveF2I_reg_reg(dst, tmp);
8350   %}
8351 %}
8352 
8353 
8354 // Convert a float to a long in a float register.
8355 // If the float is a NAN, stuff a zero in instead.
8356 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8357   effect(DEF dst, USE src, KILL fcc0);
8358   format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
8359             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8360             "FSTOX  $src,$dst\t! convert in delay slot\n\t"
8361             "FXTOD  $dst,$dst\t! change NaN/max-long to valid double\n\t"
8362             "FSUBd  $dst,$dst,$dst\t! cleared only if nan\n"
8363       "skip:" %}
8364   ins_encode(form_f2l_helper(src,dst));
8365   ins_pipe(fcvtF2L);
8366 %}
8367 
8368 instruct convF2L_stk(stackSlotL dst, regF src) %{
8369   match(Set dst (ConvF2L src));
8370   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8371   expand %{
8372     regD tmp;
8373     convF2L_helper(tmp, src);
8374     regD_to_stkL(dst, tmp);
8375   %}
8376 %}
8377 
8378 instruct convF2L_reg(iRegL dst, regF src) %{
8379   predicate(UseVIS >= 3);
8380   match(Set dst (ConvF2L src));
8381   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8382   expand %{
8383     regD tmp;
8384     convF2L_helper(tmp, src);
8385     MoveD2L_reg_reg(dst, tmp);
8386   %}
8387 %}
8388 
8389 
8390 instruct convI2D_helper(regD dst, regF tmp) %{
8391   effect(USE tmp, DEF dst);
8392   format %{ "FITOD  $tmp,$dst" %}
8393   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8394   ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8395   ins_pipe(fcvtI2D);
8396 %}
8397 
8398 instruct convI2D_stk(stackSlotI src, regD dst) %{
8399   match(Set dst (ConvI2D src));
8400   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8401   expand %{
8402     regF tmp;
8403     stkI_to_regF(tmp, src);
8404     convI2D_helper(dst, tmp);
8405   %}
8406 %}
8407 
8408 instruct convI2D_reg(regD_low dst, iRegI src) %{
8409   predicate(UseVIS >= 3);
8410   match(Set dst (ConvI2D src));
8411   expand %{
8412     regF tmp;
8413     MoveI2F_reg_reg(tmp, src);
8414     convI2D_helper(dst, tmp);
8415   %}
8416 %}
8417 
8418 instruct convI2D_mem(regD_low dst, memory mem) %{
8419   match(Set dst (ConvI2D (LoadI mem)));
8420   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8421   format %{ "LDF    $mem,$dst\n\t"
8422             "FITOD  $dst,$dst" %}
8423   opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8424   ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8425   ins_pipe(floadF_mem);
8426 %}
8427 
8428 
8429 instruct convI2F_helper(regF dst, regF tmp) %{
8430   effect(DEF dst, USE tmp);
8431   format %{ "FITOS  $tmp,$dst" %}
8432   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8433   ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8434   ins_pipe(fcvtI2F);
8435 %}
8436 
8437 instruct convI2F_stk(regF dst, stackSlotI src) %{
8438   match(Set dst (ConvI2F src));
8439   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8440   expand %{
8441     regF tmp;
8442     stkI_to_regF(tmp,src);
8443     convI2F_helper(dst, tmp);
8444   %}
8445 %}
8446 
8447 instruct convI2F_reg(regF dst, iRegI src) %{
8448   predicate(UseVIS >= 3);
8449   match(Set dst (ConvI2F src));
8450   ins_cost(DEFAULT_COST);
8451   expand %{
8452     regF tmp;
8453     MoveI2F_reg_reg(tmp, src);
8454     convI2F_helper(dst, tmp);
8455   %}
8456 %}
8457 
8458 instruct convI2F_mem( regF dst, memory mem ) %{
8459   match(Set dst (ConvI2F (LoadI mem)));
8460   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8461   format %{ "LDF    $mem,$dst\n\t"
8462             "FITOS  $dst,$dst" %}
8463   opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8464   ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8465   ins_pipe(floadF_mem);
8466 %}
8467 
8468 
8469 instruct convI2L_reg(iRegL dst, iRegI src) %{
8470   match(Set dst (ConvI2L src));
8471   size(4);
8472   format %{ "SRA    $src,0,$dst\t! int->long" %}
8473   opcode(Assembler::sra_op3, Assembler::arith_op);
8474   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8475   ins_pipe(ialu_reg_reg);
8476 %}
8477 
8478 // Zero-extend convert int to long
8479 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8480   match(Set dst (AndL (ConvI2L src) mask) );
8481   size(4);
8482   format %{ "SRL    $src,0,$dst\t! zero-extend int to long" %}
8483   opcode(Assembler::srl_op3, Assembler::arith_op);
8484   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8485   ins_pipe(ialu_reg_reg);
8486 %}
8487 
8488 // Zero-extend long
8489 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8490   match(Set dst (AndL src mask) );
8491   size(4);
8492   format %{ "SRL    $src,0,$dst\t! zero-extend long" %}
8493   opcode(Assembler::srl_op3, Assembler::arith_op);
8494   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8495   ins_pipe(ialu_reg_reg);
8496 %}
8497 
8498 
8499 //-----------
8500 // Long to Double conversion using V8 opcodes.
8501 // Still useful because cheetah traps and becomes
8502 // amazingly slow for some common numbers.
8503 
8504 // Magic constant, 0x43300000
8505 instruct loadConI_x43300000(iRegI dst) %{
8506   effect(DEF dst);
8507   size(4);
8508   format %{ "SETHI  HI(0x43300000),$dst\t! 2^52" %}
8509   ins_encode(SetHi22(0x43300000, dst));
8510   ins_pipe(ialu_none);
8511 %}
8512 
8513 // Magic constant, 0x41f00000
8514 instruct loadConI_x41f00000(iRegI dst) %{
8515   effect(DEF dst);
8516   size(4);
8517   format %{ "SETHI  HI(0x41f00000),$dst\t! 2^32" %}
8518   ins_encode(SetHi22(0x41f00000, dst));
8519   ins_pipe(ialu_none);
8520 %}
8521 
8522 // Construct a double from two float halves
8523 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8524   effect(DEF dst, USE src1, USE src2);
8525   size(8);
8526   format %{ "FMOVS  $src1.hi,$dst.hi\n\t"
8527             "FMOVS  $src2.lo,$dst.lo" %}
8528   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8529   ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8530   ins_pipe(faddD_reg_reg);
8531 %}
8532 
8533 // Convert integer in high half of a double register (in the lower half of
8534 // the double register file) to double
8535 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8536   effect(DEF dst, USE src);
8537   size(4);
8538   format %{ "FITOD  $src,$dst" %}
8539   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8540   ins_encode(form3_opf_rs2D_rdD(src, dst));
8541   ins_pipe(fcvtLHi2D);
8542 %}
8543 
8544 // Add float double precision
8545 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8546   effect(DEF dst, USE src1, USE src2);
8547   size(4);
8548   format %{ "FADDD  $src1,$src2,$dst" %}
8549   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8550   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8551   ins_pipe(faddD_reg_reg);
8552 %}
8553 
8554 // Sub float double precision
8555 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8556   effect(DEF dst, USE src1, USE src2);
8557   size(4);
8558   format %{ "FSUBD  $src1,$src2,$dst" %}
8559   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8560   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8561   ins_pipe(faddD_reg_reg);
8562 %}
8563 
8564 // Mul float double precision
8565 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8566   effect(DEF dst, USE src1, USE src2);
8567   size(4);
8568   format %{ "FMULD  $src1,$src2,$dst" %}
8569   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8570   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8571   ins_pipe(fmulD_reg_reg);
8572 %}
8573 
8574 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8575   match(Set dst (ConvL2D src));
8576   ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8577 
8578   expand %{
8579     regD_low   tmpsrc;
8580     iRegI      ix43300000;
8581     iRegI      ix41f00000;
8582     stackSlotL lx43300000;
8583     stackSlotL lx41f00000;
8584     regD_low   dx43300000;
8585     regD       dx41f00000;
8586     regD       tmp1;
8587     regD_low   tmp2;
8588     regD       tmp3;
8589     regD       tmp4;
8590 
8591     stkL_to_regD(tmpsrc, src);
8592 
8593     loadConI_x43300000(ix43300000);
8594     loadConI_x41f00000(ix41f00000);
8595     regI_to_stkLHi(lx43300000, ix43300000);
8596     regI_to_stkLHi(lx41f00000, ix41f00000);
8597     stkL_to_regD(dx43300000, lx43300000);
8598     stkL_to_regD(dx41f00000, lx41f00000);
8599 
8600     convI2D_regDHi_regD(tmp1, tmpsrc);
8601     regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8602     subD_regD_regD(tmp3, tmp2, dx43300000);
8603     mulD_regD_regD(tmp4, tmp1, dx41f00000);
8604     addD_regD_regD(dst, tmp3, tmp4);
8605   %}
8606 %}
8607 
8608 // Long to Double conversion using fast fxtof
8609 instruct convL2D_helper(regD dst, regD tmp) %{
8610   effect(DEF dst, USE tmp);
8611   size(4);
8612   format %{ "FXTOD  $tmp,$dst" %}
8613   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8614   ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8615   ins_pipe(fcvtL2D);
8616 %}
8617 
8618 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8619   predicate(VM_Version::has_fast_fxtof());
8620   match(Set dst (ConvL2D src));
8621   ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8622   expand %{
8623     regD tmp;
8624     stkL_to_regD(tmp, src);
8625     convL2D_helper(dst, tmp);
8626   %}
8627 %}
8628 
8629 instruct convL2D_reg(regD dst, iRegL src) %{
8630   predicate(UseVIS >= 3);
8631   match(Set dst (ConvL2D src));
8632   expand %{
8633     regD tmp;
8634     MoveL2D_reg_reg(tmp, src);
8635     convL2D_helper(dst, tmp);
8636   %}
8637 %}
8638 
8639 // Long to Float conversion using fast fxtof
8640 instruct convL2F_helper(regF dst, regD tmp) %{
8641   effect(DEF dst, USE tmp);
8642   size(4);
8643   format %{ "FXTOS  $tmp,$dst" %}
8644   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8645   ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8646   ins_pipe(fcvtL2F);
8647 %}
8648 
8649 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8650   match(Set dst (ConvL2F src));
8651   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8652   expand %{
8653     regD tmp;
8654     stkL_to_regD(tmp, src);
8655     convL2F_helper(dst, tmp);
8656   %}
8657 %}
8658 
8659 instruct convL2F_reg(regF dst, iRegL src) %{
8660   predicate(UseVIS >= 3);
8661   match(Set dst (ConvL2F src));
8662   ins_cost(DEFAULT_COST);
8663   expand %{
8664     regD tmp;
8665     MoveL2D_reg_reg(tmp, src);
8666     convL2F_helper(dst, tmp);
8667   %}
8668 %}
8669 
8670 //-----------
8671 
8672 instruct convL2I_reg(iRegI dst, iRegL src) %{
8673   match(Set dst (ConvL2I src));
8674 #ifndef _LP64
8675   format %{ "MOV    $src.lo,$dst\t! long->int" %}
8676   ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8677   ins_pipe(ialu_move_reg_I_to_L);
8678 #else
8679   size(4);
8680   format %{ "SRA    $src,R_G0,$dst\t! long->int" %}
8681   ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8682   ins_pipe(ialu_reg);
8683 #endif
8684 %}
8685 
8686 // Register Shift Right Immediate
8687 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8688   match(Set dst (ConvL2I (RShiftL src cnt)));
8689 
8690   size(4);
8691   format %{ "SRAX   $src,$cnt,$dst" %}
8692   opcode(Assembler::srax_op3, Assembler::arith_op);
8693   ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8694   ins_pipe(ialu_reg_imm);
8695 %}
8696 
8697 //----------Control Flow Instructions------------------------------------------
8698 // Compare Instructions
8699 // Compare Integers
8700 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8701   match(Set icc (CmpI op1 op2));
8702   effect( DEF icc, USE op1, USE op2 );
8703 
8704   size(4);
8705   format %{ "CMP    $op1,$op2" %}
8706   opcode(Assembler::subcc_op3, Assembler::arith_op);
8707   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8708   ins_pipe(ialu_cconly_reg_reg);
8709 %}
8710 
8711 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8712   match(Set icc (CmpU op1 op2));
8713 
8714   size(4);
8715   format %{ "CMP    $op1,$op2\t! unsigned" %}
8716   opcode(Assembler::subcc_op3, Assembler::arith_op);
8717   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8718   ins_pipe(ialu_cconly_reg_reg);
8719 %}
8720 
8721 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8722   match(Set icc (CmpI op1 op2));
8723   effect( DEF icc, USE op1 );
8724 
8725   size(4);
8726   format %{ "CMP    $op1,$op2" %}
8727   opcode(Assembler::subcc_op3, Assembler::arith_op);
8728   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8729   ins_pipe(ialu_cconly_reg_imm);
8730 %}
8731 
8732 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8733   match(Set icc (CmpI (AndI op1 op2) zero));
8734 
8735   size(4);
8736   format %{ "BTST   $op2,$op1" %}
8737   opcode(Assembler::andcc_op3, Assembler::arith_op);
8738   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8739   ins_pipe(ialu_cconly_reg_reg_zero);
8740 %}
8741 
8742 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8743   match(Set icc (CmpI (AndI op1 op2) zero));
8744 
8745   size(4);
8746   format %{ "BTST   $op2,$op1" %}
8747   opcode(Assembler::andcc_op3, Assembler::arith_op);
8748   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8749   ins_pipe(ialu_cconly_reg_imm_zero);
8750 %}
8751 
8752 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8753   match(Set xcc (CmpL op1 op2));
8754   effect( DEF xcc, USE op1, USE op2 );
8755 
8756   size(4);
8757   format %{ "CMP    $op1,$op2\t\t! long" %}
8758   opcode(Assembler::subcc_op3, Assembler::arith_op);
8759   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8760   ins_pipe(ialu_cconly_reg_reg);
8761 %}
8762 
8763 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8764   match(Set xcc (CmpL op1 con));
8765   effect( DEF xcc, USE op1, USE con );
8766 
8767   size(4);
8768   format %{ "CMP    $op1,$con\t\t! long" %}
8769   opcode(Assembler::subcc_op3, Assembler::arith_op);
8770   ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8771   ins_pipe(ialu_cconly_reg_reg);
8772 %}
8773 
8774 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8775   match(Set xcc (CmpL (AndL op1 op2) zero));
8776   effect( DEF xcc, USE op1, USE op2 );
8777 
8778   size(4);
8779   format %{ "BTST   $op1,$op2\t\t! long" %}
8780   opcode(Assembler::andcc_op3, Assembler::arith_op);
8781   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8782   ins_pipe(ialu_cconly_reg_reg);
8783 %}
8784 
8785 // useful for checking the alignment of a pointer:
8786 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8787   match(Set xcc (CmpL (AndL op1 con) zero));
8788   effect( DEF xcc, USE op1, USE con );
8789 
8790   size(4);
8791   format %{ "BTST   $op1,$con\t\t! long" %}
8792   opcode(Assembler::andcc_op3, Assembler::arith_op);
8793   ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8794   ins_pipe(ialu_cconly_reg_reg);
8795 %}
8796 
8797 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8798   match(Set icc (CmpU op1 op2));
8799 
8800   size(4);
8801   format %{ "CMP    $op1,$op2\t! unsigned" %}
8802   opcode(Assembler::subcc_op3, Assembler::arith_op);
8803   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8804   ins_pipe(ialu_cconly_reg_imm);
8805 %}
8806 
8807 // Compare Pointers
8808 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8809   match(Set pcc (CmpP op1 op2));
8810 
8811   size(4);
8812   format %{ "CMP    $op1,$op2\t! ptr" %}
8813   opcode(Assembler::subcc_op3, Assembler::arith_op);
8814   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8815   ins_pipe(ialu_cconly_reg_reg);
8816 %}
8817 
8818 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8819   match(Set pcc (CmpP op1 op2));
8820 
8821   size(4);
8822   format %{ "CMP    $op1,$op2\t! ptr" %}
8823   opcode(Assembler::subcc_op3, Assembler::arith_op);
8824   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8825   ins_pipe(ialu_cconly_reg_imm);
8826 %}
8827 
8828 // Compare Narrow oops
8829 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8830   match(Set icc (CmpN op1 op2));
8831 
8832   size(4);
8833   format %{ "CMP    $op1,$op2\t! compressed ptr" %}
8834   opcode(Assembler::subcc_op3, Assembler::arith_op);
8835   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8836   ins_pipe(ialu_cconly_reg_reg);
8837 %}
8838 
8839 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8840   match(Set icc (CmpN op1 op2));
8841 
8842   size(4);
8843   format %{ "CMP    $op1,$op2\t! compressed ptr" %}
8844   opcode(Assembler::subcc_op3, Assembler::arith_op);
8845   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8846   ins_pipe(ialu_cconly_reg_imm);
8847 %}
8848 
8849 //----------Max and Min--------------------------------------------------------
8850 // Min Instructions
8851 // Conditional move for min
8852 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8853   effect( USE_DEF op2, USE op1, USE icc );
8854 
8855   size(4);
8856   format %{ "MOVlt  icc,$op1,$op2\t! min" %}
8857   opcode(Assembler::less);
8858   ins_encode( enc_cmov_reg_minmax(op2,op1) );
8859   ins_pipe(ialu_reg_flags);
8860 %}
8861 
8862 // Min Register with Register.
8863 instruct minI_eReg(iRegI op1, iRegI op2) %{
8864   match(Set op2 (MinI op1 op2));
8865   ins_cost(DEFAULT_COST*2);
8866   expand %{
8867     flagsReg icc;
8868     compI_iReg(icc,op1,op2);
8869     cmovI_reg_lt(op2,op1,icc);
8870   %}
8871 %}
8872 
8873 // Max Instructions
8874 // Conditional move for max
8875 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8876   effect( USE_DEF op2, USE op1, USE icc );
8877   format %{ "MOVgt  icc,$op1,$op2\t! max" %}
8878   opcode(Assembler::greater);
8879   ins_encode( enc_cmov_reg_minmax(op2,op1) );
8880   ins_pipe(ialu_reg_flags);
8881 %}
8882 
8883 // Max Register with Register
8884 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8885   match(Set op2 (MaxI op1 op2));
8886   ins_cost(DEFAULT_COST*2);
8887   expand %{
8888     flagsReg icc;
8889     compI_iReg(icc,op1,op2);
8890     cmovI_reg_gt(op2,op1,icc);
8891   %}
8892 %}
8893 
8894 
8895 //----------Float Compares----------------------------------------------------
8896 // Compare floating, generate condition code
8897 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8898   match(Set fcc (CmpF src1 src2));
8899 
8900   size(4);
8901   format %{ "FCMPs  $fcc,$src1,$src2" %}
8902   opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8903   ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8904   ins_pipe(faddF_fcc_reg_reg_zero);
8905 %}
8906 
8907 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8908   match(Set fcc (CmpD src1 src2));
8909 
8910   size(4);
8911   format %{ "FCMPd  $fcc,$src1,$src2" %}
8912   opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8913   ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8914   ins_pipe(faddD_fcc_reg_reg_zero);
8915 %}
8916 
8917 
8918 // Compare floating, generate -1,0,1
8919 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8920   match(Set dst (CmpF3 src1 src2));
8921   effect(KILL fcc0);
8922   ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8923   format %{ "fcmpl  $dst,$src1,$src2" %}
8924   // Primary = float
8925   opcode( true );
8926   ins_encode( floating_cmp( dst, src1, src2 ) );
8927   ins_pipe( floating_cmp );
8928 %}
8929 
8930 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8931   match(Set dst (CmpD3 src1 src2));
8932   effect(KILL fcc0);
8933   ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8934   format %{ "dcmpl  $dst,$src1,$src2" %}
8935   // Primary = double (not float)
8936   opcode( false );
8937   ins_encode( floating_cmp( dst, src1, src2 ) );
8938   ins_pipe( floating_cmp );
8939 %}
8940 
8941 //----------Branches---------------------------------------------------------
8942 // Jump
8943 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8944 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8945   match(Jump switch_val);
8946   effect(TEMP table);
8947 
8948   ins_cost(350);
8949 
8950   format %{  "ADD    $constanttablebase, $constantoffset, O7\n\t"
8951              "LD     [O7 + $switch_val], O7\n\t"
8952              "JUMP   O7" %}
8953   ins_encode %{
8954     // Calculate table address into a register.
8955     Register table_reg;
8956     Register label_reg = O7;
8957     // If we are calculating the size of this instruction don't trust
8958     // zero offsets because they might change when
8959     // MachConstantBaseNode decides to optimize the constant table
8960     // base.
8961     if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
8962       table_reg = $constanttablebase;
8963     } else {
8964       table_reg = O7;
8965       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
8966       __ add($constanttablebase, con_offset, table_reg);
8967     }
8968 
8969     // Jump to base address + switch value
8970     __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8971     __ jmp(label_reg, G0);
8972     __ delayed()->nop();
8973   %}
8974   ins_pipe(ialu_reg_reg);
8975 %}
8976 
8977 // Direct Branch.  Use V8 version with longer range.
8978 instruct branch(label labl) %{
8979   match(Goto);
8980   effect(USE labl);
8981 
8982   size(8);
8983   ins_cost(BRANCH_COST);
8984   format %{ "BA     $labl" %}
8985   ins_encode %{
8986     Label* L = $labl$$label;
8987     __ ba(*L);
8988     __ delayed()->nop();
8989   %}
8990   ins_avoid_back_to_back(AVOID_BEFORE);
8991   ins_pipe(br);
8992 %}
8993 
8994 // Direct Branch, short with no delay slot
8995 instruct branch_short(label labl) %{
8996   match(Goto);
8997   predicate(UseCBCond);
8998   effect(USE labl);
8999 
9000   size(4);
9001   ins_cost(BRANCH_COST);
9002   format %{ "BA     $labl\t! short branch" %}
9003   ins_encode %{
9004     Label* L = $labl$$label;
9005     assert(__ use_cbcond(*L), "back to back cbcond");
9006     __ ba_short(*L);
9007   %}
9008   ins_short_branch(1);
9009   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9010   ins_pipe(cbcond_reg_imm);
9011 %}
9012 
9013 // Conditional Direct Branch
9014 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9015   match(If cmp icc);
9016   effect(USE labl);
9017 
9018   size(8);
9019   ins_cost(BRANCH_COST);
9020   format %{ "BP$cmp   $icc,$labl" %}
9021   // Prim = bits 24-22, Secnd = bits 31-30
9022   ins_encode( enc_bp( labl, cmp, icc ) );
9023   ins_avoid_back_to_back(AVOID_BEFORE);
9024   ins_pipe(br_cc);
9025 %}
9026 
9027 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9028   match(If cmp icc);
9029   effect(USE labl);
9030 
9031   ins_cost(BRANCH_COST);
9032   format %{ "BP$cmp  $icc,$labl" %}
9033   // Prim = bits 24-22, Secnd = bits 31-30
9034   ins_encode( enc_bp( labl, cmp, icc ) );
9035   ins_avoid_back_to_back(AVOID_BEFORE);
9036   ins_pipe(br_cc);
9037 %}
9038 
9039 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9040   match(If cmp pcc);
9041   effect(USE labl);
9042 
9043   size(8);
9044   ins_cost(BRANCH_COST);
9045   format %{ "BP$cmp  $pcc,$labl" %}
9046   ins_encode %{
9047     Label* L = $labl$$label;
9048     Assembler::Predict predict_taken =
9049       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9050 
9051     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9052     __ delayed()->nop();
9053   %}
9054   ins_avoid_back_to_back(AVOID_BEFORE);
9055   ins_pipe(br_cc);
9056 %}
9057 
9058 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9059   match(If cmp fcc);
9060   effect(USE labl);
9061 
9062   size(8);
9063   ins_cost(BRANCH_COST);
9064   format %{ "FBP$cmp $fcc,$labl" %}
9065   ins_encode %{
9066     Label* L = $labl$$label;
9067     Assembler::Predict predict_taken =
9068       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9069 
9070     __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9071     __ delayed()->nop();
9072   %}
9073   ins_avoid_back_to_back(AVOID_BEFORE);
9074   ins_pipe(br_fcc);
9075 %}
9076 
9077 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9078   match(CountedLoopEnd cmp icc);
9079   effect(USE labl);
9080 
9081   size(8);
9082   ins_cost(BRANCH_COST);
9083   format %{ "BP$cmp   $icc,$labl\t! Loop end" %}
9084   // Prim = bits 24-22, Secnd = bits 31-30
9085   ins_encode( enc_bp( labl, cmp, icc ) );
9086   ins_avoid_back_to_back(AVOID_BEFORE);
9087   ins_pipe(br_cc);
9088 %}
9089 
9090 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9091   match(CountedLoopEnd cmp icc);
9092   effect(USE labl);
9093 
9094   size(8);
9095   ins_cost(BRANCH_COST);
9096   format %{ "BP$cmp  $icc,$labl\t! Loop end" %}
9097   // Prim = bits 24-22, Secnd = bits 31-30
9098   ins_encode( enc_bp( labl, cmp, icc ) );
9099   ins_avoid_back_to_back(AVOID_BEFORE);
9100   ins_pipe(br_cc);
9101 %}
9102 
9103 // Compare and branch instructions
9104 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9105   match(If cmp (CmpI op1 op2));
9106   effect(USE labl, KILL icc);
9107 
9108   size(12);
9109   ins_cost(BRANCH_COST);
9110   format %{ "CMP    $op1,$op2\t! int\n\t"
9111             "BP$cmp   $labl" %}
9112   ins_encode %{
9113     Label* L = $labl$$label;
9114     Assembler::Predict predict_taken =
9115       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9116     __ cmp($op1$$Register, $op2$$Register);
9117     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9118     __ delayed()->nop();
9119   %}
9120   ins_pipe(cmp_br_reg_reg);
9121 %}
9122 
9123 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9124   match(If cmp (CmpI op1 op2));
9125   effect(USE labl, KILL icc);
9126 
9127   size(12);
9128   ins_cost(BRANCH_COST);
9129   format %{ "CMP    $op1,$op2\t! int\n\t"
9130             "BP$cmp   $labl" %}
9131   ins_encode %{
9132     Label* L = $labl$$label;
9133     Assembler::Predict predict_taken =
9134       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9135     __ cmp($op1$$Register, $op2$$constant);
9136     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9137     __ delayed()->nop();
9138   %}
9139   ins_pipe(cmp_br_reg_imm);
9140 %}
9141 
9142 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9143   match(If cmp (CmpU op1 op2));
9144   effect(USE labl, KILL icc);
9145 
9146   size(12);
9147   ins_cost(BRANCH_COST);
9148   format %{ "CMP    $op1,$op2\t! unsigned\n\t"
9149             "BP$cmp  $labl" %}
9150   ins_encode %{
9151     Label* L = $labl$$label;
9152     Assembler::Predict predict_taken =
9153       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9154     __ cmp($op1$$Register, $op2$$Register);
9155     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9156     __ delayed()->nop();
9157   %}
9158   ins_pipe(cmp_br_reg_reg);
9159 %}
9160 
9161 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9162   match(If cmp (CmpU op1 op2));
9163   effect(USE labl, KILL icc);
9164 
9165   size(12);
9166   ins_cost(BRANCH_COST);
9167   format %{ "CMP    $op1,$op2\t! unsigned\n\t"
9168             "BP$cmp  $labl" %}
9169   ins_encode %{
9170     Label* L = $labl$$label;
9171     Assembler::Predict predict_taken =
9172       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9173     __ cmp($op1$$Register, $op2$$constant);
9174     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9175     __ delayed()->nop();
9176   %}
9177   ins_pipe(cmp_br_reg_imm);
9178 %}
9179 
9180 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9181   match(If cmp (CmpL op1 op2));
9182   effect(USE labl, KILL xcc);
9183 
9184   size(12);
9185   ins_cost(BRANCH_COST);
9186   format %{ "CMP    $op1,$op2\t! long\n\t"
9187             "BP$cmp   $labl" %}
9188   ins_encode %{
9189     Label* L = $labl$$label;
9190     Assembler::Predict predict_taken =
9191       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9192     __ cmp($op1$$Register, $op2$$Register);
9193     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9194     __ delayed()->nop();
9195   %}
9196   ins_pipe(cmp_br_reg_reg);
9197 %}
9198 
9199 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9200   match(If cmp (CmpL op1 op2));
9201   effect(USE labl, KILL xcc);
9202 
9203   size(12);
9204   ins_cost(BRANCH_COST);
9205   format %{ "CMP    $op1,$op2\t! long\n\t"
9206             "BP$cmp   $labl" %}
9207   ins_encode %{
9208     Label* L = $labl$$label;
9209     Assembler::Predict predict_taken =
9210       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9211     __ cmp($op1$$Register, $op2$$constant);
9212     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9213     __ delayed()->nop();
9214   %}
9215   ins_pipe(cmp_br_reg_imm);
9216 %}
9217 
9218 // Compare Pointers and branch
9219 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9220   match(If cmp (CmpP op1 op2));
9221   effect(USE labl, KILL pcc);
9222 
9223   size(12);
9224   ins_cost(BRANCH_COST);
9225   format %{ "CMP    $op1,$op2\t! ptr\n\t"
9226             "B$cmp   $labl" %}
9227   ins_encode %{
9228     Label* L = $labl$$label;
9229     Assembler::Predict predict_taken =
9230       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9231     __ cmp($op1$$Register, $op2$$Register);
9232     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9233     __ delayed()->nop();
9234   %}
9235   ins_pipe(cmp_br_reg_reg);
9236 %}
9237 
9238 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9239   match(If cmp (CmpP op1 null));
9240   effect(USE labl, KILL pcc);
9241 
9242   size(12);
9243   ins_cost(BRANCH_COST);
9244   format %{ "CMP    $op1,0\t! ptr\n\t"
9245             "B$cmp   $labl" %}
9246   ins_encode %{
9247     Label* L = $labl$$label;
9248     Assembler::Predict predict_taken =
9249       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9250     __ cmp($op1$$Register, G0);
9251     // bpr() is not used here since it has shorter distance.
9252     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9253     __ delayed()->nop();
9254   %}
9255   ins_pipe(cmp_br_reg_reg);
9256 %}
9257 
9258 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9259   match(If cmp (CmpN op1 op2));
9260   effect(USE labl, KILL icc);
9261 
9262   size(12);
9263   ins_cost(BRANCH_COST);
9264   format %{ "CMP    $op1,$op2\t! compressed ptr\n\t"
9265             "BP$cmp   $labl" %}
9266   ins_encode %{
9267     Label* L = $labl$$label;
9268     Assembler::Predict predict_taken =
9269       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9270     __ cmp($op1$$Register, $op2$$Register);
9271     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9272     __ delayed()->nop();
9273   %}
9274   ins_pipe(cmp_br_reg_reg);
9275 %}
9276 
9277 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9278   match(If cmp (CmpN op1 null));
9279   effect(USE labl, KILL icc);
9280 
9281   size(12);
9282   ins_cost(BRANCH_COST);
9283   format %{ "CMP    $op1,0\t! compressed ptr\n\t"
9284             "BP$cmp   $labl" %}
9285   ins_encode %{
9286     Label* L = $labl$$label;
9287     Assembler::Predict predict_taken =
9288       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9289     __ cmp($op1$$Register, G0);
9290     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9291     __ delayed()->nop();
9292   %}
9293   ins_pipe(cmp_br_reg_reg);
9294 %}
9295 
9296 // Loop back branch
9297 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9298   match(CountedLoopEnd cmp (CmpI op1 op2));
9299   effect(USE labl, KILL icc);
9300 
9301   size(12);
9302   ins_cost(BRANCH_COST);
9303   format %{ "CMP    $op1,$op2\t! int\n\t"
9304             "BP$cmp   $labl\t! Loop end" %}
9305   ins_encode %{
9306     Label* L = $labl$$label;
9307     Assembler::Predict predict_taken =
9308       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9309     __ cmp($op1$$Register, $op2$$Register);
9310     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9311     __ delayed()->nop();
9312   %}
9313   ins_pipe(cmp_br_reg_reg);
9314 %}
9315 
9316 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9317   match(CountedLoopEnd cmp (CmpI op1 op2));
9318   effect(USE labl, KILL icc);
9319 
9320   size(12);
9321   ins_cost(BRANCH_COST);
9322   format %{ "CMP    $op1,$op2\t! int\n\t"
9323             "BP$cmp   $labl\t! Loop end" %}
9324   ins_encode %{
9325     Label* L = $labl$$label;
9326     Assembler::Predict predict_taken =
9327       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9328     __ cmp($op1$$Register, $op2$$constant);
9329     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9330     __ delayed()->nop();
9331   %}
9332   ins_pipe(cmp_br_reg_imm);
9333 %}
9334 
9335 // Short compare and branch instructions
9336 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9337   match(If cmp (CmpI op1 op2));
9338   predicate(UseCBCond);
9339   effect(USE labl, KILL icc);
9340 
9341   size(4);
9342   ins_cost(BRANCH_COST);
9343   format %{ "CWB$cmp  $op1,$op2,$labl\t! int" %}
9344   ins_encode %{
9345     Label* L = $labl$$label;
9346     assert(__ use_cbcond(*L), "back to back cbcond");
9347     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9348   %}
9349   ins_short_branch(1);
9350   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9351   ins_pipe(cbcond_reg_reg);
9352 %}
9353 
9354 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9355   match(If cmp (CmpI op1 op2));
9356   predicate(UseCBCond);
9357   effect(USE labl, KILL icc);
9358 
9359   size(4);
9360   ins_cost(BRANCH_COST);
9361   format %{ "CWB$cmp  $op1,$op2,$labl\t! int" %}
9362   ins_encode %{
9363     Label* L = $labl$$label;
9364     assert(__ use_cbcond(*L), "back to back cbcond");
9365     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9366   %}
9367   ins_short_branch(1);
9368   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9369   ins_pipe(cbcond_reg_imm);
9370 %}
9371 
9372 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9373   match(If cmp (CmpU op1 op2));
9374   predicate(UseCBCond);
9375   effect(USE labl, KILL icc);
9376 
9377   size(4);
9378   ins_cost(BRANCH_COST);
9379   format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9380   ins_encode %{
9381     Label* L = $labl$$label;
9382     assert(__ use_cbcond(*L), "back to back cbcond");
9383     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9384   %}
9385   ins_short_branch(1);
9386   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9387   ins_pipe(cbcond_reg_reg);
9388 %}
9389 
9390 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9391   match(If cmp (CmpU op1 op2));
9392   predicate(UseCBCond);
9393   effect(USE labl, KILL icc);
9394 
9395   size(4);
9396   ins_cost(BRANCH_COST);
9397   format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9398   ins_encode %{
9399     Label* L = $labl$$label;
9400     assert(__ use_cbcond(*L), "back to back cbcond");
9401     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9402   %}
9403   ins_short_branch(1);
9404   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9405   ins_pipe(cbcond_reg_imm);
9406 %}
9407 
9408 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9409   match(If cmp (CmpL op1 op2));
9410   predicate(UseCBCond);
9411   effect(USE labl, KILL xcc);
9412 
9413   size(4);
9414   ins_cost(BRANCH_COST);
9415   format %{ "CXB$cmp  $op1,$op2,$labl\t! long" %}
9416   ins_encode %{
9417     Label* L = $labl$$label;
9418     assert(__ use_cbcond(*L), "back to back cbcond");
9419     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9420   %}
9421   ins_short_branch(1);
9422   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9423   ins_pipe(cbcond_reg_reg);
9424 %}
9425 
9426 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9427   match(If cmp (CmpL op1 op2));
9428   predicate(UseCBCond);
9429   effect(USE labl, KILL xcc);
9430 
9431   size(4);
9432   ins_cost(BRANCH_COST);
9433   format %{ "CXB$cmp  $op1,$op2,$labl\t! long" %}
9434   ins_encode %{
9435     Label* L = $labl$$label;
9436     assert(__ use_cbcond(*L), "back to back cbcond");
9437     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9438   %}
9439   ins_short_branch(1);
9440   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9441   ins_pipe(cbcond_reg_imm);
9442 %}
9443 
9444 // Compare Pointers and branch
9445 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9446   match(If cmp (CmpP op1 op2));
9447   predicate(UseCBCond);
9448   effect(USE labl, KILL pcc);
9449 
9450   size(4);
9451   ins_cost(BRANCH_COST);
9452 #ifdef _LP64
9453   format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9454 #else
9455   format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9456 #endif
9457   ins_encode %{
9458     Label* L = $labl$$label;
9459     assert(__ use_cbcond(*L), "back to back cbcond");
9460     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9461   %}
9462   ins_short_branch(1);
9463   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9464   ins_pipe(cbcond_reg_reg);
9465 %}
9466 
9467 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9468   match(If cmp (CmpP op1 null));
9469   predicate(UseCBCond);
9470   effect(USE labl, KILL pcc);
9471 
9472   size(4);
9473   ins_cost(BRANCH_COST);
9474 #ifdef _LP64
9475   format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9476 #else
9477   format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9478 #endif
9479   ins_encode %{
9480     Label* L = $labl$$label;
9481     assert(__ use_cbcond(*L), "back to back cbcond");
9482     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9483   %}
9484   ins_short_branch(1);
9485   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9486   ins_pipe(cbcond_reg_reg);
9487 %}
9488 
9489 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9490   match(If cmp (CmpN op1 op2));
9491   predicate(UseCBCond);
9492   effect(USE labl, KILL icc);
9493 
9494   size(4);
9495   ins_cost(BRANCH_COST);
9496   format %{ "CWB$cmp  $op1,$op2,$labl\t! compressed ptr" %}
9497   ins_encode %{
9498     Label* L = $labl$$label;
9499     assert(__ use_cbcond(*L), "back to back cbcond");
9500     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9501   %}
9502   ins_short_branch(1);
9503   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9504   ins_pipe(cbcond_reg_reg);
9505 %}
9506 
9507 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9508   match(If cmp (CmpN op1 null));
9509   predicate(UseCBCond);
9510   effect(USE labl, KILL icc);
9511 
9512   size(4);
9513   ins_cost(BRANCH_COST);
9514   format %{ "CWB$cmp  $op1,0,$labl\t! compressed ptr" %}
9515   ins_encode %{
9516     Label* L = $labl$$label;
9517     assert(__ use_cbcond(*L), "back to back cbcond");
9518     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9519   %}
9520   ins_short_branch(1);
9521   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9522   ins_pipe(cbcond_reg_reg);
9523 %}
9524 
9525 // Loop back branch
9526 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9527   match(CountedLoopEnd cmp (CmpI op1 op2));
9528   predicate(UseCBCond);
9529   effect(USE labl, KILL icc);
9530 
9531   size(4);
9532   ins_cost(BRANCH_COST);
9533   format %{ "CWB$cmp  $op1,$op2,$labl\t! Loop end" %}
9534   ins_encode %{
9535     Label* L = $labl$$label;
9536     assert(__ use_cbcond(*L), "back to back cbcond");
9537     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9538   %}
9539   ins_short_branch(1);
9540   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9541   ins_pipe(cbcond_reg_reg);
9542 %}
9543 
9544 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9545   match(CountedLoopEnd cmp (CmpI op1 op2));
9546   predicate(UseCBCond);
9547   effect(USE labl, KILL icc);
9548 
9549   size(4);
9550   ins_cost(BRANCH_COST);
9551   format %{ "CWB$cmp  $op1,$op2,$labl\t! Loop end" %}
9552   ins_encode %{
9553     Label* L = $labl$$label;
9554     assert(__ use_cbcond(*L), "back to back cbcond");
9555     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9556   %}
9557   ins_short_branch(1);
9558   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9559   ins_pipe(cbcond_reg_imm);
9560 %}
9561 
9562 // Branch-on-register tests all 64 bits.  We assume that values
9563 // in 64-bit registers always remains zero or sign extended
9564 // unless our code munges the high bits.  Interrupts can chop
9565 // the high order bits to zero or sign at any time.
9566 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9567   match(If cmp (CmpI op1 zero));
9568   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9569   effect(USE labl);
9570 
9571   size(8);
9572   ins_cost(BRANCH_COST);
9573   format %{ "BR$cmp   $op1,$labl" %}
9574   ins_encode( enc_bpr( labl, cmp, op1 ) );
9575   ins_avoid_back_to_back(AVOID_BEFORE);
9576   ins_pipe(br_reg);
9577 %}
9578 
9579 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9580   match(If cmp (CmpP op1 null));
9581   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9582   effect(USE labl);
9583 
9584   size(8);
9585   ins_cost(BRANCH_COST);
9586   format %{ "BR$cmp   $op1,$labl" %}
9587   ins_encode( enc_bpr( labl, cmp, op1 ) );
9588   ins_avoid_back_to_back(AVOID_BEFORE);
9589   ins_pipe(br_reg);
9590 %}
9591 
9592 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9593   match(If cmp (CmpL op1 zero));
9594   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9595   effect(USE labl);
9596 
9597   size(8);
9598   ins_cost(BRANCH_COST);
9599   format %{ "BR$cmp   $op1,$labl" %}
9600   ins_encode( enc_bpr( labl, cmp, op1 ) );
9601   ins_avoid_back_to_back(AVOID_BEFORE);
9602   ins_pipe(br_reg);
9603 %}
9604 
9605 
9606 // ============================================================================
9607 // Long Compare
9608 //
9609 // Currently we hold longs in 2 registers.  Comparing such values efficiently
9610 // is tricky.  The flavor of compare used depends on whether we are testing
9611 // for LT, LE, or EQ.  For a simple LT test we can check just the sign bit.
9612 // The GE test is the negated LT test.  The LE test can be had by commuting
9613 // the operands (yielding a GE test) and then negating; negate again for the
9614 // GT test.  The EQ test is done by ORcc'ing the high and low halves, and the
9615 // NE test is negated from that.
9616 
9617 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9618 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)).  Note the
9619 // difference between 'Y' and '0L'.  The tree-matches for the CmpI sections
9620 // are collapsed internally in the ADLC's dfa-gen code.  The match for
9621 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9622 // foo match ends up with the wrong leaf.  One fix is to not match both
9623 // reg-reg and reg-zero forms of long-compare.  This is unfortunate because
9624 // both forms beat the trinary form of long-compare and both are very useful
9625 // on Intel which has so few registers.
9626 
9627 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9628   match(If cmp xcc);
9629   effect(USE labl);
9630 
9631   size(8);
9632   ins_cost(BRANCH_COST);
9633   format %{ "BP$cmp   $xcc,$labl" %}
9634   ins_encode %{
9635     Label* L = $labl$$label;
9636     Assembler::Predict predict_taken =
9637       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9638 
9639     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9640     __ delayed()->nop();
9641   %}
9642   ins_avoid_back_to_back(AVOID_BEFORE);
9643   ins_pipe(br_cc);
9644 %}
9645 
9646 // Manifest a CmpL3 result in an integer register.  Very painful.
9647 // This is the test to avoid.
9648 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9649   match(Set dst (CmpL3 src1 src2) );
9650   effect( KILL ccr );
9651   ins_cost(6*DEFAULT_COST);
9652   size(24);
9653   format %{ "CMP    $src1,$src2\t\t! long\n"
9654           "\tBLT,a,pn done\n"
9655           "\tMOV    -1,$dst\t! delay slot\n"
9656           "\tBGT,a,pn done\n"
9657           "\tMOV    1,$dst\t! delay slot\n"
9658           "\tCLR    $dst\n"
9659     "done:"     %}
9660   ins_encode( cmpl_flag(src1,src2,dst) );
9661   ins_pipe(cmpL_reg);
9662 %}
9663 
9664 // Conditional move
9665 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9666   match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9667   ins_cost(150);
9668   format %{ "MOV$cmp  $xcc,$src,$dst\t! long" %}
9669   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9670   ins_pipe(ialu_reg);
9671 %}
9672 
9673 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9674   match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9675   ins_cost(140);
9676   format %{ "MOV$cmp  $xcc,$src,$dst\t! long" %}
9677   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9678   ins_pipe(ialu_imm);
9679 %}
9680 
9681 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9682   match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9683   ins_cost(150);
9684   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9685   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9686   ins_pipe(ialu_reg);
9687 %}
9688 
9689 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9690   match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9691   ins_cost(140);
9692   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9693   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9694   ins_pipe(ialu_imm);
9695 %}
9696 
9697 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9698   match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9699   ins_cost(150);
9700   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9701   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9702   ins_pipe(ialu_reg);
9703 %}
9704 
9705 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9706   match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9707   ins_cost(150);
9708   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9709   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9710   ins_pipe(ialu_reg);
9711 %}
9712 
9713 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9714   match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9715   ins_cost(140);
9716   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9717   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9718   ins_pipe(ialu_imm);
9719 %}
9720 
9721 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9722   match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9723   ins_cost(150);
9724   opcode(0x101);
9725   format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9726   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9727   ins_pipe(int_conditional_float_move);
9728 %}
9729 
9730 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9731   match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9732   ins_cost(150);
9733   opcode(0x102);
9734   format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9735   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9736   ins_pipe(int_conditional_float_move);
9737 %}
9738 
9739 // ============================================================================
9740 // Safepoint Instruction
9741 instruct safePoint_poll(iRegP poll) %{
9742   match(SafePoint poll);
9743   effect(USE poll);
9744 
9745   size(4);
9746 #ifdef _LP64
9747   format %{ "LDX    [$poll],R_G0\t! Safepoint: poll for GC" %}
9748 #else
9749   format %{ "LDUW   [$poll],R_G0\t! Safepoint: poll for GC" %}
9750 #endif
9751   ins_encode %{
9752     __ relocate(relocInfo::poll_type);
9753     __ ld_ptr($poll$$Register, 0, G0);
9754   %}
9755   ins_pipe(loadPollP);
9756 %}
9757 
9758 // ============================================================================
9759 // Call Instructions
9760 // Call Java Static Instruction
9761 instruct CallStaticJavaDirect( method meth ) %{
9762   match(CallStaticJava);
9763   predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9764   effect(USE meth);
9765 
9766   size(8);
9767   ins_cost(CALL_COST);
9768   format %{ "CALL,static  ; NOP ==> " %}
9769   ins_encode( Java_Static_Call( meth ), call_epilog );
9770   ins_avoid_back_to_back(AVOID_BEFORE);
9771   ins_pipe(simple_call);
9772 %}
9773 
9774 // Call Java Static Instruction (method handle version)
9775 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9776   match(CallStaticJava);
9777   predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9778   effect(USE meth, KILL l7_mh_SP_save);
9779 
9780   size(16);
9781   ins_cost(CALL_COST);
9782   format %{ "CALL,static/MethodHandle" %}
9783   ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9784   ins_pipe(simple_call);
9785 %}
9786 
9787 // Call Java Dynamic Instruction
9788 instruct CallDynamicJavaDirect( method meth ) %{
9789   match(CallDynamicJava);
9790   effect(USE meth);
9791 
9792   ins_cost(CALL_COST);
9793   format %{ "SET    (empty),R_G5\n\t"
9794             "CALL,dynamic  ; NOP ==> " %}
9795   ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9796   ins_pipe(call);
9797 %}
9798 
9799 // Call Runtime Instruction
9800 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9801   match(CallRuntime);
9802   effect(USE meth, KILL l7);
9803   ins_cost(CALL_COST);
9804   format %{ "CALL,runtime" %}
9805   ins_encode( Java_To_Runtime( meth ),
9806               call_epilog, adjust_long_from_native_call );
9807   ins_avoid_back_to_back(AVOID_BEFORE);
9808   ins_pipe(simple_call);
9809 %}
9810 
9811 // Call runtime without safepoint - same as CallRuntime
9812 instruct CallLeafDirect(method meth, l7RegP l7) %{
9813   match(CallLeaf);
9814   effect(USE meth, KILL l7);
9815   ins_cost(CALL_COST);
9816   format %{ "CALL,runtime leaf" %}
9817   ins_encode( Java_To_Runtime( meth ),
9818               call_epilog,
9819               adjust_long_from_native_call );
9820   ins_avoid_back_to_back(AVOID_BEFORE);
9821   ins_pipe(simple_call);
9822 %}
9823 
9824 // Call runtime without safepoint - same as CallLeaf
9825 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9826   match(CallLeafNoFP);
9827   effect(USE meth, KILL l7);
9828   ins_cost(CALL_COST);
9829   format %{ "CALL,runtime leaf nofp" %}
9830   ins_encode( Java_To_Runtime( meth ),
9831               call_epilog,
9832               adjust_long_from_native_call );
9833   ins_avoid_back_to_back(AVOID_BEFORE);
9834   ins_pipe(simple_call);
9835 %}
9836 
9837 // Tail Call; Jump from runtime stub to Java code.
9838 // Also known as an 'interprocedural jump'.
9839 // Target of jump will eventually return to caller.
9840 // TailJump below removes the return address.
9841 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9842   match(TailCall jump_target method_oop );
9843 
9844   ins_cost(CALL_COST);
9845   format %{ "Jmp     $jump_target  ; NOP \t! $method_oop holds method oop" %}
9846   ins_encode(form_jmpl(jump_target));
9847   ins_avoid_back_to_back(AVOID_BEFORE);
9848   ins_pipe(tail_call);
9849 %}
9850 
9851 
9852 // Return Instruction
9853 instruct Ret() %{
9854   match(Return);
9855 
9856   // The epilogue node did the ret already.
9857   size(0);
9858   format %{ "! return" %}
9859   ins_encode();
9860   ins_pipe(empty);
9861 %}
9862 
9863 
9864 // Tail Jump; remove the return address; jump to target.
9865 // TailCall above leaves the return address around.
9866 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9867 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9868 // "restore" before this instruction (in Epilogue), we need to materialize it
9869 // in %i0.
9870 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9871   match( TailJump jump_target ex_oop );
9872   ins_cost(CALL_COST);
9873   format %{ "! discard R_O7\n\t"
9874             "Jmp     $jump_target  ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9875   ins_encode(form_jmpl_set_exception_pc(jump_target));
9876   // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9877   // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9878   // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9879   ins_avoid_back_to_back(AVOID_BEFORE);
9880   ins_pipe(tail_call);
9881 %}
9882 
9883 // Create exception oop: created by stack-crawling runtime code.
9884 // Created exception is now available to this handler, and is setup
9885 // just prior to jumping to this handler.  No code emitted.
9886 instruct CreateException( o0RegP ex_oop )
9887 %{
9888   match(Set ex_oop (CreateEx));
9889   ins_cost(0);
9890 
9891   size(0);
9892   // use the following format syntax
9893   format %{ "! exception oop is in R_O0; no code emitted" %}
9894   ins_encode();
9895   ins_pipe(empty);
9896 %}
9897 
9898 
9899 // Rethrow exception:
9900 // The exception oop will come in the first argument position.
9901 // Then JUMP (not call) to the rethrow stub code.
9902 instruct RethrowException()
9903 %{
9904   match(Rethrow);
9905   ins_cost(CALL_COST);
9906 
9907   // use the following format syntax
9908   format %{ "Jmp    rethrow_stub" %}
9909   ins_encode(enc_rethrow);
9910   ins_avoid_back_to_back(AVOID_BEFORE);
9911   ins_pipe(tail_call);
9912 %}
9913 
9914 
9915 // Die now
9916 instruct ShouldNotReachHere( )
9917 %{
9918   match(Halt);
9919   ins_cost(CALL_COST);
9920 
9921   size(4);
9922   // Use the following format syntax
9923   format %{ "ILLTRAP   ; ShouldNotReachHere" %}
9924   ins_encode( form2_illtrap() );
9925   ins_pipe(tail_call);
9926 %}
9927 
9928 // ============================================================================
9929 // The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary superklass
9930 // array for an instance of the superklass.  Set a hidden internal cache on a
9931 // hit (cache is checked with exposed code in gen_subtype_check()).  Return
9932 // not zero for a miss or zero for a hit.  The encoding ALSO sets flags.
9933 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9934   match(Set index (PartialSubtypeCheck sub super));
9935   effect( KILL pcc, KILL o7 );
9936   ins_cost(DEFAULT_COST*10);
9937   format %{ "CALL   PartialSubtypeCheck\n\tNOP" %}
9938   ins_encode( enc_PartialSubtypeCheck() );
9939   ins_avoid_back_to_back(AVOID_BEFORE);
9940   ins_pipe(partial_subtype_check_pipe);
9941 %}
9942 
9943 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9944   match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9945   effect( KILL idx, KILL o7 );
9946   ins_cost(DEFAULT_COST*10);
9947   format %{ "CALL   PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9948   ins_encode( enc_PartialSubtypeCheck() );
9949   ins_avoid_back_to_back(AVOID_BEFORE);
9950   ins_pipe(partial_subtype_check_pipe);
9951 %}
9952 
9953 
9954 // ============================================================================
9955 // inlined locking and unlocking
9956 
9957 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9958   match(Set pcc (FastLock object box));
9959 
9960   effect(TEMP scratch2, USE_KILL box, KILL scratch);
9961   ins_cost(100);
9962 
9963   format %{ "FASTLOCK  $object,$box\t! kills $box,$scratch,$scratch2" %}
9964   ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9965   ins_pipe(long_memory_op);
9966 %}
9967 
9968 
9969 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9970   match(Set pcc (FastUnlock object box));
9971   effect(TEMP scratch2, USE_KILL box, KILL scratch);
9972   ins_cost(100);
9973 
9974   format %{ "FASTUNLOCK  $object,$box\t! kills $box,$scratch,$scratch2" %}
9975   ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9976   ins_pipe(long_memory_op);
9977 %}
9978 
9979 // The encodings are generic.
9980 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9981   predicate(!use_block_zeroing(n->in(2)) );
9982   match(Set dummy (ClearArray cnt base));
9983   effect(TEMP temp, KILL ccr);
9984   ins_cost(300);
9985   format %{ "MOV    $cnt,$temp\n"
9986     "loop:   SUBcc  $temp,8,$temp\t! Count down a dword of bytes\n"
9987     "        BRge   loop\t\t! Clearing loop\n"
9988     "        STX    G0,[$base+$temp]\t! delay slot" %}
9989 
9990   ins_encode %{
9991     // Compiler ensures base is doubleword aligned and cnt is count of doublewords
9992     Register nof_bytes_arg    = $cnt$$Register;
9993     Register nof_bytes_tmp    = $temp$$Register;
9994     Register base_pointer_arg = $base$$Register;
9995 
9996     Label loop;
9997     __ mov(nof_bytes_arg, nof_bytes_tmp);
9998 
9999     // Loop and clear, walking backwards through the array.
10000     // nof_bytes_tmp (if >0) is always the number of bytes to zero
10001     __ bind(loop);
10002     __ deccc(nof_bytes_tmp, 8);
10003     __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10004     __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10005     // %%%% this mini-loop must not cross a cache boundary!
10006   %}
10007   ins_pipe(long_memory_op);
10008 %}
10009 
10010 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10011   predicate(use_block_zeroing(n->in(2)));
10012   match(Set dummy (ClearArray cnt base));
10013   effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10014   ins_cost(300);
10015   format %{ "CLEAR  [$base, $cnt]\t! ClearArray" %}
10016 
10017   ins_encode %{
10018 
10019     assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10020     Register to    = $base$$Register;
10021     Register count = $cnt$$Register;
10022 
10023     Label Ldone;
10024     __ nop(); // Separate short branches
10025     // Use BIS for zeroing (temp is not used).
10026     __ bis_zeroing(to, count, G0, Ldone);
10027     __ bind(Ldone);
10028 
10029   %}
10030   ins_pipe(long_memory_op);
10031 %}
10032 
10033 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10034   predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10035   match(Set dummy (ClearArray cnt base));
10036   effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10037   ins_cost(300);
10038   format %{ "CLEAR  [$base, $cnt]\t! ClearArray" %}
10039 
10040   ins_encode %{
10041 
10042     assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10043     Register to    = $base$$Register;
10044     Register count = $cnt$$Register;
10045     Register temp  = $tmp$$Register;
10046 
10047     Label Ldone;
10048     __ nop(); // Separate short branches
10049     // Use BIS for zeroing
10050     __ bis_zeroing(to, count, temp, Ldone);
10051     __ bind(Ldone);
10052 
10053   %}
10054   ins_pipe(long_memory_op);
10055 %}
10056 
10057 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10058                          o7RegI tmp, flagsReg ccr) %{
10059   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10060   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10061   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10062   ins_cost(300);
10063   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp" %}
10064   ins_encode %{
10065     __ string_compare($str1$$Register, $str2$$Register,
10066                       $cnt1$$Register, $cnt2$$Register,
10067                       $tmp$$Register, $tmp$$Register,
10068                       $result$$Register, StrIntrinsicNode::LL);
10069   %}
10070   ins_pipe(long_memory_op);
10071 %}
10072 
10073 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10074                          o7RegI tmp, flagsReg ccr) %{
10075   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10076   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10077   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10078   ins_cost(300);
10079   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp" %}
10080   ins_encode %{
10081     __ string_compare($str1$$Register, $str2$$Register,
10082                       $cnt1$$Register, $cnt2$$Register,
10083                       $tmp$$Register, $tmp$$Register,
10084                       $result$$Register, StrIntrinsicNode::UU);
10085   %}
10086   ins_pipe(long_memory_op);
10087 %}
10088 
10089 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10090                           o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10091   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10092   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10093   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10094   ins_cost(300);
10095   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1,$tmp2" %}
10096   ins_encode %{
10097     __ string_compare($str1$$Register, $str2$$Register,
10098                       $cnt1$$Register, $cnt2$$Register,
10099                       $tmp1$$Register, $tmp2$$Register,
10100                       $result$$Register, StrIntrinsicNode::LU);
10101   %}
10102   ins_pipe(long_memory_op);
10103 %}
10104 
10105 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10106                           o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10107   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10108   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10109   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10110   ins_cost(300);
10111   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1,$tmp2" %}
10112   ins_encode %{
10113     __ string_compare($str2$$Register, $str1$$Register,
10114                       $cnt2$$Register, $cnt1$$Register,
10115                       $tmp1$$Register, $tmp2$$Register,
10116                       $result$$Register, StrIntrinsicNode::UL);
10117   %}
10118   ins_pipe(long_memory_op);
10119 %}
10120 
10121 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10122                         o7RegI tmp, flagsReg ccr) %{
10123   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10124   match(Set result (StrEquals (Binary str1 str2) cnt));
10125   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10126   ins_cost(300);
10127   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result   // KILL $tmp" %}
10128   ins_encode %{
10129     __ array_equals(false, $str1$$Register, $str2$$Register,
10130                     $cnt$$Register, $tmp$$Register,
10131                     $result$$Register, true /* byte */);
10132   %}
10133   ins_pipe(long_memory_op);
10134 %}
10135 
10136 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10137                         o7RegI tmp, flagsReg ccr) %{
10138   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10139   match(Set result (StrEquals (Binary str1 str2) cnt));
10140   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10141   ins_cost(300);
10142   format %{ "String Equals char[]  $str1,$str2,$cnt -> $result   // KILL $tmp" %}
10143   ins_encode %{
10144     __ array_equals(false, $str1$$Register, $str2$$Register,
10145                     $cnt$$Register, $tmp$$Register,
10146                     $result$$Register, false /* byte */);
10147   %}
10148   ins_pipe(long_memory_op);
10149 %}
10150 
10151 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10152                        o7RegI tmp2, flagsReg ccr) %{
10153   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10154   match(Set result (AryEq ary1 ary2));
10155   effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10156   ins_cost(300);
10157   format %{ "Array Equals $ary1,$ary2 -> $result   // KILL $tmp1,$tmp2" %}
10158   ins_encode %{
10159     __ array_equals(true, $ary1$$Register, $ary2$$Register,
10160                     $tmp1$$Register, $tmp2$$Register,
10161                     $result$$Register, true /* byte */);
10162   %}
10163   ins_pipe(long_memory_op);
10164 %}
10165 
10166 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10167                        o7RegI tmp2, flagsReg ccr) %{
10168   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10169   match(Set result (AryEq ary1 ary2));
10170   effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10171   ins_cost(300);
10172   format %{ "Array Equals $ary1,$ary2 -> $result   // KILL $tmp1,$tmp2" %}
10173   ins_encode %{
10174     __ array_equals(true, $ary1$$Register, $ary2$$Register,
10175                     $tmp1$$Register, $tmp2$$Register,
10176                     $result$$Register, false /* byte */);
10177   %}
10178   ins_pipe(long_memory_op);
10179 %}
10180 
10181 instruct has_negatives(o0RegP pAryR, g3RegI iSizeR, notemp_iRegI resultR,
10182                        iRegL tmp1L, iRegL tmp2L, iRegL tmp3L, iRegL tmp4L,
10183                        flagsReg ccr) 
10184 %{
10185   match(Set resultR (HasNegatives pAryR iSizeR));
10186   effect(TEMP resultR, TEMP tmp1L, TEMP tmp2L, TEMP tmp3L, TEMP tmp4L, USE pAryR, USE iSizeR, KILL ccr);
10187   format %{ "has negatives byte[] $pAryR,$iSizeR -> $resultR // KILL $tmp1L,$tmp2L,$tmp3L,$tmp4L" %}
10188   ins_encode %{
10189     __ has_negatives($pAryR$$Register, $iSizeR$$Register, 
10190                      $resultR$$Register,
10191                      $tmp1L$$Register, $tmp2L$$Register, 
10192                      $tmp3L$$Register, $tmp4L$$Register);
10193   %}
10194   ins_pipe(long_memory_op);
10195 %}
10196 
10197 // char[] to byte[] compression
10198 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{
10199   predicate(UseVIS < 3);
10200   match(Set result (StrCompressedCopy src (Binary dst len)));
10201   effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10202   ins_cost(300);
10203   format %{ "String Compress $src,$dst,$len -> $result    // KILL $tmp" %}
10204   ins_encode %{
10205     Label Ldone;
10206     __ signx($len$$Register);
10207     __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn);
10208     __ delayed()->mov($len$$Register, $result$$Register); // copy count
10209     __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone);
10210     __ bind(Ldone);
10211   %}
10212   ins_pipe(long_memory_op);
10213 %}
10214 
10215 // fast char[] to byte[] compression using VIS instructions
10216 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result,
10217                               iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4,
10218                               regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{
10219   predicate(UseVIS >= 3);
10220   match(Set result (StrCompressedCopy src (Binary dst len)));
10221   effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10222   ins_cost(300);
10223   format %{ "String Compress Fast $src,$dst,$len -> $result    // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %}
10224   ins_encode %{
10225     Label Ldone;
10226     __ signx($len$$Register);
10227     __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register,
10228                           $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10229                           $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone);
10230     __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10231     __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone);
10232     __ bind(Ldone);
10233   %}
10234   ins_pipe(long_memory_op);
10235 %}
10236 
10237 // byte[] to char[] inflation
10238 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10239                         iRegL tmp, flagsReg ccr) %{
10240   match(Set dummy (StrInflatedCopy src (Binary dst len)));
10241   effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10242   ins_cost(300);
10243   format %{ "String Inflate $src,$dst,$len    // KILL $tmp" %}
10244   ins_encode %{
10245     Label Ldone;
10246     __ signx($len$$Register);
10247     __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10248     __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10249     __ bind(Ldone);
10250   %}
10251   ins_pipe(long_memory_op);
10252 %}
10253 
10254 // fast byte[] to char[] inflation using VIS instructions
10255 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10256                              iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{
10257   predicate(UseVIS >= 3);
10258   match(Set dummy (StrInflatedCopy src (Binary dst len)));
10259   effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10260   ins_cost(300);
10261   format %{ "String Inflate Fast $src,$dst,$len    // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %}
10262   ins_encode %{
10263     Label Ldone;
10264     __ signx($len$$Register);
10265     __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register,
10266                          $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone);
10267     __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10268     __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10269     __ bind(Ldone);
10270   %}
10271   ins_pipe(long_memory_op);
10272 %}
10273 
10274 
10275 //---------- Zeros Count Instructions ------------------------------------------
10276 
10277 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10278   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10279   match(Set dst (CountLeadingZerosI src));
10280   effect(TEMP dst, TEMP tmp, KILL cr);
10281 
10282   // x |= (x >> 1);
10283   // x |= (x >> 2);
10284   // x |= (x >> 4);
10285   // x |= (x >> 8);
10286   // x |= (x >> 16);
10287   // return (WORDBITS - popc(x));
10288   format %{ "SRL     $src,1,$tmp\t! count leading zeros (int)\n\t"
10289             "SRL     $src,0,$dst\t! 32-bit zero extend\n\t"
10290             "OR      $dst,$tmp,$dst\n\t"
10291             "SRL     $dst,2,$tmp\n\t"
10292             "OR      $dst,$tmp,$dst\n\t"
10293             "SRL     $dst,4,$tmp\n\t"
10294             "OR      $dst,$tmp,$dst\n\t"
10295             "SRL     $dst,8,$tmp\n\t"
10296             "OR      $dst,$tmp,$dst\n\t"
10297             "SRL     $dst,16,$tmp\n\t"
10298             "OR      $dst,$tmp,$dst\n\t"
10299             "POPC    $dst,$dst\n\t"
10300             "MOV     32,$tmp\n\t"
10301             "SUB     $tmp,$dst,$dst" %}
10302   ins_encode %{
10303     Register Rdst = $dst$$Register;
10304     Register Rsrc = $src$$Register;
10305     Register Rtmp = $tmp$$Register;
10306     __ srl(Rsrc, 1,    Rtmp);
10307     __ srl(Rsrc, 0,    Rdst);
10308     __ or3(Rdst, Rtmp, Rdst);
10309     __ srl(Rdst, 2,    Rtmp);
10310     __ or3(Rdst, Rtmp, Rdst);
10311     __ srl(Rdst, 4,    Rtmp);
10312     __ or3(Rdst, Rtmp, Rdst);
10313     __ srl(Rdst, 8,    Rtmp);
10314     __ or3(Rdst, Rtmp, Rdst);
10315     __ srl(Rdst, 16,   Rtmp);
10316     __ or3(Rdst, Rtmp, Rdst);
10317     __ popc(Rdst, Rdst);
10318     __ mov(BitsPerInt, Rtmp);
10319     __ sub(Rtmp, Rdst, Rdst);
10320   %}
10321   ins_pipe(ialu_reg);
10322 %}
10323 
10324 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10325   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10326   match(Set dst (CountLeadingZerosL src));
10327   effect(TEMP dst, TEMP tmp, KILL cr);
10328 
10329   // x |= (x >> 1);
10330   // x |= (x >> 2);
10331   // x |= (x >> 4);
10332   // x |= (x >> 8);
10333   // x |= (x >> 16);
10334   // x |= (x >> 32);
10335   // return (WORDBITS - popc(x));
10336   format %{ "SRLX    $src,1,$tmp\t! count leading zeros (long)\n\t"
10337             "OR      $src,$tmp,$dst\n\t"
10338             "SRLX    $dst,2,$tmp\n\t"
10339             "OR      $dst,$tmp,$dst\n\t"
10340             "SRLX    $dst,4,$tmp\n\t"
10341             "OR      $dst,$tmp,$dst\n\t"
10342             "SRLX    $dst,8,$tmp\n\t"
10343             "OR      $dst,$tmp,$dst\n\t"
10344             "SRLX    $dst,16,$tmp\n\t"
10345             "OR      $dst,$tmp,$dst\n\t"
10346             "SRLX    $dst,32,$tmp\n\t"
10347             "OR      $dst,$tmp,$dst\n\t"
10348             "POPC    $dst,$dst\n\t"
10349             "MOV     64,$tmp\n\t"
10350             "SUB     $tmp,$dst,$dst" %}
10351   ins_encode %{
10352     Register Rdst = $dst$$Register;
10353     Register Rsrc = $src$$Register;
10354     Register Rtmp = $tmp$$Register;
10355     __ srlx(Rsrc, 1,    Rtmp);
10356     __ or3( Rsrc, Rtmp, Rdst);
10357     __ srlx(Rdst, 2,    Rtmp);
10358     __ or3( Rdst, Rtmp, Rdst);
10359     __ srlx(Rdst, 4,    Rtmp);
10360     __ or3( Rdst, Rtmp, Rdst);
10361     __ srlx(Rdst, 8,    Rtmp);
10362     __ or3( Rdst, Rtmp, Rdst);
10363     __ srlx(Rdst, 16,   Rtmp);
10364     __ or3( Rdst, Rtmp, Rdst);
10365     __ srlx(Rdst, 32,   Rtmp);
10366     __ or3( Rdst, Rtmp, Rdst);
10367     __ popc(Rdst, Rdst);
10368     __ mov(BitsPerLong, Rtmp);
10369     __ sub(Rtmp, Rdst, Rdst);
10370   %}
10371   ins_pipe(ialu_reg);
10372 %}
10373 
10374 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10375   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10376   match(Set dst (CountTrailingZerosI src));
10377   effect(TEMP dst, KILL cr);
10378 
10379   // return popc(~x & (x - 1));
10380   format %{ "SUB     $src,1,$dst\t! count trailing zeros (int)\n\t"
10381             "ANDN    $dst,$src,$dst\n\t"
10382             "SRL     $dst,R_G0,$dst\n\t"
10383             "POPC    $dst,$dst" %}
10384   ins_encode %{
10385     Register Rdst = $dst$$Register;
10386     Register Rsrc = $src$$Register;
10387     __ sub(Rsrc, 1, Rdst);
10388     __ andn(Rdst, Rsrc, Rdst);
10389     __ srl(Rdst, G0, Rdst);
10390     __ popc(Rdst, Rdst);
10391   %}
10392   ins_pipe(ialu_reg);
10393 %}
10394 
10395 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10396   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10397   match(Set dst (CountTrailingZerosL src));
10398   effect(TEMP dst, KILL cr);
10399 
10400   // return popc(~x & (x - 1));
10401   format %{ "SUB     $src,1,$dst\t! count trailing zeros (long)\n\t"
10402             "ANDN    $dst,$src,$dst\n\t"
10403             "POPC    $dst,$dst" %}
10404   ins_encode %{
10405     Register Rdst = $dst$$Register;
10406     Register Rsrc = $src$$Register;
10407     __ sub(Rsrc, 1, Rdst);
10408     __ andn(Rdst, Rsrc, Rdst);
10409     __ popc(Rdst, Rdst);
10410   %}
10411   ins_pipe(ialu_reg);
10412 %}
10413 
10414 
10415 //---------- Population Count Instructions -------------------------------------
10416 
10417 instruct popCountI(iRegIsafe dst, iRegI src) %{
10418   predicate(UsePopCountInstruction);
10419   match(Set dst (PopCountI src));
10420 
10421   format %{ "SRL    $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10422             "POPC   $dst, $dst" %}
10423   ins_encode %{
10424     __ srl($src$$Register, G0, $dst$$Register);
10425     __ popc($dst$$Register, $dst$$Register);
10426   %}
10427   ins_pipe(ialu_reg);
10428 %}
10429 
10430 // Note: Long.bitCount(long) returns an int.
10431 instruct popCountL(iRegIsafe dst, iRegL src) %{
10432   predicate(UsePopCountInstruction);
10433   match(Set dst (PopCountL src));
10434 
10435   format %{ "POPC   $src, $dst" %}
10436   ins_encode %{
10437     __ popc($src$$Register, $dst$$Register);
10438   %}
10439   ins_pipe(ialu_reg);
10440 %}
10441 
10442 
10443 // ============================================================================
10444 //------------Bytes reverse--------------------------------------------------
10445 
10446 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10447   match(Set dst (ReverseBytesI src));
10448 
10449   // Op cost is artificially doubled to make sure that load or store
10450   // instructions are preferred over this one which requires a spill
10451   // onto a stack slot.
10452   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10453   format %{ "LDUWA  $src, $dst\t!asi=primary_little" %}
10454 
10455   ins_encode %{
10456     __ set($src$$disp + STACK_BIAS, O7);
10457     __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10458   %}
10459   ins_pipe( iload_mem );
10460 %}
10461 
10462 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10463   match(Set dst (ReverseBytesL src));
10464 
10465   // Op cost is artificially doubled to make sure that load or store
10466   // instructions are preferred over this one which requires a spill
10467   // onto a stack slot.
10468   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10469   format %{ "LDXA   $src, $dst\t!asi=primary_little" %}
10470 
10471   ins_encode %{
10472     __ set($src$$disp + STACK_BIAS, O7);
10473     __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10474   %}
10475   ins_pipe( iload_mem );
10476 %}
10477 
10478 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10479   match(Set dst (ReverseBytesUS src));
10480 
10481   // Op cost is artificially doubled to make sure that load or store
10482   // instructions are preferred over this one which requires a spill
10483   // onto a stack slot.
10484   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10485   format %{ "LDUHA  $src, $dst\t!asi=primary_little\n\t" %}
10486 
10487   ins_encode %{
10488     // the value was spilled as an int so bias the load
10489     __ set($src$$disp + STACK_BIAS + 2, O7);
10490     __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10491   %}
10492   ins_pipe( iload_mem );
10493 %}
10494 
10495 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10496   match(Set dst (ReverseBytesS src));
10497 
10498   // Op cost is artificially doubled to make sure that load or store
10499   // instructions are preferred over this one which requires a spill
10500   // onto a stack slot.
10501   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10502   format %{ "LDSHA  $src, $dst\t!asi=primary_little\n\t" %}
10503 
10504   ins_encode %{
10505     // the value was spilled as an int so bias the load
10506     __ set($src$$disp + STACK_BIAS + 2, O7);
10507     __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10508   %}
10509   ins_pipe( iload_mem );
10510 %}
10511 
10512 // Load Integer reversed byte order
10513 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10514   match(Set dst (ReverseBytesI (LoadI src)));
10515 
10516   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10517   size(4);
10518   format %{ "LDUWA  $src, $dst\t!asi=primary_little" %}
10519 
10520   ins_encode %{
10521     __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10522   %}
10523   ins_pipe(iload_mem);
10524 %}
10525 
10526 // Load Long - aligned and reversed
10527 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10528   match(Set dst (ReverseBytesL (LoadL src)));
10529 
10530   ins_cost(MEMORY_REF_COST);
10531   size(4);
10532   format %{ "LDXA   $src, $dst\t!asi=primary_little" %}
10533 
10534   ins_encode %{
10535     __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10536   %}
10537   ins_pipe(iload_mem);
10538 %}
10539 
10540 // Load unsigned short / char reversed byte order
10541 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10542   match(Set dst (ReverseBytesUS (LoadUS src)));
10543 
10544   ins_cost(MEMORY_REF_COST);
10545   size(4);
10546   format %{ "LDUHA  $src, $dst\t!asi=primary_little" %}
10547 
10548   ins_encode %{
10549     __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10550   %}
10551   ins_pipe(iload_mem);
10552 %}
10553 
10554 // Load short reversed byte order
10555 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10556   match(Set dst (ReverseBytesS (LoadS src)));
10557 
10558   ins_cost(MEMORY_REF_COST);
10559   size(4);
10560   format %{ "LDSHA  $src, $dst\t!asi=primary_little" %}
10561 
10562   ins_encode %{
10563     __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10564   %}
10565   ins_pipe(iload_mem);
10566 %}
10567 
10568 // Store Integer reversed byte order
10569 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10570   match(Set dst (StoreI dst (ReverseBytesI src)));
10571 
10572   ins_cost(MEMORY_REF_COST);
10573   size(4);
10574   format %{ "STWA   $src, $dst\t!asi=primary_little" %}
10575 
10576   ins_encode %{
10577     __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10578   %}
10579   ins_pipe(istore_mem_reg);
10580 %}
10581 
10582 // Store Long reversed byte order
10583 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10584   match(Set dst (StoreL dst (ReverseBytesL src)));
10585 
10586   ins_cost(MEMORY_REF_COST);
10587   size(4);
10588   format %{ "STXA   $src, $dst\t!asi=primary_little" %}
10589 
10590   ins_encode %{
10591     __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10592   %}
10593   ins_pipe(istore_mem_reg);
10594 %}
10595 
10596 // Store unsighed short/char reversed byte order
10597 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10598   match(Set dst (StoreC dst (ReverseBytesUS src)));
10599 
10600   ins_cost(MEMORY_REF_COST);
10601   size(4);
10602   format %{ "STHA   $src, $dst\t!asi=primary_little" %}
10603 
10604   ins_encode %{
10605     __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10606   %}
10607   ins_pipe(istore_mem_reg);
10608 %}
10609 
10610 // Store short reversed byte order
10611 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10612   match(Set dst (StoreC dst (ReverseBytesS src)));
10613 
10614   ins_cost(MEMORY_REF_COST);
10615   size(4);
10616   format %{ "STHA   $src, $dst\t!asi=primary_little" %}
10617 
10618   ins_encode %{
10619     __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10620   %}
10621   ins_pipe(istore_mem_reg);
10622 %}
10623 
10624 // ====================VECTOR INSTRUCTIONS=====================================
10625 
10626 // Load Aligned Packed values into a Double Register
10627 instruct loadV8(regD dst, memory mem) %{
10628   predicate(n->as_LoadVector()->memory_size() == 8);
10629   match(Set dst (LoadVector mem));
10630   ins_cost(MEMORY_REF_COST);
10631   size(4);
10632   format %{ "LDDF   $mem,$dst\t! load vector (8 bytes)" %}
10633   ins_encode %{
10634     __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10635   %}
10636   ins_pipe(floadD_mem);
10637 %}
10638 
10639 // Store Vector in Double register to memory
10640 instruct storeV8(memory mem, regD src) %{
10641   predicate(n->as_StoreVector()->memory_size() == 8);
10642   match(Set mem (StoreVector mem src));
10643   ins_cost(MEMORY_REF_COST);
10644   size(4);
10645   format %{ "STDF   $src,$mem\t! store vector (8 bytes)" %}
10646   ins_encode %{
10647     __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10648   %}
10649   ins_pipe(fstoreD_mem_reg);
10650 %}
10651 
10652 // Store Zero into vector in memory
10653 instruct storeV8B_zero(memory mem, immI0 zero) %{
10654   predicate(n->as_StoreVector()->memory_size() == 8);
10655   match(Set mem (StoreVector mem (ReplicateB zero)));
10656   ins_cost(MEMORY_REF_COST);
10657   size(4);
10658   format %{ "STX    $zero,$mem\t! store zero vector (8 bytes)" %}
10659   ins_encode %{
10660     __ stx(G0, $mem$$Address);
10661   %}
10662   ins_pipe(fstoreD_mem_zero);
10663 %}
10664 
10665 instruct storeV4S_zero(memory mem, immI0 zero) %{
10666   predicate(n->as_StoreVector()->memory_size() == 8);
10667   match(Set mem (StoreVector mem (ReplicateS zero)));
10668   ins_cost(MEMORY_REF_COST);
10669   size(4);
10670   format %{ "STX    $zero,$mem\t! store zero vector (4 shorts)" %}
10671   ins_encode %{
10672     __ stx(G0, $mem$$Address);
10673   %}
10674   ins_pipe(fstoreD_mem_zero);
10675 %}
10676 
10677 instruct storeV2I_zero(memory mem, immI0 zero) %{
10678   predicate(n->as_StoreVector()->memory_size() == 8);
10679   match(Set mem (StoreVector mem (ReplicateI zero)));
10680   ins_cost(MEMORY_REF_COST);
10681   size(4);
10682   format %{ "STX    $zero,$mem\t! store zero vector (2 ints)" %}
10683   ins_encode %{
10684     __ stx(G0, $mem$$Address);
10685   %}
10686   ins_pipe(fstoreD_mem_zero);
10687 %}
10688 
10689 instruct storeV2F_zero(memory mem, immF0 zero) %{
10690   predicate(n->as_StoreVector()->memory_size() == 8);
10691   match(Set mem (StoreVector mem (ReplicateF zero)));
10692   ins_cost(MEMORY_REF_COST);
10693   size(4);
10694   format %{ "STX    $zero,$mem\t! store zero vector (2 floats)" %}
10695   ins_encode %{
10696     __ stx(G0, $mem$$Address);
10697   %}
10698   ins_pipe(fstoreD_mem_zero);
10699 %}
10700 
10701 // Replicate scalar to packed byte values into Double register
10702 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10703   predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10704   match(Set dst (ReplicateB src));
10705   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10706   format %{ "SLLX  $src,56,$tmp\n\t"
10707             "SRLX  $tmp, 8,$tmp2\n\t"
10708             "OR    $tmp,$tmp2,$tmp\n\t"
10709             "SRLX  $tmp,16,$tmp2\n\t"
10710             "OR    $tmp,$tmp2,$tmp\n\t"
10711             "SRLX  $tmp,32,$tmp2\n\t"
10712             "OR    $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10713             "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10714   ins_encode %{
10715     Register Rsrc = $src$$Register;
10716     Register Rtmp = $tmp$$Register;
10717     Register Rtmp2 = $tmp2$$Register;
10718     __ sllx(Rsrc,    56, Rtmp);
10719     __ srlx(Rtmp,     8, Rtmp2);
10720     __ or3 (Rtmp, Rtmp2, Rtmp);
10721     __ srlx(Rtmp,    16, Rtmp2);
10722     __ or3 (Rtmp, Rtmp2, Rtmp);
10723     __ srlx(Rtmp,    32, Rtmp2);
10724     __ or3 (Rtmp, Rtmp2, Rtmp);
10725     __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10726   %}
10727   ins_pipe(ialu_reg);
10728 %}
10729 
10730 // Replicate scalar to packed byte values into Double stack
10731 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10732   predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10733   match(Set dst (ReplicateB src));
10734   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10735   format %{ "SLLX  $src,56,$tmp\n\t"
10736             "SRLX  $tmp, 8,$tmp2\n\t"
10737             "OR    $tmp,$tmp2,$tmp\n\t"
10738             "SRLX  $tmp,16,$tmp2\n\t"
10739             "OR    $tmp,$tmp2,$tmp\n\t"
10740             "SRLX  $tmp,32,$tmp2\n\t"
10741             "OR    $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10742             "STX   $tmp,$dst\t! regL to stkD" %}
10743   ins_encode %{
10744     Register Rsrc = $src$$Register;
10745     Register Rtmp = $tmp$$Register;
10746     Register Rtmp2 = $tmp2$$Register;
10747     __ sllx(Rsrc,    56, Rtmp);
10748     __ srlx(Rtmp,     8, Rtmp2);
10749     __ or3 (Rtmp, Rtmp2, Rtmp);
10750     __ srlx(Rtmp,    16, Rtmp2);
10751     __ or3 (Rtmp, Rtmp2, Rtmp);
10752     __ srlx(Rtmp,    32, Rtmp2);
10753     __ or3 (Rtmp, Rtmp2, Rtmp);
10754     __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10755     __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10756   %}
10757   ins_pipe(ialu_reg);
10758 %}
10759 
10760 // Replicate scalar constant to packed byte values in Double register
10761 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10762   predicate(n->as_Vector()->length() == 8);
10763   match(Set dst (ReplicateB con));
10764   effect(KILL tmp);
10765   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10766   ins_encode %{
10767     // XXX This is a quick fix for 6833573.
10768     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10769     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10770     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10771   %}
10772   ins_pipe(loadConFD);
10773 %}
10774 
10775 // Replicate scalar to packed char/short values into Double register
10776 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10777   predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10778   match(Set dst (ReplicateS src));
10779   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10780   format %{ "SLLX  $src,48,$tmp\n\t"
10781             "SRLX  $tmp,16,$tmp2\n\t"
10782             "OR    $tmp,$tmp2,$tmp\n\t"
10783             "SRLX  $tmp,32,$tmp2\n\t"
10784             "OR    $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10785             "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10786   ins_encode %{
10787     Register Rsrc = $src$$Register;
10788     Register Rtmp = $tmp$$Register;
10789     Register Rtmp2 = $tmp2$$Register;
10790     __ sllx(Rsrc,    48, Rtmp);
10791     __ srlx(Rtmp,    16, Rtmp2);
10792     __ or3 (Rtmp, Rtmp2, Rtmp);
10793     __ srlx(Rtmp,    32, Rtmp2);
10794     __ or3 (Rtmp, Rtmp2, Rtmp);
10795     __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10796   %}
10797   ins_pipe(ialu_reg);
10798 %}
10799 
10800 // Replicate scalar to packed char/short values into Double stack
10801 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10802   predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10803   match(Set dst (ReplicateS src));
10804   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10805   format %{ "SLLX  $src,48,$tmp\n\t"
10806             "SRLX  $tmp,16,$tmp2\n\t"
10807             "OR    $tmp,$tmp2,$tmp\n\t"
10808             "SRLX  $tmp,32,$tmp2\n\t"
10809             "OR    $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10810             "STX   $tmp,$dst\t! regL to stkD" %}
10811   ins_encode %{
10812     Register Rsrc = $src$$Register;
10813     Register Rtmp = $tmp$$Register;
10814     Register Rtmp2 = $tmp2$$Register;
10815     __ sllx(Rsrc,    48, Rtmp);
10816     __ srlx(Rtmp,    16, Rtmp2);
10817     __ or3 (Rtmp, Rtmp2, Rtmp);
10818     __ srlx(Rtmp,    32, Rtmp2);
10819     __ or3 (Rtmp, Rtmp2, Rtmp);
10820     __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10821     __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10822   %}
10823   ins_pipe(ialu_reg);
10824 %}
10825 
10826 // Replicate scalar constant to packed char/short values in Double register
10827 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10828   predicate(n->as_Vector()->length() == 4);
10829   match(Set dst (ReplicateS con));
10830   effect(KILL tmp);
10831   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10832   ins_encode %{
10833     // XXX This is a quick fix for 6833573.
10834     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10835     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10836     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10837   %}
10838   ins_pipe(loadConFD);
10839 %}
10840 
10841 // Replicate scalar to packed int values into Double register
10842 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10843   predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10844   match(Set dst (ReplicateI src));
10845   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10846   format %{ "SLLX  $src,32,$tmp\n\t"
10847             "SRLX  $tmp,32,$tmp2\n\t"
10848             "OR    $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10849             "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10850   ins_encode %{
10851     Register Rsrc = $src$$Register;
10852     Register Rtmp = $tmp$$Register;
10853     Register Rtmp2 = $tmp2$$Register;
10854     __ sllx(Rsrc,    32, Rtmp);
10855     __ srlx(Rtmp,    32, Rtmp2);
10856     __ or3 (Rtmp, Rtmp2, Rtmp);
10857     __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10858   %}
10859   ins_pipe(ialu_reg);
10860 %}
10861 
10862 // Replicate scalar to packed int values into Double stack
10863 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10864   predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10865   match(Set dst (ReplicateI src));
10866   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10867   format %{ "SLLX  $src,32,$tmp\n\t"
10868             "SRLX  $tmp,32,$tmp2\n\t"
10869             "OR    $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10870             "STX   $tmp,$dst\t! regL to stkD" %}
10871   ins_encode %{
10872     Register Rsrc = $src$$Register;
10873     Register Rtmp = $tmp$$Register;
10874     Register Rtmp2 = $tmp2$$Register;
10875     __ sllx(Rsrc,    32, Rtmp);
10876     __ srlx(Rtmp,    32, Rtmp2);
10877     __ or3 (Rtmp, Rtmp2, Rtmp);
10878     __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10879     __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10880   %}
10881   ins_pipe(ialu_reg);
10882 %}
10883 
10884 // Replicate scalar zero constant to packed int values in Double register
10885 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10886   predicate(n->as_Vector()->length() == 2);
10887   match(Set dst (ReplicateI con));
10888   effect(KILL tmp);
10889   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10890   ins_encode %{
10891     // XXX This is a quick fix for 6833573.
10892     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10893     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10894     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10895   %}
10896   ins_pipe(loadConFD);
10897 %}
10898 
10899 // Replicate scalar to packed float values into Double stack
10900 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10901   predicate(n->as_Vector()->length() == 2);
10902   match(Set dst (ReplicateF src));
10903   ins_cost(MEMORY_REF_COST*2);
10904   format %{ "STF    $src,$dst.hi\t! packed2F\n\t"
10905             "STF    $src,$dst.lo" %}
10906   opcode(Assembler::stf_op3);
10907   ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10908   ins_pipe(fstoreF_stk_reg);
10909 %}
10910 
10911 // Replicate scalar zero constant to packed float values in Double register
10912 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10913   predicate(n->as_Vector()->length() == 2);
10914   match(Set dst (ReplicateF con));
10915   effect(KILL tmp);
10916   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10917   ins_encode %{
10918     // XXX This is a quick fix for 6833573.
10919     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10920     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10921     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10922   %}
10923   ins_pipe(loadConFD);
10924 %}
10925 
10926 //----------PEEPHOLE RULES-----------------------------------------------------
10927 // These must follow all instruction definitions as they use the names
10928 // defined in the instructions definitions.
10929 //
10930 // peepmatch ( root_instr_name [preceding_instruction]* );
10931 //
10932 // peepconstraint %{
10933 // (instruction_number.operand_name relational_op instruction_number.operand_name
10934 //  [, ...] );
10935 // // instruction numbers are zero-based using left to right order in peepmatch
10936 //
10937 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
10938 // // provide an instruction_number.operand_name for each operand that appears
10939 // // in the replacement instruction's match rule
10940 //
10941 // ---------VM FLAGS---------------------------------------------------------
10942 //
10943 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10944 //
10945 // Each peephole rule is given an identifying number starting with zero and
10946 // increasing by one in the order seen by the parser.  An individual peephole
10947 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10948 // on the command-line.
10949 //
10950 // ---------CURRENT LIMITATIONS----------------------------------------------
10951 //
10952 // Only match adjacent instructions in same basic block
10953 // Only equality constraints
10954 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10955 // Only one replacement instruction
10956 //
10957 // ---------EXAMPLE----------------------------------------------------------
10958 //
10959 // // pertinent parts of existing instructions in architecture description
10960 // instruct movI(eRegI dst, eRegI src) %{
10961 //   match(Set dst (CopyI src));
10962 // %}
10963 //
10964 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10965 //   match(Set dst (AddI dst src));
10966 //   effect(KILL cr);
10967 // %}
10968 //
10969 // // Change (inc mov) to lea
10970 // peephole %{
10971 //   // increment preceeded by register-register move
10972 //   peepmatch ( incI_eReg movI );
10973 //   // require that the destination register of the increment
10974 //   // match the destination register of the move
10975 //   peepconstraint ( 0.dst == 1.dst );
10976 //   // construct a replacement instruction that sets
10977 //   // the destination to ( move's source register + one )
10978 //   peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10979 // %}
10980 //
10981 
10982 // // Change load of spilled value to only a spill
10983 // instruct storeI(memory mem, eRegI src) %{
10984 //   match(Set mem (StoreI mem src));
10985 // %}
10986 //
10987 // instruct loadI(eRegI dst, memory mem) %{
10988 //   match(Set dst (LoadI mem));
10989 // %}
10990 //
10991 // peephole %{
10992 //   peepmatch ( loadI storeI );
10993 //   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10994 //   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10995 // %}
10996 
10997 //----------SMARTSPILL RULES---------------------------------------------------
10998 // These must follow all instruction definitions as they use the names
10999 // defined in the instructions definitions.
11000 //
11001 // SPARC will probably not have any of these rules due to RISC instruction set.
11002 
11003 //----------PIPELINE-----------------------------------------------------------
11004 // Rules which define the behavior of the target architectures pipeline.