1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "logging/log.hpp"
30 #include "logging/logStream.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "vm_version_x86.hpp"
36
37
38 int VM_Version::_cpu;
39 int VM_Version::_model;
40 int VM_Version::_stepping;
41 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
42
43 // Address of instruction which causes SEGV
44 address VM_Version::_cpuinfo_segv_addr = 0;
45 // Address of instruction after the one which causes SEGV
46 address VM_Version::_cpuinfo_cont_addr = 0;
47
48 static BufferBlob* stub_blob;
49 static const int stub_size = 1100;
50
51 extern "C" {
52 typedef void (*get_cpu_info_stub_t)(void*);
53 }
54 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
55
56
57 class VM_Version_StubGenerator: public StubCodeGenerator {
58 public:
59
60 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
61
62 address generate_get_cpu_info() {
63 // Flags to test CPU type.
64 const uint32_t HS_EFL_AC = 0x40000;
65 const uint32_t HS_EFL_ID = 0x200000;
66 // Values for when we don't have a CPUID instruction.
67 const int CPU_FAMILY_SHIFT = 8;
68 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
69 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
70 bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2);
71
72 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
73 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, ext_cpuid8, done, wrapup;
74 Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
75
76 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
77 # define __ _masm->
78
79 address start = __ pc();
80
81 //
82 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
83 //
84 // LP64: rcx and rdx are first and second argument registers on windows
85
86 __ push(rbp);
87 #ifdef _LP64
88 __ mov(rbp, c_rarg0); // cpuid_info address
89 #else
90 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
91 #endif
92 __ push(rbx);
93 __ push(rsi);
94 __ pushf(); // preserve rbx, and flags
95 __ pop(rax);
96 __ push(rax);
97 __ mov(rcx, rax);
98 //
99 // if we are unable to change the AC flag, we have a 386
100 //
101 __ xorl(rax, HS_EFL_AC);
102 __ push(rax);
103 __ popf();
104 __ pushf();
105 __ pop(rax);
106 __ cmpptr(rax, rcx);
107 __ jccb(Assembler::notEqual, detect_486);
108
109 __ movl(rax, CPU_FAMILY_386);
110 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
111 __ jmp(done);
112
113 //
114 // If we are unable to change the ID flag, we have a 486 which does
115 // not support the "cpuid" instruction.
116 //
117 __ bind(detect_486);
118 __ mov(rax, rcx);
119 __ xorl(rax, HS_EFL_ID);
120 __ push(rax);
121 __ popf();
122 __ pushf();
123 __ pop(rax);
124 __ cmpptr(rcx, rax);
125 __ jccb(Assembler::notEqual, detect_586);
126
127 __ bind(cpu486);
128 __ movl(rax, CPU_FAMILY_486);
129 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
130 __ jmp(done);
131
132 //
133 // At this point, we have a chip which supports the "cpuid" instruction
134 //
135 __ bind(detect_586);
136 __ xorl(rax, rax);
137 __ cpuid();
138 __ orl(rax, rax);
139 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
140 // value of at least 1, we give up and
141 // assume a 486
142 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
143 __ movl(Address(rsi, 0), rax);
144 __ movl(Address(rsi, 4), rbx);
145 __ movl(Address(rsi, 8), rcx);
146 __ movl(Address(rsi,12), rdx);
147
148 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
149 __ jccb(Assembler::belowEqual, std_cpuid4);
150
151 //
152 // cpuid(0xB) Processor Topology
153 //
154 __ movl(rax, 0xb);
155 __ xorl(rcx, rcx); // Threads level
156 __ cpuid();
157
158 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
159 __ movl(Address(rsi, 0), rax);
160 __ movl(Address(rsi, 4), rbx);
161 __ movl(Address(rsi, 8), rcx);
162 __ movl(Address(rsi,12), rdx);
163
164 __ movl(rax, 0xb);
165 __ movl(rcx, 1); // Cores level
166 __ cpuid();
167 __ push(rax);
168 __ andl(rax, 0x1f); // Determine if valid topology level
169 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
170 __ andl(rax, 0xffff);
171 __ pop(rax);
172 __ jccb(Assembler::equal, std_cpuid4);
173
174 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
175 __ movl(Address(rsi, 0), rax);
176 __ movl(Address(rsi, 4), rbx);
177 __ movl(Address(rsi, 8), rcx);
178 __ movl(Address(rsi,12), rdx);
179
180 __ movl(rax, 0xb);
181 __ movl(rcx, 2); // Packages level
182 __ cpuid();
183 __ push(rax);
184 __ andl(rax, 0x1f); // Determine if valid topology level
185 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
186 __ andl(rax, 0xffff);
187 __ pop(rax);
188 __ jccb(Assembler::equal, std_cpuid4);
189
190 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
191 __ movl(Address(rsi, 0), rax);
192 __ movl(Address(rsi, 4), rbx);
193 __ movl(Address(rsi, 8), rcx);
194 __ movl(Address(rsi,12), rdx);
195
196 //
197 // cpuid(0x4) Deterministic cache params
198 //
199 __ bind(std_cpuid4);
200 __ movl(rax, 4);
201 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
202 __ jccb(Assembler::greater, std_cpuid1);
203
204 __ xorl(rcx, rcx); // L1 cache
205 __ cpuid();
206 __ push(rax);
207 __ andl(rax, 0x1f); // Determine if valid cache parameters used
208 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
209 __ pop(rax);
210 __ jccb(Assembler::equal, std_cpuid1);
211
212 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
213 __ movl(Address(rsi, 0), rax);
214 __ movl(Address(rsi, 4), rbx);
215 __ movl(Address(rsi, 8), rcx);
216 __ movl(Address(rsi,12), rdx);
217
218 //
219 // Standard cpuid(0x1)
220 //
221 __ bind(std_cpuid1);
222 __ movl(rax, 1);
223 __ cpuid();
224 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
225 __ movl(Address(rsi, 0), rax);
226 __ movl(Address(rsi, 4), rbx);
227 __ movl(Address(rsi, 8), rcx);
228 __ movl(Address(rsi,12), rdx);
229
230 //
231 // Check if OS has enabled XGETBV instruction to access XCR0
232 // (OSXSAVE feature flag) and CPU supports AVX
233 //
234 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
235 __ cmpl(rcx, 0x18000000);
236 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
237
238 //
239 // XCR0, XFEATURE_ENABLED_MASK register
240 //
241 __ xorl(rcx, rcx); // zero for XCR0 register
242 __ xgetbv();
243 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
244 __ movl(Address(rsi, 0), rax);
245 __ movl(Address(rsi, 4), rdx);
246
247 //
248 // cpuid(0x7) Structured Extended Features
249 //
250 __ bind(sef_cpuid);
251 __ movl(rax, 7);
252 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
253 __ jccb(Assembler::greater, ext_cpuid);
254
255 __ xorl(rcx, rcx);
256 __ cpuid();
257 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
258 __ movl(Address(rsi, 0), rax);
259 __ movl(Address(rsi, 4), rbx);
260
261 //
262 // Extended cpuid(0x80000000)
263 //
264 __ bind(ext_cpuid);
265 __ movl(rax, 0x80000000);
266 __ cpuid();
267 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
268 __ jcc(Assembler::belowEqual, done);
269 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
270 __ jcc(Assembler::belowEqual, ext_cpuid1);
271 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
272 __ jccb(Assembler::belowEqual, ext_cpuid5);
273 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
274 __ jccb(Assembler::belowEqual, ext_cpuid7);
275 __ cmpl(rax, 0x80000008); // Is cpuid(0x80000009 and above) supported?
276 __ jccb(Assembler::belowEqual, ext_cpuid8);
277 __ cmpl(rax, 0x8000001E); // Is cpuid(0x8000001E) supported?
278 __ jccb(Assembler::below, ext_cpuid8);
279 //
280 // Extended cpuid(0x8000001E)
281 //
282 __ movl(rax, 0x8000001E);
283 __ cpuid();
284 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1E_offset())));
285 __ movl(Address(rsi, 0), rax);
286 __ movl(Address(rsi, 4), rbx);
287 __ movl(Address(rsi, 8), rcx);
288 __ movl(Address(rsi,12), rdx);
289
290 //
291 // Extended cpuid(0x80000008)
292 //
293 __ bind(ext_cpuid8);
294 __ movl(rax, 0x80000008);
295 __ cpuid();
296 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
297 __ movl(Address(rsi, 0), rax);
298 __ movl(Address(rsi, 4), rbx);
299 __ movl(Address(rsi, 8), rcx);
300 __ movl(Address(rsi,12), rdx);
301
302 //
303 // Extended cpuid(0x80000007)
304 //
305 __ bind(ext_cpuid7);
306 __ movl(rax, 0x80000007);
307 __ cpuid();
308 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
309 __ movl(Address(rsi, 0), rax);
310 __ movl(Address(rsi, 4), rbx);
311 __ movl(Address(rsi, 8), rcx);
312 __ movl(Address(rsi,12), rdx);
313
314 //
315 // Extended cpuid(0x80000005)
316 //
317 __ bind(ext_cpuid5);
318 __ movl(rax, 0x80000005);
319 __ cpuid();
320 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
321 __ movl(Address(rsi, 0), rax);
322 __ movl(Address(rsi, 4), rbx);
323 __ movl(Address(rsi, 8), rcx);
324 __ movl(Address(rsi,12), rdx);
325
326 //
327 // Extended cpuid(0x80000001)
328 //
329 __ bind(ext_cpuid1);
330 __ movl(rax, 0x80000001);
331 __ cpuid();
332 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
333 __ movl(Address(rsi, 0), rax);
334 __ movl(Address(rsi, 4), rbx);
335 __ movl(Address(rsi, 8), rcx);
336 __ movl(Address(rsi,12), rdx);
337
338 //
339 // Check if OS has enabled XGETBV instruction to access XCR0
340 // (OSXSAVE feature flag) and CPU supports AVX
341 //
342 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
343 __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
344 __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
345 __ cmpl(rcx, 0x18000000);
346 __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
347
348 __ movl(rax, 0x6);
349 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
350 __ cmpl(rax, 0x6);
351 __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
352
353 // we need to bridge farther than imm8, so we use this island as a thunk
354 __ bind(done);
355 __ jmp(wrapup);
356
357 __ bind(start_simd_check);
358 //
359 // Some OSs have a bug when upper 128/256bits of YMM/ZMM
360 // registers are not restored after a signal processing.
361 // Generate SEGV here (reference through NULL)
362 // and check upper YMM/ZMM bits after it.
363 //
364 intx saved_useavx = UseAVX;
365 intx saved_usesse = UseSSE;
366 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
367 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
368 __ movl(rax, 0x10000);
369 __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
370 __ cmpl(rax, 0x10000);
371 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
372 // check _cpuid_info.xem_xcr0_eax.bits.opmask
373 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
374 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
375 __ movl(rax, 0xE0);
376 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
377 __ cmpl(rax, 0xE0);
378 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
379
380 // If UseAVX is unitialized or is set by the user to include EVEX
381 if (use_evex) {
382 // EVEX setup: run in lowest evex mode
383 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
384 UseAVX = 3;
385 UseSSE = 2;
386 #ifdef _WINDOWS
387 // xmm5-xmm15 are not preserved by caller on windows
388 // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
389 __ subptr(rsp, 64);
390 __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit);
391 #ifdef _LP64
392 __ subptr(rsp, 64);
393 __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit);
394 __ subptr(rsp, 64);
395 __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit);
396 #endif // _LP64
397 #endif // _WINDOWS
398
399 // load value into all 64 bytes of zmm7 register
400 __ movl(rcx, VM_Version::ymm_test_value());
401 __ movdl(xmm0, rcx);
402 __ movl(rcx, 0xffff);
403 __ kmovwl(k1, rcx);
404 __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
405 __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
406 #ifdef _LP64
407 __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
408 __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
409 #endif
410 VM_Version::clean_cpuFeatures();
411 __ jmp(save_restore_except);
412 }
413
414 __ bind(legacy_setup);
415 // AVX setup
416 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
417 UseAVX = 1;
418 UseSSE = 2;
419 #ifdef _WINDOWS
420 __ subptr(rsp, 32);
421 __ vmovdqu(Address(rsp, 0), xmm7);
422 #ifdef _LP64
423 __ subptr(rsp, 32);
424 __ vmovdqu(Address(rsp, 0), xmm8);
425 __ subptr(rsp, 32);
426 __ vmovdqu(Address(rsp, 0), xmm15);
427 #endif // _LP64
428 #endif // _WINDOWS
429
430 // load value into all 32 bytes of ymm7 register
431 __ movl(rcx, VM_Version::ymm_test_value());
432
433 __ movdl(xmm0, rcx);
434 __ pshufd(xmm0, xmm0, 0x00);
435 __ vinsertf128_high(xmm0, xmm0);
436 __ vmovdqu(xmm7, xmm0);
437 #ifdef _LP64
438 __ vmovdqu(xmm8, xmm0);
439 __ vmovdqu(xmm15, xmm0);
440 #endif
441 VM_Version::clean_cpuFeatures();
442
443 __ bind(save_restore_except);
444 __ xorl(rsi, rsi);
445 VM_Version::set_cpuinfo_segv_addr(__ pc());
446 // Generate SEGV
447 __ movl(rax, Address(rsi, 0));
448
449 VM_Version::set_cpuinfo_cont_addr(__ pc());
450 // Returns here after signal. Save xmm0 to check it later.
451
452 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
453 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
454 __ movl(rax, 0x10000);
455 __ andl(rax, Address(rsi, 4));
456 __ cmpl(rax, 0x10000);
457 __ jcc(Assembler::notEqual, legacy_save_restore);
458 // check _cpuid_info.xem_xcr0_eax.bits.opmask
459 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
460 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
461 __ movl(rax, 0xE0);
462 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
463 __ cmpl(rax, 0xE0);
464 __ jcc(Assembler::notEqual, legacy_save_restore);
465
466 // If UseAVX is unitialized or is set by the user to include EVEX
467 if (use_evex) {
468 // EVEX check: run in lowest evex mode
469 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
470 UseAVX = 3;
471 UseSSE = 2;
472 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
473 __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
474 __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
475 #ifdef _LP64
476 __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
477 __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
478 #endif
479
480 #ifdef _WINDOWS
481 #ifdef _LP64
482 __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
483 __ addptr(rsp, 64);
484 __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
485 __ addptr(rsp, 64);
486 #endif // _LP64
487 __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
488 __ addptr(rsp, 64);
489 #endif // _WINDOWS
490 generate_vzeroupper(wrapup);
491 VM_Version::clean_cpuFeatures();
492 UseAVX = saved_useavx;
493 UseSSE = saved_usesse;
494 __ jmp(wrapup);
495 }
496
497 __ bind(legacy_save_restore);
498 // AVX check
499 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
500 UseAVX = 1;
501 UseSSE = 2;
502 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
503 __ vmovdqu(Address(rsi, 0), xmm0);
504 __ vmovdqu(Address(rsi, 32), xmm7);
505 #ifdef _LP64
506 __ vmovdqu(Address(rsi, 64), xmm8);
507 __ vmovdqu(Address(rsi, 96), xmm15);
508 #endif
509
510 #ifdef _WINDOWS
511 #ifdef _LP64
512 __ vmovdqu(xmm15, Address(rsp, 0));
513 __ addptr(rsp, 32);
514 __ vmovdqu(xmm8, Address(rsp, 0));
515 __ addptr(rsp, 32);
516 #endif // _LP64
517 __ vmovdqu(xmm7, Address(rsp, 0));
518 __ addptr(rsp, 32);
519 #endif // _WINDOWS
520 generate_vzeroupper(wrapup);
521 VM_Version::clean_cpuFeatures();
522 UseAVX = saved_useavx;
523 UseSSE = saved_usesse;
524
525 __ bind(wrapup);
526 __ popf();
527 __ pop(rsi);
528 __ pop(rbx);
529 __ pop(rbp);
530 __ ret(0);
531
532 # undef __
533
534 return start;
535 };
536 void generate_vzeroupper(Label& L_wrapup) {
537 # define __ _masm->
538 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
539 __ cmpl(Address(rsi, 4), 0x756e6547); // 'uneG'
540 __ jcc(Assembler::notEqual, L_wrapup);
541 __ movl(rcx, 0x0FFF0FF0);
542 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
543 __ andl(rcx, Address(rsi, 0));
544 __ cmpl(rcx, 0x00050670); // If it is Xeon Phi 3200/5200/7200
545 __ jcc(Assembler::equal, L_wrapup);
546 __ cmpl(rcx, 0x00080650); // If it is Future Xeon Phi
547 __ jcc(Assembler::equal, L_wrapup);
548 __ vzeroupper();
549 # undef __
550 }
551 };
552
553 void VM_Version::get_processor_features() {
554
555 _cpu = 4; // 486 by default
556 _model = 0;
557 _stepping = 0;
558 _features = 0;
559 _logical_processors_per_package = 1;
560 // i486 internal cache is both I&D and has a 16-byte line size
561 _L1_data_cache_line_size = 16;
562
563 // Get raw processor info
564
565 get_cpu_info_stub(&_cpuid_info);
566
567 assert_is_initialized();
568 _cpu = extended_cpu_family();
569 _model = extended_cpu_model();
570 _stepping = cpu_stepping();
571
572 if (cpu_family() > 4) { // it supports CPUID
573 _features = feature_flags();
574 // Logical processors are only available on P4s and above,
575 // and only if hyperthreading is available.
576 _logical_processors_per_package = logical_processor_count();
577 _L1_data_cache_line_size = L1_line_size();
578 }
579
580 _supports_cx8 = supports_cmpxchg8();
581 // xchg and xadd instructions
582 _supports_atomic_getset4 = true;
583 _supports_atomic_getadd4 = true;
584 LP64_ONLY(_supports_atomic_getset8 = true);
585 LP64_ONLY(_supports_atomic_getadd8 = true);
586
587 #ifdef _LP64
588 // OS should support SSE for x64 and hardware should support at least SSE2.
589 if (!VM_Version::supports_sse2()) {
590 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
591 }
592 // in 64 bit the use of SSE2 is the minimum
593 if (UseSSE < 2) UseSSE = 2;
594 #endif
595
596 #ifdef AMD64
597 // flush_icache_stub have to be generated first.
598 // That is why Icache line size is hard coded in ICache class,
599 // see icache_x86.hpp. It is also the reason why we can't use
600 // clflush instruction in 32-bit VM since it could be running
601 // on CPU which does not support it.
602 //
603 // The only thing we can do is to verify that flushed
604 // ICache::line_size has correct value.
605 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
606 // clflush_size is size in quadwords (8 bytes).
607 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
608 #endif
609
610 // If the OS doesn't support SSE, we can't use this feature even if the HW does
611 if (!os::supports_sse())
612 _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
613
614 if (UseSSE < 4) {
615 _features &= ~CPU_SSE4_1;
616 _features &= ~CPU_SSE4_2;
617 }
618
619 if (UseSSE < 3) {
620 _features &= ~CPU_SSE3;
621 _features &= ~CPU_SSSE3;
622 _features &= ~CPU_SSE4A;
623 }
624
625 if (UseSSE < 2)
626 _features &= ~CPU_SSE2;
627
628 if (UseSSE < 1)
629 _features &= ~CPU_SSE;
630
631 // first try initial setting and detect what we can support
632 int use_avx_limit = 0;
633 if (UseAVX > 0) {
634 if (UseAVX > 2 && supports_evex()) {
635 use_avx_limit = 3;
636 } else if (UseAVX > 1 && supports_avx2()) {
637 use_avx_limit = 2;
638 } else if (UseAVX > 0 && supports_avx()) {
639 use_avx_limit = 1;
640 } else {
641 use_avx_limit = 0;
642 }
643 }
644 if (FLAG_IS_DEFAULT(UseAVX)) {
645 FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
646 } else if (UseAVX > use_avx_limit) {
647 warning("UseAVX=%d is not supported on this CPU, setting it to UseAVX=%d", (int) UseAVX, use_avx_limit);
648 FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
649 } else if (UseAVX < 0) {
650 warning("UseAVX=%d is not valid, setting it to UseAVX=0", (int) UseAVX);
651 FLAG_SET_DEFAULT(UseAVX, 0);
652 }
653
654 if (UseAVX < 3) {
655 _features &= ~CPU_AVX512F;
656 _features &= ~CPU_AVX512DQ;
657 _features &= ~CPU_AVX512CD;
658 _features &= ~CPU_AVX512BW;
659 _features &= ~CPU_AVX512VL;
660 }
661
662 if (UseAVX < 2)
663 _features &= ~CPU_AVX2;
664
665 if (UseAVX < 1) {
666 _features &= ~CPU_AVX;
667 _features &= ~CPU_VZEROUPPER;
668 }
669
670 if (logical_processors_per_package() == 1) {
671 // HT processor could be installed on a system which doesn't support HT.
672 _features &= ~CPU_HT;
673 }
674
675 if( is_intel() ) { // Intel cpus specific settings
676 if (is_knights_family()) {
677 _features &= ~CPU_VZEROUPPER;
678 }
679 }
680
681 char buf[256];
682 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
683 cores_per_cpu(), threads_per_core(),
684 cpu_family(), _model, _stepping,
685 (supports_cmov() ? ", cmov" : ""),
686 (supports_cmpxchg8() ? ", cx8" : ""),
687 (supports_fxsr() ? ", fxsr" : ""),
688 (supports_mmx() ? ", mmx" : ""),
689 (supports_sse() ? ", sse" : ""),
690 (supports_sse2() ? ", sse2" : ""),
691 (supports_sse3() ? ", sse3" : ""),
692 (supports_ssse3()? ", ssse3": ""),
693 (supports_sse4_1() ? ", sse4.1" : ""),
694 (supports_sse4_2() ? ", sse4.2" : ""),
695 (supports_popcnt() ? ", popcnt" : ""),
696 (supports_avx() ? ", avx" : ""),
697 (supports_avx2() ? ", avx2" : ""),
698 (supports_aes() ? ", aes" : ""),
699 (supports_clmul() ? ", clmul" : ""),
700 (supports_erms() ? ", erms" : ""),
701 (supports_rtm() ? ", rtm" : ""),
702 (supports_mmx_ext() ? ", mmxext" : ""),
703 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
704 (supports_lzcnt() ? ", lzcnt": ""),
705 (supports_sse4a() ? ", sse4a": ""),
706 (supports_ht() ? ", ht": ""),
707 (supports_tsc() ? ", tsc": ""),
708 (supports_tscinv_bit() ? ", tscinvbit": ""),
709 (supports_tscinv() ? ", tscinv": ""),
710 (supports_bmi1() ? ", bmi1" : ""),
711 (supports_bmi2() ? ", bmi2" : ""),
712 (supports_adx() ? ", adx" : ""),
713 (supports_evex() ? ", evex" : ""),
714 (supports_sha() ? ", sha" : ""),
715 (supports_fma() ? ", fma" : ""));
716 _features_string = os::strdup(buf);
717
718 // UseSSE is set to the smaller of what hardware supports and what
719 // the command line requires. I.e., you cannot set UseSSE to 2 on
720 // older Pentiums which do not support it.
721 int use_sse_limit = 0;
722 if (UseSSE > 0) {
723 if (UseSSE > 3 && supports_sse4_1()) {
724 use_sse_limit = 4;
725 } else if (UseSSE > 2 && supports_sse3()) {
726 use_sse_limit = 3;
727 } else if (UseSSE > 1 && supports_sse2()) {
728 use_sse_limit = 2;
729 } else if (UseSSE > 0 && supports_sse()) {
730 use_sse_limit = 1;
731 } else {
732 use_sse_limit = 0;
733 }
734 }
735 if (FLAG_IS_DEFAULT(UseSSE)) {
736 FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
737 } else if (UseSSE > use_sse_limit) {
738 warning("UseSSE=%d is not supported on this CPU, setting it to UseSSE=%d", (int) UseSSE, use_sse_limit);
739 FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
740 } else if (UseSSE < 0) {
741 warning("UseSSE=%d is not valid, setting it to UseSSE=0", (int) UseSSE);
742 FLAG_SET_DEFAULT(UseSSE, 0);
743 }
744
745 // Use AES instructions if available.
746 if (supports_aes()) {
747 if (FLAG_IS_DEFAULT(UseAES)) {
748 FLAG_SET_DEFAULT(UseAES, true);
749 }
750 if (!UseAES) {
751 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
752 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
753 }
754 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
755 } else {
756 if (UseSSE > 2) {
757 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
758 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
759 }
760 } else {
761 // The AES intrinsic stubs require AES instruction support (of course)
762 // but also require sse3 mode or higher for instructions it use.
763 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
764 warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
765 }
766 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
767 }
768
769 // --AES-CTR begins--
770 if (!UseAESIntrinsics) {
771 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
772 warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
773 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
774 }
775 } else {
776 if(supports_sse4_1()) {
777 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
778 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
779 }
780 } else {
781 // The AES-CTR intrinsic stubs require AES instruction support (of course)
782 // but also require sse4.1 mode or higher for instructions it use.
783 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
784 warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
785 }
786 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
787 }
788 }
789 // --AES-CTR ends--
790 }
791 } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
792 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
793 warning("AES instructions are not available on this CPU");
794 FLAG_SET_DEFAULT(UseAES, false);
795 }
796 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
797 warning("AES intrinsics are not available on this CPU");
798 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
799 }
800 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
801 warning("AES-CTR intrinsics are not available on this CPU");
802 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
803 }
804 }
805
806 // Use CLMUL instructions if available.
807 if (supports_clmul()) {
808 if (FLAG_IS_DEFAULT(UseCLMUL)) {
809 UseCLMUL = true;
810 }
811 } else if (UseCLMUL) {
812 if (!FLAG_IS_DEFAULT(UseCLMUL))
813 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
814 FLAG_SET_DEFAULT(UseCLMUL, false);
815 }
816
817 if (UseCLMUL && (UseSSE > 2)) {
818 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
819 UseCRC32Intrinsics = true;
820 }
821 } else if (UseCRC32Intrinsics) {
822 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
823 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
824 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
825 }
826
827 if (supports_sse4_2() && supports_clmul()) {
828 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
829 UseCRC32CIntrinsics = true;
830 }
831 } else if (UseCRC32CIntrinsics) {
832 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
833 warning("CRC32C intrinsics are not available on this CPU");
834 }
835 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
836 }
837
838 // GHASH/GCM intrinsics
839 if (UseCLMUL && (UseSSE > 2)) {
840 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
841 UseGHASHIntrinsics = true;
842 }
843 } else if (UseGHASHIntrinsics) {
844 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
845 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
846 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
847 }
848
849 if (supports_fma() && UseSSE >= 2) { // Check UseSSE since FMA code uses SSE instructions
850 if (FLAG_IS_DEFAULT(UseFMA)) {
851 UseFMA = true;
852 }
853 } else if (UseFMA) {
854 warning("FMA instructions are not available on this CPU");
855 FLAG_SET_DEFAULT(UseFMA, false);
856 }
857
858 if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) {
859 if (FLAG_IS_DEFAULT(UseSHA)) {
860 UseSHA = true;
861 }
862 } else if (UseSHA) {
863 warning("SHA instructions are not available on this CPU");
864 FLAG_SET_DEFAULT(UseSHA, false);
865 }
866
867 if (supports_sha() && UseSHA) {
868 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
869 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
870 }
871 } else if (UseSHA1Intrinsics) {
872 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
873 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
874 }
875
876 if (UseSHA) {
877 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
878 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
879 }
880 } else if (UseSHA256Intrinsics) {
881 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
882 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
883 }
884
885 if (UseSHA LP64_ONLY(&& supports_avx2() && supports_bmi2())) {
886 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
887 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
888 }
889 } else if (UseSHA512Intrinsics) {
890 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
891 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
892 }
893
894 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
895 FLAG_SET_DEFAULT(UseSHA, false);
896 }
897
898 if (UseAdler32Intrinsics) {
899 warning("Adler32Intrinsics not available on this CPU.");
900 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
901 }
902
903 if (!supports_rtm() && UseRTMLocking) {
904 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
905 // setting during arguments processing. See use_biased_locking().
906 // VM_Version_init() is executed after UseBiasedLocking is used
907 // in Thread::allocate().
908 vm_exit_during_initialization("RTM instructions are not available on this CPU");
909 }
910
911 #if INCLUDE_RTM_OPT
912 if (UseRTMLocking) {
913 if (is_client_compilation_mode_vm()) {
914 // Only C2 does RTM locking optimization.
915 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
916 // setting during arguments processing. See use_biased_locking().
917 vm_exit_during_initialization("RTM locking optimization is not supported in emulated client VM");
918 }
919 if (is_intel_family_core()) {
920 if ((_model == CPU_MODEL_HASWELL_E3) ||
921 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
922 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) {
923 // currently a collision between SKL and HSW_E3
924 if (!UnlockExperimentalVMOptions && UseAVX < 3) {
925 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this "
926 "platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
927 } else {
928 warning("UseRTMLocking is only available as experimental option on this platform.");
929 }
930 }
931 }
932 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
933 // RTM locking should be used only for applications with
934 // high lock contention. For now we do not use it by default.
935 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
936 }
937 } else { // !UseRTMLocking
938 if (UseRTMForStackLocks) {
939 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
940 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
941 }
942 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
943 }
944 if (UseRTMDeopt) {
945 FLAG_SET_DEFAULT(UseRTMDeopt, false);
946 }
947 if (PrintPreciseRTMLockingStatistics) {
948 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
949 }
950 }
951 #else
952 if (UseRTMLocking) {
953 // Only C2 does RTM locking optimization.
954 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
955 // setting during arguments processing. See use_biased_locking().
956 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
957 }
958 #endif
959
960 #ifdef COMPILER2
961 if (UseFPUForSpilling) {
962 if (UseSSE < 2) {
963 // Only supported with SSE2+
964 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
965 }
966 }
967 #endif
968 #if COMPILER2_OR_JVMCI
969 if (MaxVectorSize > 0) {
970 if (!is_power_of_2(MaxVectorSize)) {
971 warning("MaxVectorSize must be a power of 2");
972 FLAG_SET_DEFAULT(MaxVectorSize, 64);
973 }
974 if (UseSSE < 2) {
975 // Vectors (in XMM) are only supported with SSE2+
976 if (MaxVectorSize > 0) {
977 if (!FLAG_IS_DEFAULT(MaxVectorSize))
978 warning("MaxVectorSize must be 0");
979 FLAG_SET_DEFAULT(MaxVectorSize, 0);
980 }
981 }
982 else if (UseAVX == 0 || !os_supports_avx_vectors()) {
983 // 32 bytes vectors (in YMM) are only supported with AVX+
984 if (MaxVectorSize > 16) {
985 if (!FLAG_IS_DEFAULT(MaxVectorSize))
986 warning("MaxVectorSize must be <= 16");
987 FLAG_SET_DEFAULT(MaxVectorSize, 16);
988 }
989 }
990 else if (UseAVX == 1 || UseAVX == 2) {
991 // 64 bytes vectors (in ZMM) are only supported with AVX 3
992 if (MaxVectorSize > 32) {
993 if (!FLAG_IS_DEFAULT(MaxVectorSize))
994 warning("MaxVectorSize must be <= 32");
995 FLAG_SET_DEFAULT(MaxVectorSize, 32);
996 }
997 }
998 else if (UseAVX > 2 ) {
999 if (MaxVectorSize > 64) {
1000 if (!FLAG_IS_DEFAULT(MaxVectorSize))
1001 warning("MaxVectorSize must be <= 64");
1002 FLAG_SET_DEFAULT(MaxVectorSize, 64);
1003 }
1004 }
1005 #if defined(COMPILER2) && defined(ASSERT)
1006 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
1007 tty->print_cr("State of YMM registers after signal handle:");
1008 int nreg = 2 LP64_ONLY(+2);
1009 const char* ymm_name[4] = {"0", "7", "8", "15"};
1010 for (int i = 0; i < nreg; i++) {
1011 tty->print("YMM%s:", ymm_name[i]);
1012 for (int j = 7; j >=0; j--) {
1013 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
1014 }
1015 tty->cr();
1016 }
1017 }
1018 #endif // COMPILER2 && ASSERT
1019 }
1020 #endif // COMPILER2_OR_JVMCI
1021
1022 #ifdef COMPILER2
1023 #ifdef _LP64
1024 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1025 UseMultiplyToLenIntrinsic = true;
1026 }
1027 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1028 UseSquareToLenIntrinsic = true;
1029 }
1030 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1031 UseMulAddIntrinsic = true;
1032 }
1033 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1034 UseMontgomeryMultiplyIntrinsic = true;
1035 }
1036 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1037 UseMontgomerySquareIntrinsic = true;
1038 }
1039 #else
1040 if (UseMultiplyToLenIntrinsic) {
1041 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1042 warning("multiplyToLen intrinsic is not available in 32-bit VM");
1043 }
1044 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
1045 }
1046 if (UseMontgomeryMultiplyIntrinsic) {
1047 if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1048 warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
1049 }
1050 FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
1051 }
1052 if (UseMontgomerySquareIntrinsic) {
1053 if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1054 warning("montgomerySquare intrinsic is not available in 32-bit VM");
1055 }
1056 FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
1057 }
1058 if (UseSquareToLenIntrinsic) {
1059 if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1060 warning("squareToLen intrinsic is not available in 32-bit VM");
1061 }
1062 FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
1063 }
1064 if (UseMulAddIntrinsic) {
1065 if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1066 warning("mulAdd intrinsic is not available in 32-bit VM");
1067 }
1068 FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
1069 }
1070 #endif
1071 #endif // COMPILER2
1072
1073 // On new cpus instructions which update whole XMM register should be used
1074 // to prevent partial register stall due to dependencies on high half.
1075 //
1076 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
1077 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1078 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
1079 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
1080
1081 if( is_amd() ) { // AMD cpus specific settings
1082 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
1083 // Use it on new AMD cpus starting from Opteron.
1084 UseAddressNop = true;
1085 }
1086 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
1087 // Use it on new AMD cpus starting from Opteron.
1088 UseNewLongLShift = true;
1089 }
1090 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1091 if (supports_sse4a()) {
1092 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1093 } else {
1094 UseXmmLoadAndClearUpper = false;
1095 }
1096 }
1097 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1098 if( supports_sse4a() ) {
1099 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1100 } else {
1101 UseXmmRegToRegMoveAll = false;
1102 }
1103 }
1104 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
1105 if( supports_sse4a() ) {
1106 UseXmmI2F = true;
1107 } else {
1108 UseXmmI2F = false;
1109 }
1110 }
1111 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
1112 if( supports_sse4a() ) {
1113 UseXmmI2D = true;
1114 } else {
1115 UseXmmI2D = false;
1116 }
1117 }
1118 if (supports_sse4_2()) {
1119 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1120 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1121 }
1122 } else {
1123 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1124 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1125 }
1126 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1127 }
1128
1129 // some defaults for AMD family 15h
1130 if ( cpu_family() == 0x15 ) {
1131 // On family 15h processors default is no sw prefetch
1132 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1133 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1134 }
1135 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1136 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1137 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1138 }
1139 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1140 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1141 FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1142 }
1143 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1144 FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1145 }
1146 }
1147
1148 #ifdef COMPILER2
1149 if (cpu_family() < 0x17 && MaxVectorSize > 16) {
1150 // Limit vectors size to 16 bytes on AMD cpus < 17h.
1151 FLAG_SET_DEFAULT(MaxVectorSize, 16);
1152 }
1153 #endif // COMPILER2
1154
1155 // Some defaults for AMD family 17h
1156 if ( cpu_family() == 0x17 ) {
1157 // On family 17h processors use XMM and UnalignedLoadStores for Array Copy
1158 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1159 FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1160 }
1161 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1162 FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1163 }
1164 #ifdef COMPILER2
1165 if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1166 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1167 }
1168 #endif
1169 }
1170 }
1171
1172 if( is_intel() ) { // Intel cpus specific settings
1173 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
1174 UseStoreImmI16 = false; // don't use it on Intel cpus
1175 }
1176 if( cpu_family() == 6 || cpu_family() == 15 ) {
1177 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
1178 // Use it on all Intel cpus starting from PentiumPro
1179 UseAddressNop = true;
1180 }
1181 }
1182 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1183 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1184 }
1185 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1186 if( supports_sse3() ) {
1187 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1188 } else {
1189 UseXmmRegToRegMoveAll = false;
1190 }
1191 }
1192 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
1193 #ifdef COMPILER2
1194 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1195 // For new Intel cpus do the next optimization:
1196 // don't align the beginning of a loop if there are enough instructions
1197 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1198 // in current fetch line (OptoLoopAlignment) or the padding
1199 // is big (> MaxLoopPad).
1200 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1201 // generated NOP instructions. 11 is the largest size of one
1202 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1203 MaxLoopPad = 11;
1204 }
1205 #endif // COMPILER2
1206 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1207 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1208 }
1209 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
1210 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1211 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1212 }
1213 }
1214 if (supports_sse4_2()) {
1215 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1216 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1217 }
1218 } else {
1219 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1220 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1221 }
1222 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1223 }
1224 }
1225 if (is_atom_family() || is_knights_family()) {
1226 #ifdef COMPILER2
1227 if (FLAG_IS_DEFAULT(OptoScheduling)) {
1228 OptoScheduling = true;
1229 }
1230 #endif
1231 if (supports_sse4_2()) { // Silvermont
1232 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1233 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1234 }
1235 }
1236 if (FLAG_IS_DEFAULT(UseIncDec)) {
1237 FLAG_SET_DEFAULT(UseIncDec, false);
1238 }
1239 }
1240 if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1241 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1242 }
1243 }
1244
1245 #ifdef _LP64
1246 if (UseSSE42Intrinsics) {
1247 if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1248 UseVectorizedMismatchIntrinsic = true;
1249 }
1250 } else if (UseVectorizedMismatchIntrinsic) {
1251 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1252 warning("vectorizedMismatch intrinsics are not available on this CPU");
1253 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1254 }
1255 #else
1256 if (UseVectorizedMismatchIntrinsic) {
1257 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1258 warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1259 }
1260 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1261 }
1262 #endif // _LP64
1263
1264 // Use count leading zeros count instruction if available.
1265 if (supports_lzcnt()) {
1266 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1267 UseCountLeadingZerosInstruction = true;
1268 }
1269 } else if (UseCountLeadingZerosInstruction) {
1270 warning("lzcnt instruction is not available on this CPU");
1271 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1272 }
1273
1274 // Use count trailing zeros instruction if available
1275 if (supports_bmi1()) {
1276 // tzcnt does not require VEX prefix
1277 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1278 if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1279 // Don't use tzcnt if BMI1 is switched off on command line.
1280 UseCountTrailingZerosInstruction = false;
1281 } else {
1282 UseCountTrailingZerosInstruction = true;
1283 }
1284 }
1285 } else if (UseCountTrailingZerosInstruction) {
1286 warning("tzcnt instruction is not available on this CPU");
1287 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1288 }
1289
1290 // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1291 // VEX prefix is generated only when AVX > 0.
1292 if (supports_bmi1() && supports_avx()) {
1293 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1294 UseBMI1Instructions = true;
1295 }
1296 } else if (UseBMI1Instructions) {
1297 warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1298 FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1299 }
1300
1301 if (supports_bmi2() && supports_avx()) {
1302 if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1303 UseBMI2Instructions = true;
1304 }
1305 } else if (UseBMI2Instructions) {
1306 warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1307 FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1308 }
1309
1310 // Use population count instruction if available.
1311 if (supports_popcnt()) {
1312 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1313 UsePopCountInstruction = true;
1314 }
1315 } else if (UsePopCountInstruction) {
1316 warning("POPCNT instruction is not available on this CPU");
1317 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1318 }
1319
1320 // Use fast-string operations if available.
1321 if (supports_erms()) {
1322 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1323 UseFastStosb = true;
1324 }
1325 } else if (UseFastStosb) {
1326 warning("fast-string operations are not available on this CPU");
1327 FLAG_SET_DEFAULT(UseFastStosb, false);
1328 }
1329
1330 #ifdef COMPILER2
1331 if (FLAG_IS_DEFAULT(AlignVector)) {
1332 // Modern processors allow misaligned memory operations for vectors.
1333 AlignVector = !UseUnalignedLoadStores;
1334 }
1335 #endif // COMPILER2
1336
1337 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1338 if (AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch()) {
1339 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
1340 } else if (!supports_sse() && supports_3dnow_prefetch()) {
1341 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1342 }
1343 }
1344
1345 // Allocation prefetch settings
1346 intx cache_line_size = prefetch_data_size();
1347 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) &&
1348 (cache_line_size > AllocatePrefetchStepSize)) {
1349 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size);
1350 }
1351
1352 if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) {
1353 assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0");
1354 if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1355 warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag.");
1356 }
1357 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1358 }
1359
1360 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1361 bool use_watermark_prefetch = (AllocatePrefetchStyle == 2);
1362 FLAG_SET_DEFAULT(AllocatePrefetchDistance, allocate_prefetch_distance(use_watermark_prefetch));
1363 }
1364
1365 if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1366 if (FLAG_IS_DEFAULT(AllocatePrefetchLines) &&
1367 supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1368 FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
1369 }
1370 #ifdef COMPILER2
1371 if (FLAG_IS_DEFAULT(UseFPUForSpilling) && supports_sse4_2()) {
1372 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1373 }
1374 #endif
1375 }
1376
1377 #ifdef _LP64
1378 // Prefetch settings
1379
1380 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
1381 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
1382 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
1383 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
1384
1385 // gc copy/scan is disabled if prefetchw isn't supported, because
1386 // Prefetch::write emits an inlined prefetchw on Linux.
1387 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
1388 // The used prefetcht0 instruction works for both amd64 and em64t.
1389
1390 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) {
1391 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 576);
1392 }
1393 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1394 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1395 }
1396 if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
1397 FLAG_SET_DEFAULT(PrefetchFieldsAhead, 1);
1398 }
1399 #endif
1400
1401 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1402 (cache_line_size > ContendedPaddingWidth))
1403 ContendedPaddingWidth = cache_line_size;
1404
1405 // This machine allows unaligned memory accesses
1406 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1407 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1408 }
1409
1410 #ifndef PRODUCT
1411 if (log_is_enabled(Info, os, cpu)) {
1412 LogStream ls(Log(os, cpu)::info());
1413 outputStream* log = &ls;
1414 log->print_cr("Logical CPUs per core: %u",
1415 logical_processors_per_package());
1416 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1417 log->print("UseSSE=%d", (int) UseSSE);
1418 if (UseAVX > 0) {
1419 log->print(" UseAVX=%d", (int) UseAVX);
1420 }
1421 if (UseAES) {
1422 log->print(" UseAES=1");
1423 }
1424 #ifdef COMPILER2
1425 if (MaxVectorSize > 0) {
1426 log->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1427 }
1428 #endif
1429 log->cr();
1430 log->print("Allocation");
1431 if (AllocatePrefetchStyle <= 0 || (UseSSE == 0 && !supports_3dnow_prefetch())) {
1432 log->print_cr(": no prefetching");
1433 } else {
1434 log->print(" prefetching: ");
1435 if (UseSSE == 0 && supports_3dnow_prefetch()) {
1436 log->print("PREFETCHW");
1437 } else if (UseSSE >= 1) {
1438 if (AllocatePrefetchInstr == 0) {
1439 log->print("PREFETCHNTA");
1440 } else if (AllocatePrefetchInstr == 1) {
1441 log->print("PREFETCHT0");
1442 } else if (AllocatePrefetchInstr == 2) {
1443 log->print("PREFETCHT2");
1444 } else if (AllocatePrefetchInstr == 3) {
1445 log->print("PREFETCHW");
1446 }
1447 }
1448 if (AllocatePrefetchLines > 1) {
1449 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1450 } else {
1451 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1452 }
1453 }
1454
1455 if (PrefetchCopyIntervalInBytes > 0) {
1456 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1457 }
1458 if (PrefetchScanIntervalInBytes > 0) {
1459 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1460 }
1461 if (PrefetchFieldsAhead > 0) {
1462 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1463 }
1464 if (ContendedPaddingWidth > 0) {
1465 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1466 }
1467 }
1468 #endif // !PRODUCT
1469 }
1470
1471 bool VM_Version::use_biased_locking() {
1472 #if INCLUDE_RTM_OPT
1473 // RTM locking is most useful when there is high lock contention and
1474 // low data contention. With high lock contention the lock is usually
1475 // inflated and biased locking is not suitable for that case.
1476 // RTM locking code requires that biased locking is off.
1477 // Note: we can't switch off UseBiasedLocking in get_processor_features()
1478 // because it is used by Thread::allocate() which is called before
1479 // VM_Version::initialize().
1480 if (UseRTMLocking && UseBiasedLocking) {
1481 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1482 FLAG_SET_DEFAULT(UseBiasedLocking, false);
1483 } else {
1484 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1485 UseBiasedLocking = false;
1486 }
1487 }
1488 #endif
1489 return UseBiasedLocking;
1490 }
1491
1492 void VM_Version::initialize() {
1493 ResourceMark rm;
1494 // Making this stub must be FIRST use of assembler
1495
1496 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1497 if (stub_blob == NULL) {
1498 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1499 }
1500 CodeBuffer c(stub_blob);
1501 VM_Version_StubGenerator g(&c);
1502 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1503 g.generate_get_cpu_info());
1504
1505 get_processor_features();
1506 }