1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "opto/ad.hpp"
29 #include "opto/addnode.hpp"
30 #include "opto/callnode.hpp"
31 #include "opto/idealGraphPrinter.hpp"
32 #include "opto/matcher.hpp"
33 #include "opto/memnode.hpp"
34 #include "opto/movenode.hpp"
35 #include "opto/opcodes.hpp"
36 #include "opto/regmask.hpp"
37 #include "opto/rootnode.hpp"
38 #include "opto/runtime.hpp"
39 #include "opto/type.hpp"
40 #include "opto/vectornode.hpp"
41 #include "runtime/os.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "utilities/align.hpp"
44 #if INCLUDE_ZGC
45 #include "gc/z/zBarrierSetRuntime.hpp"
46 #endif // INCLUDE_ZGC
47
48 OptoReg::Name OptoReg::c_frame_pointer;
49
50 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
51 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
52 RegMask Matcher::STACK_ONLY_mask;
53 RegMask Matcher::c_frame_ptr_mask;
54 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
55 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
56
57 //---------------------------Matcher-------------------------------------------
58 Matcher::Matcher()
59 : PhaseTransform( Phase::Ins_Select ),
60 _states_arena(Chunk::medium_size, mtCompiler),
61 _visited(&_states_arena),
62 _shared(&_states_arena),
63 _dontcare(&_states_arena),
64 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
65 _swallowed(swallowed),
66 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
67 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
68 _must_clone(must_clone),
69 _shared_nodes(C->comp_arena()),
70 #ifdef ASSERT
71 _old2new_map(C->comp_arena()),
72 _new2old_map(C->comp_arena()),
73 #endif
74 _allocation_started(false),
75 _ruleName(ruleName),
76 _register_save_policy(register_save_policy),
77 _c_reg_save_policy(c_reg_save_policy),
78 _register_save_type(register_save_type) {
79 C->set_matcher(this);
80
81 idealreg2spillmask [Op_RegI] = NULL;
82 idealreg2spillmask [Op_RegN] = NULL;
83 idealreg2spillmask [Op_RegL] = NULL;
84 idealreg2spillmask [Op_RegF] = NULL;
85 idealreg2spillmask [Op_RegD] = NULL;
86 idealreg2spillmask [Op_RegP] = NULL;
87 idealreg2spillmask [Op_VecS] = NULL;
88 idealreg2spillmask [Op_VecD] = NULL;
89 idealreg2spillmask [Op_VecX] = NULL;
90 idealreg2spillmask [Op_VecY] = NULL;
91 idealreg2spillmask [Op_VecZ] = NULL;
92 idealreg2spillmask [Op_RegFlags] = NULL;
93
94 idealreg2debugmask [Op_RegI] = NULL;
95 idealreg2debugmask [Op_RegN] = NULL;
96 idealreg2debugmask [Op_RegL] = NULL;
97 idealreg2debugmask [Op_RegF] = NULL;
98 idealreg2debugmask [Op_RegD] = NULL;
99 idealreg2debugmask [Op_RegP] = NULL;
100 idealreg2debugmask [Op_VecS] = NULL;
101 idealreg2debugmask [Op_VecD] = NULL;
102 idealreg2debugmask [Op_VecX] = NULL;
103 idealreg2debugmask [Op_VecY] = NULL;
104 idealreg2debugmask [Op_VecZ] = NULL;
105 idealreg2debugmask [Op_RegFlags] = NULL;
106
107 idealreg2mhdebugmask[Op_RegI] = NULL;
108 idealreg2mhdebugmask[Op_RegN] = NULL;
109 idealreg2mhdebugmask[Op_RegL] = NULL;
110 idealreg2mhdebugmask[Op_RegF] = NULL;
111 idealreg2mhdebugmask[Op_RegD] = NULL;
112 idealreg2mhdebugmask[Op_RegP] = NULL;
113 idealreg2mhdebugmask[Op_VecS] = NULL;
114 idealreg2mhdebugmask[Op_VecD] = NULL;
115 idealreg2mhdebugmask[Op_VecX] = NULL;
116 idealreg2mhdebugmask[Op_VecY] = NULL;
117 idealreg2mhdebugmask[Op_VecZ] = NULL;
118 idealreg2mhdebugmask[Op_RegFlags] = NULL;
119
120 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
121 }
122
123 //------------------------------warp_incoming_stk_arg------------------------
124 // This warps a VMReg into an OptoReg::Name
125 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
126 OptoReg::Name warped;
127 if( reg->is_stack() ) { // Stack slot argument?
128 warped = OptoReg::add(_old_SP, reg->reg2stack() );
129 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
130 if( warped >= _in_arg_limit )
131 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
132 if (!RegMask::can_represent_arg(warped)) {
133 // the compiler cannot represent this method's calling sequence
134 C->record_method_not_compilable("unsupported incoming calling sequence");
135 return OptoReg::Bad;
136 }
137 return warped;
138 }
139 return OptoReg::as_OptoReg(reg);
140 }
141
142 //---------------------------compute_old_SP------------------------------------
143 OptoReg::Name Compile::compute_old_SP() {
144 int fixed = fixed_slots();
145 int preserve = in_preserve_stack_slots();
146 return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots()));
147 }
148
149
150
151 #ifdef ASSERT
152 void Matcher::verify_new_nodes_only(Node* xroot) {
153 // Make sure that the new graph only references new nodes
154 ResourceMark rm;
155 Unique_Node_List worklist;
156 VectorSet visited(Thread::current()->resource_area());
157 worklist.push(xroot);
158 while (worklist.size() > 0) {
159 Node* n = worklist.pop();
160 visited <<= n->_idx;
161 assert(C->node_arena()->contains(n), "dead node");
162 for (uint j = 0; j < n->req(); j++) {
163 Node* in = n->in(j);
164 if (in != NULL) {
165 assert(C->node_arena()->contains(in), "dead node");
166 if (!visited.test(in->_idx)) {
167 worklist.push(in);
168 }
169 }
170 }
171 }
172 }
173 #endif
174
175 // Array of RegMask, one per returned values (value type instances can
176 // be returned as multiple return values, one per field)
177 RegMask* Matcher::return_values_mask(const TypeTuple *range) {
178 uint cnt = range->cnt() - TypeFunc::Parms;
179 if (cnt == 0) {
180 return NULL;
181 }
182 RegMask* mask = NEW_RESOURCE_ARRAY(RegMask, cnt);
183
184 if (!ValueTypeReturnedAsFields) {
185 // Get ideal-register return type
186 uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
187 // Get machine return register
188 OptoRegPair regs = return_value(ireg, false);
189
190 // And mask for same
191 mask[0].Clear();
192 mask[0].Insert(regs.first());
193 if (OptoReg::is_valid(regs.second())) {
194 mask[0].Insert(regs.second());
195 }
196 } else {
197 BasicType* sig_bt = NEW_RESOURCE_ARRAY(BasicType, cnt);
198 VMRegPair* vm_parm_regs = NEW_RESOURCE_ARRAY(VMRegPair, cnt);
199
200 for (uint i = 0; i < cnt; i++) {
201 sig_bt[i] = range->field_at(i+TypeFunc::Parms)->basic_type();
202 }
203
204 int regs = SharedRuntime::java_return_convention(sig_bt, vm_parm_regs, cnt);
205 assert(regs > 0, "should have been tested during graph construction");
206 for (uint i = 0; i < cnt; i++) {
207 mask[i].Clear();
208
209 OptoReg::Name reg1 = OptoReg::as_OptoReg(vm_parm_regs[i].first());
210 if (OptoReg::is_valid(reg1)) {
211 mask[i].Insert(reg1);
212 }
213 OptoReg::Name reg2 = OptoReg::as_OptoReg(vm_parm_regs[i].second());
214 if (OptoReg::is_valid(reg2)) {
215 mask[i].Insert(reg2);
216 }
217 }
218 }
219 return mask;
220 }
221
222 //---------------------------match---------------------------------------------
223 void Matcher::match( ) {
224 if( MaxLabelRootDepth < 100 ) { // Too small?
225 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
226 MaxLabelRootDepth = 100;
227 }
228 // One-time initialization of some register masks.
229 init_spill_mask( C->root()->in(1) );
230 _return_addr_mask = return_addr();
231 #ifdef _LP64
232 // Pointers take 2 slots in 64-bit land
233 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
234 #endif
235
236 // Map Java-signature return types into return register-value
237 // machine registers.
238 const TypeTuple *range = C->tf()->range_cc();
239 _return_values_mask = return_values_mask(range);
240
241 // ---------------
242 // Frame Layout
243
244 // Need the method signature to determine the incoming argument types,
245 // because the types determine which registers the incoming arguments are
246 // in, and this affects the matched code.
247 const TypeTuple *domain = C->tf()->domain_cc();
248 uint argcnt = domain->cnt() - TypeFunc::Parms;
249 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
250 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
251 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
252 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
253 uint i;
254 for( i = 0; i<argcnt; i++ ) {
255 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
256 }
257
258 // Pass array of ideal registers and length to USER code (from the AD file)
259 // that will convert this to an array of register numbers.
260 const StartNode *start = C->start();
261 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
262 #ifdef ASSERT
263 // Sanity check users' calling convention. Real handy while trying to
264 // get the initial port correct.
265 { for (uint i = 0; i<argcnt; i++) {
266 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
267 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
268 _parm_regs[i].set_bad();
269 continue;
270 }
271 VMReg parm_reg = vm_parm_regs[i].first();
272 assert(parm_reg->is_valid(), "invalid arg?");
273 if (parm_reg->is_reg()) {
274 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
275 assert(can_be_java_arg(opto_parm_reg) ||
276 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
277 opto_parm_reg == inline_cache_reg(),
278 "parameters in register must be preserved by runtime stubs");
279 }
280 for (uint j = 0; j < i; j++) {
281 assert(parm_reg != vm_parm_regs[j].first(),
282 "calling conv. must produce distinct regs");
283 }
284 }
285 }
286 #endif
287
288 // Do some initial frame layout.
289
290 // Compute the old incoming SP (may be called FP) as
291 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
292 _old_SP = C->compute_old_SP();
293 assert( is_even(_old_SP), "must be even" );
294
295 // Compute highest incoming stack argument as
296 // _old_SP + out_preserve_stack_slots + incoming argument size.
297 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
298 assert( is_even(_in_arg_limit), "out_preserve must be even" );
299 for( i = 0; i < argcnt; i++ ) {
300 // Permit args to have no register
301 _calling_convention_mask[i].Clear();
302 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
303 continue;
304 }
305 // calling_convention returns stack arguments as a count of
306 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
307 // the allocators point of view, taking into account all the
308 // preserve area, locks & pad2.
309
310 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
311 if( OptoReg::is_valid(reg1))
312 _calling_convention_mask[i].Insert(reg1);
313
314 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
315 if( OptoReg::is_valid(reg2))
316 _calling_convention_mask[i].Insert(reg2);
317
318 // Saved biased stack-slot register number
319 _parm_regs[i].set_pair(reg2, reg1);
320 }
321
322 // Finally, make sure the incoming arguments take up an even number of
323 // words, in case the arguments or locals need to contain doubleword stack
324 // slots. The rest of the system assumes that stack slot pairs (in
325 // particular, in the spill area) which look aligned will in fact be
326 // aligned relative to the stack pointer in the target machine. Double
327 // stack slots will always be allocated aligned.
328 _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong));
329
330 // Compute highest outgoing stack argument as
331 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
332 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
333 assert( is_even(_out_arg_limit), "out_preserve must be even" );
334
335 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
336 // the compiler cannot represent this method's calling sequence
337 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
338 }
339
340 if (C->failing()) return; // bailed out on incoming arg failure
341
342 // ---------------
343 // Collect roots of matcher trees. Every node for which
344 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
345 // can be a valid interior of some tree.
346 find_shared( C->root() );
347 find_shared( C->top() );
348
349 C->print_method(PHASE_BEFORE_MATCHING);
350
351 // Create new ideal node ConP #NULL even if it does exist in old space
352 // to avoid false sharing if the corresponding mach node is not used.
353 // The corresponding mach node is only used in rare cases for derived
354 // pointers.
355 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
356
357 // Swap out to old-space; emptying new-space
358 Arena *old = C->node_arena()->move_contents(C->old_arena());
359
360 // Save debug and profile information for nodes in old space:
361 _old_node_note_array = C->node_note_array();
362 if (_old_node_note_array != NULL) {
363 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
364 (C->comp_arena(), _old_node_note_array->length(),
365 0, NULL));
366 }
367
368 // Pre-size the new_node table to avoid the need for range checks.
369 grow_new_node_array(C->unique());
370
371 // Reset node counter so MachNodes start with _idx at 0
372 int live_nodes = C->live_nodes();
373 C->set_unique(0);
374 C->reset_dead_node_list();
375
376 // Recursively match trees from old space into new space.
377 // Correct leaves of new-space Nodes; they point to old-space.
378 _visited.Clear(); // Clear visit bits for xform call
379 C->set_cached_top_node(xform( C->top(), live_nodes ));
380 if (!C->failing()) {
381 Node* xroot = xform( C->root(), 1 );
382 if (xroot == NULL) {
383 Matcher::soft_match_failure(); // recursive matching process failed
384 C->record_method_not_compilable("instruction match failed");
385 } else {
386 // During matching shared constants were attached to C->root()
387 // because xroot wasn't available yet, so transfer the uses to
388 // the xroot.
389 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
390 Node* n = C->root()->fast_out(j);
391 if (C->node_arena()->contains(n)) {
392 assert(n->in(0) == C->root(), "should be control user");
393 n->set_req(0, xroot);
394 --j;
395 --jmax;
396 }
397 }
398
399 // Generate new mach node for ConP #NULL
400 assert(new_ideal_null != NULL, "sanity");
401 _mach_null = match_tree(new_ideal_null);
402 // Don't set control, it will confuse GCM since there are no uses.
403 // The control will be set when this node is used first time
404 // in find_base_for_derived().
405 assert(_mach_null != NULL, "");
406
407 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
408
409 #ifdef ASSERT
410 verify_new_nodes_only(xroot);
411 #endif
412 }
413 }
414 if (C->top() == NULL || C->root() == NULL) {
415 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
416 }
417 if (C->failing()) {
418 // delete old;
419 old->destruct_contents();
420 return;
421 }
422 assert( C->top(), "" );
423 assert( C->root(), "" );
424 validate_null_checks();
425
426 // Now smoke old-space
427 NOT_DEBUG( old->destruct_contents() );
428
429 // ------------------------
430 // Set up save-on-entry registers
431 Fixup_Save_On_Entry( );
432 }
433
434
435 //------------------------------Fixup_Save_On_Entry----------------------------
436 // The stated purpose of this routine is to take care of save-on-entry
437 // registers. However, the overall goal of the Match phase is to convert into
438 // machine-specific instructions which have RegMasks to guide allocation.
439 // So what this procedure really does is put a valid RegMask on each input
440 // to the machine-specific variations of all Return, TailCall and Halt
441 // instructions. It also adds edgs to define the save-on-entry values (and of
442 // course gives them a mask).
443
444 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
445 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
446 // Do all the pre-defined register masks
447 rms[TypeFunc::Control ] = RegMask::Empty;
448 rms[TypeFunc::I_O ] = RegMask::Empty;
449 rms[TypeFunc::Memory ] = RegMask::Empty;
450 rms[TypeFunc::ReturnAdr] = ret_adr;
451 rms[TypeFunc::FramePtr ] = fp;
452 return rms;
453 }
454
455 //---------------------------init_first_stack_mask-----------------------------
456 // Create the initial stack mask used by values spilling to the stack.
457 // Disallow any debug info in outgoing argument areas by setting the
458 // initial mask accordingly.
459 void Matcher::init_first_stack_mask() {
460
461 // Allocate storage for spill masks as masks for the appropriate load type.
462 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5));
463
464 idealreg2spillmask [Op_RegN] = &rms[0];
465 idealreg2spillmask [Op_RegI] = &rms[1];
466 idealreg2spillmask [Op_RegL] = &rms[2];
467 idealreg2spillmask [Op_RegF] = &rms[3];
468 idealreg2spillmask [Op_RegD] = &rms[4];
469 idealreg2spillmask [Op_RegP] = &rms[5];
470
471 idealreg2debugmask [Op_RegN] = &rms[6];
472 idealreg2debugmask [Op_RegI] = &rms[7];
473 idealreg2debugmask [Op_RegL] = &rms[8];
474 idealreg2debugmask [Op_RegF] = &rms[9];
475 idealreg2debugmask [Op_RegD] = &rms[10];
476 idealreg2debugmask [Op_RegP] = &rms[11];
477
478 idealreg2mhdebugmask[Op_RegN] = &rms[12];
479 idealreg2mhdebugmask[Op_RegI] = &rms[13];
480 idealreg2mhdebugmask[Op_RegL] = &rms[14];
481 idealreg2mhdebugmask[Op_RegF] = &rms[15];
482 idealreg2mhdebugmask[Op_RegD] = &rms[16];
483 idealreg2mhdebugmask[Op_RegP] = &rms[17];
484
485 idealreg2spillmask [Op_VecS] = &rms[18];
486 idealreg2spillmask [Op_VecD] = &rms[19];
487 idealreg2spillmask [Op_VecX] = &rms[20];
488 idealreg2spillmask [Op_VecY] = &rms[21];
489 idealreg2spillmask [Op_VecZ] = &rms[22];
490
491 OptoReg::Name i;
492
493 // At first, start with the empty mask
494 C->FIRST_STACK_mask().Clear();
495
496 // Check if method has a reserved entry in the argument stack area that
497 // should not be used for spilling because it holds the return address.
498 OptoRegPair res_entry;
499 if (C->needs_stack_repair()) {
500 int res_idx = C->get_res_entry()._offset;
501 res_entry = _parm_regs[res_idx];
502 }
503
504 // Add in the incoming argument area
505 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
506 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
507 if (i == res_entry.first() || i == res_entry.second()) {
508 continue; // Skip reserved slot to avoid spilling
509 }
510 C->FIRST_STACK_mask().Insert(i);
511 }
512 // Add in all bits past the outgoing argument area
513 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
514 "must be able to represent all call arguments in reg mask");
515 OptoReg::Name init = _out_arg_limit;
516 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
517 C->FIRST_STACK_mask().Insert(i);
518 }
519 // Finally, set the "infinite stack" bit.
520 C->FIRST_STACK_mask().set_AllStack();
521
522 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
523 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
524 // Keep spill masks aligned.
525 aligned_stack_mask.clear_to_pairs();
526 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
527
528 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
529 #ifdef _LP64
530 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
531 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
532 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
533 #else
534 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
535 #endif
536 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
537 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
538 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
539 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
540 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
541 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
542 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
543 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
544
545 if (Matcher::vector_size_supported(T_BYTE,4)) {
546 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
547 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
548 }
549 if (Matcher::vector_size_supported(T_FLOAT,2)) {
550 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
551 // RA guarantees such alignment since it is needed for Double and Long values.
552 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
553 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
554 }
555 if (Matcher::vector_size_supported(T_FLOAT,4)) {
556 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
557 //
558 // RA can use input arguments stack slots for spills but until RA
559 // we don't know frame size and offset of input arg stack slots.
560 //
561 // Exclude last input arg stack slots to avoid spilling vectors there
562 // otherwise vector spills could stomp over stack slots in caller frame.
563 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
564 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
565 aligned_stack_mask.Remove(in);
566 in = OptoReg::add(in, -1);
567 }
568 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
569 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
570 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
571 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
572 }
573 if (Matcher::vector_size_supported(T_FLOAT,8)) {
574 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
575 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
576 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
577 aligned_stack_mask.Remove(in);
578 in = OptoReg::add(in, -1);
579 }
580 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
581 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
582 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
583 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
584 }
585 if (Matcher::vector_size_supported(T_FLOAT,16)) {
586 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
587 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
588 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
589 aligned_stack_mask.Remove(in);
590 in = OptoReg::add(in, -1);
591 }
592 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
593 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
594 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
595 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
596 }
597 if (UseFPUForSpilling) {
598 // This mask logic assumes that the spill operations are
599 // symmetric and that the registers involved are the same size.
600 // On sparc for instance we may have to use 64 bit moves will
601 // kill 2 registers when used with F0-F31.
602 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
603 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
604 #ifdef _LP64
605 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
606 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
607 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
608 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
609 #else
610 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
611 #ifdef ARM
612 // ARM has support for moving 64bit values between a pair of
613 // integer registers and a double register
614 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
615 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
616 #endif
617 #endif
618 }
619
620 // Make up debug masks. Any spill slot plus callee-save registers.
621 // Caller-save registers are assumed to be trashable by the various
622 // inline-cache fixup routines.
623 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
624 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
625 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
626 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
627 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
628 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
629
630 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
631 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
632 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
633 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
634 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
635 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
636
637 // Prevent stub compilations from attempting to reference
638 // callee-saved registers from debug info
639 bool exclude_soe = !Compile::current()->is_method_compilation();
640
641 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
642 // registers the caller has to save do not work
643 if( _register_save_policy[i] == 'C' ||
644 _register_save_policy[i] == 'A' ||
645 (_register_save_policy[i] == 'E' && exclude_soe) ) {
646 idealreg2debugmask [Op_RegN]->Remove(i);
647 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
648 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
649 idealreg2debugmask [Op_RegF]->Remove(i); // masks
650 idealreg2debugmask [Op_RegD]->Remove(i);
651 idealreg2debugmask [Op_RegP]->Remove(i);
652
653 idealreg2mhdebugmask[Op_RegN]->Remove(i);
654 idealreg2mhdebugmask[Op_RegI]->Remove(i);
655 idealreg2mhdebugmask[Op_RegL]->Remove(i);
656 idealreg2mhdebugmask[Op_RegF]->Remove(i);
657 idealreg2mhdebugmask[Op_RegD]->Remove(i);
658 idealreg2mhdebugmask[Op_RegP]->Remove(i);
659 }
660 }
661
662 // Subtract the register we use to save the SP for MethodHandle
663 // invokes to from the debug mask.
664 const RegMask save_mask = method_handle_invoke_SP_save_mask();
665 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
666 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
667 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
668 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
669 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
670 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
671 }
672
673 //---------------------------is_save_on_entry----------------------------------
674 bool Matcher::is_save_on_entry( int reg ) {
675 return
676 _register_save_policy[reg] == 'E' ||
677 _register_save_policy[reg] == 'A' || // Save-on-entry register?
678 // Also save argument registers in the trampolining stubs
679 (C->save_argument_registers() && is_spillable_arg(reg));
680 }
681
682 //---------------------------Fixup_Save_On_Entry-------------------------------
683 void Matcher::Fixup_Save_On_Entry( ) {
684 init_first_stack_mask();
685
686 Node *root = C->root(); // Short name for root
687 // Count number of save-on-entry registers.
688 uint soe_cnt = number_of_saved_registers();
689 uint i;
690
691 // Find the procedure Start Node
692 StartNode *start = C->start();
693 assert( start, "Expect a start node" );
694
695 // Save argument registers in the trampolining stubs
696 if( C->save_argument_registers() )
697 for( i = 0; i < _last_Mach_Reg; i++ )
698 if( is_spillable_arg(i) )
699 soe_cnt++;
700
701 // Input RegMask array shared by all Returns.
702 // The type for doubles and longs has a count of 2, but
703 // there is only 1 returned value
704 uint ret_edge_cnt = C->tf()->range_cc()->cnt();
705 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
706 for (i = TypeFunc::Parms; i < ret_edge_cnt; i++) {
707 ret_rms[i] = _return_values_mask[i-TypeFunc::Parms];
708 }
709
710 // Input RegMask array shared by all Rethrows.
711 uint reth_edge_cnt = TypeFunc::Parms+1;
712 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
713 // Rethrow takes exception oop only, but in the argument 0 slot.
714 OptoReg::Name reg = find_receiver(false);
715 if (reg >= 0) {
716 reth_rms[TypeFunc::Parms] = mreg2regmask[reg];
717 #ifdef _LP64
718 // Need two slots for ptrs in 64-bit land
719 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
720 #endif
721 }
722
723 // Input RegMask array shared by all TailCalls
724 uint tail_call_edge_cnt = TypeFunc::Parms+2;
725 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
726
727 // Input RegMask array shared by all TailJumps
728 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
729 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
730
731 // TailCalls have 2 returned values (target & moop), whose masks come
732 // from the usual MachNode/MachOper mechanism. Find a sample
733 // TailCall to extract these masks and put the correct masks into
734 // the tail_call_rms array.
735 for( i=1; i < root->req(); i++ ) {
736 MachReturnNode *m = root->in(i)->as_MachReturn();
737 if( m->ideal_Opcode() == Op_TailCall ) {
738 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
739 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
740 break;
741 }
742 }
743
744 // TailJumps have 2 returned values (target & ex_oop), whose masks come
745 // from the usual MachNode/MachOper mechanism. Find a sample
746 // TailJump to extract these masks and put the correct masks into
747 // the tail_jump_rms array.
748 for( i=1; i < root->req(); i++ ) {
749 MachReturnNode *m = root->in(i)->as_MachReturn();
750 if( m->ideal_Opcode() == Op_TailJump ) {
751 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
752 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
753 break;
754 }
755 }
756
757 // Input RegMask array shared by all Halts
758 uint halt_edge_cnt = TypeFunc::Parms;
759 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
760
761 // Capture the return input masks into each exit flavor
762 for( i=1; i < root->req(); i++ ) {
763 MachReturnNode *exit = root->in(i)->as_MachReturn();
764 switch( exit->ideal_Opcode() ) {
765 case Op_Return : exit->_in_rms = ret_rms; break;
766 case Op_Rethrow : exit->_in_rms = reth_rms; break;
767 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
768 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
769 case Op_Halt : exit->_in_rms = halt_rms; break;
770 default : ShouldNotReachHere();
771 }
772 }
773
774 // Next unused projection number from Start.
775 int proj_cnt = C->tf()->domain_cc()->cnt();
776
777 // Do all the save-on-entry registers. Make projections from Start for
778 // them, and give them a use at the exit points. To the allocator, they
779 // look like incoming register arguments.
780 for( i = 0; i < _last_Mach_Reg; i++ ) {
781 if( is_save_on_entry(i) ) {
782
783 // Add the save-on-entry to the mask array
784 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
785 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
786 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
787 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
788 // Halts need the SOE registers, but only in the stack as debug info.
789 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
790 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
791
792 Node *mproj;
793
794 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
795 // into a single RegD.
796 if( (i&1) == 0 &&
797 _register_save_type[i ] == Op_RegF &&
798 _register_save_type[i+1] == Op_RegF &&
799 is_save_on_entry(i+1) ) {
800 // Add other bit for double
801 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
802 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
803 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
804 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
805 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
806 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
807 proj_cnt += 2; // Skip 2 for doubles
808 }
809 else if( (i&1) == 1 && // Else check for high half of double
810 _register_save_type[i-1] == Op_RegF &&
811 _register_save_type[i ] == Op_RegF &&
812 is_save_on_entry(i-1) ) {
813 ret_rms [ ret_edge_cnt] = RegMask::Empty;
814 reth_rms [ reth_edge_cnt] = RegMask::Empty;
815 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
816 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
817 halt_rms [ halt_edge_cnt] = RegMask::Empty;
818 mproj = C->top();
819 }
820 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
821 // into a single RegL.
822 else if( (i&1) == 0 &&
823 _register_save_type[i ] == Op_RegI &&
824 _register_save_type[i+1] == Op_RegI &&
825 is_save_on_entry(i+1) ) {
826 // Add other bit for long
827 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
828 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
829 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
830 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
831 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
832 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
833 proj_cnt += 2; // Skip 2 for longs
834 }
835 else if( (i&1) == 1 && // Else check for high half of long
836 _register_save_type[i-1] == Op_RegI &&
837 _register_save_type[i ] == Op_RegI &&
838 is_save_on_entry(i-1) ) {
839 ret_rms [ ret_edge_cnt] = RegMask::Empty;
840 reth_rms [ reth_edge_cnt] = RegMask::Empty;
841 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
842 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
843 halt_rms [ halt_edge_cnt] = RegMask::Empty;
844 mproj = C->top();
845 } else {
846 // Make a projection for it off the Start
847 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
848 }
849
850 ret_edge_cnt ++;
851 reth_edge_cnt ++;
852 tail_call_edge_cnt ++;
853 tail_jump_edge_cnt ++;
854 halt_edge_cnt ++;
855
856 // Add a use of the SOE register to all exit paths
857 for( uint j=1; j < root->req(); j++ )
858 root->in(j)->add_req(mproj);
859 } // End of if a save-on-entry register
860 } // End of for all machine registers
861 }
862
863 //------------------------------init_spill_mask--------------------------------
864 void Matcher::init_spill_mask( Node *ret ) {
865 if( idealreg2regmask[Op_RegI] ) return; // One time only init
866
867 OptoReg::c_frame_pointer = c_frame_pointer();
868 c_frame_ptr_mask = c_frame_pointer();
869 #ifdef _LP64
870 // pointers are twice as big
871 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
872 #endif
873
874 // Start at OptoReg::stack0()
875 STACK_ONLY_mask.Clear();
876 OptoReg::Name init = OptoReg::stack2reg(0);
877 // STACK_ONLY_mask is all stack bits
878 OptoReg::Name i;
879 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
880 STACK_ONLY_mask.Insert(i);
881 // Also set the "infinite stack" bit.
882 STACK_ONLY_mask.set_AllStack();
883
884 // Copy the register names over into the shared world
885 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
886 // SharedInfo::regName[i] = regName[i];
887 // Handy RegMasks per machine register
888 mreg2regmask[i].Insert(i);
889 }
890
891 // Grab the Frame Pointer
892 Node *fp = ret->in(TypeFunc::FramePtr);
893 Node *mem = ret->in(TypeFunc::Memory);
894 const TypePtr* atp = TypePtr::BOTTOM;
895 // Share frame pointer while making spill ops
896 set_shared(fp);
897
898 // Compute generic short-offset Loads
899 #ifdef _LP64
900 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
901 #endif
902 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
903 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false));
904 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
905 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
906 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
907 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
908 spillD != NULL && spillP != NULL, "");
909 // Get the ADLC notion of the right regmask, for each basic type.
910 #ifdef _LP64
911 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
912 #endif
913 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
914 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
915 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
916 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
917 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
918
919 // Vector regmasks.
920 if (Matcher::vector_size_supported(T_BYTE,4)) {
921 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
922 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
923 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
924 }
925 if (Matcher::vector_size_supported(T_FLOAT,2)) {
926 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
927 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
928 }
929 if (Matcher::vector_size_supported(T_FLOAT,4)) {
930 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
931 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
932 }
933 if (Matcher::vector_size_supported(T_FLOAT,8)) {
934 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
935 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
936 }
937 if (Matcher::vector_size_supported(T_FLOAT,16)) {
938 MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ));
939 idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask();
940 }
941 }
942
943 #ifdef ASSERT
944 static void match_alias_type(Compile* C, Node* n, Node* m) {
945 if (!VerifyAliases) return; // do not go looking for trouble by default
946 const TypePtr* nat = n->adr_type();
947 const TypePtr* mat = m->adr_type();
948 int nidx = C->get_alias_index(nat);
949 int midx = C->get_alias_index(mat);
950 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
951 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
952 for (uint i = 1; i < n->req(); i++) {
953 Node* n1 = n->in(i);
954 const TypePtr* n1at = n1->adr_type();
955 if (n1at != NULL) {
956 nat = n1at;
957 nidx = C->get_alias_index(n1at);
958 }
959 }
960 }
961 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
962 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
963 switch (n->Opcode()) {
964 case Op_PrefetchAllocation:
965 nidx = Compile::AliasIdxRaw;
966 nat = TypeRawPtr::BOTTOM;
967 break;
968 }
969 }
970 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
971 switch (n->Opcode()) {
972 case Op_ClearArray:
973 midx = Compile::AliasIdxRaw;
974 mat = TypeRawPtr::BOTTOM;
975 break;
976 }
977 }
978 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
979 switch (n->Opcode()) {
980 case Op_Return:
981 case Op_Rethrow:
982 case Op_Halt:
983 case Op_TailCall:
984 case Op_TailJump:
985 nidx = Compile::AliasIdxBot;
986 nat = TypePtr::BOTTOM;
987 break;
988 }
989 }
990 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
991 switch (n->Opcode()) {
992 case Op_StrComp:
993 case Op_StrEquals:
994 case Op_StrIndexOf:
995 case Op_StrIndexOfChar:
996 case Op_AryEq:
997 case Op_HasNegatives:
998 case Op_MemBarVolatile:
999 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
1000 case Op_StrInflatedCopy:
1001 case Op_StrCompressedCopy:
1002 case Op_OnSpinWait:
1003 case Op_EncodeISOArray:
1004 nidx = Compile::AliasIdxTop;
1005 nat = NULL;
1006 break;
1007 }
1008 }
1009 if (nidx != midx) {
1010 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
1011 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
1012 n->dump();
1013 m->dump();
1014 }
1015 assert(C->subsume_loads() && C->must_alias(nat, midx),
1016 "must not lose alias info when matching");
1017 }
1018 }
1019 #endif
1020
1021 //------------------------------xform------------------------------------------
1022 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
1023 // Node in new-space. Given a new-space Node, recursively walk his children.
1024 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1025 Node *Matcher::xform( Node *n, int max_stack ) {
1026 // Use one stack to keep both: child's node/state and parent's node/index
1027 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1028 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
1029 while (mstack.is_nonempty()) {
1030 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1031 if (C->failing()) return NULL;
1032 n = mstack.node(); // Leave node on stack
1033 Node_State nstate = mstack.state();
1034 if (nstate == Visit) {
1035 mstack.set_state(Post_Visit);
1036 Node *oldn = n;
1037 // Old-space or new-space check
1038 if (!C->node_arena()->contains(n)) {
1039 // Old space!
1040 Node* m;
1041 if (has_new_node(n)) { // Not yet Label/Reduced
1042 m = new_node(n);
1043 } else {
1044 if (!is_dontcare(n)) { // Matcher can match this guy
1045 // Calls match special. They match alone with no children.
1046 // Their children, the incoming arguments, match normally.
1047 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1048 if (C->failing()) return NULL;
1049 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1050 if (n->is_MemBar()) {
1051 m->as_MachMemBar()->set_adr_type(n->adr_type());
1052 }
1053 } else { // Nothing the matcher cares about
1054 if (n->is_Proj() && n->in(0) != NULL && n->in(0)->is_Multi()) { // Projections?
1055 // Convert to machine-dependent projection
1056 RegMask* mask = NULL;
1057 if (n->in(0)->is_Call()) {
1058 mask = return_values_mask(n->in(0)->as_Call()->tf()->range_cc());
1059 }
1060 m = n->in(0)->as_Multi()->match(n->as_Proj(), this, mask);
1061 #ifdef ASSERT
1062 _new2old_map.map(m->_idx, n);
1063 #endif
1064 if (m->in(0) != NULL) // m might be top
1065 collect_null_checks(m, n);
1066 } else { // Else just a regular 'ol guy
1067 m = n->clone(); // So just clone into new-space
1068 #ifdef ASSERT
1069 _new2old_map.map(m->_idx, n);
1070 #endif
1071 // Def-Use edges will be added incrementally as Uses
1072 // of this node are matched.
1073 assert(m->outcnt() == 0, "no Uses of this clone yet");
1074 }
1075 }
1076
1077 set_new_node(n, m); // Map old to new
1078 if (_old_node_note_array != NULL) {
1079 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1080 n->_idx);
1081 C->set_node_notes_at(m->_idx, nn);
1082 }
1083 debug_only(match_alias_type(C, n, m));
1084 }
1085 n = m; // n is now a new-space node
1086 mstack.set_node(n);
1087 }
1088
1089 // New space!
1090 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1091
1092 int i;
1093 // Put precedence edges on stack first (match them last).
1094 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1095 Node *m = oldn->in(i);
1096 if (m == NULL) break;
1097 // set -1 to call add_prec() instead of set_req() during Step1
1098 mstack.push(m, Visit, n, -1);
1099 }
1100
1101 // Handle precedence edges for interior nodes
1102 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1103 Node *m = n->in(i);
1104 if (m == NULL || C->node_arena()->contains(m)) continue;
1105 n->rm_prec(i);
1106 // set -1 to call add_prec() instead of set_req() during Step1
1107 mstack.push(m, Visit, n, -1);
1108 }
1109
1110 // For constant debug info, I'd rather have unmatched constants.
1111 int cnt = n->req();
1112 JVMState* jvms = n->jvms();
1113 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1114
1115 // Now do only debug info. Clone constants rather than matching.
1116 // Constants are represented directly in the debug info without
1117 // the need for executable machine instructions.
1118 // Monitor boxes are also represented directly.
1119 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1120 Node *m = n->in(i); // Get input
1121 int op = m->Opcode();
1122 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1123 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1124 op == Op_ConF || op == Op_ConD || op == Op_ConL
1125 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1126 ) {
1127 m = m->clone();
1128 #ifdef ASSERT
1129 _new2old_map.map(m->_idx, n);
1130 #endif
1131 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1132 mstack.push(m->in(0), Visit, m, 0);
1133 } else {
1134 mstack.push(m, Visit, n, i);
1135 }
1136 }
1137
1138 // And now walk his children, and convert his inputs to new-space.
1139 for( ; i >= 0; --i ) { // For all normal inputs do
1140 Node *m = n->in(i); // Get input
1141 if(m != NULL)
1142 mstack.push(m, Visit, n, i);
1143 }
1144
1145 }
1146 else if (nstate == Post_Visit) {
1147 // Set xformed input
1148 Node *p = mstack.parent();
1149 if (p != NULL) { // root doesn't have parent
1150 int i = (int)mstack.index();
1151 if (i >= 0)
1152 p->set_req(i, n); // required input
1153 else if (i == -1)
1154 p->add_prec(n); // precedence input
1155 else
1156 ShouldNotReachHere();
1157 }
1158 mstack.pop(); // remove processed node from stack
1159 }
1160 else {
1161 ShouldNotReachHere();
1162 }
1163 } // while (mstack.is_nonempty())
1164 return n; // Return new-space Node
1165 }
1166
1167 //------------------------------warp_outgoing_stk_arg------------------------
1168 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1169 // Convert outgoing argument location to a pre-biased stack offset
1170 if (reg->is_stack()) {
1171 OptoReg::Name warped = reg->reg2stack();
1172 // Adjust the stack slot offset to be the register number used
1173 // by the allocator.
1174 warped = OptoReg::add(begin_out_arg_area, warped);
1175 // Keep track of the largest numbered stack slot used for an arg.
1176 // Largest used slot per call-site indicates the amount of stack
1177 // that is killed by the call.
1178 if( warped >= out_arg_limit_per_call )
1179 out_arg_limit_per_call = OptoReg::add(warped,1);
1180 if (!RegMask::can_represent_arg(warped)) {
1181 C->record_method_not_compilable("unsupported calling sequence");
1182 return OptoReg::Bad;
1183 }
1184 return warped;
1185 }
1186 return OptoReg::as_OptoReg(reg);
1187 }
1188
1189
1190 //------------------------------match_sfpt-------------------------------------
1191 // Helper function to match call instructions. Calls match special.
1192 // They match alone with no children. Their children, the incoming
1193 // arguments, match normally.
1194 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1195 MachSafePointNode *msfpt = NULL;
1196 MachCallNode *mcall = NULL;
1197 uint cnt;
1198 // Split out case for SafePoint vs Call
1199 CallNode *call;
1200 const TypeTuple *domain;
1201 ciMethod* method = NULL;
1202 bool is_method_handle_invoke = false; // for special kill effects
1203 if( sfpt->is_Call() ) {
1204 call = sfpt->as_Call();
1205 domain = call->tf()->domain_cc();
1206 cnt = domain->cnt();
1207
1208 // Match just the call, nothing else
1209 MachNode *m = match_tree(call);
1210 if (C->failing()) return NULL;
1211 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1212
1213 // Copy data from the Ideal SafePoint to the machine version
1214 mcall = m->as_MachCall();
1215
1216 mcall->set_tf( call->tf());
1217 mcall->set_entry_point(call->entry_point());
1218 mcall->set_cnt( call->cnt());
1219
1220 if( mcall->is_MachCallJava() ) {
1221 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1222 const CallJavaNode *call_java = call->as_CallJava();
1223 method = call_java->method();
1224 mcall_java->_method = method;
1225 mcall_java->_bci = call_java->_bci;
1226 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1227 is_method_handle_invoke = call_java->is_method_handle_invoke();
1228 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1229 mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1230 if (is_method_handle_invoke) {
1231 C->set_has_method_handle_invokes(true);
1232 }
1233 if( mcall_java->is_MachCallStaticJava() )
1234 mcall_java->as_MachCallStaticJava()->_name =
1235 call_java->as_CallStaticJava()->_name;
1236 if( mcall_java->is_MachCallDynamicJava() )
1237 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1238 call_java->as_CallDynamicJava()->_vtable_index;
1239 }
1240 else if( mcall->is_MachCallRuntime() ) {
1241 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1242 }
1243 msfpt = mcall;
1244 }
1245 // This is a non-call safepoint
1246 else {
1247 call = NULL;
1248 domain = NULL;
1249 MachNode *mn = match_tree(sfpt);
1250 if (C->failing()) return NULL;
1251 msfpt = mn->as_MachSafePoint();
1252 cnt = TypeFunc::Parms;
1253 }
1254
1255 // Advertise the correct memory effects (for anti-dependence computation).
1256 msfpt->set_adr_type(sfpt->adr_type());
1257
1258 // Allocate a private array of RegMasks. These RegMasks are not shared.
1259 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1260 // Empty them all.
1261 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1262
1263 // Do all the pre-defined non-Empty register masks
1264 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1265 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1266
1267 // Place first outgoing argument can possibly be put.
1268 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1269 assert( is_even(begin_out_arg_area), "" );
1270 // Compute max outgoing register number per call site.
1271 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1272 // Calls to C may hammer extra stack slots above and beyond any arguments.
1273 // These are usually backing store for register arguments for varargs.
1274 if( call != NULL && call->is_CallRuntime() )
1275 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1276
1277
1278 // Do the normal argument list (parameters) register masks
1279 // Null entry point is a special cast where the target of the call
1280 // is in a register.
1281 int adj = (call != NULL && call->entry_point() == NULL) ? 1 : 0;
1282 int argcnt = cnt - TypeFunc::Parms - adj;
1283 if( argcnt > 0 ) { // Skip it all if we have no args
1284 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1285 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1286 int i;
1287 for( i = 0; i < argcnt; i++ ) {
1288 sig_bt[i] = domain->field_at(i+TypeFunc::Parms+adj)->basic_type();
1289 }
1290 // V-call to pick proper calling convention
1291 call->calling_convention( sig_bt, parm_regs, argcnt );
1292
1293 #ifdef ASSERT
1294 // Sanity check users' calling convention. Really handy during
1295 // the initial porting effort. Fairly expensive otherwise.
1296 { for (int i = 0; i<argcnt; i++) {
1297 if( !parm_regs[i].first()->is_valid() &&
1298 !parm_regs[i].second()->is_valid() ) continue;
1299 VMReg reg1 = parm_regs[i].first();
1300 VMReg reg2 = parm_regs[i].second();
1301 for (int j = 0; j < i; j++) {
1302 if( !parm_regs[j].first()->is_valid() &&
1303 !parm_regs[j].second()->is_valid() ) continue;
1304 VMReg reg3 = parm_regs[j].first();
1305 VMReg reg4 = parm_regs[j].second();
1306 if( !reg1->is_valid() ) {
1307 assert( !reg2->is_valid(), "valid halvsies" );
1308 } else if( !reg3->is_valid() ) {
1309 assert( !reg4->is_valid(), "valid halvsies" );
1310 } else {
1311 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1312 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1313 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1314 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1315 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1316 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1317 }
1318 }
1319 }
1320 }
1321 #endif
1322
1323 // Visit each argument. Compute its outgoing register mask.
1324 // Return results now can have 2 bits returned.
1325 // Compute max over all outgoing arguments both per call-site
1326 // and over the entire method.
1327 for( i = 0; i < argcnt; i++ ) {
1328 // Address of incoming argument mask to fill in
1329 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms+adj];
1330 if( !parm_regs[i].first()->is_valid() &&
1331 !parm_regs[i].second()->is_valid() ) {
1332 continue; // Avoid Halves
1333 }
1334 // Grab first register, adjust stack slots and insert in mask.
1335 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1336 if (OptoReg::is_valid(reg1)) {
1337 rm->Insert( reg1 );
1338 }
1339 // Grab second register (if any), adjust stack slots and insert in mask.
1340 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1341 if (OptoReg::is_valid(reg2)) {
1342 rm->Insert( reg2 );
1343 }
1344 } // End of for all arguments
1345
1346 // Compute number of stack slots needed to restore stack in case of
1347 // Pascal-style argument popping.
1348 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1349 }
1350
1351 // Compute the max stack slot killed by any call. These will not be
1352 // available for debug info, and will be used to adjust FIRST_STACK_mask
1353 // after all call sites have been visited.
1354 if( _out_arg_limit < out_arg_limit_per_call)
1355 _out_arg_limit = out_arg_limit_per_call;
1356
1357 if (mcall) {
1358 // Kill the outgoing argument area, including any non-argument holes and
1359 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1360 // Since the max-per-method covers the max-per-call-site and debug info
1361 // is excluded on the max-per-method basis, debug info cannot land in
1362 // this killed area.
1363 uint r_cnt = mcall->tf()->range_sig()->cnt();
1364 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1365 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1366 C->record_method_not_compilable("unsupported outgoing calling sequence");
1367 } else {
1368 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1369 proj->_rout.Insert(OptoReg::Name(i));
1370 }
1371 if (proj->_rout.is_NotEmpty()) {
1372 push_projection(proj);
1373 }
1374 }
1375 // Transfer the safepoint information from the call to the mcall
1376 // Move the JVMState list
1377 msfpt->set_jvms(sfpt->jvms());
1378 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1379 jvms->set_map(sfpt);
1380 }
1381
1382 // Debug inputs begin just after the last incoming parameter
1383 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1384 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain_cc()->cnt()), "");
1385
1386 // Move the OopMap
1387 msfpt->_oop_map = sfpt->_oop_map;
1388
1389 // Add additional edges.
1390 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1391 // For these calls we can not add MachConstantBase in expand(), as the
1392 // ins are not complete then.
1393 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1394 if (msfpt->jvms() &&
1395 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1396 // We added an edge before jvms, so we must adapt the position of the ins.
1397 msfpt->jvms()->adapt_position(+1);
1398 }
1399 }
1400
1401 // Registers killed by the call are set in the local scheduling pass
1402 // of Global Code Motion.
1403 return msfpt;
1404 }
1405
1406 //---------------------------match_tree----------------------------------------
1407 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1408 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1409 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1410 // a Load's result RegMask for memoization in idealreg2regmask[]
1411 MachNode *Matcher::match_tree( const Node *n ) {
1412 assert( n->Opcode() != Op_Phi, "cannot match" );
1413 assert( !n->is_block_start(), "cannot match" );
1414 // Set the mark for all locally allocated State objects.
1415 // When this call returns, the _states_arena arena will be reset
1416 // freeing all State objects.
1417 ResourceMark rm( &_states_arena );
1418
1419 LabelRootDepth = 0;
1420
1421 // StoreNodes require their Memory input to match any LoadNodes
1422 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1423 #ifdef ASSERT
1424 Node* save_mem_node = _mem_node;
1425 _mem_node = n->is_Store() ? (Node*)n : NULL;
1426 #endif
1427 // State object for root node of match tree
1428 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1429 State *s = new (&_states_arena) State;
1430 s->_kids[0] = NULL;
1431 s->_kids[1] = NULL;
1432 s->_leaf = (Node*)n;
1433 // Label the input tree, allocating labels from top-level arena
1434 Label_Root( n, s, n->in(0), mem );
1435 if (C->failing()) return NULL;
1436
1437 // The minimum cost match for the whole tree is found at the root State
1438 uint mincost = max_juint;
1439 uint cost = max_juint;
1440 uint i;
1441 for( i = 0; i < NUM_OPERANDS; i++ ) {
1442 if( s->valid(i) && // valid entry and
1443 s->_cost[i] < cost && // low cost and
1444 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1445 cost = s->_cost[mincost=i];
1446 }
1447 if (mincost == max_juint) {
1448 #ifndef PRODUCT
1449 tty->print("No matching rule for:");
1450 s->dump();
1451 #endif
1452 Matcher::soft_match_failure();
1453 return NULL;
1454 }
1455 // Reduce input tree based upon the state labels to machine Nodes
1456 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1457 #ifdef ASSERT
1458 _old2new_map.map(n->_idx, m);
1459 _new2old_map.map(m->_idx, (Node*)n);
1460 #endif
1461
1462 // Add any Matcher-ignored edges
1463 uint cnt = n->req();
1464 uint start = 1;
1465 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1466 if( n->is_AddP() ) {
1467 assert( mem == (Node*)1, "" );
1468 start = AddPNode::Base+1;
1469 }
1470 for( i = start; i < cnt; i++ ) {
1471 if( !n->match_edge(i) ) {
1472 if( i < m->req() )
1473 m->ins_req( i, n->in(i) );
1474 else
1475 m->add_req( n->in(i) );
1476 }
1477 }
1478
1479 debug_only( _mem_node = save_mem_node; )
1480 return m;
1481 }
1482
1483
1484 //------------------------------match_into_reg---------------------------------
1485 // Choose to either match this Node in a register or part of the current
1486 // match tree. Return true for requiring a register and false for matching
1487 // as part of the current match tree.
1488 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1489
1490 const Type *t = m->bottom_type();
1491
1492 if (t->singleton()) {
1493 // Never force constants into registers. Allow them to match as
1494 // constants or registers. Copies of the same value will share
1495 // the same register. See find_shared_node.
1496 return false;
1497 } else { // Not a constant
1498 // Stop recursion if they have different Controls.
1499 Node* m_control = m->in(0);
1500 // Control of load's memory can post-dominates load's control.
1501 // So use it since load can't float above its memory.
1502 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1503 if (control && m_control && control != m_control && control != mem_control) {
1504
1505 // Actually, we can live with the most conservative control we
1506 // find, if it post-dominates the others. This allows us to
1507 // pick up load/op/store trees where the load can float a little
1508 // above the store.
1509 Node *x = control;
1510 const uint max_scan = 6; // Arbitrary scan cutoff
1511 uint j;
1512 for (j=0; j<max_scan; j++) {
1513 if (x->is_Region()) // Bail out at merge points
1514 return true;
1515 x = x->in(0);
1516 if (x == m_control) // Does 'control' post-dominate
1517 break; // m->in(0)? If so, we can use it
1518 if (x == mem_control) // Does 'control' post-dominate
1519 break; // mem_control? If so, we can use it
1520 }
1521 if (j == max_scan) // No post-domination before scan end?
1522 return true; // Then break the match tree up
1523 }
1524 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1525 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1526 // These are commonly used in address expressions and can
1527 // efficiently fold into them on X64 in some cases.
1528 return false;
1529 }
1530 }
1531
1532 // Not forceable cloning. If shared, put it into a register.
1533 return shared;
1534 }
1535
1536
1537 //------------------------------Instruction Selection--------------------------
1538 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1539 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1540 // things the Matcher does not match (e.g., Memory), and things with different
1541 // Controls (hence forced into different blocks). We pass in the Control
1542 // selected for this entire State tree.
1543
1544 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1545 // Store and the Load must have identical Memories (as well as identical
1546 // pointers). Since the Matcher does not have anything for Memory (and
1547 // does not handle DAGs), I have to match the Memory input myself. If the
1548 // Tree root is a Store, I require all Loads to have the identical memory.
1549 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1550 // Since Label_Root is a recursive function, its possible that we might run
1551 // out of stack space. See bugs 6272980 & 6227033 for more info.
1552 LabelRootDepth++;
1553 if (LabelRootDepth > MaxLabelRootDepth) {
1554 C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth");
1555 return NULL;
1556 }
1557 uint care = 0; // Edges matcher cares about
1558 uint cnt = n->req();
1559 uint i = 0;
1560
1561 // Examine children for memory state
1562 // Can only subsume a child into your match-tree if that child's memory state
1563 // is not modified along the path to another input.
1564 // It is unsafe even if the other inputs are separate roots.
1565 Node *input_mem = NULL;
1566 for( i = 1; i < cnt; i++ ) {
1567 if( !n->match_edge(i) ) continue;
1568 Node *m = n->in(i); // Get ith input
1569 assert( m, "expect non-null children" );
1570 if( m->is_Load() ) {
1571 if( input_mem == NULL ) {
1572 input_mem = m->in(MemNode::Memory);
1573 } else if( input_mem != m->in(MemNode::Memory) ) {
1574 input_mem = NodeSentinel;
1575 }
1576 }
1577 }
1578
1579 for( i = 1; i < cnt; i++ ){// For my children
1580 if( !n->match_edge(i) ) continue;
1581 Node *m = n->in(i); // Get ith input
1582 // Allocate states out of a private arena
1583 State *s = new (&_states_arena) State;
1584 svec->_kids[care++] = s;
1585 assert( care <= 2, "binary only for now" );
1586
1587 // Recursively label the State tree.
1588 s->_kids[0] = NULL;
1589 s->_kids[1] = NULL;
1590 s->_leaf = m;
1591
1592 // Check for leaves of the State Tree; things that cannot be a part of
1593 // the current tree. If it finds any, that value is matched as a
1594 // register operand. If not, then the normal matching is used.
1595 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1596 //
1597 // Stop recursion if this is LoadNode and the root of this tree is a
1598 // StoreNode and the load & store have different memories.
1599 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1600 // Can NOT include the match of a subtree when its memory state
1601 // is used by any of the other subtrees
1602 (input_mem == NodeSentinel) ) {
1603 // Print when we exclude matching due to different memory states at input-loads
1604 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1605 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1606 tty->print_cr("invalid input_mem");
1607 }
1608 // Switch to a register-only opcode; this value must be in a register
1609 // and cannot be subsumed as part of a larger instruction.
1610 s->DFA( m->ideal_reg(), m );
1611
1612 } else {
1613 // If match tree has no control and we do, adopt it for entire tree
1614 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1615 control = m->in(0); // Pick up control
1616 // Else match as a normal part of the match tree.
1617 control = Label_Root(m,s,control,mem);
1618 if (C->failing()) return NULL;
1619 }
1620 }
1621
1622
1623 // Call DFA to match this node, and return
1624 svec->DFA( n->Opcode(), n );
1625
1626 #ifdef ASSERT
1627 uint x;
1628 for( x = 0; x < _LAST_MACH_OPER; x++ )
1629 if( svec->valid(x) )
1630 break;
1631
1632 if (x >= _LAST_MACH_OPER) {
1633 n->dump();
1634 svec->dump();
1635 assert( false, "bad AD file" );
1636 }
1637 #endif
1638 return control;
1639 }
1640
1641
1642 // Con nodes reduced using the same rule can share their MachNode
1643 // which reduces the number of copies of a constant in the final
1644 // program. The register allocator is free to split uses later to
1645 // split live ranges.
1646 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1647 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1648
1649 // See if this Con has already been reduced using this rule.
1650 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1651 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1652 if (last != NULL && rule == last->rule()) {
1653 // Don't expect control change for DecodeN
1654 if (leaf->is_DecodeNarrowPtr())
1655 return last;
1656 // Get the new space root.
1657 Node* xroot = new_node(C->root());
1658 if (xroot == NULL) {
1659 // This shouldn't happen give the order of matching.
1660 return NULL;
1661 }
1662
1663 // Shared constants need to have their control be root so they
1664 // can be scheduled properly.
1665 Node* control = last->in(0);
1666 if (control != xroot) {
1667 if (control == NULL || control == C->root()) {
1668 last->set_req(0, xroot);
1669 } else {
1670 assert(false, "unexpected control");
1671 return NULL;
1672 }
1673 }
1674 return last;
1675 }
1676 return NULL;
1677 }
1678
1679
1680 //------------------------------ReduceInst-------------------------------------
1681 // Reduce a State tree (with given Control) into a tree of MachNodes.
1682 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1683 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1684 // Each MachNode has a number of complicated MachOper operands; each
1685 // MachOper also covers a further tree of Ideal Nodes.
1686
1687 // The root of the Ideal match tree is always an instruction, so we enter
1688 // the recursion here. After building the MachNode, we need to recurse
1689 // the tree checking for these cases:
1690 // (1) Child is an instruction -
1691 // Build the instruction (recursively), add it as an edge.
1692 // Build a simple operand (register) to hold the result of the instruction.
1693 // (2) Child is an interior part of an instruction -
1694 // Skip over it (do nothing)
1695 // (3) Child is the start of a operand -
1696 // Build the operand, place it inside the instruction
1697 // Call ReduceOper.
1698 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1699 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1700
1701 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1702 if (shared_node != NULL) {
1703 return shared_node;
1704 }
1705
1706 // Build the object to represent this state & prepare for recursive calls
1707 MachNode *mach = s->MachNodeGenerator(rule);
1708 guarantee(mach != NULL, "Missing MachNode");
1709 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1710 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1711 Node *leaf = s->_leaf;
1712 // Check for instruction or instruction chain rule
1713 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1714 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1715 "duplicating node that's already been matched");
1716 // Instruction
1717 mach->add_req( leaf->in(0) ); // Set initial control
1718 // Reduce interior of complex instruction
1719 ReduceInst_Interior( s, rule, mem, mach, 1 );
1720 } else {
1721 // Instruction chain rules are data-dependent on their inputs
1722 mach->add_req(0); // Set initial control to none
1723 ReduceInst_Chain_Rule( s, rule, mem, mach );
1724 }
1725
1726 // If a Memory was used, insert a Memory edge
1727 if( mem != (Node*)1 ) {
1728 mach->ins_req(MemNode::Memory,mem);
1729 #ifdef ASSERT
1730 // Verify adr type after matching memory operation
1731 const MachOper* oper = mach->memory_operand();
1732 if (oper != NULL && oper != (MachOper*)-1) {
1733 // It has a unique memory operand. Find corresponding ideal mem node.
1734 Node* m = NULL;
1735 if (leaf->is_Mem()) {
1736 m = leaf;
1737 } else {
1738 m = _mem_node;
1739 assert(m != NULL && m->is_Mem(), "expecting memory node");
1740 }
1741 const Type* mach_at = mach->adr_type();
1742 // DecodeN node consumed by an address may have different type
1743 // than its input. Don't compare types for such case.
1744 if (m->adr_type() != mach_at &&
1745 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1746 (m->in(MemNode::Address)->is_AddP() &&
1747 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()) ||
1748 (m->in(MemNode::Address)->is_AddP() &&
1749 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1750 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()))) {
1751 mach_at = m->adr_type();
1752 }
1753 if (m->adr_type() != mach_at) {
1754 m->dump();
1755 tty->print_cr("mach:");
1756 mach->dump(1);
1757 }
1758 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1759 }
1760 #endif
1761 }
1762
1763 // If the _leaf is an AddP, insert the base edge
1764 if (leaf->is_AddP()) {
1765 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1766 }
1767
1768 uint number_of_projections_prior = number_of_projections();
1769
1770 // Perform any 1-to-many expansions required
1771 MachNode *ex = mach->Expand(s, _projection_list, mem);
1772 if (ex != mach) {
1773 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1774 if( ex->in(1)->is_Con() )
1775 ex->in(1)->set_req(0, C->root());
1776 // Remove old node from the graph
1777 for( uint i=0; i<mach->req(); i++ ) {
1778 mach->set_req(i,NULL);
1779 }
1780 #ifdef ASSERT
1781 _new2old_map.map(ex->_idx, s->_leaf);
1782 #endif
1783 }
1784
1785 // PhaseChaitin::fixup_spills will sometimes generate spill code
1786 // via the matcher. By the time, nodes have been wired into the CFG,
1787 // and any further nodes generated by expand rules will be left hanging
1788 // in space, and will not get emitted as output code. Catch this.
1789 // Also, catch any new register allocation constraints ("projections")
1790 // generated belatedly during spill code generation.
1791 if (_allocation_started) {
1792 guarantee(ex == mach, "no expand rules during spill generation");
1793 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1794 }
1795
1796 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1797 // Record the con for sharing
1798 _shared_nodes.map(leaf->_idx, ex);
1799 }
1800
1801 return ex;
1802 }
1803
1804 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1805 for (uint i = n->req(); i < n->len(); i++) {
1806 if (n->in(i) != NULL) {
1807 mach->add_prec(n->in(i));
1808 }
1809 }
1810 }
1811
1812 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1813 // 'op' is what I am expecting to receive
1814 int op = _leftOp[rule];
1815 // Operand type to catch childs result
1816 // This is what my child will give me.
1817 int opnd_class_instance = s->_rule[op];
1818 // Choose between operand class or not.
1819 // This is what I will receive.
1820 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1821 // New rule for child. Chase operand classes to get the actual rule.
1822 int newrule = s->_rule[catch_op];
1823
1824 if( newrule < NUM_OPERANDS ) {
1825 // Chain from operand or operand class, may be output of shared node
1826 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1827 "Bad AD file: Instruction chain rule must chain from operand");
1828 // Insert operand into array of operands for this instruction
1829 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1830
1831 ReduceOper( s, newrule, mem, mach );
1832 } else {
1833 // Chain from the result of an instruction
1834 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1835 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1836 Node *mem1 = (Node*)1;
1837 debug_only(Node *save_mem_node = _mem_node;)
1838 mach->add_req( ReduceInst(s, newrule, mem1) );
1839 debug_only(_mem_node = save_mem_node;)
1840 }
1841 return;
1842 }
1843
1844
1845 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1846 handle_precedence_edges(s->_leaf, mach);
1847
1848 if( s->_leaf->is_Load() ) {
1849 Node *mem2 = s->_leaf->in(MemNode::Memory);
1850 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1851 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1852 mem = mem2;
1853 }
1854 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1855 if( mach->in(0) == NULL )
1856 mach->set_req(0, s->_leaf->in(0));
1857 }
1858
1859 // Now recursively walk the state tree & add operand list.
1860 for( uint i=0; i<2; i++ ) { // binary tree
1861 State *newstate = s->_kids[i];
1862 if( newstate == NULL ) break; // Might only have 1 child
1863 // 'op' is what I am expecting to receive
1864 int op;
1865 if( i == 0 ) {
1866 op = _leftOp[rule];
1867 } else {
1868 op = _rightOp[rule];
1869 }
1870 // Operand type to catch childs result
1871 // This is what my child will give me.
1872 int opnd_class_instance = newstate->_rule[op];
1873 // Choose between operand class or not.
1874 // This is what I will receive.
1875 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1876 // New rule for child. Chase operand classes to get the actual rule.
1877 int newrule = newstate->_rule[catch_op];
1878
1879 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1880 // Operand/operandClass
1881 // Insert operand into array of operands for this instruction
1882 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1883 ReduceOper( newstate, newrule, mem, mach );
1884
1885 } else { // Child is internal operand or new instruction
1886 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1887 // internal operand --> call ReduceInst_Interior
1888 // Interior of complex instruction. Do nothing but recurse.
1889 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1890 } else {
1891 // instruction --> call build operand( ) to catch result
1892 // --> ReduceInst( newrule )
1893 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
1894 Node *mem1 = (Node*)1;
1895 debug_only(Node *save_mem_node = _mem_node;)
1896 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1897 debug_only(_mem_node = save_mem_node;)
1898 }
1899 }
1900 assert( mach->_opnds[num_opnds-1], "" );
1901 }
1902 return num_opnds;
1903 }
1904
1905 // This routine walks the interior of possible complex operands.
1906 // At each point we check our children in the match tree:
1907 // (1) No children -
1908 // We are a leaf; add _leaf field as an input to the MachNode
1909 // (2) Child is an internal operand -
1910 // Skip over it ( do nothing )
1911 // (3) Child is an instruction -
1912 // Call ReduceInst recursively and
1913 // and instruction as an input to the MachNode
1914 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1915 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1916 State *kid = s->_kids[0];
1917 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1918
1919 // Leaf? And not subsumed?
1920 if( kid == NULL && !_swallowed[rule] ) {
1921 mach->add_req( s->_leaf ); // Add leaf pointer
1922 return; // Bail out
1923 }
1924
1925 if( s->_leaf->is_Load() ) {
1926 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1927 mem = s->_leaf->in(MemNode::Memory);
1928 debug_only(_mem_node = s->_leaf;)
1929 }
1930
1931 handle_precedence_edges(s->_leaf, mach);
1932
1933 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1934 if( !mach->in(0) )
1935 mach->set_req(0,s->_leaf->in(0));
1936 else {
1937 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1938 }
1939 }
1940
1941 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1942 int newrule;
1943 if( i == 0)
1944 newrule = kid->_rule[_leftOp[rule]];
1945 else
1946 newrule = kid->_rule[_rightOp[rule]];
1947
1948 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1949 // Internal operand; recurse but do nothing else
1950 ReduceOper( kid, newrule, mem, mach );
1951
1952 } else { // Child is a new instruction
1953 // Reduce the instruction, and add a direct pointer from this
1954 // machine instruction to the newly reduced one.
1955 Node *mem1 = (Node*)1;
1956 debug_only(Node *save_mem_node = _mem_node;)
1957 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1958 debug_only(_mem_node = save_mem_node;)
1959 }
1960 }
1961 }
1962
1963
1964 // -------------------------------------------------------------------------
1965 // Java-Java calling convention
1966 // (what you use when Java calls Java)
1967
1968 //------------------------------find_receiver----------------------------------
1969 // For a given signature, return the OptoReg for parameter 0.
1970 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1971 VMRegPair regs;
1972 BasicType sig_bt = T_OBJECT;
1973 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1974 // Return argument 0 register. In the LP64 build pointers
1975 // take 2 registers, but the VM wants only the 'main' name.
1976 return OptoReg::as_OptoReg(regs.first());
1977 }
1978
1979 // This function identifies sub-graphs in which a 'load' node is
1980 // input to two different nodes, and such that it can be matched
1981 // with BMI instructions like blsi, blsr, etc.
1982 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1983 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1984 // refers to the same node.
1985 #ifdef X86
1986 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1987 // This is a temporary solution until we make DAGs expressible in ADL.
1988 template<typename ConType>
1989 class FusedPatternMatcher {
1990 Node* _op1_node;
1991 Node* _mop_node;
1992 int _con_op;
1993
1994 static int match_next(Node* n, int next_op, int next_op_idx) {
1995 if (n->in(1) == NULL || n->in(2) == NULL) {
1996 return -1;
1997 }
1998
1999 if (next_op_idx == -1) { // n is commutative, try rotations
2000 if (n->in(1)->Opcode() == next_op) {
2001 return 1;
2002 } else if (n->in(2)->Opcode() == next_op) {
2003 return 2;
2004 }
2005 } else {
2006 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
2007 if (n->in(next_op_idx)->Opcode() == next_op) {
2008 return next_op_idx;
2009 }
2010 }
2011 return -1;
2012 }
2013 public:
2014 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
2015 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
2016
2017 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
2018 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
2019 typename ConType::NativeType con_value) {
2020 if (_op1_node->Opcode() != op1) {
2021 return false;
2022 }
2023 if (_mop_node->outcnt() > 2) {
2024 return false;
2025 }
2026 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
2027 if (op1_op2_idx == -1) {
2028 return false;
2029 }
2030 // Memory operation must be the other edge
2031 int op1_mop_idx = (op1_op2_idx & 1) + 1;
2032
2033 // Check that the mop node is really what we want
2034 if (_op1_node->in(op1_mop_idx) == _mop_node) {
2035 Node *op2_node = _op1_node->in(op1_op2_idx);
2036 if (op2_node->outcnt() > 1) {
2037 return false;
2038 }
2039 assert(op2_node->Opcode() == op2, "Should be");
2040 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
2041 if (op2_con_idx == -1) {
2042 return false;
2043 }
2044 // Memory operation must be the other edge
2045 int op2_mop_idx = (op2_con_idx & 1) + 1;
2046 // Check that the memory operation is the same node
2047 if (op2_node->in(op2_mop_idx) == _mop_node) {
2048 // Now check the constant
2049 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
2050 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
2051 return true;
2052 }
2053 }
2054 }
2055 return false;
2056 }
2057 };
2058
2059
2060 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2061 if (n != NULL && m != NULL) {
2062 if (m->Opcode() == Op_LoadI) {
2063 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2064 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
2065 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
2066 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2067 } else if (m->Opcode() == Op_LoadL) {
2068 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2069 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
2070 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2071 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2072 }
2073 }
2074 return false;
2075 }
2076 #endif // X86
2077
2078 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2079 Node *off = m->in(AddPNode::Offset);
2080 if (off->is_Con()) {
2081 address_visited.test_set(m->_idx); // Flag as address_visited
2082 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2083 // Clone X+offset as it also folds into most addressing expressions
2084 mstack.push(off, Visit);
2085 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2086 return true;
2087 }
2088 return false;
2089 }
2090
2091 // A method-klass-holder may be passed in the inline_cache_reg
2092 // and then expanded into the inline_cache_reg and a method_oop register
2093 // defined in ad_<arch>.cpp
2094
2095 //------------------------------find_shared------------------------------------
2096 // Set bits if Node is shared or otherwise a root
2097 void Matcher::find_shared( Node *n ) {
2098 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2099 MStack mstack(C->live_nodes() * 2);
2100 // Mark nodes as address_visited if they are inputs to an address expression
2101 VectorSet address_visited(Thread::current()->resource_area());
2102 mstack.push(n, Visit); // Don't need to pre-visit root node
2103 while (mstack.is_nonempty()) {
2104 n = mstack.node(); // Leave node on stack
2105 Node_State nstate = mstack.state();
2106 uint nop = n->Opcode();
2107 if (nstate == Pre_Visit) {
2108 if (address_visited.test(n->_idx)) { // Visited in address already?
2109 // Flag as visited and shared now.
2110 set_visited(n);
2111 }
2112 if (is_visited(n)) { // Visited already?
2113 // Node is shared and has no reason to clone. Flag it as shared.
2114 // This causes it to match into a register for the sharing.
2115 set_shared(n); // Flag as shared and
2116 mstack.pop(); // remove node from stack
2117 continue;
2118 }
2119 nstate = Visit; // Not already visited; so visit now
2120 }
2121 if (nstate == Visit) {
2122 mstack.set_state(Post_Visit);
2123 set_visited(n); // Flag as visited now
2124 bool mem_op = false;
2125 int mem_addr_idx = MemNode::Address;
2126
2127 switch( nop ) { // Handle some opcodes special
2128 case Op_Phi: // Treat Phis as shared roots
2129 case Op_Parm:
2130 case Op_Proj: // All handled specially during matching
2131 case Op_SafePointScalarObject:
2132 set_shared(n);
2133 set_dontcare(n);
2134 break;
2135 case Op_If:
2136 case Op_CountedLoopEnd:
2137 mstack.set_state(Alt_Post_Visit); // Alternative way
2138 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2139 // with matching cmp/branch in 1 instruction. The Matcher needs the
2140 // Bool and CmpX side-by-side, because it can only get at constants
2141 // that are at the leaves of Match trees, and the Bool's condition acts
2142 // as a constant here.
2143 mstack.push(n->in(1), Visit); // Clone the Bool
2144 mstack.push(n->in(0), Pre_Visit); // Visit control input
2145 continue; // while (mstack.is_nonempty())
2146 case Op_ConvI2D: // These forms efficiently match with a prior
2147 case Op_ConvI2F: // Load but not a following Store
2148 if( n->in(1)->is_Load() && // Prior load
2149 n->outcnt() == 1 && // Not already shared
2150 n->unique_out()->is_Store() ) // Following store
2151 set_shared(n); // Force it to be a root
2152 break;
2153 case Op_ReverseBytesI:
2154 case Op_ReverseBytesL:
2155 if( n->in(1)->is_Load() && // Prior load
2156 n->outcnt() == 1 ) // Not already shared
2157 set_shared(n); // Force it to be a root
2158 break;
2159 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
2160 case Op_IfFalse:
2161 case Op_IfTrue:
2162 case Op_MachProj:
2163 case Op_MergeMem:
2164 case Op_Catch:
2165 case Op_CatchProj:
2166 case Op_CProj:
2167 case Op_JumpProj:
2168 case Op_JProj:
2169 case Op_NeverBranch:
2170 set_dontcare(n);
2171 break;
2172 case Op_Jump:
2173 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2174 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2175 continue; // while (mstack.is_nonempty())
2176 case Op_StrComp:
2177 case Op_StrEquals:
2178 case Op_StrIndexOf:
2179 case Op_StrIndexOfChar:
2180 case Op_AryEq:
2181 case Op_HasNegatives:
2182 case Op_StrInflatedCopy:
2183 case Op_StrCompressedCopy:
2184 case Op_EncodeISOArray:
2185 case Op_FmaD:
2186 case Op_FmaF:
2187 case Op_FmaVD:
2188 case Op_FmaVF:
2189 set_shared(n); // Force result into register (it will be anyways)
2190 break;
2191 case Op_ConP: { // Convert pointers above the centerline to NUL
2192 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2193 const TypePtr* tp = tn->type()->is_ptr();
2194 if (tp->_ptr == TypePtr::AnyNull) {
2195 tn->set_type(TypePtr::NULL_PTR);
2196 }
2197 break;
2198 }
2199 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2200 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2201 const TypePtr* tp = tn->type()->make_ptr();
2202 if (tp && tp->_ptr == TypePtr::AnyNull) {
2203 tn->set_type(TypeNarrowOop::NULL_PTR);
2204 }
2205 break;
2206 }
2207 case Op_Binary: // These are introduced in the Post_Visit state.
2208 ShouldNotReachHere();
2209 break;
2210 case Op_ClearArray:
2211 case Op_SafePoint:
2212 mem_op = true;
2213 break;
2214 #if INCLUDE_ZGC
2215 case Op_CallLeaf:
2216 if (UseZGC) {
2217 if (n->as_Call()->entry_point() == ZBarrierSetRuntime::load_barrier_on_oop_field_preloaded_addr() ||
2218 n->as_Call()->entry_point() == ZBarrierSetRuntime::load_barrier_on_weak_oop_field_preloaded_addr()) {
2219 mem_op = true;
2220 mem_addr_idx = TypeFunc::Parms+1;
2221 }
2222 break;
2223 }
2224 #endif
2225 default:
2226 if( n->is_Store() ) {
2227 // Do match stores, despite no ideal reg
2228 mem_op = true;
2229 break;
2230 }
2231 if( n->is_Mem() ) { // Loads and LoadStores
2232 mem_op = true;
2233 // Loads must be root of match tree due to prior load conflict
2234 if( C->subsume_loads() == false )
2235 set_shared(n);
2236 }
2237 // Fall into default case
2238 if( !n->ideal_reg() )
2239 set_dontcare(n); // Unmatchable Nodes
2240 } // end_switch
2241
2242 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2243 Node *m = n->in(i); // Get ith input
2244 if (m == NULL) continue; // Ignore NULLs
2245 uint mop = m->Opcode();
2246
2247 // Must clone all producers of flags, or we will not match correctly.
2248 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2249 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2250 // are also there, so we may match a float-branch to int-flags and
2251 // expect the allocator to haul the flags from the int-side to the
2252 // fp-side. No can do.
2253 if( _must_clone[mop] ) {
2254 mstack.push(m, Visit);
2255 continue; // for(int i = ...)
2256 }
2257
2258 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2259 // Bases used in addresses must be shared but since
2260 // they are shared through a DecodeN they may appear
2261 // to have a single use so force sharing here.
2262 set_shared(m->in(AddPNode::Base)->in(1));
2263 }
2264
2265 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2266 #ifdef X86
2267 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2268 mstack.push(m, Visit);
2269 continue;
2270 }
2271 #endif
2272
2273 // Clone addressing expressions as they are "free" in memory access instructions
2274 if (mem_op && i == mem_addr_idx && mop == Op_AddP &&
2275 // When there are other uses besides address expressions
2276 // put it on stack and mark as shared.
2277 !is_visited(m)) {
2278 // Some inputs for address expression are not put on stack
2279 // to avoid marking them as shared and forcing them into register
2280 // if they are used only in address expressions.
2281 // But they should be marked as shared if there are other uses
2282 // besides address expressions.
2283
2284 if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
2285 continue;
2286 }
2287 } // if( mem_op &&
2288 mstack.push(m, Pre_Visit);
2289 } // for(int i = ...)
2290 }
2291 else if (nstate == Alt_Post_Visit) {
2292 mstack.pop(); // Remove node from stack
2293 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2294 // shared and all users of the Bool need to move the Cmp in parallel.
2295 // This leaves both the Bool and the If pointing at the Cmp. To
2296 // prevent the Matcher from trying to Match the Cmp along both paths
2297 // BoolNode::match_edge always returns a zero.
2298
2299 // We reorder the Op_If in a pre-order manner, so we can visit without
2300 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2301 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2302 }
2303 else if (nstate == Post_Visit) {
2304 mstack.pop(); // Remove node from stack
2305
2306 // Now hack a few special opcodes
2307 switch( n->Opcode() ) { // Handle some opcodes special
2308 case Op_StorePConditional:
2309 case Op_StoreIConditional:
2310 case Op_StoreLConditional:
2311 case Op_CompareAndExchangeB:
2312 case Op_CompareAndExchangeS:
2313 case Op_CompareAndExchangeI:
2314 case Op_CompareAndExchangeL:
2315 case Op_CompareAndExchangeP:
2316 case Op_CompareAndExchangeN:
2317 case Op_WeakCompareAndSwapB:
2318 case Op_WeakCompareAndSwapS:
2319 case Op_WeakCompareAndSwapI:
2320 case Op_WeakCompareAndSwapL:
2321 case Op_WeakCompareAndSwapP:
2322 case Op_WeakCompareAndSwapN:
2323 case Op_CompareAndSwapB:
2324 case Op_CompareAndSwapS:
2325 case Op_CompareAndSwapI:
2326 case Op_CompareAndSwapL:
2327 case Op_CompareAndSwapP:
2328 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2329 Node *newval = n->in(MemNode::ValueIn );
2330 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2331 Node *pair = new BinaryNode( oldval, newval );
2332 n->set_req(MemNode::ValueIn,pair);
2333 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2334 break;
2335 }
2336 case Op_CMoveD: // Convert trinary to binary-tree
2337 case Op_CMoveF:
2338 case Op_CMoveI:
2339 case Op_CMoveL:
2340 case Op_CMoveN:
2341 case Op_CMoveP:
2342 case Op_CMoveVF:
2343 case Op_CMoveVD: {
2344 // Restructure into a binary tree for Matching. It's possible that
2345 // we could move this code up next to the graph reshaping for IfNodes
2346 // or vice-versa, but I do not want to debug this for Ladybird.
2347 // 10/2/2000 CNC.
2348 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2349 n->set_req(1,pair1);
2350 Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2351 n->set_req(2,pair2);
2352 n->del_req(3);
2353 break;
2354 }
2355 case Op_LoopLimit: {
2356 Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2357 n->set_req(1,pair1);
2358 n->set_req(2,n->in(3));
2359 n->del_req(3);
2360 break;
2361 }
2362 case Op_StrEquals:
2363 case Op_StrIndexOfChar: {
2364 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2365 n->set_req(2,pair1);
2366 n->set_req(3,n->in(4));
2367 n->del_req(4);
2368 break;
2369 }
2370 case Op_StrComp:
2371 case Op_StrIndexOf: {
2372 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2373 n->set_req(2,pair1);
2374 Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2375 n->set_req(3,pair2);
2376 n->del_req(5);
2377 n->del_req(4);
2378 break;
2379 }
2380 case Op_StrCompressedCopy:
2381 case Op_StrInflatedCopy:
2382 case Op_EncodeISOArray: {
2383 // Restructure into a binary tree for Matching.
2384 Node* pair = new BinaryNode(n->in(3), n->in(4));
2385 n->set_req(3, pair);
2386 n->del_req(4);
2387 break;
2388 }
2389 case Op_FmaD:
2390 case Op_FmaF:
2391 case Op_FmaVD:
2392 case Op_FmaVF: {
2393 // Restructure into a binary tree for Matching.
2394 Node* pair = new BinaryNode(n->in(1), n->in(2));
2395 n->set_req(2, pair);
2396 n->set_req(1, n->in(3));
2397 n->del_req(3);
2398 break;
2399 }
2400 case Op_ClearArray: {
2401 Node* pair = new BinaryNode(n->in(2), n->in(3));
2402 n->set_req(2, pair);
2403 n->set_req(3, n->in(4));
2404 n->del_req(4);
2405 break;
2406 }
2407 default:
2408 break;
2409 }
2410 }
2411 else {
2412 ShouldNotReachHere();
2413 }
2414 } // end of while (mstack.is_nonempty())
2415 }
2416
2417 #ifdef ASSERT
2418 // machine-independent root to machine-dependent root
2419 void Matcher::dump_old2new_map() {
2420 _old2new_map.dump();
2421 }
2422 #endif
2423
2424 //---------------------------collect_null_checks-------------------------------
2425 // Find null checks in the ideal graph; write a machine-specific node for
2426 // it. Used by later implicit-null-check handling. Actually collects
2427 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2428 // value being tested.
2429 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2430 Node *iff = proj->in(0);
2431 if( iff->Opcode() == Op_If ) {
2432 // During matching If's have Bool & Cmp side-by-side
2433 BoolNode *b = iff->in(1)->as_Bool();
2434 Node *cmp = iff->in(2);
2435 int opc = cmp->Opcode();
2436 if (opc != Op_CmpP && opc != Op_CmpN) return;
2437
2438 const Type* ct = cmp->in(2)->bottom_type();
2439 if (ct == TypePtr::NULL_PTR ||
2440 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2441
2442 bool push_it = false;
2443 if( proj->Opcode() == Op_IfTrue ) {
2444 #ifndef PRODUCT
2445 extern int all_null_checks_found;
2446 all_null_checks_found++;
2447 #endif
2448 if( b->_test._test == BoolTest::ne ) {
2449 push_it = true;
2450 }
2451 } else {
2452 assert( proj->Opcode() == Op_IfFalse, "" );
2453 if( b->_test._test == BoolTest::eq ) {
2454 push_it = true;
2455 }
2456 }
2457 if( push_it ) {
2458 _null_check_tests.push(proj);
2459 Node* val = cmp->in(1);
2460 #ifdef _LP64
2461 if (val->bottom_type()->isa_narrowoop() &&
2462 !Matcher::narrow_oop_use_complex_address()) {
2463 //
2464 // Look for DecodeN node which should be pinned to orig_proj.
2465 // On platforms (Sparc) which can not handle 2 adds
2466 // in addressing mode we have to keep a DecodeN node and
2467 // use it to do implicit NULL check in address.
2468 //
2469 // DecodeN node was pinned to non-null path (orig_proj) during
2470 // CastPP transformation in final_graph_reshaping_impl().
2471 //
2472 uint cnt = orig_proj->outcnt();
2473 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2474 Node* d = orig_proj->raw_out(i);
2475 if (d->is_DecodeN() && d->in(1) == val) {
2476 val = d;
2477 val->set_req(0, NULL); // Unpin now.
2478 // Mark this as special case to distinguish from
2479 // a regular case: CmpP(DecodeN, NULL).
2480 val = (Node*)(((intptr_t)val) | 1);
2481 break;
2482 }
2483 }
2484 }
2485 #endif
2486 _null_check_tests.push(val);
2487 }
2488 }
2489 }
2490 }
2491
2492 //---------------------------validate_null_checks------------------------------
2493 // Its possible that the value being NULL checked is not the root of a match
2494 // tree. If so, I cannot use the value in an implicit null check.
2495 void Matcher::validate_null_checks( ) {
2496 uint cnt = _null_check_tests.size();
2497 for( uint i=0; i < cnt; i+=2 ) {
2498 Node *test = _null_check_tests[i];
2499 Node *val = _null_check_tests[i+1];
2500 bool is_decoden = ((intptr_t)val) & 1;
2501 val = (Node*)(((intptr_t)val) & ~1);
2502 if (has_new_node(val)) {
2503 Node* new_val = new_node(val);
2504 if (is_decoden) {
2505 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2506 // Note: new_val may have a control edge if
2507 // the original ideal node DecodeN was matched before
2508 // it was unpinned in Matcher::collect_null_checks().
2509 // Unpin the mach node and mark it.
2510 new_val->set_req(0, NULL);
2511 new_val = (Node*)(((intptr_t)new_val) | 1);
2512 }
2513 // Is a match-tree root, so replace with the matched value
2514 _null_check_tests.map(i+1, new_val);
2515 } else {
2516 // Yank from candidate list
2517 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2518 _null_check_tests.map(i,_null_check_tests[--cnt]);
2519 _null_check_tests.pop();
2520 _null_check_tests.pop();
2521 i-=2;
2522 }
2523 }
2524 }
2525
2526 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2527 // atomic instruction acting as a store_load barrier without any
2528 // intervening volatile load, and thus we don't need a barrier here.
2529 // We retain the Node to act as a compiler ordering barrier.
2530 bool Matcher::post_store_load_barrier(const Node* vmb) {
2531 Compile* C = Compile::current();
2532 assert(vmb->is_MemBar(), "");
2533 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2534 const MemBarNode* membar = vmb->as_MemBar();
2535
2536 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2537 Node* ctrl = NULL;
2538 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2539 Node* p = membar->fast_out(i);
2540 assert(p->is_Proj(), "only projections here");
2541 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2542 !C->node_arena()->contains(p)) { // Unmatched old-space only
2543 ctrl = p;
2544 break;
2545 }
2546 }
2547 assert((ctrl != NULL), "missing control projection");
2548
2549 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2550 Node *x = ctrl->fast_out(j);
2551 int xop = x->Opcode();
2552
2553 // We don't need current barrier if we see another or a lock
2554 // before seeing volatile load.
2555 //
2556 // Op_Fastunlock previously appeared in the Op_* list below.
2557 // With the advent of 1-0 lock operations we're no longer guaranteed
2558 // that a monitor exit operation contains a serializing instruction.
2559
2560 if (xop == Op_MemBarVolatile ||
2561 xop == Op_CompareAndExchangeB ||
2562 xop == Op_CompareAndExchangeS ||
2563 xop == Op_CompareAndExchangeI ||
2564 xop == Op_CompareAndExchangeL ||
2565 xop == Op_CompareAndExchangeP ||
2566 xop == Op_CompareAndExchangeN ||
2567 xop == Op_WeakCompareAndSwapB ||
2568 xop == Op_WeakCompareAndSwapS ||
2569 xop == Op_WeakCompareAndSwapL ||
2570 xop == Op_WeakCompareAndSwapP ||
2571 xop == Op_WeakCompareAndSwapN ||
2572 xop == Op_WeakCompareAndSwapI ||
2573 xop == Op_CompareAndSwapB ||
2574 xop == Op_CompareAndSwapS ||
2575 xop == Op_CompareAndSwapL ||
2576 xop == Op_CompareAndSwapP ||
2577 xop == Op_CompareAndSwapN ||
2578 xop == Op_CompareAndSwapI) {
2579 return true;
2580 }
2581
2582 // Op_FastLock previously appeared in the Op_* list above.
2583 // With biased locking we're no longer guaranteed that a monitor
2584 // enter operation contains a serializing instruction.
2585 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2586 return true;
2587 }
2588
2589 if (x->is_MemBar()) {
2590 // We must retain this membar if there is an upcoming volatile
2591 // load, which will be followed by acquire membar.
2592 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2593 return false;
2594 } else {
2595 // For other kinds of barriers, check by pretending we
2596 // are them, and seeing if we can be removed.
2597 return post_store_load_barrier(x->as_MemBar());
2598 }
2599 }
2600
2601 // probably not necessary to check for these
2602 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2603 return false;
2604 }
2605 }
2606 return false;
2607 }
2608
2609 // Check whether node n is a branch to an uncommon trap that we could
2610 // optimize as test with very high branch costs in case of going to
2611 // the uncommon trap. The code must be able to be recompiled to use
2612 // a cheaper test.
2613 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2614 // Don't do it for natives, adapters, or runtime stubs
2615 Compile *C = Compile::current();
2616 if (!C->is_method_compilation()) return false;
2617
2618 assert(n->is_If(), "You should only call this on if nodes.");
2619 IfNode *ifn = n->as_If();
2620
2621 Node *ifFalse = NULL;
2622 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2623 if (ifn->fast_out(i)->is_IfFalse()) {
2624 ifFalse = ifn->fast_out(i);
2625 break;
2626 }
2627 }
2628 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2629
2630 Node *reg = ifFalse;
2631 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2632 // Alternatively use visited set? Seems too expensive.
2633 while (reg != NULL && cnt > 0) {
2634 CallNode *call = NULL;
2635 RegionNode *nxt_reg = NULL;
2636 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2637 Node *o = reg->fast_out(i);
2638 if (o->is_Call()) {
2639 call = o->as_Call();
2640 }
2641 if (o->is_Region()) {
2642 nxt_reg = o->as_Region();
2643 }
2644 }
2645
2646 if (call &&
2647 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2648 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2649 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2650 jint tr_con = trtype->is_int()->get_con();
2651 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2652 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2653 assert((int)reason < (int)BitsPerInt, "recode bit map");
2654
2655 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2656 && action != Deoptimization::Action_none) {
2657 // This uncommon trap is sure to recompile, eventually.
2658 // When that happens, C->too_many_traps will prevent
2659 // this transformation from happening again.
2660 return true;
2661 }
2662 }
2663 }
2664
2665 reg = nxt_reg;
2666 cnt--;
2667 }
2668
2669 return false;
2670 }
2671
2672 //=============================================================================
2673 //---------------------------State---------------------------------------------
2674 State::State(void) {
2675 #ifdef ASSERT
2676 _id = 0;
2677 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2678 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2679 //memset(_cost, -1, sizeof(_cost));
2680 //memset(_rule, -1, sizeof(_rule));
2681 #endif
2682 memset(_valid, 0, sizeof(_valid));
2683 }
2684
2685 #ifdef ASSERT
2686 State::~State() {
2687 _id = 99;
2688 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2689 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2690 memset(_cost, -3, sizeof(_cost));
2691 memset(_rule, -3, sizeof(_rule));
2692 }
2693 #endif
2694
2695 #ifndef PRODUCT
2696 //---------------------------dump----------------------------------------------
2697 void State::dump() {
2698 tty->print("\n");
2699 dump(0);
2700 }
2701
2702 void State::dump(int depth) {
2703 for( int j = 0; j < depth; j++ )
2704 tty->print(" ");
2705 tty->print("--N: ");
2706 _leaf->dump();
2707 uint i;
2708 for( i = 0; i < _LAST_MACH_OPER; i++ )
2709 // Check for valid entry
2710 if( valid(i) ) {
2711 for( int j = 0; j < depth; j++ )
2712 tty->print(" ");
2713 assert(_cost[i] != max_juint, "cost must be a valid value");
2714 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2715 tty->print_cr("%s %d %s",
2716 ruleName[i], _cost[i], ruleName[_rule[i]] );
2717 }
2718 tty->cr();
2719
2720 for( i=0; i<2; i++ )
2721 if( _kids[i] )
2722 _kids[i]->dump(depth+1);
2723 }
2724 #endif