476 idealreg2debugmask [Op_RegP] = &rms[11]; 477 478 idealreg2mhdebugmask[Op_RegN] = &rms[12]; 479 idealreg2mhdebugmask[Op_RegI] = &rms[13]; 480 idealreg2mhdebugmask[Op_RegL] = &rms[14]; 481 idealreg2mhdebugmask[Op_RegF] = &rms[15]; 482 idealreg2mhdebugmask[Op_RegD] = &rms[16]; 483 idealreg2mhdebugmask[Op_RegP] = &rms[17]; 484 485 idealreg2spillmask [Op_VecS] = &rms[18]; 486 idealreg2spillmask [Op_VecD] = &rms[19]; 487 idealreg2spillmask [Op_VecX] = &rms[20]; 488 idealreg2spillmask [Op_VecY] = &rms[21]; 489 idealreg2spillmask [Op_VecZ] = &rms[22]; 490 491 OptoReg::Name i; 492 493 // At first, start with the empty mask 494 C->FIRST_STACK_mask().Clear(); 495 496 // Add in the incoming argument area 497 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 498 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) { 499 C->FIRST_STACK_mask().Insert(i); 500 } 501 // Add in all bits past the outgoing argument area 502 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)), 503 "must be able to represent all call arguments in reg mask"); 504 OptoReg::Name init = _out_arg_limit; 505 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) { 506 C->FIRST_STACK_mask().Insert(i); 507 } 508 // Finally, set the "infinite stack" bit. 509 C->FIRST_STACK_mask().set_AllStack(); 510 511 // Make spill masks. Registers for their class, plus FIRST_STACK_mask. 512 RegMask aligned_stack_mask = C->FIRST_STACK_mask(); 513 // Keep spill masks aligned. 514 aligned_stack_mask.clear_to_pairs(); 515 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 516 517 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP]; 518 #ifdef _LP64 | 476 idealreg2debugmask [Op_RegP] = &rms[11]; 477 478 idealreg2mhdebugmask[Op_RegN] = &rms[12]; 479 idealreg2mhdebugmask[Op_RegI] = &rms[13]; 480 idealreg2mhdebugmask[Op_RegL] = &rms[14]; 481 idealreg2mhdebugmask[Op_RegF] = &rms[15]; 482 idealreg2mhdebugmask[Op_RegD] = &rms[16]; 483 idealreg2mhdebugmask[Op_RegP] = &rms[17]; 484 485 idealreg2spillmask [Op_VecS] = &rms[18]; 486 idealreg2spillmask [Op_VecD] = &rms[19]; 487 idealreg2spillmask [Op_VecX] = &rms[20]; 488 idealreg2spillmask [Op_VecY] = &rms[21]; 489 idealreg2spillmask [Op_VecZ] = &rms[22]; 490 491 OptoReg::Name i; 492 493 // At first, start with the empty mask 494 C->FIRST_STACK_mask().Clear(); 495 496 // Check if method has a reserved entry in the argument stack area that 497 // should not be used for spilling because it holds the return address. 498 OptoRegPair res_entry; 499 if (C->needs_stack_repair()) { 500 int res_idx = C->get_res_entry()._offset; 501 res_entry = _parm_regs[res_idx]; 502 } 503 504 // Add in the incoming argument area 505 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 506 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) { 507 if (i == res_entry.first() || i == res_entry.second()) { 508 continue; // Skip reserved slot to avoid spilling 509 } 510 C->FIRST_STACK_mask().Insert(i); 511 } 512 // Add in all bits past the outgoing argument area 513 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)), 514 "must be able to represent all call arguments in reg mask"); 515 OptoReg::Name init = _out_arg_limit; 516 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) { 517 C->FIRST_STACK_mask().Insert(i); 518 } 519 // Finally, set the "infinite stack" bit. 520 C->FIRST_STACK_mask().set_AllStack(); 521 522 // Make spill masks. Registers for their class, plus FIRST_STACK_mask. 523 RegMask aligned_stack_mask = C->FIRST_STACK_mask(); 524 // Keep spill masks aligned. 525 aligned_stack_mask.clear_to_pairs(); 526 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 527 528 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP]; 529 #ifdef _LP64 |