1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 public:
42 // Support for VM calls
43 //
44 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
45 // may customize this version by overriding it for its purposes (e.g., to save/restore
46 // additional registers when doing a VM call).
47
48 virtual void call_VM_leaf_base(
49 address entry_point, // the entry point
50 int number_of_arguments // the number of arguments to pop after the call
51 );
52
53 protected:
54 // This is the base routine called by the different versions of call_VM. The interpreter
55 // may customize this version by overriding it for its purposes (e.g., to save/restore
56 // additional registers when doing a VM call).
57 //
58 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
59 // returns the register which contains the thread upon return. If a thread register has been
60 // specified, the return value will correspond to that register. If no last_java_sp is specified
61 // (noreg) than rsp will be used instead.
62 virtual void call_VM_base( // returns the register containing the thread upon return
63 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
64 Register java_thread, // the thread if computed before ; use noreg otherwise
65 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
66 address entry_point, // the entry point
67 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
68 bool check_exceptions // whether to check for pending exceptions after return
69 );
70
71 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
72
73 // helpers for FPU flag access
74 // tmp is a temporary register, if none is available use noreg
75 void save_rax (Register tmp);
76 void restore_rax(Register tmp);
77
78 public:
79 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
80
81 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
82 // The implementation is only non-empty for the InterpreterMacroAssembler,
83 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
84 virtual void check_and_handle_popframe(Register java_thread);
85 virtual void check_and_handle_earlyret(Register java_thread);
86
87 Address as_Address(AddressLiteral adr);
88 Address as_Address(ArrayAddress adr);
89
90 // Support for NULL-checks
91 //
92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
93 // If the accessed location is M[reg + offset] and the offset is known, provide the
94 // offset. No explicit code generation is needed if the offset is within a certain
95 // range (0 <= offset <= page_size).
96
97 void null_check(Register reg, int offset = -1);
98 static bool needs_explicit_null_check(intptr_t offset);
99 static bool uses_implicit_null_check(void* address);
100
101 void test_klass_is_value(Register klass, Register temp_reg, Label& is_value);
102
103 void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable);
104 void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable);
105 void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened);
106
107 // Check klass/oops is flat value type array (oop->_klass->_layout_helper & vt_bit)
108 void test_flat_array_klass(Register klass, Register temp_reg, Label& is_flat_array);
109 void test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array);
110
111 // Required platform-specific helpers for Label::patch_instructions.
112 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
113 void pd_patch_instruction(address branch, address target, const char* file, int line) {
114 unsigned char op = branch[0];
115 assert(op == 0xE8 /* call */ ||
116 op == 0xE9 /* jmp */ ||
117 op == 0xEB /* short jmp */ ||
118 (op & 0xF0) == 0x70 /* short jcc */ ||
119 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
120 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
121 "Invalid opcode at patch point");
122
123 if (op == 0xEB || (op & 0xF0) == 0x70) {
124 // short offset operators (jmp and jcc)
125 char* disp = (char*) &branch[1];
126 int imm8 = target - (address) &disp[1];
127 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d", file, line);
128 *disp = imm8;
129 } else {
130 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
131 int imm32 = target - (address) &disp[1];
132 *disp = imm32;
133 }
134 }
135
136 // The following 4 methods return the offset of the appropriate move instruction
137
138 // Support for fast byte/short loading with zero extension (depending on particular CPU)
139 int load_unsigned_byte(Register dst, Address src);
140 int load_unsigned_short(Register dst, Address src);
141
142 // Support for fast byte/short loading with sign extension (depending on particular CPU)
143 int load_signed_byte(Register dst, Address src);
144 int load_signed_short(Register dst, Address src);
145
146 // Support for sign-extension (hi:lo = extend_sign(lo))
147 void extend_sign(Register hi, Register lo);
148
149 // Load and store values by size and signed-ness
150 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
151 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
152
153 // Support for inc/dec with optimal instruction selection depending on value
154
155 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
156 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
157
158 void decrementl(Address dst, int value = 1);
159 void decrementl(Register reg, int value = 1);
160
161 void decrementq(Register reg, int value = 1);
162 void decrementq(Address dst, int value = 1);
163
164 void incrementl(Address dst, int value = 1);
165 void incrementl(Register reg, int value = 1);
166
167 void incrementq(Register reg, int value = 1);
168 void incrementq(Address dst, int value = 1);
169
170 #ifdef COMPILER2
171 // special instructions for EVEX
172 void setvectmask(Register dst, Register src);
173 void restorevectmask();
174 #endif
175
176 // Support optimal SSE move instructions.
177 void movflt(XMMRegister dst, XMMRegister src) {
178 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
179 else { movss (dst, src); return; }
180 }
181 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
182 void movflt(XMMRegister dst, AddressLiteral src);
183 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
184
185 void movdbl(XMMRegister dst, XMMRegister src) {
186 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
187 else { movsd (dst, src); return; }
188 }
189
190 void movdbl(XMMRegister dst, AddressLiteral src);
191
192 void movdbl(XMMRegister dst, Address src) {
193 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
194 else { movlpd(dst, src); return; }
195 }
196 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
197
198 void incrementl(AddressLiteral dst);
199 void incrementl(ArrayAddress dst);
200
201 void incrementq(AddressLiteral dst);
202
203 // Alignment
204 void align(int modulus);
205 void align(int modulus, int target);
206
207 // A 5 byte nop that is safe for patching (see patch_verified_entry)
208 void fat_nop();
209
210 // Stack frame creation/removal
211 void enter();
212 void leave();
213
214 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
215 // The pointer will be loaded into the thread register.
216 void get_thread(Register thread);
217
218
219 // Support for VM calls
220 //
221 // It is imperative that all calls into the VM are handled via the call_VM macros.
222 // They make sure that the stack linkage is setup correctly. call_VM's correspond
223 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
224
225
226 void call_VM(Register oop_result,
227 address entry_point,
228 bool check_exceptions = true);
229 void call_VM(Register oop_result,
230 address entry_point,
231 Register arg_1,
232 bool check_exceptions = true);
233 void call_VM(Register oop_result,
234 address entry_point,
235 Register arg_1, Register arg_2,
236 bool check_exceptions = true);
237 void call_VM(Register oop_result,
238 address entry_point,
239 Register arg_1, Register arg_2, Register arg_3,
240 bool check_exceptions = true);
241
242 // Overloadings with last_Java_sp
243 void call_VM(Register oop_result,
244 Register last_java_sp,
245 address entry_point,
246 int number_of_arguments = 0,
247 bool check_exceptions = true);
248 void call_VM(Register oop_result,
249 Register last_java_sp,
250 address entry_point,
251 Register arg_1, bool
252 check_exceptions = true);
253 void call_VM(Register oop_result,
254 Register last_java_sp,
255 address entry_point,
256 Register arg_1, Register arg_2,
257 bool check_exceptions = true);
258 void call_VM(Register oop_result,
259 Register last_java_sp,
260 address entry_point,
261 Register arg_1, Register arg_2, Register arg_3,
262 bool check_exceptions = true);
263
264 void get_vm_result (Register oop_result, Register thread);
265 void get_vm_result_2(Register metadata_result, Register thread);
266
267 // These always tightly bind to MacroAssembler::call_VM_base
268 // bypassing the virtual implementation
269 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
270 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
271 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
272 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
273 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
274
275 void call_VM_leaf0(address entry_point);
276 void call_VM_leaf(address entry_point,
277 int number_of_arguments = 0);
278 void call_VM_leaf(address entry_point,
279 Register arg_1);
280 void call_VM_leaf(address entry_point,
281 Register arg_1, Register arg_2);
282 void call_VM_leaf(address entry_point,
283 Register arg_1, Register arg_2, Register arg_3);
284
285 // These always tightly bind to MacroAssembler::call_VM_leaf_base
286 // bypassing the virtual implementation
287 void super_call_VM_leaf(address entry_point);
288 void super_call_VM_leaf(address entry_point, Register arg_1);
289 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
290 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
291 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
292
293 // last Java Frame (fills frame anchor)
294 void set_last_Java_frame(Register thread,
295 Register last_java_sp,
296 Register last_java_fp,
297 address last_java_pc);
298
299 // thread in the default location (r15_thread on 64bit)
300 void set_last_Java_frame(Register last_java_sp,
301 Register last_java_fp,
302 address last_java_pc);
303
304 void reset_last_Java_frame(Register thread, bool clear_fp);
305
306 // thread in the default location (r15_thread on 64bit)
307 void reset_last_Java_frame(bool clear_fp);
308
309 // jobjects
310 void clear_jweak_tag(Register possibly_jweak);
311 void resolve_jobject(Register value, Register thread, Register tmp);
312
313 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
314 void c2bool(Register x);
315
316 // C++ bool manipulation
317
318 void movbool(Register dst, Address src);
319 void movbool(Address dst, bool boolconst);
320 void movbool(Address dst, Register src);
321 void testbool(Register dst);
322
323 void resolve_oop_handle(Register result, Register tmp = rscratch2);
324 void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
325
326 // oop manipulations
327 void load_klass(Register dst, Register src);
328 void store_klass(Register dst, Register src);
329
330 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
331 Register tmp1, Register thread_tmp);
332 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
333 Register tmp1, Register tmp2);
334
335 // Resolves obj access. Result is placed in the same register.
336 // All other registers are preserved.
337 void resolve(DecoratorSet decorators, Register obj);
338
339 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
340 Register thread_tmp = noreg, DecoratorSet decorators = 0);
341 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
342 Register thread_tmp = noreg, DecoratorSet decorators = 0);
343 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
344 Register tmp2 = noreg, DecoratorSet decorators = 0);
345
346 // Used for storing NULL. All other oop constants should be
347 // stored using routines that take a jobject.
348 void store_heap_oop_null(Address dst);
349
350 void load_prototype_header(Register dst, Register src);
351
352 #ifdef _LP64
353 void store_klass_gap(Register dst, Register src);
354
355 // This dummy is to prevent a call to store_heap_oop from
356 // converting a zero (like NULL) into a Register by giving
357 // the compiler two choices it can't resolve
358
359 void store_heap_oop(Address dst, void* dummy);
360
361 void encode_heap_oop(Register r);
362 void decode_heap_oop(Register r);
363 void encode_heap_oop_not_null(Register r);
364 void decode_heap_oop_not_null(Register r);
365 void encode_heap_oop_not_null(Register dst, Register src);
366 void decode_heap_oop_not_null(Register dst, Register src);
367
368 void set_narrow_oop(Register dst, jobject obj);
369 void set_narrow_oop(Address dst, jobject obj);
370 void cmp_narrow_oop(Register dst, jobject obj);
371 void cmp_narrow_oop(Address dst, jobject obj);
372
373 void encode_klass_not_null(Register r);
374 void decode_klass_not_null(Register r);
375 void encode_klass_not_null(Register dst, Register src);
376 void decode_klass_not_null(Register dst, Register src);
377 void set_narrow_klass(Register dst, Klass* k);
378 void set_narrow_klass(Address dst, Klass* k);
379 void cmp_narrow_klass(Register dst, Klass* k);
380 void cmp_narrow_klass(Address dst, Klass* k);
381
382 // Returns the byte size of the instructions generated by decode_klass_not_null()
383 // when compressed klass pointers are being used.
384 static int instr_size_for_decode_klass_not_null();
385
386 // if heap base register is used - reinit it with the correct value
387 void reinit_heapbase();
388
389 DEBUG_ONLY(void verify_heapbase(const char* msg);)
390
391 #endif // _LP64
392
393 // Int division/remainder for Java
394 // (as idivl, but checks for special case as described in JVM spec.)
395 // returns idivl instruction offset for implicit exception handling
396 int corrected_idivl(Register reg);
397
398 // Long division/remainder for Java
399 // (as idivq, but checks for special case as described in JVM spec.)
400 // returns idivq instruction offset for implicit exception handling
401 int corrected_idivq(Register reg);
402
403 void int3();
404
405 // Long operation macros for a 32bit cpu
406 // Long negation for Java
407 void lneg(Register hi, Register lo);
408
409 // Long multiplication for Java
410 // (destroys contents of eax, ebx, ecx and edx)
411 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
412
413 // Long shifts for Java
414 // (semantics as described in JVM spec.)
415 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
416 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
417
418 // Long compare for Java
419 // (semantics as described in JVM spec.)
420 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
421
422
423 // misc
424
425 // Sign extension
426 void sign_extend_short(Register reg);
427 void sign_extend_byte(Register reg);
428
429 // Division by power of 2, rounding towards 0
430 void division_with_shift(Register reg, int shift_value);
431
432 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
433 //
434 // CF (corresponds to C0) if x < y
435 // PF (corresponds to C2) if unordered
436 // ZF (corresponds to C3) if x = y
437 //
438 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
439 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
440 void fcmp(Register tmp);
441 // Variant of the above which allows y to be further down the stack
442 // and which only pops x and y if specified. If pop_right is
443 // specified then pop_left must also be specified.
444 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
445
446 // Floating-point comparison for Java
447 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
448 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
449 // (semantics as described in JVM spec.)
450 void fcmp2int(Register dst, bool unordered_is_less);
451 // Variant of the above which allows y to be further down the stack
452 // and which only pops x and y if specified. If pop_right is
453 // specified then pop_left must also be specified.
454 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
455
456 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
457 // tmp is a temporary register, if none is available use noreg
458 void fremr(Register tmp);
459
460 // dst = c = a * b + c
461 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
462 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
463
464 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
465 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
466 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
467 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
468
469
470 // same as fcmp2int, but using SSE2
471 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
472 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
473
474 // branch to L if FPU flag C2 is set/not set
475 // tmp is a temporary register, if none is available use noreg
476 void jC2 (Register tmp, Label& L);
477 void jnC2(Register tmp, Label& L);
478
479 // Pop ST (ffree & fincstp combined)
480 void fpop();
481
482 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
483 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
484 void load_float(Address src);
485
486 // Store float value to 'address'. If UseSSE >= 1, the value is stored
487 // from register xmm0. Otherwise, the value is stored from the FPU stack.
488 void store_float(Address dst);
489
490 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
491 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
492 void load_double(Address src);
493
494 // Store double value to 'address'. If UseSSE >= 2, the value is stored
495 // from register xmm0. Otherwise, the value is stored from the FPU stack.
496 void store_double(Address dst);
497
498 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
499 void push_fTOS();
500
501 // pops double TOS element from CPU stack and pushes on FPU stack
502 void pop_fTOS();
503
504 void empty_FPU_stack();
505
506 void push_IU_state();
507 void pop_IU_state();
508
509 void push_FPU_state();
510 void pop_FPU_state();
511
512 void push_CPU_state();
513 void pop_CPU_state();
514
515 // Round up to a power of two
516 void round_to(Register reg, int modulus);
517
518 // Callee saved registers handling
519 void push_callee_saved_registers();
520 void pop_callee_saved_registers();
521
522 // allocation
523 void eden_allocate(
524 Register thread, // Current thread
525 Register obj, // result: pointer to object after successful allocation
526 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
527 int con_size_in_bytes, // object size in bytes if known at compile time
528 Register t1, // temp register
529 Label& slow_case // continuation point if fast allocation fails
530 );
531 void tlab_allocate(
532 Register thread, // Current thread
533 Register obj, // result: pointer to object after successful allocation
534 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
535 int con_size_in_bytes, // object size in bytes if known at compile time
536 Register t1, // temp register
537 Register t2, // temp register
538 Label& slow_case // continuation point if fast allocation fails
539 );
540 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
541
542 // interface method calling
543 void lookup_interface_method(Register recv_klass,
544 Register intf_klass,
545 RegisterOrConstant itable_index,
546 Register method_result,
547 Register scan_temp,
548 Label& no_such_interface,
549 bool return_method = true);
550
551 // virtual method calling
552 void lookup_virtual_method(Register recv_klass,
553 RegisterOrConstant vtable_index,
554 Register method_result);
555
556 // Test sub_klass against super_klass, with fast and slow paths.
557
558 // The fast path produces a tri-state answer: yes / no / maybe-slow.
559 // One of the three labels can be NULL, meaning take the fall-through.
560 // If super_check_offset is -1, the value is loaded up from super_klass.
561 // No registers are killed, except temp_reg.
562 void check_klass_subtype_fast_path(Register sub_klass,
563 Register super_klass,
564 Register temp_reg,
565 Label* L_success,
566 Label* L_failure,
567 Label* L_slow_path,
568 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
569
570 // The rest of the type check; must be wired to a corresponding fast path.
571 // It does not repeat the fast path logic, so don't use it standalone.
572 // The temp_reg and temp2_reg can be noreg, if no temps are available.
573 // Updates the sub's secondary super cache as necessary.
574 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
575 void check_klass_subtype_slow_path(Register sub_klass,
576 Register super_klass,
577 Register temp_reg,
578 Register temp2_reg,
579 Label* L_success,
580 Label* L_failure,
581 bool set_cond_codes = false);
582
583 // Simplified, combined version, good for typical uses.
584 // Falls through on failure.
585 void check_klass_subtype(Register sub_klass,
586 Register super_klass,
587 Register temp_reg,
588 Label& L_success);
589
590 // method handles (JSR 292)
591 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
592
593 //----
594 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
595
596 // Debugging
597
598 // only if +VerifyOops
599 // TODO: Make these macros with file and line like sparc version!
600 void verify_oop(Register reg, const char* s = "broken oop");
601 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
602
603 // TODO: verify method and klass metadata (compare against vptr?)
604 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
605 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
606
607 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
608 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
609
610 // only if +VerifyFPU
611 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
612
613 // Verify or restore cpu control state after JNI call
614 void restore_cpu_control_state_after_jni();
615
616 // prints msg, dumps registers and stops execution
617 void stop(const char* msg);
618
619 // prints msg and continues
620 void warn(const char* msg);
621
622 // dumps registers and other state
623 void print_state();
624
625 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
626 static void debug64(char* msg, int64_t pc, int64_t regs[]);
627 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
628 static void print_state64(int64_t pc, int64_t regs[]);
629
630 void os_breakpoint();
631
632 void untested() { stop("untested"); }
633
634 void unimplemented(const char* what = "");
635
636 void should_not_reach_here() { stop("should not reach here"); }
637
638 void print_CPU_state();
639
640 // Stack overflow checking
641 void bang_stack_with_offset(int offset) {
642 // stack grows down, caller passes positive offset
643 assert(offset > 0, "must bang with negative offset");
644 movl(Address(rsp, (-offset)), rax);
645 }
646
647 // Writes to stack successive pages until offset reached to check for
648 // stack overflow + shadow pages. Also, clobbers tmp
649 void bang_stack_size(Register size, Register tmp);
650
651 // Check for reserved stack access in method being exited (for JIT)
652 void reserved_stack_check();
653
654 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
655 Register tmp,
656 int offset);
657
658 // If thread_reg is != noreg the code assumes the register passed contains
659 // the thread (required on 64 bit).
660 void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
661
662 void verify_tlab();
663
664 // Biased locking support
665 // lock_reg and obj_reg must be loaded up with the appropriate values.
666 // swap_reg must be rax, and is killed.
667 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
668 // be killed; if not supplied, push/pop will be used internally to
669 // allocate a temporary (inefficient, avoid if possible).
670 // Optional slow case is for implementations (interpreter and C1) which branch to
671 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
672 // Returns offset of first potentially-faulting instruction for null
673 // check info (currently consumed only by C1). If
674 // swap_reg_contains_mark is true then returns -1 as it is assumed
675 // the calling code has already passed any potential faults.
676 int biased_locking_enter(Register lock_reg, Register obj_reg,
677 Register swap_reg, Register tmp_reg,
678 bool swap_reg_contains_mark,
679 Label& done, Label* slow_case = NULL,
680 BiasedLockingCounters* counters = NULL);
681 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
682 #ifdef COMPILER2
683 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
684 // See full desription in macroAssembler_x86.cpp.
685 void fast_lock(Register obj, Register box, Register tmp,
686 Register scr, Register cx1, Register cx2,
687 BiasedLockingCounters* counters,
688 RTMLockingCounters* rtm_counters,
689 RTMLockingCounters* stack_rtm_counters,
690 Metadata* method_data,
691 bool use_rtm, bool profile_rtm);
692 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
693 #if INCLUDE_RTM_OPT
694 void rtm_counters_update(Register abort_status, Register rtm_counters);
695 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
696 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
697 RTMLockingCounters* rtm_counters,
698 Metadata* method_data);
699 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
700 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
701 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
702 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
703 void rtm_stack_locking(Register obj, Register tmp, Register scr,
704 Register retry_on_abort_count,
705 RTMLockingCounters* stack_rtm_counters,
706 Metadata* method_data, bool profile_rtm,
707 Label& DONE_LABEL, Label& IsInflated);
708 void rtm_inflated_locking(Register obj, Register box, Register tmp,
709 Register scr, Register retry_on_busy_count,
710 Register retry_on_abort_count,
711 RTMLockingCounters* rtm_counters,
712 Metadata* method_data, bool profile_rtm,
713 Label& DONE_LABEL);
714 #endif
715 #endif
716
717 Condition negate_condition(Condition cond);
718
719 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
720 // operands. In general the names are modified to avoid hiding the instruction in Assembler
721 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
722 // here in MacroAssembler. The major exception to this rule is call
723
724 // Arithmetics
725
726
727 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
728 void addptr(Address dst, Register src);
729
730 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
731 void addptr(Register dst, int32_t src);
732 void addptr(Register dst, Register src);
733 void addptr(Register dst, RegisterOrConstant src) {
734 if (src.is_constant()) addptr(dst, (int) src.as_constant());
735 else addptr(dst, src.as_register());
736 }
737
738 void andptr(Register dst, int32_t src);
739 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
740
741 void cmp8(AddressLiteral src1, int imm);
742
743 // renamed to drag out the casting of address to int32_t/intptr_t
744 void cmp32(Register src1, int32_t imm);
745
746 void cmp32(AddressLiteral src1, int32_t imm);
747 // compare reg - mem, or reg - &mem
748 void cmp32(Register src1, AddressLiteral src2);
749
750 void cmp32(Register src1, Address src2);
751
752 #ifndef _LP64
753 void cmpklass(Address dst, Metadata* obj);
754 void cmpklass(Register dst, Metadata* obj);
755 void cmpoop(Address dst, jobject obj);
756 void cmpoop_raw(Address dst, jobject obj);
757 #endif // _LP64
758
759 void cmpoop(Register src1, Register src2);
760 void cmpoop(Register src1, Address src2);
761 void cmpoop(Register dst, jobject obj);
762 void cmpoop_raw(Register dst, jobject obj);
763
764 // NOTE src2 must be the lval. This is NOT an mem-mem compare
765 void cmpptr(Address src1, AddressLiteral src2);
766
767 void cmpptr(Register src1, AddressLiteral src2);
768
769 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
770 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
771 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
772
773 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
774 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
775
776 // cmp64 to avoild hiding cmpq
777 void cmp64(Register src1, AddressLiteral src);
778
779 void cmpxchgptr(Register reg, Address adr);
780
781 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
782
783
784 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
785 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
786
787
788 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
789
790 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
791
792 void shlptr(Register dst, int32_t shift);
793 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
794
795 void shrptr(Register dst, int32_t shift);
796 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
797
798 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
799 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
800
801 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
802
803 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
804 void subptr(Register dst, int32_t src);
805 // Force generation of a 4 byte immediate value even if it fits into 8bit
806 void subptr_imm32(Register dst, int32_t src);
807 void subptr(Register dst, Register src);
808 void subptr(Register dst, RegisterOrConstant src) {
809 if (src.is_constant()) subptr(dst, (int) src.as_constant());
810 else subptr(dst, src.as_register());
811 }
812
813 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
814 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
815
816 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
817 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
818
819 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
820
821
822
823 // Helper functions for statistics gathering.
824 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
825 void cond_inc32(Condition cond, AddressLiteral counter_addr);
826 // Unconditional atomic increment.
827 void atomic_incl(Address counter_addr);
828 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
829 #ifdef _LP64
830 void atomic_incq(Address counter_addr);
831 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
832 #endif
833 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
834 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
835
836 void lea(Register dst, AddressLiteral adr);
837 void lea(Address dst, AddressLiteral adr);
838 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
839
840 void leal32(Register dst, Address src) { leal(dst, src); }
841
842 // Import other testl() methods from the parent class or else
843 // they will be hidden by the following overriding declaration.
844 using Assembler::testl;
845 void testl(Register dst, AddressLiteral src);
846
847 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
848 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
849 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
850 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
851
852 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
853 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
854 void testptr(Register src1, Register src2);
855
856 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
857 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
858
859 // Calls
860
861 void call(Label& L, relocInfo::relocType rtype);
862 void call(Register entry);
863
864 // NOTE: this call transfers to the effective address of entry NOT
865 // the address contained by entry. This is because this is more natural
866 // for jumps/calls.
867 void call(AddressLiteral entry);
868
869 // Emit the CompiledIC call idiom
870 void ic_call(address entry, jint method_index = 0);
871
872 // Jumps
873
874 // NOTE: these jumps tranfer to the effective address of dst NOT
875 // the address contained by dst. This is because this is more natural
876 // for jumps/calls.
877 void jump(AddressLiteral dst);
878 void jump_cc(Condition cc, AddressLiteral dst);
879
880 // 32bit can do a case table jump in one instruction but we no longer allow the base
881 // to be installed in the Address class. This jump will tranfers to the address
882 // contained in the location described by entry (not the address of entry)
883 void jump(ArrayAddress entry);
884
885 // Floating
886
887 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
888 void andpd(XMMRegister dst, AddressLiteral src);
889 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
890
891 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
892 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
893 void andps(XMMRegister dst, AddressLiteral src);
894
895 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
896 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
897 void comiss(XMMRegister dst, AddressLiteral src);
898
899 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
900 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
901 void comisd(XMMRegister dst, AddressLiteral src);
902
903 void fadd_s(Address src) { Assembler::fadd_s(src); }
904 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
905
906 void fldcw(Address src) { Assembler::fldcw(src); }
907 void fldcw(AddressLiteral src);
908
909 void fld_s(int index) { Assembler::fld_s(index); }
910 void fld_s(Address src) { Assembler::fld_s(src); }
911 void fld_s(AddressLiteral src);
912
913 void fld_d(Address src) { Assembler::fld_d(src); }
914 void fld_d(AddressLiteral src);
915
916 void fld_x(Address src) { Assembler::fld_x(src); }
917 void fld_x(AddressLiteral src);
918
919 void fmul_s(Address src) { Assembler::fmul_s(src); }
920 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
921
922 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
923 void ldmxcsr(AddressLiteral src);
924
925 #ifdef _LP64
926 private:
927 void sha256_AVX2_one_round_compute(
928 Register reg_old_h,
929 Register reg_a,
930 Register reg_b,
931 Register reg_c,
932 Register reg_d,
933 Register reg_e,
934 Register reg_f,
935 Register reg_g,
936 Register reg_h,
937 int iter);
938 void sha256_AVX2_four_rounds_compute_first(int start);
939 void sha256_AVX2_four_rounds_compute_last(int start);
940 void sha256_AVX2_one_round_and_sched(
941 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
942 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
943 XMMRegister xmm_2, /* ymm6 */
944 XMMRegister xmm_3, /* ymm7 */
945 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
946 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
947 Register reg_c, /* edi */
948 Register reg_d, /* esi */
949 Register reg_e, /* r8d */
950 Register reg_f, /* r9d */
951 Register reg_g, /* r10d */
952 Register reg_h, /* r11d */
953 int iter);
954
955 void addm(int disp, Register r1, Register r2);
956
957 public:
958 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
959 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
960 Register buf, Register state, Register ofs, Register limit, Register rsp,
961 bool multi_block, XMMRegister shuf_mask);
962 #endif
963
964 #ifdef _LP64
965 private:
966 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
967 Register e, Register f, Register g, Register h, int iteration);
968
969 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
970 Register a, Register b, Register c, Register d, Register e, Register f,
971 Register g, Register h, int iteration);
972
973 void addmq(int disp, Register r1, Register r2);
974 public:
975 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
976 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
977 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
978 XMMRegister shuf_mask);
979 #endif
980
981 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
982 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
983 Register buf, Register state, Register ofs, Register limit, Register rsp,
984 bool multi_block);
985
986 #ifdef _LP64
987 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
988 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
989 Register buf, Register state, Register ofs, Register limit, Register rsp,
990 bool multi_block, XMMRegister shuf_mask);
991 #else
992 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
993 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
994 Register buf, Register state, Register ofs, Register limit, Register rsp,
995 bool multi_block);
996 #endif
997
998 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
999 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1000 Register rax, Register rcx, Register rdx, Register tmp);
1001
1002 #ifdef _LP64
1003 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1004 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1005 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1006
1007 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1008 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1009 Register rax, Register rcx, Register rdx, Register r11);
1010
1011 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1012 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1013 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1014
1015 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1016 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1017 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1018 Register tmp3, Register tmp4);
1019
1020 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1021 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1022 Register rax, Register rcx, Register rdx, Register tmp1,
1023 Register tmp2, Register tmp3, Register tmp4);
1024 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1025 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1026 Register rax, Register rcx, Register rdx, Register tmp1,
1027 Register tmp2, Register tmp3, Register tmp4);
1028 #else
1029 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1030 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1031 Register rax, Register rcx, Register rdx, Register tmp1);
1032
1033 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1034 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1035 Register rax, Register rcx, Register rdx, Register tmp);
1036
1037 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1038 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1039 Register rdx, Register tmp);
1040
1041 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1042 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1043 Register rax, Register rbx, Register rdx);
1044
1045 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1046 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1047 Register rax, Register rcx, Register rdx, Register tmp);
1048
1049 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1050 Register edx, Register ebx, Register esi, Register edi,
1051 Register ebp, Register esp);
1052
1053 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1054 Register esi, Register edi, Register ebp, Register esp);
1055
1056 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1057 Register edx, Register ebx, Register esi, Register edi,
1058 Register ebp, Register esp);
1059
1060 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1061 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1062 Register rax, Register rcx, Register rdx, Register tmp);
1063 #endif
1064
1065 void increase_precision();
1066 void restore_precision();
1067
1068 private:
1069
1070 // these are private because users should be doing movflt/movdbl
1071
1072 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1073 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1074 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1075 void movss(XMMRegister dst, AddressLiteral src);
1076
1077 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1078 void movlpd(XMMRegister dst, AddressLiteral src);
1079
1080 public:
1081
1082 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1083 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1084 void addsd(XMMRegister dst, AddressLiteral src);
1085
1086 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1087 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1088 void addss(XMMRegister dst, AddressLiteral src);
1089
1090 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1091 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1092 void addpd(XMMRegister dst, AddressLiteral src);
1093
1094 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1095 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1096 void divsd(XMMRegister dst, AddressLiteral src);
1097
1098 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1099 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1100 void divss(XMMRegister dst, AddressLiteral src);
1101
1102 // Move Unaligned Double Quadword
1103 void movdqu(Address dst, XMMRegister src);
1104 void movdqu(XMMRegister dst, Address src);
1105 void movdqu(XMMRegister dst, XMMRegister src);
1106 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1107 // AVX Unaligned forms
1108 void vmovdqu(Address dst, XMMRegister src);
1109 void vmovdqu(XMMRegister dst, Address src);
1110 void vmovdqu(XMMRegister dst, XMMRegister src);
1111 void vmovdqu(XMMRegister dst, AddressLiteral src);
1112 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1113 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1114 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1115 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1116
1117 // Move Aligned Double Quadword
1118 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1119 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1120 void movdqa(XMMRegister dst, AddressLiteral src);
1121
1122 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1123 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1124 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1125 void movsd(XMMRegister dst, AddressLiteral src);
1126
1127 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1128 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1129 void mulpd(XMMRegister dst, AddressLiteral src);
1130
1131 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1132 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1133 void mulsd(XMMRegister dst, AddressLiteral src);
1134
1135 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1136 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1137 void mulss(XMMRegister dst, AddressLiteral src);
1138
1139 // Carry-Less Multiplication Quadword
1140 void pclmulldq(XMMRegister dst, XMMRegister src) {
1141 // 0x00 - multiply lower 64 bits [0:63]
1142 Assembler::pclmulqdq(dst, src, 0x00);
1143 }
1144 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1145 // 0x11 - multiply upper 64 bits [64:127]
1146 Assembler::pclmulqdq(dst, src, 0x11);
1147 }
1148
1149 void pcmpeqb(XMMRegister dst, XMMRegister src);
1150 void pcmpeqw(XMMRegister dst, XMMRegister src);
1151
1152 void pcmpestri(XMMRegister dst, Address src, int imm8);
1153 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1154
1155 void pmovzxbw(XMMRegister dst, XMMRegister src);
1156 void pmovzxbw(XMMRegister dst, Address src);
1157
1158 void pmovmskb(Register dst, XMMRegister src);
1159
1160 void ptest(XMMRegister dst, XMMRegister src);
1161
1162 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1163 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1164 void sqrtsd(XMMRegister dst, AddressLiteral src);
1165
1166 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1167 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1168 void sqrtss(XMMRegister dst, AddressLiteral src);
1169
1170 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1171 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1172 void subsd(XMMRegister dst, AddressLiteral src);
1173
1174 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1175 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1176 void subss(XMMRegister dst, AddressLiteral src);
1177
1178 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1179 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1180 void ucomiss(XMMRegister dst, AddressLiteral src);
1181
1182 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1183 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1184 void ucomisd(XMMRegister dst, AddressLiteral src);
1185
1186 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1187 void xorpd(XMMRegister dst, XMMRegister src);
1188 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1189 void xorpd(XMMRegister dst, AddressLiteral src);
1190
1191 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1192 void xorps(XMMRegister dst, XMMRegister src);
1193 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1194 void xorps(XMMRegister dst, AddressLiteral src);
1195
1196 // Shuffle Bytes
1197 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1198 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1199 void pshufb(XMMRegister dst, AddressLiteral src);
1200 // AVX 3-operands instructions
1201
1202 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1203 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1204 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1205
1206 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1207 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1208 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1209
1210 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1211 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1212
1213 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1214 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1215
1216 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1217 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1218
1219 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1220 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1221 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1222
1223 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1224 void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1225
1226 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1227
1228 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1229
1230 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1231 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1232
1233 void vpmovmskb(Register dst, XMMRegister src);
1234
1235 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1236 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1237
1238 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1239 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1240
1241 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1242 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1243
1244 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1245 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1246
1247 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1248 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1249
1250 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1251 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1252
1253 void vptest(XMMRegister dst, XMMRegister src);
1254
1255 void punpcklbw(XMMRegister dst, XMMRegister src);
1256 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1257
1258 void pshufd(XMMRegister dst, Address src, int mode);
1259 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1260
1261 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1262 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1263
1264 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1265 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1266 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1267
1268 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1269 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1270 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1271
1272 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1273 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1274 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1275
1276 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1277 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1278 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1279
1280 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1281 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1282 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1283
1284 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1285 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1286 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1287
1288 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1289 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1290 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1291
1292 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1293 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1294 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1295
1296 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1297 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1298
1299 // AVX Vector instructions
1300
1301 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1302 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1303 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1304
1305 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1306 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1307 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1308
1309 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1310 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1311 Assembler::vpxor(dst, nds, src, vector_len);
1312 else
1313 Assembler::vxorpd(dst, nds, src, vector_len);
1314 }
1315 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1316 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1317 Assembler::vpxor(dst, nds, src, vector_len);
1318 else
1319 Assembler::vxorpd(dst, nds, src, vector_len);
1320 }
1321
1322 // Simple version for AVX2 256bit vectors
1323 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1324 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1325
1326 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1327 if (UseAVX > 2) {
1328 Assembler::vinserti32x4(dst, dst, src, imm8);
1329 } else if (UseAVX > 1) {
1330 // vinserti128 is available only in AVX2
1331 Assembler::vinserti128(dst, nds, src, imm8);
1332 } else {
1333 Assembler::vinsertf128(dst, nds, src, imm8);
1334 }
1335 }
1336
1337 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1338 if (UseAVX > 2) {
1339 Assembler::vinserti32x4(dst, dst, src, imm8);
1340 } else if (UseAVX > 1) {
1341 // vinserti128 is available only in AVX2
1342 Assembler::vinserti128(dst, nds, src, imm8);
1343 } else {
1344 Assembler::vinsertf128(dst, nds, src, imm8);
1345 }
1346 }
1347
1348 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1349 if (UseAVX > 2) {
1350 Assembler::vextracti32x4(dst, src, imm8);
1351 } else if (UseAVX > 1) {
1352 // vextracti128 is available only in AVX2
1353 Assembler::vextracti128(dst, src, imm8);
1354 } else {
1355 Assembler::vextractf128(dst, src, imm8);
1356 }
1357 }
1358
1359 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1360 if (UseAVX > 2) {
1361 Assembler::vextracti32x4(dst, src, imm8);
1362 } else if (UseAVX > 1) {
1363 // vextracti128 is available only in AVX2
1364 Assembler::vextracti128(dst, src, imm8);
1365 } else {
1366 Assembler::vextractf128(dst, src, imm8);
1367 }
1368 }
1369
1370 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1371 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1372 vinserti128(dst, dst, src, 1);
1373 }
1374 void vinserti128_high(XMMRegister dst, Address src) {
1375 vinserti128(dst, dst, src, 1);
1376 }
1377 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1378 vextracti128(dst, src, 1);
1379 }
1380 void vextracti128_high(Address dst, XMMRegister src) {
1381 vextracti128(dst, src, 1);
1382 }
1383
1384 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1385 if (UseAVX > 2) {
1386 Assembler::vinsertf32x4(dst, dst, src, 1);
1387 } else {
1388 Assembler::vinsertf128(dst, dst, src, 1);
1389 }
1390 }
1391
1392 void vinsertf128_high(XMMRegister dst, Address src) {
1393 if (UseAVX > 2) {
1394 Assembler::vinsertf32x4(dst, dst, src, 1);
1395 } else {
1396 Assembler::vinsertf128(dst, dst, src, 1);
1397 }
1398 }
1399
1400 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1401 if (UseAVX > 2) {
1402 Assembler::vextractf32x4(dst, src, 1);
1403 } else {
1404 Assembler::vextractf128(dst, src, 1);
1405 }
1406 }
1407
1408 void vextractf128_high(Address dst, XMMRegister src) {
1409 if (UseAVX > 2) {
1410 Assembler::vextractf32x4(dst, src, 1);
1411 } else {
1412 Assembler::vextractf128(dst, src, 1);
1413 }
1414 }
1415
1416 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1417 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1418 Assembler::vinserti64x4(dst, dst, src, 1);
1419 }
1420 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1421 Assembler::vinsertf64x4(dst, dst, src, 1);
1422 }
1423 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1424 Assembler::vextracti64x4(dst, src, 1);
1425 }
1426 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1427 Assembler::vextractf64x4(dst, src, 1);
1428 }
1429 void vextractf64x4_high(Address dst, XMMRegister src) {
1430 Assembler::vextractf64x4(dst, src, 1);
1431 }
1432 void vinsertf64x4_high(XMMRegister dst, Address src) {
1433 Assembler::vinsertf64x4(dst, dst, src, 1);
1434 }
1435
1436 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1437 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1438 vinserti128(dst, dst, src, 0);
1439 }
1440 void vinserti128_low(XMMRegister dst, Address src) {
1441 vinserti128(dst, dst, src, 0);
1442 }
1443 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1444 vextracti128(dst, src, 0);
1445 }
1446 void vextracti128_low(Address dst, XMMRegister src) {
1447 vextracti128(dst, src, 0);
1448 }
1449
1450 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1451 if (UseAVX > 2) {
1452 Assembler::vinsertf32x4(dst, dst, src, 0);
1453 } else {
1454 Assembler::vinsertf128(dst, dst, src, 0);
1455 }
1456 }
1457
1458 void vinsertf128_low(XMMRegister dst, Address src) {
1459 if (UseAVX > 2) {
1460 Assembler::vinsertf32x4(dst, dst, src, 0);
1461 } else {
1462 Assembler::vinsertf128(dst, dst, src, 0);
1463 }
1464 }
1465
1466 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1467 if (UseAVX > 2) {
1468 Assembler::vextractf32x4(dst, src, 0);
1469 } else {
1470 Assembler::vextractf128(dst, src, 0);
1471 }
1472 }
1473
1474 void vextractf128_low(Address dst, XMMRegister src) {
1475 if (UseAVX > 2) {
1476 Assembler::vextractf32x4(dst, src, 0);
1477 } else {
1478 Assembler::vextractf128(dst, src, 0);
1479 }
1480 }
1481
1482 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1483 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1484 Assembler::vinserti64x4(dst, dst, src, 0);
1485 }
1486 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1487 Assembler::vinsertf64x4(dst, dst, src, 0);
1488 }
1489 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1490 Assembler::vextracti64x4(dst, src, 0);
1491 }
1492 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1493 Assembler::vextractf64x4(dst, src, 0);
1494 }
1495 void vextractf64x4_low(Address dst, XMMRegister src) {
1496 Assembler::vextractf64x4(dst, src, 0);
1497 }
1498 void vinsertf64x4_low(XMMRegister dst, Address src) {
1499 Assembler::vinsertf64x4(dst, dst, src, 0);
1500 }
1501
1502 // Carry-Less Multiplication Quadword
1503 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1504 // 0x00 - multiply lower 64 bits [0:63]
1505 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1506 }
1507 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1508 // 0x11 - multiply upper 64 bits [64:127]
1509 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1510 }
1511 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1512 // 0x00 - multiply lower 64 bits [0:63]
1513 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1514 }
1515 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1516 // 0x11 - multiply upper 64 bits [64:127]
1517 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1518 }
1519
1520 // Data
1521
1522 void cmov32( Condition cc, Register dst, Address src);
1523 void cmov32( Condition cc, Register dst, Register src);
1524
1525 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1526
1527 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1528 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1529
1530 void movoop(Register dst, jobject obj);
1531 void movoop(Address dst, jobject obj);
1532
1533 void mov_metadata(Register dst, Metadata* obj);
1534 void mov_metadata(Address dst, Metadata* obj);
1535
1536 void movptr(ArrayAddress dst, Register src);
1537 // can this do an lea?
1538 void movptr(Register dst, ArrayAddress src);
1539
1540 void movptr(Register dst, Address src);
1541
1542 #ifdef _LP64
1543 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1544 #else
1545 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1546 #endif
1547
1548 void movptr(Register dst, intptr_t src);
1549 void movptr(Register dst, Register src);
1550 void movptr(Address dst, intptr_t src);
1551
1552 void movptr(Address dst, Register src);
1553
1554 void movptr(Register dst, RegisterOrConstant src) {
1555 if (src.is_constant()) movptr(dst, src.as_constant());
1556 else movptr(dst, src.as_register());
1557 }
1558
1559 #ifdef _LP64
1560 // Generally the next two are only used for moving NULL
1561 // Although there are situations in initializing the mark word where
1562 // they could be used. They are dangerous.
1563
1564 // They only exist on LP64 so that int32_t and intptr_t are not the same
1565 // and we have ambiguous declarations.
1566
1567 void movptr(Address dst, int32_t imm32);
1568 void movptr(Register dst, int32_t imm32);
1569 #endif // _LP64
1570
1571 // to avoid hiding movl
1572 void mov32(AddressLiteral dst, Register src);
1573 void mov32(Register dst, AddressLiteral src);
1574
1575 // to avoid hiding movb
1576 void movbyte(ArrayAddress dst, int src);
1577
1578 // Import other mov() methods from the parent class or else
1579 // they will be hidden by the following overriding declaration.
1580 using Assembler::movdl;
1581 using Assembler::movq;
1582 void movdl(XMMRegister dst, AddressLiteral src);
1583 void movq(XMMRegister dst, AddressLiteral src);
1584
1585 // Can push value or effective address
1586 void pushptr(AddressLiteral src);
1587
1588 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1589 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1590
1591 void pushoop(jobject obj);
1592 void pushklass(Metadata* obj);
1593
1594 // sign extend as need a l to ptr sized element
1595 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1596 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1597
1598 // C2 compiled method's prolog code.
1599 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub);
1600
1601 // clear memory of size 'cnt' qwords, starting at 'base';
1602 // if 'is_large' is set, do not try to produce short loop
1603 void clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, bool is_large, bool word_copy_only);
1604
1605 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1606 void xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp);
1607
1608 #ifdef COMPILER2
1609 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1610 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1611
1612 // IndexOf strings.
1613 // Small strings are loaded through stack if they cross page boundary.
1614 void string_indexof(Register str1, Register str2,
1615 Register cnt1, Register cnt2,
1616 int int_cnt2, Register result,
1617 XMMRegister vec, Register tmp,
1618 int ae);
1619
1620 // IndexOf for constant substrings with size >= 8 elements
1621 // which don't need to be loaded through stack.
1622 void string_indexofC8(Register str1, Register str2,
1623 Register cnt1, Register cnt2,
1624 int int_cnt2, Register result,
1625 XMMRegister vec, Register tmp,
1626 int ae);
1627
1628 // Smallest code: we don't need to load through stack,
1629 // check string tail.
1630
1631 // helper function for string_compare
1632 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1633 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1634 Address::ScaleFactor scale2, Register index, int ae);
1635 // Compare strings.
1636 void string_compare(Register str1, Register str2,
1637 Register cnt1, Register cnt2, Register result,
1638 XMMRegister vec1, int ae);
1639
1640 // Search for Non-ASCII character (Negative byte value) in a byte array,
1641 // return true if it has any and false otherwise.
1642 void has_negatives(Register ary1, Register len,
1643 Register result, Register tmp1,
1644 XMMRegister vec1, XMMRegister vec2);
1645
1646 // Compare char[] or byte[] arrays.
1647 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1648 Register limit, Register result, Register chr,
1649 XMMRegister vec1, XMMRegister vec2, bool is_char);
1650
1651 #endif
1652
1653 // Fill primitive arrays
1654 void generate_fill(BasicType t, bool aligned,
1655 Register to, Register value, Register count,
1656 Register rtmp, XMMRegister xtmp);
1657
1658 void encode_iso_array(Register src, Register dst, Register len,
1659 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1660 XMMRegister tmp4, Register tmp5, Register result);
1661
1662 #ifdef _LP64
1663 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1664 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1665 Register y, Register y_idx, Register z,
1666 Register carry, Register product,
1667 Register idx, Register kdx);
1668 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1669 Register yz_idx, Register idx,
1670 Register carry, Register product, int offset);
1671 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1672 Register carry, Register carry2,
1673 Register idx, Register jdx,
1674 Register yz_idx1, Register yz_idx2,
1675 Register tmp, Register tmp3, Register tmp4);
1676 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1677 Register yz_idx, Register idx, Register jdx,
1678 Register carry, Register product,
1679 Register carry2);
1680 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1681 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1682 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1683 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1684 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1685 Register tmp2);
1686 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1687 Register rdxReg, Register raxReg);
1688 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1689 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1690 Register tmp3, Register tmp4);
1691 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1692 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1693
1694 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1695 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1696 Register raxReg);
1697 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1698 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1699 Register raxReg);
1700 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1701 Register result, Register tmp1, Register tmp2,
1702 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1703 #endif
1704
1705 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1706 void update_byte_crc32(Register crc, Register val, Register table);
1707 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1708 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1709 // Note on a naming convention:
1710 // Prefix w = register only used on a Westmere+ architecture
1711 // Prefix n = register only used on a Nehalem architecture
1712 #ifdef _LP64
1713 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1714 Register tmp1, Register tmp2, Register tmp3);
1715 #else
1716 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1717 Register tmp1, Register tmp2, Register tmp3,
1718 XMMRegister xtmp1, XMMRegister xtmp2);
1719 #endif
1720 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1721 Register in_out,
1722 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1723 XMMRegister w_xtmp2,
1724 Register tmp1,
1725 Register n_tmp2, Register n_tmp3);
1726 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1727 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1728 Register tmp1, Register tmp2,
1729 Register n_tmp3);
1730 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1731 Register in_out1, Register in_out2, Register in_out3,
1732 Register tmp1, Register tmp2, Register tmp3,
1733 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1734 Register tmp4, Register tmp5,
1735 Register n_tmp6);
1736 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1737 Register tmp1, Register tmp2, Register tmp3,
1738 Register tmp4, Register tmp5, Register tmp6,
1739 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1740 bool is_pclmulqdq_supported);
1741 // Fold 128-bit data chunk
1742 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1743 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1744 // Fold 8-bit data
1745 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1746 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1747 void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1748
1749 // Compress char[] array to byte[].
1750 void char_array_compress(Register src, Register dst, Register len,
1751 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1752 XMMRegister tmp4, Register tmp5, Register result);
1753
1754 // Inflate byte[] array to char[].
1755 void byte_array_inflate(Register src, Register dst, Register len,
1756 XMMRegister tmp1, Register tmp2);
1757
1758 };
1759
1760 /**
1761 * class SkipIfEqual:
1762 *
1763 * Instantiating this class will result in assembly code being output that will
1764 * jump around any code emitted between the creation of the instance and it's
1765 * automatic destruction at the end of a scope block, depending on the value of
1766 * the flag passed to the constructor, which will be checked at run-time.
1767 */
1768 class SkipIfEqual {
1769 private:
1770 MacroAssembler* _masm;
1771 Label _label;
1772
1773 public:
1774 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1775 ~SkipIfEqual();
1776 };
1777
1778 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP