11989 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11990 %{
11991 match(Set cr (CmpI (AndI src con) zero));
11992
11993 format %{ "testl $src, $con" %}
11994 opcode(0xF7, 0x00);
11995 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11996 ins_pipe(ialu_cr_reg_imm);
11997 %}
11998
11999 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
12000 %{
12001 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
12002
12003 format %{ "testl $src, $mem" %}
12004 opcode(0x85);
12005 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
12006 ins_pipe(ialu_cr_reg_mem);
12007 %}
12008
12009 // Unsigned compare Instructions; really, same as signed except they
12010 // produce an rFlagsRegU instead of rFlagsReg.
12011 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
12012 %{
12013 match(Set cr (CmpU op1 op2));
12014
12015 format %{ "cmpl $op1, $op2\t# unsigned" %}
12016 opcode(0x3B); /* Opcode 3B /r */
12017 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
12018 ins_pipe(ialu_cr_reg_reg);
12019 %}
12020
12021 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
12022 %{
12023 match(Set cr (CmpU op1 op2));
12024
12025 format %{ "cmpl $op1, $op2\t# unsigned" %}
12026 opcode(0x81,0x07); /* Opcode 81 /7 */
12027 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
12028 ins_pipe(ialu_cr_reg_imm);
12290
12291 format %{ "testq $src, $con\t# long" %}
12292 opcode(0xF7, 0x00);
12293 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
12294 ins_pipe(ialu_cr_reg_imm);
12295 %}
12296
12297 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
12298 %{
12299 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
12300
12301 format %{ "testq $src, $mem" %}
12302 opcode(0x85);
12303 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12304 ins_pipe(ialu_cr_reg_mem);
12305 %}
12306
12307 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
12308 %{
12309 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
12310
12311 format %{ "testq $src, $mem" %}
12312 opcode(0x85);
12313 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12314 ins_pipe(ialu_cr_reg_mem);
12315 %}
12316
12317 // Manifest a CmpL result in an integer register. Very painful.
12318 // This is the test to avoid.
12319 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12320 %{
12321 match(Set dst (CmpL3 src1 src2));
12322 effect(KILL flags);
12323
12324 ins_cost(275); // XXX
12325 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12326 "movl $dst, -1\n\t"
12327 "jl,s done\n\t"
12328 "setne $dst\n\t"
12329 "movzbl $dst, $dst\n\t"
|
11989 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11990 %{
11991 match(Set cr (CmpI (AndI src con) zero));
11992
11993 format %{ "testl $src, $con" %}
11994 opcode(0xF7, 0x00);
11995 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11996 ins_pipe(ialu_cr_reg_imm);
11997 %}
11998
11999 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
12000 %{
12001 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
12002
12003 format %{ "testl $src, $mem" %}
12004 opcode(0x85);
12005 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
12006 ins_pipe(ialu_cr_reg_mem);
12007 %}
12008
12009 // Fold array properties check
12010 instruct testI_mem_imm(rFlagsReg cr, memory mem, immI con, immI0 zero)
12011 %{
12012 match(Set cr (CmpI (AndI (CastN2I (LoadNKlass mem)) con) zero));
12013
12014 format %{ "testl $mem, $con" %}
12015 opcode(0xF7, 0x00);
12016 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(con));
12017 ins_pipe(ialu_mem_imm);
12018 %}
12019
12020 // Unsigned compare Instructions; really, same as signed except they
12021 // produce an rFlagsRegU instead of rFlagsReg.
12022 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
12023 %{
12024 match(Set cr (CmpU op1 op2));
12025
12026 format %{ "cmpl $op1, $op2\t# unsigned" %}
12027 opcode(0x3B); /* Opcode 3B /r */
12028 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
12029 ins_pipe(ialu_cr_reg_reg);
12030 %}
12031
12032 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
12033 %{
12034 match(Set cr (CmpU op1 op2));
12035
12036 format %{ "cmpl $op1, $op2\t# unsigned" %}
12037 opcode(0x81,0x07); /* Opcode 81 /7 */
12038 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
12039 ins_pipe(ialu_cr_reg_imm);
12301
12302 format %{ "testq $src, $con\t# long" %}
12303 opcode(0xF7, 0x00);
12304 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
12305 ins_pipe(ialu_cr_reg_imm);
12306 %}
12307
12308 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
12309 %{
12310 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
12311
12312 format %{ "testq $src, $mem" %}
12313 opcode(0x85);
12314 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12315 ins_pipe(ialu_cr_reg_mem);
12316 %}
12317
12318 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
12319 %{
12320 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
12321
12322 format %{ "testq $src, $mem" %}
12323 opcode(0x85);
12324 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12325 ins_pipe(ialu_cr_reg_mem);
12326 %}
12327
12328 // Fold array properties check
12329 instruct testL_reg_mem3(rFlagsReg cr, memory mem, rRegL src, immL0 zero)
12330 %{
12331 match(Set cr (CmpL (AndL (CastP2X (LoadKlass mem)) src) zero));
12332
12333 format %{ "testq $src, $mem" %}
12334 opcode(0x85);
12335 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12336 ins_pipe(ialu_cr_reg_mem);
12337 %}
12338
12339 // Manifest a CmpL result in an integer register. Very painful.
12340 // This is the test to avoid.
12341 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12342 %{
12343 match(Set dst (CmpL3 src1 src2));
12344 effect(KILL flags);
12345
12346 ins_cost(275); // XXX
12347 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12348 "movl $dst, -1\n\t"
12349 "jl,s done\n\t"
12350 "setne $dst\n\t"
12351 "movzbl $dst, $dst\n\t"
|