--- old/src/hotspot/cpu/x86/x86_64.ad	2019-10-08 15:53:41.035651665 +0200
+++ new/src/hotspot/cpu/x86/x86_64.ad	2019-10-08 15:53:40.735651669 +0200
@@ -3937,6 +3937,22 @@
   %}
 %}
 
+// Indirect Narrow Oop Operand
+operand indCompressedOop(rRegN reg) %{
+  predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
+  constraint(ALLOC_IN_RC(ptr_reg));
+  match(DecodeN reg);
+
+  op_cost(10);
+  format %{"[R12 + $reg << 3] (compressed oop addressing)" %}
+  interface(MEMORY_INTER) %{
+    base(0xc); // R12
+    index($reg);
+    scale(0x3);
+    disp(0x0);
+  %}
+%}
+
 // Indirect Narrow Oop Plus Offset Operand
 // Note: x86 architecture doesn't support "scale * index + offset" without a base
 // we can't free r12 even with CompressedOops::base() == NULL.
@@ -4473,7 +4489,7 @@
 
 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
                indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
-               indCompressedOopOffset,
+               indCompressedOop, indCompressedOopOffset,
                indirectNarrow, indOffset8Narrow, indOffset32Narrow,
                indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
                indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
@@ -12069,6 +12085,21 @@
   ins_pipe(ialu_mem_imm);
 %}
 
+// Clear array property bits
+instruct clear_property_bits(rRegN dst, memory mem, immU31 mask, rFlagsReg cr)
+%{
+  match(Set dst (CastI2N (AndI (CastN2I (LoadNKlass mem)) mask)));
+  effect(KILL cr);
+
+  format %{ "movl    $dst, $mem\t# clear property bits\n\t"
+            "andl    $dst, $mask" %}
+  ins_encode %{
+    __ movl($dst$$Register, $mem$$Address);
+    __ andl($dst$$Register, $mask$$constant);
+  %}
+  ins_pipe(ialu_reg_mem);
+%}
+
 // Unsigned compare Instructions; really, same as signed except they
 // produce an rFlagsRegU instead of rFlagsReg.
 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
@@ -12382,7 +12413,7 @@
 %{
   match(Set cr (CmpL (AndL (CastP2X (LoadKlass mem)) src) zero));
 
-  format %{ "testq   $src, $mem" %}
+  format %{ "testq   $src, $mem\t# test array properties" %}
   opcode(0x85);
   ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
   ins_pipe(ialu_cr_reg_mem);