3920 %}
3921 %}
3922
3923 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3924 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3925 %{
3926 constraint(ALLOC_IN_RC(ptr_reg));
3927 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3928 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3929
3930 op_cost(10);
3931 format %{"[$reg + $off + $idx << $scale]" %}
3932 interface(MEMORY_INTER) %{
3933 base($reg);
3934 index($idx);
3935 scale($scale);
3936 disp($off);
3937 %}
3938 %}
3939
3940 // Indirect Narrow Oop Plus Offset Operand
3941 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3942 // we can't free r12 even with CompressedOops::base() == NULL.
3943 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3944 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3945 constraint(ALLOC_IN_RC(ptr_reg));
3946 match(AddP (DecodeN reg) off);
3947
3948 op_cost(10);
3949 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3950 interface(MEMORY_INTER) %{
3951 base(0xc); // R12
3952 index($reg);
3953 scale(0x3);
3954 disp($off);
3955 %}
3956 %}
3957
3958 // Indirect Memory Operand
3959 operand indirectNarrow(rRegN reg)
4456 match(VecX);
4457 format%{%}
4458 interface(REG_INTER);
4459 %}
4460 operand rxmm31() %{
4461 constraint(ALLOC_IN_RC(xmm31_reg));
4462 match(VecX);
4463 format%{%}
4464 interface(REG_INTER);
4465 %}
4466
4467 //----------OPERAND CLASSES----------------------------------------------------
4468 // Operand Classes are groups of operands that are used as to simplify
4469 // instruction definitions by not requiring the AD writer to specify separate
4470 // instructions for every form of operand when the instruction accepts
4471 // multiple operand types with the same basic encoding and format. The classic
4472 // case of this is memory operands.
4473
4474 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4475 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4476 indCompressedOopOffset,
4477 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4478 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4479 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4480
4481 //----------PIPELINE-----------------------------------------------------------
4482 // Rules which define the behavior of the target architectures pipeline.
4483 pipeline %{
4484
4485 //----------ATTRIBUTES---------------------------------------------------------
4486 attributes %{
4487 variable_size_instructions; // Fixed size instructions
4488 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4489 instruction_unit_size = 1; // An instruction is 1 bytes long
4490 instruction_fetch_unit_size = 16; // The processor fetches one line
4491 instruction_fetch_units = 1; // of 16 bytes
4492
4493 // List of nop instructions
4494 nops( MachNop );
4495 %}
4496
12052 %{
12053 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
12054
12055 format %{ "testl $src, $mem" %}
12056 opcode(0x85);
12057 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
12058 ins_pipe(ialu_cr_reg_mem);
12059 %}
12060
12061 // Fold array properties check
12062 instruct testI_mem_imm(rFlagsReg cr, memory mem, immI con, immI0 zero)
12063 %{
12064 match(Set cr (CmpI (AndI (CastN2I (LoadNKlass mem)) con) zero));
12065
12066 format %{ "testl $mem, $con" %}
12067 opcode(0xF7, 0x00);
12068 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(con));
12069 ins_pipe(ialu_mem_imm);
12070 %}
12071
12072 // Unsigned compare Instructions; really, same as signed except they
12073 // produce an rFlagsRegU instead of rFlagsReg.
12074 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
12075 %{
12076 match(Set cr (CmpU op1 op2));
12077
12078 format %{ "cmpl $op1, $op2\t# unsigned" %}
12079 opcode(0x3B); /* Opcode 3B /r */
12080 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
12081 ins_pipe(ialu_cr_reg_reg);
12082 %}
12083
12084 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
12085 %{
12086 match(Set cr (CmpU op1 op2));
12087
12088 format %{ "cmpl $op1, $op2\t# unsigned" %}
12089 opcode(0x81,0x07); /* Opcode 81 /7 */
12090 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
12091 ins_pipe(ialu_cr_reg_imm);
12365 opcode(0x85);
12366 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12367 ins_pipe(ialu_cr_reg_mem);
12368 %}
12369
12370 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
12371 %{
12372 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
12373
12374 format %{ "testq $src, $mem" %}
12375 opcode(0x85);
12376 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12377 ins_pipe(ialu_cr_reg_mem);
12378 %}
12379
12380 // Fold array properties check
12381 instruct testL_reg_mem3(rFlagsReg cr, memory mem, rRegL src, immL0 zero)
12382 %{
12383 match(Set cr (CmpL (AndL (CastP2X (LoadKlass mem)) src) zero));
12384
12385 format %{ "testq $src, $mem" %}
12386 opcode(0x85);
12387 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12388 ins_pipe(ialu_cr_reg_mem);
12389 %}
12390
12391 // Manifest a CmpL result in an integer register. Very painful.
12392 // This is the test to avoid.
12393 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12394 %{
12395 match(Set dst (CmpL3 src1 src2));
12396 effect(KILL flags);
12397
12398 ins_cost(275); // XXX
12399 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12400 "movl $dst, -1\n\t"
12401 "jl,s done\n\t"
12402 "setne $dst\n\t"
12403 "movzbl $dst, $dst\n\t"
12404 "done:" %}
12405 ins_encode(cmpl3_flag(src1, src2, dst));
|
3920 %}
3921 %}
3922
3923 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3924 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3925 %{
3926 constraint(ALLOC_IN_RC(ptr_reg));
3927 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3928 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3929
3930 op_cost(10);
3931 format %{"[$reg + $off + $idx << $scale]" %}
3932 interface(MEMORY_INTER) %{
3933 base($reg);
3934 index($idx);
3935 scale($scale);
3936 disp($off);
3937 %}
3938 %}
3939
3940 // Indirect Narrow Oop Operand
3941 operand indCompressedOop(rRegN reg) %{
3942 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3943 constraint(ALLOC_IN_RC(ptr_reg));
3944 match(DecodeN reg);
3945
3946 op_cost(10);
3947 format %{"[R12 + $reg << 3] (compressed oop addressing)" %}
3948 interface(MEMORY_INTER) %{
3949 base(0xc); // R12
3950 index($reg);
3951 scale(0x3);
3952 disp(0x0);
3953 %}
3954 %}
3955
3956 // Indirect Narrow Oop Plus Offset Operand
3957 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3958 // we can't free r12 even with CompressedOops::base() == NULL.
3959 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3960 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3961 constraint(ALLOC_IN_RC(ptr_reg));
3962 match(AddP (DecodeN reg) off);
3963
3964 op_cost(10);
3965 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3966 interface(MEMORY_INTER) %{
3967 base(0xc); // R12
3968 index($reg);
3969 scale(0x3);
3970 disp($off);
3971 %}
3972 %}
3973
3974 // Indirect Memory Operand
3975 operand indirectNarrow(rRegN reg)
4472 match(VecX);
4473 format%{%}
4474 interface(REG_INTER);
4475 %}
4476 operand rxmm31() %{
4477 constraint(ALLOC_IN_RC(xmm31_reg));
4478 match(VecX);
4479 format%{%}
4480 interface(REG_INTER);
4481 %}
4482
4483 //----------OPERAND CLASSES----------------------------------------------------
4484 // Operand Classes are groups of operands that are used as to simplify
4485 // instruction definitions by not requiring the AD writer to specify separate
4486 // instructions for every form of operand when the instruction accepts
4487 // multiple operand types with the same basic encoding and format. The classic
4488 // case of this is memory operands.
4489
4490 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4491 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4492 indCompressedOop, indCompressedOopOffset,
4493 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4494 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4495 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4496
4497 //----------PIPELINE-----------------------------------------------------------
4498 // Rules which define the behavior of the target architectures pipeline.
4499 pipeline %{
4500
4501 //----------ATTRIBUTES---------------------------------------------------------
4502 attributes %{
4503 variable_size_instructions; // Fixed size instructions
4504 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4505 instruction_unit_size = 1; // An instruction is 1 bytes long
4506 instruction_fetch_unit_size = 16; // The processor fetches one line
4507 instruction_fetch_units = 1; // of 16 bytes
4508
4509 // List of nop instructions
4510 nops( MachNop );
4511 %}
4512
12068 %{
12069 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
12070
12071 format %{ "testl $src, $mem" %}
12072 opcode(0x85);
12073 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
12074 ins_pipe(ialu_cr_reg_mem);
12075 %}
12076
12077 // Fold array properties check
12078 instruct testI_mem_imm(rFlagsReg cr, memory mem, immI con, immI0 zero)
12079 %{
12080 match(Set cr (CmpI (AndI (CastN2I (LoadNKlass mem)) con) zero));
12081
12082 format %{ "testl $mem, $con" %}
12083 opcode(0xF7, 0x00);
12084 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(con));
12085 ins_pipe(ialu_mem_imm);
12086 %}
12087
12088 // Clear array property bits
12089 instruct clear_property_bits(rRegN dst, memory mem, immU31 mask, rFlagsReg cr)
12090 %{
12091 match(Set dst (CastI2N (AndI (CastN2I (LoadNKlass mem)) mask)));
12092 effect(KILL cr);
12093
12094 format %{ "movl $dst, $mem\t# clear property bits\n\t"
12095 "andl $dst, $mask" %}
12096 ins_encode %{
12097 __ movl($dst$$Register, $mem$$Address);
12098 __ andl($dst$$Register, $mask$$constant);
12099 %}
12100 ins_pipe(ialu_reg_mem);
12101 %}
12102
12103 // Unsigned compare Instructions; really, same as signed except they
12104 // produce an rFlagsRegU instead of rFlagsReg.
12105 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
12106 %{
12107 match(Set cr (CmpU op1 op2));
12108
12109 format %{ "cmpl $op1, $op2\t# unsigned" %}
12110 opcode(0x3B); /* Opcode 3B /r */
12111 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
12112 ins_pipe(ialu_cr_reg_reg);
12113 %}
12114
12115 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
12116 %{
12117 match(Set cr (CmpU op1 op2));
12118
12119 format %{ "cmpl $op1, $op2\t# unsigned" %}
12120 opcode(0x81,0x07); /* Opcode 81 /7 */
12121 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
12122 ins_pipe(ialu_cr_reg_imm);
12396 opcode(0x85);
12397 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12398 ins_pipe(ialu_cr_reg_mem);
12399 %}
12400
12401 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
12402 %{
12403 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
12404
12405 format %{ "testq $src, $mem" %}
12406 opcode(0x85);
12407 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12408 ins_pipe(ialu_cr_reg_mem);
12409 %}
12410
12411 // Fold array properties check
12412 instruct testL_reg_mem3(rFlagsReg cr, memory mem, rRegL src, immL0 zero)
12413 %{
12414 match(Set cr (CmpL (AndL (CastP2X (LoadKlass mem)) src) zero));
12415
12416 format %{ "testq $src, $mem\t# test array properties" %}
12417 opcode(0x85);
12418 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12419 ins_pipe(ialu_cr_reg_mem);
12420 %}
12421
12422 // Manifest a CmpL result in an integer register. Very painful.
12423 // This is the test to avoid.
12424 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12425 %{
12426 match(Set dst (CmpL3 src1 src2));
12427 effect(KILL flags);
12428
12429 ins_cost(275); // XXX
12430 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12431 "movl $dst, -1\n\t"
12432 "jl,s done\n\t"
12433 "setne $dst\n\t"
12434 "movzbl $dst, $dst\n\t"
12435 "done:" %}
12436 ins_encode(cmpl3_flag(src1, src2, dst));
|