src/hotspot/cpu/x86/x86_64.ad

*** 3935,3944 ****
--- 3935,3960 ----
      scale($scale);
      disp($off);
    %}
  %}
  
+ // Indirect Narrow Oop Operand
+ operand indCompressedOop(rRegN reg) %{
+   predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
+   constraint(ALLOC_IN_RC(ptr_reg));
+   match(DecodeN reg);
+ 
+   op_cost(10);
+   format %{"[R12 + $reg << 3] (compressed oop addressing)" %}
+   interface(MEMORY_INTER) %{
+     base(0xc); // R12
+     index($reg);
+     scale(0x3);
+     disp(0x0);
+   %}
+ %}
+ 
  // Indirect Narrow Oop Plus Offset Operand
  // Note: x86 architecture doesn't support "scale * index + offset" without a base
  // we can't free r12 even with CompressedOops::base() == NULL.
  operand indCompressedOopOffset(rRegN reg, immL32 off) %{
    predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
*** 4471,4481 ****
  // multiple operand types with the same basic encoding and format.  The classic
  // case of this is memory operands.
  
  opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
                 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
!                indCompressedOopOffset,
                 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
                 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
                 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
  
  //----------PIPELINE-----------------------------------------------------------
--- 4487,4497 ----
  // multiple operand types with the same basic encoding and format.  The classic
  // case of this is memory operands.
  
  opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
                 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
!                indCompressedOop, indCompressedOopOffset,
                 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
                 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
                 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
  
  //----------PIPELINE-----------------------------------------------------------
*** 12067,12076 ****
--- 12083,12107 ----
    opcode(0xF7, 0x00);
    ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(con));
    ins_pipe(ialu_mem_imm);
  %}
  
+ // Clear array property bits
+ instruct clear_property_bits(rRegN dst, memory mem, immU31 mask, rFlagsReg cr)
+ %{
+   match(Set dst (CastI2N (AndI (CastN2I (LoadNKlass mem)) mask)));
+   effect(KILL cr);
+ 
+   format %{ "movl    $dst, $mem\t# clear property bits\n\t"
+             "andl    $dst, $mask" %}
+   ins_encode %{
+     __ movl($dst$$Register, $mem$$Address);
+     __ andl($dst$$Register, $mask$$constant);
+   %}
+   ins_pipe(ialu_reg_mem);
+ %}
+ 
  // Unsigned compare Instructions; really, same as signed except they
  // produce an rFlagsRegU instead of rFlagsReg.
  instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
  %{
    match(Set cr (CmpU op1 op2));
*** 12380,12390 ****
  // Fold array properties check
  instruct testL_reg_mem3(rFlagsReg cr, memory mem, rRegL src, immL0 zero)
  %{
    match(Set cr (CmpL (AndL (CastP2X (LoadKlass mem)) src) zero));
  
!   format %{ "testq   $src, $mem" %}
    opcode(0x85);
    ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
    ins_pipe(ialu_cr_reg_mem);
  %}
  
--- 12411,12421 ----
  // Fold array properties check
  instruct testL_reg_mem3(rFlagsReg cr, memory mem, rRegL src, immL0 zero)
  %{
    match(Set cr (CmpL (AndL (CastP2X (LoadKlass mem)) src) zero));
  
!   format %{ "testq   $src, $mem\t# test array properties" %}
    opcode(0x85);
    ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
    ins_pipe(ialu_cr_reg_mem);
  %}