107 sra_op3 = 0x27,
108 srax_op3 = 0x27,
109 rdreg_op3 = 0x28,
110 membar_op3 = 0x28,
111
112 flushw_op3 = 0x2b,
113 movcc_op3 = 0x2c,
114 sdivx_op3 = 0x2d,
115 popc_op3 = 0x2e,
116 movr_op3 = 0x2f,
117
118 sir_op3 = 0x30,
119 wrreg_op3 = 0x30,
120 saved_op3 = 0x31,
121
122 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36,
126 sha_op3 = 0x36,
127 alignaddr_op3 = 0x36,
128 faligndata_op3 = 0x36,
129 flog3_op3 = 0x36,
130 edge_op3 = 0x36,
131 fzero_op3 = 0x36,
132 fsrc_op3 = 0x36,
133 fnot_op3 = 0x36,
134 xmulx_op3 = 0x36,
135 crc32c_op3 = 0x36,
136 impdep2_op3 = 0x37,
137 stpartialf_op3 = 0x37,
138 jmpl_op3 = 0x38,
139 rett_op3 = 0x39,
140 trap_op3 = 0x3a,
141 flush_op3 = 0x3b,
142 save_op3 = 0x3c,
143 restore_op3 = 0x3d,
144 done_op3 = 0x3e,
145 retry_op3 = 0x3e,
146
177 casa_op3 = 0x3c,
178 casxa_op3 = 0x3e,
179
180 mftoi_op3 = 0x36,
181
182 alt_bit_op3 = 0x10,
183 cc_bit_op3 = 0x10
184 };
185
186 enum opfs {
187 // selected opfs
188 edge8n_opf = 0x01,
189
190 fmovs_opf = 0x01,
191 fmovd_opf = 0x02,
192
193 fnegs_opf = 0x05,
194 fnegd_opf = 0x06,
195
196 alignaddr_opf = 0x18,
197
198 fadds_opf = 0x41,
199 faddd_opf = 0x42,
200 fsubs_opf = 0x45,
201 fsubd_opf = 0x46,
202
203 faligndata_opf = 0x48,
204
205 fmuls_opf = 0x49,
206 fmuld_opf = 0x4a,
207 fdivs_opf = 0x4d,
208 fdivd_opf = 0x4e,
209
210 fcmps_opf = 0x51,
211 fcmpd_opf = 0x52,
212
213 fstox_opf = 0x81,
214 fdtox_opf = 0x82,
215 fxtos_opf = 0x84,
216 fxtod_opf = 0x88,
217 fitos_opf = 0xc4,
218 fdtos_opf = 0xc6,
219 fitod_opf = 0xc8,
220 fstod_opf = 0xc9,
221 fstoi_opf = 0xd1,
222 fdtoi_opf = 0xd2,
223
224 mdtox_opf = 0x110,
225 mstouw_opf = 0x111,
226 mstosw_opf = 0x113,
1208
1209 // VIS1 instructions
1210
1211 void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
1212
1213 void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
1214
1215 void fzero( FloatRegisterImpl::Width w, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fzero_op3) | opf(0x62 - w)); }
1216
1217 void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
1218
1219 void fnot1( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fnot_op3) | fs1(s1, w) | opf(0x6C - w)); }
1220
1221 void fpmerge( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(0x36) | fs1(s1, FloatRegisterImpl::S) | opf(0x4b) | fs2(s2, FloatRegisterImpl::S)); }
1222
1223 void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
1224
1225 // VIS2 instructions
1226
1227 void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
1228
1229 // VIS3 instructions
1230
1231 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1232 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1233 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1234
1235 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1236 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1237
1238 void xmulx(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); }
1239 void xmulxhi(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); }
1240
1241 // Crypto SHA instructions
1242
1243 void sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
1244 void sha256() { sha256_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
1245 void sha512() { sha512_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }
1246
1247 // CRC32C instruction
|
107 sra_op3 = 0x27,
108 srax_op3 = 0x27,
109 rdreg_op3 = 0x28,
110 membar_op3 = 0x28,
111
112 flushw_op3 = 0x2b,
113 movcc_op3 = 0x2c,
114 sdivx_op3 = 0x2d,
115 popc_op3 = 0x2e,
116 movr_op3 = 0x2f,
117
118 sir_op3 = 0x30,
119 wrreg_op3 = 0x30,
120 saved_op3 = 0x31,
121
122 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36,
126 sha_op3 = 0x36,
127 bmask_op3 = 0x36,
128 bshuffle_op3 = 0x36,
129 alignaddr_op3 = 0x36,
130 faligndata_op3 = 0x36,
131 flog3_op3 = 0x36,
132 edge_op3 = 0x36,
133 fzero_op3 = 0x36,
134 fsrc_op3 = 0x36,
135 fnot_op3 = 0x36,
136 xmulx_op3 = 0x36,
137 crc32c_op3 = 0x36,
138 impdep2_op3 = 0x37,
139 stpartialf_op3 = 0x37,
140 jmpl_op3 = 0x38,
141 rett_op3 = 0x39,
142 trap_op3 = 0x3a,
143 flush_op3 = 0x3b,
144 save_op3 = 0x3c,
145 restore_op3 = 0x3d,
146 done_op3 = 0x3e,
147 retry_op3 = 0x3e,
148
179 casa_op3 = 0x3c,
180 casxa_op3 = 0x3e,
181
182 mftoi_op3 = 0x36,
183
184 alt_bit_op3 = 0x10,
185 cc_bit_op3 = 0x10
186 };
187
188 enum opfs {
189 // selected opfs
190 edge8n_opf = 0x01,
191
192 fmovs_opf = 0x01,
193 fmovd_opf = 0x02,
194
195 fnegs_opf = 0x05,
196 fnegd_opf = 0x06,
197
198 alignaddr_opf = 0x18,
199 bmask_opf = 0x19,
200
201 fadds_opf = 0x41,
202 faddd_opf = 0x42,
203 fsubs_opf = 0x45,
204 fsubd_opf = 0x46,
205
206 faligndata_opf = 0x48,
207
208 fmuls_opf = 0x49,
209 fmuld_opf = 0x4a,
210 bshuffle_opf = 0x4c,
211 fdivs_opf = 0x4d,
212 fdivd_opf = 0x4e,
213
214 fcmps_opf = 0x51,
215 fcmpd_opf = 0x52,
216
217 fstox_opf = 0x81,
218 fdtox_opf = 0x82,
219 fxtos_opf = 0x84,
220 fxtod_opf = 0x88,
221 fitos_opf = 0xc4,
222 fdtos_opf = 0xc6,
223 fitod_opf = 0xc8,
224 fstod_opf = 0xc9,
225 fstoi_opf = 0xd1,
226 fdtoi_opf = 0xd2,
227
228 mdtox_opf = 0x110,
229 mstouw_opf = 0x111,
230 mstosw_opf = 0x113,
1212
1213 // VIS1 instructions
1214
1215 void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
1216
1217 void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
1218
1219 void fzero( FloatRegisterImpl::Width w, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fzero_op3) | opf(0x62 - w)); }
1220
1221 void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
1222
1223 void fnot1( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fnot_op3) | fs1(s1, w) | opf(0x6C - w)); }
1224
1225 void fpmerge( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(0x36) | fs1(s1, FloatRegisterImpl::S) | opf(0x4b) | fs2(s2, FloatRegisterImpl::S)); }
1226
1227 void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
1228
1229 // VIS2 instructions
1230
1231 void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
1232
1233 void bmask( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(bmask_op3) | rs1(s1) | opf(bmask_opf) | rs2(s2)); }
1234 void bshuffle( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis2_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(bshuffle_op3) | fs1(s1, FloatRegisterImpl::D) | opf(bshuffle_opf) | fs2(s2, FloatRegisterImpl::D)); }
1235
1236 // VIS3 instructions
1237
1238 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1239 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1240 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1241
1242 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1243 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1244
1245 void xmulx(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); }
1246 void xmulxhi(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); }
1247
1248 // Crypto SHA instructions
1249
1250 void sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
1251 void sha256() { sha256_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
1252 void sha512() { sha512_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }
1253
1254 // CRC32C instruction
|