1 /* 2 * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_LIRAssembler.hpp" 30 #include "c1/c1_MacroAssembler.hpp" 31 #include "c1/c1_Runtime1.hpp" 32 #include "c1/c1_ValueStack.hpp" 33 #include "ci/ciArrayKlass.hpp" 34 #include "ci/ciInstance.hpp" 35 #include "gc/shared/barrierSet.hpp" 36 #include "gc/shared/cardTableBarrierSet.hpp" 37 #include "gc/shared/collectedHeap.hpp" 38 #include "nativeInst_x86.hpp" 39 #include "oops/objArrayKlass.hpp" 40 #include "runtime/frame.inline.hpp" 41 #include "runtime/safepointMechanism.hpp" 42 #include "runtime/sharedRuntime.hpp" 43 #include "vmreg_x86.inline.hpp" 44 45 46 // These masks are used to provide 128-bit aligned bitmasks to the XMM 47 // instructions, to allow sign-masking or sign-bit flipping. They allow 48 // fast versions of NegF/NegD and AbsF/AbsD. 49 50 // Note: 'double' and 'long long' have 32-bits alignment on x86. 51 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 52 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 53 // of 128-bits operands for SSE instructions. 54 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); 55 // Store the value to a 128-bits operand. 56 operand[0] = lo; 57 operand[1] = hi; 58 return operand; 59 } 60 61 // Buffer for 128-bits masks used by SSE instructions. 62 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 63 64 // Static initialization during VM startup. 65 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 66 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 67 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000)); 68 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000)); 69 70 71 NEEDS_CLEANUP // remove this definitions ? 72 const Register IC_Klass = rax; // where the IC klass is cached 73 const Register SYNC_header = rax; // synchronization header 74 const Register SHIFT_count = rcx; // where count for shift operations must be 75 76 #define __ _masm-> 77 78 79 static void select_different_registers(Register preserve, 80 Register extra, 81 Register &tmp1, 82 Register &tmp2) { 83 if (tmp1 == preserve) { 84 assert_different_registers(tmp1, tmp2, extra); 85 tmp1 = extra; 86 } else if (tmp2 == preserve) { 87 assert_different_registers(tmp1, tmp2, extra); 88 tmp2 = extra; 89 } 90 assert_different_registers(preserve, tmp1, tmp2); 91 } 92 93 94 95 static void select_different_registers(Register preserve, 96 Register extra, 97 Register &tmp1, 98 Register &tmp2, 99 Register &tmp3) { 100 if (tmp1 == preserve) { 101 assert_different_registers(tmp1, tmp2, tmp3, extra); 102 tmp1 = extra; 103 } else if (tmp2 == preserve) { 104 assert_different_registers(tmp1, tmp2, tmp3, extra); 105 tmp2 = extra; 106 } else if (tmp3 == preserve) { 107 assert_different_registers(tmp1, tmp2, tmp3, extra); 108 tmp3 = extra; 109 } 110 assert_different_registers(preserve, tmp1, tmp2, tmp3); 111 } 112 113 114 115 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 116 if (opr->is_constant()) { 117 LIR_Const* constant = opr->as_constant_ptr(); 118 switch (constant->type()) { 119 case T_INT: { 120 return true; 121 } 122 123 default: 124 return false; 125 } 126 } 127 return false; 128 } 129 130 131 LIR_Opr LIR_Assembler::receiverOpr() { 132 return FrameMap::receiver_opr; 133 } 134 135 LIR_Opr LIR_Assembler::osrBufferPointer() { 136 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 137 } 138 139 //--------------fpu register translations----------------------- 140 141 142 address LIR_Assembler::float_constant(float f) { 143 address const_addr = __ float_constant(f); 144 if (const_addr == NULL) { 145 bailout("const section overflow"); 146 return __ code()->consts()->start(); 147 } else { 148 return const_addr; 149 } 150 } 151 152 153 address LIR_Assembler::double_constant(double d) { 154 address const_addr = __ double_constant(d); 155 if (const_addr == NULL) { 156 bailout("const section overflow"); 157 return __ code()->consts()->start(); 158 } else { 159 return const_addr; 160 } 161 } 162 163 164 void LIR_Assembler::set_24bit_FPU() { 165 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 166 } 167 168 void LIR_Assembler::reset_FPU() { 169 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 170 } 171 172 void LIR_Assembler::fpop() { 173 __ fpop(); 174 } 175 176 void LIR_Assembler::fxch(int i) { 177 __ fxch(i); 178 } 179 180 void LIR_Assembler::fld(int i) { 181 __ fld_s(i); 182 } 183 184 void LIR_Assembler::ffree(int i) { 185 __ ffree(i); 186 } 187 188 void LIR_Assembler::breakpoint() { 189 __ int3(); 190 } 191 192 void LIR_Assembler::push(LIR_Opr opr) { 193 if (opr->is_single_cpu()) { 194 __ push_reg(opr->as_register()); 195 } else if (opr->is_double_cpu()) { 196 NOT_LP64(__ push_reg(opr->as_register_hi())); 197 __ push_reg(opr->as_register_lo()); 198 } else if (opr->is_stack()) { 199 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 200 } else if (opr->is_constant()) { 201 LIR_Const* const_opr = opr->as_constant_ptr(); 202 if (const_opr->type() == T_OBJECT || const_opr->type() == T_VALUETYPE) { 203 __ push_oop(const_opr->as_jobject()); 204 } else if (const_opr->type() == T_INT) { 205 __ push_jint(const_opr->as_jint()); 206 } else { 207 ShouldNotReachHere(); 208 } 209 210 } else { 211 ShouldNotReachHere(); 212 } 213 } 214 215 void LIR_Assembler::pop(LIR_Opr opr) { 216 if (opr->is_single_cpu()) { 217 __ pop_reg(opr->as_register()); 218 } else { 219 ShouldNotReachHere(); 220 } 221 } 222 223 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 224 return addr->base()->is_illegal() && addr->index()->is_illegal(); 225 } 226 227 //------------------------------------------- 228 229 Address LIR_Assembler::as_Address(LIR_Address* addr) { 230 return as_Address(addr, rscratch1); 231 } 232 233 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 234 if (addr->base()->is_illegal()) { 235 assert(addr->index()->is_illegal(), "must be illegal too"); 236 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 237 if (! __ reachable(laddr)) { 238 __ movptr(tmp, laddr.addr()); 239 Address res(tmp, 0); 240 return res; 241 } else { 242 return __ as_Address(laddr); 243 } 244 } 245 246 Register base = addr->base()->as_pointer_register(); 247 248 if (addr->index()->is_illegal()) { 249 return Address( base, addr->disp()); 250 } else if (addr->index()->is_cpu_register()) { 251 Register index = addr->index()->as_pointer_register(); 252 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 253 } else if (addr->index()->is_constant()) { 254 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 255 assert(Assembler::is_simm32(addr_offset), "must be"); 256 257 return Address(base, addr_offset); 258 } else { 259 Unimplemented(); 260 return Address(); 261 } 262 } 263 264 265 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 266 Address base = as_Address(addr); 267 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 268 } 269 270 271 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 272 return as_Address(addr); 273 } 274 275 276 void LIR_Assembler::osr_entry() { 277 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 278 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 279 ValueStack* entry_state = osr_entry->state(); 280 int number_of_locks = entry_state->locks_size(); 281 282 // we jump here if osr happens with the interpreter 283 // state set up to continue at the beginning of the 284 // loop that triggered osr - in particular, we have 285 // the following registers setup: 286 // 287 // rcx: osr buffer 288 // 289 290 // build frame 291 ciMethod* m = compilation()->method(); 292 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 293 294 // OSR buffer is 295 // 296 // locals[nlocals-1..0] 297 // monitors[0..number_of_locks] 298 // 299 // locals is a direct copy of the interpreter frame so in the osr buffer 300 // so first slot in the local array is the last local from the interpreter 301 // and last slot is local[0] (receiver) from the interpreter 302 // 303 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 304 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 305 // in the interpreter frame (the method lock if a sync method) 306 307 // Initialize monitors in the compiled activation. 308 // rcx: pointer to osr buffer 309 // 310 // All other registers are dead at this point and the locals will be 311 // copied into place by code emitted in the IR. 312 313 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 314 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 315 int monitor_offset = BytesPerWord * method()->max_locals() + 316 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); 317 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 318 // the OSR buffer using 2 word entries: first the lock and then 319 // the oop. 320 for (int i = 0; i < number_of_locks; i++) { 321 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 322 #ifdef ASSERT 323 // verify the interpreter's monitor has a non-null object 324 { 325 Label L; 326 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); 327 __ jcc(Assembler::notZero, L); 328 __ stop("locked object is NULL"); 329 __ bind(L); 330 } 331 #endif 332 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 333 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 334 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 335 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 336 } 337 } 338 } 339 340 341 // inline cache check; done before the frame is built. 342 int LIR_Assembler::check_icache() { 343 Register receiver = FrameMap::receiver_opr->as_register(); 344 Register ic_klass = IC_Klass; 345 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 346 const bool do_post_padding = VerifyOops || UseCompressedClassPointers; 347 if (!do_post_padding) { 348 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 349 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size); 350 } 351 int offset = __ offset(); 352 __ inline_cache_check(receiver, IC_Klass); 353 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); 354 if (do_post_padding) { 355 // force alignment after the cache check. 356 // It's been verified to be aligned if !VerifyOops 357 __ align(CodeEntryAlignment); 358 } 359 return offset; 360 } 361 362 363 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 364 jobject o = NULL; 365 PatchingStub* patch = new PatchingStub(_masm, patching_id(info)); 366 __ movoop(reg, o); 367 patching_epilog(patch, lir_patch_normal, reg, info); 368 } 369 370 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 371 Metadata* o = NULL; 372 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 373 __ mov_metadata(reg, o); 374 patching_epilog(patch, lir_patch_normal, reg, info); 375 } 376 377 // This specifies the rsp decrement needed to build the frame 378 int LIR_Assembler::initial_frame_size_in_bytes() const { 379 // if rounding, must let FrameMap know! 380 381 // The frame_map records size in slots (32bit word) 382 383 // subtract two words to account for return address and link 384 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 385 } 386 387 388 int LIR_Assembler::emit_exception_handler() { 389 // if the last instruction is a call (typically to do a throw which 390 // is coming at the end after block reordering) the return address 391 // must still point into the code area in order to avoid assertion 392 // failures when searching for the corresponding bci => add a nop 393 // (was bug 5/14/1999 - gri) 394 __ nop(); 395 396 // generate code for exception handler 397 address handler_base = __ start_a_stub(exception_handler_size()); 398 if (handler_base == NULL) { 399 // not enough space left for the handler 400 bailout("exception handler overflow"); 401 return -1; 402 } 403 404 int offset = code_offset(); 405 406 // the exception oop and pc are in rax, and rdx 407 // no other registers need to be preserved, so invalidate them 408 __ invalidate_registers(false, true, true, false, true, true); 409 410 // check that there is really an exception 411 __ verify_not_null_oop(rax); 412 413 // search an exception handler (rax: exception oop, rdx: throwing pc) 414 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 415 __ should_not_reach_here(); 416 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 417 __ end_a_stub(); 418 419 return offset; 420 } 421 422 423 // Emit the code to remove the frame from the stack in the exception 424 // unwind path. 425 int LIR_Assembler::emit_unwind_handler() { 426 #ifndef PRODUCT 427 if (CommentedAssembly) { 428 _masm->block_comment("Unwind handler"); 429 } 430 #endif 431 432 int offset = code_offset(); 433 434 // Fetch the exception from TLS and clear out exception related thread state 435 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 436 NOT_LP64(__ get_thread(rsi)); 437 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset())); 438 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); 439 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); 440 441 __ bind(_unwind_handler_entry); 442 __ verify_not_null_oop(rax); 443 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 444 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved) 445 } 446 447 // Preform needed unlocking 448 MonitorExitStub* stub = NULL; 449 if (method()->is_synchronized()) { 450 monitor_address(0, FrameMap::rax_opr); 451 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 452 __ unlock_object(rdi, rsi, rax, *stub->entry()); 453 __ bind(*stub->continuation()); 454 } 455 456 if (compilation()->env()->dtrace_method_probes()) { 457 #ifdef _LP64 458 __ mov(rdi, r15_thread); 459 __ mov_metadata(rsi, method()->constant_encoding()); 460 #else 461 __ get_thread(rax); 462 __ movptr(Address(rsp, 0), rax); 463 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding()); 464 #endif 465 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 466 } 467 468 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 469 __ mov(rax, rbx); // Restore the exception 470 } 471 472 // remove the activation and dispatch to the unwind handler 473 __ remove_frame(initial_frame_size_in_bytes()); 474 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 475 476 // Emit the slow path assembly 477 if (stub != NULL) { 478 stub->emit_code(this); 479 } 480 481 return offset; 482 } 483 484 485 int LIR_Assembler::emit_deopt_handler() { 486 // if the last instruction is a call (typically to do a throw which 487 // is coming at the end after block reordering) the return address 488 // must still point into the code area in order to avoid assertion 489 // failures when searching for the corresponding bci => add a nop 490 // (was bug 5/14/1999 - gri) 491 __ nop(); 492 493 // generate code for exception handler 494 address handler_base = __ start_a_stub(deopt_handler_size()); 495 if (handler_base == NULL) { 496 // not enough space left for the handler 497 bailout("deopt handler overflow"); 498 return -1; 499 } 500 501 int offset = code_offset(); 502 InternalAddress here(__ pc()); 503 504 __ pushptr(here.addr()); 505 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 506 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 507 __ end_a_stub(); 508 509 return offset; 510 } 511 512 513 void LIR_Assembler::return_op(LIR_Opr result) { 514 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 515 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 516 assert(result->fpu() == 0, "result must already be on TOS"); 517 } 518 519 // Pop the stack before the safepoint code 520 __ remove_frame(initial_frame_size_in_bytes()); 521 522 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 523 __ reserved_stack_check(); 524 } 525 526 bool result_is_oop = result->is_valid() ? result->is_oop() : false; 527 528 // Note: we do not need to round double result; float result has the right precision 529 // the poll sets the condition code, but no data registers 530 531 if (SafepointMechanism::uses_thread_local_poll()) { 532 #ifdef _LP64 533 const Register poll_addr = rscratch1; 534 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset())); 535 #else 536 const Register poll_addr = rbx; 537 assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite"); 538 __ get_thread(poll_addr); 539 __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset())); 540 #endif 541 __ relocate(relocInfo::poll_return_type); 542 __ testl(rax, Address(poll_addr, 0)); 543 } else { 544 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); 545 546 if (Assembler::is_polling_page_far()) { 547 __ lea(rscratch1, polling_page); 548 __ relocate(relocInfo::poll_return_type); 549 __ testl(rax, Address(rscratch1, 0)); 550 } else { 551 __ testl(rax, polling_page); 552 } 553 } 554 __ ret(0); 555 } 556 557 558 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 559 guarantee(info != NULL, "Shouldn't be NULL"); 560 int offset = __ offset(); 561 if (SafepointMechanism::uses_thread_local_poll()) { 562 #ifdef _LP64 563 const Register poll_addr = rscratch1; 564 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset())); 565 #else 566 assert(tmp->is_cpu_register(), "needed"); 567 const Register poll_addr = tmp->as_register(); 568 __ get_thread(poll_addr); 569 __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset()))); 570 #endif 571 add_debug_info_for_branch(info); 572 __ relocate(relocInfo::poll_type); 573 address pre_pc = __ pc(); 574 __ testl(rax, Address(poll_addr, 0)); 575 address post_pc = __ pc(); 576 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length"); 577 } else { 578 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type); 579 if (Assembler::is_polling_page_far()) { 580 __ lea(rscratch1, polling_page); 581 offset = __ offset(); 582 add_debug_info_for_branch(info); 583 __ relocate(relocInfo::poll_type); 584 __ testl(rax, Address(rscratch1, 0)); 585 } else { 586 add_debug_info_for_branch(info); 587 __ testl(rax, polling_page); 588 } 589 } 590 return offset; 591 } 592 593 594 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 595 if (from_reg != to_reg) __ mov(to_reg, from_reg); 596 } 597 598 void LIR_Assembler::swap_reg(Register a, Register b) { 599 __ xchgptr(a, b); 600 } 601 602 603 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 604 assert(src->is_constant(), "should not call otherwise"); 605 assert(dest->is_register(), "should not call otherwise"); 606 LIR_Const* c = src->as_constant_ptr(); 607 608 switch (c->type()) { 609 case T_INT: { 610 assert(patch_code == lir_patch_none, "no patching handled here"); 611 __ movl(dest->as_register(), c->as_jint()); 612 break; 613 } 614 615 case T_ADDRESS: { 616 assert(patch_code == lir_patch_none, "no patching handled here"); 617 __ movptr(dest->as_register(), c->as_jint()); 618 break; 619 } 620 621 case T_LONG: { 622 assert(patch_code == lir_patch_none, "no patching handled here"); 623 #ifdef _LP64 624 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 625 #else 626 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 627 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 628 #endif // _LP64 629 break; 630 } 631 632 case T_VALUETYPE: // Fall through 633 case T_OBJECT: { 634 if (patch_code != lir_patch_none) { 635 jobject2reg_with_patching(dest->as_register(), info); 636 } else { 637 __ movoop(dest->as_register(), c->as_jobject()); 638 } 639 break; 640 } 641 642 case T_METADATA: { 643 if (patch_code != lir_patch_none) { 644 klass2reg_with_patching(dest->as_register(), info); 645 } else { 646 __ mov_metadata(dest->as_register(), c->as_metadata()); 647 } 648 break; 649 } 650 651 case T_FLOAT: { 652 if (dest->is_single_xmm()) { 653 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) { 654 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 655 } else { 656 __ movflt(dest->as_xmm_float_reg(), 657 InternalAddress(float_constant(c->as_jfloat()))); 658 } 659 } else { 660 assert(dest->is_single_fpu(), "must be"); 661 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 662 if (c->is_zero_float()) { 663 __ fldz(); 664 } else if (c->is_one_float()) { 665 __ fld1(); 666 } else { 667 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 668 } 669 } 670 break; 671 } 672 673 case T_DOUBLE: { 674 if (dest->is_double_xmm()) { 675 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) { 676 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 677 } else { 678 __ movdbl(dest->as_xmm_double_reg(), 679 InternalAddress(double_constant(c->as_jdouble()))); 680 } 681 } else { 682 assert(dest->is_double_fpu(), "must be"); 683 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 684 if (c->is_zero_double()) { 685 __ fldz(); 686 } else if (c->is_one_double()) { 687 __ fld1(); 688 } else { 689 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 690 } 691 } 692 break; 693 } 694 695 default: 696 ShouldNotReachHere(); 697 } 698 } 699 700 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 701 assert(src->is_constant(), "should not call otherwise"); 702 assert(dest->is_stack(), "should not call otherwise"); 703 LIR_Const* c = src->as_constant_ptr(); 704 705 switch (c->type()) { 706 case T_INT: // fall through 707 case T_FLOAT: 708 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 709 break; 710 711 case T_ADDRESS: 712 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 713 break; 714 715 case T_VALUETYPE: // Fall through 716 case T_OBJECT: 717 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 718 break; 719 720 case T_LONG: // fall through 721 case T_DOUBLE: 722 #ifdef _LP64 723 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 724 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 725 #else 726 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 727 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 728 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 729 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 730 #endif // _LP64 731 break; 732 733 default: 734 ShouldNotReachHere(); 735 } 736 } 737 738 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 739 assert(src->is_constant(), "should not call otherwise"); 740 assert(dest->is_address(), "should not call otherwise"); 741 LIR_Const* c = src->as_constant_ptr(); 742 LIR_Address* addr = dest->as_address_ptr(); 743 744 int null_check_here = code_offset(); 745 switch (type) { 746 case T_INT: // fall through 747 case T_FLOAT: 748 __ movl(as_Address(addr), c->as_jint_bits()); 749 break; 750 751 case T_ADDRESS: 752 __ movptr(as_Address(addr), c->as_jint_bits()); 753 break; 754 755 case T_VALUETYPE: // fall through 756 case T_OBJECT: // fall through 757 case T_ARRAY: 758 if (c->as_jobject() == NULL) { 759 if (UseCompressedOops && !wide) { 760 __ movl(as_Address(addr), (int32_t)NULL_WORD); 761 } else { 762 #ifdef _LP64 763 __ xorptr(rscratch1, rscratch1); 764 null_check_here = code_offset(); 765 __ movptr(as_Address(addr), rscratch1); 766 #else 767 __ movptr(as_Address(addr), NULL_WORD); 768 #endif 769 } 770 } else { 771 if (is_literal_address(addr)) { 772 ShouldNotReachHere(); 773 __ movoop(as_Address(addr, noreg), c->as_jobject()); 774 } else { 775 #ifdef _LP64 776 __ movoop(rscratch1, c->as_jobject()); 777 if (UseCompressedOops && !wide) { 778 __ encode_heap_oop(rscratch1); 779 null_check_here = code_offset(); 780 __ movl(as_Address_lo(addr), rscratch1); 781 } else { 782 null_check_here = code_offset(); 783 __ movptr(as_Address_lo(addr), rscratch1); 784 } 785 #else 786 __ movoop(as_Address(addr), c->as_jobject()); 787 #endif 788 } 789 } 790 break; 791 792 case T_LONG: // fall through 793 case T_DOUBLE: 794 #ifdef _LP64 795 if (is_literal_address(addr)) { 796 ShouldNotReachHere(); 797 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 798 } else { 799 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 800 null_check_here = code_offset(); 801 __ movptr(as_Address_lo(addr), r10); 802 } 803 #else 804 // Always reachable in 32bit so this doesn't produce useless move literal 805 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 806 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 807 #endif // _LP64 808 break; 809 810 case T_BOOLEAN: // fall through 811 case T_BYTE: 812 __ movb(as_Address(addr), c->as_jint() & 0xFF); 813 break; 814 815 case T_CHAR: // fall through 816 case T_SHORT: 817 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 818 break; 819 820 default: 821 ShouldNotReachHere(); 822 }; 823 824 if (info != NULL) { 825 add_debug_info_for_null_check(null_check_here, info); 826 } 827 } 828 829 830 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 831 assert(src->is_register(), "should not call otherwise"); 832 assert(dest->is_register(), "should not call otherwise"); 833 834 // move between cpu-registers 835 if (dest->is_single_cpu()) { 836 #ifdef _LP64 837 if (src->type() == T_LONG) { 838 // Can do LONG -> OBJECT 839 move_regs(src->as_register_lo(), dest->as_register()); 840 return; 841 } 842 #endif 843 assert(src->is_single_cpu(), "must match"); 844 if (src->type() == T_OBJECT || src->type() == T_VALUETYPE) { 845 __ verify_oop(src->as_register()); 846 } 847 move_regs(src->as_register(), dest->as_register()); 848 849 } else if (dest->is_double_cpu()) { 850 #ifdef _LP64 851 if (src->type() == T_OBJECT || src->type() == T_ARRAY || src->type() == T_VALUETYPE) { 852 // Surprising to me but we can see move of a long to t_object 853 __ verify_oop(src->as_register()); 854 move_regs(src->as_register(), dest->as_register_lo()); 855 return; 856 } 857 #endif 858 assert(src->is_double_cpu(), "must match"); 859 Register f_lo = src->as_register_lo(); 860 Register f_hi = src->as_register_hi(); 861 Register t_lo = dest->as_register_lo(); 862 Register t_hi = dest->as_register_hi(); 863 #ifdef _LP64 864 assert(f_hi == f_lo, "must be same"); 865 assert(t_hi == t_lo, "must be same"); 866 move_regs(f_lo, t_lo); 867 #else 868 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 869 870 871 if (f_lo == t_hi && f_hi == t_lo) { 872 swap_reg(f_lo, f_hi); 873 } else if (f_hi == t_lo) { 874 assert(f_lo != t_hi, "overwriting register"); 875 move_regs(f_hi, t_hi); 876 move_regs(f_lo, t_lo); 877 } else { 878 assert(f_hi != t_lo, "overwriting register"); 879 move_regs(f_lo, t_lo); 880 move_regs(f_hi, t_hi); 881 } 882 #endif // LP64 883 884 // special moves from fpu-register to xmm-register 885 // necessary for method results 886 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 887 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 888 __ fld_s(Address(rsp, 0)); 889 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 890 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 891 __ fld_d(Address(rsp, 0)); 892 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 893 __ fstp_s(Address(rsp, 0)); 894 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 895 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 896 __ fstp_d(Address(rsp, 0)); 897 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 898 899 // move between xmm-registers 900 } else if (dest->is_single_xmm()) { 901 assert(src->is_single_xmm(), "must match"); 902 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 903 } else if (dest->is_double_xmm()) { 904 assert(src->is_double_xmm(), "must match"); 905 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 906 907 // move between fpu-registers (no instruction necessary because of fpu-stack) 908 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 909 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 910 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 911 } else { 912 ShouldNotReachHere(); 913 } 914 } 915 916 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 917 assert(src->is_register(), "should not call otherwise"); 918 assert(dest->is_stack(), "should not call otherwise"); 919 920 if (src->is_single_cpu()) { 921 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 922 if (type == T_OBJECT || type == T_ARRAY || type == T_VALUETYPE) { 923 __ verify_oop(src->as_register()); 924 __ movptr (dst, src->as_register()); 925 } else if (type == T_METADATA) { 926 __ movptr (dst, src->as_register()); 927 } else { 928 __ movl (dst, src->as_register()); 929 } 930 931 } else if (src->is_double_cpu()) { 932 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 933 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 934 __ movptr (dstLO, src->as_register_lo()); 935 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 936 937 } else if (src->is_single_xmm()) { 938 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 939 __ movflt(dst_addr, src->as_xmm_float_reg()); 940 941 } else if (src->is_double_xmm()) { 942 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 943 __ movdbl(dst_addr, src->as_xmm_double_reg()); 944 945 } else if (src->is_single_fpu()) { 946 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 947 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 948 if (pop_fpu_stack) __ fstp_s (dst_addr); 949 else __ fst_s (dst_addr); 950 951 } else if (src->is_double_fpu()) { 952 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 953 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 954 if (pop_fpu_stack) __ fstp_d (dst_addr); 955 else __ fst_d (dst_addr); 956 957 } else { 958 ShouldNotReachHere(); 959 } 960 } 961 962 963 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { 964 LIR_Address* to_addr = dest->as_address_ptr(); 965 PatchingStub* patch = NULL; 966 Register compressed_src = rscratch1; 967 968 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) { 969 __ verify_oop(src->as_register()); 970 #ifdef _LP64 971 if (UseCompressedOops && !wide) { 972 __ movptr(compressed_src, src->as_register()); 973 __ encode_heap_oop(compressed_src); 974 if (patch_code != lir_patch_none) { 975 info->oop_map()->set_narrowoop(compressed_src->as_VMReg()); 976 } 977 } 978 #endif 979 } 980 981 if (patch_code != lir_patch_none) { 982 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 983 Address toa = as_Address(to_addr); 984 assert(toa.disp() != 0, "must have"); 985 } 986 987 int null_check_here = code_offset(); 988 switch (type) { 989 case T_FLOAT: { 990 if (src->is_single_xmm()) { 991 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 992 } else { 993 assert(src->is_single_fpu(), "must be"); 994 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 995 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 996 else __ fst_s (as_Address(to_addr)); 997 } 998 break; 999 } 1000 1001 case T_DOUBLE: { 1002 if (src->is_double_xmm()) { 1003 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 1004 } else { 1005 assert(src->is_double_fpu(), "must be"); 1006 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 1007 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 1008 else __ fst_d (as_Address(to_addr)); 1009 } 1010 break; 1011 } 1012 1013 case T_VALUETYPE: // fall through 1014 case T_ARRAY: // fall through 1015 case T_OBJECT: // fall through 1016 if (UseCompressedOops && !wide) { 1017 __ movl(as_Address(to_addr), compressed_src); 1018 } else { 1019 __ movptr(as_Address(to_addr), src->as_register()); 1020 } 1021 break; 1022 case T_METADATA: 1023 // We get here to store a method pointer to the stack to pass to 1024 // a dtrace runtime call. This can't work on 64 bit with 1025 // compressed klass ptrs: T_METADATA can be a compressed klass 1026 // ptr or a 64 bit method pointer. 1027 LP64_ONLY(ShouldNotReachHere()); 1028 __ movptr(as_Address(to_addr), src->as_register()); 1029 break; 1030 case T_ADDRESS: 1031 __ movptr(as_Address(to_addr), src->as_register()); 1032 break; 1033 case T_INT: 1034 __ movl(as_Address(to_addr), src->as_register()); 1035 break; 1036 1037 case T_LONG: { 1038 Register from_lo = src->as_register_lo(); 1039 Register from_hi = src->as_register_hi(); 1040 #ifdef _LP64 1041 __ movptr(as_Address_lo(to_addr), from_lo); 1042 #else 1043 Register base = to_addr->base()->as_register(); 1044 Register index = noreg; 1045 if (to_addr->index()->is_register()) { 1046 index = to_addr->index()->as_register(); 1047 } 1048 if (base == from_lo || index == from_lo) { 1049 assert(base != from_hi, "can't be"); 1050 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1051 __ movl(as_Address_hi(to_addr), from_hi); 1052 if (patch != NULL) { 1053 patching_epilog(patch, lir_patch_high, base, info); 1054 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1055 patch_code = lir_patch_low; 1056 } 1057 __ movl(as_Address_lo(to_addr), from_lo); 1058 } else { 1059 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1060 __ movl(as_Address_lo(to_addr), from_lo); 1061 if (patch != NULL) { 1062 patching_epilog(patch, lir_patch_low, base, info); 1063 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1064 patch_code = lir_patch_high; 1065 } 1066 __ movl(as_Address_hi(to_addr), from_hi); 1067 } 1068 #endif // _LP64 1069 break; 1070 } 1071 1072 case T_BYTE: // fall through 1073 case T_BOOLEAN: { 1074 Register src_reg = src->as_register(); 1075 Address dst_addr = as_Address(to_addr); 1076 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1077 __ movb(dst_addr, src_reg); 1078 break; 1079 } 1080 1081 case T_CHAR: // fall through 1082 case T_SHORT: 1083 __ movw(as_Address(to_addr), src->as_register()); 1084 break; 1085 1086 default: 1087 ShouldNotReachHere(); 1088 } 1089 if (info != NULL) { 1090 add_debug_info_for_null_check(null_check_here, info); 1091 } 1092 1093 if (patch_code != lir_patch_none) { 1094 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1095 } 1096 } 1097 1098 1099 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1100 assert(src->is_stack(), "should not call otherwise"); 1101 assert(dest->is_register(), "should not call otherwise"); 1102 1103 if (dest->is_single_cpu()) { 1104 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) { 1105 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1106 __ verify_oop(dest->as_register()); 1107 } else if (type == T_METADATA) { 1108 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1109 } else { 1110 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1111 } 1112 1113 } else if (dest->is_double_cpu()) { 1114 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1115 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1116 __ movptr(dest->as_register_lo(), src_addr_LO); 1117 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1118 1119 } else if (dest->is_single_xmm()) { 1120 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1121 __ movflt(dest->as_xmm_float_reg(), src_addr); 1122 1123 } else if (dest->is_double_xmm()) { 1124 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1125 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1126 1127 } else if (dest->is_single_fpu()) { 1128 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1129 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1130 __ fld_s(src_addr); 1131 1132 } else if (dest->is_double_fpu()) { 1133 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1134 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1135 __ fld_d(src_addr); 1136 1137 } else { 1138 ShouldNotReachHere(); 1139 } 1140 } 1141 1142 1143 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1144 if (src->is_single_stack()) { 1145 if (type == T_OBJECT || type == T_ARRAY || type == T_VALUETYPE) { 1146 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1147 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1148 } else { 1149 #ifndef _LP64 1150 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1151 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1152 #else 1153 //no pushl on 64bits 1154 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1155 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1156 #endif 1157 } 1158 1159 } else if (src->is_double_stack()) { 1160 #ifdef _LP64 1161 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1162 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1163 #else 1164 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1165 // push and pop the part at src + wordSize, adding wordSize for the previous push 1166 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1167 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1168 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1169 #endif // _LP64 1170 1171 } else { 1172 ShouldNotReachHere(); 1173 } 1174 } 1175 1176 1177 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { 1178 assert(src->is_address(), "should not call otherwise"); 1179 assert(dest->is_register(), "should not call otherwise"); 1180 1181 LIR_Address* addr = src->as_address_ptr(); 1182 Address from_addr = as_Address(addr); 1183 1184 if (addr->base()->type() == T_OBJECT || addr->base()->type() == T_VALUETYPE) { 1185 __ verify_oop(addr->base()->as_pointer_register()); 1186 } 1187 1188 switch (type) { 1189 case T_BOOLEAN: // fall through 1190 case T_BYTE: // fall through 1191 case T_CHAR: // fall through 1192 case T_SHORT: 1193 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1194 // on pre P6 processors we may get partial register stalls 1195 // so blow away the value of to_rinfo before loading a 1196 // partial word into it. Do it here so that it precedes 1197 // the potential patch point below. 1198 __ xorptr(dest->as_register(), dest->as_register()); 1199 } 1200 break; 1201 default: 1202 break; 1203 } 1204 1205 PatchingStub* patch = NULL; 1206 if (patch_code != lir_patch_none) { 1207 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1208 assert(from_addr.disp() != 0, "must have"); 1209 } 1210 if (info != NULL) { 1211 add_debug_info_for_null_check_here(info); 1212 } 1213 1214 switch (type) { 1215 case T_FLOAT: { 1216 if (dest->is_single_xmm()) { 1217 __ movflt(dest->as_xmm_float_reg(), from_addr); 1218 } else { 1219 assert(dest->is_single_fpu(), "must be"); 1220 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1221 __ fld_s(from_addr); 1222 } 1223 break; 1224 } 1225 1226 case T_DOUBLE: { 1227 if (dest->is_double_xmm()) { 1228 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1229 } else { 1230 assert(dest->is_double_fpu(), "must be"); 1231 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1232 __ fld_d(from_addr); 1233 } 1234 break; 1235 } 1236 1237 case T_VALUETYPE: // fall through 1238 case T_OBJECT: // fall through 1239 case T_ARRAY: // fall through 1240 if (UseCompressedOops && !wide) { 1241 __ movl(dest->as_register(), from_addr); 1242 } else { 1243 __ movptr(dest->as_register(), from_addr); 1244 } 1245 break; 1246 1247 case T_ADDRESS: 1248 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1249 __ movl(dest->as_register(), from_addr); 1250 } else { 1251 __ movptr(dest->as_register(), from_addr); 1252 } 1253 break; 1254 case T_INT: 1255 __ movl(dest->as_register(), from_addr); 1256 break; 1257 1258 case T_LONG: { 1259 Register to_lo = dest->as_register_lo(); 1260 Register to_hi = dest->as_register_hi(); 1261 #ifdef _LP64 1262 __ movptr(to_lo, as_Address_lo(addr)); 1263 #else 1264 Register base = addr->base()->as_register(); 1265 Register index = noreg; 1266 if (addr->index()->is_register()) { 1267 index = addr->index()->as_register(); 1268 } 1269 if ((base == to_lo && index == to_hi) || 1270 (base == to_hi && index == to_lo)) { 1271 // addresses with 2 registers are only formed as a result of 1272 // array access so this code will never have to deal with 1273 // patches or null checks. 1274 assert(info == NULL && patch == NULL, "must be"); 1275 __ lea(to_hi, as_Address(addr)); 1276 __ movl(to_lo, Address(to_hi, 0)); 1277 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1278 } else if (base == to_lo || index == to_lo) { 1279 assert(base != to_hi, "can't be"); 1280 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1281 __ movl(to_hi, as_Address_hi(addr)); 1282 if (patch != NULL) { 1283 patching_epilog(patch, lir_patch_high, base, info); 1284 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1285 patch_code = lir_patch_low; 1286 } 1287 __ movl(to_lo, as_Address_lo(addr)); 1288 } else { 1289 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1290 __ movl(to_lo, as_Address_lo(addr)); 1291 if (patch != NULL) { 1292 patching_epilog(patch, lir_patch_low, base, info); 1293 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1294 patch_code = lir_patch_high; 1295 } 1296 __ movl(to_hi, as_Address_hi(addr)); 1297 } 1298 #endif // _LP64 1299 break; 1300 } 1301 1302 case T_BOOLEAN: // fall through 1303 case T_BYTE: { 1304 Register dest_reg = dest->as_register(); 1305 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1306 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1307 __ movsbl(dest_reg, from_addr); 1308 } else { 1309 __ movb(dest_reg, from_addr); 1310 __ shll(dest_reg, 24); 1311 __ sarl(dest_reg, 24); 1312 } 1313 break; 1314 } 1315 1316 case T_CHAR: { 1317 Register dest_reg = dest->as_register(); 1318 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1319 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1320 __ movzwl(dest_reg, from_addr); 1321 } else { 1322 __ movw(dest_reg, from_addr); 1323 } 1324 break; 1325 } 1326 1327 case T_SHORT: { 1328 Register dest_reg = dest->as_register(); 1329 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1330 __ movswl(dest_reg, from_addr); 1331 } else { 1332 __ movw(dest_reg, from_addr); 1333 __ shll(dest_reg, 16); 1334 __ sarl(dest_reg, 16); 1335 } 1336 break; 1337 } 1338 1339 default: 1340 ShouldNotReachHere(); 1341 } 1342 1343 if (patch != NULL) { 1344 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1345 } 1346 1347 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) { 1348 #ifdef _LP64 1349 if (UseCompressedOops && !wide) { 1350 __ decode_heap_oop(dest->as_register()); 1351 } 1352 #endif 1353 1354 // Load barrier has not yet been applied, so ZGC can't verify the oop here 1355 if (!UseZGC) { 1356 __ verify_oop(dest->as_register()); 1357 } 1358 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1359 #ifdef _LP64 1360 if (UseCompressedClassPointers) { 1361 __ decode_klass_not_null(dest->as_register()); 1362 } 1363 #endif 1364 } 1365 } 1366 1367 1368 NEEDS_CLEANUP; // This could be static? 1369 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1370 int elem_size = type2aelembytes(type); 1371 switch (elem_size) { 1372 case 1: return Address::times_1; 1373 case 2: return Address::times_2; 1374 case 4: return Address::times_4; 1375 case 8: return Address::times_8; 1376 } 1377 ShouldNotReachHere(); 1378 return Address::no_scale; 1379 } 1380 1381 1382 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1383 switch (op->code()) { 1384 case lir_idiv: 1385 case lir_irem: 1386 arithmetic_idiv(op->code(), 1387 op->in_opr1(), 1388 op->in_opr2(), 1389 op->in_opr3(), 1390 op->result_opr(), 1391 op->info()); 1392 break; 1393 case lir_fmad: 1394 __ fmad(op->result_opr()->as_xmm_double_reg(), 1395 op->in_opr1()->as_xmm_double_reg(), 1396 op->in_opr2()->as_xmm_double_reg(), 1397 op->in_opr3()->as_xmm_double_reg()); 1398 break; 1399 case lir_fmaf: 1400 __ fmaf(op->result_opr()->as_xmm_float_reg(), 1401 op->in_opr1()->as_xmm_float_reg(), 1402 op->in_opr2()->as_xmm_float_reg(), 1403 op->in_opr3()->as_xmm_float_reg()); 1404 break; 1405 default: ShouldNotReachHere(); break; 1406 } 1407 } 1408 1409 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1410 #ifdef ASSERT 1411 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1412 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1413 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1414 #endif 1415 1416 if (op->cond() == lir_cond_always) { 1417 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1418 __ jmp (*(op->label())); 1419 } else { 1420 Assembler::Condition acond = Assembler::zero; 1421 if (op->code() == lir_cond_float_branch) { 1422 assert(op->ublock() != NULL, "must have unordered successor"); 1423 __ jcc(Assembler::parity, *(op->ublock()->label())); 1424 switch(op->cond()) { 1425 case lir_cond_equal: acond = Assembler::equal; break; 1426 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1427 case lir_cond_less: acond = Assembler::below; break; 1428 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1429 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1430 case lir_cond_greater: acond = Assembler::above; break; 1431 default: ShouldNotReachHere(); 1432 } 1433 } else { 1434 switch (op->cond()) { 1435 case lir_cond_equal: acond = Assembler::equal; break; 1436 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1437 case lir_cond_less: acond = Assembler::less; break; 1438 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1439 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1440 case lir_cond_greater: acond = Assembler::greater; break; 1441 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1442 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1443 default: ShouldNotReachHere(); 1444 } 1445 } 1446 __ jcc(acond,*(op->label())); 1447 } 1448 } 1449 1450 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1451 LIR_Opr src = op->in_opr(); 1452 LIR_Opr dest = op->result_opr(); 1453 1454 switch (op->bytecode()) { 1455 case Bytecodes::_i2l: 1456 #ifdef _LP64 1457 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1458 #else 1459 move_regs(src->as_register(), dest->as_register_lo()); 1460 move_regs(src->as_register(), dest->as_register_hi()); 1461 __ sarl(dest->as_register_hi(), 31); 1462 #endif // LP64 1463 break; 1464 1465 case Bytecodes::_l2i: 1466 #ifdef _LP64 1467 __ movl(dest->as_register(), src->as_register_lo()); 1468 #else 1469 move_regs(src->as_register_lo(), dest->as_register()); 1470 #endif 1471 break; 1472 1473 case Bytecodes::_i2b: 1474 move_regs(src->as_register(), dest->as_register()); 1475 __ sign_extend_byte(dest->as_register()); 1476 break; 1477 1478 case Bytecodes::_i2c: 1479 move_regs(src->as_register(), dest->as_register()); 1480 __ andl(dest->as_register(), 0xFFFF); 1481 break; 1482 1483 case Bytecodes::_i2s: 1484 move_regs(src->as_register(), dest->as_register()); 1485 __ sign_extend_short(dest->as_register()); 1486 break; 1487 1488 1489 case Bytecodes::_f2d: 1490 case Bytecodes::_d2f: 1491 if (dest->is_single_xmm()) { 1492 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1493 } else if (dest->is_double_xmm()) { 1494 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1495 } else { 1496 assert(src->fpu() == dest->fpu(), "register must be equal"); 1497 // do nothing (float result is rounded later through spilling) 1498 } 1499 break; 1500 1501 case Bytecodes::_i2f: 1502 case Bytecodes::_i2d: 1503 if (dest->is_single_xmm()) { 1504 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1505 } else if (dest->is_double_xmm()) { 1506 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1507 } else { 1508 assert(dest->fpu() == 0, "result must be on TOS"); 1509 __ movl(Address(rsp, 0), src->as_register()); 1510 __ fild_s(Address(rsp, 0)); 1511 } 1512 break; 1513 1514 case Bytecodes::_f2i: 1515 case Bytecodes::_d2i: 1516 if (src->is_single_xmm()) { 1517 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1518 } else if (src->is_double_xmm()) { 1519 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1520 } else { 1521 assert(src->fpu() == 0, "input must be on TOS"); 1522 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 1523 __ fist_s(Address(rsp, 0)); 1524 __ movl(dest->as_register(), Address(rsp, 0)); 1525 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1526 } 1527 1528 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1529 assert(op->stub() != NULL, "stub required"); 1530 __ cmpl(dest->as_register(), 0x80000000); 1531 __ jcc(Assembler::equal, *op->stub()->entry()); 1532 __ bind(*op->stub()->continuation()); 1533 break; 1534 1535 case Bytecodes::_l2f: 1536 case Bytecodes::_l2d: 1537 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1538 assert(dest->fpu() == 0, "result must be on TOS"); 1539 1540 __ movptr(Address(rsp, 0), src->as_register_lo()); 1541 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1542 __ fild_d(Address(rsp, 0)); 1543 // float result is rounded later through spilling 1544 break; 1545 1546 case Bytecodes::_f2l: 1547 case Bytecodes::_d2l: 1548 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1549 assert(src->fpu() == 0, "input must be on TOS"); 1550 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1551 1552 // instruction sequence too long to inline it here 1553 { 1554 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1555 } 1556 break; 1557 1558 default: ShouldNotReachHere(); 1559 } 1560 } 1561 1562 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1563 if (op->init_check()) { 1564 add_debug_info_for_null_check_here(op->stub()->info()); 1565 __ cmpb(Address(op->klass()->as_register(), 1566 InstanceKlass::init_state_offset()), 1567 InstanceKlass::fully_initialized); 1568 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1569 } 1570 __ allocate_object(op->obj()->as_register(), 1571 op->tmp1()->as_register(), 1572 op->tmp2()->as_register(), 1573 op->header_size(), 1574 op->object_size(), 1575 op->klass()->as_register(), 1576 *op->stub()->entry()); 1577 __ bind(*op->stub()->continuation()); 1578 } 1579 1580 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1581 Register len = op->len()->as_register(); 1582 LP64_ONLY( __ movslq(len, len); ) 1583 1584 if (UseSlowPath || op->type() == T_VALUETYPE || 1585 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1586 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 1587 __ jmp(*op->stub()->entry()); 1588 } else { 1589 Register tmp1 = op->tmp1()->as_register(); 1590 Register tmp2 = op->tmp2()->as_register(); 1591 Register tmp3 = op->tmp3()->as_register(); 1592 if (len == tmp1) { 1593 tmp1 = tmp3; 1594 } else if (len == tmp2) { 1595 tmp2 = tmp3; 1596 } else if (len == tmp3) { 1597 // everything is ok 1598 } else { 1599 __ mov(tmp3, len); 1600 } 1601 __ allocate_array(op->obj()->as_register(), 1602 len, 1603 tmp1, 1604 tmp2, 1605 arrayOopDesc::header_size(op->type()), 1606 array_element_size(op->type()), 1607 op->klass()->as_register(), 1608 *op->stub()->entry()); 1609 } 1610 __ bind(*op->stub()->continuation()); 1611 } 1612 1613 void LIR_Assembler::type_profile_helper(Register mdo, 1614 ciMethodData *md, ciProfileData *data, 1615 Register recv, Label* update_done) { 1616 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1617 Label next_test; 1618 // See if the receiver is receiver[n]. 1619 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1620 __ jccb(Assembler::notEqual, next_test); 1621 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1622 __ addptr(data_addr, DataLayout::counter_increment); 1623 __ jmp(*update_done); 1624 __ bind(next_test); 1625 } 1626 1627 // Didn't find receiver; find next empty slot and fill it in 1628 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1629 Label next_test; 1630 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1631 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); 1632 __ jccb(Assembler::notEqual, next_test); 1633 __ movptr(recv_addr, recv); 1634 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1635 __ jmp(*update_done); 1636 __ bind(next_test); 1637 } 1638 } 1639 1640 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1641 // we always need a stub for the failure case. 1642 CodeStub* stub = op->stub(); 1643 Register obj = op->object()->as_register(); 1644 Register k_RInfo = op->tmp1()->as_register(); 1645 Register klass_RInfo = op->tmp2()->as_register(); 1646 Register dst = op->result_opr()->as_register(); 1647 ciKlass* k = op->klass(); 1648 Register Rtmp1 = noreg; 1649 1650 // check if it needs to be profiled 1651 ciMethodData* md = NULL; 1652 ciProfileData* data = NULL; 1653 1654 if (op->should_profile()) { 1655 ciMethod* method = op->profiled_method(); 1656 assert(method != NULL, "Should have method"); 1657 int bci = op->profiled_bci(); 1658 md = method->method_data_or_null(); 1659 assert(md != NULL, "Sanity"); 1660 data = md->bci_to_data(bci); 1661 assert(data != NULL, "need data for type check"); 1662 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1663 } 1664 Label profile_cast_success, profile_cast_failure; 1665 Label *success_target = op->should_profile() ? &profile_cast_success : success; 1666 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 1667 1668 if (obj == k_RInfo) { 1669 k_RInfo = dst; 1670 } else if (obj == klass_RInfo) { 1671 klass_RInfo = dst; 1672 } 1673 if (k->is_loaded() && !UseCompressedClassPointers) { 1674 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1675 } else { 1676 Rtmp1 = op->tmp3()->as_register(); 1677 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1678 } 1679 1680 assert_different_registers(obj, k_RInfo, klass_RInfo); 1681 1682 if (op->need_null_check()) { 1683 __ cmpptr(obj, (int32_t)NULL_WORD); 1684 if (op->should_profile()) { 1685 Label not_null; 1686 __ jccb(Assembler::notEqual, not_null); 1687 // Object is null; update MDO and exit 1688 Register mdo = klass_RInfo; 1689 __ mov_metadata(mdo, md->constant_encoding()); 1690 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset())); 1691 int header_bits = BitData::null_seen_byte_constant(); 1692 __ orb(data_addr, header_bits); 1693 __ jmp(*obj_is_null); 1694 __ bind(not_null); 1695 } else { 1696 __ jcc(Assembler::equal, *obj_is_null); 1697 } 1698 } 1699 1700 if (!k->is_loaded()) { 1701 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1702 } else { 1703 #ifdef _LP64 1704 __ mov_metadata(k_RInfo, k->constant_encoding()); 1705 #endif // _LP64 1706 } 1707 __ verify_oop(obj); 1708 1709 if (op->fast_check()) { 1710 // get object class 1711 // not a safepoint as obj null check happens earlier 1712 #ifdef _LP64 1713 if (UseCompressedClassPointers) { 1714 __ load_klass(Rtmp1, obj); 1715 __ cmpptr(k_RInfo, Rtmp1); 1716 } else { 1717 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1718 } 1719 #else 1720 if (k->is_loaded()) { 1721 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1722 } else { 1723 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1724 } 1725 #endif 1726 __ jcc(Assembler::notEqual, *failure_target); 1727 // successful cast, fall through to profile or jump 1728 } else { 1729 // get object class 1730 // not a safepoint as obj null check happens earlier 1731 __ load_klass(klass_RInfo, obj); 1732 if (k->is_loaded()) { 1733 // See if we get an immediate positive hit 1734 #ifdef _LP64 1735 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1736 #else 1737 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1738 #endif // _LP64 1739 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1740 __ jcc(Assembler::notEqual, *failure_target); 1741 // successful cast, fall through to profile or jump 1742 } else { 1743 // See if we get an immediate positive hit 1744 __ jcc(Assembler::equal, *success_target); 1745 // check for self 1746 #ifdef _LP64 1747 __ cmpptr(klass_RInfo, k_RInfo); 1748 #else 1749 __ cmpklass(klass_RInfo, k->constant_encoding()); 1750 #endif // _LP64 1751 __ jcc(Assembler::equal, *success_target); 1752 1753 __ push(klass_RInfo); 1754 #ifdef _LP64 1755 __ push(k_RInfo); 1756 #else 1757 __ pushklass(k->constant_encoding()); 1758 #endif // _LP64 1759 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1760 __ pop(klass_RInfo); 1761 __ pop(klass_RInfo); 1762 // result is a boolean 1763 __ cmpl(klass_RInfo, 0); 1764 __ jcc(Assembler::equal, *failure_target); 1765 // successful cast, fall through to profile or jump 1766 } 1767 } else { 1768 // perform the fast part of the checking logic 1769 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1770 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1771 __ push(klass_RInfo); 1772 __ push(k_RInfo); 1773 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1774 __ pop(klass_RInfo); 1775 __ pop(k_RInfo); 1776 // result is a boolean 1777 __ cmpl(k_RInfo, 0); 1778 __ jcc(Assembler::equal, *failure_target); 1779 // successful cast, fall through to profile or jump 1780 } 1781 } 1782 if (op->should_profile()) { 1783 Register mdo = klass_RInfo, recv = k_RInfo; 1784 __ bind(profile_cast_success); 1785 __ mov_metadata(mdo, md->constant_encoding()); 1786 __ load_klass(recv, obj); 1787 type_profile_helper(mdo, md, data, recv, success); 1788 __ jmp(*success); 1789 1790 __ bind(profile_cast_failure); 1791 __ mov_metadata(mdo, md->constant_encoding()); 1792 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1793 __ subptr(counter_addr, DataLayout::counter_increment); 1794 __ jmp(*failure); 1795 } 1796 __ jmp(*success); 1797 } 1798 1799 1800 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1801 LIR_Code code = op->code(); 1802 if (code == lir_store_check) { 1803 Register value = op->object()->as_register(); 1804 Register array = op->array()->as_register(); 1805 Register k_RInfo = op->tmp1()->as_register(); 1806 Register klass_RInfo = op->tmp2()->as_register(); 1807 Register Rtmp1 = op->tmp3()->as_register(); 1808 1809 CodeStub* stub = op->stub(); 1810 1811 // check if it needs to be profiled 1812 ciMethodData* md = NULL; 1813 ciProfileData* data = NULL; 1814 1815 if (op->should_profile()) { 1816 ciMethod* method = op->profiled_method(); 1817 assert(method != NULL, "Should have method"); 1818 int bci = op->profiled_bci(); 1819 md = method->method_data_or_null(); 1820 assert(md != NULL, "Sanity"); 1821 data = md->bci_to_data(bci); 1822 assert(data != NULL, "need data for type check"); 1823 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1824 } 1825 Label profile_cast_success, profile_cast_failure, done; 1826 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 1827 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 1828 1829 __ cmpptr(value, (int32_t)NULL_WORD); 1830 if (op->should_profile()) { 1831 Label not_null; 1832 __ jccb(Assembler::notEqual, not_null); 1833 // Object is null; update MDO and exit 1834 Register mdo = klass_RInfo; 1835 __ mov_metadata(mdo, md->constant_encoding()); 1836 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset())); 1837 int header_bits = BitData::null_seen_byte_constant(); 1838 __ orb(data_addr, header_bits); 1839 __ jmp(done); 1840 __ bind(not_null); 1841 } else { 1842 __ jcc(Assembler::equal, done); 1843 } 1844 1845 add_debug_info_for_null_check_here(op->info_for_exception()); 1846 __ load_klass(k_RInfo, array); 1847 __ load_klass(klass_RInfo, value); 1848 1849 // get instance klass (it's already uncompressed) 1850 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1851 // perform the fast part of the checking logic 1852 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1853 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1854 __ push(klass_RInfo); 1855 __ push(k_RInfo); 1856 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1857 __ pop(klass_RInfo); 1858 __ pop(k_RInfo); 1859 // result is a boolean 1860 __ cmpl(k_RInfo, 0); 1861 __ jcc(Assembler::equal, *failure_target); 1862 // fall through to the success case 1863 1864 if (op->should_profile()) { 1865 Register mdo = klass_RInfo, recv = k_RInfo; 1866 __ bind(profile_cast_success); 1867 __ mov_metadata(mdo, md->constant_encoding()); 1868 __ load_klass(recv, value); 1869 type_profile_helper(mdo, md, data, recv, &done); 1870 __ jmpb(done); 1871 1872 __ bind(profile_cast_failure); 1873 __ mov_metadata(mdo, md->constant_encoding()); 1874 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1875 __ subptr(counter_addr, DataLayout::counter_increment); 1876 __ jmp(*stub->entry()); 1877 } 1878 1879 __ bind(done); 1880 } else 1881 if (code == lir_checkcast) { 1882 Register obj = op->object()->as_register(); 1883 Register dst = op->result_opr()->as_register(); 1884 Label success; 1885 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1886 __ bind(success); 1887 if (dst != obj) { 1888 __ mov(dst, obj); 1889 } 1890 } else 1891 if (code == lir_instanceof) { 1892 Register obj = op->object()->as_register(); 1893 Register dst = op->result_opr()->as_register(); 1894 Label success, failure, done; 1895 emit_typecheck_helper(op, &success, &failure, &failure); 1896 __ bind(failure); 1897 __ xorptr(dst, dst); 1898 __ jmpb(done); 1899 __ bind(success); 1900 __ movptr(dst, 1); 1901 __ bind(done); 1902 } else { 1903 ShouldNotReachHere(); 1904 } 1905 1906 } 1907 1908 void LIR_Assembler::emit_opFlattenedStoreCheck(LIR_OpFlattenedStoreCheck* op) { 1909 Klass* k = (Klass*)(op->element_klass()->constant_encoding()); 1910 assert(k->is_klass(), "must be a loaded klass"); 1911 add_debug_info_for_null_check_here(op->info_for_exception()); 1912 1913 #ifdef _LP64 1914 if (UseCompressedClassPointers) { 1915 __ movl(op->tmp1()->as_register(), Address(op->object()->as_register(), oopDesc::klass_offset_in_bytes())); 1916 __ cmp_narrow_klass(op->tmp1()->as_register(), k); 1917 } else { 1918 __ movq(op->tmp1()->as_register(), Address(op->object()->as_register(), oopDesc::klass_offset_in_bytes())); 1919 __ cmpq(op->tmp1()->as_register(), op->tmp2()->as_register()); 1920 } 1921 #else 1922 Unimplemented(); // FIXME 1923 #endif 1924 1925 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1926 __ bind(*op->stub()->continuation()); 1927 } 1928 1929 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1930 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1931 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1932 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1933 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1934 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1935 Register addr = op->addr()->as_register(); 1936 __ lock(); 1937 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1938 1939 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1940 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1941 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1942 Register newval = op->new_value()->as_register(); 1943 Register cmpval = op->cmp_value()->as_register(); 1944 assert(cmpval == rax, "wrong register"); 1945 assert(newval != NULL, "new val must be register"); 1946 assert(cmpval != newval, "cmp and new values must be in different registers"); 1947 assert(cmpval != addr, "cmp and addr must be in different registers"); 1948 assert(newval != addr, "new value and addr must be in different registers"); 1949 1950 if ( op->code() == lir_cas_obj) { 1951 #ifdef _LP64 1952 if (UseCompressedOops) { 1953 __ encode_heap_oop(cmpval); 1954 __ mov(rscratch1, newval); 1955 __ encode_heap_oop(rscratch1); 1956 __ lock(); 1957 // cmpval (rax) is implicitly used by this instruction 1958 __ cmpxchgl(rscratch1, Address(addr, 0)); 1959 } else 1960 #endif 1961 { 1962 __ lock(); 1963 __ cmpxchgptr(newval, Address(addr, 0)); 1964 } 1965 } else { 1966 assert(op->code() == lir_cas_int, "lir_cas_int expected"); 1967 __ lock(); 1968 __ cmpxchgl(newval, Address(addr, 0)); 1969 } 1970 #ifdef _LP64 1971 } else if (op->code() == lir_cas_long) { 1972 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1973 Register newval = op->new_value()->as_register_lo(); 1974 Register cmpval = op->cmp_value()->as_register_lo(); 1975 assert(cmpval == rax, "wrong register"); 1976 assert(newval != NULL, "new val must be register"); 1977 assert(cmpval != newval, "cmp and new values must be in different registers"); 1978 assert(cmpval != addr, "cmp and addr must be in different registers"); 1979 assert(newval != addr, "new value and addr must be in different registers"); 1980 __ lock(); 1981 __ cmpxchgq(newval, Address(addr, 0)); 1982 #endif // _LP64 1983 } else { 1984 Unimplemented(); 1985 } 1986 } 1987 1988 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1989 Assembler::Condition acond, ncond; 1990 switch (condition) { 1991 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1992 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1993 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1994 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 1995 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 1996 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 1997 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 1998 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 1999 default: acond = Assembler::equal; ncond = Assembler::notEqual; 2000 ShouldNotReachHere(); 2001 } 2002 2003 if (opr1->is_cpu_register()) { 2004 reg2reg(opr1, result); 2005 } else if (opr1->is_stack()) { 2006 stack2reg(opr1, result, result->type()); 2007 } else if (opr1->is_constant()) { 2008 const2reg(opr1, result, lir_patch_none, NULL); 2009 } else { 2010 ShouldNotReachHere(); 2011 } 2012 2013 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 2014 // optimized version that does not require a branch 2015 if (opr2->is_single_cpu()) { 2016 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 2017 __ cmov(ncond, result->as_register(), opr2->as_register()); 2018 } else if (opr2->is_double_cpu()) { 2019 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2020 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2021 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 2022 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 2023 } else if (opr2->is_single_stack()) { 2024 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 2025 } else if (opr2->is_double_stack()) { 2026 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 2027 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2028 } else { 2029 ShouldNotReachHere(); 2030 } 2031 2032 } else { 2033 Label skip; 2034 __ jcc (acond, skip); 2035 if (opr2->is_cpu_register()) { 2036 reg2reg(opr2, result); 2037 } else if (opr2->is_stack()) { 2038 stack2reg(opr2, result, result->type()); 2039 } else if (opr2->is_constant()) { 2040 const2reg(opr2, result, lir_patch_none, NULL); 2041 } else { 2042 ShouldNotReachHere(); 2043 } 2044 __ bind(skip); 2045 } 2046 } 2047 2048 2049 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 2050 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 2051 2052 if (left->is_single_cpu()) { 2053 assert(left == dest, "left and dest must be equal"); 2054 Register lreg = left->as_register(); 2055 2056 if (right->is_single_cpu()) { 2057 // cpu register - cpu register 2058 Register rreg = right->as_register(); 2059 switch (code) { 2060 case lir_add: __ addl (lreg, rreg); break; 2061 case lir_sub: __ subl (lreg, rreg); break; 2062 case lir_mul: __ imull(lreg, rreg); break; 2063 default: ShouldNotReachHere(); 2064 } 2065 2066 } else if (right->is_stack()) { 2067 // cpu register - stack 2068 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2069 switch (code) { 2070 case lir_add: __ addl(lreg, raddr); break; 2071 case lir_sub: __ subl(lreg, raddr); break; 2072 default: ShouldNotReachHere(); 2073 } 2074 2075 } else if (right->is_constant()) { 2076 // cpu register - constant 2077 jint c = right->as_constant_ptr()->as_jint(); 2078 switch (code) { 2079 case lir_add: { 2080 __ incrementl(lreg, c); 2081 break; 2082 } 2083 case lir_sub: { 2084 __ decrementl(lreg, c); 2085 break; 2086 } 2087 default: ShouldNotReachHere(); 2088 } 2089 2090 } else { 2091 ShouldNotReachHere(); 2092 } 2093 2094 } else if (left->is_double_cpu()) { 2095 assert(left == dest, "left and dest must be equal"); 2096 Register lreg_lo = left->as_register_lo(); 2097 Register lreg_hi = left->as_register_hi(); 2098 2099 if (right->is_double_cpu()) { 2100 // cpu register - cpu register 2101 Register rreg_lo = right->as_register_lo(); 2102 Register rreg_hi = right->as_register_hi(); 2103 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2104 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2105 switch (code) { 2106 case lir_add: 2107 __ addptr(lreg_lo, rreg_lo); 2108 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2109 break; 2110 case lir_sub: 2111 __ subptr(lreg_lo, rreg_lo); 2112 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2113 break; 2114 case lir_mul: 2115 #ifdef _LP64 2116 __ imulq(lreg_lo, rreg_lo); 2117 #else 2118 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2119 __ imull(lreg_hi, rreg_lo); 2120 __ imull(rreg_hi, lreg_lo); 2121 __ addl (rreg_hi, lreg_hi); 2122 __ mull (rreg_lo); 2123 __ addl (lreg_hi, rreg_hi); 2124 #endif // _LP64 2125 break; 2126 default: 2127 ShouldNotReachHere(); 2128 } 2129 2130 } else if (right->is_constant()) { 2131 // cpu register - constant 2132 #ifdef _LP64 2133 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2134 __ movptr(r10, (intptr_t) c); 2135 switch (code) { 2136 case lir_add: 2137 __ addptr(lreg_lo, r10); 2138 break; 2139 case lir_sub: 2140 __ subptr(lreg_lo, r10); 2141 break; 2142 default: 2143 ShouldNotReachHere(); 2144 } 2145 #else 2146 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2147 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2148 switch (code) { 2149 case lir_add: 2150 __ addptr(lreg_lo, c_lo); 2151 __ adcl(lreg_hi, c_hi); 2152 break; 2153 case lir_sub: 2154 __ subptr(lreg_lo, c_lo); 2155 __ sbbl(lreg_hi, c_hi); 2156 break; 2157 default: 2158 ShouldNotReachHere(); 2159 } 2160 #endif // _LP64 2161 2162 } else { 2163 ShouldNotReachHere(); 2164 } 2165 2166 } else if (left->is_single_xmm()) { 2167 assert(left == dest, "left and dest must be equal"); 2168 XMMRegister lreg = left->as_xmm_float_reg(); 2169 2170 if (right->is_single_xmm()) { 2171 XMMRegister rreg = right->as_xmm_float_reg(); 2172 switch (code) { 2173 case lir_add: __ addss(lreg, rreg); break; 2174 case lir_sub: __ subss(lreg, rreg); break; 2175 case lir_mul_strictfp: // fall through 2176 case lir_mul: __ mulss(lreg, rreg); break; 2177 case lir_div_strictfp: // fall through 2178 case lir_div: __ divss(lreg, rreg); break; 2179 default: ShouldNotReachHere(); 2180 } 2181 } else { 2182 Address raddr; 2183 if (right->is_single_stack()) { 2184 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2185 } else if (right->is_constant()) { 2186 // hack for now 2187 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2188 } else { 2189 ShouldNotReachHere(); 2190 } 2191 switch (code) { 2192 case lir_add: __ addss(lreg, raddr); break; 2193 case lir_sub: __ subss(lreg, raddr); break; 2194 case lir_mul_strictfp: // fall through 2195 case lir_mul: __ mulss(lreg, raddr); break; 2196 case lir_div_strictfp: // fall through 2197 case lir_div: __ divss(lreg, raddr); break; 2198 default: ShouldNotReachHere(); 2199 } 2200 } 2201 2202 } else if (left->is_double_xmm()) { 2203 assert(left == dest, "left and dest must be equal"); 2204 2205 XMMRegister lreg = left->as_xmm_double_reg(); 2206 if (right->is_double_xmm()) { 2207 XMMRegister rreg = right->as_xmm_double_reg(); 2208 switch (code) { 2209 case lir_add: __ addsd(lreg, rreg); break; 2210 case lir_sub: __ subsd(lreg, rreg); break; 2211 case lir_mul_strictfp: // fall through 2212 case lir_mul: __ mulsd(lreg, rreg); break; 2213 case lir_div_strictfp: // fall through 2214 case lir_div: __ divsd(lreg, rreg); break; 2215 default: ShouldNotReachHere(); 2216 } 2217 } else { 2218 Address raddr; 2219 if (right->is_double_stack()) { 2220 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2221 } else if (right->is_constant()) { 2222 // hack for now 2223 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2224 } else { 2225 ShouldNotReachHere(); 2226 } 2227 switch (code) { 2228 case lir_add: __ addsd(lreg, raddr); break; 2229 case lir_sub: __ subsd(lreg, raddr); break; 2230 case lir_mul_strictfp: // fall through 2231 case lir_mul: __ mulsd(lreg, raddr); break; 2232 case lir_div_strictfp: // fall through 2233 case lir_div: __ divsd(lreg, raddr); break; 2234 default: ShouldNotReachHere(); 2235 } 2236 } 2237 2238 } else if (left->is_single_fpu()) { 2239 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2240 2241 if (right->is_single_fpu()) { 2242 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2243 2244 } else { 2245 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2246 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2247 2248 Address raddr; 2249 if (right->is_single_stack()) { 2250 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2251 } else if (right->is_constant()) { 2252 address const_addr = float_constant(right->as_jfloat()); 2253 assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2254 // hack for now 2255 raddr = __ as_Address(InternalAddress(const_addr)); 2256 } else { 2257 ShouldNotReachHere(); 2258 } 2259 2260 switch (code) { 2261 case lir_add: __ fadd_s(raddr); break; 2262 case lir_sub: __ fsub_s(raddr); break; 2263 case lir_mul_strictfp: // fall through 2264 case lir_mul: __ fmul_s(raddr); break; 2265 case lir_div_strictfp: // fall through 2266 case lir_div: __ fdiv_s(raddr); break; 2267 default: ShouldNotReachHere(); 2268 } 2269 } 2270 2271 } else if (left->is_double_fpu()) { 2272 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2273 2274 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2275 // Double values require special handling for strictfp mul/div on x86 2276 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2277 __ fmulp(left->fpu_regnrLo() + 1); 2278 } 2279 2280 if (right->is_double_fpu()) { 2281 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2282 2283 } else { 2284 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2285 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2286 2287 Address raddr; 2288 if (right->is_double_stack()) { 2289 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2290 } else if (right->is_constant()) { 2291 // hack for now 2292 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2293 } else { 2294 ShouldNotReachHere(); 2295 } 2296 2297 switch (code) { 2298 case lir_add: __ fadd_d(raddr); break; 2299 case lir_sub: __ fsub_d(raddr); break; 2300 case lir_mul_strictfp: // fall through 2301 case lir_mul: __ fmul_d(raddr); break; 2302 case lir_div_strictfp: // fall through 2303 case lir_div: __ fdiv_d(raddr); break; 2304 default: ShouldNotReachHere(); 2305 } 2306 } 2307 2308 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2309 // Double values require special handling for strictfp mul/div on x86 2310 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2311 __ fmulp(dest->fpu_regnrLo() + 1); 2312 } 2313 2314 } else if (left->is_single_stack() || left->is_address()) { 2315 assert(left == dest, "left and dest must be equal"); 2316 2317 Address laddr; 2318 if (left->is_single_stack()) { 2319 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2320 } else if (left->is_address()) { 2321 laddr = as_Address(left->as_address_ptr()); 2322 } else { 2323 ShouldNotReachHere(); 2324 } 2325 2326 if (right->is_single_cpu()) { 2327 Register rreg = right->as_register(); 2328 switch (code) { 2329 case lir_add: __ addl(laddr, rreg); break; 2330 case lir_sub: __ subl(laddr, rreg); break; 2331 default: ShouldNotReachHere(); 2332 } 2333 } else if (right->is_constant()) { 2334 jint c = right->as_constant_ptr()->as_jint(); 2335 switch (code) { 2336 case lir_add: { 2337 __ incrementl(laddr, c); 2338 break; 2339 } 2340 case lir_sub: { 2341 __ decrementl(laddr, c); 2342 break; 2343 } 2344 default: ShouldNotReachHere(); 2345 } 2346 } else { 2347 ShouldNotReachHere(); 2348 } 2349 2350 } else { 2351 ShouldNotReachHere(); 2352 } 2353 } 2354 2355 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2356 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2357 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2358 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2359 2360 bool left_is_tos = (left_index == 0); 2361 bool dest_is_tos = (dest_index == 0); 2362 int non_tos_index = (left_is_tos ? right_index : left_index); 2363 2364 switch (code) { 2365 case lir_add: 2366 if (pop_fpu_stack) __ faddp(non_tos_index); 2367 else if (dest_is_tos) __ fadd (non_tos_index); 2368 else __ fadda(non_tos_index); 2369 break; 2370 2371 case lir_sub: 2372 if (left_is_tos) { 2373 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2374 else if (dest_is_tos) __ fsub (non_tos_index); 2375 else __ fsubra(non_tos_index); 2376 } else { 2377 if (pop_fpu_stack) __ fsubp (non_tos_index); 2378 else if (dest_is_tos) __ fsubr (non_tos_index); 2379 else __ fsuba (non_tos_index); 2380 } 2381 break; 2382 2383 case lir_mul_strictfp: // fall through 2384 case lir_mul: 2385 if (pop_fpu_stack) __ fmulp(non_tos_index); 2386 else if (dest_is_tos) __ fmul (non_tos_index); 2387 else __ fmula(non_tos_index); 2388 break; 2389 2390 case lir_div_strictfp: // fall through 2391 case lir_div: 2392 if (left_is_tos) { 2393 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2394 else if (dest_is_tos) __ fdiv (non_tos_index); 2395 else __ fdivra(non_tos_index); 2396 } else { 2397 if (pop_fpu_stack) __ fdivp (non_tos_index); 2398 else if (dest_is_tos) __ fdivr (non_tos_index); 2399 else __ fdiva (non_tos_index); 2400 } 2401 break; 2402 2403 case lir_rem: 2404 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2405 __ fremr(noreg); 2406 break; 2407 2408 default: 2409 ShouldNotReachHere(); 2410 } 2411 } 2412 2413 2414 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) { 2415 if (value->is_double_xmm()) { 2416 switch(code) { 2417 case lir_abs : 2418 { 2419 #ifdef _LP64 2420 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 2421 assert(tmp->is_valid(), "need temporary"); 2422 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2); 2423 } else 2424 #endif 2425 { 2426 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2427 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2428 } 2429 assert(!tmp->is_valid(), "do not need temporary"); 2430 __ andpd(dest->as_xmm_double_reg(), 2431 ExternalAddress((address)double_signmask_pool)); 2432 } 2433 } 2434 break; 2435 2436 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2437 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2438 default : ShouldNotReachHere(); 2439 } 2440 2441 } else if (value->is_double_fpu()) { 2442 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2443 switch(code) { 2444 case lir_abs : __ fabs() ; break; 2445 case lir_sqrt : __ fsqrt(); break; 2446 default : ShouldNotReachHere(); 2447 } 2448 } else { 2449 Unimplemented(); 2450 } 2451 } 2452 2453 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2454 // assert(left->destroys_register(), "check"); 2455 if (left->is_single_cpu()) { 2456 Register reg = left->as_register(); 2457 if (right->is_constant()) { 2458 int val = right->as_constant_ptr()->as_jint(); 2459 switch (code) { 2460 case lir_logic_and: __ andl (reg, val); break; 2461 case lir_logic_or: __ orl (reg, val); break; 2462 case lir_logic_xor: __ xorl (reg, val); break; 2463 default: ShouldNotReachHere(); 2464 } 2465 } else if (right->is_stack()) { 2466 // added support for stack operands 2467 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2468 switch (code) { 2469 case lir_logic_and: __ andl (reg, raddr); break; 2470 case lir_logic_or: __ orl (reg, raddr); break; 2471 case lir_logic_xor: __ xorl (reg, raddr); break; 2472 default: ShouldNotReachHere(); 2473 } 2474 } else { 2475 Register rright = right->as_register(); 2476 switch (code) { 2477 case lir_logic_and: __ andptr (reg, rright); break; 2478 case lir_logic_or : __ orptr (reg, rright); break; 2479 case lir_logic_xor: __ xorptr (reg, rright); break; 2480 default: ShouldNotReachHere(); 2481 } 2482 } 2483 move_regs(reg, dst->as_register()); 2484 } else { 2485 Register l_lo = left->as_register_lo(); 2486 Register l_hi = left->as_register_hi(); 2487 if (right->is_constant()) { 2488 #ifdef _LP64 2489 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2490 switch (code) { 2491 case lir_logic_and: 2492 __ andq(l_lo, rscratch1); 2493 break; 2494 case lir_logic_or: 2495 __ orq(l_lo, rscratch1); 2496 break; 2497 case lir_logic_xor: 2498 __ xorq(l_lo, rscratch1); 2499 break; 2500 default: ShouldNotReachHere(); 2501 } 2502 #else 2503 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2504 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2505 switch (code) { 2506 case lir_logic_and: 2507 __ andl(l_lo, r_lo); 2508 __ andl(l_hi, r_hi); 2509 break; 2510 case lir_logic_or: 2511 __ orl(l_lo, r_lo); 2512 __ orl(l_hi, r_hi); 2513 break; 2514 case lir_logic_xor: 2515 __ xorl(l_lo, r_lo); 2516 __ xorl(l_hi, r_hi); 2517 break; 2518 default: ShouldNotReachHere(); 2519 } 2520 #endif // _LP64 2521 } else { 2522 #ifdef _LP64 2523 Register r_lo; 2524 if (right->type() == T_OBJECT || right->type() == T_ARRAY || right->type() == T_VALUETYPE) { 2525 r_lo = right->as_register(); 2526 } else { 2527 r_lo = right->as_register_lo(); 2528 } 2529 #else 2530 Register r_lo = right->as_register_lo(); 2531 Register r_hi = right->as_register_hi(); 2532 assert(l_lo != r_hi, "overwriting registers"); 2533 #endif 2534 switch (code) { 2535 case lir_logic_and: 2536 __ andptr(l_lo, r_lo); 2537 NOT_LP64(__ andptr(l_hi, r_hi);) 2538 break; 2539 case lir_logic_or: 2540 __ orptr(l_lo, r_lo); 2541 NOT_LP64(__ orptr(l_hi, r_hi);) 2542 break; 2543 case lir_logic_xor: 2544 __ xorptr(l_lo, r_lo); 2545 NOT_LP64(__ xorptr(l_hi, r_hi);) 2546 break; 2547 default: ShouldNotReachHere(); 2548 } 2549 } 2550 2551 Register dst_lo = dst->as_register_lo(); 2552 Register dst_hi = dst->as_register_hi(); 2553 2554 #ifdef _LP64 2555 move_regs(l_lo, dst_lo); 2556 #else 2557 if (dst_lo == l_hi) { 2558 assert(dst_hi != l_lo, "overwriting registers"); 2559 move_regs(l_hi, dst_hi); 2560 move_regs(l_lo, dst_lo); 2561 } else { 2562 assert(dst_lo != l_hi, "overwriting registers"); 2563 move_regs(l_lo, dst_lo); 2564 move_regs(l_hi, dst_hi); 2565 } 2566 #endif // _LP64 2567 } 2568 } 2569 2570 2571 // we assume that rax, and rdx can be overwritten 2572 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2573 2574 assert(left->is_single_cpu(), "left must be register"); 2575 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2576 assert(result->is_single_cpu(), "result must be register"); 2577 2578 // assert(left->destroys_register(), "check"); 2579 // assert(right->destroys_register(), "check"); 2580 2581 Register lreg = left->as_register(); 2582 Register dreg = result->as_register(); 2583 2584 if (right->is_constant()) { 2585 jint divisor = right->as_constant_ptr()->as_jint(); 2586 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2587 if (code == lir_idiv) { 2588 assert(lreg == rax, "must be rax,"); 2589 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2590 __ cdql(); // sign extend into rdx:rax 2591 if (divisor == 2) { 2592 __ subl(lreg, rdx); 2593 } else { 2594 __ andl(rdx, divisor - 1); 2595 __ addl(lreg, rdx); 2596 } 2597 __ sarl(lreg, log2_jint(divisor)); 2598 move_regs(lreg, dreg); 2599 } else if (code == lir_irem) { 2600 Label done; 2601 __ mov(dreg, lreg); 2602 __ andl(dreg, 0x80000000 | (divisor - 1)); 2603 __ jcc(Assembler::positive, done); 2604 __ decrement(dreg); 2605 __ orl(dreg, ~(divisor - 1)); 2606 __ increment(dreg); 2607 __ bind(done); 2608 } else { 2609 ShouldNotReachHere(); 2610 } 2611 } else { 2612 Register rreg = right->as_register(); 2613 assert(lreg == rax, "left register must be rax,"); 2614 assert(rreg != rdx, "right register must not be rdx"); 2615 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2616 2617 move_regs(lreg, rax); 2618 2619 int idivl_offset = __ corrected_idivl(rreg); 2620 if (ImplicitDiv0Checks) { 2621 add_debug_info_for_div0(idivl_offset, info); 2622 } 2623 if (code == lir_irem) { 2624 move_regs(rdx, dreg); // result is in rdx 2625 } else { 2626 move_regs(rax, dreg); 2627 } 2628 } 2629 } 2630 2631 2632 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2633 if (opr1->is_single_cpu()) { 2634 Register reg1 = opr1->as_register(); 2635 if (opr2->is_single_cpu()) { 2636 // cpu register - cpu register 2637 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY || opr1->type() == T_VALUETYPE) { 2638 __ cmpoop(reg1, opr2->as_register()); 2639 } else { 2640 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_VALUETYPE, "cmp int, oop?"); 2641 __ cmpl(reg1, opr2->as_register()); 2642 } 2643 } else if (opr2->is_stack()) { 2644 // cpu register - stack 2645 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY || opr1->type() == T_VALUETYPE) { 2646 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2647 } else { 2648 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2649 } 2650 } else if (opr2->is_constant()) { 2651 // cpu register - constant 2652 LIR_Const* c = opr2->as_constant_ptr(); 2653 if (c->type() == T_INT) { 2654 __ cmpl(reg1, c->as_jint()); 2655 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) { 2656 // In 64bit oops are single register 2657 jobject o = c->as_jobject(); 2658 if (o == NULL) { 2659 __ cmpptr(reg1, (int32_t)NULL_WORD); 2660 } else { 2661 __ cmpoop(reg1, o); 2662 } 2663 } else { 2664 fatal("unexpected type: %s", basictype_to_str(c->type())); 2665 } 2666 // cpu register - address 2667 } else if (opr2->is_address()) { 2668 if (op->info() != NULL) { 2669 add_debug_info_for_null_check_here(op->info()); 2670 } 2671 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2672 } else { 2673 ShouldNotReachHere(); 2674 } 2675 2676 } else if(opr1->is_double_cpu()) { 2677 Register xlo = opr1->as_register_lo(); 2678 Register xhi = opr1->as_register_hi(); 2679 if (opr2->is_double_cpu()) { 2680 #ifdef _LP64 2681 __ cmpptr(xlo, opr2->as_register_lo()); 2682 #else 2683 // cpu register - cpu register 2684 Register ylo = opr2->as_register_lo(); 2685 Register yhi = opr2->as_register_hi(); 2686 __ subl(xlo, ylo); 2687 __ sbbl(xhi, yhi); 2688 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2689 __ orl(xhi, xlo); 2690 } 2691 #endif // _LP64 2692 } else if (opr2->is_constant()) { 2693 // cpu register - constant 0 2694 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2695 #ifdef _LP64 2696 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2697 #else 2698 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2699 __ orl(xhi, xlo); 2700 #endif // _LP64 2701 } else { 2702 ShouldNotReachHere(); 2703 } 2704 2705 } else if (opr1->is_single_xmm()) { 2706 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2707 if (opr2->is_single_xmm()) { 2708 // xmm register - xmm register 2709 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2710 } else if (opr2->is_stack()) { 2711 // xmm register - stack 2712 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2713 } else if (opr2->is_constant()) { 2714 // xmm register - constant 2715 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2716 } else if (opr2->is_address()) { 2717 // xmm register - address 2718 if (op->info() != NULL) { 2719 add_debug_info_for_null_check_here(op->info()); 2720 } 2721 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2722 } else { 2723 ShouldNotReachHere(); 2724 } 2725 2726 } else if (opr1->is_double_xmm()) { 2727 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2728 if (opr2->is_double_xmm()) { 2729 // xmm register - xmm register 2730 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2731 } else if (opr2->is_stack()) { 2732 // xmm register - stack 2733 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2734 } else if (opr2->is_constant()) { 2735 // xmm register - constant 2736 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2737 } else if (opr2->is_address()) { 2738 // xmm register - address 2739 if (op->info() != NULL) { 2740 add_debug_info_for_null_check_here(op->info()); 2741 } 2742 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2743 } else { 2744 ShouldNotReachHere(); 2745 } 2746 2747 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2748 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2749 assert(opr2->is_fpu_register(), "both must be registers"); 2750 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2751 2752 } else if (opr1->is_address() && opr2->is_constant()) { 2753 LIR_Const* c = opr2->as_constant_ptr(); 2754 #ifdef _LP64 2755 if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) { 2756 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2757 __ movoop(rscratch1, c->as_jobject()); 2758 } 2759 #endif // LP64 2760 if (op->info() != NULL) { 2761 add_debug_info_for_null_check_here(op->info()); 2762 } 2763 // special case: address - constant 2764 LIR_Address* addr = opr1->as_address_ptr(); 2765 if (c->type() == T_INT) { 2766 __ cmpl(as_Address(addr), c->as_jint()); 2767 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) { 2768 #ifdef _LP64 2769 // %%% Make this explode if addr isn't reachable until we figure out a 2770 // better strategy by giving noreg as the temp for as_Address 2771 __ cmpoop(rscratch1, as_Address(addr, noreg)); 2772 #else 2773 __ cmpoop(as_Address(addr), c->as_jobject()); 2774 #endif // _LP64 2775 } else { 2776 ShouldNotReachHere(); 2777 } 2778 2779 } else { 2780 ShouldNotReachHere(); 2781 } 2782 } 2783 2784 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2785 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2786 if (left->is_single_xmm()) { 2787 assert(right->is_single_xmm(), "must match"); 2788 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2789 } else if (left->is_double_xmm()) { 2790 assert(right->is_double_xmm(), "must match"); 2791 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2792 2793 } else { 2794 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2795 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2796 2797 assert(left->fpu() == 0, "left must be on TOS"); 2798 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2799 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2800 } 2801 } else { 2802 assert(code == lir_cmp_l2i, "check"); 2803 #ifdef _LP64 2804 Label done; 2805 Register dest = dst->as_register(); 2806 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2807 __ movl(dest, -1); 2808 __ jccb(Assembler::less, done); 2809 __ set_byte_if_not_zero(dest); 2810 __ movzbl(dest, dest); 2811 __ bind(done); 2812 #else 2813 __ lcmp2int(left->as_register_hi(), 2814 left->as_register_lo(), 2815 right->as_register_hi(), 2816 right->as_register_lo()); 2817 move_regs(left->as_register_hi(), dst->as_register()); 2818 #endif // _LP64 2819 } 2820 } 2821 2822 2823 void LIR_Assembler::align_call(LIR_Code code) { 2824 // make sure that the displacement word of the call ends up word aligned 2825 int offset = __ offset(); 2826 switch (code) { 2827 case lir_static_call: 2828 case lir_optvirtual_call: 2829 case lir_dynamic_call: 2830 offset += NativeCall::displacement_offset; 2831 break; 2832 case lir_icvirtual_call: 2833 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2834 break; 2835 case lir_virtual_call: // currently, sparc-specific for niagara 2836 default: ShouldNotReachHere(); 2837 } 2838 __ align(BytesPerWord, offset); 2839 } 2840 2841 2842 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2843 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2844 "must be aligned"); 2845 __ call(AddressLiteral(op->addr(), rtype)); 2846 add_call_info(code_offset(), op->info()); 2847 } 2848 2849 2850 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2851 __ ic_call(op->addr()); 2852 add_call_info(code_offset(), op->info()); 2853 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0, 2854 "must be aligned"); 2855 } 2856 2857 2858 /* Currently, vtable-dispatch is only enabled for sparc platforms */ 2859 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 2860 ShouldNotReachHere(); 2861 } 2862 2863 2864 void LIR_Assembler::emit_static_call_stub() { 2865 address call_pc = __ pc(); 2866 address stub = __ start_a_stub(call_stub_size()); 2867 if (stub == NULL) { 2868 bailout("static call stub overflow"); 2869 return; 2870 } 2871 2872 int start = __ offset(); 2873 2874 // make sure that the displacement word of the call ends up word aligned 2875 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset); 2876 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */)); 2877 __ mov_metadata(rbx, (Metadata*)NULL); 2878 // must be set to -1 at code generation time 2879 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned"); 2880 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2881 __ jump(RuntimeAddress(__ pc())); 2882 2883 if (UseAOT) { 2884 // Trampoline to aot code 2885 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */)); 2886 #ifdef _LP64 2887 __ mov64(rax, CONST64(0)); // address is zapped till fixup time. 2888 #else 2889 __ movl(rax, 0xdeadffff); // address is zapped till fixup time. 2890 #endif 2891 __ jmp(rax); 2892 } 2893 assert(__ offset() - start <= call_stub_size(), "stub too big"); 2894 __ end_a_stub(); 2895 } 2896 2897 2898 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2899 assert(exceptionOop->as_register() == rax, "must match"); 2900 assert(exceptionPC->as_register() == rdx, "must match"); 2901 2902 // exception object is not added to oop map by LinearScan 2903 // (LinearScan assumes that no oops are in fixed registers) 2904 info->add_register_oop(exceptionOop); 2905 Runtime1::StubID unwind_id; 2906 2907 // get current pc information 2908 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2909 int pc_for_athrow_offset = __ offset(); 2910 InternalAddress pc_for_athrow(__ pc()); 2911 __ lea(exceptionPC->as_register(), pc_for_athrow); 2912 add_call_info(pc_for_athrow_offset, info); // for exception handler 2913 2914 __ verify_not_null_oop(rax); 2915 // search an exception handler (rax: exception oop, rdx: throwing pc) 2916 if (compilation()->has_fpu_code()) { 2917 unwind_id = Runtime1::handle_exception_id; 2918 } else { 2919 unwind_id = Runtime1::handle_exception_nofpu_id; 2920 } 2921 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2922 2923 // enough room for two byte trap 2924 __ nop(); 2925 } 2926 2927 2928 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2929 assert(exceptionOop->as_register() == rax, "must match"); 2930 2931 __ jmp(_unwind_handler_entry); 2932 } 2933 2934 2935 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2936 2937 // optimized version for linear scan: 2938 // * count must be already in ECX (guaranteed by LinearScan) 2939 // * left and dest must be equal 2940 // * tmp must be unused 2941 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2942 assert(left == dest, "left and dest must be equal"); 2943 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2944 2945 if (left->is_single_cpu()) { 2946 Register value = left->as_register(); 2947 assert(value != SHIFT_count, "left cannot be ECX"); 2948 2949 switch (code) { 2950 case lir_shl: __ shll(value); break; 2951 case lir_shr: __ sarl(value); break; 2952 case lir_ushr: __ shrl(value); break; 2953 default: ShouldNotReachHere(); 2954 } 2955 } else if (left->is_double_cpu()) { 2956 Register lo = left->as_register_lo(); 2957 Register hi = left->as_register_hi(); 2958 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2959 #ifdef _LP64 2960 switch (code) { 2961 case lir_shl: __ shlptr(lo); break; 2962 case lir_shr: __ sarptr(lo); break; 2963 case lir_ushr: __ shrptr(lo); break; 2964 default: ShouldNotReachHere(); 2965 } 2966 #else 2967 2968 switch (code) { 2969 case lir_shl: __ lshl(hi, lo); break; 2970 case lir_shr: __ lshr(hi, lo, true); break; 2971 case lir_ushr: __ lshr(hi, lo, false); break; 2972 default: ShouldNotReachHere(); 2973 } 2974 #endif // LP64 2975 } else { 2976 ShouldNotReachHere(); 2977 } 2978 } 2979 2980 2981 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2982 if (dest->is_single_cpu()) { 2983 // first move left into dest so that left is not destroyed by the shift 2984 Register value = dest->as_register(); 2985 count = count & 0x1F; // Java spec 2986 2987 move_regs(left->as_register(), value); 2988 switch (code) { 2989 case lir_shl: __ shll(value, count); break; 2990 case lir_shr: __ sarl(value, count); break; 2991 case lir_ushr: __ shrl(value, count); break; 2992 default: ShouldNotReachHere(); 2993 } 2994 } else if (dest->is_double_cpu()) { 2995 #ifndef _LP64 2996 Unimplemented(); 2997 #else 2998 // first move left into dest so that left is not destroyed by the shift 2999 Register value = dest->as_register_lo(); 3000 count = count & 0x1F; // Java spec 3001 3002 move_regs(left->as_register_lo(), value); 3003 switch (code) { 3004 case lir_shl: __ shlptr(value, count); break; 3005 case lir_shr: __ sarptr(value, count); break; 3006 case lir_ushr: __ shrptr(value, count); break; 3007 default: ShouldNotReachHere(); 3008 } 3009 #endif // _LP64 3010 } else { 3011 ShouldNotReachHere(); 3012 } 3013 } 3014 3015 3016 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 3017 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3018 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3019 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3020 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 3021 } 3022 3023 3024 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 3025 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3026 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3027 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3028 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 3029 } 3030 3031 3032 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 3033 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3034 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3035 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3036 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 3037 } 3038 3039 3040 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) { 3041 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3042 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3043 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3044 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m); 3045 } 3046 3047 3048 void LIR_Assembler::arraycopy_flat_check(Register obj, Register tmp, CodeStub* slow_path) { 3049 Address klass_addr = Address(obj, oopDesc::klass_offset_in_bytes()); 3050 if (UseCompressedClassPointers) { 3051 __ movl(tmp, klass_addr); 3052 LP64_ONLY(__ decode_klass_not_null(tmp)); 3053 } else { 3054 __ movptr(tmp, klass_addr); 3055 } 3056 __ movl(tmp, Address(tmp, Klass::layout_helper_offset())); 3057 __ sarl(tmp, Klass::_lh_array_tag_shift); 3058 __ cmpl(tmp, Klass::_lh_array_tag_vt_value); 3059 __ jcc(Assembler::equal, *slow_path->entry()); 3060 } 3061 3062 3063 // This code replaces a call to arraycopy; no exception may 3064 // be thrown in this code, they must be thrown in the System.arraycopy 3065 // activation frame; we could save some checks if this would not be the case 3066 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 3067 ciArrayKlass* default_type = op->expected_type(); 3068 Register src = op->src()->as_register(); 3069 Register dst = op->dst()->as_register(); 3070 Register src_pos = op->src_pos()->as_register(); 3071 Register dst_pos = op->dst_pos()->as_register(); 3072 Register length = op->length()->as_register(); 3073 Register tmp = op->tmp()->as_register(); 3074 3075 __ resolve(ACCESS_READ, src); 3076 __ resolve(ACCESS_WRITE, dst); 3077 3078 CodeStub* stub = op->stub(); 3079 int flags = op->flags(); 3080 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 3081 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 3082 3083 if (flags & LIR_OpArrayCopy::always_slow_path) { 3084 __ jmp(*stub->entry()); 3085 __ bind(*stub->continuation()); 3086 return; 3087 } 3088 3089 if (flags & LIR_OpArrayCopy::src_flat_check) { 3090 arraycopy_flat_check(src, tmp, stub); 3091 } 3092 3093 if (flags & LIR_OpArrayCopy::dst_flat_check) { 3094 arraycopy_flat_check(dst, tmp, stub); 3095 } 3096 3097 if (basic_type == T_VALUETYPE) { 3098 assert(flags & (LIR_OpArrayCopy::always_slow_path | 3099 LIR_OpArrayCopy::src_flat_check | 3100 LIR_OpArrayCopy::dst_flat_check), "must have checked"); 3101 // If either src or dst is (or maybe) a flattened array, one of the 3 checks 3102 // above would have caught it, and taken the slow path. So when we come here, 3103 // the array must be a (non-flat) object array. 3104 basic_type = T_OBJECT; 3105 } 3106 3107 // if we don't know anything, just go through the generic arraycopy 3108 if (default_type == NULL) { 3109 // save outgoing arguments on stack in case call to System.arraycopy is needed 3110 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3111 // for interpreter calling conventions. Now we have to do it in new style conventions. 3112 // For the moment until C1 gets the new register allocator I just force all the 3113 // args to the right place (except the register args) and then on the back side 3114 // reload the register args properly if we go slow path. Yuck 3115 3116 // These are proper for the calling convention 3117 store_parameter(length, 2); 3118 store_parameter(dst_pos, 1); 3119 store_parameter(dst, 0); 3120 3121 // these are just temporary placements until we need to reload 3122 store_parameter(src_pos, 3); 3123 store_parameter(src, 4); 3124 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3125 3126 address copyfunc_addr = StubRoutines::generic_arraycopy(); 3127 assert(copyfunc_addr != NULL, "generic arraycopy stub required"); 3128 3129 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3130 #ifdef _LP64 3131 // The arguments are in java calling convention so we can trivially shift them to C 3132 // convention 3133 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3134 __ mov(c_rarg0, j_rarg0); 3135 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3136 __ mov(c_rarg1, j_rarg1); 3137 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3138 __ mov(c_rarg2, j_rarg2); 3139 assert_different_registers(c_rarg3, j_rarg4); 3140 __ mov(c_rarg3, j_rarg3); 3141 #ifdef _WIN64 3142 // Allocate abi space for args but be sure to keep stack aligned 3143 __ subptr(rsp, 6*wordSize); 3144 store_parameter(j_rarg4, 4); 3145 #ifndef PRODUCT 3146 if (PrintC1Statistics) { 3147 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3148 } 3149 #endif 3150 __ call(RuntimeAddress(copyfunc_addr)); 3151 __ addptr(rsp, 6*wordSize); 3152 #else 3153 __ mov(c_rarg4, j_rarg4); 3154 #ifndef PRODUCT 3155 if (PrintC1Statistics) { 3156 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3157 } 3158 #endif 3159 __ call(RuntimeAddress(copyfunc_addr)); 3160 #endif // _WIN64 3161 #else 3162 __ push(length); 3163 __ push(dst_pos); 3164 __ push(dst); 3165 __ push(src_pos); 3166 __ push(src); 3167 3168 #ifndef PRODUCT 3169 if (PrintC1Statistics) { 3170 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3171 } 3172 #endif 3173 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack 3174 3175 #endif // _LP64 3176 3177 __ cmpl(rax, 0); 3178 __ jcc(Assembler::equal, *stub->continuation()); 3179 3180 __ mov(tmp, rax); 3181 __ xorl(tmp, -1); 3182 3183 // Reload values from the stack so they are where the stub 3184 // expects them. 3185 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3186 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3187 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3188 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3189 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3190 3191 __ subl(length, tmp); 3192 __ addl(src_pos, tmp); 3193 __ addl(dst_pos, tmp); 3194 __ jmp(*stub->entry()); 3195 3196 __ bind(*stub->continuation()); 3197 return; 3198 } 3199 3200 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3201 3202 int elem_size = type2aelembytes(basic_type); 3203 Address::ScaleFactor scale; 3204 3205 switch (elem_size) { 3206 case 1 : 3207 scale = Address::times_1; 3208 break; 3209 case 2 : 3210 scale = Address::times_2; 3211 break; 3212 case 4 : 3213 scale = Address::times_4; 3214 break; 3215 case 8 : 3216 scale = Address::times_8; 3217 break; 3218 default: 3219 scale = Address::no_scale; 3220 ShouldNotReachHere(); 3221 } 3222 3223 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3224 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3225 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3226 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3227 3228 // length and pos's are all sign extended at this point on 64bit 3229 3230 // test for NULL 3231 if (flags & LIR_OpArrayCopy::src_null_check) { 3232 __ testptr(src, src); 3233 __ jcc(Assembler::zero, *stub->entry()); 3234 } 3235 if (flags & LIR_OpArrayCopy::dst_null_check) { 3236 __ testptr(dst, dst); 3237 __ jcc(Assembler::zero, *stub->entry()); 3238 } 3239 3240 // If the compiler was not able to prove that exact type of the source or the destination 3241 // of the arraycopy is an array type, check at runtime if the source or the destination is 3242 // an instance type. 3243 if (flags & LIR_OpArrayCopy::type_check) { 3244 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3245 __ load_klass(tmp, dst); 3246 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3247 __ jcc(Assembler::greaterEqual, *stub->entry()); 3248 } 3249 3250 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3251 __ load_klass(tmp, src); 3252 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3253 __ jcc(Assembler::greaterEqual, *stub->entry()); 3254 } 3255 } 3256 3257 // check if negative 3258 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3259 __ testl(src_pos, src_pos); 3260 __ jcc(Assembler::less, *stub->entry()); 3261 } 3262 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3263 __ testl(dst_pos, dst_pos); 3264 __ jcc(Assembler::less, *stub->entry()); 3265 } 3266 3267 if (flags & LIR_OpArrayCopy::src_range_check) { 3268 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3269 __ cmpl(tmp, src_length_addr); 3270 __ jcc(Assembler::above, *stub->entry()); 3271 } 3272 if (flags & LIR_OpArrayCopy::dst_range_check) { 3273 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3274 __ cmpl(tmp, dst_length_addr); 3275 __ jcc(Assembler::above, *stub->entry()); 3276 } 3277 3278 if (flags & LIR_OpArrayCopy::length_positive_check) { 3279 __ testl(length, length); 3280 __ jcc(Assembler::less, *stub->entry()); 3281 } 3282 3283 #ifdef _LP64 3284 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3285 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3286 #endif 3287 3288 if (flags & LIR_OpArrayCopy::type_check) { 3289 // We don't know the array types are compatible 3290 if (basic_type != T_OBJECT) { 3291 // Simple test for basic type arrays 3292 if (UseCompressedClassPointers) { 3293 __ movl(tmp, src_klass_addr); 3294 __ cmpl(tmp, dst_klass_addr); 3295 } else { 3296 __ movptr(tmp, src_klass_addr); 3297 __ cmpptr(tmp, dst_klass_addr); 3298 } 3299 __ jcc(Assembler::notEqual, *stub->entry()); 3300 } else { 3301 // For object arrays, if src is a sub class of dst then we can 3302 // safely do the copy. 3303 Label cont, slow; 3304 3305 __ push(src); 3306 __ push(dst); 3307 3308 __ load_klass(src, src); 3309 __ load_klass(dst, dst); 3310 3311 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); 3312 3313 __ push(src); 3314 __ push(dst); 3315 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 3316 __ pop(dst); 3317 __ pop(src); 3318 3319 __ cmpl(src, 0); 3320 __ jcc(Assembler::notEqual, cont); 3321 3322 __ bind(slow); 3323 __ pop(dst); 3324 __ pop(src); 3325 3326 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 3327 if (copyfunc_addr != NULL) { // use stub if available 3328 // src is not a sub class of dst so we have to do a 3329 // per-element check. 3330 3331 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 3332 if ((flags & mask) != mask) { 3333 // Check that at least both of them object arrays. 3334 assert(flags & mask, "one of the two should be known to be an object array"); 3335 3336 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3337 __ load_klass(tmp, src); 3338 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3339 __ load_klass(tmp, dst); 3340 } 3341 int lh_offset = in_bytes(Klass::layout_helper_offset()); 3342 Address klass_lh_addr(tmp, lh_offset); 3343 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 3344 __ cmpl(klass_lh_addr, objArray_lh); 3345 __ jcc(Assembler::notEqual, *stub->entry()); 3346 } 3347 3348 // Spill because stubs can use any register they like and it's 3349 // easier to restore just those that we care about. 3350 store_parameter(dst, 0); 3351 store_parameter(dst_pos, 1); 3352 store_parameter(length, 2); 3353 store_parameter(src_pos, 3); 3354 store_parameter(src, 4); 3355 3356 #ifndef _LP64 3357 __ movptr(tmp, dst_klass_addr); 3358 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset())); 3359 __ push(tmp); 3360 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); 3361 __ push(tmp); 3362 __ push(length); 3363 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3364 __ push(tmp); 3365 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3366 __ push(tmp); 3367 3368 __ call_VM_leaf(copyfunc_addr, 5); 3369 #else 3370 __ movl2ptr(length, length); //higher 32bits must be null 3371 3372 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3373 assert_different_registers(c_rarg0, dst, dst_pos, length); 3374 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3375 assert_different_registers(c_rarg1, dst, length); 3376 3377 __ mov(c_rarg2, length); 3378 assert_different_registers(c_rarg2, dst); 3379 3380 #ifdef _WIN64 3381 // Allocate abi space for args but be sure to keep stack aligned 3382 __ subptr(rsp, 6*wordSize); 3383 __ load_klass(c_rarg3, dst); 3384 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset())); 3385 store_parameter(c_rarg3, 4); 3386 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); 3387 __ call(RuntimeAddress(copyfunc_addr)); 3388 __ addptr(rsp, 6*wordSize); 3389 #else 3390 __ load_klass(c_rarg4, dst); 3391 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 3392 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 3393 __ call(RuntimeAddress(copyfunc_addr)); 3394 #endif 3395 3396 #endif 3397 3398 #ifndef PRODUCT 3399 if (PrintC1Statistics) { 3400 Label failed; 3401 __ testl(rax, rax); 3402 __ jcc(Assembler::notZero, failed); 3403 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 3404 __ bind(failed); 3405 } 3406 #endif 3407 3408 __ testl(rax, rax); 3409 __ jcc(Assembler::zero, *stub->continuation()); 3410 3411 #ifndef PRODUCT 3412 if (PrintC1Statistics) { 3413 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 3414 } 3415 #endif 3416 3417 __ mov(tmp, rax); 3418 3419 __ xorl(tmp, -1); 3420 3421 // Restore previously spilled arguments 3422 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3423 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3424 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3425 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3426 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3427 3428 3429 __ subl(length, tmp); 3430 __ addl(src_pos, tmp); 3431 __ addl(dst_pos, tmp); 3432 } 3433 3434 __ jmp(*stub->entry()); 3435 3436 __ bind(cont); 3437 __ pop(dst); 3438 __ pop(src); 3439 } 3440 } 3441 3442 #ifdef ASSERT 3443 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3444 // Sanity check the known type with the incoming class. For the 3445 // primitive case the types must match exactly with src.klass and 3446 // dst.klass each exactly matching the default type. For the 3447 // object array case, if no type check is needed then either the 3448 // dst type is exactly the expected type and the src type is a 3449 // subtype which we can't check or src is the same array as dst 3450 // but not necessarily exactly of type default_type. 3451 Label known_ok, halt; 3452 __ mov_metadata(tmp, default_type->constant_encoding()); 3453 #ifdef _LP64 3454 if (UseCompressedClassPointers) { 3455 __ encode_klass_not_null(tmp); 3456 } 3457 #endif 3458 3459 if (basic_type != T_OBJECT) { 3460 3461 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3462 else __ cmpptr(tmp, dst_klass_addr); 3463 __ jcc(Assembler::notEqual, halt); 3464 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr); 3465 else __ cmpptr(tmp, src_klass_addr); 3466 __ jcc(Assembler::equal, known_ok); 3467 } else { 3468 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3469 else __ cmpptr(tmp, dst_klass_addr); 3470 __ jcc(Assembler::equal, known_ok); 3471 __ cmpptr(src, dst); 3472 __ jcc(Assembler::equal, known_ok); 3473 } 3474 __ bind(halt); 3475 __ stop("incorrect type information in arraycopy"); 3476 __ bind(known_ok); 3477 } 3478 #endif 3479 3480 #ifndef PRODUCT 3481 if (PrintC1Statistics) { 3482 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 3483 } 3484 #endif 3485 3486 #ifdef _LP64 3487 assert_different_registers(c_rarg0, dst, dst_pos, length); 3488 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3489 assert_different_registers(c_rarg1, length); 3490 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3491 __ mov(c_rarg2, length); 3492 3493 #else 3494 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3495 store_parameter(tmp, 0); 3496 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3497 store_parameter(tmp, 1); 3498 store_parameter(length, 2); 3499 #endif // _LP64 3500 3501 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 3502 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 3503 const char *name; 3504 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 3505 __ call_VM_leaf(entry, 0); 3506 3507 __ bind(*stub->continuation()); 3508 } 3509 3510 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3511 assert(op->crc()->is_single_cpu(), "crc must be register"); 3512 assert(op->val()->is_single_cpu(), "byte value must be register"); 3513 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3514 Register crc = op->crc()->as_register(); 3515 Register val = op->val()->as_register(); 3516 Register res = op->result_opr()->as_register(); 3517 3518 assert_different_registers(val, crc, res); 3519 3520 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr())); 3521 __ notl(crc); // ~crc 3522 __ update_byte_crc32(crc, val, res); 3523 __ notl(crc); // ~crc 3524 __ mov(res, crc); 3525 } 3526 3527 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3528 Register obj = op->obj_opr()->as_register(); // may not be an oop 3529 Register hdr = op->hdr_opr()->as_register(); 3530 Register lock = op->lock_opr()->as_register(); 3531 if (!UseFastLocking) { 3532 __ jmp(*op->stub()->entry()); 3533 } else if (op->code() == lir_lock) { 3534 Register scratch = noreg; 3535 if (UseBiasedLocking) { 3536 scratch = op->scratch_opr()->as_register(); 3537 } 3538 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3539 __ resolve(ACCESS_READ | ACCESS_WRITE, obj); 3540 // add debug info for NullPointerException only if one is possible 3541 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3542 if (op->info() != NULL) { 3543 add_debug_info_for_null_check(null_check_offset, op->info()); 3544 } 3545 // done 3546 } else if (op->code() == lir_unlock) { 3547 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3548 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3549 } else { 3550 Unimplemented(); 3551 } 3552 __ bind(*op->stub()->continuation()); 3553 } 3554 3555 3556 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3557 ciMethod* method = op->profiled_method(); 3558 int bci = op->profiled_bci(); 3559 ciMethod* callee = op->profiled_callee(); 3560 3561 // Update counter for all call types 3562 ciMethodData* md = method->method_data_or_null(); 3563 assert(md != NULL, "Sanity"); 3564 ciProfileData* data = md->bci_to_data(bci); 3565 assert(data != NULL && data->is_CounterData(), "need CounterData for calls"); 3566 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3567 Register mdo = op->mdo()->as_register(); 3568 __ mov_metadata(mdo, md->constant_encoding()); 3569 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3570 // Perform additional virtual call profiling for invokevirtual and 3571 // invokeinterface bytecodes 3572 if (op->should_profile_receiver_type()) { 3573 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3574 Register recv = op->recv()->as_register(); 3575 assert_different_registers(mdo, recv); 3576 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3577 ciKlass* known_klass = op->known_holder(); 3578 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 3579 // We know the type that will be seen at this call site; we can 3580 // statically update the MethodData* rather than needing to do 3581 // dynamic tests on the receiver type 3582 3583 // NOTE: we should probably put a lock around this search to 3584 // avoid collisions by concurrent compilations 3585 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3586 uint i; 3587 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3588 ciKlass* receiver = vc_data->receiver(i); 3589 if (known_klass->equals(receiver)) { 3590 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3591 __ addptr(data_addr, DataLayout::counter_increment); 3592 return; 3593 } 3594 } 3595 3596 // Receiver type not found in profile data; select an empty slot 3597 3598 // Note that this is less efficient than it should be because it 3599 // always does a write to the receiver part of the 3600 // VirtualCallData rather than just the first time 3601 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3602 ciKlass* receiver = vc_data->receiver(i); 3603 if (receiver == NULL) { 3604 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3605 __ mov_metadata(recv_addr, known_klass->constant_encoding()); 3606 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3607 __ addptr(data_addr, DataLayout::counter_increment); 3608 return; 3609 } 3610 } 3611 } else { 3612 __ load_klass(recv, recv); 3613 Label update_done; 3614 type_profile_helper(mdo, md, data, recv, &update_done); 3615 // Receiver did not match any saved receiver and there is no empty row for it. 3616 // Increment total counter to indicate polymorphic case. 3617 __ addptr(counter_addr, DataLayout::counter_increment); 3618 3619 __ bind(update_done); 3620 } 3621 } else { 3622 // Static call 3623 __ addptr(counter_addr, DataLayout::counter_increment); 3624 } 3625 } 3626 3627 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3628 Register obj = op->obj()->as_register(); 3629 Register tmp = op->tmp()->as_pointer_register(); 3630 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 3631 ciKlass* exact_klass = op->exact_klass(); 3632 intptr_t current_klass = op->current_klass(); 3633 bool not_null = op->not_null(); 3634 bool no_conflict = op->no_conflict(); 3635 3636 Label update, next, none; 3637 3638 bool do_null = !not_null; 3639 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3640 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3641 3642 assert(do_null || do_update, "why are we here?"); 3643 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3644 3645 __ verify_oop(obj); 3646 3647 if (tmp != obj) { 3648 __ mov(tmp, obj); 3649 } 3650 if (do_null) { 3651 __ testptr(tmp, tmp); 3652 __ jccb(Assembler::notZero, update); 3653 if (!TypeEntries::was_null_seen(current_klass)) { 3654 __ orptr(mdo_addr, TypeEntries::null_seen); 3655 } 3656 if (do_update) { 3657 #ifndef ASSERT 3658 __ jmpb(next); 3659 } 3660 #else 3661 __ jmp(next); 3662 } 3663 } else { 3664 __ testptr(tmp, tmp); 3665 __ jcc(Assembler::notZero, update); 3666 __ stop("unexpect null obj"); 3667 #endif 3668 } 3669 3670 __ bind(update); 3671 3672 if (do_update) { 3673 #ifdef ASSERT 3674 if (exact_klass != NULL) { 3675 Label ok; 3676 __ load_klass(tmp, tmp); 3677 __ push(tmp); 3678 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3679 __ cmpptr(tmp, Address(rsp, 0)); 3680 __ jcc(Assembler::equal, ok); 3681 __ stop("exact klass and actual klass differ"); 3682 __ bind(ok); 3683 __ pop(tmp); 3684 } 3685 #endif 3686 if (!no_conflict) { 3687 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 3688 if (exact_klass != NULL) { 3689 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3690 } else { 3691 __ load_klass(tmp, tmp); 3692 } 3693 3694 __ xorptr(tmp, mdo_addr); 3695 __ testptr(tmp, TypeEntries::type_klass_mask); 3696 // klass seen before, nothing to do. The unknown bit may have been 3697 // set already but no need to check. 3698 __ jccb(Assembler::zero, next); 3699 3700 __ testptr(tmp, TypeEntries::type_unknown); 3701 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3702 3703 if (TypeEntries::is_type_none(current_klass)) { 3704 __ cmpptr(mdo_addr, 0); 3705 __ jccb(Assembler::equal, none); 3706 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3707 __ jccb(Assembler::equal, none); 3708 // There is a chance that the checks above (re-reading profiling 3709 // data from memory) fail if another thread has just set the 3710 // profiling to this obj's klass 3711 __ xorptr(tmp, mdo_addr); 3712 __ testptr(tmp, TypeEntries::type_klass_mask); 3713 __ jccb(Assembler::zero, next); 3714 } 3715 } else { 3716 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3717 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3718 3719 __ movptr(tmp, mdo_addr); 3720 __ testptr(tmp, TypeEntries::type_unknown); 3721 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3722 } 3723 3724 // different than before. Cannot keep accurate profile. 3725 __ orptr(mdo_addr, TypeEntries::type_unknown); 3726 3727 if (TypeEntries::is_type_none(current_klass)) { 3728 __ jmpb(next); 3729 3730 __ bind(none); 3731 // first time here. Set profile type. 3732 __ movptr(mdo_addr, tmp); 3733 } 3734 } else { 3735 // There's a single possible klass at this profile point 3736 assert(exact_klass != NULL, "should be"); 3737 if (TypeEntries::is_type_none(current_klass)) { 3738 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3739 __ xorptr(tmp, mdo_addr); 3740 __ testptr(tmp, TypeEntries::type_klass_mask); 3741 #ifdef ASSERT 3742 __ jcc(Assembler::zero, next); 3743 3744 { 3745 Label ok; 3746 __ push(tmp); 3747 __ cmpptr(mdo_addr, 0); 3748 __ jcc(Assembler::equal, ok); 3749 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3750 __ jcc(Assembler::equal, ok); 3751 // may have been set by another thread 3752 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3753 __ xorptr(tmp, mdo_addr); 3754 __ testptr(tmp, TypeEntries::type_mask); 3755 __ jcc(Assembler::zero, ok); 3756 3757 __ stop("unexpected profiling mismatch"); 3758 __ bind(ok); 3759 __ pop(tmp); 3760 } 3761 #else 3762 __ jccb(Assembler::zero, next); 3763 #endif 3764 // first time here. Set profile type. 3765 __ movptr(mdo_addr, tmp); 3766 } else { 3767 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3768 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3769 3770 __ movptr(tmp, mdo_addr); 3771 __ testptr(tmp, TypeEntries::type_unknown); 3772 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3773 3774 __ orptr(mdo_addr, TypeEntries::type_unknown); 3775 } 3776 } 3777 3778 __ bind(next); 3779 } 3780 } 3781 3782 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3783 Unimplemented(); 3784 } 3785 3786 3787 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3788 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3789 } 3790 3791 3792 void LIR_Assembler::align_backward_branch_target() { 3793 __ align(BytesPerWord); 3794 } 3795 3796 3797 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) { 3798 if (left->is_single_cpu()) { 3799 __ negl(left->as_register()); 3800 move_regs(left->as_register(), dest->as_register()); 3801 3802 } else if (left->is_double_cpu()) { 3803 Register lo = left->as_register_lo(); 3804 #ifdef _LP64 3805 Register dst = dest->as_register_lo(); 3806 __ movptr(dst, lo); 3807 __ negptr(dst); 3808 #else 3809 Register hi = left->as_register_hi(); 3810 __ lneg(hi, lo); 3811 if (dest->as_register_lo() == hi) { 3812 assert(dest->as_register_hi() != lo, "destroying register"); 3813 move_regs(hi, dest->as_register_hi()); 3814 move_regs(lo, dest->as_register_lo()); 3815 } else { 3816 move_regs(lo, dest->as_register_lo()); 3817 move_regs(hi, dest->as_register_hi()); 3818 } 3819 #endif // _LP64 3820 3821 } else if (dest->is_single_xmm()) { 3822 #ifdef _LP64 3823 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3824 assert(tmp->is_valid(), "need temporary"); 3825 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg()); 3826 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2); 3827 } 3828 else 3829 #endif 3830 { 3831 assert(!tmp->is_valid(), "do not need temporary"); 3832 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3833 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3834 } 3835 __ xorps(dest->as_xmm_float_reg(), 3836 ExternalAddress((address)float_signflip_pool)); 3837 } 3838 } else if (dest->is_double_xmm()) { 3839 #ifdef _LP64 3840 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3841 assert(tmp->is_valid(), "need temporary"); 3842 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg()); 3843 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2); 3844 } 3845 else 3846 #endif 3847 { 3848 assert(!tmp->is_valid(), "do not need temporary"); 3849 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3850 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3851 } 3852 __ xorpd(dest->as_xmm_double_reg(), 3853 ExternalAddress((address)double_signflip_pool)); 3854 } 3855 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3856 assert(left->fpu() == 0, "arg must be on TOS"); 3857 assert(dest->fpu() == 0, "dest must be TOS"); 3858 __ fchs(); 3859 3860 } else { 3861 ShouldNotReachHere(); 3862 } 3863 } 3864 3865 3866 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 3867 assert(src->is_address(), "must be an address"); 3868 assert(dest->is_register(), "must be a register"); 3869 3870 PatchingStub* patch = NULL; 3871 if (patch_code != lir_patch_none) { 3872 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 3873 } 3874 3875 Register reg = dest->as_pointer_register(); 3876 LIR_Address* addr = src->as_address_ptr(); 3877 __ lea(reg, as_Address(addr)); 3878 3879 if (patch != NULL) { 3880 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 3881 } 3882 } 3883 3884 3885 3886 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3887 assert(!tmp->is_valid(), "don't need temporary"); 3888 __ call(RuntimeAddress(dest)); 3889 if (info != NULL) { 3890 add_call_info_here(info); 3891 } 3892 } 3893 3894 3895 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3896 assert(type == T_LONG, "only for volatile long fields"); 3897 3898 if (info != NULL) { 3899 add_debug_info_for_null_check_here(info); 3900 } 3901 3902 if (src->is_double_xmm()) { 3903 if (dest->is_double_cpu()) { 3904 #ifdef _LP64 3905 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3906 #else 3907 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3908 __ psrlq(src->as_xmm_double_reg(), 32); 3909 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3910 #endif // _LP64 3911 } else if (dest->is_double_stack()) { 3912 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3913 } else if (dest->is_address()) { 3914 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3915 } else { 3916 ShouldNotReachHere(); 3917 } 3918 3919 } else if (dest->is_double_xmm()) { 3920 if (src->is_double_stack()) { 3921 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3922 } else if (src->is_address()) { 3923 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3924 } else { 3925 ShouldNotReachHere(); 3926 } 3927 3928 } else if (src->is_double_fpu()) { 3929 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3930 if (dest->is_double_stack()) { 3931 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3932 } else if (dest->is_address()) { 3933 __ fistp_d(as_Address(dest->as_address_ptr())); 3934 } else { 3935 ShouldNotReachHere(); 3936 } 3937 3938 } else if (dest->is_double_fpu()) { 3939 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3940 if (src->is_double_stack()) { 3941 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3942 } else if (src->is_address()) { 3943 __ fild_d(as_Address(src->as_address_ptr())); 3944 } else { 3945 ShouldNotReachHere(); 3946 } 3947 } else { 3948 ShouldNotReachHere(); 3949 } 3950 } 3951 3952 #ifdef ASSERT 3953 // emit run-time assertion 3954 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 3955 assert(op->code() == lir_assert, "must be"); 3956 3957 if (op->in_opr1()->is_valid()) { 3958 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 3959 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 3960 } else { 3961 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 3962 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 3963 } 3964 3965 Label ok; 3966 if (op->condition() != lir_cond_always) { 3967 Assembler::Condition acond = Assembler::zero; 3968 switch (op->condition()) { 3969 case lir_cond_equal: acond = Assembler::equal; break; 3970 case lir_cond_notEqual: acond = Assembler::notEqual; break; 3971 case lir_cond_less: acond = Assembler::less; break; 3972 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 3973 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 3974 case lir_cond_greater: acond = Assembler::greater; break; 3975 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 3976 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 3977 default: ShouldNotReachHere(); 3978 } 3979 __ jcc(acond, ok); 3980 } 3981 if (op->halt()) { 3982 const char* str = __ code_string(op->msg()); 3983 __ stop(str); 3984 } else { 3985 breakpoint(); 3986 } 3987 __ bind(ok); 3988 } 3989 #endif 3990 3991 void LIR_Assembler::membar() { 3992 // QQQ sparc TSO uses this, 3993 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3994 } 3995 3996 void LIR_Assembler::membar_acquire() { 3997 // No x86 machines currently require load fences 3998 } 3999 4000 void LIR_Assembler::membar_release() { 4001 // No x86 machines currently require store fences 4002 } 4003 4004 void LIR_Assembler::membar_loadload() { 4005 // no-op 4006 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 4007 } 4008 4009 void LIR_Assembler::membar_storestore() { 4010 // no-op 4011 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 4012 } 4013 4014 void LIR_Assembler::membar_loadstore() { 4015 // no-op 4016 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 4017 } 4018 4019 void LIR_Assembler::membar_storeload() { 4020 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 4021 } 4022 4023 void LIR_Assembler::on_spin_wait() { 4024 __ pause (); 4025 } 4026 4027 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 4028 assert(result_reg->is_register(), "check"); 4029 #ifdef _LP64 4030 // __ get_thread(result_reg->as_register_lo()); 4031 __ mov(result_reg->as_register(), r15_thread); 4032 #else 4033 __ get_thread(result_reg->as_register()); 4034 #endif // _LP64 4035 } 4036 4037 4038 void LIR_Assembler::peephole(LIR_List*) { 4039 // do nothing for now 4040 } 4041 4042 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 4043 assert(data == dest, "xchg/xadd uses only 2 operands"); 4044 4045 if (data->type() == T_INT) { 4046 if (code == lir_xadd) { 4047 __ lock(); 4048 __ xaddl(as_Address(src->as_address_ptr()), data->as_register()); 4049 } else { 4050 __ xchgl(data->as_register(), as_Address(src->as_address_ptr())); 4051 } 4052 } else if (data->is_oop()) { 4053 assert (code == lir_xchg, "xadd for oops"); 4054 Register obj = data->as_register(); 4055 #ifdef _LP64 4056 if (UseCompressedOops) { 4057 __ encode_heap_oop(obj); 4058 __ xchgl(obj, as_Address(src->as_address_ptr())); 4059 __ decode_heap_oop(obj); 4060 } else { 4061 __ xchgptr(obj, as_Address(src->as_address_ptr())); 4062 } 4063 #else 4064 __ xchgl(obj, as_Address(src->as_address_ptr())); 4065 #endif 4066 } else if (data->type() == T_LONG) { 4067 #ifdef _LP64 4068 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); 4069 if (code == lir_xadd) { 4070 __ lock(); 4071 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo()); 4072 } else { 4073 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr())); 4074 } 4075 #else 4076 ShouldNotReachHere(); 4077 #endif 4078 } else { 4079 ShouldNotReachHere(); 4080 } 4081 } 4082 4083 #undef __