1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31 #include "runtime/signature.hpp"
32
33 // MacroAssembler extends Assembler by frequently used macros.
34 //
35 // Instructions for which a 'better' code sequence exists depending
36 // on arguments should also go in here.
37
38 class MacroAssembler: public Assembler {
39 friend class LIR_Assembler;
40 friend class Runtime1; // as_Address()
41
42 public:
43 // Support for VM calls
44 //
45 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
46 // may customize this version by overriding it for its purposes (e.g., to save/restore
47 // additional registers when doing a VM call).
48
49 virtual void call_VM_leaf_base(
50 address entry_point, // the entry point
51 int number_of_arguments // the number of arguments to pop after the call
52 );
53
54 protected:
55 // This is the base routine called by the different versions of call_VM. The interpreter
56 // may customize this version by overriding it for its purposes (e.g., to save/restore
57 // additional registers when doing a VM call).
58 //
59 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
60 // returns the register which contains the thread upon return. If a thread register has been
61 // specified, the return value will correspond to that register. If no last_java_sp is specified
62 // (noreg) than rsp will be used instead.
63 virtual void call_VM_base( // returns the register containing the thread upon return
64 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
65 Register java_thread, // the thread if computed before ; use noreg otherwise
66 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
67 address entry_point, // the entry point
68 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
69 bool check_exceptions // whether to check for pending exceptions after return
70 );
71
72 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
73
74 // helpers for FPU flag access
75 // tmp is a temporary register, if none is available use noreg
76 void save_rax (Register tmp);
77 void restore_rax(Register tmp);
78
79 public:
80 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
81
82 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
83 // The implementation is only non-empty for the InterpreterMacroAssembler,
84 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
85 virtual void check_and_handle_popframe(Register java_thread);
86 virtual void check_and_handle_earlyret(Register java_thread);
87
88 Address as_Address(AddressLiteral adr);
89 Address as_Address(ArrayAddress adr);
90
91 // Support for NULL-checks
92 //
93 // Generates code that causes a NULL OS exception if the content of reg is NULL.
94 // If the accessed location is M[reg + offset] and the offset is known, provide the
95 // offset. No explicit code generation is needed if the offset is within a certain
96 // range (0 <= offset <= page_size).
97
98 void null_check(Register reg, int offset = -1);
99 static bool needs_explicit_null_check(intptr_t offset);
100 static bool uses_implicit_null_check(void* address);
101
102 void test_klass_is_value(Register klass, Register temp_reg, Label& is_value);
103
104 void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable);
105 void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable);
106 void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened);
107
108 // Check klass/oops is flat value type array (oop->_klass->_layout_helper & vt_bit)
109 void test_flat_array_klass(Register klass, Register temp_reg, Label& is_flat_array);
110 void test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array);
111
112 // Required platform-specific helpers for Label::patch_instructions.
113 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
114 void pd_patch_instruction(address branch, address target, const char* file, int line) {
115 unsigned char op = branch[0];
116 assert(op == 0xE8 /* call */ ||
117 op == 0xE9 /* jmp */ ||
118 op == 0xEB /* short jmp */ ||
119 (op & 0xF0) == 0x70 /* short jcc */ ||
120 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
121 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
122 "Invalid opcode at patch point");
123
124 if (op == 0xEB || (op & 0xF0) == 0x70) {
125 // short offset operators (jmp and jcc)
126 char* disp = (char*) &branch[1];
127 int imm8 = target - (address) &disp[1];
128 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d", file, line);
129 *disp = imm8;
130 } else {
131 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
132 int imm32 = target - (address) &disp[1];
133 *disp = imm32;
134 }
135 }
136
137 // The following 4 methods return the offset of the appropriate move instruction
138
139 // Support for fast byte/short loading with zero extension (depending on particular CPU)
140 int load_unsigned_byte(Register dst, Address src);
141 int load_unsigned_short(Register dst, Address src);
142
143 // Support for fast byte/short loading with sign extension (depending on particular CPU)
144 int load_signed_byte(Register dst, Address src);
145 int load_signed_short(Register dst, Address src);
146
147 // Support for sign-extension (hi:lo = extend_sign(lo))
148 void extend_sign(Register hi, Register lo);
149
150 // Load and store values by size and signed-ness
151 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
152 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
153
154 // Support for inc/dec with optimal instruction selection depending on value
155
156 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
157 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
158
159 void decrementl(Address dst, int value = 1);
160 void decrementl(Register reg, int value = 1);
161
162 void decrementq(Register reg, int value = 1);
163 void decrementq(Address dst, int value = 1);
164
165 void incrementl(Address dst, int value = 1);
166 void incrementl(Register reg, int value = 1);
167
168 void incrementq(Register reg, int value = 1);
169 void incrementq(Address dst, int value = 1);
170
171 #ifdef COMPILER2
172 // special instructions for EVEX
173 void setvectmask(Register dst, Register src);
174 void restorevectmask();
175 #endif
176
177 // Support optimal SSE move instructions.
178 void movflt(XMMRegister dst, XMMRegister src) {
179 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
180 else { movss (dst, src); return; }
181 }
182 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
183 void movflt(XMMRegister dst, AddressLiteral src);
184 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
185
186 void movdbl(XMMRegister dst, XMMRegister src) {
187 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
188 else { movsd (dst, src); return; }
189 }
190
191 void movdbl(XMMRegister dst, AddressLiteral src);
192
193 void movdbl(XMMRegister dst, Address src) {
194 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
195 else { movlpd(dst, src); return; }
196 }
197 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
198
199 void incrementl(AddressLiteral dst);
200 void incrementl(ArrayAddress dst);
201
202 void incrementq(AddressLiteral dst);
203
204 // Alignment
205 void align(int modulus);
206 void align(int modulus, int target);
207
208 // A 5 byte nop that is safe for patching (see patch_verified_entry)
209 void fat_nop();
210
211 // Stack frame creation/removal
212 void enter();
213 void leave();
214
215 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
216 // The pointer will be loaded into the thread register.
217 void get_thread(Register thread);
218
219
220 // Support for VM calls
221 //
222 // It is imperative that all calls into the VM are handled via the call_VM macros.
223 // They make sure that the stack linkage is setup correctly. call_VM's correspond
224 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
225
226
227 void call_VM(Register oop_result,
228 address entry_point,
229 bool check_exceptions = true);
230 void call_VM(Register oop_result,
231 address entry_point,
232 Register arg_1,
233 bool check_exceptions = true);
234 void call_VM(Register oop_result,
235 address entry_point,
236 Register arg_1, Register arg_2,
237 bool check_exceptions = true);
238 void call_VM(Register oop_result,
239 address entry_point,
240 Register arg_1, Register arg_2, Register arg_3,
241 bool check_exceptions = true);
242
243 // Overloadings with last_Java_sp
244 void call_VM(Register oop_result,
245 Register last_java_sp,
246 address entry_point,
247 int number_of_arguments = 0,
248 bool check_exceptions = true);
249 void call_VM(Register oop_result,
250 Register last_java_sp,
251 address entry_point,
252 Register arg_1, bool
253 check_exceptions = true);
254 void call_VM(Register oop_result,
255 Register last_java_sp,
256 address entry_point,
257 Register arg_1, Register arg_2,
258 bool check_exceptions = true);
259 void call_VM(Register oop_result,
260 Register last_java_sp,
261 address entry_point,
262 Register arg_1, Register arg_2, Register arg_3,
263 bool check_exceptions = true);
264
265 void get_vm_result (Register oop_result, Register thread);
266 void get_vm_result_2(Register metadata_result, Register thread);
267
268 // These always tightly bind to MacroAssembler::call_VM_base
269 // bypassing the virtual implementation
270 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
271 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
272 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
273 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
274 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
275
276 void call_VM_leaf0(address entry_point);
277 void call_VM_leaf(address entry_point,
278 int number_of_arguments = 0);
279 void call_VM_leaf(address entry_point,
280 Register arg_1);
281 void call_VM_leaf(address entry_point,
282 Register arg_1, Register arg_2);
283 void call_VM_leaf(address entry_point,
284 Register arg_1, Register arg_2, Register arg_3);
285
286 // These always tightly bind to MacroAssembler::call_VM_leaf_base
287 // bypassing the virtual implementation
288 void super_call_VM_leaf(address entry_point);
289 void super_call_VM_leaf(address entry_point, Register arg_1);
290 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
291 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
292 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
293
294 // last Java Frame (fills frame anchor)
295 void set_last_Java_frame(Register thread,
296 Register last_java_sp,
297 Register last_java_fp,
298 address last_java_pc);
299
300 // thread in the default location (r15_thread on 64bit)
301 void set_last_Java_frame(Register last_java_sp,
302 Register last_java_fp,
303 address last_java_pc);
304
305 void reset_last_Java_frame(Register thread, bool clear_fp);
306
307 // thread in the default location (r15_thread on 64bit)
308 void reset_last_Java_frame(bool clear_fp);
309
310 // jobjects
311 void clear_jweak_tag(Register possibly_jweak);
312 void resolve_jobject(Register value, Register thread, Register tmp);
313
314 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
315 void c2bool(Register x);
316
317 // C++ bool manipulation
318
319 void movbool(Register dst, Address src);
320 void movbool(Address dst, bool boolconst);
321 void movbool(Address dst, Register src);
322 void testbool(Register dst);
323
324 void resolve_oop_handle(Register result, Register tmp = rscratch2);
325 void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
326
327 // oop manipulations
328 void load_klass(Register dst, Register src);
329 void store_klass(Register dst, Register src);
330
331 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
332 Register tmp1, Register thread_tmp);
333 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
334 Register tmp1, Register tmp2);
335
336 // Resolves obj access. Result is placed in the same register.
337 // All other registers are preserved.
338 void resolve(DecoratorSet decorators, Register obj);
339
340 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
341 Register thread_tmp = noreg, DecoratorSet decorators = 0);
342 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
343 Register thread_tmp = noreg, DecoratorSet decorators = 0);
344 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
345 Register tmp2 = noreg, DecoratorSet decorators = 0);
346
347 // Used for storing NULL. All other oop constants should be
348 // stored using routines that take a jobject.
349 void store_heap_oop_null(Address dst);
350
351 void load_prototype_header(Register dst, Register src);
352
353 #ifdef _LP64
354 void store_klass_gap(Register dst, Register src);
355
356 // This dummy is to prevent a call to store_heap_oop from
357 // converting a zero (like NULL) into a Register by giving
358 // the compiler two choices it can't resolve
359
360 void store_heap_oop(Address dst, void* dummy);
361
362 void encode_heap_oop(Register r);
363 void decode_heap_oop(Register r);
364 void encode_heap_oop_not_null(Register r);
365 void decode_heap_oop_not_null(Register r);
366 void encode_heap_oop_not_null(Register dst, Register src);
367 void decode_heap_oop_not_null(Register dst, Register src);
368
369 void set_narrow_oop(Register dst, jobject obj);
370 void set_narrow_oop(Address dst, jobject obj);
371 void cmp_narrow_oop(Register dst, jobject obj);
372 void cmp_narrow_oop(Address dst, jobject obj);
373
374 void encode_klass_not_null(Register r);
375 void decode_klass_not_null(Register r);
376 void encode_klass_not_null(Register dst, Register src);
377 void decode_klass_not_null(Register dst, Register src);
378 void set_narrow_klass(Register dst, Klass* k);
379 void set_narrow_klass(Address dst, Klass* k);
380 void cmp_narrow_klass(Register dst, Klass* k);
381 void cmp_narrow_klass(Address dst, Klass* k);
382
383 // Returns the byte size of the instructions generated by decode_klass_not_null()
384 // when compressed klass pointers are being used.
385 static int instr_size_for_decode_klass_not_null();
386
387 // if heap base register is used - reinit it with the correct value
388 void reinit_heapbase();
389
390 DEBUG_ONLY(void verify_heapbase(const char* msg);)
391
392 #endif // _LP64
393
394 // Int division/remainder for Java
395 // (as idivl, but checks for special case as described in JVM spec.)
396 // returns idivl instruction offset for implicit exception handling
397 int corrected_idivl(Register reg);
398
399 // Long division/remainder for Java
400 // (as idivq, but checks for special case as described in JVM spec.)
401 // returns idivq instruction offset for implicit exception handling
402 int corrected_idivq(Register reg);
403
404 void int3();
405
406 // Long operation macros for a 32bit cpu
407 // Long negation for Java
408 void lneg(Register hi, Register lo);
409
410 // Long multiplication for Java
411 // (destroys contents of eax, ebx, ecx and edx)
412 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
413
414 // Long shifts for Java
415 // (semantics as described in JVM spec.)
416 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
417 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
418
419 // Long compare for Java
420 // (semantics as described in JVM spec.)
421 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
422
423
424 // misc
425
426 // Sign extension
427 void sign_extend_short(Register reg);
428 void sign_extend_byte(Register reg);
429
430 // Division by power of 2, rounding towards 0
431 void division_with_shift(Register reg, int shift_value);
432
433 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
434 //
435 // CF (corresponds to C0) if x < y
436 // PF (corresponds to C2) if unordered
437 // ZF (corresponds to C3) if x = y
438 //
439 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
440 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
441 void fcmp(Register tmp);
442 // Variant of the above which allows y to be further down the stack
443 // and which only pops x and y if specified. If pop_right is
444 // specified then pop_left must also be specified.
445 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
446
447 // Floating-point comparison for Java
448 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
449 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
450 // (semantics as described in JVM spec.)
451 void fcmp2int(Register dst, bool unordered_is_less);
452 // Variant of the above which allows y to be further down the stack
453 // and which only pops x and y if specified. If pop_right is
454 // specified then pop_left must also be specified.
455 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
456
457 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
458 // tmp is a temporary register, if none is available use noreg
459 void fremr(Register tmp);
460
461 // dst = c = a * b + c
462 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
463 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
464
465 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
466 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
467 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
468 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
469
470
471 // same as fcmp2int, but using SSE2
472 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
473 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
474
475 // branch to L if FPU flag C2 is set/not set
476 // tmp is a temporary register, if none is available use noreg
477 void jC2 (Register tmp, Label& L);
478 void jnC2(Register tmp, Label& L);
479
480 // Pop ST (ffree & fincstp combined)
481 void fpop();
482
483 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
484 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
485 void load_float(Address src);
486
487 // Store float value to 'address'. If UseSSE >= 1, the value is stored
488 // from register xmm0. Otherwise, the value is stored from the FPU stack.
489 void store_float(Address dst);
490
491 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
492 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
493 void load_double(Address src);
494
495 // Store double value to 'address'. If UseSSE >= 2, the value is stored
496 // from register xmm0. Otherwise, the value is stored from the FPU stack.
497 void store_double(Address dst);
498
499 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
500 void push_fTOS();
501
502 // pops double TOS element from CPU stack and pushes on FPU stack
503 void pop_fTOS();
504
505 void empty_FPU_stack();
506
507 void push_IU_state();
508 void pop_IU_state();
509
510 void push_FPU_state();
511 void pop_FPU_state();
512
513 void push_CPU_state();
514 void pop_CPU_state();
515
516 // Round up to a power of two
517 void round_to(Register reg, int modulus);
518
519 // Callee saved registers handling
520 void push_callee_saved_registers();
521 void pop_callee_saved_registers();
522
523 // allocation
524 void eden_allocate(
525 Register thread, // Current thread
526 Register obj, // result: pointer to object after successful allocation
527 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
528 int con_size_in_bytes, // object size in bytes if known at compile time
529 Register t1, // temp register
530 Label& slow_case // continuation point if fast allocation fails
531 );
532 void tlab_allocate(
533 Register thread, // Current thread
534 Register obj, // result: pointer to object after successful allocation
535 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
536 int con_size_in_bytes, // object size in bytes if known at compile time
537 Register t1, // temp register
538 Register t2, // temp register
539 Label& slow_case // continuation point if fast allocation fails
540 );
541 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
542
543 // interface method calling
544 void lookup_interface_method(Register recv_klass,
545 Register intf_klass,
546 RegisterOrConstant itable_index,
547 Register method_result,
548 Register scan_temp,
549 Label& no_such_interface,
550 bool return_method = true);
551
552 // virtual method calling
553 void lookup_virtual_method(Register recv_klass,
554 RegisterOrConstant vtable_index,
555 Register method_result);
556
557 // Test sub_klass against super_klass, with fast and slow paths.
558
559 // The fast path produces a tri-state answer: yes / no / maybe-slow.
560 // One of the three labels can be NULL, meaning take the fall-through.
561 // If super_check_offset is -1, the value is loaded up from super_klass.
562 // No registers are killed, except temp_reg.
563 void check_klass_subtype_fast_path(Register sub_klass,
564 Register super_klass,
565 Register temp_reg,
566 Label* L_success,
567 Label* L_failure,
568 Label* L_slow_path,
569 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
570
571 // The rest of the type check; must be wired to a corresponding fast path.
572 // It does not repeat the fast path logic, so don't use it standalone.
573 // The temp_reg and temp2_reg can be noreg, if no temps are available.
574 // Updates the sub's secondary super cache as necessary.
575 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
576 void check_klass_subtype_slow_path(Register sub_klass,
577 Register super_klass,
578 Register temp_reg,
579 Register temp2_reg,
580 Label* L_success,
581 Label* L_failure,
582 bool set_cond_codes = false);
583
584 // Simplified, combined version, good for typical uses.
585 // Falls through on failure.
586 void check_klass_subtype(Register sub_klass,
587 Register super_klass,
588 Register temp_reg,
589 Label& L_success);
590
591 // method handles (JSR 292)
592 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
593
594 //----
595 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
596
597 // Debugging
598
599 // only if +VerifyOops
600 // TODO: Make these macros with file and line like sparc version!
601 void verify_oop(Register reg, const char* s = "broken oop");
602 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
603
604 // TODO: verify method and klass metadata (compare against vptr?)
605 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
606 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
607
608 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
609 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
610
611 // only if +VerifyFPU
612 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
613
614 // Verify or restore cpu control state after JNI call
615 void restore_cpu_control_state_after_jni();
616
617 // prints msg, dumps registers and stops execution
618 void stop(const char* msg);
619
620 // prints msg and continues
621 void warn(const char* msg);
622
623 // dumps registers and other state
624 void print_state();
625
626 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
627 static void debug64(char* msg, int64_t pc, int64_t regs[]);
628 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
629 static void print_state64(int64_t pc, int64_t regs[]);
630
631 void os_breakpoint();
632
633 void untested() { stop("untested"); }
634
635 void unimplemented(const char* what = "");
636
637 void should_not_reach_here() { stop("should not reach here"); }
638
639 void print_CPU_state();
640
641 // Stack overflow checking
642 void bang_stack_with_offset(int offset) {
643 // stack grows down, caller passes positive offset
644 assert(offset > 0, "must bang with negative offset");
645 movl(Address(rsp, (-offset)), rax);
646 }
647
648 // Writes to stack successive pages until offset reached to check for
649 // stack overflow + shadow pages. Also, clobbers tmp
650 void bang_stack_size(Register size, Register tmp);
651
652 // Check for reserved stack access in method being exited (for JIT)
653 void reserved_stack_check();
654
655 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
656 Register tmp,
657 int offset);
658
659 // If thread_reg is != noreg the code assumes the register passed contains
660 // the thread (required on 64 bit).
661 void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
662
663 void verify_tlab();
664
665 // Biased locking support
666 // lock_reg and obj_reg must be loaded up with the appropriate values.
667 // swap_reg must be rax, and is killed.
668 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
669 // be killed; if not supplied, push/pop will be used internally to
670 // allocate a temporary (inefficient, avoid if possible).
671 // Optional slow case is for implementations (interpreter and C1) which branch to
672 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
673 // Returns offset of first potentially-faulting instruction for null
674 // check info (currently consumed only by C1). If
675 // swap_reg_contains_mark is true then returns -1 as it is assumed
676 // the calling code has already passed any potential faults.
677 int biased_locking_enter(Register lock_reg, Register obj_reg,
678 Register swap_reg, Register tmp_reg,
679 bool swap_reg_contains_mark,
680 Label& done, Label* slow_case = NULL,
681 BiasedLockingCounters* counters = NULL);
682 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
683 #ifdef COMPILER2
684 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
685 // See full desription in macroAssembler_x86.cpp.
686 void fast_lock(Register obj, Register box, Register tmp,
687 Register scr, Register cx1, Register cx2,
688 BiasedLockingCounters* counters,
689 RTMLockingCounters* rtm_counters,
690 RTMLockingCounters* stack_rtm_counters,
691 Metadata* method_data,
692 bool use_rtm, bool profile_rtm);
693 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
694 #if INCLUDE_RTM_OPT
695 void rtm_counters_update(Register abort_status, Register rtm_counters);
696 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
697 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
698 RTMLockingCounters* rtm_counters,
699 Metadata* method_data);
700 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
701 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
702 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
703 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
704 void rtm_stack_locking(Register obj, Register tmp, Register scr,
705 Register retry_on_abort_count,
706 RTMLockingCounters* stack_rtm_counters,
707 Metadata* method_data, bool profile_rtm,
708 Label& DONE_LABEL, Label& IsInflated);
709 void rtm_inflated_locking(Register obj, Register box, Register tmp,
710 Register scr, Register retry_on_busy_count,
711 Register retry_on_abort_count,
712 RTMLockingCounters* rtm_counters,
713 Metadata* method_data, bool profile_rtm,
714 Label& DONE_LABEL);
715 #endif
716 #endif
717
718 Condition negate_condition(Condition cond);
719
720 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
721 // operands. In general the names are modified to avoid hiding the instruction in Assembler
722 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
723 // here in MacroAssembler. The major exception to this rule is call
724
725 // Arithmetics
726
727
728 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
729 void addptr(Address dst, Register src);
730
731 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
732 void addptr(Register dst, int32_t src);
733 void addptr(Register dst, Register src);
734 void addptr(Register dst, RegisterOrConstant src) {
735 if (src.is_constant()) addptr(dst, (int) src.as_constant());
736 else addptr(dst, src.as_register());
737 }
738
739 void andptr(Register dst, int32_t src);
740 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
741
742 void cmp8(AddressLiteral src1, int imm);
743
744 // renamed to drag out the casting of address to int32_t/intptr_t
745 void cmp32(Register src1, int32_t imm);
746
747 void cmp32(AddressLiteral src1, int32_t imm);
748 // compare reg - mem, or reg - &mem
749 void cmp32(Register src1, AddressLiteral src2);
750
751 void cmp32(Register src1, Address src2);
752
753 #ifndef _LP64
754 void cmpklass(Address dst, Metadata* obj);
755 void cmpklass(Register dst, Metadata* obj);
756 void cmpoop(Address dst, jobject obj);
757 void cmpoop_raw(Address dst, jobject obj);
758 #endif // _LP64
759
760 void cmpoop(Register src1, Register src2);
761 void cmpoop(Register src1, Address src2);
762 void cmpoop(Register dst, jobject obj);
763 void cmpoop_raw(Register dst, jobject obj);
764
765 // NOTE src2 must be the lval. This is NOT an mem-mem compare
766 void cmpptr(Address src1, AddressLiteral src2);
767
768 void cmpptr(Register src1, AddressLiteral src2);
769
770 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
771 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
772 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
773
774 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
775 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
776
777 // cmp64 to avoild hiding cmpq
778 void cmp64(Register src1, AddressLiteral src);
779
780 void cmpxchgptr(Register reg, Address adr);
781
782 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
783
784
785 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
786 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
787
788
789 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
790
791 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
792
793 void shlptr(Register dst, int32_t shift);
794 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
795
796 void shrptr(Register dst, int32_t shift);
797 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
798
799 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
800 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
801
802 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
803
804 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
805 void subptr(Register dst, int32_t src);
806 // Force generation of a 4 byte immediate value even if it fits into 8bit
807 void subptr_imm32(Register dst, int32_t src);
808 void subptr(Register dst, Register src);
809 void subptr(Register dst, RegisterOrConstant src) {
810 if (src.is_constant()) subptr(dst, (int) src.as_constant());
811 else subptr(dst, src.as_register());
812 }
813
814 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
815 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
816
817 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
818 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
819
820 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
821
822
823
824 // Helper functions for statistics gathering.
825 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
826 void cond_inc32(Condition cond, AddressLiteral counter_addr);
827 // Unconditional atomic increment.
828 void atomic_incl(Address counter_addr);
829 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
830 #ifdef _LP64
831 void atomic_incq(Address counter_addr);
832 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
833 #endif
834 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
835 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
836
837 void lea(Register dst, AddressLiteral adr);
838 void lea(Address dst, AddressLiteral adr);
839 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
840
841 void leal32(Register dst, Address src) { leal(dst, src); }
842
843 // Import other testl() methods from the parent class or else
844 // they will be hidden by the following overriding declaration.
845 using Assembler::testl;
846 void testl(Register dst, AddressLiteral src);
847
848 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
849 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
850 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
851 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
852
853 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
854 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
855 void testptr(Register src1, Register src2);
856
857 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
858 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
859
860 // Calls
861
862 void call(Label& L, relocInfo::relocType rtype);
863 void call(Register entry);
864
865 // NOTE: this call transfers to the effective address of entry NOT
866 // the address contained by entry. This is because this is more natural
867 // for jumps/calls.
868 void call(AddressLiteral entry);
869
870 // Emit the CompiledIC call idiom
871 void ic_call(address entry, jint method_index = 0);
872
873 // Jumps
874
875 // NOTE: these jumps tranfer to the effective address of dst NOT
876 // the address contained by dst. This is because this is more natural
877 // for jumps/calls.
878 void jump(AddressLiteral dst);
879 void jump_cc(Condition cc, AddressLiteral dst);
880
881 // 32bit can do a case table jump in one instruction but we no longer allow the base
882 // to be installed in the Address class. This jump will tranfers to the address
883 // contained in the location described by entry (not the address of entry)
884 void jump(ArrayAddress entry);
885
886 // Floating
887
888 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
889 void andpd(XMMRegister dst, AddressLiteral src);
890 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
891
892 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
893 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
894 void andps(XMMRegister dst, AddressLiteral src);
895
896 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
897 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
898 void comiss(XMMRegister dst, AddressLiteral src);
899
900 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
901 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
902 void comisd(XMMRegister dst, AddressLiteral src);
903
904 void fadd_s(Address src) { Assembler::fadd_s(src); }
905 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
906
907 void fldcw(Address src) { Assembler::fldcw(src); }
908 void fldcw(AddressLiteral src);
909
910 void fld_s(int index) { Assembler::fld_s(index); }
911 void fld_s(Address src) { Assembler::fld_s(src); }
912 void fld_s(AddressLiteral src);
913
914 void fld_d(Address src) { Assembler::fld_d(src); }
915 void fld_d(AddressLiteral src);
916
917 void fld_x(Address src) { Assembler::fld_x(src); }
918 void fld_x(AddressLiteral src);
919
920 void fmul_s(Address src) { Assembler::fmul_s(src); }
921 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
922
923 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
924 void ldmxcsr(AddressLiteral src);
925
926 #ifdef _LP64
927 private:
928 void sha256_AVX2_one_round_compute(
929 Register reg_old_h,
930 Register reg_a,
931 Register reg_b,
932 Register reg_c,
933 Register reg_d,
934 Register reg_e,
935 Register reg_f,
936 Register reg_g,
937 Register reg_h,
938 int iter);
939 void sha256_AVX2_four_rounds_compute_first(int start);
940 void sha256_AVX2_four_rounds_compute_last(int start);
941 void sha256_AVX2_one_round_and_sched(
942 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
943 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
944 XMMRegister xmm_2, /* ymm6 */
945 XMMRegister xmm_3, /* ymm7 */
946 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
947 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
948 Register reg_c, /* edi */
949 Register reg_d, /* esi */
950 Register reg_e, /* r8d */
951 Register reg_f, /* r9d */
952 Register reg_g, /* r10d */
953 Register reg_h, /* r11d */
954 int iter);
955
956 void addm(int disp, Register r1, Register r2);
957 void gfmul(XMMRegister tmp0, XMMRegister t);
958 void schoolbookAAD(int i, Register subkeyH, XMMRegister data, XMMRegister tmp0,
959 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3);
960 void generateHtbl_one_block(Register htbl);
961 void generateHtbl_eight_blocks(Register htbl);
962 public:
963 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
964 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
965 Register buf, Register state, Register ofs, Register limit, Register rsp,
966 bool multi_block, XMMRegister shuf_mask);
967 void avx_ghash(Register state, Register htbl, Register data, Register blocks);
968 #endif
969
970 #ifdef _LP64
971 private:
972 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
973 Register e, Register f, Register g, Register h, int iteration);
974
975 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
976 Register a, Register b, Register c, Register d, Register e, Register f,
977 Register g, Register h, int iteration);
978
979 void addmq(int disp, Register r1, Register r2);
980 public:
981 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
982 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
983 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
984 XMMRegister shuf_mask);
985 #endif
986
987 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
988 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
989 Register buf, Register state, Register ofs, Register limit, Register rsp,
990 bool multi_block);
991
992 #ifdef _LP64
993 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
994 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
995 Register buf, Register state, Register ofs, Register limit, Register rsp,
996 bool multi_block, XMMRegister shuf_mask);
997 #else
998 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
999 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1000 Register buf, Register state, Register ofs, Register limit, Register rsp,
1001 bool multi_block);
1002 #endif
1003
1004 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1005 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1006 Register rax, Register rcx, Register rdx, Register tmp);
1007
1008 #ifdef _LP64
1009 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1010 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1011 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1012
1013 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1014 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1015 Register rax, Register rcx, Register rdx, Register r11);
1016
1017 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1018 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1019 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1020
1021 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1022 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1023 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1024 Register tmp3, Register tmp4);
1025
1026 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1027 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1028 Register rax, Register rcx, Register rdx, Register tmp1,
1029 Register tmp2, Register tmp3, Register tmp4);
1030 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1031 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1032 Register rax, Register rcx, Register rdx, Register tmp1,
1033 Register tmp2, Register tmp3, Register tmp4);
1034 #else
1035 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1036 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1037 Register rax, Register rcx, Register rdx, Register tmp1);
1038
1039 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1040 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1041 Register rax, Register rcx, Register rdx, Register tmp);
1042
1043 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1044 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1045 Register rdx, Register tmp);
1046
1047 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1048 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1049 Register rax, Register rbx, Register rdx);
1050
1051 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1052 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1053 Register rax, Register rcx, Register rdx, Register tmp);
1054
1055 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1056 Register edx, Register ebx, Register esi, Register edi,
1057 Register ebp, Register esp);
1058
1059 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1060 Register esi, Register edi, Register ebp, Register esp);
1061
1062 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1063 Register edx, Register ebx, Register esi, Register edi,
1064 Register ebp, Register esp);
1065
1066 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1067 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1068 Register rax, Register rcx, Register rdx, Register tmp);
1069 #endif
1070
1071 void increase_precision();
1072 void restore_precision();
1073
1074 private:
1075
1076 // these are private because users should be doing movflt/movdbl
1077
1078 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1079 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1080 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1081 void movss(XMMRegister dst, AddressLiteral src);
1082
1083 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1084 void movlpd(XMMRegister dst, AddressLiteral src);
1085
1086 public:
1087
1088 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1089 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1090 void addsd(XMMRegister dst, AddressLiteral src);
1091
1092 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1093 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1094 void addss(XMMRegister dst, AddressLiteral src);
1095
1096 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1097 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1098 void addpd(XMMRegister dst, AddressLiteral src);
1099
1100 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1101 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1102 void divsd(XMMRegister dst, AddressLiteral src);
1103
1104 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1105 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1106 void divss(XMMRegister dst, AddressLiteral src);
1107
1108 // Move Unaligned Double Quadword
1109 void movdqu(Address dst, XMMRegister src);
1110 void movdqu(XMMRegister dst, Address src);
1111 void movdqu(XMMRegister dst, XMMRegister src);
1112 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1113 // AVX Unaligned forms
1114 void vmovdqu(Address dst, XMMRegister src);
1115 void vmovdqu(XMMRegister dst, Address src);
1116 void vmovdqu(XMMRegister dst, XMMRegister src);
1117 void vmovdqu(XMMRegister dst, AddressLiteral src);
1118 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1119 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1120 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1121 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1122
1123 // Move Aligned Double Quadword
1124 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1125 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1126 void movdqa(XMMRegister dst, AddressLiteral src);
1127
1128 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1129 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1130 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1131 void movsd(XMMRegister dst, AddressLiteral src);
1132
1133 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1134 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1135 void mulpd(XMMRegister dst, AddressLiteral src);
1136
1137 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1138 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1139 void mulsd(XMMRegister dst, AddressLiteral src);
1140
1141 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1142 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1143 void mulss(XMMRegister dst, AddressLiteral src);
1144
1145 // Carry-Less Multiplication Quadword
1146 void pclmulldq(XMMRegister dst, XMMRegister src) {
1147 // 0x00 - multiply lower 64 bits [0:63]
1148 Assembler::pclmulqdq(dst, src, 0x00);
1149 }
1150 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1151 // 0x11 - multiply upper 64 bits [64:127]
1152 Assembler::pclmulqdq(dst, src, 0x11);
1153 }
1154
1155 void pcmpeqb(XMMRegister dst, XMMRegister src);
1156 void pcmpeqw(XMMRegister dst, XMMRegister src);
1157
1158 void pcmpestri(XMMRegister dst, Address src, int imm8);
1159 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1160
1161 void pmovzxbw(XMMRegister dst, XMMRegister src);
1162 void pmovzxbw(XMMRegister dst, Address src);
1163
1164 void pmovmskb(Register dst, XMMRegister src);
1165
1166 void ptest(XMMRegister dst, XMMRegister src);
1167
1168 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1169 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1170 void sqrtsd(XMMRegister dst, AddressLiteral src);
1171
1172 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1173 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1174 void sqrtss(XMMRegister dst, AddressLiteral src);
1175
1176 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1177 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1178 void subsd(XMMRegister dst, AddressLiteral src);
1179
1180 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1181 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1182 void subss(XMMRegister dst, AddressLiteral src);
1183
1184 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1185 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1186 void ucomiss(XMMRegister dst, AddressLiteral src);
1187
1188 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1189 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1190 void ucomisd(XMMRegister dst, AddressLiteral src);
1191
1192 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1193 void xorpd(XMMRegister dst, XMMRegister src);
1194 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1195 void xorpd(XMMRegister dst, AddressLiteral src);
1196
1197 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1198 void xorps(XMMRegister dst, XMMRegister src);
1199 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1200 void xorps(XMMRegister dst, AddressLiteral src);
1201
1202 // Shuffle Bytes
1203 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1204 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1205 void pshufb(XMMRegister dst, AddressLiteral src);
1206 // AVX 3-operands instructions
1207
1208 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1209 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1210 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1211
1212 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1213 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1214 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1215
1216 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1217 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1218
1219 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1220 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1221
1222 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1223 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1224
1225 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1226 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1227 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1228
1229 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1230 void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1231
1232 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1233
1234 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1235
1236 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1237 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1238
1239 void vpmovmskb(Register dst, XMMRegister src);
1240
1241 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1242 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1243
1244 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1245 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1246
1247 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1248 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1249
1250 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1251 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1252
1253 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1254 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1255
1256 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1257 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1258
1259 void vptest(XMMRegister dst, XMMRegister src);
1260
1261 void punpcklbw(XMMRegister dst, XMMRegister src);
1262 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1263
1264 void pshufd(XMMRegister dst, Address src, int mode);
1265 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1266
1267 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1268 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1269
1270 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1271 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1272 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1273
1274 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1275 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1276 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1277
1278 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1279 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1280 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1281
1282 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1283 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1284 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1285
1286 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1287 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1288 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1289
1290 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1291 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1292 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1293
1294 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1295 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1296 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1297
1298 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1299 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1300 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1301
1302 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1303 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1304
1305 // AVX Vector instructions
1306
1307 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1308 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1309 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1310
1311 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1312 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1313 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1314
1315 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1316 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1317 Assembler::vpxor(dst, nds, src, vector_len);
1318 else
1319 Assembler::vxorpd(dst, nds, src, vector_len);
1320 }
1321 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1322 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1323 Assembler::vpxor(dst, nds, src, vector_len);
1324 else
1325 Assembler::vxorpd(dst, nds, src, vector_len);
1326 }
1327
1328 // Simple version for AVX2 256bit vectors
1329 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1330 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1331
1332 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1333 if (UseAVX > 2) {
1334 Assembler::vinserti32x4(dst, dst, src, imm8);
1335 } else if (UseAVX > 1) {
1336 // vinserti128 is available only in AVX2
1337 Assembler::vinserti128(dst, nds, src, imm8);
1338 } else {
1339 Assembler::vinsertf128(dst, nds, src, imm8);
1340 }
1341 }
1342
1343 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1344 if (UseAVX > 2) {
1345 Assembler::vinserti32x4(dst, dst, src, imm8);
1346 } else if (UseAVX > 1) {
1347 // vinserti128 is available only in AVX2
1348 Assembler::vinserti128(dst, nds, src, imm8);
1349 } else {
1350 Assembler::vinsertf128(dst, nds, src, imm8);
1351 }
1352 }
1353
1354 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1355 if (UseAVX > 2) {
1356 Assembler::vextracti32x4(dst, src, imm8);
1357 } else if (UseAVX > 1) {
1358 // vextracti128 is available only in AVX2
1359 Assembler::vextracti128(dst, src, imm8);
1360 } else {
1361 Assembler::vextractf128(dst, src, imm8);
1362 }
1363 }
1364
1365 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1366 if (UseAVX > 2) {
1367 Assembler::vextracti32x4(dst, src, imm8);
1368 } else if (UseAVX > 1) {
1369 // vextracti128 is available only in AVX2
1370 Assembler::vextracti128(dst, src, imm8);
1371 } else {
1372 Assembler::vextractf128(dst, src, imm8);
1373 }
1374 }
1375
1376 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1377 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1378 vinserti128(dst, dst, src, 1);
1379 }
1380 void vinserti128_high(XMMRegister dst, Address src) {
1381 vinserti128(dst, dst, src, 1);
1382 }
1383 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1384 vextracti128(dst, src, 1);
1385 }
1386 void vextracti128_high(Address dst, XMMRegister src) {
1387 vextracti128(dst, src, 1);
1388 }
1389
1390 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1391 if (UseAVX > 2) {
1392 Assembler::vinsertf32x4(dst, dst, src, 1);
1393 } else {
1394 Assembler::vinsertf128(dst, dst, src, 1);
1395 }
1396 }
1397
1398 void vinsertf128_high(XMMRegister dst, Address src) {
1399 if (UseAVX > 2) {
1400 Assembler::vinsertf32x4(dst, dst, src, 1);
1401 } else {
1402 Assembler::vinsertf128(dst, dst, src, 1);
1403 }
1404 }
1405
1406 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1407 if (UseAVX > 2) {
1408 Assembler::vextractf32x4(dst, src, 1);
1409 } else {
1410 Assembler::vextractf128(dst, src, 1);
1411 }
1412 }
1413
1414 void vextractf128_high(Address dst, XMMRegister src) {
1415 if (UseAVX > 2) {
1416 Assembler::vextractf32x4(dst, src, 1);
1417 } else {
1418 Assembler::vextractf128(dst, src, 1);
1419 }
1420 }
1421
1422 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1423 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1424 Assembler::vinserti64x4(dst, dst, src, 1);
1425 }
1426 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1427 Assembler::vinsertf64x4(dst, dst, src, 1);
1428 }
1429 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1430 Assembler::vextracti64x4(dst, src, 1);
1431 }
1432 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1433 Assembler::vextractf64x4(dst, src, 1);
1434 }
1435 void vextractf64x4_high(Address dst, XMMRegister src) {
1436 Assembler::vextractf64x4(dst, src, 1);
1437 }
1438 void vinsertf64x4_high(XMMRegister dst, Address src) {
1439 Assembler::vinsertf64x4(dst, dst, src, 1);
1440 }
1441
1442 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1443 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1444 vinserti128(dst, dst, src, 0);
1445 }
1446 void vinserti128_low(XMMRegister dst, Address src) {
1447 vinserti128(dst, dst, src, 0);
1448 }
1449 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1450 vextracti128(dst, src, 0);
1451 }
1452 void vextracti128_low(Address dst, XMMRegister src) {
1453 vextracti128(dst, src, 0);
1454 }
1455
1456 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1457 if (UseAVX > 2) {
1458 Assembler::vinsertf32x4(dst, dst, src, 0);
1459 } else {
1460 Assembler::vinsertf128(dst, dst, src, 0);
1461 }
1462 }
1463
1464 void vinsertf128_low(XMMRegister dst, Address src) {
1465 if (UseAVX > 2) {
1466 Assembler::vinsertf32x4(dst, dst, src, 0);
1467 } else {
1468 Assembler::vinsertf128(dst, dst, src, 0);
1469 }
1470 }
1471
1472 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1473 if (UseAVX > 2) {
1474 Assembler::vextractf32x4(dst, src, 0);
1475 } else {
1476 Assembler::vextractf128(dst, src, 0);
1477 }
1478 }
1479
1480 void vextractf128_low(Address dst, XMMRegister src) {
1481 if (UseAVX > 2) {
1482 Assembler::vextractf32x4(dst, src, 0);
1483 } else {
1484 Assembler::vextractf128(dst, src, 0);
1485 }
1486 }
1487
1488 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1489 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1490 Assembler::vinserti64x4(dst, dst, src, 0);
1491 }
1492 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1493 Assembler::vinsertf64x4(dst, dst, src, 0);
1494 }
1495 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1496 Assembler::vextracti64x4(dst, src, 0);
1497 }
1498 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1499 Assembler::vextractf64x4(dst, src, 0);
1500 }
1501 void vextractf64x4_low(Address dst, XMMRegister src) {
1502 Assembler::vextractf64x4(dst, src, 0);
1503 }
1504 void vinsertf64x4_low(XMMRegister dst, Address src) {
1505 Assembler::vinsertf64x4(dst, dst, src, 0);
1506 }
1507
1508 // Carry-Less Multiplication Quadword
1509 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1510 // 0x00 - multiply lower 64 bits [0:63]
1511 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1512 }
1513 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1514 // 0x11 - multiply upper 64 bits [64:127]
1515 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1516 }
1517 void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1518 // 0x10 - multiply nds[0:63] and src[64:127]
1519 Assembler::vpclmulqdq(dst, nds, src, 0x10);
1520 }
1521 void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1522 //0x01 - multiply nds[64:127] and src[0:63]
1523 Assembler::vpclmulqdq(dst, nds, src, 0x01);
1524 }
1525
1526 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1527 // 0x00 - multiply lower 64 bits [0:63]
1528 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1529 }
1530 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1531 // 0x11 - multiply upper 64 bits [64:127]
1532 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1533 }
1534
1535 // Data
1536
1537 void cmov32( Condition cc, Register dst, Address src);
1538 void cmov32( Condition cc, Register dst, Register src);
1539
1540 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1541
1542 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1543 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1544
1545 void movoop(Register dst, jobject obj);
1546 void movoop(Address dst, jobject obj);
1547
1548 void mov_metadata(Register dst, Metadata* obj);
1549 void mov_metadata(Address dst, Metadata* obj);
1550
1551 void movptr(ArrayAddress dst, Register src);
1552 // can this do an lea?
1553 void movptr(Register dst, ArrayAddress src);
1554
1555 void movptr(Register dst, Address src);
1556
1557 #ifdef _LP64
1558 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1559 #else
1560 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1561 #endif
1562
1563 void movptr(Register dst, intptr_t src);
1564 void movptr(Register dst, Register src);
1565 void movptr(Address dst, intptr_t src);
1566
1567 void movptr(Address dst, Register src);
1568
1569 void movptr(Register dst, RegisterOrConstant src) {
1570 if (src.is_constant()) movptr(dst, src.as_constant());
1571 else movptr(dst, src.as_register());
1572 }
1573
1574 #ifdef _LP64
1575 // Generally the next two are only used for moving NULL
1576 // Although there are situations in initializing the mark word where
1577 // they could be used. They are dangerous.
1578
1579 // They only exist on LP64 so that int32_t and intptr_t are not the same
1580 // and we have ambiguous declarations.
1581
1582 void movptr(Address dst, int32_t imm32);
1583 void movptr(Register dst, int32_t imm32);
1584 #endif // _LP64
1585
1586 // to avoid hiding movl
1587 void mov32(AddressLiteral dst, Register src);
1588 void mov32(Register dst, AddressLiteral src);
1589
1590 // to avoid hiding movb
1591 void movbyte(ArrayAddress dst, int src);
1592
1593 // Import other mov() methods from the parent class or else
1594 // they will be hidden by the following overriding declaration.
1595 using Assembler::movdl;
1596 using Assembler::movq;
1597 void movdl(XMMRegister dst, AddressLiteral src);
1598 void movq(XMMRegister dst, AddressLiteral src);
1599
1600 // Can push value or effective address
1601 void pushptr(AddressLiteral src);
1602
1603 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1604 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1605
1606 void pushoop(jobject obj);
1607 void pushklass(Metadata* obj);
1608
1609 // sign extend as need a l to ptr sized element
1610 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1611 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1612
1613 // C2 compiled method's prolog code.
1614 void verified_entry(Compile* C, int sp_inc = 0);
1615
1616 enum RegState {
1617 reg_readonly,
1618 reg_writable,
1619 reg_written
1620 };
1621
1622 // Unpack all value type arguments passed as oops
1623 void unpack_value_args(Compile* C, bool receiver_only);
1624 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[], int ret_off);
1625 bool unpack_value_helper(const GrowableArray<SigEntry>* sig, int& sig_index, VMReg from, VMRegPair* regs_to, int& to_index, RegState reg_state[], int ret_off);
1626 void restore_stack(Compile* C);
1627
1628 // clear memory of size 'cnt' qwords, starting at 'base';
1629 // if 'is_large' is set, do not try to produce short loop
1630 void clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, bool is_large, bool word_copy_only);
1631
1632 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1633 void xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp);
1634
1635 #ifdef COMPILER2
1636 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1637 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1638
1639 // IndexOf strings.
1640 // Small strings are loaded through stack if they cross page boundary.
1641 void string_indexof(Register str1, Register str2,
1642 Register cnt1, Register cnt2,
1643 int int_cnt2, Register result,
1644 XMMRegister vec, Register tmp,
1645 int ae);
1646
1647 // IndexOf for constant substrings with size >= 8 elements
1648 // which don't need to be loaded through stack.
1649 void string_indexofC8(Register str1, Register str2,
1650 Register cnt1, Register cnt2,
1651 int int_cnt2, Register result,
1652 XMMRegister vec, Register tmp,
1653 int ae);
1654
1655 // Smallest code: we don't need to load through stack,
1656 // check string tail.
1657
1658 // helper function for string_compare
1659 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1660 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1661 Address::ScaleFactor scale2, Register index, int ae);
1662 // Compare strings.
1663 void string_compare(Register str1, Register str2,
1664 Register cnt1, Register cnt2, Register result,
1665 XMMRegister vec1, int ae);
1666
1667 // Search for Non-ASCII character (Negative byte value) in a byte array,
1668 // return true if it has any and false otherwise.
1669 void has_negatives(Register ary1, Register len,
1670 Register result, Register tmp1,
1671 XMMRegister vec1, XMMRegister vec2);
1672
1673 // Compare char[] or byte[] arrays.
1674 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1675 Register limit, Register result, Register chr,
1676 XMMRegister vec1, XMMRegister vec2, bool is_char);
1677
1678 #endif
1679
1680 // Fill primitive arrays
1681 void generate_fill(BasicType t, bool aligned,
1682 Register to, Register value, Register count,
1683 Register rtmp, XMMRegister xtmp);
1684
1685 void encode_iso_array(Register src, Register dst, Register len,
1686 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1687 XMMRegister tmp4, Register tmp5, Register result);
1688
1689 #ifdef _LP64
1690 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1691 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1692 Register y, Register y_idx, Register z,
1693 Register carry, Register product,
1694 Register idx, Register kdx);
1695 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1696 Register yz_idx, Register idx,
1697 Register carry, Register product, int offset);
1698 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1699 Register carry, Register carry2,
1700 Register idx, Register jdx,
1701 Register yz_idx1, Register yz_idx2,
1702 Register tmp, Register tmp3, Register tmp4);
1703 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1704 Register yz_idx, Register idx, Register jdx,
1705 Register carry, Register product,
1706 Register carry2);
1707 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1708 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1709 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1710 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1711 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1712 Register tmp2);
1713 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1714 Register rdxReg, Register raxReg);
1715 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1716 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1717 Register tmp3, Register tmp4);
1718 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1719 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1720
1721 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1722 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1723 Register raxReg);
1724 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1725 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1726 Register raxReg);
1727 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1728 Register result, Register tmp1, Register tmp2,
1729 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1730 #endif
1731
1732 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1733 void update_byte_crc32(Register crc, Register val, Register table);
1734 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1735 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1736 // Note on a naming convention:
1737 // Prefix w = register only used on a Westmere+ architecture
1738 // Prefix n = register only used on a Nehalem architecture
1739 #ifdef _LP64
1740 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1741 Register tmp1, Register tmp2, Register tmp3);
1742 #else
1743 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1744 Register tmp1, Register tmp2, Register tmp3,
1745 XMMRegister xtmp1, XMMRegister xtmp2);
1746 #endif
1747 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1748 Register in_out,
1749 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1750 XMMRegister w_xtmp2,
1751 Register tmp1,
1752 Register n_tmp2, Register n_tmp3);
1753 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1754 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1755 Register tmp1, Register tmp2,
1756 Register n_tmp3);
1757 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1758 Register in_out1, Register in_out2, Register in_out3,
1759 Register tmp1, Register tmp2, Register tmp3,
1760 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1761 Register tmp4, Register tmp5,
1762 Register n_tmp6);
1763 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1764 Register tmp1, Register tmp2, Register tmp3,
1765 Register tmp4, Register tmp5, Register tmp6,
1766 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1767 bool is_pclmulqdq_supported);
1768 // Fold 128-bit data chunk
1769 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1770 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1771 // Fold 8-bit data
1772 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1773 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1774 void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1775
1776 // Compress char[] array to byte[].
1777 void char_array_compress(Register src, Register dst, Register len,
1778 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1779 XMMRegister tmp4, Register tmp5, Register result);
1780
1781 // Inflate byte[] array to char[].
1782 void byte_array_inflate(Register src, Register dst, Register len,
1783 XMMRegister tmp1, Register tmp2);
1784
1785 };
1786
1787 /**
1788 * class SkipIfEqual:
1789 *
1790 * Instantiating this class will result in assembly code being output that will
1791 * jump around any code emitted between the creation of the instance and it's
1792 * automatic destruction at the end of a scope block, depending on the value of
1793 * the flag passed to the constructor, which will be checked at run-time.
1794 */
1795 class SkipIfEqual {
1796 private:
1797 MacroAssembler* _masm;
1798 Label _label;
1799
1800 public:
1801 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1802 ~SkipIfEqual();
1803 };
1804
1805 #endif // CPU_X86_MACROASSEMBLER_X86_HPP