1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
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7 * published by the Free Software Foundation.
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
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15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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23 */
24
25 #ifndef SHARE_OPTO_MATCHER_HPP
26 #define SHARE_OPTO_MATCHER_HPP
27
28 #include "libadt/vectset.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "opto/node.hpp"
31 #include "opto/phaseX.hpp"
32 #include "opto/regmask.hpp"
33
34 class Compile;
35 class Node;
36 class MachNode;
37 class MachTypeNode;
38 class MachOper;
39
40 //---------------------------Matcher-------------------------------------------
41 class Matcher : public PhaseTransform {
42 friend class VMStructs;
43
44 public:
45
46 // State and MStack class used in xform() and find_shared() iterative methods.
47 enum Node_State { Pre_Visit, // node has to be pre-visited
48 Visit, // visit node
49 Post_Visit, // post-visit node
50 Alt_Post_Visit // alternative post-visit path
51 };
52
53 class MStack: public Node_Stack {
54 public:
55 MStack(int size) : Node_Stack(size) { }
56
57 void push(Node *n, Node_State ns) {
58 Node_Stack::push(n, (uint)ns);
59 }
60 void push(Node *n, Node_State ns, Node *parent, int indx) {
61 ++_inode_top;
62 if ((_inode_top + 1) >= _inode_max) grow();
63 _inode_top->node = parent;
64 _inode_top->indx = (uint)indx;
65 ++_inode_top;
66 _inode_top->node = n;
67 _inode_top->indx = (uint)ns;
68 }
69 Node *parent() {
70 pop();
71 return node();
72 }
73 Node_State state() const {
74 return (Node_State)index();
75 }
76 void set_state(Node_State ns) {
77 set_index((uint)ns);
78 }
79 };
80
81 private:
82 // Private arena of State objects
83 ResourceArea _states_arena;
84
85 VectorSet _visited; // Visit bits
86
87 // Used to control the Label pass
88 VectorSet _shared; // Shared Ideal Node
89 VectorSet _dontcare; // Nothing the matcher cares about
90
91 // Private methods which perform the actual matching and reduction
92 // Walks the label tree, generating machine nodes
93 MachNode *ReduceInst( State *s, int rule, Node *&mem);
94 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach);
95 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds);
96 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach );
97
98 // If this node already matched using "rule", return the MachNode for it.
99 MachNode* find_shared_node(Node* n, uint rule);
100
101 // Convert a dense opcode number to an expanded rule number
102 const int *_reduceOp;
103 const int *_leftOp;
104 const int *_rightOp;
105
106 // Map dense opcode number to info on when rule is swallowed constant.
107 const bool *_swallowed;
108
109 // Map dense rule number to determine if this is an instruction chain rule
110 const uint _begin_inst_chain_rule;
111 const uint _end_inst_chain_rule;
112
113 // We want to clone constants and possible CmpI-variants.
114 // If we do not clone CmpI, then we can have many instances of
115 // condition codes alive at once. This is OK on some chips and
116 // bad on others. Hence the machine-dependent table lookup.
117 const char *_must_clone;
118
119 // Find shared Nodes, or Nodes that otherwise are Matcher roots
120 void find_shared( Node *n );
121 bool find_shared_visit(MStack& mstack, Node* n, uint opcode, bool& mem_op, int& mem_addr_idx);
122 void find_shared_post_visit(Node* n, uint opcode);
123
124 #ifdef X86
125 bool is_bmi_pattern(Node *n, Node *m);
126 #endif
127
128 // Debug and profile information for nodes in old space:
129 GrowableArray<Node_Notes*>* _old_node_note_array;
130
131 // Node labeling iterator for instruction selection
132 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem );
133
134 Node *transform( Node *dummy );
135
136 Node_List _projection_list; // For Machine nodes killing many values
137
138 Node_Array _shared_nodes;
139
140 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots
141 debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal
142
143 // Accessors for the inherited field PhaseTransform::_nodes:
144 void grow_new_node_array(uint idx_limit) {
145 _nodes.map(idx_limit-1, NULL);
146 }
147 bool has_new_node(const Node* n) const {
148 return _nodes.at(n->_idx) != NULL;
149 }
150 Node* new_node(const Node* n) const {
151 assert(has_new_node(n), "set before get");
152 return _nodes.at(n->_idx);
153 }
154 void set_new_node(const Node* n, Node *nn) {
155 assert(!has_new_node(n), "set only once");
156 _nodes.map(n->_idx, nn);
157 }
158
159 #ifdef ASSERT
160 // Make sure only new nodes are reachable from this node
161 void verify_new_nodes_only(Node* root);
162
163 Node* _mem_node; // Ideal memory node consumed by mach node
164 #endif
165
166 // Mach node for ConP #NULL
167 MachNode* _mach_null;
168
169 void handle_precedence_edges(Node* n, MachNode *mach);
170
171 public:
172 int LabelRootDepth;
173 // Convert ideal machine register to a register mask for spill-loads
174 static const RegMask *idealreg2regmask[];
175 RegMask *idealreg2spillmask [_last_machine_leaf];
176 RegMask *idealreg2debugmask [_last_machine_leaf];
177 RegMask *idealreg2mhdebugmask[_last_machine_leaf];
178 void init_spill_mask( Node *ret );
179 // Convert machine register number to register mask
180 static uint mreg2regmask_max;
181 static RegMask mreg2regmask[];
182 static RegMask STACK_ONLY_mask;
183
184 MachNode* mach_null() const { return _mach_null; }
185
186 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; }
187 void set_shared( Node *n ) { _shared.set(n->_idx); }
188 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; }
189 void set_visited( Node *n ) { _visited.set(n->_idx); }
190 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; }
191 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); }
192
193 // Mode bit to tell DFA and expand rules whether we are running after
194 // (or during) register selection. Usually, the matcher runs before,
195 // but it will also get called to generate post-allocation spill code.
196 // In this situation, it is a deadly error to attempt to allocate more
197 // temporary registers.
198 bool _allocation_started;
199
200 // Machine register names
201 static const char *regName[];
202 // Machine register encodings
203 static const unsigned char _regEncode[];
204 // Machine Node names
205 const char **_ruleName;
206 // Rules that are cheaper to rematerialize than to spill
207 static const uint _begin_rematerialize;
208 static const uint _end_rematerialize;
209
210 // An array of chars, from 0 to _last_Mach_Reg.
211 // No Save = 'N' (for register windows)
212 // Save on Entry = 'E'
213 // Save on Call = 'C'
214 // Always Save = 'A' (same as SOE + SOC)
215 const char *_register_save_policy;
216 const char *_c_reg_save_policy;
217 // Convert a machine register to a machine register type, so-as to
218 // properly match spill code.
219 const int *_register_save_type;
220 // Maps from machine register to boolean; true if machine register can
221 // be holding a call argument in some signature.
222 static bool can_be_java_arg( int reg );
223 // Maps from machine register to boolean; true if machine register holds
224 // a spillable argument.
225 static bool is_spillable_arg( int reg );
226
227 // List of IfFalse or IfTrue Nodes that indicate a taken null test.
228 // List is valid in the post-matching space.
229 Node_List _null_check_tests;
230 void collect_null_checks( Node *proj, Node *orig_proj );
231 void validate_null_checks( );
232
233 Matcher();
234
235 // Get a projection node at position pos
236 Node* get_projection(uint pos) {
237 return _projection_list[pos];
238 }
239
240 // Push a projection node onto the projection list
241 void push_projection(Node* node) {
242 _projection_list.push(node);
243 }
244
245 Node* pop_projection() {
246 return _projection_list.pop();
247 }
248
249 // Number of nodes in the projection list
250 uint number_of_projections() const {
251 return _projection_list.size();
252 }
253
254 // Select instructions for entire method
255 void match();
256
257 // Helper for match
258 OptoReg::Name warp_incoming_stk_arg( VMReg reg );
259
260 // Transform, then walk. Does implicit DCE while walking.
261 // Name changed from "transform" to avoid it being virtual.
262 Node *xform( Node *old_space_node, int Nodes );
263
264 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce.
265 MachNode *match_tree( const Node *n );
266 MachNode *match_sfpt( SafePointNode *sfpt );
267 // Helper for match_sfpt
268 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call );
269
270 // Initialize first stack mask and related masks.
271 void init_first_stack_mask();
272
273 // If we should save-on-entry this register
274 bool is_save_on_entry( int reg );
275
276 // Fixup the save-on-entry registers
277 void Fixup_Save_On_Entry( );
278
279 // --- Frame handling ---
280
281 // Register number of the stack slot corresponding to the incoming SP.
282 // Per the Big Picture in the AD file, it is:
283 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2.
284 OptoReg::Name _old_SP;
285
286 // Register number of the stack slot corresponding to the highest incoming
287 // argument on the stack. Per the Big Picture in the AD file, it is:
288 // _old_SP + out_preserve_stack_slots + incoming argument size.
289 OptoReg::Name _in_arg_limit;
290
291 // Register number of the stack slot corresponding to the new SP.
292 // Per the Big Picture in the AD file, it is:
293 // _in_arg_limit + pad0
294 OptoReg::Name _new_SP;
295
296 // Register number of the stack slot corresponding to the highest outgoing
297 // argument on the stack. Per the Big Picture in the AD file, it is:
298 // _new_SP + max outgoing arguments of all calls
299 OptoReg::Name _out_arg_limit;
300
301 OptoRegPair *_parm_regs; // Array of machine registers per argument
302 RegMask *_calling_convention_mask; // Array of RegMasks per argument
303
304 // Does matcher have a match rule for this ideal node?
305 static const bool has_match_rule(int opcode);
306 static const bool _hasMatchRule[_last_opcode];
307
308 // Does matcher have a match rule for this ideal node and is the
309 // predicate (if there is one) true?
310 // NOTE: If this function is used more commonly in the future, ADLC
311 // should generate this one.
312 static const bool match_rule_supported(int opcode);
313
314 // identify extra cases that we might want to provide match rules for
315 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
316 static const bool match_rule_supported_vector(int opcode, int vlen);
317
318 // Some microarchitectures have mask registers used on vectors
319 static const bool has_predicated_vectors(void);
320
321 // Some uarchs have different sized float register resources
322 static const int float_pressure(int default_pressure_threshold);
323
324 // Used to determine if we have fast l2f conversion
325 // USII has it, USIII doesn't
326 static const bool convL2FSupported(void);
327
328 // Vector width in bytes
329 static const int vector_width_in_bytes(BasicType bt);
330
331 // Limits on vector size (number of elements).
332 static const int max_vector_size(const BasicType bt);
333 static const int min_vector_size(const BasicType bt);
334 static const bool vector_size_supported(const BasicType bt, int size) {
335 return (Matcher::max_vector_size(bt) >= size &&
336 Matcher::min_vector_size(bt) <= size);
337 }
338
339 // Vector ideal reg
340 static const uint vector_ideal_reg(int len);
341 static const uint vector_shift_count_ideal_reg(int len);
342
343 // CPU supports misaligned vectors store/load.
344 static const bool misaligned_vectors_ok();
345
346 // Should original key array reference be passed to AES stubs
347 static const bool pass_original_key_for_aes();
348
349 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.)
350 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI).
351 // Depends on the details of 64-bit constant generation on the CPU.
352 static const bool isSimpleConstant64(jlong con);
353
354 // These calls are all generated by the ADLC
355
356 // TRUE - grows up, FALSE - grows down (Intel)
357 virtual bool stack_direction() const;
358
359 // Java-Java calling convention
360 // (what you use when Java calls Java)
361
362 // Alignment of stack in bytes, standard Intel word alignment is 4.
363 // Sparc probably wants at least double-word (8).
364 static uint stack_alignment_in_bytes();
365 // Alignment of stack, measured in stack slots.
366 // The size of stack slots is defined by VMRegImpl::stack_slot_size.
367 static uint stack_alignment_in_slots() {
368 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size);
369 }
370
371 // Array mapping arguments to registers. Argument 0 is usually the 'this'
372 // pointer. Registers can include stack-slots and regular registers.
373 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing );
374
375 // Convert a sig into a calling convention register layout
376 // and find interesting things about it.
377 static OptoReg::Name find_receiver( bool is_outgoing );
378 // Return address register. On Intel it is a stack-slot. On PowerPC
379 // it is the Link register. On Sparc it is r31?
380 virtual OptoReg::Name return_addr() const;
381 RegMask _return_addr_mask;
382 // Return value register. On Intel it is EAX. On Sparc i0/o0.
383 static OptoRegPair return_value(uint ideal_reg, bool is_outgoing);
384 static OptoRegPair c_return_value(uint ideal_reg, bool is_outgoing);
385 RegMask _return_value_mask;
386 // Inline Cache Register
387 static OptoReg::Name inline_cache_reg();
388 static int inline_cache_reg_encode();
389
390 // Register for DIVI projection of divmodI
391 static RegMask divI_proj_mask();
392 // Register for MODI projection of divmodI
393 static RegMask modI_proj_mask();
394
395 // Register for DIVL projection of divmodL
396 static RegMask divL_proj_mask();
397 // Register for MODL projection of divmodL
398 static RegMask modL_proj_mask();
399
400 // Use hardware DIV instruction when it is faster than
401 // a code which use multiply for division by constant.
402 static bool use_asm_for_ldiv_by_con( jlong divisor );
403
404 static const RegMask method_handle_invoke_SP_save_mask();
405
406 // Java-Interpreter calling convention
407 // (what you use when calling between compiled-Java and Interpreted-Java
408
409 // Number of callee-save + always-save registers
410 // Ignores frame pointer and "special" registers
411 static int number_of_saved_registers();
412
413 // The Method-klass-holder may be passed in the inline_cache_reg
414 // and then expanded into the inline_cache_reg and a method_oop register
415
416 static OptoReg::Name interpreter_method_oop_reg();
417 static int interpreter_method_oop_reg_encode();
418
419 static OptoReg::Name compiler_method_oop_reg();
420 static const RegMask &compiler_method_oop_reg_mask();
421 static int compiler_method_oop_reg_encode();
422
423 // Interpreter's Frame Pointer Register
424 static OptoReg::Name interpreter_frame_pointer_reg();
425
426 // Java-Native calling convention
427 // (what you use when intercalling between Java and C++ code)
428
429 // Array mapping arguments to registers. Argument 0 is usually the 'this'
430 // pointer. Registers can include stack-slots and regular registers.
431 static void c_calling_convention( BasicType*, VMRegPair *, uint );
432 // Frame pointer. The frame pointer is kept at the base of the stack
433 // and so is probably the stack pointer for most machines. On Intel
434 // it is ESP. On the PowerPC it is R1. On Sparc it is SP.
435 OptoReg::Name c_frame_pointer() const;
436 static RegMask c_frame_ptr_mask;
437
438 // !!!!! Special stuff for building ScopeDescs
439 virtual int regnum_to_fpu_offset(int regnum);
440
441 // Is this branch offset small enough to be addressed by a short branch?
442 bool is_short_branch_offset(int rule, int br_size, int offset);
443
444 // Optional scaling for the parameter to the ClearArray/CopyArray node.
445 static const bool init_array_count_is_in_bytes;
446
447 // Some hardware needs 2 CMOV's for longs.
448 static const int long_cmove_cost();
449
450 // Some hardware have expensive CMOV for float and double.
451 static const int float_cmove_cost();
452
453 // Should the Matcher clone shifts on addressing modes, expecting them to
454 // be subsumed into complex addressing expressions or compute them into
455 // registers? True for Intel but false for most RISCs
456 bool clone_address_expressions(AddPNode* m, MStack& mstack, VectorSet& address_visited);
457 // Clone base + offset address expression
458 bool clone_base_plus_offset_address(AddPNode* m, MStack& mstack, VectorSet& address_visited);
459
460 static bool narrow_oop_use_complex_address();
461 static bool narrow_klass_use_complex_address();
462
463 static bool const_oop_prefer_decode();
464 static bool const_klass_prefer_decode();
465
466 // Generate implicit null check for narrow oops if it can fold
467 // into address expression (x64).
468 //
469 // [R12 + narrow_oop_reg<<3 + offset] // fold into address expression
470 // NullCheck narrow_oop_reg
471 //
472 // When narrow oops can't fold into address expression (Sparc) and
473 // base is not null use decode_not_null and normal implicit null check.
474 // Note, decode_not_null node can be used here since it is referenced
475 // only on non null path but it requires special handling, see
476 // collect_null_checks():
477 //
478 // decode_not_null narrow_oop_reg, oop_reg // 'shift' and 'add base'
479 // [oop_reg + offset]
480 // NullCheck oop_reg
481 //
482 // With Zero base and when narrow oops can not fold into address
483 // expression use normal implicit null check since only shift
484 // is needed to decode narrow oop.
485 //
486 // decode narrow_oop_reg, oop_reg // only 'shift'
487 // [oop_reg + offset]
488 // NullCheck oop_reg
489 //
490 inline static bool gen_narrow_oop_implicit_null_checks() {
491 // Advice matcher to perform null checks on the narrow oop side.
492 // Implicit checks are not possible on the uncompressed oop side anyway
493 // (at least not for read accesses).
494 // Performs significantly better (especially on Power 6).
495 if (!os::zero_page_read_protected()) {
496 return true;
497 }
498 return Universe::narrow_oop_use_implicit_null_checks() &&
499 (narrow_oop_use_complex_address() ||
500 Universe::narrow_oop_base() != NULL);
501 }
502
503 // Is it better to copy float constants, or load them directly from memory?
504 // Intel can load a float constant from a direct address, requiring no
505 // extra registers. Most RISCs will have to materialize an address into a
506 // register first, so they may as well materialize the constant immediately.
507 static const bool rematerialize_float_constants;
508
509 // If CPU can load and store mis-aligned doubles directly then no fixup is
510 // needed. Else we split the double into 2 integer pieces and move it
511 // piece-by-piece. Only happens when passing doubles into C code or when
512 // calling i2c adapters as the Java calling convention forces doubles to be
513 // aligned.
514 static const bool misaligned_doubles_ok;
515
516 // Does the CPU require postalloc expand (see block.cpp for description of
517 // postalloc expand)?
518 static const bool require_postalloc_expand;
519
520 // Perform a platform dependent implicit null fixup. This is needed
521 // on windows95 to take care of some unusual register constraints.
522 void pd_implicit_null_fixup(MachNode *load, uint idx);
523
524 // Advertise here if the CPU requires explicit rounding operations
525 // to implement the UseStrictFP mode.
526 static const bool strict_fp_requires_explicit_rounding;
527
528 // Are floats conerted to double when stored to stack during deoptimization?
529 static bool float_in_double();
530 // Do ints take an entire long register or just half?
531 static const bool int_in_long;
532
533 // Do the processor's shift instructions only use the low 5/6 bits
534 // of the count for 32/64 bit ints? If not we need to do the masking
535 // ourselves.
536 static const bool need_masked_shift_count;
537
538 // Whether code generation need accurate ConvI2L types.
539 static const bool convi2l_type_required;
540
541 // This routine is run whenever a graph fails to match.
542 // If it returns, the compiler should bailout to interpreter without error.
543 // In non-product mode, SoftMatchFailure is false to detect non-canonical
544 // graphs. Print a message and exit.
545 static void soft_match_failure() {
546 if( SoftMatchFailure ) return;
547 else { fatal("SoftMatchFailure is not allowed except in product"); }
548 }
549
550 // Check for a following volatile memory barrier without an
551 // intervening load and thus we don't need a barrier here. We
552 // retain the Node to act as a compiler ordering barrier.
553 static bool post_store_load_barrier(const Node* mb);
554
555 // Does n lead to an uncommon trap that can cause deoptimization?
556 static bool branches_to_uncommon_trap(const Node *n);
557
558 #ifdef ASSERT
559 void dump_old2new_map(); // machine-independent to machine-dependent
560
561 Node* find_old_node(Node* new_node) {
562 return _new2old_map[new_node->_idx];
563 }
564 #endif
565 };
566
567 #endif // SHARE_OPTO_MATCHER_HPP