1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc/shared/cardTableModRefBS.hpp"
30 #include "gc/shared/collectedHeap.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "oops/klass.inline.hpp"
35 #include "prims/methodHandles.hpp"
36 #include "runtime/biasedLocking.hpp"
37 #include "runtime/interfaceSupport.hpp"
38 #include "runtime/objectMonitor.hpp"
39 #include "runtime/os.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "runtime/stubRoutines.hpp"
42 #include "runtime/thread.hpp"
43 #include "utilities/macros.hpp"
44 #if INCLUDE_ALL_GCS
45 #include "gc/g1/g1CollectedHeap.inline.hpp"
46 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
47 #include "gc/g1/heapRegion.hpp"
48 #endif // INCLUDE_ALL_GCS
49 #include "crc32c.h"
50 #ifdef COMPILER2
51 #include "opto/intrinsicnode.hpp"
52 #endif
53
54 #ifdef PRODUCT
55 #define BLOCK_COMMENT(str) /* nothing */
56 #define STOP(error) stop(error)
57 #else
58 #define BLOCK_COMMENT(str) block_comment(str)
59 #define STOP(error) block_comment(error); stop(error)
60 #endif
61
62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
63
64 #ifdef ASSERT
65 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
66 #endif
67
68 static Assembler::Condition reverse[] = {
69 Assembler::noOverflow /* overflow = 0x0 */ ,
70 Assembler::overflow /* noOverflow = 0x1 */ ,
71 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
72 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
73 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
74 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
75 Assembler::above /* belowEqual = 0x6 */ ,
76 Assembler::belowEqual /* above = 0x7 */ ,
77 Assembler::positive /* negative = 0x8 */ ,
78 Assembler::negative /* positive = 0x9 */ ,
79 Assembler::noParity /* parity = 0xa */ ,
80 Assembler::parity /* noParity = 0xb */ ,
81 Assembler::greaterEqual /* less = 0xc */ ,
82 Assembler::less /* greaterEqual = 0xd */ ,
83 Assembler::greater /* lessEqual = 0xe */ ,
84 Assembler::lessEqual /* greater = 0xf, */
85
86 };
87
88
89 // Implementation of MacroAssembler
90
91 // First all the versions that have distinct versions depending on 32/64 bit
92 // Unless the difference is trivial (1 line or so).
93
94 #ifndef _LP64
95
96 // 32bit versions
97
98 Address MacroAssembler::as_Address(AddressLiteral adr) {
99 return Address(adr.target(), adr.rspec());
100 }
101
102 Address MacroAssembler::as_Address(ArrayAddress adr) {
103 return Address::make_array(adr);
104 }
105
106 void MacroAssembler::call_VM_leaf_base(address entry_point,
107 int number_of_arguments) {
108 call(RuntimeAddress(entry_point));
109 increment(rsp, number_of_arguments * wordSize);
110 }
111
112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
114 }
115
116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
117 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
118 }
119
120 void MacroAssembler::cmpoop(Address src1, jobject obj) {
121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
122 }
123
124 void MacroAssembler::cmpoop(Register src1, jobject obj) {
125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
126 }
127
128 void MacroAssembler::extend_sign(Register hi, Register lo) {
129 // According to Intel Doc. AP-526, "Integer Divide", p.18.
130 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
131 cdql();
132 } else {
133 movl(hi, lo);
134 sarl(hi, 31);
135 }
136 }
137
138 void MacroAssembler::jC2(Register tmp, Label& L) {
139 // set parity bit if FPU flag C2 is set (via rax)
140 save_rax(tmp);
141 fwait(); fnstsw_ax();
142 sahf();
143 restore_rax(tmp);
144 // branch
145 jcc(Assembler::parity, L);
146 }
147
148 void MacroAssembler::jnC2(Register tmp, Label& L) {
149 // set parity bit if FPU flag C2 is set (via rax)
150 save_rax(tmp);
151 fwait(); fnstsw_ax();
152 sahf();
153 restore_rax(tmp);
154 // branch
155 jcc(Assembler::noParity, L);
156 }
157
158 // 32bit can do a case table jump in one instruction but we no longer allow the base
159 // to be installed in the Address class
160 void MacroAssembler::jump(ArrayAddress entry) {
161 jmp(as_Address(entry));
162 }
163
164 // Note: y_lo will be destroyed
165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
166 // Long compare for Java (semantics as described in JVM spec.)
167 Label high, low, done;
168
169 cmpl(x_hi, y_hi);
170 jcc(Assembler::less, low);
171 jcc(Assembler::greater, high);
172 // x_hi is the return register
173 xorl(x_hi, x_hi);
174 cmpl(x_lo, y_lo);
175 jcc(Assembler::below, low);
176 jcc(Assembler::equal, done);
177
178 bind(high);
179 xorl(x_hi, x_hi);
180 increment(x_hi);
181 jmp(done);
182
183 bind(low);
184 xorl(x_hi, x_hi);
185 decrementl(x_hi);
186
187 bind(done);
188 }
189
190 void MacroAssembler::lea(Register dst, AddressLiteral src) {
191 mov_literal32(dst, (int32_t)src.target(), src.rspec());
192 }
193
194 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
195 // leal(dst, as_Address(adr));
196 // see note in movl as to why we must use a move
197 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
198 }
199
200 void MacroAssembler::leave() {
201 mov(rsp, rbp);
202 pop(rbp);
203 }
204
205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
206 // Multiplication of two Java long values stored on the stack
207 // as illustrated below. Result is in rdx:rax.
208 //
209 // rsp ---> [ ?? ] \ \
210 // .... | y_rsp_offset |
211 // [ y_lo ] / (in bytes) | x_rsp_offset
212 // [ y_hi ] | (in bytes)
213 // .... |
214 // [ x_lo ] /
215 // [ x_hi ]
216 // ....
217 //
218 // Basic idea: lo(result) = lo(x_lo * y_lo)
219 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
220 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
221 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
222 Label quick;
223 // load x_hi, y_hi and check if quick
224 // multiplication is possible
225 movl(rbx, x_hi);
226 movl(rcx, y_hi);
227 movl(rax, rbx);
228 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
229 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
230 // do full multiplication
231 // 1st step
232 mull(y_lo); // x_hi * y_lo
233 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
234 // 2nd step
235 movl(rax, x_lo);
236 mull(rcx); // x_lo * y_hi
237 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
238 // 3rd step
239 bind(quick); // note: rbx, = 0 if quick multiply!
240 movl(rax, x_lo);
241 mull(y_lo); // x_lo * y_lo
242 addl(rdx, rbx); // correct hi(x_lo * y_lo)
243 }
244
245 void MacroAssembler::lneg(Register hi, Register lo) {
246 negl(lo);
247 adcl(hi, 0);
248 negl(hi);
249 }
250
251 void MacroAssembler::lshl(Register hi, Register lo) {
252 // Java shift left long support (semantics as described in JVM spec., p.305)
253 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
254 // shift value is in rcx !
255 assert(hi != rcx, "must not use rcx");
256 assert(lo != rcx, "must not use rcx");
257 const Register s = rcx; // shift count
258 const int n = BitsPerWord;
259 Label L;
260 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
261 cmpl(s, n); // if (s < n)
262 jcc(Assembler::less, L); // else (s >= n)
263 movl(hi, lo); // x := x << n
264 xorl(lo, lo);
265 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
266 bind(L); // s (mod n) < n
267 shldl(hi, lo); // x := x << s
268 shll(lo);
269 }
270
271
272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
273 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
274 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
275 assert(hi != rcx, "must not use rcx");
276 assert(lo != rcx, "must not use rcx");
277 const Register s = rcx; // shift count
278 const int n = BitsPerWord;
279 Label L;
280 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
281 cmpl(s, n); // if (s < n)
282 jcc(Assembler::less, L); // else (s >= n)
283 movl(lo, hi); // x := x >> n
284 if (sign_extension) sarl(hi, 31);
285 else xorl(hi, hi);
286 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
287 bind(L); // s (mod n) < n
288 shrdl(lo, hi); // x := x >> s
289 if (sign_extension) sarl(hi);
290 else shrl(hi);
291 }
292
293 void MacroAssembler::movoop(Register dst, jobject obj) {
294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
295 }
296
297 void MacroAssembler::movoop(Address dst, jobject obj) {
298 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
299 }
300
301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
303 }
304
305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
306 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
307 }
308
309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
310 // scratch register is not used,
311 // it is defined to match parameters of 64-bit version of this method.
312 if (src.is_lval()) {
313 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
314 } else {
315 movl(dst, as_Address(src));
316 }
317 }
318
319 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
320 movl(as_Address(dst), src);
321 }
322
323 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
324 movl(dst, as_Address(src));
325 }
326
327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
328 void MacroAssembler::movptr(Address dst, intptr_t src) {
329 movl(dst, src);
330 }
331
332
333 void MacroAssembler::pop_callee_saved_registers() {
334 pop(rcx);
335 pop(rdx);
336 pop(rdi);
337 pop(rsi);
338 }
339
340 void MacroAssembler::pop_fTOS() {
341 fld_d(Address(rsp, 0));
342 addl(rsp, 2 * wordSize);
343 }
344
345 void MacroAssembler::push_callee_saved_registers() {
346 push(rsi);
347 push(rdi);
348 push(rdx);
349 push(rcx);
350 }
351
352 void MacroAssembler::push_fTOS() {
353 subl(rsp, 2 * wordSize);
354 fstp_d(Address(rsp, 0));
355 }
356
357
358 void MacroAssembler::pushoop(jobject obj) {
359 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
360 }
361
362 void MacroAssembler::pushklass(Metadata* obj) {
363 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
364 }
365
366 void MacroAssembler::pushptr(AddressLiteral src) {
367 if (src.is_lval()) {
368 push_literal32((int32_t)src.target(), src.rspec());
369 } else {
370 pushl(as_Address(src));
371 }
372 }
373
374 void MacroAssembler::set_word_if_not_zero(Register dst) {
375 xorl(dst, dst);
376 set_byte_if_not_zero(dst);
377 }
378
379 static void pass_arg0(MacroAssembler* masm, Register arg) {
380 masm->push(arg);
381 }
382
383 static void pass_arg1(MacroAssembler* masm, Register arg) {
384 masm->push(arg);
385 }
386
387 static void pass_arg2(MacroAssembler* masm, Register arg) {
388 masm->push(arg);
389 }
390
391 static void pass_arg3(MacroAssembler* masm, Register arg) {
392 masm->push(arg);
393 }
394
395 #ifndef PRODUCT
396 extern "C" void findpc(intptr_t x);
397 #endif
398
399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
400 // In order to get locks to work, we need to fake a in_VM state
401 JavaThread* thread = JavaThread::current();
402 JavaThreadState saved_state = thread->thread_state();
403 thread->set_thread_state(_thread_in_vm);
404 if (ShowMessageBoxOnError) {
405 JavaThread* thread = JavaThread::current();
406 JavaThreadState saved_state = thread->thread_state();
407 thread->set_thread_state(_thread_in_vm);
408 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
409 ttyLocker ttyl;
410 BytecodeCounter::print();
411 }
412 // To see where a verify_oop failed, get $ebx+40/X for this frame.
413 // This is the value of eip which points to where verify_oop will return.
414 if (os::message_box(msg, "Execution stopped, print registers?")) {
415 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
416 BREAKPOINT;
417 }
418 } else {
419 ttyLocker ttyl;
420 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
421 }
422 // Don't assert holding the ttyLock
423 assert(false, "DEBUG MESSAGE: %s", msg);
424 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
425 }
426
427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
428 ttyLocker ttyl;
429 FlagSetting fs(Debugging, true);
430 tty->print_cr("eip = 0x%08x", eip);
431 #ifndef PRODUCT
432 if ((WizardMode || Verbose) && PrintMiscellaneous) {
433 tty->cr();
434 findpc(eip);
435 tty->cr();
436 }
437 #endif
438 #define PRINT_REG(rax) \
439 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
440 PRINT_REG(rax);
441 PRINT_REG(rbx);
442 PRINT_REG(rcx);
443 PRINT_REG(rdx);
444 PRINT_REG(rdi);
445 PRINT_REG(rsi);
446 PRINT_REG(rbp);
447 PRINT_REG(rsp);
448 #undef PRINT_REG
449 // Print some words near top of staack.
450 int* dump_sp = (int*) rsp;
451 for (int col1 = 0; col1 < 8; col1++) {
452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
453 os::print_location(tty, *dump_sp++);
454 }
455 for (int row = 0; row < 16; row++) {
456 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
457 for (int col = 0; col < 8; col++) {
458 tty->print(" 0x%08x", *dump_sp++);
459 }
460 tty->cr();
461 }
462 // Print some instructions around pc:
463 Disassembler::decode((address)eip-64, (address)eip);
464 tty->print_cr("--------");
465 Disassembler::decode((address)eip, (address)eip+32);
466 }
467
468 void MacroAssembler::stop(const char* msg) {
469 ExternalAddress message((address)msg);
470 // push address of message
471 pushptr(message.addr());
472 { Label L; call(L, relocInfo::none); bind(L); } // push eip
473 pusha(); // push registers
474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
475 hlt();
476 }
477
478 void MacroAssembler::warn(const char* msg) {
479 push_CPU_state();
480
481 ExternalAddress message((address) msg);
482 // push address of message
483 pushptr(message.addr());
484
485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
486 addl(rsp, wordSize); // discard argument
487 pop_CPU_state();
488 }
489
490 void MacroAssembler::print_state() {
491 { Label L; call(L, relocInfo::none); bind(L); } // push eip
492 pusha(); // push registers
493
494 push_CPU_state();
495 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
496 pop_CPU_state();
497
498 popa();
499 addl(rsp, wordSize);
500 }
501
502 #else // _LP64
503
504 // 64 bit versions
505
506 Address MacroAssembler::as_Address(AddressLiteral adr) {
507 // amd64 always does this as a pc-rel
508 // we can be absolute or disp based on the instruction type
509 // jmp/call are displacements others are absolute
510 assert(!adr.is_lval(), "must be rval");
511 assert(reachable(adr), "must be");
512 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
513
514 }
515
516 Address MacroAssembler::as_Address(ArrayAddress adr) {
517 AddressLiteral base = adr.base();
518 lea(rscratch1, base);
519 Address index = adr.index();
520 assert(index._disp == 0, "must not have disp"); // maybe it can?
521 Address array(rscratch1, index._index, index._scale, index._disp);
522 return array;
523 }
524
525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
526 Label L, E;
527
528 #ifdef _WIN64
529 // Windows always allocates space for it's register args
530 assert(num_args <= 4, "only register arguments supported");
531 subq(rsp, frame::arg_reg_save_area_bytes);
532 #endif
533
534 // Align stack if necessary
535 testl(rsp, 15);
536 jcc(Assembler::zero, L);
537
538 subq(rsp, 8);
539 {
540 call(RuntimeAddress(entry_point));
541 }
542 addq(rsp, 8);
543 jmp(E);
544
545 bind(L);
546 {
547 call(RuntimeAddress(entry_point));
548 }
549
550 bind(E);
551
552 #ifdef _WIN64
553 // restore stack pointer
554 addq(rsp, frame::arg_reg_save_area_bytes);
555 #endif
556
557 }
558
559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
560 assert(!src2.is_lval(), "should use cmpptr");
561
562 if (reachable(src2)) {
563 cmpq(src1, as_Address(src2));
564 } else {
565 lea(rscratch1, src2);
566 Assembler::cmpq(src1, Address(rscratch1, 0));
567 }
568 }
569
570 int MacroAssembler::corrected_idivq(Register reg) {
571 // Full implementation of Java ldiv and lrem; checks for special
572 // case as described in JVM spec., p.243 & p.271. The function
573 // returns the (pc) offset of the idivl instruction - may be needed
574 // for implicit exceptions.
575 //
576 // normal case special case
577 //
578 // input : rax: dividend min_long
579 // reg: divisor (may not be eax/edx) -1
580 //
581 // output: rax: quotient (= rax idiv reg) min_long
582 // rdx: remainder (= rax irem reg) 0
583 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
584 static const int64_t min_long = 0x8000000000000000;
585 Label normal_case, special_case;
586
587 // check for special case
588 cmp64(rax, ExternalAddress((address) &min_long));
589 jcc(Assembler::notEqual, normal_case);
590 xorl(rdx, rdx); // prepare rdx for possible special case (where
591 // remainder = 0)
592 cmpq(reg, -1);
593 jcc(Assembler::equal, special_case);
594
595 // handle normal case
596 bind(normal_case);
597 cdqq();
598 int idivq_offset = offset();
599 idivq(reg);
600
601 // normal and special case exit
602 bind(special_case);
603
604 return idivq_offset;
605 }
606
607 void MacroAssembler::decrementq(Register reg, int value) {
608 if (value == min_jint) { subq(reg, value); return; }
609 if (value < 0) { incrementq(reg, -value); return; }
610 if (value == 0) { ; return; }
611 if (value == 1 && UseIncDec) { decq(reg) ; return; }
612 /* else */ { subq(reg, value) ; return; }
613 }
614
615 void MacroAssembler::decrementq(Address dst, int value) {
616 if (value == min_jint) { subq(dst, value); return; }
617 if (value < 0) { incrementq(dst, -value); return; }
618 if (value == 0) { ; return; }
619 if (value == 1 && UseIncDec) { decq(dst) ; return; }
620 /* else */ { subq(dst, value) ; return; }
621 }
622
623 void MacroAssembler::incrementq(AddressLiteral dst) {
624 if (reachable(dst)) {
625 incrementq(as_Address(dst));
626 } else {
627 lea(rscratch1, dst);
628 incrementq(Address(rscratch1, 0));
629 }
630 }
631
632 void MacroAssembler::incrementq(Register reg, int value) {
633 if (value == min_jint) { addq(reg, value); return; }
634 if (value < 0) { decrementq(reg, -value); return; }
635 if (value == 0) { ; return; }
636 if (value == 1 && UseIncDec) { incq(reg) ; return; }
637 /* else */ { addq(reg, value) ; return; }
638 }
639
640 void MacroAssembler::incrementq(Address dst, int value) {
641 if (value == min_jint) { addq(dst, value); return; }
642 if (value < 0) { decrementq(dst, -value); return; }
643 if (value == 0) { ; return; }
644 if (value == 1 && UseIncDec) { incq(dst) ; return; }
645 /* else */ { addq(dst, value) ; return; }
646 }
647
648 // 32bit can do a case table jump in one instruction but we no longer allow the base
649 // to be installed in the Address class
650 void MacroAssembler::jump(ArrayAddress entry) {
651 lea(rscratch1, entry.base());
652 Address dispatch = entry.index();
653 assert(dispatch._base == noreg, "must be");
654 dispatch._base = rscratch1;
655 jmp(dispatch);
656 }
657
658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
659 ShouldNotReachHere(); // 64bit doesn't use two regs
660 cmpq(x_lo, y_lo);
661 }
662
663 void MacroAssembler::lea(Register dst, AddressLiteral src) {
664 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
665 }
666
667 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
668 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
669 movptr(dst, rscratch1);
670 }
671
672 void MacroAssembler::leave() {
673 // %%% is this really better? Why not on 32bit too?
674 emit_int8((unsigned char)0xC9); // LEAVE
675 }
676
677 void MacroAssembler::lneg(Register hi, Register lo) {
678 ShouldNotReachHere(); // 64bit doesn't use two regs
679 negq(lo);
680 }
681
682 void MacroAssembler::movoop(Register dst, jobject obj) {
683 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
684 }
685
686 void MacroAssembler::movoop(Address dst, jobject obj) {
687 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
688 movq(dst, rscratch1);
689 }
690
691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
692 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
693 }
694
695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
696 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
697 movq(dst, rscratch1);
698 }
699
700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
701 if (src.is_lval()) {
702 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
703 } else {
704 if (reachable(src)) {
705 movq(dst, as_Address(src));
706 } else {
707 lea(scratch, src);
708 movq(dst, Address(scratch, 0));
709 }
710 }
711 }
712
713 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
714 movq(as_Address(dst), src);
715 }
716
717 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
718 movq(dst, as_Address(src));
719 }
720
721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
722 void MacroAssembler::movptr(Address dst, intptr_t src) {
723 mov64(rscratch1, src);
724 movq(dst, rscratch1);
725 }
726
727 // These are mostly for initializing NULL
728 void MacroAssembler::movptr(Address dst, int32_t src) {
729 movslq(dst, src);
730 }
731
732 void MacroAssembler::movptr(Register dst, int32_t src) {
733 mov64(dst, (intptr_t)src);
734 }
735
736 void MacroAssembler::pushoop(jobject obj) {
737 movoop(rscratch1, obj);
738 push(rscratch1);
739 }
740
741 void MacroAssembler::pushklass(Metadata* obj) {
742 mov_metadata(rscratch1, obj);
743 push(rscratch1);
744 }
745
746 void MacroAssembler::pushptr(AddressLiteral src) {
747 lea(rscratch1, src);
748 if (src.is_lval()) {
749 push(rscratch1);
750 } else {
751 pushq(Address(rscratch1, 0));
752 }
753 }
754
755 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
756 // we must set sp to zero to clear frame
757 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
758 // must clear fp, so that compiled frames are not confused; it is
759 // possible that we need it only for debugging
760 if (clear_fp) {
761 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
762 }
763
764 // Always clear the pc because it could have been set by make_walkable()
765 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
766 vzeroupper();
767 }
768
769 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
770 Register last_java_fp,
771 address last_java_pc) {
772 vzeroupper();
773 // determine last_java_sp register
774 if (!last_java_sp->is_valid()) {
775 last_java_sp = rsp;
776 }
777
778 // last_java_fp is optional
779 if (last_java_fp->is_valid()) {
780 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
781 last_java_fp);
782 }
783
784 // last_java_pc is optional
785 if (last_java_pc != NULL) {
786 Address java_pc(r15_thread,
787 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
788 lea(rscratch1, InternalAddress(last_java_pc));
789 movptr(java_pc, rscratch1);
790 }
791
792 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
793 }
794
795 static void pass_arg0(MacroAssembler* masm, Register arg) {
796 if (c_rarg0 != arg ) {
797 masm->mov(c_rarg0, arg);
798 }
799 }
800
801 static void pass_arg1(MacroAssembler* masm, Register arg) {
802 if (c_rarg1 != arg ) {
803 masm->mov(c_rarg1, arg);
804 }
805 }
806
807 static void pass_arg2(MacroAssembler* masm, Register arg) {
808 if (c_rarg2 != arg ) {
809 masm->mov(c_rarg2, arg);
810 }
811 }
812
813 static void pass_arg3(MacroAssembler* masm, Register arg) {
814 if (c_rarg3 != arg ) {
815 masm->mov(c_rarg3, arg);
816 }
817 }
818
819 void MacroAssembler::stop(const char* msg) {
820 address rip = pc();
821 pusha(); // get regs on stack
822 lea(c_rarg0, ExternalAddress((address) msg));
823 lea(c_rarg1, InternalAddress(rip));
824 movq(c_rarg2, rsp); // pass pointer to regs array
825 andq(rsp, -16); // align stack as required by ABI
826 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
827 hlt();
828 }
829
830 void MacroAssembler::warn(const char* msg) {
831 push(rbp);
832 movq(rbp, rsp);
833 andq(rsp, -16); // align stack as required by push_CPU_state and call
834 push_CPU_state(); // keeps alignment at 16 bytes
835 lea(c_rarg0, ExternalAddress((address) msg));
836 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
837 pop_CPU_state();
838 mov(rsp, rbp);
839 pop(rbp);
840 }
841
842 void MacroAssembler::print_state() {
843 address rip = pc();
844 pusha(); // get regs on stack
845 push(rbp);
846 movq(rbp, rsp);
847 andq(rsp, -16); // align stack as required by push_CPU_state and call
848 push_CPU_state(); // keeps alignment at 16 bytes
849
850 lea(c_rarg0, InternalAddress(rip));
851 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
852 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
853
854 pop_CPU_state();
855 mov(rsp, rbp);
856 pop(rbp);
857 popa();
858 }
859
860 #ifndef PRODUCT
861 extern "C" void findpc(intptr_t x);
862 #endif
863
864 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
865 // In order to get locks to work, we need to fake a in_VM state
866 if (ShowMessageBoxOnError) {
867 JavaThread* thread = JavaThread::current();
868 JavaThreadState saved_state = thread->thread_state();
869 thread->set_thread_state(_thread_in_vm);
870 #ifndef PRODUCT
871 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
872 ttyLocker ttyl;
873 BytecodeCounter::print();
874 }
875 #endif
876 // To see where a verify_oop failed, get $ebx+40/X for this frame.
877 // XXX correct this offset for amd64
878 // This is the value of eip which points to where verify_oop will return.
879 if (os::message_box(msg, "Execution stopped, print registers?")) {
880 print_state64(pc, regs);
881 BREAKPOINT;
882 assert(false, "start up GDB");
883 }
884 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
885 } else {
886 ttyLocker ttyl;
887 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
888 msg);
889 assert(false, "DEBUG MESSAGE: %s", msg);
890 }
891 }
892
893 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
894 ttyLocker ttyl;
895 FlagSetting fs(Debugging, true);
896 tty->print_cr("rip = 0x%016lx", pc);
897 #ifndef PRODUCT
898 tty->cr();
899 findpc(pc);
900 tty->cr();
901 #endif
902 #define PRINT_REG(rax, value) \
903 { tty->print("%s = ", #rax); os::print_location(tty, value); }
904 PRINT_REG(rax, regs[15]);
905 PRINT_REG(rbx, regs[12]);
906 PRINT_REG(rcx, regs[14]);
907 PRINT_REG(rdx, regs[13]);
908 PRINT_REG(rdi, regs[8]);
909 PRINT_REG(rsi, regs[9]);
910 PRINT_REG(rbp, regs[10]);
911 PRINT_REG(rsp, regs[11]);
912 PRINT_REG(r8 , regs[7]);
913 PRINT_REG(r9 , regs[6]);
914 PRINT_REG(r10, regs[5]);
915 PRINT_REG(r11, regs[4]);
916 PRINT_REG(r12, regs[3]);
917 PRINT_REG(r13, regs[2]);
918 PRINT_REG(r14, regs[1]);
919 PRINT_REG(r15, regs[0]);
920 #undef PRINT_REG
921 // Print some words near top of staack.
922 int64_t* rsp = (int64_t*) regs[11];
923 int64_t* dump_sp = rsp;
924 for (int col1 = 0; col1 < 8; col1++) {
925 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
926 os::print_location(tty, *dump_sp++);
927 }
928 for (int row = 0; row < 25; row++) {
929 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
930 for (int col = 0; col < 4; col++) {
931 tty->print(" 0x%016lx", *dump_sp++);
932 }
933 tty->cr();
934 }
935 // Print some instructions around pc:
936 Disassembler::decode((address)pc-64, (address)pc);
937 tty->print_cr("--------");
938 Disassembler::decode((address)pc, (address)pc+32);
939 }
940
941 #endif // _LP64
942
943 // Now versions that are common to 32/64 bit
944
945 void MacroAssembler::addptr(Register dst, int32_t imm32) {
946 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
947 }
948
949 void MacroAssembler::addptr(Register dst, Register src) {
950 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
951 }
952
953 void MacroAssembler::addptr(Address dst, Register src) {
954 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
955 }
956
957 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
958 if (reachable(src)) {
959 Assembler::addsd(dst, as_Address(src));
960 } else {
961 lea(rscratch1, src);
962 Assembler::addsd(dst, Address(rscratch1, 0));
963 }
964 }
965
966 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
967 if (reachable(src)) {
968 addss(dst, as_Address(src));
969 } else {
970 lea(rscratch1, src);
971 addss(dst, Address(rscratch1, 0));
972 }
973 }
974
975 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
976 if (reachable(src)) {
977 Assembler::addpd(dst, as_Address(src));
978 } else {
979 lea(rscratch1, src);
980 Assembler::addpd(dst, Address(rscratch1, 0));
981 }
982 }
983
984 void MacroAssembler::align(int modulus) {
985 align(modulus, offset());
986 }
987
988 void MacroAssembler::align(int modulus, int target) {
989 if (target % modulus != 0) {
990 nop(modulus - (target % modulus));
991 }
992 }
993
994 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
995 // Used in sign-masking with aligned address.
996 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
997 if (reachable(src)) {
998 Assembler::andpd(dst, as_Address(src));
999 } else {
1000 lea(rscratch1, src);
1001 Assembler::andpd(dst, Address(rscratch1, 0));
1002 }
1003 }
1004
1005 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1006 // Used in sign-masking with aligned address.
1007 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1008 if (reachable(src)) {
1009 Assembler::andps(dst, as_Address(src));
1010 } else {
1011 lea(rscratch1, src);
1012 Assembler::andps(dst, Address(rscratch1, 0));
1013 }
1014 }
1015
1016 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1017 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1018 }
1019
1020 void MacroAssembler::atomic_incl(Address counter_addr) {
1021 if (os::is_MP())
1022 lock();
1023 incrementl(counter_addr);
1024 }
1025
1026 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1027 if (reachable(counter_addr)) {
1028 atomic_incl(as_Address(counter_addr));
1029 } else {
1030 lea(scr, counter_addr);
1031 atomic_incl(Address(scr, 0));
1032 }
1033 }
1034
1035 #ifdef _LP64
1036 void MacroAssembler::atomic_incq(Address counter_addr) {
1037 if (os::is_MP())
1038 lock();
1039 incrementq(counter_addr);
1040 }
1041
1042 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1043 if (reachable(counter_addr)) {
1044 atomic_incq(as_Address(counter_addr));
1045 } else {
1046 lea(scr, counter_addr);
1047 atomic_incq(Address(scr, 0));
1048 }
1049 }
1050 #endif
1051
1052 // Writes to stack successive pages until offset reached to check for
1053 // stack overflow + shadow pages. This clobbers tmp.
1054 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1055 movptr(tmp, rsp);
1056 // Bang stack for total size given plus shadow page size.
1057 // Bang one page at a time because large size can bang beyond yellow and
1058 // red zones.
1059 Label loop;
1060 bind(loop);
1061 movl(Address(tmp, (-os::vm_page_size())), size );
1062 subptr(tmp, os::vm_page_size());
1063 subl(size, os::vm_page_size());
1064 jcc(Assembler::greater, loop);
1065
1066 // Bang down shadow pages too.
1067 // At this point, (tmp-0) is the last address touched, so don't
1068 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1069 // was post-decremented.) Skip this address by starting at i=1, and
1070 // touch a few more pages below. N.B. It is important to touch all
1071 // the way down including all pages in the shadow zone.
1072 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1073 // this could be any sized move but this is can be a debugging crumb
1074 // so the bigger the better.
1075 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1076 }
1077 }
1078
1079 void MacroAssembler::reserved_stack_check() {
1080 // testing if reserved zone needs to be enabled
1081 Label no_reserved_zone_enabling;
1082 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1083 NOT_LP64(get_thread(rsi);)
1084
1085 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1086 jcc(Assembler::below, no_reserved_zone_enabling);
1087
1088 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1089 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1090 should_not_reach_here();
1091
1092 bind(no_reserved_zone_enabling);
1093 }
1094
1095 int MacroAssembler::biased_locking_enter(Register lock_reg,
1096 Register obj_reg,
1097 Register swap_reg,
1098 Register tmp_reg,
1099 bool swap_reg_contains_mark,
1100 Label& done,
1101 Label* slow_case,
1102 BiasedLockingCounters* counters) {
1103 assert(UseBiasedLocking, "why call this otherwise?");
1104 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1105 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1106 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1107 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1108 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1109 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1110
1111 if (PrintBiasedLockingStatistics && counters == NULL) {
1112 counters = BiasedLocking::counters();
1113 }
1114 // Biased locking
1115 // See whether the lock is currently biased toward our thread and
1116 // whether the epoch is still valid
1117 // Note that the runtime guarantees sufficient alignment of JavaThread
1118 // pointers to allow age to be placed into low bits
1119 // First check to see whether biasing is even enabled for this object
1120 Label cas_label;
1121 int null_check_offset = -1;
1122 if (!swap_reg_contains_mark) {
1123 null_check_offset = offset();
1124 movptr(swap_reg, mark_addr);
1125 }
1126 movptr(tmp_reg, swap_reg);
1127 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1128 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1129 jcc(Assembler::notEqual, cas_label);
1130 // The bias pattern is present in the object's header. Need to check
1131 // whether the bias owner and the epoch are both still current.
1132 #ifndef _LP64
1133 // Note that because there is no current thread register on x86_32 we
1134 // need to store off the mark word we read out of the object to
1135 // avoid reloading it and needing to recheck invariants below. This
1136 // store is unfortunate but it makes the overall code shorter and
1137 // simpler.
1138 movptr(saved_mark_addr, swap_reg);
1139 #endif
1140 if (swap_reg_contains_mark) {
1141 null_check_offset = offset();
1142 }
1143 load_prototype_header(tmp_reg, obj_reg);
1144 #ifdef _LP64
1145 orptr(tmp_reg, r15_thread);
1146 xorptr(tmp_reg, swap_reg);
1147 Register header_reg = tmp_reg;
1148 #else
1149 xorptr(tmp_reg, swap_reg);
1150 get_thread(swap_reg);
1151 xorptr(swap_reg, tmp_reg);
1152 Register header_reg = swap_reg;
1153 #endif
1154 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1155 if (counters != NULL) {
1156 cond_inc32(Assembler::zero,
1157 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1158 }
1159 jcc(Assembler::equal, done);
1160
1161 Label try_revoke_bias;
1162 Label try_rebias;
1163
1164 // At this point we know that the header has the bias pattern and
1165 // that we are not the bias owner in the current epoch. We need to
1166 // figure out more details about the state of the header in order to
1167 // know what operations can be legally performed on the object's
1168 // header.
1169
1170 // If the low three bits in the xor result aren't clear, that means
1171 // the prototype header is no longer biased and we have to revoke
1172 // the bias on this object.
1173 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1174 jccb(Assembler::notZero, try_revoke_bias);
1175
1176 // Biasing is still enabled for this data type. See whether the
1177 // epoch of the current bias is still valid, meaning that the epoch
1178 // bits of the mark word are equal to the epoch bits of the
1179 // prototype header. (Note that the prototype header's epoch bits
1180 // only change at a safepoint.) If not, attempt to rebias the object
1181 // toward the current thread. Note that we must be absolutely sure
1182 // that the current epoch is invalid in order to do this because
1183 // otherwise the manipulations it performs on the mark word are
1184 // illegal.
1185 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1186 jccb(Assembler::notZero, try_rebias);
1187
1188 // The epoch of the current bias is still valid but we know nothing
1189 // about the owner; it might be set or it might be clear. Try to
1190 // acquire the bias of the object using an atomic operation. If this
1191 // fails we will go in to the runtime to revoke the object's bias.
1192 // Note that we first construct the presumed unbiased header so we
1193 // don't accidentally blow away another thread's valid bias.
1194 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1195 andptr(swap_reg,
1196 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1197 #ifdef _LP64
1198 movptr(tmp_reg, swap_reg);
1199 orptr(tmp_reg, r15_thread);
1200 #else
1201 get_thread(tmp_reg);
1202 orptr(tmp_reg, swap_reg);
1203 #endif
1204 if (os::is_MP()) {
1205 lock();
1206 }
1207 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1208 // If the biasing toward our thread failed, this means that
1209 // another thread succeeded in biasing it toward itself and we
1210 // need to revoke that bias. The revocation will occur in the
1211 // interpreter runtime in the slow case.
1212 if (counters != NULL) {
1213 cond_inc32(Assembler::zero,
1214 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1215 }
1216 if (slow_case != NULL) {
1217 jcc(Assembler::notZero, *slow_case);
1218 }
1219 jmp(done);
1220
1221 bind(try_rebias);
1222 // At this point we know the epoch has expired, meaning that the
1223 // current "bias owner", if any, is actually invalid. Under these
1224 // circumstances _only_, we are allowed to use the current header's
1225 // value as the comparison value when doing the cas to acquire the
1226 // bias in the current epoch. In other words, we allow transfer of
1227 // the bias from one thread to another directly in this situation.
1228 //
1229 // FIXME: due to a lack of registers we currently blow away the age
1230 // bits in this situation. Should attempt to preserve them.
1231 load_prototype_header(tmp_reg, obj_reg);
1232 #ifdef _LP64
1233 orptr(tmp_reg, r15_thread);
1234 #else
1235 get_thread(swap_reg);
1236 orptr(tmp_reg, swap_reg);
1237 movptr(swap_reg, saved_mark_addr);
1238 #endif
1239 if (os::is_MP()) {
1240 lock();
1241 }
1242 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1243 // If the biasing toward our thread failed, then another thread
1244 // succeeded in biasing it toward itself and we need to revoke that
1245 // bias. The revocation will occur in the runtime in the slow case.
1246 if (counters != NULL) {
1247 cond_inc32(Assembler::zero,
1248 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1249 }
1250 if (slow_case != NULL) {
1251 jcc(Assembler::notZero, *slow_case);
1252 }
1253 jmp(done);
1254
1255 bind(try_revoke_bias);
1256 // The prototype mark in the klass doesn't have the bias bit set any
1257 // more, indicating that objects of this data type are not supposed
1258 // to be biased any more. We are going to try to reset the mark of
1259 // this object to the prototype value and fall through to the
1260 // CAS-based locking scheme. Note that if our CAS fails, it means
1261 // that another thread raced us for the privilege of revoking the
1262 // bias of this particular object, so it's okay to continue in the
1263 // normal locking code.
1264 //
1265 // FIXME: due to a lack of registers we currently blow away the age
1266 // bits in this situation. Should attempt to preserve them.
1267 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1268 load_prototype_header(tmp_reg, obj_reg);
1269 if (os::is_MP()) {
1270 lock();
1271 }
1272 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1273 // Fall through to the normal CAS-based lock, because no matter what
1274 // the result of the above CAS, some thread must have succeeded in
1275 // removing the bias bit from the object's header.
1276 if (counters != NULL) {
1277 cond_inc32(Assembler::zero,
1278 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1279 }
1280
1281 bind(cas_label);
1282
1283 return null_check_offset;
1284 }
1285
1286 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1287 assert(UseBiasedLocking, "why call this otherwise?");
1288
1289 // Check for biased locking unlock case, which is a no-op
1290 // Note: we do not have to check the thread ID for two reasons.
1291 // First, the interpreter checks for IllegalMonitorStateException at
1292 // a higher level. Second, if the bias was revoked while we held the
1293 // lock, the object could not be rebiased toward another thread, so
1294 // the bias bit would be clear.
1295 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1296 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1297 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1298 jcc(Assembler::equal, done);
1299 }
1300
1301 #ifdef COMPILER2
1302
1303 #if INCLUDE_RTM_OPT
1304
1305 // Update rtm_counters based on abort status
1306 // input: abort_status
1307 // rtm_counters (RTMLockingCounters*)
1308 // flags are killed
1309 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1310
1311 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1312 if (PrintPreciseRTMLockingStatistics) {
1313 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1314 Label check_abort;
1315 testl(abort_status, (1<<i));
1316 jccb(Assembler::equal, check_abort);
1317 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1318 bind(check_abort);
1319 }
1320 }
1321 }
1322
1323 // Branch if (random & (count-1) != 0), count is 2^n
1324 // tmp, scr and flags are killed
1325 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1326 assert(tmp == rax, "");
1327 assert(scr == rdx, "");
1328 rdtsc(); // modifies EDX:EAX
1329 andptr(tmp, count-1);
1330 jccb(Assembler::notZero, brLabel);
1331 }
1332
1333 // Perform abort ratio calculation, set no_rtm bit if high ratio
1334 // input: rtm_counters_Reg (RTMLockingCounters* address)
1335 // tmpReg, rtm_counters_Reg and flags are killed
1336 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1337 Register rtm_counters_Reg,
1338 RTMLockingCounters* rtm_counters,
1339 Metadata* method_data) {
1340 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1341
1342 if (RTMLockingCalculationDelay > 0) {
1343 // Delay calculation
1344 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1345 testptr(tmpReg, tmpReg);
1346 jccb(Assembler::equal, L_done);
1347 }
1348 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1349 // Aborted transactions = abort_count * 100
1350 // All transactions = total_count * RTMTotalCountIncrRate
1351 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1352
1353 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1354 cmpptr(tmpReg, RTMAbortThreshold);
1355 jccb(Assembler::below, L_check_always_rtm2);
1356 imulptr(tmpReg, tmpReg, 100);
1357
1358 Register scrReg = rtm_counters_Reg;
1359 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1360 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1361 imulptr(scrReg, scrReg, RTMAbortRatio);
1362 cmpptr(tmpReg, scrReg);
1363 jccb(Assembler::below, L_check_always_rtm1);
1364 if (method_data != NULL) {
1365 // set rtm_state to "no rtm" in MDO
1366 mov_metadata(tmpReg, method_data);
1367 if (os::is_MP()) {
1368 lock();
1369 }
1370 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1371 }
1372 jmpb(L_done);
1373 bind(L_check_always_rtm1);
1374 // Reload RTMLockingCounters* address
1375 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1376 bind(L_check_always_rtm2);
1377 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1378 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1379 jccb(Assembler::below, L_done);
1380 if (method_data != NULL) {
1381 // set rtm_state to "always rtm" in MDO
1382 mov_metadata(tmpReg, method_data);
1383 if (os::is_MP()) {
1384 lock();
1385 }
1386 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1387 }
1388 bind(L_done);
1389 }
1390
1391 // Update counters and perform abort ratio calculation
1392 // input: abort_status_Reg
1393 // rtm_counters_Reg, flags are killed
1394 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1395 Register rtm_counters_Reg,
1396 RTMLockingCounters* rtm_counters,
1397 Metadata* method_data,
1398 bool profile_rtm) {
1399
1400 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1401 // update rtm counters based on rax value at abort
1402 // reads abort_status_Reg, updates flags
1403 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1404 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1405 if (profile_rtm) {
1406 // Save abort status because abort_status_Reg is used by following code.
1407 if (RTMRetryCount > 0) {
1408 push(abort_status_Reg);
1409 }
1410 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1411 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1412 // restore abort status
1413 if (RTMRetryCount > 0) {
1414 pop(abort_status_Reg);
1415 }
1416 }
1417 }
1418
1419 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1420 // inputs: retry_count_Reg
1421 // : abort_status_Reg
1422 // output: retry_count_Reg decremented by 1
1423 // flags are killed
1424 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1425 Label doneRetry;
1426 assert(abort_status_Reg == rax, "");
1427 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1428 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1429 // if reason is in 0x6 and retry count != 0 then retry
1430 andptr(abort_status_Reg, 0x6);
1431 jccb(Assembler::zero, doneRetry);
1432 testl(retry_count_Reg, retry_count_Reg);
1433 jccb(Assembler::zero, doneRetry);
1434 pause();
1435 decrementl(retry_count_Reg);
1436 jmp(retryLabel);
1437 bind(doneRetry);
1438 }
1439
1440 // Spin and retry if lock is busy,
1441 // inputs: box_Reg (monitor address)
1442 // : retry_count_Reg
1443 // output: retry_count_Reg decremented by 1
1444 // : clear z flag if retry count exceeded
1445 // tmp_Reg, scr_Reg, flags are killed
1446 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1447 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1448 Label SpinLoop, SpinExit, doneRetry;
1449 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1450
1451 testl(retry_count_Reg, retry_count_Reg);
1452 jccb(Assembler::zero, doneRetry);
1453 decrementl(retry_count_Reg);
1454 movptr(scr_Reg, RTMSpinLoopCount);
1455
1456 bind(SpinLoop);
1457 pause();
1458 decrementl(scr_Reg);
1459 jccb(Assembler::lessEqual, SpinExit);
1460 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1461 testptr(tmp_Reg, tmp_Reg);
1462 jccb(Assembler::notZero, SpinLoop);
1463
1464 bind(SpinExit);
1465 jmp(retryLabel);
1466 bind(doneRetry);
1467 incrementl(retry_count_Reg); // clear z flag
1468 }
1469
1470 // Use RTM for normal stack locks
1471 // Input: objReg (object to lock)
1472 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1473 Register retry_on_abort_count_Reg,
1474 RTMLockingCounters* stack_rtm_counters,
1475 Metadata* method_data, bool profile_rtm,
1476 Label& DONE_LABEL, Label& IsInflated) {
1477 assert(UseRTMForStackLocks, "why call this otherwise?");
1478 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1479 assert(tmpReg == rax, "");
1480 assert(scrReg == rdx, "");
1481 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1482
1483 if (RTMRetryCount > 0) {
1484 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1485 bind(L_rtm_retry);
1486 }
1487 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1488 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1489 jcc(Assembler::notZero, IsInflated);
1490
1491 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1492 Label L_noincrement;
1493 if (RTMTotalCountIncrRate > 1) {
1494 // tmpReg, scrReg and flags are killed
1495 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1496 }
1497 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1498 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1499 bind(L_noincrement);
1500 }
1501 xbegin(L_on_abort);
1502 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1503 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1504 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1505 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1506
1507 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1508 if (UseRTMXendForLockBusy) {
1509 xend();
1510 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1511 jmp(L_decrement_retry);
1512 }
1513 else {
1514 xabort(0);
1515 }
1516 bind(L_on_abort);
1517 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1518 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1519 }
1520 bind(L_decrement_retry);
1521 if (RTMRetryCount > 0) {
1522 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1523 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1524 }
1525 }
1526
1527 // Use RTM for inflating locks
1528 // inputs: objReg (object to lock)
1529 // boxReg (on-stack box address (displaced header location) - KILLED)
1530 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1531 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1532 Register scrReg, Register retry_on_busy_count_Reg,
1533 Register retry_on_abort_count_Reg,
1534 RTMLockingCounters* rtm_counters,
1535 Metadata* method_data, bool profile_rtm,
1536 Label& DONE_LABEL) {
1537 assert(UseRTMLocking, "why call this otherwise?");
1538 assert(tmpReg == rax, "");
1539 assert(scrReg == rdx, "");
1540 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1541 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1542
1543 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1544 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1545 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1546
1547 if (RTMRetryCount > 0) {
1548 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1549 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1550 bind(L_rtm_retry);
1551 }
1552 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1553 Label L_noincrement;
1554 if (RTMTotalCountIncrRate > 1) {
1555 // tmpReg, scrReg and flags are killed
1556 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1557 }
1558 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1559 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1560 bind(L_noincrement);
1561 }
1562 xbegin(L_on_abort);
1563 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1564 movptr(tmpReg, Address(tmpReg, owner_offset));
1565 testptr(tmpReg, tmpReg);
1566 jcc(Assembler::zero, DONE_LABEL);
1567 if (UseRTMXendForLockBusy) {
1568 xend();
1569 jmp(L_decrement_retry);
1570 }
1571 else {
1572 xabort(0);
1573 }
1574 bind(L_on_abort);
1575 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1576 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1577 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1578 }
1579 if (RTMRetryCount > 0) {
1580 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1581 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1582 }
1583
1584 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1585 testptr(tmpReg, tmpReg) ;
1586 jccb(Assembler::notZero, L_decrement_retry) ;
1587
1588 // Appears unlocked - try to swing _owner from null to non-null.
1589 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1590 #ifdef _LP64
1591 Register threadReg = r15_thread;
1592 #else
1593 get_thread(scrReg);
1594 Register threadReg = scrReg;
1595 #endif
1596 if (os::is_MP()) {
1597 lock();
1598 }
1599 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1600
1601 if (RTMRetryCount > 0) {
1602 // success done else retry
1603 jccb(Assembler::equal, DONE_LABEL) ;
1604 bind(L_decrement_retry);
1605 // Spin and retry if lock is busy.
1606 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1607 }
1608 else {
1609 bind(L_decrement_retry);
1610 }
1611 }
1612
1613 #endif // INCLUDE_RTM_OPT
1614
1615 // Fast_Lock and Fast_Unlock used by C2
1616
1617 // Because the transitions from emitted code to the runtime
1618 // monitorenter/exit helper stubs are so slow it's critical that
1619 // we inline both the stack-locking fast-path and the inflated fast path.
1620 //
1621 // See also: cmpFastLock and cmpFastUnlock.
1622 //
1623 // What follows is a specialized inline transliteration of the code
1624 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1625 // another option would be to emit TrySlowEnter and TrySlowExit methods
1626 // at startup-time. These methods would accept arguments as
1627 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1628 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1629 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1630 // In practice, however, the # of lock sites is bounded and is usually small.
1631 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1632 // if the processor uses simple bimodal branch predictors keyed by EIP
1633 // Since the helper routines would be called from multiple synchronization
1634 // sites.
1635 //
1636 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1637 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1638 // to those specialized methods. That'd give us a mostly platform-independent
1639 // implementation that the JITs could optimize and inline at their pleasure.
1640 // Done correctly, the only time we'd need to cross to native could would be
1641 // to park() or unpark() threads. We'd also need a few more unsafe operators
1642 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1643 // (b) explicit barriers or fence operations.
1644 //
1645 // TODO:
1646 //
1647 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1648 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1649 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1650 // the lock operators would typically be faster than reifying Self.
1651 //
1652 // * Ideally I'd define the primitives as:
1653 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1654 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1655 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1656 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1657 // Furthermore the register assignments are overconstrained, possibly resulting in
1658 // sub-optimal code near the synchronization site.
1659 //
1660 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1661 // Alternately, use a better sp-proximity test.
1662 //
1663 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1664 // Either one is sufficient to uniquely identify a thread.
1665 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1666 //
1667 // * Intrinsify notify() and notifyAll() for the common cases where the
1668 // object is locked by the calling thread but the waitlist is empty.
1669 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1670 //
1671 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1672 // But beware of excessive branch density on AMD Opterons.
1673 //
1674 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1675 // or failure of the fast-path. If the fast-path fails then we pass
1676 // control to the slow-path, typically in C. In Fast_Lock and
1677 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1678 // will emit a conditional branch immediately after the node.
1679 // So we have branches to branches and lots of ICC.ZF games.
1680 // Instead, it might be better to have C2 pass a "FailureLabel"
1681 // into Fast_Lock and Fast_Unlock. In the case of success, control
1682 // will drop through the node. ICC.ZF is undefined at exit.
1683 // In the case of failure, the node will branch directly to the
1684 // FailureLabel
1685
1686
1687 // obj: object to lock
1688 // box: on-stack box address (displaced header location) - KILLED
1689 // rax,: tmp -- KILLED
1690 // scr: tmp -- KILLED
1691 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1692 Register scrReg, Register cx1Reg, Register cx2Reg,
1693 BiasedLockingCounters* counters,
1694 RTMLockingCounters* rtm_counters,
1695 RTMLockingCounters* stack_rtm_counters,
1696 Metadata* method_data,
1697 bool use_rtm, bool profile_rtm) {
1698 // Ensure the register assignments are disjoint
1699 assert(tmpReg == rax, "");
1700
1701 if (use_rtm) {
1702 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1703 } else {
1704 assert(cx1Reg == noreg, "");
1705 assert(cx2Reg == noreg, "");
1706 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1707 }
1708
1709 if (counters != NULL) {
1710 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1711 }
1712 if (EmitSync & 1) {
1713 // set box->dhw = markOopDesc::unused_mark()
1714 // Force all sync thru slow-path: slow_enter() and slow_exit()
1715 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1716 cmpptr (rsp, (int32_t)NULL_WORD);
1717 } else {
1718 // Possible cases that we'll encounter in fast_lock
1719 // ------------------------------------------------
1720 // * Inflated
1721 // -- unlocked
1722 // -- Locked
1723 // = by self
1724 // = by other
1725 // * biased
1726 // -- by Self
1727 // -- by other
1728 // * neutral
1729 // * stack-locked
1730 // -- by self
1731 // = sp-proximity test hits
1732 // = sp-proximity test generates false-negative
1733 // -- by other
1734 //
1735
1736 Label IsInflated, DONE_LABEL;
1737
1738 // it's stack-locked, biased or neutral
1739 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1740 // order to reduce the number of conditional branches in the most common cases.
1741 // Beware -- there's a subtle invariant that fetch of the markword
1742 // at [FETCH], below, will never observe a biased encoding (*101b).
1743 // If this invariant is not held we risk exclusion (safety) failure.
1744 if (UseBiasedLocking && !UseOptoBiasInlining) {
1745 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1746 }
1747
1748 #if INCLUDE_RTM_OPT
1749 if (UseRTMForStackLocks && use_rtm) {
1750 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1751 stack_rtm_counters, method_data, profile_rtm,
1752 DONE_LABEL, IsInflated);
1753 }
1754 #endif // INCLUDE_RTM_OPT
1755
1756 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1757 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1758 jccb(Assembler::notZero, IsInflated);
1759
1760 // Attempt stack-locking ...
1761 orptr (tmpReg, markOopDesc::unlocked_value);
1762 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1763 if (os::is_MP()) {
1764 lock();
1765 }
1766 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1767 if (counters != NULL) {
1768 cond_inc32(Assembler::equal,
1769 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1770 }
1771 jcc(Assembler::equal, DONE_LABEL); // Success
1772
1773 // Recursive locking.
1774 // The object is stack-locked: markword contains stack pointer to BasicLock.
1775 // Locked by current thread if difference with current SP is less than one page.
1776 subptr(tmpReg, rsp);
1777 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1778 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1779 movptr(Address(boxReg, 0), tmpReg);
1780 if (counters != NULL) {
1781 cond_inc32(Assembler::equal,
1782 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1783 }
1784 jmp(DONE_LABEL);
1785
1786 bind(IsInflated);
1787 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1788
1789 #if INCLUDE_RTM_OPT
1790 // Use the same RTM locking code in 32- and 64-bit VM.
1791 if (use_rtm) {
1792 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1793 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1794 } else {
1795 #endif // INCLUDE_RTM_OPT
1796
1797 #ifndef _LP64
1798 // The object is inflated.
1799
1800 // boxReg refers to the on-stack BasicLock in the current frame.
1801 // We'd like to write:
1802 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1803 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1804 // additional latency as we have another ST in the store buffer that must drain.
1805
1806 if (EmitSync & 8192) {
1807 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1808 get_thread (scrReg);
1809 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1810 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1811 if (os::is_MP()) {
1812 lock();
1813 }
1814 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1815 } else
1816 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1817 // register juggle because we need tmpReg for cmpxchgptr below
1818 movptr(scrReg, boxReg);
1819 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1820
1821 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1822 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1823 // prefetchw [eax + Offset(_owner)-2]
1824 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1825 }
1826
1827 if ((EmitSync & 64) == 0) {
1828 // Optimistic form: consider XORL tmpReg,tmpReg
1829 movptr(tmpReg, NULL_WORD);
1830 } else {
1831 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1832 // Test-And-CAS instead of CAS
1833 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1834 testptr(tmpReg, tmpReg); // Locked ?
1835 jccb (Assembler::notZero, DONE_LABEL);
1836 }
1837
1838 // Appears unlocked - try to swing _owner from null to non-null.
1839 // Ideally, I'd manifest "Self" with get_thread and then attempt
1840 // to CAS the register containing Self into m->Owner.
1841 // But we don't have enough registers, so instead we can either try to CAS
1842 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1843 // we later store "Self" into m->Owner. Transiently storing a stack address
1844 // (rsp or the address of the box) into m->owner is harmless.
1845 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1846 if (os::is_MP()) {
1847 lock();
1848 }
1849 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1850 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1851 // If we weren't able to swing _owner from NULL to the BasicLock
1852 // then take the slow path.
1853 jccb (Assembler::notZero, DONE_LABEL);
1854 // update _owner from BasicLock to thread
1855 get_thread (scrReg); // beware: clobbers ICCs
1856 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1857 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1858
1859 // If the CAS fails we can either retry or pass control to the slow-path.
1860 // We use the latter tactic.
1861 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1862 // If the CAS was successful ...
1863 // Self has acquired the lock
1864 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1865 // Intentional fall-through into DONE_LABEL ...
1866 } else {
1867 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1868 movptr(boxReg, tmpReg);
1869
1870 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1871 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1872 // prefetchw [eax + Offset(_owner)-2]
1873 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1874 }
1875
1876 if ((EmitSync & 64) == 0) {
1877 // Optimistic form
1878 xorptr (tmpReg, tmpReg);
1879 } else {
1880 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1881 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1882 testptr(tmpReg, tmpReg); // Locked ?
1883 jccb (Assembler::notZero, DONE_LABEL);
1884 }
1885
1886 // Appears unlocked - try to swing _owner from null to non-null.
1887 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1888 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1889 get_thread (scrReg);
1890 if (os::is_MP()) {
1891 lock();
1892 }
1893 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1894
1895 // If the CAS fails we can either retry or pass control to the slow-path.
1896 // We use the latter tactic.
1897 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1898 // If the CAS was successful ...
1899 // Self has acquired the lock
1900 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1901 // Intentional fall-through into DONE_LABEL ...
1902 }
1903 #else // _LP64
1904 // It's inflated
1905 movq(scrReg, tmpReg);
1906 xorq(tmpReg, tmpReg);
1907
1908 if (os::is_MP()) {
1909 lock();
1910 }
1911 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1912 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1913 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1914 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1915 // Intentional fall-through into DONE_LABEL ...
1916 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1917 #endif // _LP64
1918 #if INCLUDE_RTM_OPT
1919 } // use_rtm()
1920 #endif
1921 // DONE_LABEL is a hot target - we'd really like to place it at the
1922 // start of cache line by padding with NOPs.
1923 // See the AMD and Intel software optimization manuals for the
1924 // most efficient "long" NOP encodings.
1925 // Unfortunately none of our alignment mechanisms suffice.
1926 bind(DONE_LABEL);
1927
1928 // At DONE_LABEL the icc ZFlag is set as follows ...
1929 // Fast_Unlock uses the same protocol.
1930 // ZFlag == 1 -> Success
1931 // ZFlag == 0 -> Failure - force control through the slow-path
1932 }
1933 }
1934
1935 // obj: object to unlock
1936 // box: box address (displaced header location), killed. Must be EAX.
1937 // tmp: killed, cannot be obj nor box.
1938 //
1939 // Some commentary on balanced locking:
1940 //
1941 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1942 // Methods that don't have provably balanced locking are forced to run in the
1943 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1944 // The interpreter provides two properties:
1945 // I1: At return-time the interpreter automatically and quietly unlocks any
1946 // objects acquired the current activation (frame). Recall that the
1947 // interpreter maintains an on-stack list of locks currently held by
1948 // a frame.
1949 // I2: If a method attempts to unlock an object that is not held by the
1950 // the frame the interpreter throws IMSX.
1951 //
1952 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1953 // B() doesn't have provably balanced locking so it runs in the interpreter.
1954 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1955 // is still locked by A().
1956 //
1957 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1958 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1959 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1960 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1961 // Arguably given that the spec legislates the JNI case as undefined our implementation
1962 // could reasonably *avoid* checking owner in Fast_Unlock().
1963 // In the interest of performance we elide m->Owner==Self check in unlock.
1964 // A perfectly viable alternative is to elide the owner check except when
1965 // Xcheck:jni is enabled.
1966
1967 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1968 assert(boxReg == rax, "");
1969 assert_different_registers(objReg, boxReg, tmpReg);
1970
1971 if (EmitSync & 4) {
1972 // Disable - inhibit all inlining. Force control through the slow-path
1973 cmpptr (rsp, 0);
1974 } else {
1975 Label DONE_LABEL, Stacked, CheckSucc;
1976
1977 // Critically, the biased locking test must have precedence over
1978 // and appear before the (box->dhw == 0) recursive stack-lock test.
1979 if (UseBiasedLocking && !UseOptoBiasInlining) {
1980 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1981 }
1982
1983 #if INCLUDE_RTM_OPT
1984 if (UseRTMForStackLocks && use_rtm) {
1985 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1986 Label L_regular_unlock;
1987 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1988 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1989 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1990 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1991 xend(); // otherwise end...
1992 jmp(DONE_LABEL); // ... and we're done
1993 bind(L_regular_unlock);
1994 }
1995 #endif
1996
1997 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1998 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
1999 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
2000 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2001 jccb (Assembler::zero, Stacked);
2002
2003 // It's inflated.
2004 #if INCLUDE_RTM_OPT
2005 if (use_rtm) {
2006 Label L_regular_inflated_unlock;
2007 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2008 movptr(boxReg, Address(tmpReg, owner_offset));
2009 testptr(boxReg, boxReg);
2010 jccb(Assembler::notZero, L_regular_inflated_unlock);
2011 xend();
2012 jmpb(DONE_LABEL);
2013 bind(L_regular_inflated_unlock);
2014 }
2015 #endif
2016
2017 // Despite our balanced locking property we still check that m->_owner == Self
2018 // as java routines or native JNI code called by this thread might
2019 // have released the lock.
2020 // Refer to the comments in synchronizer.cpp for how we might encode extra
2021 // state in _succ so we can avoid fetching EntryList|cxq.
2022 //
2023 // I'd like to add more cases in fast_lock() and fast_unlock() --
2024 // such as recursive enter and exit -- but we have to be wary of
2025 // I$ bloat, T$ effects and BP$ effects.
2026 //
2027 // If there's no contention try a 1-0 exit. That is, exit without
2028 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2029 // we detect and recover from the race that the 1-0 exit admits.
2030 //
2031 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2032 // before it STs null into _owner, releasing the lock. Updates
2033 // to data protected by the critical section must be visible before
2034 // we drop the lock (and thus before any other thread could acquire
2035 // the lock and observe the fields protected by the lock).
2036 // IA32's memory-model is SPO, so STs are ordered with respect to
2037 // each other and there's no need for an explicit barrier (fence).
2038 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2039 #ifndef _LP64
2040 get_thread (boxReg);
2041 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2042 // prefetchw [ebx + Offset(_owner)-2]
2043 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2044 }
2045
2046 // Note that we could employ various encoding schemes to reduce
2047 // the number of loads below (currently 4) to just 2 or 3.
2048 // Refer to the comments in synchronizer.cpp.
2049 // In practice the chain of fetches doesn't seem to impact performance, however.
2050 xorptr(boxReg, boxReg);
2051 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2052 // Attempt to reduce branch density - AMD's branch predictor.
2053 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2054 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2055 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2056 jccb (Assembler::notZero, DONE_LABEL);
2057 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2058 jmpb (DONE_LABEL);
2059 } else {
2060 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2061 jccb (Assembler::notZero, DONE_LABEL);
2062 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2063 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2064 jccb (Assembler::notZero, CheckSucc);
2065 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2066 jmpb (DONE_LABEL);
2067 }
2068
2069 // The Following code fragment (EmitSync & 65536) improves the performance of
2070 // contended applications and contended synchronization microbenchmarks.
2071 // Unfortunately the emission of the code - even though not executed - causes regressions
2072 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2073 // with an equal number of never-executed NOPs results in the same regression.
2074 // We leave it off by default.
2075
2076 if ((EmitSync & 65536) != 0) {
2077 Label LSuccess, LGoSlowPath ;
2078
2079 bind (CheckSucc);
2080
2081 // Optional pre-test ... it's safe to elide this
2082 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2083 jccb(Assembler::zero, LGoSlowPath);
2084
2085 // We have a classic Dekker-style idiom:
2086 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2087 // There are a number of ways to implement the barrier:
2088 // (1) lock:andl &m->_owner, 0
2089 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2090 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2091 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2092 // (2) If supported, an explicit MFENCE is appealing.
2093 // In older IA32 processors MFENCE is slower than lock:add or xchg
2094 // particularly if the write-buffer is full as might be the case if
2095 // if stores closely precede the fence or fence-equivalent instruction.
2096 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2097 // as the situation has changed with Nehalem and Shanghai.
2098 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2099 // The $lines underlying the top-of-stack should be in M-state.
2100 // The locked add instruction is serializing, of course.
2101 // (4) Use xchg, which is serializing
2102 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2103 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2104 // The integer condition codes will tell us if succ was 0.
2105 // Since _succ and _owner should reside in the same $line and
2106 // we just stored into _owner, it's likely that the $line
2107 // remains in M-state for the lock:orl.
2108 //
2109 // We currently use (3), although it's likely that switching to (2)
2110 // is correct for the future.
2111
2112 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2113 if (os::is_MP()) {
2114 lock(); addptr(Address(rsp, 0), 0);
2115 }
2116 // Ratify _succ remains non-null
2117 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2118 jccb (Assembler::notZero, LSuccess);
2119
2120 xorptr(boxReg, boxReg); // box is really EAX
2121 if (os::is_MP()) { lock(); }
2122 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2123 // There's no successor so we tried to regrab the lock with the
2124 // placeholder value. If that didn't work, then another thread
2125 // grabbed the lock so we're done (and exit was a success).
2126 jccb (Assembler::notEqual, LSuccess);
2127 // Since we're low on registers we installed rsp as a placeholding in _owner.
2128 // Now install Self over rsp. This is safe as we're transitioning from
2129 // non-null to non=null
2130 get_thread (boxReg);
2131 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2132 // Intentional fall-through into LGoSlowPath ...
2133
2134 bind (LGoSlowPath);
2135 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2136 jmpb (DONE_LABEL);
2137
2138 bind (LSuccess);
2139 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2140 jmpb (DONE_LABEL);
2141 }
2142
2143 bind (Stacked);
2144 // It's not inflated and it's not recursively stack-locked and it's not biased.
2145 // It must be stack-locked.
2146 // Try to reset the header to displaced header.
2147 // The "box" value on the stack is stable, so we can reload
2148 // and be assured we observe the same value as above.
2149 movptr(tmpReg, Address(boxReg, 0));
2150 if (os::is_MP()) {
2151 lock();
2152 }
2153 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2154 // Intention fall-thru into DONE_LABEL
2155
2156 // DONE_LABEL is a hot target - we'd really like to place it at the
2157 // start of cache line by padding with NOPs.
2158 // See the AMD and Intel software optimization manuals for the
2159 // most efficient "long" NOP encodings.
2160 // Unfortunately none of our alignment mechanisms suffice.
2161 if ((EmitSync & 65536) == 0) {
2162 bind (CheckSucc);
2163 }
2164 #else // _LP64
2165 // It's inflated
2166 if (EmitSync & 1024) {
2167 // Emit code to check that _owner == Self
2168 // We could fold the _owner test into subsequent code more efficiently
2169 // than using a stand-alone check, but since _owner checking is off by
2170 // default we don't bother. We also might consider predicating the
2171 // _owner==Self check on Xcheck:jni or running on a debug build.
2172 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2173 xorptr(boxReg, r15_thread);
2174 } else {
2175 xorptr(boxReg, boxReg);
2176 }
2177 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2178 jccb (Assembler::notZero, DONE_LABEL);
2179 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2180 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2181 jccb (Assembler::notZero, CheckSucc);
2182 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2183 jmpb (DONE_LABEL);
2184
2185 if ((EmitSync & 65536) == 0) {
2186 // Try to avoid passing control into the slow_path ...
2187 Label LSuccess, LGoSlowPath ;
2188 bind (CheckSucc);
2189
2190 // The following optional optimization can be elided if necessary
2191 // Effectively: if (succ == null) goto SlowPath
2192 // The code reduces the window for a race, however,
2193 // and thus benefits performance.
2194 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2195 jccb (Assembler::zero, LGoSlowPath);
2196
2197 xorptr(boxReg, boxReg);
2198 if ((EmitSync & 16) && os::is_MP()) {
2199 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2200 } else {
2201 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2202 if (os::is_MP()) {
2203 // Memory barrier/fence
2204 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2205 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2206 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2207 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2208 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2209 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2210 lock(); addl(Address(rsp, 0), 0);
2211 }
2212 }
2213 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2214 jccb (Assembler::notZero, LSuccess);
2215
2216 // Rare inopportune interleaving - race.
2217 // The successor vanished in the small window above.
2218 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2219 // We need to ensure progress and succession.
2220 // Try to reacquire the lock.
2221 // If that fails then the new owner is responsible for succession and this
2222 // thread needs to take no further action and can exit via the fast path (success).
2223 // If the re-acquire succeeds then pass control into the slow path.
2224 // As implemented, this latter mode is horrible because we generated more
2225 // coherence traffic on the lock *and* artifically extended the critical section
2226 // length while by virtue of passing control into the slow path.
2227
2228 // box is really RAX -- the following CMPXCHG depends on that binding
2229 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2230 if (os::is_MP()) { lock(); }
2231 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2232 // There's no successor so we tried to regrab the lock.
2233 // If that didn't work, then another thread grabbed the
2234 // lock so we're done (and exit was a success).
2235 jccb (Assembler::notEqual, LSuccess);
2236 // Intentional fall-through into slow-path
2237
2238 bind (LGoSlowPath);
2239 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2240 jmpb (DONE_LABEL);
2241
2242 bind (LSuccess);
2243 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2244 jmpb (DONE_LABEL);
2245 }
2246
2247 bind (Stacked);
2248 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2249 if (os::is_MP()) { lock(); }
2250 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2251
2252 if (EmitSync & 65536) {
2253 bind (CheckSucc);
2254 }
2255 #endif
2256 bind(DONE_LABEL);
2257 }
2258 }
2259 #endif // COMPILER2
2260
2261 void MacroAssembler::c2bool(Register x) {
2262 // implements x == 0 ? 0 : 1
2263 // note: must only look at least-significant byte of x
2264 // since C-style booleans are stored in one byte
2265 // only! (was bug)
2266 andl(x, 0xFF);
2267 setb(Assembler::notZero, x);
2268 }
2269
2270 // Wouldn't need if AddressLiteral version had new name
2271 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2272 Assembler::call(L, rtype);
2273 }
2274
2275 void MacroAssembler::call(Register entry) {
2276 Assembler::call(entry);
2277 }
2278
2279 void MacroAssembler::call(AddressLiteral entry) {
2280 if (reachable(entry)) {
2281 Assembler::call_literal(entry.target(), entry.rspec());
2282 } else {
2283 lea(rscratch1, entry);
2284 Assembler::call(rscratch1);
2285 }
2286 }
2287
2288 void MacroAssembler::ic_call(address entry, jint method_index) {
2289 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2290 movptr(rax, (intptr_t)Universe::non_oop_word());
2291 call(AddressLiteral(entry, rh));
2292 }
2293
2294 // Implementation of call_VM versions
2295
2296 void MacroAssembler::call_VM(Register oop_result,
2297 address entry_point,
2298 bool check_exceptions) {
2299 Label C, E;
2300 call(C, relocInfo::none);
2301 jmp(E);
2302
2303 bind(C);
2304 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2305 ret(0);
2306
2307 bind(E);
2308 }
2309
2310 void MacroAssembler::call_VM(Register oop_result,
2311 address entry_point,
2312 Register arg_1,
2313 bool check_exceptions) {
2314 Label C, E;
2315 call(C, relocInfo::none);
2316 jmp(E);
2317
2318 bind(C);
2319 pass_arg1(this, arg_1);
2320 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2321 ret(0);
2322
2323 bind(E);
2324 }
2325
2326 void MacroAssembler::call_VM(Register oop_result,
2327 address entry_point,
2328 Register arg_1,
2329 Register arg_2,
2330 bool check_exceptions) {
2331 Label C, E;
2332 call(C, relocInfo::none);
2333 jmp(E);
2334
2335 bind(C);
2336
2337 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2338
2339 pass_arg2(this, arg_2);
2340 pass_arg1(this, arg_1);
2341 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2342 ret(0);
2343
2344 bind(E);
2345 }
2346
2347 void MacroAssembler::call_VM(Register oop_result,
2348 address entry_point,
2349 Register arg_1,
2350 Register arg_2,
2351 Register arg_3,
2352 bool check_exceptions) {
2353 Label C, E;
2354 call(C, relocInfo::none);
2355 jmp(E);
2356
2357 bind(C);
2358
2359 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2360 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2361 pass_arg3(this, arg_3);
2362
2363 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2364 pass_arg2(this, arg_2);
2365
2366 pass_arg1(this, arg_1);
2367 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2368 ret(0);
2369
2370 bind(E);
2371 }
2372
2373 void MacroAssembler::call_VM(Register oop_result,
2374 Register last_java_sp,
2375 address entry_point,
2376 int number_of_arguments,
2377 bool check_exceptions) {
2378 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2379 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2380 }
2381
2382 void MacroAssembler::call_VM(Register oop_result,
2383 Register last_java_sp,
2384 address entry_point,
2385 Register arg_1,
2386 bool check_exceptions) {
2387 pass_arg1(this, arg_1);
2388 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2389 }
2390
2391 void MacroAssembler::call_VM(Register oop_result,
2392 Register last_java_sp,
2393 address entry_point,
2394 Register arg_1,
2395 Register arg_2,
2396 bool check_exceptions) {
2397
2398 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2399 pass_arg2(this, arg_2);
2400 pass_arg1(this, arg_1);
2401 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2402 }
2403
2404 void MacroAssembler::call_VM(Register oop_result,
2405 Register last_java_sp,
2406 address entry_point,
2407 Register arg_1,
2408 Register arg_2,
2409 Register arg_3,
2410 bool check_exceptions) {
2411 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2412 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2413 pass_arg3(this, arg_3);
2414 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2415 pass_arg2(this, arg_2);
2416 pass_arg1(this, arg_1);
2417 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2418 }
2419
2420 void MacroAssembler::super_call_VM(Register oop_result,
2421 Register last_java_sp,
2422 address entry_point,
2423 int number_of_arguments,
2424 bool check_exceptions) {
2425 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2426 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2427 }
2428
2429 void MacroAssembler::super_call_VM(Register oop_result,
2430 Register last_java_sp,
2431 address entry_point,
2432 Register arg_1,
2433 bool check_exceptions) {
2434 pass_arg1(this, arg_1);
2435 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2436 }
2437
2438 void MacroAssembler::super_call_VM(Register oop_result,
2439 Register last_java_sp,
2440 address entry_point,
2441 Register arg_1,
2442 Register arg_2,
2443 bool check_exceptions) {
2444
2445 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2446 pass_arg2(this, arg_2);
2447 pass_arg1(this, arg_1);
2448 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2449 }
2450
2451 void MacroAssembler::super_call_VM(Register oop_result,
2452 Register last_java_sp,
2453 address entry_point,
2454 Register arg_1,
2455 Register arg_2,
2456 Register arg_3,
2457 bool check_exceptions) {
2458 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2459 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2460 pass_arg3(this, arg_3);
2461 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2462 pass_arg2(this, arg_2);
2463 pass_arg1(this, arg_1);
2464 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2465 }
2466
2467 void MacroAssembler::call_VM_base(Register oop_result,
2468 Register java_thread,
2469 Register last_java_sp,
2470 address entry_point,
2471 int number_of_arguments,
2472 bool check_exceptions) {
2473 // determine java_thread register
2474 if (!java_thread->is_valid()) {
2475 #ifdef _LP64
2476 java_thread = r15_thread;
2477 #else
2478 java_thread = rdi;
2479 get_thread(java_thread);
2480 #endif // LP64
2481 }
2482 // determine last_java_sp register
2483 if (!last_java_sp->is_valid()) {
2484 last_java_sp = rsp;
2485 }
2486 // debugging support
2487 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2488 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2489 #ifdef ASSERT
2490 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2491 // r12 is the heapbase.
2492 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2493 #endif // ASSERT
2494
2495 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2496 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2497
2498 // push java thread (becomes first argument of C function)
2499
2500 NOT_LP64(push(java_thread); number_of_arguments++);
2501 LP64_ONLY(mov(c_rarg0, r15_thread));
2502
2503 // set last Java frame before call
2504 assert(last_java_sp != rbp, "can't use ebp/rbp");
2505
2506 // Only interpreter should have to set fp
2507 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2508
2509 // do the call, remove parameters
2510 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2511
2512 // restore the thread (cannot use the pushed argument since arguments
2513 // may be overwritten by C code generated by an optimizing compiler);
2514 // however can use the register value directly if it is callee saved.
2515 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2516 // rdi & rsi (also r15) are callee saved -> nothing to do
2517 #ifdef ASSERT
2518 guarantee(java_thread != rax, "change this code");
2519 push(rax);
2520 { Label L;
2521 get_thread(rax);
2522 cmpptr(java_thread, rax);
2523 jcc(Assembler::equal, L);
2524 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2525 bind(L);
2526 }
2527 pop(rax);
2528 #endif
2529 } else {
2530 get_thread(java_thread);
2531 }
2532 // reset last Java frame
2533 // Only interpreter should have to clear fp
2534 reset_last_Java_frame(java_thread, true);
2535
2536 // C++ interp handles this in the interpreter
2537 check_and_handle_popframe(java_thread);
2538 check_and_handle_earlyret(java_thread);
2539
2540 if (check_exceptions) {
2541 // check for pending exceptions (java_thread is set upon return)
2542 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2543 #ifndef _LP64
2544 jump_cc(Assembler::notEqual,
2545 RuntimeAddress(StubRoutines::forward_exception_entry()));
2546 #else
2547 // This used to conditionally jump to forward_exception however it is
2548 // possible if we relocate that the branch will not reach. So we must jump
2549 // around so we can always reach
2550
2551 Label ok;
2552 jcc(Assembler::equal, ok);
2553 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2554 bind(ok);
2555 #endif // LP64
2556 }
2557
2558 // get oop result if there is one and reset the value in the thread
2559 if (oop_result->is_valid()) {
2560 get_vm_result(oop_result, java_thread);
2561 }
2562 }
2563
2564 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2565
2566 // Calculate the value for last_Java_sp
2567 // somewhat subtle. call_VM does an intermediate call
2568 // which places a return address on the stack just under the
2569 // stack pointer as the user finsihed with it. This allows
2570 // use to retrieve last_Java_pc from last_Java_sp[-1].
2571 // On 32bit we then have to push additional args on the stack to accomplish
2572 // the actual requested call. On 64bit call_VM only can use register args
2573 // so the only extra space is the return address that call_VM created.
2574 // This hopefully explains the calculations here.
2575
2576 #ifdef _LP64
2577 // We've pushed one address, correct last_Java_sp
2578 lea(rax, Address(rsp, wordSize));
2579 #else
2580 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2581 #endif // LP64
2582
2583 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2584
2585 }
2586
2587 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2588 void MacroAssembler::call_VM_leaf0(address entry_point) {
2589 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2590 }
2591
2592 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2593 call_VM_leaf_base(entry_point, number_of_arguments);
2594 }
2595
2596 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2597 pass_arg0(this, arg_0);
2598 call_VM_leaf(entry_point, 1);
2599 }
2600
2601 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2602
2603 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2604 pass_arg1(this, arg_1);
2605 pass_arg0(this, arg_0);
2606 call_VM_leaf(entry_point, 2);
2607 }
2608
2609 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2610 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2611 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2612 pass_arg2(this, arg_2);
2613 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2614 pass_arg1(this, arg_1);
2615 pass_arg0(this, arg_0);
2616 call_VM_leaf(entry_point, 3);
2617 }
2618
2619 void MacroAssembler::super_call_VM_leaf(address entry_point) {
2620 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2621 }
2622
2623 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2624 pass_arg0(this, arg_0);
2625 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2626 }
2627
2628 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2629
2630 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2631 pass_arg1(this, arg_1);
2632 pass_arg0(this, arg_0);
2633 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2634 }
2635
2636 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2637 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2638 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2639 pass_arg2(this, arg_2);
2640 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2641 pass_arg1(this, arg_1);
2642 pass_arg0(this, arg_0);
2643 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2644 }
2645
2646 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2647 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2648 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2649 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2650 pass_arg3(this, arg_3);
2651 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2652 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2653 pass_arg2(this, arg_2);
2654 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2655 pass_arg1(this, arg_1);
2656 pass_arg0(this, arg_0);
2657 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2658 }
2659
2660 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2661 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2662 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2663 verify_oop(oop_result, "broken oop in call_VM_base");
2664 }
2665
2666 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2667 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2668 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2669 }
2670
2671 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2672 }
2673
2674 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2675 }
2676
2677 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2678 if (reachable(src1)) {
2679 cmpl(as_Address(src1), imm);
2680 } else {
2681 lea(rscratch1, src1);
2682 cmpl(Address(rscratch1, 0), imm);
2683 }
2684 }
2685
2686 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2687 assert(!src2.is_lval(), "use cmpptr");
2688 if (reachable(src2)) {
2689 cmpl(src1, as_Address(src2));
2690 } else {
2691 lea(rscratch1, src2);
2692 cmpl(src1, Address(rscratch1, 0));
2693 }
2694 }
2695
2696 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2697 Assembler::cmpl(src1, imm);
2698 }
2699
2700 void MacroAssembler::cmp32(Register src1, Address src2) {
2701 Assembler::cmpl(src1, src2);
2702 }
2703
2704 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2705 ucomisd(opr1, opr2);
2706
2707 Label L;
2708 if (unordered_is_less) {
2709 movl(dst, -1);
2710 jcc(Assembler::parity, L);
2711 jcc(Assembler::below , L);
2712 movl(dst, 0);
2713 jcc(Assembler::equal , L);
2714 increment(dst);
2715 } else { // unordered is greater
2716 movl(dst, 1);
2717 jcc(Assembler::parity, L);
2718 jcc(Assembler::above , L);
2719 movl(dst, 0);
2720 jcc(Assembler::equal , L);
2721 decrementl(dst);
2722 }
2723 bind(L);
2724 }
2725
2726 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2727 ucomiss(opr1, opr2);
2728
2729 Label L;
2730 if (unordered_is_less) {
2731 movl(dst, -1);
2732 jcc(Assembler::parity, L);
2733 jcc(Assembler::below , L);
2734 movl(dst, 0);
2735 jcc(Assembler::equal , L);
2736 increment(dst);
2737 } else { // unordered is greater
2738 movl(dst, 1);
2739 jcc(Assembler::parity, L);
2740 jcc(Assembler::above , L);
2741 movl(dst, 0);
2742 jcc(Assembler::equal , L);
2743 decrementl(dst);
2744 }
2745 bind(L);
2746 }
2747
2748
2749 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2750 if (reachable(src1)) {
2751 cmpb(as_Address(src1), imm);
2752 } else {
2753 lea(rscratch1, src1);
2754 cmpb(Address(rscratch1, 0), imm);
2755 }
2756 }
2757
2758 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2759 #ifdef _LP64
2760 if (src2.is_lval()) {
2761 movptr(rscratch1, src2);
2762 Assembler::cmpq(src1, rscratch1);
2763 } else if (reachable(src2)) {
2764 cmpq(src1, as_Address(src2));
2765 } else {
2766 lea(rscratch1, src2);
2767 Assembler::cmpq(src1, Address(rscratch1, 0));
2768 }
2769 #else
2770 if (src2.is_lval()) {
2771 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2772 } else {
2773 cmpl(src1, as_Address(src2));
2774 }
2775 #endif // _LP64
2776 }
2777
2778 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2779 assert(src2.is_lval(), "not a mem-mem compare");
2780 #ifdef _LP64
2781 // moves src2's literal address
2782 movptr(rscratch1, src2);
2783 Assembler::cmpq(src1, rscratch1);
2784 #else
2785 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2786 #endif // _LP64
2787 }
2788
2789 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2790 if (reachable(adr)) {
2791 if (os::is_MP())
2792 lock();
2793 cmpxchgptr(reg, as_Address(adr));
2794 } else {
2795 lea(rscratch1, adr);
2796 if (os::is_MP())
2797 lock();
2798 cmpxchgptr(reg, Address(rscratch1, 0));
2799 }
2800 }
2801
2802 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2803 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2804 }
2805
2806 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2807 if (reachable(src)) {
2808 Assembler::comisd(dst, as_Address(src));
2809 } else {
2810 lea(rscratch1, src);
2811 Assembler::comisd(dst, Address(rscratch1, 0));
2812 }
2813 }
2814
2815 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2816 if (reachable(src)) {
2817 Assembler::comiss(dst, as_Address(src));
2818 } else {
2819 lea(rscratch1, src);
2820 Assembler::comiss(dst, Address(rscratch1, 0));
2821 }
2822 }
2823
2824
2825 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2826 Condition negated_cond = negate_condition(cond);
2827 Label L;
2828 jcc(negated_cond, L);
2829 pushf(); // Preserve flags
2830 atomic_incl(counter_addr);
2831 popf();
2832 bind(L);
2833 }
2834
2835 int MacroAssembler::corrected_idivl(Register reg) {
2836 // Full implementation of Java idiv and irem; checks for
2837 // special case as described in JVM spec., p.243 & p.271.
2838 // The function returns the (pc) offset of the idivl
2839 // instruction - may be needed for implicit exceptions.
2840 //
2841 // normal case special case
2842 //
2843 // input : rax,: dividend min_int
2844 // reg: divisor (may not be rax,/rdx) -1
2845 //
2846 // output: rax,: quotient (= rax, idiv reg) min_int
2847 // rdx: remainder (= rax, irem reg) 0
2848 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2849 const int min_int = 0x80000000;
2850 Label normal_case, special_case;
2851
2852 // check for special case
2853 cmpl(rax, min_int);
2854 jcc(Assembler::notEqual, normal_case);
2855 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2856 cmpl(reg, -1);
2857 jcc(Assembler::equal, special_case);
2858
2859 // handle normal case
2860 bind(normal_case);
2861 cdql();
2862 int idivl_offset = offset();
2863 idivl(reg);
2864
2865 // normal and special case exit
2866 bind(special_case);
2867
2868 return idivl_offset;
2869 }
2870
2871
2872
2873 void MacroAssembler::decrementl(Register reg, int value) {
2874 if (value == min_jint) {subl(reg, value) ; return; }
2875 if (value < 0) { incrementl(reg, -value); return; }
2876 if (value == 0) { ; return; }
2877 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2878 /* else */ { subl(reg, value) ; return; }
2879 }
2880
2881 void MacroAssembler::decrementl(Address dst, int value) {
2882 if (value == min_jint) {subl(dst, value) ; return; }
2883 if (value < 0) { incrementl(dst, -value); return; }
2884 if (value == 0) { ; return; }
2885 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2886 /* else */ { subl(dst, value) ; return; }
2887 }
2888
2889 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2890 assert (shift_value > 0, "illegal shift value");
2891 Label _is_positive;
2892 testl (reg, reg);
2893 jcc (Assembler::positive, _is_positive);
2894 int offset = (1 << shift_value) - 1 ;
2895
2896 if (offset == 1) {
2897 incrementl(reg);
2898 } else {
2899 addl(reg, offset);
2900 }
2901
2902 bind (_is_positive);
2903 sarl(reg, shift_value);
2904 }
2905
2906 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2907 if (reachable(src)) {
2908 Assembler::divsd(dst, as_Address(src));
2909 } else {
2910 lea(rscratch1, src);
2911 Assembler::divsd(dst, Address(rscratch1, 0));
2912 }
2913 }
2914
2915 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2916 if (reachable(src)) {
2917 Assembler::divss(dst, as_Address(src));
2918 } else {
2919 lea(rscratch1, src);
2920 Assembler::divss(dst, Address(rscratch1, 0));
2921 }
2922 }
2923
2924 // !defined(COMPILER2) is because of stupid core builds
2925 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2926 void MacroAssembler::empty_FPU_stack() {
2927 if (VM_Version::supports_mmx()) {
2928 emms();
2929 } else {
2930 for (int i = 8; i-- > 0; ) ffree(i);
2931 }
2932 }
2933 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2934
2935
2936 // Defines obj, preserves var_size_in_bytes
2937 void MacroAssembler::eden_allocate(Register obj,
2938 Register var_size_in_bytes,
2939 int con_size_in_bytes,
2940 Register t1,
2941 Label& slow_case) {
2942 assert(obj == rax, "obj must be in rax, for cmpxchg");
2943 assert_different_registers(obj, var_size_in_bytes, t1);
2944 if (!Universe::heap()->supports_inline_contig_alloc()) {
2945 jmp(slow_case);
2946 } else {
2947 Register end = t1;
2948 Label retry;
2949 bind(retry);
2950 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2951 movptr(obj, heap_top);
2952 if (var_size_in_bytes == noreg) {
2953 lea(end, Address(obj, con_size_in_bytes));
2954 } else {
2955 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2956 }
2957 // if end < obj then we wrapped around => object too long => slow case
2958 cmpptr(end, obj);
2959 jcc(Assembler::below, slow_case);
2960 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2961 jcc(Assembler::above, slow_case);
2962 // Compare obj with the top addr, and if still equal, store the new top addr in
2963 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2964 // it otherwise. Use lock prefix for atomicity on MPs.
2965 locked_cmpxchgptr(end, heap_top);
2966 jcc(Assembler::notEqual, retry);
2967 }
2968 }
2969
2970 void MacroAssembler::enter() {
2971 push(rbp);
2972 mov(rbp, rsp);
2973 }
2974
2975 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2976 void MacroAssembler::fat_nop() {
2977 if (UseAddressNop) {
2978 addr_nop_5();
2979 } else {
2980 emit_int8(0x26); // es:
2981 emit_int8(0x2e); // cs:
2982 emit_int8(0x64); // fs:
2983 emit_int8(0x65); // gs:
2984 emit_int8((unsigned char)0x90);
2985 }
2986 }
2987
2988 void MacroAssembler::fcmp(Register tmp) {
2989 fcmp(tmp, 1, true, true);
2990 }
2991
2992 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2993 assert(!pop_right || pop_left, "usage error");
2994 if (VM_Version::supports_cmov()) {
2995 assert(tmp == noreg, "unneeded temp");
2996 if (pop_left) {
2997 fucomip(index);
2998 } else {
2999 fucomi(index);
3000 }
3001 if (pop_right) {
3002 fpop();
3003 }
3004 } else {
3005 assert(tmp != noreg, "need temp");
3006 if (pop_left) {
3007 if (pop_right) {
3008 fcompp();
3009 } else {
3010 fcomp(index);
3011 }
3012 } else {
3013 fcom(index);
3014 }
3015 // convert FPU condition into eflags condition via rax,
3016 save_rax(tmp);
3017 fwait(); fnstsw_ax();
3018 sahf();
3019 restore_rax(tmp);
3020 }
3021 // condition codes set as follows:
3022 //
3023 // CF (corresponds to C0) if x < y
3024 // PF (corresponds to C2) if unordered
3025 // ZF (corresponds to C3) if x = y
3026 }
3027
3028 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3029 fcmp2int(dst, unordered_is_less, 1, true, true);
3030 }
3031
3032 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3033 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3034 Label L;
3035 if (unordered_is_less) {
3036 movl(dst, -1);
3037 jcc(Assembler::parity, L);
3038 jcc(Assembler::below , L);
3039 movl(dst, 0);
3040 jcc(Assembler::equal , L);
3041 increment(dst);
3042 } else { // unordered is greater
3043 movl(dst, 1);
3044 jcc(Assembler::parity, L);
3045 jcc(Assembler::above , L);
3046 movl(dst, 0);
3047 jcc(Assembler::equal , L);
3048 decrementl(dst);
3049 }
3050 bind(L);
3051 }
3052
3053 void MacroAssembler::fld_d(AddressLiteral src) {
3054 fld_d(as_Address(src));
3055 }
3056
3057 void MacroAssembler::fld_s(AddressLiteral src) {
3058 fld_s(as_Address(src));
3059 }
3060
3061 void MacroAssembler::fld_x(AddressLiteral src) {
3062 Assembler::fld_x(as_Address(src));
3063 }
3064
3065 void MacroAssembler::fldcw(AddressLiteral src) {
3066 Assembler::fldcw(as_Address(src));
3067 }
3068
3069 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3070 if (reachable(src)) {
3071 Assembler::mulpd(dst, as_Address(src));
3072 } else {
3073 lea(rscratch1, src);
3074 Assembler::mulpd(dst, Address(rscratch1, 0));
3075 }
3076 }
3077
3078 void MacroAssembler::increase_precision() {
3079 subptr(rsp, BytesPerWord);
3080 fnstcw(Address(rsp, 0));
3081 movl(rax, Address(rsp, 0));
3082 orl(rax, 0x300);
3083 push(rax);
3084 fldcw(Address(rsp, 0));
3085 pop(rax);
3086 }
3087
3088 void MacroAssembler::restore_precision() {
3089 fldcw(Address(rsp, 0));
3090 addptr(rsp, BytesPerWord);
3091 }
3092
3093 void MacroAssembler::fpop() {
3094 ffree();
3095 fincstp();
3096 }
3097
3098 void MacroAssembler::load_float(Address src) {
3099 if (UseSSE >= 1) {
3100 movflt(xmm0, src);
3101 } else {
3102 LP64_ONLY(ShouldNotReachHere());
3103 NOT_LP64(fld_s(src));
3104 }
3105 }
3106
3107 void MacroAssembler::store_float(Address dst) {
3108 if (UseSSE >= 1) {
3109 movflt(dst, xmm0);
3110 } else {
3111 LP64_ONLY(ShouldNotReachHere());
3112 NOT_LP64(fstp_s(dst));
3113 }
3114 }
3115
3116 void MacroAssembler::load_double(Address src) {
3117 if (UseSSE >= 2) {
3118 movdbl(xmm0, src);
3119 } else {
3120 LP64_ONLY(ShouldNotReachHere());
3121 NOT_LP64(fld_d(src));
3122 }
3123 }
3124
3125 void MacroAssembler::store_double(Address dst) {
3126 if (UseSSE >= 2) {
3127 movdbl(dst, xmm0);
3128 } else {
3129 LP64_ONLY(ShouldNotReachHere());
3130 NOT_LP64(fstp_d(dst));
3131 }
3132 }
3133
3134 void MacroAssembler::fremr(Register tmp) {
3135 save_rax(tmp);
3136 { Label L;
3137 bind(L);
3138 fprem();
3139 fwait(); fnstsw_ax();
3140 #ifdef _LP64
3141 testl(rax, 0x400);
3142 jcc(Assembler::notEqual, L);
3143 #else
3144 sahf();
3145 jcc(Assembler::parity, L);
3146 #endif // _LP64
3147 }
3148 restore_rax(tmp);
3149 // Result is in ST0.
3150 // Note: fxch & fpop to get rid of ST1
3151 // (otherwise FPU stack could overflow eventually)
3152 fxch(1);
3153 fpop();
3154 }
3155
3156 // dst = c = a * b + c
3157 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3158 Assembler::vfmadd231sd(c, a, b);
3159 if (dst != c) {
3160 movdbl(dst, c);
3161 }
3162 }
3163
3164 // dst = c = a * b + c
3165 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3166 Assembler::vfmadd231ss(c, a, b);
3167 if (dst != c) {
3168 movflt(dst, c);
3169 }
3170 }
3171
3172
3173
3174
3175 void MacroAssembler::incrementl(AddressLiteral dst) {
3176 if (reachable(dst)) {
3177 incrementl(as_Address(dst));
3178 } else {
3179 lea(rscratch1, dst);
3180 incrementl(Address(rscratch1, 0));
3181 }
3182 }
3183
3184 void MacroAssembler::incrementl(ArrayAddress dst) {
3185 incrementl(as_Address(dst));
3186 }
3187
3188 void MacroAssembler::incrementl(Register reg, int value) {
3189 if (value == min_jint) {addl(reg, value) ; return; }
3190 if (value < 0) { decrementl(reg, -value); return; }
3191 if (value == 0) { ; return; }
3192 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3193 /* else */ { addl(reg, value) ; return; }
3194 }
3195
3196 void MacroAssembler::incrementl(Address dst, int value) {
3197 if (value == min_jint) {addl(dst, value) ; return; }
3198 if (value < 0) { decrementl(dst, -value); return; }
3199 if (value == 0) { ; return; }
3200 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3201 /* else */ { addl(dst, value) ; return; }
3202 }
3203
3204 void MacroAssembler::jump(AddressLiteral dst) {
3205 if (reachable(dst)) {
3206 jmp_literal(dst.target(), dst.rspec());
3207 } else {
3208 lea(rscratch1, dst);
3209 jmp(rscratch1);
3210 }
3211 }
3212
3213 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3214 if (reachable(dst)) {
3215 InstructionMark im(this);
3216 relocate(dst.reloc());
3217 const int short_size = 2;
3218 const int long_size = 6;
3219 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3220 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3221 // 0111 tttn #8-bit disp
3222 emit_int8(0x70 | cc);
3223 emit_int8((offs - short_size) & 0xFF);
3224 } else {
3225 // 0000 1111 1000 tttn #32-bit disp
3226 emit_int8(0x0F);
3227 emit_int8((unsigned char)(0x80 | cc));
3228 emit_int32(offs - long_size);
3229 }
3230 } else {
3231 #ifdef ASSERT
3232 warning("reversing conditional branch");
3233 #endif /* ASSERT */
3234 Label skip;
3235 jccb(reverse[cc], skip);
3236 lea(rscratch1, dst);
3237 Assembler::jmp(rscratch1);
3238 bind(skip);
3239 }
3240 }
3241
3242 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3243 if (reachable(src)) {
3244 Assembler::ldmxcsr(as_Address(src));
3245 } else {
3246 lea(rscratch1, src);
3247 Assembler::ldmxcsr(Address(rscratch1, 0));
3248 }
3249 }
3250
3251 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3252 int off;
3253 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3254 off = offset();
3255 movsbl(dst, src); // movsxb
3256 } else {
3257 off = load_unsigned_byte(dst, src);
3258 shll(dst, 24);
3259 sarl(dst, 24);
3260 }
3261 return off;
3262 }
3263
3264 // Note: load_signed_short used to be called load_signed_word.
3265 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3266 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3267 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3268 int MacroAssembler::load_signed_short(Register dst, Address src) {
3269 int off;
3270 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3271 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3272 // version but this is what 64bit has always done. This seems to imply
3273 // that users are only using 32bits worth.
3274 off = offset();
3275 movswl(dst, src); // movsxw
3276 } else {
3277 off = load_unsigned_short(dst, src);
3278 shll(dst, 16);
3279 sarl(dst, 16);
3280 }
3281 return off;
3282 }
3283
3284 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3285 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3286 // and "3.9 Partial Register Penalties", p. 22).
3287 int off;
3288 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3289 off = offset();
3290 movzbl(dst, src); // movzxb
3291 } else {
3292 xorl(dst, dst);
3293 off = offset();
3294 movb(dst, src);
3295 }
3296 return off;
3297 }
3298
3299 // Note: load_unsigned_short used to be called load_unsigned_word.
3300 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3301 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3302 // and "3.9 Partial Register Penalties", p. 22).
3303 int off;
3304 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3305 off = offset();
3306 movzwl(dst, src); // movzxw
3307 } else {
3308 xorl(dst, dst);
3309 off = offset();
3310 movw(dst, src);
3311 }
3312 return off;
3313 }
3314
3315 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3316 switch (size_in_bytes) {
3317 #ifndef _LP64
3318 case 8:
3319 assert(dst2 != noreg, "second dest register required");
3320 movl(dst, src);
3321 movl(dst2, src.plus_disp(BytesPerInt));
3322 break;
3323 #else
3324 case 8: movq(dst, src); break;
3325 #endif
3326 case 4: movl(dst, src); break;
3327 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3328 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3329 default: ShouldNotReachHere();
3330 }
3331 }
3332
3333 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3334 switch (size_in_bytes) {
3335 #ifndef _LP64
3336 case 8:
3337 assert(src2 != noreg, "second source register required");
3338 movl(dst, src);
3339 movl(dst.plus_disp(BytesPerInt), src2);
3340 break;
3341 #else
3342 case 8: movq(dst, src); break;
3343 #endif
3344 case 4: movl(dst, src); break;
3345 case 2: movw(dst, src); break;
3346 case 1: movb(dst, src); break;
3347 default: ShouldNotReachHere();
3348 }
3349 }
3350
3351 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3352 if (reachable(dst)) {
3353 movl(as_Address(dst), src);
3354 } else {
3355 lea(rscratch1, dst);
3356 movl(Address(rscratch1, 0), src);
3357 }
3358 }
3359
3360 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3361 if (reachable(src)) {
3362 movl(dst, as_Address(src));
3363 } else {
3364 lea(rscratch1, src);
3365 movl(dst, Address(rscratch1, 0));
3366 }
3367 }
3368
3369 // C++ bool manipulation
3370
3371 void MacroAssembler::movbool(Register dst, Address src) {
3372 if(sizeof(bool) == 1)
3373 movb(dst, src);
3374 else if(sizeof(bool) == 2)
3375 movw(dst, src);
3376 else if(sizeof(bool) == 4)
3377 movl(dst, src);
3378 else
3379 // unsupported
3380 ShouldNotReachHere();
3381 }
3382
3383 void MacroAssembler::movbool(Address dst, bool boolconst) {
3384 if(sizeof(bool) == 1)
3385 movb(dst, (int) boolconst);
3386 else if(sizeof(bool) == 2)
3387 movw(dst, (int) boolconst);
3388 else if(sizeof(bool) == 4)
3389 movl(dst, (int) boolconst);
3390 else
3391 // unsupported
3392 ShouldNotReachHere();
3393 }
3394
3395 void MacroAssembler::movbool(Address dst, Register src) {
3396 if(sizeof(bool) == 1)
3397 movb(dst, src);
3398 else if(sizeof(bool) == 2)
3399 movw(dst, src);
3400 else if(sizeof(bool) == 4)
3401 movl(dst, src);
3402 else
3403 // unsupported
3404 ShouldNotReachHere();
3405 }
3406
3407 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3408 movb(as_Address(dst), src);
3409 }
3410
3411 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3412 if (reachable(src)) {
3413 movdl(dst, as_Address(src));
3414 } else {
3415 lea(rscratch1, src);
3416 movdl(dst, Address(rscratch1, 0));
3417 }
3418 }
3419
3420 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3421 if (reachable(src)) {
3422 movq(dst, as_Address(src));
3423 } else {
3424 lea(rscratch1, src);
3425 movq(dst, Address(rscratch1, 0));
3426 }
3427 }
3428
3429 void MacroAssembler::setvectmask(Register dst, Register src) {
3430 Assembler::movl(dst, 1);
3431 Assembler::shlxl(dst, dst, src);
3432 Assembler::decl(dst);
3433 Assembler::kmovdl(k1, dst);
3434 Assembler::movl(dst, src);
3435 }
3436
3437 void MacroAssembler::restorevectmask() {
3438 Assembler::knotwl(k1, k0);
3439 }
3440
3441 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3442 if (reachable(src)) {
3443 if (UseXmmLoadAndClearUpper) {
3444 movsd (dst, as_Address(src));
3445 } else {
3446 movlpd(dst, as_Address(src));
3447 }
3448 } else {
3449 lea(rscratch1, src);
3450 if (UseXmmLoadAndClearUpper) {
3451 movsd (dst, Address(rscratch1, 0));
3452 } else {
3453 movlpd(dst, Address(rscratch1, 0));
3454 }
3455 }
3456 }
3457
3458 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3459 if (reachable(src)) {
3460 movss(dst, as_Address(src));
3461 } else {
3462 lea(rscratch1, src);
3463 movss(dst, Address(rscratch1, 0));
3464 }
3465 }
3466
3467 void MacroAssembler::movptr(Register dst, Register src) {
3468 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3469 }
3470
3471 void MacroAssembler::movptr(Register dst, Address src) {
3472 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3473 }
3474
3475 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3476 void MacroAssembler::movptr(Register dst, intptr_t src) {
3477 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3478 }
3479
3480 void MacroAssembler::movptr(Address dst, Register src) {
3481 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3482 }
3483
3484 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3485 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3486 Assembler::vextractf32x4(dst, src, 0);
3487 } else {
3488 Assembler::movdqu(dst, src);
3489 }
3490 }
3491
3492 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3493 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3494 Assembler::vinsertf32x4(dst, dst, src, 0);
3495 } else {
3496 Assembler::movdqu(dst, src);
3497 }
3498 }
3499
3500 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3501 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3502 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3503 } else {
3504 Assembler::movdqu(dst, src);
3505 }
3506 }
3507
3508 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3509 if (reachable(src)) {
3510 movdqu(dst, as_Address(src));
3511 } else {
3512 lea(scratchReg, src);
3513 movdqu(dst, Address(scratchReg, 0));
3514 }
3515 }
3516
3517 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3518 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3519 vextractf64x4_low(dst, src);
3520 } else {
3521 Assembler::vmovdqu(dst, src);
3522 }
3523 }
3524
3525 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3526 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3527 vinsertf64x4_low(dst, src);
3528 } else {
3529 Assembler::vmovdqu(dst, src);
3530 }
3531 }
3532
3533 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3534 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3535 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3536 }
3537 else {
3538 Assembler::vmovdqu(dst, src);
3539 }
3540 }
3541
3542 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3543 if (reachable(src)) {
3544 vmovdqu(dst, as_Address(src));
3545 }
3546 else {
3547 lea(rscratch1, src);
3548 vmovdqu(dst, Address(rscratch1, 0));
3549 }
3550 }
3551
3552 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3553 if (reachable(src)) {
3554 Assembler::movdqa(dst, as_Address(src));
3555 } else {
3556 lea(rscratch1, src);
3557 Assembler::movdqa(dst, Address(rscratch1, 0));
3558 }
3559 }
3560
3561 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3562 if (reachable(src)) {
3563 Assembler::movsd(dst, as_Address(src));
3564 } else {
3565 lea(rscratch1, src);
3566 Assembler::movsd(dst, Address(rscratch1, 0));
3567 }
3568 }
3569
3570 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3571 if (reachable(src)) {
3572 Assembler::movss(dst, as_Address(src));
3573 } else {
3574 lea(rscratch1, src);
3575 Assembler::movss(dst, Address(rscratch1, 0));
3576 }
3577 }
3578
3579 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3580 if (reachable(src)) {
3581 Assembler::mulsd(dst, as_Address(src));
3582 } else {
3583 lea(rscratch1, src);
3584 Assembler::mulsd(dst, Address(rscratch1, 0));
3585 }
3586 }
3587
3588 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3589 if (reachable(src)) {
3590 Assembler::mulss(dst, as_Address(src));
3591 } else {
3592 lea(rscratch1, src);
3593 Assembler::mulss(dst, Address(rscratch1, 0));
3594 }
3595 }
3596
3597 void MacroAssembler::null_check(Register reg, int offset) {
3598 if (needs_explicit_null_check(offset)) {
3599 // provoke OS NULL exception if reg = NULL by
3600 // accessing M[reg] w/o changing any (non-CC) registers
3601 // NOTE: cmpl is plenty here to provoke a segv
3602 cmpptr(rax, Address(reg, 0));
3603 // Note: should probably use testl(rax, Address(reg, 0));
3604 // may be shorter code (however, this version of
3605 // testl needs to be implemented first)
3606 } else {
3607 // nothing to do, (later) access of M[reg + offset]
3608 // will provoke OS NULL exception if reg = NULL
3609 }
3610 }
3611
3612 void MacroAssembler::os_breakpoint() {
3613 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3614 // (e.g., MSVC can't call ps() otherwise)
3615 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3616 }
3617
3618 #ifdef _LP64
3619 #define XSTATE_BV 0x200
3620 #endif
3621
3622 void MacroAssembler::pop_CPU_state() {
3623 pop_FPU_state();
3624 pop_IU_state();
3625 }
3626
3627 void MacroAssembler::pop_FPU_state() {
3628 #ifndef _LP64
3629 frstor(Address(rsp, 0));
3630 #else
3631 fxrstor(Address(rsp, 0));
3632 #endif
3633 addptr(rsp, FPUStateSizeInWords * wordSize);
3634 }
3635
3636 void MacroAssembler::pop_IU_state() {
3637 popa();
3638 LP64_ONLY(addq(rsp, 8));
3639 popf();
3640 }
3641
3642 // Save Integer and Float state
3643 // Warning: Stack must be 16 byte aligned (64bit)
3644 void MacroAssembler::push_CPU_state() {
3645 push_IU_state();
3646 push_FPU_state();
3647 }
3648
3649 void MacroAssembler::push_FPU_state() {
3650 subptr(rsp, FPUStateSizeInWords * wordSize);
3651 #ifndef _LP64
3652 fnsave(Address(rsp, 0));
3653 fwait();
3654 #else
3655 fxsave(Address(rsp, 0));
3656 #endif // LP64
3657 }
3658
3659 void MacroAssembler::push_IU_state() {
3660 // Push flags first because pusha kills them
3661 pushf();
3662 // Make sure rsp stays 16-byte aligned
3663 LP64_ONLY(subq(rsp, 8));
3664 pusha();
3665 }
3666
3667 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3668 if (!java_thread->is_valid()) {
3669 java_thread = rdi;
3670 get_thread(java_thread);
3671 }
3672 // we must set sp to zero to clear frame
3673 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3674 if (clear_fp) {
3675 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3676 }
3677
3678 // Always clear the pc because it could have been set by make_walkable()
3679 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3680
3681 vzeroupper();
3682 }
3683
3684 void MacroAssembler::restore_rax(Register tmp) {
3685 if (tmp == noreg) pop(rax);
3686 else if (tmp != rax) mov(rax, tmp);
3687 }
3688
3689 void MacroAssembler::round_to(Register reg, int modulus) {
3690 addptr(reg, modulus - 1);
3691 andptr(reg, -modulus);
3692 }
3693
3694 void MacroAssembler::save_rax(Register tmp) {
3695 if (tmp == noreg) push(rax);
3696 else if (tmp != rax) mov(tmp, rax);
3697 }
3698
3699 // Write serialization page so VM thread can do a pseudo remote membar.
3700 // We use the current thread pointer to calculate a thread specific
3701 // offset to write to within the page. This minimizes bus traffic
3702 // due to cache line collision.
3703 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3704 movl(tmp, thread);
3705 shrl(tmp, os::get_serialize_page_shift_count());
3706 andl(tmp, (os::vm_page_size() - sizeof(int)));
3707
3708 Address index(noreg, tmp, Address::times_1);
3709 ExternalAddress page(os::get_memory_serialize_page());
3710
3711 // Size of store must match masking code above
3712 movl(as_Address(ArrayAddress(page, index)), tmp);
3713 }
3714
3715 // Calls to C land
3716 //
3717 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3718 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3719 // has to be reset to 0. This is required to allow proper stack traversal.
3720 void MacroAssembler::set_last_Java_frame(Register java_thread,
3721 Register last_java_sp,
3722 Register last_java_fp,
3723 address last_java_pc) {
3724 vzeroupper();
3725 // determine java_thread register
3726 if (!java_thread->is_valid()) {
3727 java_thread = rdi;
3728 get_thread(java_thread);
3729 }
3730 // determine last_java_sp register
3731 if (!last_java_sp->is_valid()) {
3732 last_java_sp = rsp;
3733 }
3734
3735 // last_java_fp is optional
3736
3737 if (last_java_fp->is_valid()) {
3738 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3739 }
3740
3741 // last_java_pc is optional
3742
3743 if (last_java_pc != NULL) {
3744 lea(Address(java_thread,
3745 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3746 InternalAddress(last_java_pc));
3747
3748 }
3749 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3750 }
3751
3752 void MacroAssembler::shlptr(Register dst, int imm8) {
3753 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3754 }
3755
3756 void MacroAssembler::shrptr(Register dst, int imm8) {
3757 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3758 }
3759
3760 void MacroAssembler::sign_extend_byte(Register reg) {
3761 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3762 movsbl(reg, reg); // movsxb
3763 } else {
3764 shll(reg, 24);
3765 sarl(reg, 24);
3766 }
3767 }
3768
3769 void MacroAssembler::sign_extend_short(Register reg) {
3770 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3771 movswl(reg, reg); // movsxw
3772 } else {
3773 shll(reg, 16);
3774 sarl(reg, 16);
3775 }
3776 }
3777
3778 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3779 assert(reachable(src), "Address should be reachable");
3780 testl(dst, as_Address(src));
3781 }
3782
3783 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3784 int dst_enc = dst->encoding();
3785 int src_enc = src->encoding();
3786 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3787 Assembler::pcmpeqb(dst, src);
3788 } else if ((dst_enc < 16) && (src_enc < 16)) {
3789 Assembler::pcmpeqb(dst, src);
3790 } else if (src_enc < 16) {
3791 subptr(rsp, 64);
3792 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3793 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3794 Assembler::pcmpeqb(xmm0, src);
3795 movdqu(dst, xmm0);
3796 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3797 addptr(rsp, 64);
3798 } else if (dst_enc < 16) {
3799 subptr(rsp, 64);
3800 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3801 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3802 Assembler::pcmpeqb(dst, xmm0);
3803 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3804 addptr(rsp, 64);
3805 } else {
3806 subptr(rsp, 64);
3807 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3808 subptr(rsp, 64);
3809 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3810 movdqu(xmm0, src);
3811 movdqu(xmm1, dst);
3812 Assembler::pcmpeqb(xmm1, xmm0);
3813 movdqu(dst, xmm1);
3814 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3815 addptr(rsp, 64);
3816 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3817 addptr(rsp, 64);
3818 }
3819 }
3820
3821 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3822 int dst_enc = dst->encoding();
3823 int src_enc = src->encoding();
3824 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3825 Assembler::pcmpeqw(dst, src);
3826 } else if ((dst_enc < 16) && (src_enc < 16)) {
3827 Assembler::pcmpeqw(dst, src);
3828 } else if (src_enc < 16) {
3829 subptr(rsp, 64);
3830 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3831 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3832 Assembler::pcmpeqw(xmm0, src);
3833 movdqu(dst, xmm0);
3834 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3835 addptr(rsp, 64);
3836 } else if (dst_enc < 16) {
3837 subptr(rsp, 64);
3838 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3839 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3840 Assembler::pcmpeqw(dst, xmm0);
3841 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3842 addptr(rsp, 64);
3843 } else {
3844 subptr(rsp, 64);
3845 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3846 subptr(rsp, 64);
3847 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3848 movdqu(xmm0, src);
3849 movdqu(xmm1, dst);
3850 Assembler::pcmpeqw(xmm1, xmm0);
3851 movdqu(dst, xmm1);
3852 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3853 addptr(rsp, 64);
3854 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3855 addptr(rsp, 64);
3856 }
3857 }
3858
3859 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3860 int dst_enc = dst->encoding();
3861 if (dst_enc < 16) {
3862 Assembler::pcmpestri(dst, src, imm8);
3863 } else {
3864 subptr(rsp, 64);
3865 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3866 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3867 Assembler::pcmpestri(xmm0, src, imm8);
3868 movdqu(dst, xmm0);
3869 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3870 addptr(rsp, 64);
3871 }
3872 }
3873
3874 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3875 int dst_enc = dst->encoding();
3876 int src_enc = src->encoding();
3877 if ((dst_enc < 16) && (src_enc < 16)) {
3878 Assembler::pcmpestri(dst, src, imm8);
3879 } else if (src_enc < 16) {
3880 subptr(rsp, 64);
3881 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3882 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3883 Assembler::pcmpestri(xmm0, src, imm8);
3884 movdqu(dst, xmm0);
3885 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3886 addptr(rsp, 64);
3887 } else if (dst_enc < 16) {
3888 subptr(rsp, 64);
3889 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3890 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3891 Assembler::pcmpestri(dst, xmm0, imm8);
3892 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3893 addptr(rsp, 64);
3894 } else {
3895 subptr(rsp, 64);
3896 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3897 subptr(rsp, 64);
3898 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3899 movdqu(xmm0, src);
3900 movdqu(xmm1, dst);
3901 Assembler::pcmpestri(xmm1, xmm0, imm8);
3902 movdqu(dst, xmm1);
3903 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3904 addptr(rsp, 64);
3905 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3906 addptr(rsp, 64);
3907 }
3908 }
3909
3910 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3911 int dst_enc = dst->encoding();
3912 int src_enc = src->encoding();
3913 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3914 Assembler::pmovzxbw(dst, src);
3915 } else if ((dst_enc < 16) && (src_enc < 16)) {
3916 Assembler::pmovzxbw(dst, src);
3917 } else if (src_enc < 16) {
3918 subptr(rsp, 64);
3919 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3920 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3921 Assembler::pmovzxbw(xmm0, src);
3922 movdqu(dst, xmm0);
3923 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3924 addptr(rsp, 64);
3925 } else if (dst_enc < 16) {
3926 subptr(rsp, 64);
3927 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3928 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3929 Assembler::pmovzxbw(dst, xmm0);
3930 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3931 addptr(rsp, 64);
3932 } else {
3933 subptr(rsp, 64);
3934 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3935 subptr(rsp, 64);
3936 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3937 movdqu(xmm0, src);
3938 movdqu(xmm1, dst);
3939 Assembler::pmovzxbw(xmm1, xmm0);
3940 movdqu(dst, xmm1);
3941 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3942 addptr(rsp, 64);
3943 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3944 addptr(rsp, 64);
3945 }
3946 }
3947
3948 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3949 int dst_enc = dst->encoding();
3950 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3951 Assembler::pmovzxbw(dst, src);
3952 } else if (dst_enc < 16) {
3953 Assembler::pmovzxbw(dst, src);
3954 } else {
3955 subptr(rsp, 64);
3956 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3957 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3958 Assembler::pmovzxbw(xmm0, src);
3959 movdqu(dst, xmm0);
3960 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3961 addptr(rsp, 64);
3962 }
3963 }
3964
3965 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3966 int src_enc = src->encoding();
3967 if (src_enc < 16) {
3968 Assembler::pmovmskb(dst, src);
3969 } else {
3970 subptr(rsp, 64);
3971 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3972 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3973 Assembler::pmovmskb(dst, xmm0);
3974 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3975 addptr(rsp, 64);
3976 }
3977 }
3978
3979 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3980 int dst_enc = dst->encoding();
3981 int src_enc = src->encoding();
3982 if ((dst_enc < 16) && (src_enc < 16)) {
3983 Assembler::ptest(dst, src);
3984 } else if (src_enc < 16) {
3985 subptr(rsp, 64);
3986 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3987 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3988 Assembler::ptest(xmm0, src);
3989 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3990 addptr(rsp, 64);
3991 } else if (dst_enc < 16) {
3992 subptr(rsp, 64);
3993 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3994 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3995 Assembler::ptest(dst, xmm0);
3996 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3997 addptr(rsp, 64);
3998 } else {
3999 subptr(rsp, 64);
4000 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4001 subptr(rsp, 64);
4002 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4003 movdqu(xmm0, src);
4004 movdqu(xmm1, dst);
4005 Assembler::ptest(xmm1, xmm0);
4006 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4007 addptr(rsp, 64);
4008 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4009 addptr(rsp, 64);
4010 }
4011 }
4012
4013 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
4014 if (reachable(src)) {
4015 Assembler::sqrtsd(dst, as_Address(src));
4016 } else {
4017 lea(rscratch1, src);
4018 Assembler::sqrtsd(dst, Address(rscratch1, 0));
4019 }
4020 }
4021
4022 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
4023 if (reachable(src)) {
4024 Assembler::sqrtss(dst, as_Address(src));
4025 } else {
4026 lea(rscratch1, src);
4027 Assembler::sqrtss(dst, Address(rscratch1, 0));
4028 }
4029 }
4030
4031 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
4032 if (reachable(src)) {
4033 Assembler::subsd(dst, as_Address(src));
4034 } else {
4035 lea(rscratch1, src);
4036 Assembler::subsd(dst, Address(rscratch1, 0));
4037 }
4038 }
4039
4040 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4041 if (reachable(src)) {
4042 Assembler::subss(dst, as_Address(src));
4043 } else {
4044 lea(rscratch1, src);
4045 Assembler::subss(dst, Address(rscratch1, 0));
4046 }
4047 }
4048
4049 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4050 if (reachable(src)) {
4051 Assembler::ucomisd(dst, as_Address(src));
4052 } else {
4053 lea(rscratch1, src);
4054 Assembler::ucomisd(dst, Address(rscratch1, 0));
4055 }
4056 }
4057
4058 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4059 if (reachable(src)) {
4060 Assembler::ucomiss(dst, as_Address(src));
4061 } else {
4062 lea(rscratch1, src);
4063 Assembler::ucomiss(dst, Address(rscratch1, 0));
4064 }
4065 }
4066
4067 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4068 // Used in sign-bit flipping with aligned address.
4069 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4070 if (reachable(src)) {
4071 Assembler::xorpd(dst, as_Address(src));
4072 } else {
4073 lea(rscratch1, src);
4074 Assembler::xorpd(dst, Address(rscratch1, 0));
4075 }
4076 }
4077
4078 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4079 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4080 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4081 }
4082 else {
4083 Assembler::xorpd(dst, src);
4084 }
4085 }
4086
4087 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4088 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4089 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4090 } else {
4091 Assembler::xorps(dst, src);
4092 }
4093 }
4094
4095 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4096 // Used in sign-bit flipping with aligned address.
4097 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4098 if (reachable(src)) {
4099 Assembler::xorps(dst, as_Address(src));
4100 } else {
4101 lea(rscratch1, src);
4102 Assembler::xorps(dst, Address(rscratch1, 0));
4103 }
4104 }
4105
4106 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4107 // Used in sign-bit flipping with aligned address.
4108 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4109 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4110 if (reachable(src)) {
4111 Assembler::pshufb(dst, as_Address(src));
4112 } else {
4113 lea(rscratch1, src);
4114 Assembler::pshufb(dst, Address(rscratch1, 0));
4115 }
4116 }
4117
4118 // AVX 3-operands instructions
4119
4120 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4121 if (reachable(src)) {
4122 vaddsd(dst, nds, as_Address(src));
4123 } else {
4124 lea(rscratch1, src);
4125 vaddsd(dst, nds, Address(rscratch1, 0));
4126 }
4127 }
4128
4129 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4130 if (reachable(src)) {
4131 vaddss(dst, nds, as_Address(src));
4132 } else {
4133 lea(rscratch1, src);
4134 vaddss(dst, nds, Address(rscratch1, 0));
4135 }
4136 }
4137
4138 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4139 int dst_enc = dst->encoding();
4140 int nds_enc = nds->encoding();
4141 int src_enc = src->encoding();
4142 if ((dst_enc < 16) && (nds_enc < 16)) {
4143 vandps(dst, nds, negate_field, vector_len);
4144 } else if ((src_enc < 16) && (dst_enc < 16)) {
4145 movss(src, nds);
4146 vandps(dst, src, negate_field, vector_len);
4147 } else if (src_enc < 16) {
4148 movss(src, nds);
4149 vandps(src, src, negate_field, vector_len);
4150 movss(dst, src);
4151 } else if (dst_enc < 16) {
4152 movdqu(src, xmm0);
4153 movss(xmm0, nds);
4154 vandps(dst, xmm0, negate_field, vector_len);
4155 movdqu(xmm0, src);
4156 } else if (nds_enc < 16) {
4157 movdqu(src, xmm0);
4158 vandps(xmm0, nds, negate_field, vector_len);
4159 movss(dst, xmm0);
4160 movdqu(xmm0, src);
4161 } else {
4162 movdqu(src, xmm0);
4163 movss(xmm0, nds);
4164 vandps(xmm0, xmm0, negate_field, vector_len);
4165 movss(dst, xmm0);
4166 movdqu(xmm0, src);
4167 }
4168 }
4169
4170 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4171 int dst_enc = dst->encoding();
4172 int nds_enc = nds->encoding();
4173 int src_enc = src->encoding();
4174 if ((dst_enc < 16) && (nds_enc < 16)) {
4175 vandpd(dst, nds, negate_field, vector_len);
4176 } else if ((src_enc < 16) && (dst_enc < 16)) {
4177 movsd(src, nds);
4178 vandpd(dst, src, negate_field, vector_len);
4179 } else if (src_enc < 16) {
4180 movsd(src, nds);
4181 vandpd(src, src, negate_field, vector_len);
4182 movsd(dst, src);
4183 } else if (dst_enc < 16) {
4184 movdqu(src, xmm0);
4185 movsd(xmm0, nds);
4186 vandpd(dst, xmm0, negate_field, vector_len);
4187 movdqu(xmm0, src);
4188 } else if (nds_enc < 16) {
4189 movdqu(src, xmm0);
4190 vandpd(xmm0, nds, negate_field, vector_len);
4191 movsd(dst, xmm0);
4192 movdqu(xmm0, src);
4193 } else {
4194 movdqu(src, xmm0);
4195 movsd(xmm0, nds);
4196 vandpd(xmm0, xmm0, negate_field, vector_len);
4197 movsd(dst, xmm0);
4198 movdqu(xmm0, src);
4199 }
4200 }
4201
4202 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4203 int dst_enc = dst->encoding();
4204 int nds_enc = nds->encoding();
4205 int src_enc = src->encoding();
4206 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4207 Assembler::vpaddb(dst, nds, src, vector_len);
4208 } else if ((dst_enc < 16) && (src_enc < 16)) {
4209 Assembler::vpaddb(dst, dst, src, vector_len);
4210 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4211 // use nds as scratch for src
4212 evmovdqul(nds, src, Assembler::AVX_512bit);
4213 Assembler::vpaddb(dst, dst, nds, vector_len);
4214 } else if ((src_enc < 16) && (nds_enc < 16)) {
4215 // use nds as scratch for dst
4216 evmovdqul(nds, dst, Assembler::AVX_512bit);
4217 Assembler::vpaddb(nds, nds, src, vector_len);
4218 evmovdqul(dst, nds, Assembler::AVX_512bit);
4219 } else if (dst_enc < 16) {
4220 // use nds as scatch for xmm0 to hold src
4221 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4222 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4223 Assembler::vpaddb(dst, dst, xmm0, vector_len);
4224 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4225 } else {
4226 // worse case scenario, all regs are in the upper bank
4227 subptr(rsp, 64);
4228 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4229 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4230 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4231 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4232 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4233 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4234 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4235 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4236 addptr(rsp, 64);
4237 }
4238 }
4239
4240 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4241 int dst_enc = dst->encoding();
4242 int nds_enc = nds->encoding();
4243 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4244 Assembler::vpaddb(dst, nds, src, vector_len);
4245 } else if (dst_enc < 16) {
4246 Assembler::vpaddb(dst, dst, src, vector_len);
4247 } else if (nds_enc < 16) {
4248 // implies dst_enc in upper bank with src as scratch
4249 evmovdqul(nds, dst, Assembler::AVX_512bit);
4250 Assembler::vpaddb(nds, nds, src, vector_len);
4251 evmovdqul(dst, nds, Assembler::AVX_512bit);
4252 } else {
4253 // worse case scenario, all regs in upper bank
4254 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4255 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4256 Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4257 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4258 }
4259 }
4260
4261 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4262 int dst_enc = dst->encoding();
4263 int nds_enc = nds->encoding();
4264 int src_enc = src->encoding();
4265 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4266 Assembler::vpaddw(dst, nds, src, vector_len);
4267 } else if ((dst_enc < 16) && (src_enc < 16)) {
4268 Assembler::vpaddw(dst, dst, src, vector_len);
4269 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4270 // use nds as scratch for src
4271 evmovdqul(nds, src, Assembler::AVX_512bit);
4272 Assembler::vpaddw(dst, dst, nds, vector_len);
4273 } else if ((src_enc < 16) && (nds_enc < 16)) {
4274 // use nds as scratch for dst
4275 evmovdqul(nds, dst, Assembler::AVX_512bit);
4276 Assembler::vpaddw(nds, nds, src, vector_len);
4277 evmovdqul(dst, nds, Assembler::AVX_512bit);
4278 } else if (dst_enc < 16) {
4279 // use nds as scatch for xmm0 to hold src
4280 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4281 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4282 Assembler::vpaddw(dst, dst, xmm0, vector_len);
4283 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4284 } else {
4285 // worse case scenario, all regs are in the upper bank
4286 subptr(rsp, 64);
4287 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4288 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4289 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4290 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4291 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4292 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4293 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4294 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4295 addptr(rsp, 64);
4296 }
4297 }
4298
4299 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4300 int dst_enc = dst->encoding();
4301 int nds_enc = nds->encoding();
4302 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4303 Assembler::vpaddw(dst, nds, src, vector_len);
4304 } else if (dst_enc < 16) {
4305 Assembler::vpaddw(dst, dst, src, vector_len);
4306 } else if (nds_enc < 16) {
4307 // implies dst_enc in upper bank with src as scratch
4308 evmovdqul(nds, dst, Assembler::AVX_512bit);
4309 Assembler::vpaddw(nds, nds, src, vector_len);
4310 evmovdqul(dst, nds, Assembler::AVX_512bit);
4311 } else {
4312 // worse case scenario, all regs in upper bank
4313 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4314 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4315 Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4316 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4317 }
4318 }
4319
4320 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4321 if (reachable(src)) {
4322 Assembler::vpand(dst, nds, as_Address(src), vector_len);
4323 } else {
4324 lea(rscratch1, src);
4325 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
4326 }
4327 }
4328
4329 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4330 int dst_enc = dst->encoding();
4331 int src_enc = src->encoding();
4332 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4333 Assembler::vpbroadcastw(dst, src);
4334 } else if ((dst_enc < 16) && (src_enc < 16)) {
4335 Assembler::vpbroadcastw(dst, src);
4336 } else if (src_enc < 16) {
4337 subptr(rsp, 64);
4338 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4339 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4340 Assembler::vpbroadcastw(xmm0, src);
4341 movdqu(dst, xmm0);
4342 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4343 addptr(rsp, 64);
4344 } else if (dst_enc < 16) {
4345 subptr(rsp, 64);
4346 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4347 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4348 Assembler::vpbroadcastw(dst, xmm0);
4349 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4350 addptr(rsp, 64);
4351 } else {
4352 subptr(rsp, 64);
4353 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4354 subptr(rsp, 64);
4355 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4356 movdqu(xmm0, src);
4357 movdqu(xmm1, dst);
4358 Assembler::vpbroadcastw(xmm1, xmm0);
4359 movdqu(dst, xmm1);
4360 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4361 addptr(rsp, 64);
4362 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4363 addptr(rsp, 64);
4364 }
4365 }
4366
4367 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4368 int dst_enc = dst->encoding();
4369 int nds_enc = nds->encoding();
4370 int src_enc = src->encoding();
4371 assert(dst_enc == nds_enc, "");
4372 if ((dst_enc < 16) && (src_enc < 16)) {
4373 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4374 } else if (src_enc < 16) {
4375 subptr(rsp, 64);
4376 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4377 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4378 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4379 movdqu(dst, xmm0);
4380 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4381 addptr(rsp, 64);
4382 } else if (dst_enc < 16) {
4383 subptr(rsp, 64);
4384 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4385 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4386 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4387 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4388 addptr(rsp, 64);
4389 } else {
4390 subptr(rsp, 64);
4391 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4392 subptr(rsp, 64);
4393 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4394 movdqu(xmm0, src);
4395 movdqu(xmm1, dst);
4396 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4397 movdqu(dst, xmm1);
4398 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4399 addptr(rsp, 64);
4400 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4401 addptr(rsp, 64);
4402 }
4403 }
4404
4405 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4406 int dst_enc = dst->encoding();
4407 int nds_enc = nds->encoding();
4408 int src_enc = src->encoding();
4409 assert(dst_enc == nds_enc, "");
4410 if ((dst_enc < 16) && (src_enc < 16)) {
4411 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4412 } else if (src_enc < 16) {
4413 subptr(rsp, 64);
4414 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4415 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4416 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4417 movdqu(dst, xmm0);
4418 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4419 addptr(rsp, 64);
4420 } else if (dst_enc < 16) {
4421 subptr(rsp, 64);
4422 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4423 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4424 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4425 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4426 addptr(rsp, 64);
4427 } else {
4428 subptr(rsp, 64);
4429 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4430 subptr(rsp, 64);
4431 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4432 movdqu(xmm0, src);
4433 movdqu(xmm1, dst);
4434 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4435 movdqu(dst, xmm1);
4436 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4437 addptr(rsp, 64);
4438 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4439 addptr(rsp, 64);
4440 }
4441 }
4442
4443 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4444 int dst_enc = dst->encoding();
4445 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4446 Assembler::vpmovzxbw(dst, src, vector_len);
4447 } else if (dst_enc < 16) {
4448 Assembler::vpmovzxbw(dst, src, vector_len);
4449 } else {
4450 subptr(rsp, 64);
4451 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4452 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4453 Assembler::vpmovzxbw(xmm0, src, vector_len);
4454 movdqu(dst, xmm0);
4455 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4456 addptr(rsp, 64);
4457 }
4458 }
4459
4460 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4461 int src_enc = src->encoding();
4462 if (src_enc < 16) {
4463 Assembler::vpmovmskb(dst, src);
4464 } else {
4465 subptr(rsp, 64);
4466 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4467 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4468 Assembler::vpmovmskb(dst, xmm0);
4469 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4470 addptr(rsp, 64);
4471 }
4472 }
4473
4474 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4475 int dst_enc = dst->encoding();
4476 int nds_enc = nds->encoding();
4477 int src_enc = src->encoding();
4478 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4479 Assembler::vpmullw(dst, nds, src, vector_len);
4480 } else if ((dst_enc < 16) && (src_enc < 16)) {
4481 Assembler::vpmullw(dst, dst, src, vector_len);
4482 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4483 // use nds as scratch for src
4484 evmovdqul(nds, src, Assembler::AVX_512bit);
4485 Assembler::vpmullw(dst, dst, nds, vector_len);
4486 } else if ((src_enc < 16) && (nds_enc < 16)) {
4487 // use nds as scratch for dst
4488 evmovdqul(nds, dst, Assembler::AVX_512bit);
4489 Assembler::vpmullw(nds, nds, src, vector_len);
4490 evmovdqul(dst, nds, Assembler::AVX_512bit);
4491 } else if (dst_enc < 16) {
4492 // use nds as scatch for xmm0 to hold src
4493 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4494 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4495 Assembler::vpmullw(dst, dst, xmm0, vector_len);
4496 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4497 } else {
4498 // worse case scenario, all regs are in the upper bank
4499 subptr(rsp, 64);
4500 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4501 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4502 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4503 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4504 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4505 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4506 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4507 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4508 addptr(rsp, 64);
4509 }
4510 }
4511
4512 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4513 int dst_enc = dst->encoding();
4514 int nds_enc = nds->encoding();
4515 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4516 Assembler::vpmullw(dst, nds, src, vector_len);
4517 } else if (dst_enc < 16) {
4518 Assembler::vpmullw(dst, dst, src, vector_len);
4519 } else if (nds_enc < 16) {
4520 // implies dst_enc in upper bank with src as scratch
4521 evmovdqul(nds, dst, Assembler::AVX_512bit);
4522 Assembler::vpmullw(nds, nds, src, vector_len);
4523 evmovdqul(dst, nds, Assembler::AVX_512bit);
4524 } else {
4525 // worse case scenario, all regs in upper bank
4526 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4527 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4528 Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4529 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4530 }
4531 }
4532
4533 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4534 int dst_enc = dst->encoding();
4535 int nds_enc = nds->encoding();
4536 int src_enc = src->encoding();
4537 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4538 Assembler::vpsubb(dst, nds, src, vector_len);
4539 } else if ((dst_enc < 16) && (src_enc < 16)) {
4540 Assembler::vpsubb(dst, dst, src, vector_len);
4541 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4542 // use nds as scratch for src
4543 evmovdqul(nds, src, Assembler::AVX_512bit);
4544 Assembler::vpsubb(dst, dst, nds, vector_len);
4545 } else if ((src_enc < 16) && (nds_enc < 16)) {
4546 // use nds as scratch for dst
4547 evmovdqul(nds, dst, Assembler::AVX_512bit);
4548 Assembler::vpsubb(nds, nds, src, vector_len);
4549 evmovdqul(dst, nds, Assembler::AVX_512bit);
4550 } else if (dst_enc < 16) {
4551 // use nds as scatch for xmm0 to hold src
4552 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4553 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4554 Assembler::vpsubb(dst, dst, xmm0, vector_len);
4555 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4556 } else {
4557 // worse case scenario, all regs are in the upper bank
4558 subptr(rsp, 64);
4559 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4560 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4561 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4562 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4563 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4564 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4565 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4566 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4567 addptr(rsp, 64);
4568 }
4569 }
4570
4571 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4572 int dst_enc = dst->encoding();
4573 int nds_enc = nds->encoding();
4574 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4575 Assembler::vpsubb(dst, nds, src, vector_len);
4576 } else if (dst_enc < 16) {
4577 Assembler::vpsubb(dst, dst, src, vector_len);
4578 } else if (nds_enc < 16) {
4579 // implies dst_enc in upper bank with src as scratch
4580 evmovdqul(nds, dst, Assembler::AVX_512bit);
4581 Assembler::vpsubb(nds, nds, src, vector_len);
4582 evmovdqul(dst, nds, Assembler::AVX_512bit);
4583 } else {
4584 // worse case scenario, all regs in upper bank
4585 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4586 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4587 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4588 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4589 }
4590 }
4591
4592 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4593 int dst_enc = dst->encoding();
4594 int nds_enc = nds->encoding();
4595 int src_enc = src->encoding();
4596 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4597 Assembler::vpsubw(dst, nds, src, vector_len);
4598 } else if ((dst_enc < 16) && (src_enc < 16)) {
4599 Assembler::vpsubw(dst, dst, src, vector_len);
4600 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4601 // use nds as scratch for src
4602 evmovdqul(nds, src, Assembler::AVX_512bit);
4603 Assembler::vpsubw(dst, dst, nds, vector_len);
4604 } else if ((src_enc < 16) && (nds_enc < 16)) {
4605 // use nds as scratch for dst
4606 evmovdqul(nds, dst, Assembler::AVX_512bit);
4607 Assembler::vpsubw(nds, nds, src, vector_len);
4608 evmovdqul(dst, nds, Assembler::AVX_512bit);
4609 } else if (dst_enc < 16) {
4610 // use nds as scatch for xmm0 to hold src
4611 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4612 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4613 Assembler::vpsubw(dst, dst, xmm0, vector_len);
4614 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4615 } else {
4616 // worse case scenario, all regs are in the upper bank
4617 subptr(rsp, 64);
4618 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4619 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4620 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4621 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4622 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4623 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4624 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4625 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4626 addptr(rsp, 64);
4627 }
4628 }
4629
4630 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4631 int dst_enc = dst->encoding();
4632 int nds_enc = nds->encoding();
4633 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4634 Assembler::vpsubw(dst, nds, src, vector_len);
4635 } else if (dst_enc < 16) {
4636 Assembler::vpsubw(dst, dst, src, vector_len);
4637 } else if (nds_enc < 16) {
4638 // implies dst_enc in upper bank with src as scratch
4639 evmovdqul(nds, dst, Assembler::AVX_512bit);
4640 Assembler::vpsubw(nds, nds, src, vector_len);
4641 evmovdqul(dst, nds, Assembler::AVX_512bit);
4642 } else {
4643 // worse case scenario, all regs in upper bank
4644 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4645 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4646 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4647 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4648 }
4649 }
4650
4651 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4652 int dst_enc = dst->encoding();
4653 int nds_enc = nds->encoding();
4654 int shift_enc = shift->encoding();
4655 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4656 Assembler::vpsraw(dst, nds, shift, vector_len);
4657 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4658 Assembler::vpsraw(dst, dst, shift, vector_len);
4659 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4660 // use nds_enc as scratch with shift
4661 evmovdqul(nds, shift, Assembler::AVX_512bit);
4662 Assembler::vpsraw(dst, dst, nds, vector_len);
4663 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4664 // use nds as scratch with dst
4665 evmovdqul(nds, dst, Assembler::AVX_512bit);
4666 Assembler::vpsraw(nds, nds, shift, vector_len);
4667 evmovdqul(dst, nds, Assembler::AVX_512bit);
4668 } else if (dst_enc < 16) {
4669 // use nds to save a copy of xmm0 and hold shift
4670 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4671 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4672 Assembler::vpsraw(dst, dst, xmm0, vector_len);
4673 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4674 } else if (nds_enc < 16) {
4675 // use nds as dest as temps
4676 evmovdqul(nds, dst, Assembler::AVX_512bit);
4677 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4678 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4679 Assembler::vpsraw(nds, nds, xmm0, vector_len);
4680 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4681 evmovdqul(dst, nds, Assembler::AVX_512bit);
4682 } else {
4683 // worse case scenario, all regs are in the upper bank
4684 subptr(rsp, 64);
4685 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4686 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4687 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4688 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4689 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4690 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4691 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4692 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4693 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4694 addptr(rsp, 64);
4695 }
4696 }
4697
4698 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4699 int dst_enc = dst->encoding();
4700 int nds_enc = nds->encoding();
4701 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4702 Assembler::vpsraw(dst, nds, shift, vector_len);
4703 } else if (dst_enc < 16) {
4704 Assembler::vpsraw(dst, dst, shift, vector_len);
4705 } else if (nds_enc < 16) {
4706 // use nds as scratch
4707 evmovdqul(nds, dst, Assembler::AVX_512bit);
4708 Assembler::vpsraw(nds, nds, shift, vector_len);
4709 evmovdqul(dst, nds, Assembler::AVX_512bit);
4710 } else {
4711 // use nds as scratch for xmm0
4712 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4713 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4714 Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4715 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4716 }
4717 }
4718
4719 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4720 int dst_enc = dst->encoding();
4721 int nds_enc = nds->encoding();
4722 int shift_enc = shift->encoding();
4723 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4724 Assembler::vpsrlw(dst, nds, shift, vector_len);
4725 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4726 Assembler::vpsrlw(dst, dst, shift, vector_len);
4727 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4728 // use nds_enc as scratch with shift
4729 evmovdqul(nds, shift, Assembler::AVX_512bit);
4730 Assembler::vpsrlw(dst, dst, nds, vector_len);
4731 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4732 // use nds as scratch with dst
4733 evmovdqul(nds, dst, Assembler::AVX_512bit);
4734 Assembler::vpsrlw(nds, nds, shift, vector_len);
4735 evmovdqul(dst, nds, Assembler::AVX_512bit);
4736 } else if (dst_enc < 16) {
4737 // use nds to save a copy of xmm0 and hold shift
4738 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4739 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4740 Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4741 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4742 } else if (nds_enc < 16) {
4743 // use nds as dest as temps
4744 evmovdqul(nds, dst, Assembler::AVX_512bit);
4745 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4746 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4747 Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4748 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4749 evmovdqul(dst, nds, Assembler::AVX_512bit);
4750 } else {
4751 // worse case scenario, all regs are in the upper bank
4752 subptr(rsp, 64);
4753 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4754 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4755 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4756 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4757 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4758 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4759 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4760 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4761 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4762 addptr(rsp, 64);
4763 }
4764 }
4765
4766 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4767 int dst_enc = dst->encoding();
4768 int nds_enc = nds->encoding();
4769 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4770 Assembler::vpsrlw(dst, nds, shift, vector_len);
4771 } else if (dst_enc < 16) {
4772 Assembler::vpsrlw(dst, dst, shift, vector_len);
4773 } else if (nds_enc < 16) {
4774 // use nds as scratch
4775 evmovdqul(nds, dst, Assembler::AVX_512bit);
4776 Assembler::vpsrlw(nds, nds, shift, vector_len);
4777 evmovdqul(dst, nds, Assembler::AVX_512bit);
4778 } else {
4779 // use nds as scratch for xmm0
4780 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4781 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4782 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4783 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4784 }
4785 }
4786
4787 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4788 int dst_enc = dst->encoding();
4789 int nds_enc = nds->encoding();
4790 int shift_enc = shift->encoding();
4791 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4792 Assembler::vpsllw(dst, nds, shift, vector_len);
4793 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4794 Assembler::vpsllw(dst, dst, shift, vector_len);
4795 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4796 // use nds_enc as scratch with shift
4797 evmovdqul(nds, shift, Assembler::AVX_512bit);
4798 Assembler::vpsllw(dst, dst, nds, vector_len);
4799 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4800 // use nds as scratch with dst
4801 evmovdqul(nds, dst, Assembler::AVX_512bit);
4802 Assembler::vpsllw(nds, nds, shift, vector_len);
4803 evmovdqul(dst, nds, Assembler::AVX_512bit);
4804 } else if (dst_enc < 16) {
4805 // use nds to save a copy of xmm0 and hold shift
4806 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4807 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4808 Assembler::vpsllw(dst, dst, xmm0, vector_len);
4809 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4810 } else if (nds_enc < 16) {
4811 // use nds as dest as temps
4812 evmovdqul(nds, dst, Assembler::AVX_512bit);
4813 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4814 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4815 Assembler::vpsllw(nds, nds, xmm0, vector_len);
4816 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4817 evmovdqul(dst, nds, Assembler::AVX_512bit);
4818 } else {
4819 // worse case scenario, all regs are in the upper bank
4820 subptr(rsp, 64);
4821 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4822 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4823 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4824 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4825 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4826 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4827 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4828 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4829 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4830 addptr(rsp, 64);
4831 }
4832 }
4833
4834 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4835 int dst_enc = dst->encoding();
4836 int nds_enc = nds->encoding();
4837 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4838 Assembler::vpsllw(dst, nds, shift, vector_len);
4839 } else if (dst_enc < 16) {
4840 Assembler::vpsllw(dst, dst, shift, vector_len);
4841 } else if (nds_enc < 16) {
4842 // use nds as scratch
4843 evmovdqul(nds, dst, Assembler::AVX_512bit);
4844 Assembler::vpsllw(nds, nds, shift, vector_len);
4845 evmovdqul(dst, nds, Assembler::AVX_512bit);
4846 } else {
4847 // use nds as scratch for xmm0
4848 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4849 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4850 Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4851 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4852 }
4853 }
4854
4855 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4856 int dst_enc = dst->encoding();
4857 int src_enc = src->encoding();
4858 if ((dst_enc < 16) && (src_enc < 16)) {
4859 Assembler::vptest(dst, src);
4860 } else if (src_enc < 16) {
4861 subptr(rsp, 64);
4862 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4863 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4864 Assembler::vptest(xmm0, src);
4865 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4866 addptr(rsp, 64);
4867 } else if (dst_enc < 16) {
4868 subptr(rsp, 64);
4869 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4870 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4871 Assembler::vptest(dst, xmm0);
4872 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4873 addptr(rsp, 64);
4874 } else {
4875 subptr(rsp, 64);
4876 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4877 subptr(rsp, 64);
4878 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4879 movdqu(xmm0, src);
4880 movdqu(xmm1, dst);
4881 Assembler::vptest(xmm1, xmm0);
4882 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4883 addptr(rsp, 64);
4884 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4885 addptr(rsp, 64);
4886 }
4887 }
4888
4889 // This instruction exists within macros, ergo we cannot control its input
4890 // when emitted through those patterns.
4891 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4892 if (VM_Version::supports_avx512nobw()) {
4893 int dst_enc = dst->encoding();
4894 int src_enc = src->encoding();
4895 if (dst_enc == src_enc) {
4896 if (dst_enc < 16) {
4897 Assembler::punpcklbw(dst, src);
4898 } else {
4899 subptr(rsp, 64);
4900 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4901 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4902 Assembler::punpcklbw(xmm0, xmm0);
4903 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4904 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4905 addptr(rsp, 64);
4906 }
4907 } else {
4908 if ((src_enc < 16) && (dst_enc < 16)) {
4909 Assembler::punpcklbw(dst, src);
4910 } else if (src_enc < 16) {
4911 subptr(rsp, 64);
4912 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4913 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4914 Assembler::punpcklbw(xmm0, src);
4915 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4916 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4917 addptr(rsp, 64);
4918 } else if (dst_enc < 16) {
4919 subptr(rsp, 64);
4920 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4921 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4922 Assembler::punpcklbw(dst, xmm0);
4923 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4924 addptr(rsp, 64);
4925 } else {
4926 subptr(rsp, 64);
4927 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4928 subptr(rsp, 64);
4929 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4930 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4931 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4932 Assembler::punpcklbw(xmm0, xmm1);
4933 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4934 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4935 addptr(rsp, 64);
4936 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4937 addptr(rsp, 64);
4938 }
4939 }
4940 } else {
4941 Assembler::punpcklbw(dst, src);
4942 }
4943 }
4944
4945 // This instruction exists within macros, ergo we cannot control its input
4946 // when emitted through those patterns.
4947 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4948 if (VM_Version::supports_avx512nobw()) {
4949 int dst_enc = dst->encoding();
4950 int src_enc = src->encoding();
4951 if (dst_enc == src_enc) {
4952 if (dst_enc < 16) {
4953 Assembler::pshuflw(dst, src, mode);
4954 } else {
4955 subptr(rsp, 64);
4956 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4957 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4958 Assembler::pshuflw(xmm0, xmm0, mode);
4959 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4960 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4961 addptr(rsp, 64);
4962 }
4963 } else {
4964 if ((src_enc < 16) && (dst_enc < 16)) {
4965 Assembler::pshuflw(dst, src, mode);
4966 } else if (src_enc < 16) {
4967 subptr(rsp, 64);
4968 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4969 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4970 Assembler::pshuflw(xmm0, src, mode);
4971 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4972 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4973 addptr(rsp, 64);
4974 } else if (dst_enc < 16) {
4975 subptr(rsp, 64);
4976 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4977 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4978 Assembler::pshuflw(dst, xmm0, mode);
4979 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4980 addptr(rsp, 64);
4981 } else {
4982 subptr(rsp, 64);
4983 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4984 subptr(rsp, 64);
4985 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4986 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4987 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4988 Assembler::pshuflw(xmm0, xmm1, mode);
4989 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4990 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4991 addptr(rsp, 64);
4992 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4993 addptr(rsp, 64);
4994 }
4995 }
4996 } else {
4997 Assembler::pshuflw(dst, src, mode);
4998 }
4999 }
5000
5001 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5002 if (reachable(src)) {
5003 vandpd(dst, nds, as_Address(src), vector_len);
5004 } else {
5005 lea(rscratch1, src);
5006 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
5007 }
5008 }
5009
5010 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5011 if (reachable(src)) {
5012 vandps(dst, nds, as_Address(src), vector_len);
5013 } else {
5014 lea(rscratch1, src);
5015 vandps(dst, nds, Address(rscratch1, 0), vector_len);
5016 }
5017 }
5018
5019 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5020 if (reachable(src)) {
5021 vdivsd(dst, nds, as_Address(src));
5022 } else {
5023 lea(rscratch1, src);
5024 vdivsd(dst, nds, Address(rscratch1, 0));
5025 }
5026 }
5027
5028 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5029 if (reachable(src)) {
5030 vdivss(dst, nds, as_Address(src));
5031 } else {
5032 lea(rscratch1, src);
5033 vdivss(dst, nds, Address(rscratch1, 0));
5034 }
5035 }
5036
5037 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5038 if (reachable(src)) {
5039 vmulsd(dst, nds, as_Address(src));
5040 } else {
5041 lea(rscratch1, src);
5042 vmulsd(dst, nds, Address(rscratch1, 0));
5043 }
5044 }
5045
5046 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5047 if (reachable(src)) {
5048 vmulss(dst, nds, as_Address(src));
5049 } else {
5050 lea(rscratch1, src);
5051 vmulss(dst, nds, Address(rscratch1, 0));
5052 }
5053 }
5054
5055 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5056 if (reachable(src)) {
5057 vsubsd(dst, nds, as_Address(src));
5058 } else {
5059 lea(rscratch1, src);
5060 vsubsd(dst, nds, Address(rscratch1, 0));
5061 }
5062 }
5063
5064 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5065 if (reachable(src)) {
5066 vsubss(dst, nds, as_Address(src));
5067 } else {
5068 lea(rscratch1, src);
5069 vsubss(dst, nds, Address(rscratch1, 0));
5070 }
5071 }
5072
5073 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5074 int nds_enc = nds->encoding();
5075 int dst_enc = dst->encoding();
5076 bool dst_upper_bank = (dst_enc > 15);
5077 bool nds_upper_bank = (nds_enc > 15);
5078 if (VM_Version::supports_avx512novl() &&
5079 (nds_upper_bank || dst_upper_bank)) {
5080 if (dst_upper_bank) {
5081 subptr(rsp, 64);
5082 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5083 movflt(xmm0, nds);
5084 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5085 movflt(dst, xmm0);
5086 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5087 addptr(rsp, 64);
5088 } else {
5089 movflt(dst, nds);
5090 vxorps(dst, dst, src, Assembler::AVX_128bit);
5091 }
5092 } else {
5093 vxorps(dst, nds, src, Assembler::AVX_128bit);
5094 }
5095 }
5096
5097 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5098 int nds_enc = nds->encoding();
5099 int dst_enc = dst->encoding();
5100 bool dst_upper_bank = (dst_enc > 15);
5101 bool nds_upper_bank = (nds_enc > 15);
5102 if (VM_Version::supports_avx512novl() &&
5103 (nds_upper_bank || dst_upper_bank)) {
5104 if (dst_upper_bank) {
5105 subptr(rsp, 64);
5106 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5107 movdbl(xmm0, nds);
5108 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5109 movdbl(dst, xmm0);
5110 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5111 addptr(rsp, 64);
5112 } else {
5113 movdbl(dst, nds);
5114 vxorpd(dst, dst, src, Assembler::AVX_128bit);
5115 }
5116 } else {
5117 vxorpd(dst, nds, src, Assembler::AVX_128bit);
5118 }
5119 }
5120
5121 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5122 if (reachable(src)) {
5123 vxorpd(dst, nds, as_Address(src), vector_len);
5124 } else {
5125 lea(rscratch1, src);
5126 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5127 }
5128 }
5129
5130 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5131 if (reachable(src)) {
5132 vxorps(dst, nds, as_Address(src), vector_len);
5133 } else {
5134 lea(rscratch1, src);
5135 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5136 }
5137 }
5138
5139
5140 void MacroAssembler::resolve_jobject(Register value,
5141 Register thread,
5142 Register tmp) {
5143 assert_different_registers(value, thread, tmp);
5144 Label done, not_weak;
5145 testptr(value, value);
5146 jcc(Assembler::zero, done); // Use NULL as-is.
5147 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
5148 jcc(Assembler::zero, not_weak);
5149 // Resolve jweak.
5150 movptr(value, Address(value, -JNIHandles::weak_tag_value));
5151 verify_oop(value);
5152 #if INCLUDE_ALL_GCS
5153 if (UseG1GC) {
5154 g1_write_barrier_pre(noreg /* obj */,
5155 value /* pre_val */,
5156 thread /* thread */,
5157 tmp /* tmp */,
5158 true /* tosca_live */,
5159 true /* expand_call */);
5160 }
5161 #endif // INCLUDE_ALL_GCS
5162 jmp(done);
5163 bind(not_weak);
5164 // Resolve (untagged) jobject.
5165 movptr(value, Address(value, 0));
5166 verify_oop(value);
5167 bind(done);
5168 }
5169
5170 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
5171 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
5172 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
5173 // The inverted mask is sign-extended
5174 andptr(possibly_jweak, inverted_jweak_mask);
5175 }
5176
5177 //////////////////////////////////////////////////////////////////////////////////
5178 #if INCLUDE_ALL_GCS
5179
5180 void MacroAssembler::g1_write_barrier_pre(Register obj,
5181 Register pre_val,
5182 Register thread,
5183 Register tmp,
5184 bool tosca_live,
5185 bool expand_call) {
5186
5187 // If expand_call is true then we expand the call_VM_leaf macro
5188 // directly to skip generating the check by
5189 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
5190
5191 #ifdef _LP64
5192 assert(thread == r15_thread, "must be");
5193 #endif // _LP64
5194
5195 Label done;
5196 Label runtime;
5197
5198 assert(pre_val != noreg, "check this code");
5199
5200 if (obj != noreg) {
5201 assert_different_registers(obj, pre_val, tmp);
5202 assert(pre_val != rax, "check this code");
5203 }
5204
5205 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5206 SATBMarkQueue::byte_offset_of_active()));
5207 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5208 SATBMarkQueue::byte_offset_of_index()));
5209 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5210 SATBMarkQueue::byte_offset_of_buf()));
5211
5212
5213 // Is marking active?
5214 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
5215 cmpl(in_progress, 0);
5216 } else {
5217 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
5218 cmpb(in_progress, 0);
5219 }
5220 jcc(Assembler::equal, done);
5221
5222 // Do we need to load the previous value?
5223 if (obj != noreg) {
5224 load_heap_oop(pre_val, Address(obj, 0));
5225 }
5226
5227 // Is the previous value null?
5228 cmpptr(pre_val, (int32_t) NULL_WORD);
5229 jcc(Assembler::equal, done);
5230
5231 // Can we store original value in the thread's buffer?
5232 // Is index == 0?
5233 // (The index field is typed as size_t.)
5234
5235 movptr(tmp, index); // tmp := *index_adr
5236 cmpptr(tmp, 0); // tmp == 0?
5237 jcc(Assembler::equal, runtime); // If yes, goto runtime
5238
5239 subptr(tmp, wordSize); // tmp := tmp - wordSize
5240 movptr(index, tmp); // *index_adr := tmp
5241 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
5242
5243 // Record the previous value
5244 movptr(Address(tmp, 0), pre_val);
5245 jmp(done);
5246
5247 bind(runtime);
5248 // save the live input values
5249 if(tosca_live) push(rax);
5250
5251 if (obj != noreg && obj != rax)
5252 push(obj);
5253
5254 if (pre_val != rax)
5255 push(pre_val);
5256
5257 // Calling the runtime using the regular call_VM_leaf mechanism generates
5258 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
5259 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
5260 //
5261 // If we care generating the pre-barrier without a frame (e.g. in the
5262 // intrinsified Reference.get() routine) then ebp might be pointing to
5263 // the caller frame and so this check will most likely fail at runtime.
5264 //
5265 // Expanding the call directly bypasses the generation of the check.
5266 // So when we do not have have a full interpreter frame on the stack
5267 // expand_call should be passed true.
5268
5269 NOT_LP64( push(thread); )
5270
5271 if (expand_call) {
5272 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
5273 pass_arg1(this, thread);
5274 pass_arg0(this, pre_val);
5275 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
5276 } else {
5277 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
5278 }
5279
5280 NOT_LP64( pop(thread); )
5281
5282 // save the live input values
5283 if (pre_val != rax)
5284 pop(pre_val);
5285
5286 if (obj != noreg && obj != rax)
5287 pop(obj);
5288
5289 if(tosca_live) pop(rax);
5290
5291 bind(done);
5292 }
5293
5294 void MacroAssembler::g1_write_barrier_post(Register store_addr,
5295 Register new_val,
5296 Register thread,
5297 Register tmp,
5298 Register tmp2) {
5299 #ifdef _LP64
5300 assert(thread == r15_thread, "must be");
5301 #endif // _LP64
5302
5303 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5304 DirtyCardQueue::byte_offset_of_index()));
5305 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5306 DirtyCardQueue::byte_offset_of_buf()));
5307
5308 CardTableModRefBS* ct =
5309 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
5310 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5311
5312 Label done;
5313 Label runtime;
5314
5315 // Does store cross heap regions?
5316
5317 movptr(tmp, store_addr);
5318 xorptr(tmp, new_val);
5319 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
5320 jcc(Assembler::equal, done);
5321
5322 // crosses regions, storing NULL?
5323
5324 cmpptr(new_val, (int32_t) NULL_WORD);
5325 jcc(Assembler::equal, done);
5326
5327 // storing region crossing non-NULL, is card already dirty?
5328
5329 const Register card_addr = tmp;
5330 const Register cardtable = tmp2;
5331
5332 movptr(card_addr, store_addr);
5333 shrptr(card_addr, CardTableModRefBS::card_shift);
5334 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
5335 // a valid address and therefore is not properly handled by the relocation code.
5336 movptr(cardtable, (intptr_t)ct->byte_map_base);
5337 addptr(card_addr, cardtable);
5338
5339 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
5340 jcc(Assembler::equal, done);
5341
5342 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
5343 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5344 jcc(Assembler::equal, done);
5345
5346
5347 // storing a region crossing, non-NULL oop, card is clean.
5348 // dirty card and log.
5349
5350 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5351
5352 cmpl(queue_index, 0);
5353 jcc(Assembler::equal, runtime);
5354 subl(queue_index, wordSize);
5355 movptr(tmp2, buffer);
5356 #ifdef _LP64
5357 movslq(rscratch1, queue_index);
5358 addq(tmp2, rscratch1);
5359 movq(Address(tmp2, 0), card_addr);
5360 #else
5361 addl(tmp2, queue_index);
5362 movl(Address(tmp2, 0), card_addr);
5363 #endif
5364 jmp(done);
5365
5366 bind(runtime);
5367 // save the live input values
5368 push(store_addr);
5369 push(new_val);
5370 #ifdef _LP64
5371 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
5372 #else
5373 push(thread);
5374 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
5375 pop(thread);
5376 #endif
5377 pop(new_val);
5378 pop(store_addr);
5379
5380 bind(done);
5381 }
5382
5383 #endif // INCLUDE_ALL_GCS
5384 //////////////////////////////////////////////////////////////////////////////////
5385
5386
5387 void MacroAssembler::store_check(Register obj, Address dst) {
5388 store_check(obj);
5389 }
5390
5391 void MacroAssembler::store_check(Register obj) {
5392 // Does a store check for the oop in register obj. The content of
5393 // register obj is destroyed afterwards.
5394 BarrierSet* bs = Universe::heap()->barrier_set();
5395 assert(bs->kind() == BarrierSet::CardTableForRS ||
5396 bs->kind() == BarrierSet::CardTableExtension,
5397 "Wrong barrier set kind");
5398
5399 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
5400 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5401
5402 shrptr(obj, CardTableModRefBS::card_shift);
5403
5404 Address card_addr;
5405
5406 // The calculation for byte_map_base is as follows:
5407 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
5408 // So this essentially converts an address to a displacement and it will
5409 // never need to be relocated. On 64bit however the value may be too
5410 // large for a 32bit displacement.
5411 intptr_t disp = (intptr_t) ct->byte_map_base;
5412 if (is_simm32(disp)) {
5413 card_addr = Address(noreg, obj, Address::times_1, disp);
5414 } else {
5415 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
5416 // displacement and done in a single instruction given favorable mapping and a
5417 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
5418 // entry and that entry is not properly handled by the relocation code.
5419 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
5420 Address index(noreg, obj, Address::times_1);
5421 card_addr = as_Address(ArrayAddress(cardtable, index));
5422 }
5423
5424 int dirty = CardTableModRefBS::dirty_card_val();
5425 if (UseCondCardMark) {
5426 Label L_already_dirty;
5427 if (UseConcMarkSweepGC) {
5428 membar(Assembler::StoreLoad);
5429 }
5430 cmpb(card_addr, dirty);
5431 jcc(Assembler::equal, L_already_dirty);
5432 movb(card_addr, dirty);
5433 bind(L_already_dirty);
5434 } else {
5435 movb(card_addr, dirty);
5436 }
5437 }
5438
5439 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5440 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5441 }
5442
5443 // Force generation of a 4 byte immediate value even if it fits into 8bit
5444 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5445 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5446 }
5447
5448 void MacroAssembler::subptr(Register dst, Register src) {
5449 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5450 }
5451
5452 // C++ bool manipulation
5453 void MacroAssembler::testbool(Register dst) {
5454 if(sizeof(bool) == 1)
5455 testb(dst, 0xff);
5456 else if(sizeof(bool) == 2) {
5457 // testw implementation needed for two byte bools
5458 ShouldNotReachHere();
5459 } else if(sizeof(bool) == 4)
5460 testl(dst, dst);
5461 else
5462 // unsupported
5463 ShouldNotReachHere();
5464 }
5465
5466 void MacroAssembler::testptr(Register dst, Register src) {
5467 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5468 }
5469
5470 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5471 void MacroAssembler::tlab_allocate(Register obj,
5472 Register var_size_in_bytes,
5473 int con_size_in_bytes,
5474 Register t1,
5475 Register t2,
5476 Label& slow_case) {
5477 assert_different_registers(obj, t1, t2);
5478 assert_different_registers(obj, var_size_in_bytes, t1);
5479 Register end = t2;
5480 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
5481
5482 verify_tlab();
5483
5484 NOT_LP64(get_thread(thread));
5485
5486 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
5487 if (var_size_in_bytes == noreg) {
5488 lea(end, Address(obj, con_size_in_bytes));
5489 } else {
5490 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
5491 }
5492 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
5493 jcc(Assembler::above, slow_case);
5494
5495 // update the tlab top pointer
5496 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
5497
5498 // recover var_size_in_bytes if necessary
5499 if (var_size_in_bytes == end) {
5500 subptr(var_size_in_bytes, obj);
5501 }
5502 verify_tlab();
5503 }
5504
5505 // Preserves rbx, and rdx.
5506 Register MacroAssembler::tlab_refill(Label& retry,
5507 Label& try_eden,
5508 Label& slow_case) {
5509 Register top = rax;
5510 Register t1 = rcx; // object size
5511 Register t2 = rsi;
5512 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
5513 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
5514 Label do_refill, discard_tlab;
5515
5516 if (!Universe::heap()->supports_inline_contig_alloc()) {
5517 // No allocation in the shared eden.
5518 jmp(slow_case);
5519 }
5520
5521 NOT_LP64(get_thread(thread_reg));
5522
5523 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5524 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5525
5526 // calculate amount of free space
5527 subptr(t1, top);
5528 shrptr(t1, LogHeapWordSize);
5529
5530 // Retain tlab and allocate object in shared space if
5531 // the amount free in the tlab is too large to discard.
5532 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
5533 jcc(Assembler::lessEqual, discard_tlab);
5534
5535 // Retain
5536 // %%% yuck as movptr...
5537 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
5538 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
5539 if (TLABStats) {
5540 // increment number of slow_allocations
5541 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
5542 }
5543 jmp(try_eden);
5544
5545 bind(discard_tlab);
5546 if (TLABStats) {
5547 // increment number of refills
5548 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
5549 // accumulate wastage -- t1 is amount free in tlab
5550 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
5551 }
5552
5553 // if tlab is currently allocated (top or end != null) then
5554 // fill [top, end + alignment_reserve) with array object
5555 testptr(top, top);
5556 jcc(Assembler::zero, do_refill);
5557
5558 // set up the mark word
5559 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
5560 // set the length to the remaining space
5561 subptr(t1, typeArrayOopDesc::header_size(T_INT));
5562 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
5563 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
5564 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
5565 // set klass to intArrayKlass
5566 // dubious reloc why not an oop reloc?
5567 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
5568 // store klass last. concurrent gcs assumes klass length is valid if
5569 // klass field is not null.
5570 store_klass(top, t1);
5571
5572 movptr(t1, top);
5573 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5574 incr_allocated_bytes(thread_reg, t1, 0);
5575
5576 // refill the tlab with an eden allocation
5577 bind(do_refill);
5578 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5579 shlptr(t1, LogHeapWordSize);
5580 // allocate new tlab, address returned in top
5581 eden_allocate(top, t1, 0, t2, slow_case);
5582
5583 // Check that t1 was preserved in eden_allocate.
5584 #ifdef ASSERT
5585 if (UseTLAB) {
5586 Label ok;
5587 Register tsize = rsi;
5588 assert_different_registers(tsize, thread_reg, t1);
5589 push(tsize);
5590 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5591 shlptr(tsize, LogHeapWordSize);
5592 cmpptr(t1, tsize);
5593 jcc(Assembler::equal, ok);
5594 STOP("assert(t1 != tlab size)");
5595 should_not_reach_here();
5596
5597 bind(ok);
5598 pop(tsize);
5599 }
5600 #endif
5601 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
5602 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
5603 addptr(top, t1);
5604 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
5605 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
5606
5607 if (ZeroTLAB) {
5608 // This is a fast TLAB refill, therefore the GC is not notified of it.
5609 // So compiled code must fill the new TLAB with zeroes.
5610 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5611 zero_memory(top, t1, 0, t2);
5612 }
5613
5614 verify_tlab();
5615 jmp(retry);
5616
5617 return thread_reg; // for use by caller
5618 }
5619
5620 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5621 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5622 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5623 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5624 Label done;
5625
5626 testptr(length_in_bytes, length_in_bytes);
5627 jcc(Assembler::zero, done);
5628
5629 // initialize topmost word, divide index by 2, check if odd and test if zero
5630 // note: for the remaining code to work, index must be a multiple of BytesPerWord
5631 #ifdef ASSERT
5632 {
5633 Label L;
5634 testptr(length_in_bytes, BytesPerWord - 1);
5635 jcc(Assembler::zero, L);
5636 stop("length must be a multiple of BytesPerWord");
5637 bind(L);
5638 }
5639 #endif
5640 Register index = length_in_bytes;
5641 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
5642 if (UseIncDec) {
5643 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
5644 } else {
5645 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
5646 shrptr(index, 1);
5647 }
5648 #ifndef _LP64
5649 // index could have not been a multiple of 8 (i.e., bit 2 was set)
5650 {
5651 Label even;
5652 // note: if index was a multiple of 8, then it cannot
5653 // be 0 now otherwise it must have been 0 before
5654 // => if it is even, we don't need to check for 0 again
5655 jcc(Assembler::carryClear, even);
5656 // clear topmost word (no jump would be needed if conditional assignment worked here)
5657 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5658 // index could be 0 now, must check again
5659 jcc(Assembler::zero, done);
5660 bind(even);
5661 }
5662 #endif // !_LP64
5663 // initialize remaining object fields: index is a multiple of 2 now
5664 {
5665 Label loop;
5666 bind(loop);
5667 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5668 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5669 decrement(index);
5670 jcc(Assembler::notZero, loop);
5671 }
5672
5673 bind(done);
5674 }
5675
5676 void MacroAssembler::incr_allocated_bytes(Register thread,
5677 Register var_size_in_bytes,
5678 int con_size_in_bytes,
5679 Register t1) {
5680 if (!thread->is_valid()) {
5681 #ifdef _LP64
5682 thread = r15_thread;
5683 #else
5684 assert(t1->is_valid(), "need temp reg");
5685 thread = t1;
5686 get_thread(thread);
5687 #endif
5688 }
5689
5690 #ifdef _LP64
5691 if (var_size_in_bytes->is_valid()) {
5692 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5693 } else {
5694 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5695 }
5696 #else
5697 if (var_size_in_bytes->is_valid()) {
5698 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5699 } else {
5700 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5701 }
5702 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
5703 #endif
5704 }
5705
5706 // Look up the method for a megamorphic invokeinterface call.
5707 // The target method is determined by <intf_klass, itable_index>.
5708 // The receiver klass is in recv_klass.
5709 // On success, the result will be in method_result, and execution falls through.
5710 // On failure, execution transfers to the given label.
5711 void MacroAssembler::lookup_interface_method(Register recv_klass,
5712 Register intf_klass,
5713 RegisterOrConstant itable_index,
5714 Register method_result,
5715 Register scan_temp,
5716 Label& L_no_such_interface) {
5717 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
5718 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5719 "caller must use same register for non-constant itable index as for method");
5720
5721 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5722 int vtable_base = in_bytes(Klass::vtable_start_offset());
5723 int itentry_off = itableMethodEntry::method_offset_in_bytes();
5724 int scan_step = itableOffsetEntry::size() * wordSize;
5725 int vte_size = vtableEntry::size_in_bytes();
5726 Address::ScaleFactor times_vte_scale = Address::times_ptr;
5727 assert(vte_size == wordSize, "else adjust times_vte_scale");
5728
5729 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
5730
5731 // %%% Could store the aligned, prescaled offset in the klassoop.
5732 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5733
5734 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5735 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5736 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5737
5738 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5739 // if (scan->interface() == intf) {
5740 // result = (klass + scan->offset() + itable_index);
5741 // }
5742 // }
5743 Label search, found_method;
5744
5745 for (int peel = 1; peel >= 0; peel--) {
5746 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5747 cmpptr(intf_klass, method_result);
5748
5749 if (peel) {
5750 jccb(Assembler::equal, found_method);
5751 } else {
5752 jccb(Assembler::notEqual, search);
5753 // (invert the test to fall through to found_method...)
5754 }
5755
5756 if (!peel) break;
5757
5758 bind(search);
5759
5760 // Check that the previous entry is non-null. A null entry means that
5761 // the receiver class doesn't implement the interface, and wasn't the
5762 // same as when the caller was compiled.
5763 testptr(method_result, method_result);
5764 jcc(Assembler::zero, L_no_such_interface);
5765 addptr(scan_temp, scan_step);
5766 }
5767
5768 bind(found_method);
5769
5770 // Got a hit.
5771 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5772 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5773 }
5774
5775
5776 // virtual method calling
5777 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5778 RegisterOrConstant vtable_index,
5779 Register method_result) {
5780 const int base = in_bytes(Klass::vtable_start_offset());
5781 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5782 Address vtable_entry_addr(recv_klass,
5783 vtable_index, Address::times_ptr,
5784 base + vtableEntry::method_offset_in_bytes());
5785 movptr(method_result, vtable_entry_addr);
5786 }
5787
5788
5789 void MacroAssembler::check_klass_subtype(Register sub_klass,
5790 Register super_klass,
5791 Register temp_reg,
5792 Label& L_success) {
5793 Label L_failure;
5794 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5795 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5796 bind(L_failure);
5797 }
5798
5799
5800 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5801 Register super_klass,
5802 Register temp_reg,
5803 Label* L_success,
5804 Label* L_failure,
5805 Label* L_slow_path,
5806 RegisterOrConstant super_check_offset) {
5807 assert_different_registers(sub_klass, super_klass, temp_reg);
5808 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5809 if (super_check_offset.is_register()) {
5810 assert_different_registers(sub_klass, super_klass,
5811 super_check_offset.as_register());
5812 } else if (must_load_sco) {
5813 assert(temp_reg != noreg, "supply either a temp or a register offset");
5814 }
5815
5816 Label L_fallthrough;
5817 int label_nulls = 0;
5818 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5819 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5820 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5821 assert(label_nulls <= 1, "at most one NULL in the batch");
5822
5823 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5824 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5825 Address super_check_offset_addr(super_klass, sco_offset);
5826
5827 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5828 // range of a jccb. If this routine grows larger, reconsider at
5829 // least some of these.
5830 #define local_jcc(assembler_cond, label) \
5831 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5832 else jcc( assembler_cond, label) /*omit semi*/
5833
5834 // Hacked jmp, which may only be used just before L_fallthrough.
5835 #define final_jmp(label) \
5836 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5837 else jmp(label) /*omit semi*/
5838
5839 // If the pointers are equal, we are done (e.g., String[] elements).
5840 // This self-check enables sharing of secondary supertype arrays among
5841 // non-primary types such as array-of-interface. Otherwise, each such
5842 // type would need its own customized SSA.
5843 // We move this check to the front of the fast path because many
5844 // type checks are in fact trivially successful in this manner,
5845 // so we get a nicely predicted branch right at the start of the check.
5846 cmpptr(sub_klass, super_klass);
5847 local_jcc(Assembler::equal, *L_success);
5848
5849 // Check the supertype display:
5850 if (must_load_sco) {
5851 // Positive movl does right thing on LP64.
5852 movl(temp_reg, super_check_offset_addr);
5853 super_check_offset = RegisterOrConstant(temp_reg);
5854 }
5855 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5856 cmpptr(super_klass, super_check_addr); // load displayed supertype
5857
5858 // This check has worked decisively for primary supers.
5859 // Secondary supers are sought in the super_cache ('super_cache_addr').
5860 // (Secondary supers are interfaces and very deeply nested subtypes.)
5861 // This works in the same check above because of a tricky aliasing
5862 // between the super_cache and the primary super display elements.
5863 // (The 'super_check_addr' can address either, as the case requires.)
5864 // Note that the cache is updated below if it does not help us find
5865 // what we need immediately.
5866 // So if it was a primary super, we can just fail immediately.
5867 // Otherwise, it's the slow path for us (no success at this point).
5868
5869 if (super_check_offset.is_register()) {
5870 local_jcc(Assembler::equal, *L_success);
5871 cmpl(super_check_offset.as_register(), sc_offset);
5872 if (L_failure == &L_fallthrough) {
5873 local_jcc(Assembler::equal, *L_slow_path);
5874 } else {
5875 local_jcc(Assembler::notEqual, *L_failure);
5876 final_jmp(*L_slow_path);
5877 }
5878 } else if (super_check_offset.as_constant() == sc_offset) {
5879 // Need a slow path; fast failure is impossible.
5880 if (L_slow_path == &L_fallthrough) {
5881 local_jcc(Assembler::equal, *L_success);
5882 } else {
5883 local_jcc(Assembler::notEqual, *L_slow_path);
5884 final_jmp(*L_success);
5885 }
5886 } else {
5887 // No slow path; it's a fast decision.
5888 if (L_failure == &L_fallthrough) {
5889 local_jcc(Assembler::equal, *L_success);
5890 } else {
5891 local_jcc(Assembler::notEqual, *L_failure);
5892 final_jmp(*L_success);
5893 }
5894 }
5895
5896 bind(L_fallthrough);
5897
5898 #undef local_jcc
5899 #undef final_jmp
5900 }
5901
5902
5903 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5904 Register super_klass,
5905 Register temp_reg,
5906 Register temp2_reg,
5907 Label* L_success,
5908 Label* L_failure,
5909 bool set_cond_codes) {
5910 assert_different_registers(sub_klass, super_klass, temp_reg);
5911 if (temp2_reg != noreg)
5912 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5913 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5914
5915 Label L_fallthrough;
5916 int label_nulls = 0;
5917 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5918 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5919 assert(label_nulls <= 1, "at most one NULL in the batch");
5920
5921 // a couple of useful fields in sub_klass:
5922 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5923 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5924 Address secondary_supers_addr(sub_klass, ss_offset);
5925 Address super_cache_addr( sub_klass, sc_offset);
5926
5927 // Do a linear scan of the secondary super-klass chain.
5928 // This code is rarely used, so simplicity is a virtue here.
5929 // The repne_scan instruction uses fixed registers, which we must spill.
5930 // Don't worry too much about pre-existing connections with the input regs.
5931
5932 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5933 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5934
5935 // Get super_klass value into rax (even if it was in rdi or rcx).
5936 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5937 if (super_klass != rax || UseCompressedOops) {
5938 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5939 mov(rax, super_klass);
5940 }
5941 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5942 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5943
5944 #ifndef PRODUCT
5945 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5946 ExternalAddress pst_counter_addr((address) pst_counter);
5947 NOT_LP64( incrementl(pst_counter_addr) );
5948 LP64_ONLY( lea(rcx, pst_counter_addr) );
5949 LP64_ONLY( incrementl(Address(rcx, 0)) );
5950 #endif //PRODUCT
5951
5952 // We will consult the secondary-super array.
5953 movptr(rdi, secondary_supers_addr);
5954 // Load the array length. (Positive movl does right thing on LP64.)
5955 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5956 // Skip to start of data.
5957 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5958
5959 // Scan RCX words at [RDI] for an occurrence of RAX.
5960 // Set NZ/Z based on last compare.
5961 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5962 // not change flags (only scas instruction which is repeated sets flags).
5963 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5964
5965 testptr(rax,rax); // Set Z = 0
5966 repne_scan();
5967
5968 // Unspill the temp. registers:
5969 if (pushed_rdi) pop(rdi);
5970 if (pushed_rcx) pop(rcx);
5971 if (pushed_rax) pop(rax);
5972
5973 if (set_cond_codes) {
5974 // Special hack for the AD files: rdi is guaranteed non-zero.
5975 assert(!pushed_rdi, "rdi must be left non-NULL");
5976 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5977 }
5978
5979 if (L_failure == &L_fallthrough)
5980 jccb(Assembler::notEqual, *L_failure);
5981 else jcc(Assembler::notEqual, *L_failure);
5982
5983 // Success. Cache the super we found and proceed in triumph.
5984 movptr(super_cache_addr, super_klass);
5985
5986 if (L_success != &L_fallthrough) {
5987 jmp(*L_success);
5988 }
5989
5990 #undef IS_A_TEMP
5991
5992 bind(L_fallthrough);
5993 }
5994
5995
5996 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5997 if (VM_Version::supports_cmov()) {
5998 cmovl(cc, dst, src);
5999 } else {
6000 Label L;
6001 jccb(negate_condition(cc), L);
6002 movl(dst, src);
6003 bind(L);
6004 }
6005 }
6006
6007 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
6008 if (VM_Version::supports_cmov()) {
6009 cmovl(cc, dst, src);
6010 } else {
6011 Label L;
6012 jccb(negate_condition(cc), L);
6013 movl(dst, src);
6014 bind(L);
6015 }
6016 }
6017
6018 void MacroAssembler::verify_oop(Register reg, const char* s) {
6019 if (!VerifyOops || VerifyAdapterSharing) {
6020 // Below address of the code string confuses VerifyAdapterSharing
6021 // because it may differ between otherwise equivalent adapters.
6022 return;
6023 }
6024
6025 // Pass register number to verify_oop_subroutine
6026 const char* b = NULL;
6027 {
6028 ResourceMark rm;
6029 stringStream ss;
6030 ss.print("verify_oop: %s: %s", reg->name(), s);
6031 b = code_string(ss.as_string());
6032 }
6033 BLOCK_COMMENT("verify_oop {");
6034 #ifdef _LP64
6035 push(rscratch1); // save r10, trashed by movptr()
6036 #endif
6037 push(rax); // save rax,
6038 push(reg); // pass register argument
6039 ExternalAddress buffer((address) b);
6040 // avoid using pushptr, as it modifies scratch registers
6041 // and our contract is not to modify anything
6042 movptr(rax, buffer.addr());
6043 push(rax);
6044 // call indirectly to solve generation ordering problem
6045 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6046 call(rax);
6047 // Caller pops the arguments (oop, message) and restores rax, r10
6048 BLOCK_COMMENT("} verify_oop");
6049 }
6050
6051
6052 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
6053 Register tmp,
6054 int offset) {
6055 intptr_t value = *delayed_value_addr;
6056 if (value != 0)
6057 return RegisterOrConstant(value + offset);
6058
6059 // load indirectly to solve generation ordering problem
6060 movptr(tmp, ExternalAddress((address) delayed_value_addr));
6061
6062 #ifdef ASSERT
6063 { Label L;
6064 testptr(tmp, tmp);
6065 if (WizardMode) {
6066 const char* buf = NULL;
6067 {
6068 ResourceMark rm;
6069 stringStream ss;
6070 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
6071 buf = code_string(ss.as_string());
6072 }
6073 jcc(Assembler::notZero, L);
6074 STOP(buf);
6075 } else {
6076 jccb(Assembler::notZero, L);
6077 hlt();
6078 }
6079 bind(L);
6080 }
6081 #endif
6082
6083 if (offset != 0)
6084 addptr(tmp, offset);
6085
6086 return RegisterOrConstant(tmp);
6087 }
6088
6089
6090 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
6091 int extra_slot_offset) {
6092 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
6093 int stackElementSize = Interpreter::stackElementSize;
6094 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
6095 #ifdef ASSERT
6096 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
6097 assert(offset1 - offset == stackElementSize, "correct arithmetic");
6098 #endif
6099 Register scale_reg = noreg;
6100 Address::ScaleFactor scale_factor = Address::no_scale;
6101 if (arg_slot.is_constant()) {
6102 offset += arg_slot.as_constant() * stackElementSize;
6103 } else {
6104 scale_reg = arg_slot.as_register();
6105 scale_factor = Address::times(stackElementSize);
6106 }
6107 offset += wordSize; // return PC is on stack
6108 return Address(rsp, scale_reg, scale_factor, offset);
6109 }
6110
6111
6112 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
6113 if (!VerifyOops || VerifyAdapterSharing) {
6114 // Below address of the code string confuses VerifyAdapterSharing
6115 // because it may differ between otherwise equivalent adapters.
6116 return;
6117 }
6118
6119 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
6120 // Pass register number to verify_oop_subroutine
6121 const char* b = NULL;
6122 {
6123 ResourceMark rm;
6124 stringStream ss;
6125 ss.print("verify_oop_addr: %s", s);
6126 b = code_string(ss.as_string());
6127 }
6128 #ifdef _LP64
6129 push(rscratch1); // save r10, trashed by movptr()
6130 #endif
6131 push(rax); // save rax,
6132 // addr may contain rsp so we will have to adjust it based on the push
6133 // we just did (and on 64 bit we do two pushes)
6134 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
6135 // stores rax into addr which is backwards of what was intended.
6136 if (addr.uses(rsp)) {
6137 lea(rax, addr);
6138 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
6139 } else {
6140 pushptr(addr);
6141 }
6142
6143 ExternalAddress buffer((address) b);
6144 // pass msg argument
6145 // avoid using pushptr, as it modifies scratch registers
6146 // and our contract is not to modify anything
6147 movptr(rax, buffer.addr());
6148 push(rax);
6149
6150 // call indirectly to solve generation ordering problem
6151 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6152 call(rax);
6153 // Caller pops the arguments (addr, message) and restores rax, r10.
6154 }
6155
6156 void MacroAssembler::verify_tlab() {
6157 #ifdef ASSERT
6158 if (UseTLAB && VerifyOops) {
6159 Label next, ok;
6160 Register t1 = rsi;
6161 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
6162
6163 push(t1);
6164 NOT_LP64(push(thread_reg));
6165 NOT_LP64(get_thread(thread_reg));
6166
6167 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6168 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
6169 jcc(Assembler::aboveEqual, next);
6170 STOP("assert(top >= start)");
6171 should_not_reach_here();
6172
6173 bind(next);
6174 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
6175 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6176 jcc(Assembler::aboveEqual, ok);
6177 STOP("assert(top <= end)");
6178 should_not_reach_here();
6179
6180 bind(ok);
6181 NOT_LP64(pop(thread_reg));
6182 pop(t1);
6183 }
6184 #endif
6185 }
6186
6187 class ControlWord {
6188 public:
6189 int32_t _value;
6190
6191 int rounding_control() const { return (_value >> 10) & 3 ; }
6192 int precision_control() const { return (_value >> 8) & 3 ; }
6193 bool precision() const { return ((_value >> 5) & 1) != 0; }
6194 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6195 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6196 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6197 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6198 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6199
6200 void print() const {
6201 // rounding control
6202 const char* rc;
6203 switch (rounding_control()) {
6204 case 0: rc = "round near"; break;
6205 case 1: rc = "round down"; break;
6206 case 2: rc = "round up "; break;
6207 case 3: rc = "chop "; break;
6208 };
6209 // precision control
6210 const char* pc;
6211 switch (precision_control()) {
6212 case 0: pc = "24 bits "; break;
6213 case 1: pc = "reserved"; break;
6214 case 2: pc = "53 bits "; break;
6215 case 3: pc = "64 bits "; break;
6216 };
6217 // flags
6218 char f[9];
6219 f[0] = ' ';
6220 f[1] = ' ';
6221 f[2] = (precision ()) ? 'P' : 'p';
6222 f[3] = (underflow ()) ? 'U' : 'u';
6223 f[4] = (overflow ()) ? 'O' : 'o';
6224 f[5] = (zero_divide ()) ? 'Z' : 'z';
6225 f[6] = (denormalized()) ? 'D' : 'd';
6226 f[7] = (invalid ()) ? 'I' : 'i';
6227 f[8] = '\x0';
6228 // output
6229 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
6230 }
6231
6232 };
6233
6234 class StatusWord {
6235 public:
6236 int32_t _value;
6237
6238 bool busy() const { return ((_value >> 15) & 1) != 0; }
6239 bool C3() const { return ((_value >> 14) & 1) != 0; }
6240 bool C2() const { return ((_value >> 10) & 1) != 0; }
6241 bool C1() const { return ((_value >> 9) & 1) != 0; }
6242 bool C0() const { return ((_value >> 8) & 1) != 0; }
6243 int top() const { return (_value >> 11) & 7 ; }
6244 bool error_status() const { return ((_value >> 7) & 1) != 0; }
6245 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
6246 bool precision() const { return ((_value >> 5) & 1) != 0; }
6247 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6248 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6249 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6250 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6251 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6252
6253 void print() const {
6254 // condition codes
6255 char c[5];
6256 c[0] = (C3()) ? '3' : '-';
6257 c[1] = (C2()) ? '2' : '-';
6258 c[2] = (C1()) ? '1' : '-';
6259 c[3] = (C0()) ? '0' : '-';
6260 c[4] = '\x0';
6261 // flags
6262 char f[9];
6263 f[0] = (error_status()) ? 'E' : '-';
6264 f[1] = (stack_fault ()) ? 'S' : '-';
6265 f[2] = (precision ()) ? 'P' : '-';
6266 f[3] = (underflow ()) ? 'U' : '-';
6267 f[4] = (overflow ()) ? 'O' : '-';
6268 f[5] = (zero_divide ()) ? 'Z' : '-';
6269 f[6] = (denormalized()) ? 'D' : '-';
6270 f[7] = (invalid ()) ? 'I' : '-';
6271 f[8] = '\x0';
6272 // output
6273 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
6274 }
6275
6276 };
6277
6278 class TagWord {
6279 public:
6280 int32_t _value;
6281
6282 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
6283
6284 void print() const {
6285 printf("%04x", _value & 0xFFFF);
6286 }
6287
6288 };
6289
6290 class FPU_Register {
6291 public:
6292 int32_t _m0;
6293 int32_t _m1;
6294 int16_t _ex;
6295
6296 bool is_indefinite() const {
6297 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
6298 }
6299
6300 void print() const {
6301 char sign = (_ex < 0) ? '-' : '+';
6302 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
6303 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
6304 };
6305
6306 };
6307
6308 class FPU_State {
6309 public:
6310 enum {
6311 register_size = 10,
6312 number_of_registers = 8,
6313 register_mask = 7
6314 };
6315
6316 ControlWord _control_word;
6317 StatusWord _status_word;
6318 TagWord _tag_word;
6319 int32_t _error_offset;
6320 int32_t _error_selector;
6321 int32_t _data_offset;
6322 int32_t _data_selector;
6323 int8_t _register[register_size * number_of_registers];
6324
6325 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
6326 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
6327
6328 const char* tag_as_string(int tag) const {
6329 switch (tag) {
6330 case 0: return "valid";
6331 case 1: return "zero";
6332 case 2: return "special";
6333 case 3: return "empty";
6334 }
6335 ShouldNotReachHere();
6336 return NULL;
6337 }
6338
6339 void print() const {
6340 // print computation registers
6341 { int t = _status_word.top();
6342 for (int i = 0; i < number_of_registers; i++) {
6343 int j = (i - t) & register_mask;
6344 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
6345 st(j)->print();
6346 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
6347 }
6348 }
6349 printf("\n");
6350 // print control registers
6351 printf("ctrl = "); _control_word.print(); printf("\n");
6352 printf("stat = "); _status_word .print(); printf("\n");
6353 printf("tags = "); _tag_word .print(); printf("\n");
6354 }
6355
6356 };
6357
6358 class Flag_Register {
6359 public:
6360 int32_t _value;
6361
6362 bool overflow() const { return ((_value >> 11) & 1) != 0; }
6363 bool direction() const { return ((_value >> 10) & 1) != 0; }
6364 bool sign() const { return ((_value >> 7) & 1) != 0; }
6365 bool zero() const { return ((_value >> 6) & 1) != 0; }
6366 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
6367 bool parity() const { return ((_value >> 2) & 1) != 0; }
6368 bool carry() const { return ((_value >> 0) & 1) != 0; }
6369
6370 void print() const {
6371 // flags
6372 char f[8];
6373 f[0] = (overflow ()) ? 'O' : '-';
6374 f[1] = (direction ()) ? 'D' : '-';
6375 f[2] = (sign ()) ? 'S' : '-';
6376 f[3] = (zero ()) ? 'Z' : '-';
6377 f[4] = (auxiliary_carry()) ? 'A' : '-';
6378 f[5] = (parity ()) ? 'P' : '-';
6379 f[6] = (carry ()) ? 'C' : '-';
6380 f[7] = '\x0';
6381 // output
6382 printf("%08x flags = %s", _value, f);
6383 }
6384
6385 };
6386
6387 class IU_Register {
6388 public:
6389 int32_t _value;
6390
6391 void print() const {
6392 printf("%08x %11d", _value, _value);
6393 }
6394
6395 };
6396
6397 class IU_State {
6398 public:
6399 Flag_Register _eflags;
6400 IU_Register _rdi;
6401 IU_Register _rsi;
6402 IU_Register _rbp;
6403 IU_Register _rsp;
6404 IU_Register _rbx;
6405 IU_Register _rdx;
6406 IU_Register _rcx;
6407 IU_Register _rax;
6408
6409 void print() const {
6410 // computation registers
6411 printf("rax, = "); _rax.print(); printf("\n");
6412 printf("rbx, = "); _rbx.print(); printf("\n");
6413 printf("rcx = "); _rcx.print(); printf("\n");
6414 printf("rdx = "); _rdx.print(); printf("\n");
6415 printf("rdi = "); _rdi.print(); printf("\n");
6416 printf("rsi = "); _rsi.print(); printf("\n");
6417 printf("rbp, = "); _rbp.print(); printf("\n");
6418 printf("rsp = "); _rsp.print(); printf("\n");
6419 printf("\n");
6420 // control registers
6421 printf("flgs = "); _eflags.print(); printf("\n");
6422 }
6423 };
6424
6425
6426 class CPU_State {
6427 public:
6428 FPU_State _fpu_state;
6429 IU_State _iu_state;
6430
6431 void print() const {
6432 printf("--------------------------------------------------\n");
6433 _iu_state .print();
6434 printf("\n");
6435 _fpu_state.print();
6436 printf("--------------------------------------------------\n");
6437 }
6438
6439 };
6440
6441
6442 static void _print_CPU_state(CPU_State* state) {
6443 state->print();
6444 };
6445
6446
6447 void MacroAssembler::print_CPU_state() {
6448 push_CPU_state();
6449 push(rsp); // pass CPU state
6450 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
6451 addptr(rsp, wordSize); // discard argument
6452 pop_CPU_state();
6453 }
6454
6455
6456 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
6457 static int counter = 0;
6458 FPU_State* fs = &state->_fpu_state;
6459 counter++;
6460 // For leaf calls, only verify that the top few elements remain empty.
6461 // We only need 1 empty at the top for C2 code.
6462 if( stack_depth < 0 ) {
6463 if( fs->tag_for_st(7) != 3 ) {
6464 printf("FPR7 not empty\n");
6465 state->print();
6466 assert(false, "error");
6467 return false;
6468 }
6469 return true; // All other stack states do not matter
6470 }
6471
6472 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6473 "bad FPU control word");
6474
6475 // compute stack depth
6476 int i = 0;
6477 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
6478 int d = i;
6479 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6480 // verify findings
6481 if (i != FPU_State::number_of_registers) {
6482 // stack not contiguous
6483 printf("%s: stack not contiguous at ST%d\n", s, i);
6484 state->print();
6485 assert(false, "error");
6486 return false;
6487 }
6488 // check if computed stack depth corresponds to expected stack depth
6489 if (stack_depth < 0) {
6490 // expected stack depth is -stack_depth or less
6491 if (d > -stack_depth) {
6492 // too many elements on the stack
6493 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6494 state->print();
6495 assert(false, "error");
6496 return false;
6497 }
6498 } else {
6499 // expected stack depth is stack_depth
6500 if (d != stack_depth) {
6501 // wrong stack depth
6502 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6503 state->print();
6504 assert(false, "error");
6505 return false;
6506 }
6507 }
6508 // everything is cool
6509 return true;
6510 }
6511
6512
6513 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6514 if (!VerifyFPU) return;
6515 push_CPU_state();
6516 push(rsp); // pass CPU state
6517 ExternalAddress msg((address) s);
6518 // pass message string s
6519 pushptr(msg.addr());
6520 push(stack_depth); // pass stack depth
6521 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6522 addptr(rsp, 3 * wordSize); // discard arguments
6523 // check for error
6524 { Label L;
6525 testl(rax, rax);
6526 jcc(Assembler::notZero, L);
6527 int3(); // break if error condition
6528 bind(L);
6529 }
6530 pop_CPU_state();
6531 }
6532
6533 void MacroAssembler::restore_cpu_control_state_after_jni() {
6534 // Either restore the MXCSR register after returning from the JNI Call
6535 // or verify that it wasn't changed (with -Xcheck:jni flag).
6536 if (VM_Version::supports_sse()) {
6537 if (RestoreMXCSROnJNICalls) {
6538 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6539 } else if (CheckJNICalls) {
6540 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6541 }
6542 }
6543 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6544 vzeroupper();
6545
6546 #ifndef _LP64
6547 // Either restore the x87 floating pointer control word after returning
6548 // from the JNI call or verify that it wasn't changed.
6549 if (CheckJNICalls) {
6550 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6551 }
6552 #endif // _LP64
6553 }
6554
6555 void MacroAssembler::load_mirror(Register mirror, Register method) {
6556 // get mirror
6557 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6558 movptr(mirror, Address(method, Method::const_offset()));
6559 movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
6560 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
6561 movptr(mirror, Address(mirror, mirror_offset));
6562 }
6563
6564 void MacroAssembler::load_klass(Register dst, Register src) {
6565 #ifdef _LP64
6566 if (UseCompressedClassPointers) {
6567 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6568 decode_klass_not_null(dst);
6569 } else
6570 #endif
6571 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6572 }
6573
6574 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6575 load_klass(dst, src);
6576 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6577 }
6578
6579 void MacroAssembler::store_klass(Register dst, Register src) {
6580 #ifdef _LP64
6581 if (UseCompressedClassPointers) {
6582 encode_klass_not_null(src);
6583 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6584 } else
6585 #endif
6586 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6587 }
6588
6589 void MacroAssembler::load_heap_oop(Register dst, Address src) {
6590 #ifdef _LP64
6591 // FIXME: Must change all places where we try to load the klass.
6592 if (UseCompressedOops) {
6593 movl(dst, src);
6594 decode_heap_oop(dst);
6595 } else
6596 #endif
6597 movptr(dst, src);
6598 }
6599
6600 // Doesn't do verfication, generates fixed size code
6601 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
6602 #ifdef _LP64
6603 if (UseCompressedOops) {
6604 movl(dst, src);
6605 decode_heap_oop_not_null(dst);
6606 } else
6607 #endif
6608 movptr(dst, src);
6609 }
6610
6611 void MacroAssembler::store_heap_oop(Address dst, Register src) {
6612 #ifdef _LP64
6613 if (UseCompressedOops) {
6614 assert(!dst.uses(src), "not enough registers");
6615 encode_heap_oop(src);
6616 movl(dst, src);
6617 } else
6618 #endif
6619 movptr(dst, src);
6620 }
6621
6622 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
6623 assert_different_registers(src1, tmp);
6624 #ifdef _LP64
6625 if (UseCompressedOops) {
6626 bool did_push = false;
6627 if (tmp == noreg) {
6628 tmp = rax;
6629 push(tmp);
6630 did_push = true;
6631 assert(!src2.uses(rsp), "can't push");
6632 }
6633 load_heap_oop(tmp, src2);
6634 cmpptr(src1, tmp);
6635 if (did_push) pop(tmp);
6636 } else
6637 #endif
6638 cmpptr(src1, src2);
6639 }
6640
6641 // Used for storing NULLs.
6642 void MacroAssembler::store_heap_oop_null(Address dst) {
6643 #ifdef _LP64
6644 if (UseCompressedOops) {
6645 movl(dst, (int32_t)NULL_WORD);
6646 } else {
6647 movslq(dst, (int32_t)NULL_WORD);
6648 }
6649 #else
6650 movl(dst, (int32_t)NULL_WORD);
6651 #endif
6652 }
6653
6654 #ifdef _LP64
6655 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6656 if (UseCompressedClassPointers) {
6657 // Store to klass gap in destination
6658 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6659 }
6660 }
6661
6662 #ifdef ASSERT
6663 void MacroAssembler::verify_heapbase(const char* msg) {
6664 assert (UseCompressedOops, "should be compressed");
6665 assert (Universe::heap() != NULL, "java heap should be initialized");
6666 if (CheckCompressedOops) {
6667 Label ok;
6668 push(rscratch1); // cmpptr trashes rscratch1
6669 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6670 jcc(Assembler::equal, ok);
6671 STOP(msg);
6672 bind(ok);
6673 pop(rscratch1);
6674 }
6675 }
6676 #endif
6677
6678 // Algorithm must match oop.inline.hpp encode_heap_oop.
6679 void MacroAssembler::encode_heap_oop(Register r) {
6680 #ifdef ASSERT
6681 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6682 #endif
6683 verify_oop(r, "broken oop in encode_heap_oop");
6684 if (Universe::narrow_oop_base() == NULL) {
6685 if (Universe::narrow_oop_shift() != 0) {
6686 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6687 shrq(r, LogMinObjAlignmentInBytes);
6688 }
6689 return;
6690 }
6691 testq(r, r);
6692 cmovq(Assembler::equal, r, r12_heapbase);
6693 subq(r, r12_heapbase);
6694 shrq(r, LogMinObjAlignmentInBytes);
6695 }
6696
6697 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6698 #ifdef ASSERT
6699 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6700 if (CheckCompressedOops) {
6701 Label ok;
6702 testq(r, r);
6703 jcc(Assembler::notEqual, ok);
6704 STOP("null oop passed to encode_heap_oop_not_null");
6705 bind(ok);
6706 }
6707 #endif
6708 verify_oop(r, "broken oop in encode_heap_oop_not_null");
6709 if (Universe::narrow_oop_base() != NULL) {
6710 subq(r, r12_heapbase);
6711 }
6712 if (Universe::narrow_oop_shift() != 0) {
6713 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6714 shrq(r, LogMinObjAlignmentInBytes);
6715 }
6716 }
6717
6718 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6719 #ifdef ASSERT
6720 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6721 if (CheckCompressedOops) {
6722 Label ok;
6723 testq(src, src);
6724 jcc(Assembler::notEqual, ok);
6725 STOP("null oop passed to encode_heap_oop_not_null2");
6726 bind(ok);
6727 }
6728 #endif
6729 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6730 if (dst != src) {
6731 movq(dst, src);
6732 }
6733 if (Universe::narrow_oop_base() != NULL) {
6734 subq(dst, r12_heapbase);
6735 }
6736 if (Universe::narrow_oop_shift() != 0) {
6737 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6738 shrq(dst, LogMinObjAlignmentInBytes);
6739 }
6740 }
6741
6742 void MacroAssembler::decode_heap_oop(Register r) {
6743 #ifdef ASSERT
6744 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6745 #endif
6746 if (Universe::narrow_oop_base() == NULL) {
6747 if (Universe::narrow_oop_shift() != 0) {
6748 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6749 shlq(r, LogMinObjAlignmentInBytes);
6750 }
6751 } else {
6752 Label done;
6753 shlq(r, LogMinObjAlignmentInBytes);
6754 jccb(Assembler::equal, done);
6755 addq(r, r12_heapbase);
6756 bind(done);
6757 }
6758 verify_oop(r, "broken oop in decode_heap_oop");
6759 }
6760
6761 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6762 // Note: it will change flags
6763 assert (UseCompressedOops, "should only be used for compressed headers");
6764 assert (Universe::heap() != NULL, "java heap should be initialized");
6765 // Cannot assert, unverified entry point counts instructions (see .ad file)
6766 // vtableStubs also counts instructions in pd_code_size_limit.
6767 // Also do not verify_oop as this is called by verify_oop.
6768 if (Universe::narrow_oop_shift() != 0) {
6769 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6770 shlq(r, LogMinObjAlignmentInBytes);
6771 if (Universe::narrow_oop_base() != NULL) {
6772 addq(r, r12_heapbase);
6773 }
6774 } else {
6775 assert (Universe::narrow_oop_base() == NULL, "sanity");
6776 }
6777 }
6778
6779 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6780 // Note: it will change flags
6781 assert (UseCompressedOops, "should only be used for compressed headers");
6782 assert (Universe::heap() != NULL, "java heap should be initialized");
6783 // Cannot assert, unverified entry point counts instructions (see .ad file)
6784 // vtableStubs also counts instructions in pd_code_size_limit.
6785 // Also do not verify_oop as this is called by verify_oop.
6786 if (Universe::narrow_oop_shift() != 0) {
6787 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6788 if (LogMinObjAlignmentInBytes == Address::times_8) {
6789 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6790 } else {
6791 if (dst != src) {
6792 movq(dst, src);
6793 }
6794 shlq(dst, LogMinObjAlignmentInBytes);
6795 if (Universe::narrow_oop_base() != NULL) {
6796 addq(dst, r12_heapbase);
6797 }
6798 }
6799 } else {
6800 assert (Universe::narrow_oop_base() == NULL, "sanity");
6801 if (dst != src) {
6802 movq(dst, src);
6803 }
6804 }
6805 }
6806
6807 void MacroAssembler::encode_klass_not_null(Register r) {
6808 if (Universe::narrow_klass_base() != NULL) {
6809 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6810 assert(r != r12_heapbase, "Encoding a klass in r12");
6811 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6812 subq(r, r12_heapbase);
6813 }
6814 if (Universe::narrow_klass_shift() != 0) {
6815 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6816 shrq(r, LogKlassAlignmentInBytes);
6817 }
6818 if (Universe::narrow_klass_base() != NULL) {
6819 reinit_heapbase();
6820 }
6821 }
6822
6823 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6824 if (dst == src) {
6825 encode_klass_not_null(src);
6826 } else {
6827 if (Universe::narrow_klass_base() != NULL) {
6828 mov64(dst, (int64_t)Universe::narrow_klass_base());
6829 negq(dst);
6830 addq(dst, src);
6831 } else {
6832 movptr(dst, src);
6833 }
6834 if (Universe::narrow_klass_shift() != 0) {
6835 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6836 shrq(dst, LogKlassAlignmentInBytes);
6837 }
6838 }
6839 }
6840
6841 // Function instr_size_for_decode_klass_not_null() counts the instructions
6842 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6843 // when (Universe::heap() != NULL). Hence, if the instructions they
6844 // generate change, then this method needs to be updated.
6845 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6846 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6847 if (Universe::narrow_klass_base() != NULL) {
6848 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6849 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6850 } else {
6851 // longest load decode klass function, mov64, leaq
6852 return 16;
6853 }
6854 }
6855
6856 // !!! If the instructions that get generated here change then function
6857 // instr_size_for_decode_klass_not_null() needs to get updated.
6858 void MacroAssembler::decode_klass_not_null(Register r) {
6859 // Note: it will change flags
6860 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6861 assert(r != r12_heapbase, "Decoding a klass in r12");
6862 // Cannot assert, unverified entry point counts instructions (see .ad file)
6863 // vtableStubs also counts instructions in pd_code_size_limit.
6864 // Also do not verify_oop as this is called by verify_oop.
6865 if (Universe::narrow_klass_shift() != 0) {
6866 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6867 shlq(r, LogKlassAlignmentInBytes);
6868 }
6869 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6870 if (Universe::narrow_klass_base() != NULL) {
6871 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6872 addq(r, r12_heapbase);
6873 reinit_heapbase();
6874 }
6875 }
6876
6877 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6878 // Note: it will change flags
6879 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6880 if (dst == src) {
6881 decode_klass_not_null(dst);
6882 } else {
6883 // Cannot assert, unverified entry point counts instructions (see .ad file)
6884 // vtableStubs also counts instructions in pd_code_size_limit.
6885 // Also do not verify_oop as this is called by verify_oop.
6886 mov64(dst, (int64_t)Universe::narrow_klass_base());
6887 if (Universe::narrow_klass_shift() != 0) {
6888 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6889 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6890 leaq(dst, Address(dst, src, Address::times_8, 0));
6891 } else {
6892 addq(dst, src);
6893 }
6894 }
6895 }
6896
6897 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6898 assert (UseCompressedOops, "should only be used for compressed headers");
6899 assert (Universe::heap() != NULL, "java heap should be initialized");
6900 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6901 int oop_index = oop_recorder()->find_index(obj);
6902 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6903 mov_narrow_oop(dst, oop_index, rspec);
6904 }
6905
6906 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6907 assert (UseCompressedOops, "should only be used for compressed headers");
6908 assert (Universe::heap() != NULL, "java heap should be initialized");
6909 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6910 int oop_index = oop_recorder()->find_index(obj);
6911 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6912 mov_narrow_oop(dst, oop_index, rspec);
6913 }
6914
6915 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6916 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6917 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6918 int klass_index = oop_recorder()->find_index(k);
6919 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6920 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6921 }
6922
6923 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6924 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6925 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6926 int klass_index = oop_recorder()->find_index(k);
6927 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6928 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6929 }
6930
6931 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6932 assert (UseCompressedOops, "should only be used for compressed headers");
6933 assert (Universe::heap() != NULL, "java heap should be initialized");
6934 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6935 int oop_index = oop_recorder()->find_index(obj);
6936 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6937 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6938 }
6939
6940 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6941 assert (UseCompressedOops, "should only be used for compressed headers");
6942 assert (Universe::heap() != NULL, "java heap should be initialized");
6943 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6944 int oop_index = oop_recorder()->find_index(obj);
6945 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6946 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6947 }
6948
6949 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6950 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6951 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6952 int klass_index = oop_recorder()->find_index(k);
6953 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6954 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6955 }
6956
6957 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6958 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6959 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6960 int klass_index = oop_recorder()->find_index(k);
6961 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6962 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6963 }
6964
6965 void MacroAssembler::reinit_heapbase() {
6966 if (UseCompressedOops || UseCompressedClassPointers) {
6967 if (Universe::heap() != NULL) {
6968 if (Universe::narrow_oop_base() == NULL) {
6969 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6970 } else {
6971 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6972 }
6973 } else {
6974 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6975 }
6976 }
6977 }
6978
6979 #endif // _LP64
6980
6981
6982 // C2 compiled method's prolog code.
6983 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6984
6985 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6986 // NativeJump::patch_verified_entry will be able to patch out the entry
6987 // code safely. The push to verify stack depth is ok at 5 bytes,
6988 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6989 // stack bang then we must use the 6 byte frame allocation even if
6990 // we have no frame. :-(
6991 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6992
6993 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6994 // Remove word for return addr
6995 framesize -= wordSize;
6996 stack_bang_size -= wordSize;
6997
6998 // Calls to C2R adapters often do not accept exceptional returns.
6999 // We require that their callers must bang for them. But be careful, because
7000 // some VM calls (such as call site linkage) can use several kilobytes of
7001 // stack. But the stack safety zone should account for that.
7002 // See bugs 4446381, 4468289, 4497237.
7003 if (stack_bang_size > 0) {
7004 generate_stack_overflow_check(stack_bang_size);
7005
7006 // We always push rbp, so that on return to interpreter rbp, will be
7007 // restored correctly and we can correct the stack.
7008 push(rbp);
7009 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7010 if (PreserveFramePointer) {
7011 mov(rbp, rsp);
7012 }
7013 // Remove word for ebp
7014 framesize -= wordSize;
7015
7016 // Create frame
7017 if (framesize) {
7018 subptr(rsp, framesize);
7019 }
7020 } else {
7021 // Create frame (force generation of a 4 byte immediate value)
7022 subptr_imm32(rsp, framesize);
7023
7024 // Save RBP register now.
7025 framesize -= wordSize;
7026 movptr(Address(rsp, framesize), rbp);
7027 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7028 if (PreserveFramePointer) {
7029 movptr(rbp, rsp);
7030 if (framesize > 0) {
7031 addptr(rbp, framesize);
7032 }
7033 }
7034 }
7035
7036 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
7037 framesize -= wordSize;
7038 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
7039 }
7040
7041 #ifndef _LP64
7042 // If method sets FPU control word do it now
7043 if (fp_mode_24b) {
7044 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
7045 }
7046 if (UseSSE >= 2 && VerifyFPU) {
7047 verify_FPU(0, "FPU stack must be clean on entry");
7048 }
7049 #endif
7050
7051 #ifdef ASSERT
7052 if (VerifyStackAtCalls) {
7053 Label L;
7054 push(rax);
7055 mov(rax, rsp);
7056 andptr(rax, StackAlignmentInBytes-1);
7057 cmpptr(rax, StackAlignmentInBytes-wordSize);
7058 pop(rax);
7059 jcc(Assembler::equal, L);
7060 STOP("Stack is not properly aligned!");
7061 bind(L);
7062 }
7063 #endif
7064
7065 }
7066
7067 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) {
7068 // cnt - number of qwords (8-byte words).
7069 // base - start address, qword aligned.
7070 // is_large - if optimizers know cnt is larger than InitArrayShortSize
7071 assert(base==rdi, "base register must be edi for rep stos");
7072 assert(tmp==rax, "tmp register must be eax for rep stos");
7073 assert(cnt==rcx, "cnt register must be ecx for rep stos");
7074 assert(InitArrayShortSize % BytesPerLong == 0,
7075 "InitArrayShortSize should be the multiple of BytesPerLong");
7076
7077 Label DONE;
7078
7079 xorptr(tmp, tmp);
7080
7081 if (!is_large) {
7082 Label LOOP, LONG;
7083 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
7084 jccb(Assembler::greater, LONG);
7085
7086 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7087
7088 decrement(cnt);
7089 jccb(Assembler::negative, DONE); // Zero length
7090
7091 // Use individual pointer-sized stores for small counts:
7092 BIND(LOOP);
7093 movptr(Address(base, cnt, Address::times_ptr), tmp);
7094 decrement(cnt);
7095 jccb(Assembler::greaterEqual, LOOP);
7096 jmpb(DONE);
7097
7098 BIND(LONG);
7099 }
7100
7101 // Use longer rep-prefixed ops for non-small counts:
7102 if (UseFastStosb) {
7103 shlptr(cnt, 3); // convert to number of bytes
7104 rep_stosb();
7105 } else {
7106 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7107 rep_stos();
7108 }
7109
7110 BIND(DONE);
7111 }
7112
7113 #ifdef COMPILER2
7114
7115 // IndexOf for constant substrings with size >= 8 chars
7116 // which don't need to be loaded through stack.
7117 void MacroAssembler::string_indexofC8(Register str1, Register str2,
7118 Register cnt1, Register cnt2,
7119 int int_cnt2, Register result,
7120 XMMRegister vec, Register tmp,
7121 int ae) {
7122 ShortBranchVerifier sbv(this);
7123 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7124 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7125
7126 // This method uses the pcmpestri instruction with bound registers
7127 // inputs:
7128 // xmm - substring
7129 // rax - substring length (elements count)
7130 // mem - scanned string
7131 // rdx - string length (elements count)
7132 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7133 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7134 // outputs:
7135 // rcx - matched index in string
7136 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7137 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7138 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7139 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7140 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7141
7142 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
7143 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
7144 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
7145
7146 // Note, inline_string_indexOf() generates checks:
7147 // if (substr.count > string.count) return -1;
7148 // if (substr.count == 0) return 0;
7149 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
7150
7151 // Load substring.
7152 if (ae == StrIntrinsicNode::UL) {
7153 pmovzxbw(vec, Address(str2, 0));
7154 } else {
7155 movdqu(vec, Address(str2, 0));
7156 }
7157 movl(cnt2, int_cnt2);
7158 movptr(result, str1); // string addr
7159
7160 if (int_cnt2 > stride) {
7161 jmpb(SCAN_TO_SUBSTR);
7162
7163 // Reload substr for rescan, this code
7164 // is executed only for large substrings (> 8 chars)
7165 bind(RELOAD_SUBSTR);
7166 if (ae == StrIntrinsicNode::UL) {
7167 pmovzxbw(vec, Address(str2, 0));
7168 } else {
7169 movdqu(vec, Address(str2, 0));
7170 }
7171 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
7172
7173 bind(RELOAD_STR);
7174 // We came here after the beginning of the substring was
7175 // matched but the rest of it was not so we need to search
7176 // again. Start from the next element after the previous match.
7177
7178 // cnt2 is number of substring reminding elements and
7179 // cnt1 is number of string reminding elements when cmp failed.
7180 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
7181 subl(cnt1, cnt2);
7182 addl(cnt1, int_cnt2);
7183 movl(cnt2, int_cnt2); // Now restore cnt2
7184
7185 decrementl(cnt1); // Shift to next element
7186 cmpl(cnt1, cnt2);
7187 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7188
7189 addptr(result, (1<<scale1));
7190
7191 } // (int_cnt2 > 8)
7192
7193 // Scan string for start of substr in 16-byte vectors
7194 bind(SCAN_TO_SUBSTR);
7195 pcmpestri(vec, Address(result, 0), mode);
7196 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7197 subl(cnt1, stride);
7198 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7199 cmpl(cnt1, cnt2);
7200 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7201 addptr(result, 16);
7202 jmpb(SCAN_TO_SUBSTR);
7203
7204 // Found a potential substr
7205 bind(FOUND_CANDIDATE);
7206 // Matched whole vector if first element matched (tmp(rcx) == 0).
7207 if (int_cnt2 == stride) {
7208 jccb(Assembler::overflow, RET_FOUND); // OF == 1
7209 } else { // int_cnt2 > 8
7210 jccb(Assembler::overflow, FOUND_SUBSTR);
7211 }
7212 // After pcmpestri tmp(rcx) contains matched element index
7213 // Compute start addr of substr
7214 lea(result, Address(result, tmp, scale1));
7215
7216 // Make sure string is still long enough
7217 subl(cnt1, tmp);
7218 cmpl(cnt1, cnt2);
7219 if (int_cnt2 == stride) {
7220 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7221 } else { // int_cnt2 > 8
7222 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
7223 }
7224 // Left less then substring.
7225
7226 bind(RET_NOT_FOUND);
7227 movl(result, -1);
7228 jmp(EXIT);
7229
7230 if (int_cnt2 > stride) {
7231 // This code is optimized for the case when whole substring
7232 // is matched if its head is matched.
7233 bind(MATCH_SUBSTR_HEAD);
7234 pcmpestri(vec, Address(result, 0), mode);
7235 // Reload only string if does not match
7236 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
7237
7238 Label CONT_SCAN_SUBSTR;
7239 // Compare the rest of substring (> 8 chars).
7240 bind(FOUND_SUBSTR);
7241 // First 8 chars are already matched.
7242 negptr(cnt2);
7243 addptr(cnt2, stride);
7244
7245 bind(SCAN_SUBSTR);
7246 subl(cnt1, stride);
7247 cmpl(cnt2, -stride); // Do not read beyond substring
7248 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
7249 // Back-up strings to avoid reading beyond substring:
7250 // cnt1 = cnt1 - cnt2 + 8
7251 addl(cnt1, cnt2); // cnt2 is negative
7252 addl(cnt1, stride);
7253 movl(cnt2, stride); negptr(cnt2);
7254 bind(CONT_SCAN_SUBSTR);
7255 if (int_cnt2 < (int)G) {
7256 int tail_off1 = int_cnt2<<scale1;
7257 int tail_off2 = int_cnt2<<scale2;
7258 if (ae == StrIntrinsicNode::UL) {
7259 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
7260 } else {
7261 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
7262 }
7263 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
7264 } else {
7265 // calculate index in register to avoid integer overflow (int_cnt2*2)
7266 movl(tmp, int_cnt2);
7267 addptr(tmp, cnt2);
7268 if (ae == StrIntrinsicNode::UL) {
7269 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
7270 } else {
7271 movdqu(vec, Address(str2, tmp, scale2, 0));
7272 }
7273 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
7274 }
7275 // Need to reload strings pointers if not matched whole vector
7276 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7277 addptr(cnt2, stride);
7278 jcc(Assembler::negative, SCAN_SUBSTR);
7279 // Fall through if found full substring
7280
7281 } // (int_cnt2 > 8)
7282
7283 bind(RET_FOUND);
7284 // Found result if we matched full small substring.
7285 // Compute substr offset
7286 subptr(result, str1);
7287 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7288 shrl(result, 1); // index
7289 }
7290 bind(EXIT);
7291
7292 } // string_indexofC8
7293
7294 // Small strings are loaded through stack if they cross page boundary.
7295 void MacroAssembler::string_indexof(Register str1, Register str2,
7296 Register cnt1, Register cnt2,
7297 int int_cnt2, Register result,
7298 XMMRegister vec, Register tmp,
7299 int ae) {
7300 ShortBranchVerifier sbv(this);
7301 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7302 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7303
7304 //
7305 // int_cnt2 is length of small (< 8 chars) constant substring
7306 // or (-1) for non constant substring in which case its length
7307 // is in cnt2 register.
7308 //
7309 // Note, inline_string_indexOf() generates checks:
7310 // if (substr.count > string.count) return -1;
7311 // if (substr.count == 0) return 0;
7312 //
7313 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7314 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
7315 // This method uses the pcmpestri instruction with bound registers
7316 // inputs:
7317 // xmm - substring
7318 // rax - substring length (elements count)
7319 // mem - scanned string
7320 // rdx - string length (elements count)
7321 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7322 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7323 // outputs:
7324 // rcx - matched index in string
7325 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7326 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7327 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7328 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7329
7330 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
7331 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
7332 FOUND_CANDIDATE;
7333
7334 { //========================================================
7335 // We don't know where these strings are located
7336 // and we can't read beyond them. Load them through stack.
7337 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
7338
7339 movptr(tmp, rsp); // save old SP
7340
7341 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
7342 if (int_cnt2 == (1>>scale2)) { // One byte
7343 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
7344 load_unsigned_byte(result, Address(str2, 0));
7345 movdl(vec, result); // move 32 bits
7346 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
7347 // Not enough header space in 32-bit VM: 12+3 = 15.
7348 movl(result, Address(str2, -1));
7349 shrl(result, 8);
7350 movdl(vec, result); // move 32 bits
7351 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
7352 load_unsigned_short(result, Address(str2, 0));
7353 movdl(vec, result); // move 32 bits
7354 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
7355 movdl(vec, Address(str2, 0)); // move 32 bits
7356 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
7357 movq(vec, Address(str2, 0)); // move 64 bits
7358 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
7359 // Array header size is 12 bytes in 32-bit VM
7360 // + 6 bytes for 3 chars == 18 bytes,
7361 // enough space to load vec and shift.
7362 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
7363 if (ae == StrIntrinsicNode::UL) {
7364 int tail_off = int_cnt2-8;
7365 pmovzxbw(vec, Address(str2, tail_off));
7366 psrldq(vec, -2*tail_off);
7367 }
7368 else {
7369 int tail_off = int_cnt2*(1<<scale2);
7370 movdqu(vec, Address(str2, tail_off-16));
7371 psrldq(vec, 16-tail_off);
7372 }
7373 }
7374 } else { // not constant substring
7375 cmpl(cnt2, stride);
7376 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
7377
7378 // We can read beyond string if srt+16 does not cross page boundary
7379 // since heaps are aligned and mapped by pages.
7380 assert(os::vm_page_size() < (int)G, "default page should be small");
7381 movl(result, str2); // We need only low 32 bits
7382 andl(result, (os::vm_page_size()-1));
7383 cmpl(result, (os::vm_page_size()-16));
7384 jccb(Assembler::belowEqual, CHECK_STR);
7385
7386 // Move small strings to stack to allow load 16 bytes into vec.
7387 subptr(rsp, 16);
7388 int stk_offset = wordSize-(1<<scale2);
7389 push(cnt2);
7390
7391 bind(COPY_SUBSTR);
7392 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
7393 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
7394 movb(Address(rsp, cnt2, scale2, stk_offset), result);
7395 } else if (ae == StrIntrinsicNode::UU) {
7396 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7397 movw(Address(rsp, cnt2, scale2, stk_offset), result);
7398 }
7399 decrement(cnt2);
7400 jccb(Assembler::notZero, COPY_SUBSTR);
7401
7402 pop(cnt2);
7403 movptr(str2, rsp); // New substring address
7404 } // non constant
7405
7406 bind(CHECK_STR);
7407 cmpl(cnt1, stride);
7408 jccb(Assembler::aboveEqual, BIG_STRINGS);
7409
7410 // Check cross page boundary.
7411 movl(result, str1); // We need only low 32 bits
7412 andl(result, (os::vm_page_size()-1));
7413 cmpl(result, (os::vm_page_size()-16));
7414 jccb(Assembler::belowEqual, BIG_STRINGS);
7415
7416 subptr(rsp, 16);
7417 int stk_offset = -(1<<scale1);
7418 if (int_cnt2 < 0) { // not constant
7419 push(cnt2);
7420 stk_offset += wordSize;
7421 }
7422 movl(cnt2, cnt1);
7423
7424 bind(COPY_STR);
7425 if (ae == StrIntrinsicNode::LL) {
7426 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7427 movb(Address(rsp, cnt2, scale1, stk_offset), result);
7428 } else {
7429 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7430 movw(Address(rsp, cnt2, scale1, stk_offset), result);
7431 }
7432 decrement(cnt2);
7433 jccb(Assembler::notZero, COPY_STR);
7434
7435 if (int_cnt2 < 0) { // not constant
7436 pop(cnt2);
7437 }
7438 movptr(str1, rsp); // New string address
7439
7440 bind(BIG_STRINGS);
7441 // Load substring.
7442 if (int_cnt2 < 0) { // -1
7443 if (ae == StrIntrinsicNode::UL) {
7444 pmovzxbw(vec, Address(str2, 0));
7445 } else {
7446 movdqu(vec, Address(str2, 0));
7447 }
7448 push(cnt2); // substr count
7449 push(str2); // substr addr
7450 push(str1); // string addr
7451 } else {
7452 // Small (< 8 chars) constant substrings are loaded already.
7453 movl(cnt2, int_cnt2);
7454 }
7455 push(tmp); // original SP
7456
7457 } // Finished loading
7458
7459 //========================================================
7460 // Start search
7461 //
7462
7463 movptr(result, str1); // string addr
7464
7465 if (int_cnt2 < 0) { // Only for non constant substring
7466 jmpb(SCAN_TO_SUBSTR);
7467
7468 // SP saved at sp+0
7469 // String saved at sp+1*wordSize
7470 // Substr saved at sp+2*wordSize
7471 // Substr count saved at sp+3*wordSize
7472
7473 // Reload substr for rescan, this code
7474 // is executed only for large substrings (> 8 chars)
7475 bind(RELOAD_SUBSTR);
7476 movptr(str2, Address(rsp, 2*wordSize));
7477 movl(cnt2, Address(rsp, 3*wordSize));
7478 if (ae == StrIntrinsicNode::UL) {
7479 pmovzxbw(vec, Address(str2, 0));
7480 } else {
7481 movdqu(vec, Address(str2, 0));
7482 }
7483 // We came here after the beginning of the substring was
7484 // matched but the rest of it was not so we need to search
7485 // again. Start from the next element after the previous match.
7486 subptr(str1, result); // Restore counter
7487 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7488 shrl(str1, 1);
7489 }
7490 addl(cnt1, str1);
7491 decrementl(cnt1); // Shift to next element
7492 cmpl(cnt1, cnt2);
7493 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7494
7495 addptr(result, (1<<scale1));
7496 } // non constant
7497
7498 // Scan string for start of substr in 16-byte vectors
7499 bind(SCAN_TO_SUBSTR);
7500 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7501 pcmpestri(vec, Address(result, 0), mode);
7502 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7503 subl(cnt1, stride);
7504 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7505 cmpl(cnt1, cnt2);
7506 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7507 addptr(result, 16);
7508
7509 bind(ADJUST_STR);
7510 cmpl(cnt1, stride); // Do not read beyond string
7511 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7512 // Back-up string to avoid reading beyond string.
7513 lea(result, Address(result, cnt1, scale1, -16));
7514 movl(cnt1, stride);
7515 jmpb(SCAN_TO_SUBSTR);
7516
7517 // Found a potential substr
7518 bind(FOUND_CANDIDATE);
7519 // After pcmpestri tmp(rcx) contains matched element index
7520
7521 // Make sure string is still long enough
7522 subl(cnt1, tmp);
7523 cmpl(cnt1, cnt2);
7524 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7525 // Left less then substring.
7526
7527 bind(RET_NOT_FOUND);
7528 movl(result, -1);
7529 jmpb(CLEANUP);
7530
7531 bind(FOUND_SUBSTR);
7532 // Compute start addr of substr
7533 lea(result, Address(result, tmp, scale1));
7534 if (int_cnt2 > 0) { // Constant substring
7535 // Repeat search for small substring (< 8 chars)
7536 // from new point without reloading substring.
7537 // Have to check that we don't read beyond string.
7538 cmpl(tmp, stride-int_cnt2);
7539 jccb(Assembler::greater, ADJUST_STR);
7540 // Fall through if matched whole substring.
7541 } else { // non constant
7542 assert(int_cnt2 == -1, "should be != 0");
7543
7544 addl(tmp, cnt2);
7545 // Found result if we matched whole substring.
7546 cmpl(tmp, stride);
7547 jccb(Assembler::lessEqual, RET_FOUND);
7548
7549 // Repeat search for small substring (<= 8 chars)
7550 // from new point 'str1' without reloading substring.
7551 cmpl(cnt2, stride);
7552 // Have to check that we don't read beyond string.
7553 jccb(Assembler::lessEqual, ADJUST_STR);
7554
7555 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7556 // Compare the rest of substring (> 8 chars).
7557 movptr(str1, result);
7558
7559 cmpl(tmp, cnt2);
7560 // First 8 chars are already matched.
7561 jccb(Assembler::equal, CHECK_NEXT);
7562
7563 bind(SCAN_SUBSTR);
7564 pcmpestri(vec, Address(str1, 0), mode);
7565 // Need to reload strings pointers if not matched whole vector
7566 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7567
7568 bind(CHECK_NEXT);
7569 subl(cnt2, stride);
7570 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7571 addptr(str1, 16);
7572 if (ae == StrIntrinsicNode::UL) {
7573 addptr(str2, 8);
7574 } else {
7575 addptr(str2, 16);
7576 }
7577 subl(cnt1, stride);
7578 cmpl(cnt2, stride); // Do not read beyond substring
7579 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7580 // Back-up strings to avoid reading beyond substring.
7581
7582 if (ae == StrIntrinsicNode::UL) {
7583 lea(str2, Address(str2, cnt2, scale2, -8));
7584 lea(str1, Address(str1, cnt2, scale1, -16));
7585 } else {
7586 lea(str2, Address(str2, cnt2, scale2, -16));
7587 lea(str1, Address(str1, cnt2, scale1, -16));
7588 }
7589 subl(cnt1, cnt2);
7590 movl(cnt2, stride);
7591 addl(cnt1, stride);
7592 bind(CONT_SCAN_SUBSTR);
7593 if (ae == StrIntrinsicNode::UL) {
7594 pmovzxbw(vec, Address(str2, 0));
7595 } else {
7596 movdqu(vec, Address(str2, 0));
7597 }
7598 jmp(SCAN_SUBSTR);
7599
7600 bind(RET_FOUND_LONG);
7601 movptr(str1, Address(rsp, wordSize));
7602 } // non constant
7603
7604 bind(RET_FOUND);
7605 // Compute substr offset
7606 subptr(result, str1);
7607 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7608 shrl(result, 1); // index
7609 }
7610 bind(CLEANUP);
7611 pop(rsp); // restore SP
7612
7613 } // string_indexof
7614
7615 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7616 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7617 ShortBranchVerifier sbv(this);
7618 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7619
7620 int stride = 8;
7621
7622 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7623 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7624 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7625 FOUND_SEQ_CHAR, DONE_LABEL;
7626
7627 movptr(result, str1);
7628 if (UseAVX >= 2) {
7629 cmpl(cnt1, stride);
7630 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7631 cmpl(cnt1, 2*stride);
7632 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
7633 movdl(vec1, ch);
7634 vpbroadcastw(vec1, vec1);
7635 vpxor(vec2, vec2);
7636 movl(tmp, cnt1);
7637 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
7638 andl(cnt1,0x0000000F); //tail count (in chars)
7639
7640 bind(SCAN_TO_16_CHAR_LOOP);
7641 vmovdqu(vec3, Address(result, 0));
7642 vpcmpeqw(vec3, vec3, vec1, 1);
7643 vptest(vec2, vec3);
7644 jcc(Assembler::carryClear, FOUND_CHAR);
7645 addptr(result, 32);
7646 subl(tmp, 2*stride);
7647 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7648 jmp(SCAN_TO_8_CHAR);
7649 bind(SCAN_TO_8_CHAR_INIT);
7650 movdl(vec1, ch);
7651 pshuflw(vec1, vec1, 0x00);
7652 pshufd(vec1, vec1, 0);
7653 pxor(vec2, vec2);
7654 }
7655 bind(SCAN_TO_8_CHAR);
7656 cmpl(cnt1, stride);
7657 if (UseAVX >= 2) {
7658 jcc(Assembler::less, SCAN_TO_CHAR);
7659 } else {
7660 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7661 movdl(vec1, ch);
7662 pshuflw(vec1, vec1, 0x00);
7663 pshufd(vec1, vec1, 0);
7664 pxor(vec2, vec2);
7665 }
7666 movl(tmp, cnt1);
7667 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
7668 andl(cnt1,0x00000007); //tail count (in chars)
7669
7670 bind(SCAN_TO_8_CHAR_LOOP);
7671 movdqu(vec3, Address(result, 0));
7672 pcmpeqw(vec3, vec1);
7673 ptest(vec2, vec3);
7674 jcc(Assembler::carryClear, FOUND_CHAR);
7675 addptr(result, 16);
7676 subl(tmp, stride);
7677 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7678 bind(SCAN_TO_CHAR);
7679 testl(cnt1, cnt1);
7680 jcc(Assembler::zero, RET_NOT_FOUND);
7681 bind(SCAN_TO_CHAR_LOOP);
7682 load_unsigned_short(tmp, Address(result, 0));
7683 cmpl(ch, tmp);
7684 jccb(Assembler::equal, FOUND_SEQ_CHAR);
7685 addptr(result, 2);
7686 subl(cnt1, 1);
7687 jccb(Assembler::zero, RET_NOT_FOUND);
7688 jmp(SCAN_TO_CHAR_LOOP);
7689
7690 bind(RET_NOT_FOUND);
7691 movl(result, -1);
7692 jmpb(DONE_LABEL);
7693
7694 bind(FOUND_CHAR);
7695 if (UseAVX >= 2) {
7696 vpmovmskb(tmp, vec3);
7697 } else {
7698 pmovmskb(tmp, vec3);
7699 }
7700 bsfl(ch, tmp);
7701 addl(result, ch);
7702
7703 bind(FOUND_SEQ_CHAR);
7704 subptr(result, str1);
7705 shrl(result, 1);
7706
7707 bind(DONE_LABEL);
7708 } // string_indexof_char
7709
7710 // helper function for string_compare
7711 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7712 Address::ScaleFactor scale, Address::ScaleFactor scale1,
7713 Address::ScaleFactor scale2, Register index, int ae) {
7714 if (ae == StrIntrinsicNode::LL) {
7715 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7716 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7717 } else if (ae == StrIntrinsicNode::UU) {
7718 load_unsigned_short(elem1, Address(str1, index, scale, 0));
7719 load_unsigned_short(elem2, Address(str2, index, scale, 0));
7720 } else {
7721 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7722 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7723 }
7724 }
7725
7726 // Compare strings, used for char[] and byte[].
7727 void MacroAssembler::string_compare(Register str1, Register str2,
7728 Register cnt1, Register cnt2, Register result,
7729 XMMRegister vec1, int ae) {
7730 ShortBranchVerifier sbv(this);
7731 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7732 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
7733 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7734 int stride2x2 = 0x40;
7735 Address::ScaleFactor scale = Address::no_scale;
7736 Address::ScaleFactor scale1 = Address::no_scale;
7737 Address::ScaleFactor scale2 = Address::no_scale;
7738
7739 if (ae != StrIntrinsicNode::LL) {
7740 stride2x2 = 0x20;
7741 }
7742
7743 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7744 shrl(cnt2, 1);
7745 }
7746 // Compute the minimum of the string lengths and the
7747 // difference of the string lengths (stack).
7748 // Do the conditional move stuff
7749 movl(result, cnt1);
7750 subl(cnt1, cnt2);
7751 push(cnt1);
7752 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
7753
7754 // Is the minimum length zero?
7755 testl(cnt2, cnt2);
7756 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7757 if (ae == StrIntrinsicNode::LL) {
7758 // Load first bytes
7759 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
7760 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
7761 } else if (ae == StrIntrinsicNode::UU) {
7762 // Load first characters
7763 load_unsigned_short(result, Address(str1, 0));
7764 load_unsigned_short(cnt1, Address(str2, 0));
7765 } else {
7766 load_unsigned_byte(result, Address(str1, 0));
7767 load_unsigned_short(cnt1, Address(str2, 0));
7768 }
7769 subl(result, cnt1);
7770 jcc(Assembler::notZero, POP_LABEL);
7771
7772 if (ae == StrIntrinsicNode::UU) {
7773 // Divide length by 2 to get number of chars
7774 shrl(cnt2, 1);
7775 }
7776 cmpl(cnt2, 1);
7777 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7778
7779 // Check if the strings start at the same location and setup scale and stride
7780 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7781 cmpptr(str1, str2);
7782 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7783 if (ae == StrIntrinsicNode::LL) {
7784 scale = Address::times_1;
7785 stride = 16;
7786 } else {
7787 scale = Address::times_2;
7788 stride = 8;
7789 }
7790 } else {
7791 scale1 = Address::times_1;
7792 scale2 = Address::times_2;
7793 // scale not used
7794 stride = 8;
7795 }
7796
7797 if (UseAVX >= 2 && UseSSE42Intrinsics) {
7798 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7799 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7800 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7801 Label COMPARE_TAIL_LONG;
7802 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
7803
7804 int pcmpmask = 0x19;
7805 if (ae == StrIntrinsicNode::LL) {
7806 pcmpmask &= ~0x01;
7807 }
7808
7809 // Setup to compare 16-chars (32-bytes) vectors,
7810 // start from first character again because it has aligned address.
7811 if (ae == StrIntrinsicNode::LL) {
7812 stride2 = 32;
7813 } else {
7814 stride2 = 16;
7815 }
7816 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7817 adr_stride = stride << scale;
7818 } else {
7819 adr_stride1 = 8; //stride << scale1;
7820 adr_stride2 = 16; //stride << scale2;
7821 }
7822
7823 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7824 // rax and rdx are used by pcmpestri as elements counters
7825 movl(result, cnt2);
7826 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
7827 jcc(Assembler::zero, COMPARE_TAIL_LONG);
7828
7829 // fast path : compare first 2 8-char vectors.
7830 bind(COMPARE_16_CHARS);
7831 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7832 movdqu(vec1, Address(str1, 0));
7833 } else {
7834 pmovzxbw(vec1, Address(str1, 0));
7835 }
7836 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7837 jccb(Assembler::below, COMPARE_INDEX_CHAR);
7838
7839 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7840 movdqu(vec1, Address(str1, adr_stride));
7841 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7842 } else {
7843 pmovzxbw(vec1, Address(str1, adr_stride1));
7844 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7845 }
7846 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7847 addl(cnt1, stride);
7848
7849 // Compare the characters at index in cnt1
7850 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7851 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7852 subl(result, cnt2);
7853 jmp(POP_LABEL);
7854
7855 // Setup the registers to start vector comparison loop
7856 bind(COMPARE_WIDE_VECTORS);
7857 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7858 lea(str1, Address(str1, result, scale));
7859 lea(str2, Address(str2, result, scale));
7860 } else {
7861 lea(str1, Address(str1, result, scale1));
7862 lea(str2, Address(str2, result, scale2));
7863 }
7864 subl(result, stride2);
7865 subl(cnt2, stride2);
7866 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
7867 negptr(result);
7868
7869 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
7870 bind(COMPARE_WIDE_VECTORS_LOOP);
7871
7872 #ifdef _LP64
7873 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7874 cmpl(cnt2, stride2x2);
7875 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7876 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
7877 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
7878
7879 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7880 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7881 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
7882 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7883 } else {
7884 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
7885 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7886 }
7887 kortestql(k7, k7);
7888 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
7889 addptr(result, stride2x2); // update since we already compared at this addr
7890 subl(cnt2, stride2x2); // and sub the size too
7891 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7892
7893 vpxor(vec1, vec1);
7894 jmpb(COMPARE_WIDE_TAIL);
7895 }//if (VM_Version::supports_avx512vlbw())
7896 #endif // _LP64
7897
7898
7899 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7900 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7901 vmovdqu(vec1, Address(str1, result, scale));
7902 vpxor(vec1, Address(str2, result, scale));
7903 } else {
7904 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
7905 vpxor(vec1, Address(str2, result, scale2));
7906 }
7907 vptest(vec1, vec1);
7908 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
7909 addptr(result, stride2);
7910 subl(cnt2, stride2);
7911 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
7912 // clean upper bits of YMM registers
7913 vpxor(vec1, vec1);
7914
7915 // compare wide vectors tail
7916 bind(COMPARE_WIDE_TAIL);
7917 testptr(result, result);
7918 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7919
7920 movl(result, stride2);
7921 movl(cnt2, result);
7922 negptr(result);
7923 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7924
7925 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
7926 bind(VECTOR_NOT_EQUAL);
7927 // clean upper bits of YMM registers
7928 vpxor(vec1, vec1);
7929 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7930 lea(str1, Address(str1, result, scale));
7931 lea(str2, Address(str2, result, scale));
7932 } else {
7933 lea(str1, Address(str1, result, scale1));
7934 lea(str2, Address(str2, result, scale2));
7935 }
7936 jmp(COMPARE_16_CHARS);
7937
7938 // Compare tail chars, length between 1 to 15 chars
7939 bind(COMPARE_TAIL_LONG);
7940 movl(cnt2, result);
7941 cmpl(cnt2, stride);
7942 jcc(Assembler::less, COMPARE_SMALL_STR);
7943
7944 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7945 movdqu(vec1, Address(str1, 0));
7946 } else {
7947 pmovzxbw(vec1, Address(str1, 0));
7948 }
7949 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7950 jcc(Assembler::below, COMPARE_INDEX_CHAR);
7951 subptr(cnt2, stride);
7952 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7953 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7954 lea(str1, Address(str1, result, scale));
7955 lea(str2, Address(str2, result, scale));
7956 } else {
7957 lea(str1, Address(str1, result, scale1));
7958 lea(str2, Address(str2, result, scale2));
7959 }
7960 negptr(cnt2);
7961 jmpb(WHILE_HEAD_LABEL);
7962
7963 bind(COMPARE_SMALL_STR);
7964 } else if (UseSSE42Intrinsics) {
7965 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
7966 int pcmpmask = 0x19;
7967 // Setup to compare 8-char (16-byte) vectors,
7968 // start from first character again because it has aligned address.
7969 movl(result, cnt2);
7970 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
7971 if (ae == StrIntrinsicNode::LL) {
7972 pcmpmask &= ~0x01;
7973 }
7974 jcc(Assembler::zero, COMPARE_TAIL);
7975 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7976 lea(str1, Address(str1, result, scale));
7977 lea(str2, Address(str2, result, scale));
7978 } else {
7979 lea(str1, Address(str1, result, scale1));
7980 lea(str2, Address(str2, result, scale2));
7981 }
7982 negptr(result);
7983
7984 // pcmpestri
7985 // inputs:
7986 // vec1- substring
7987 // rax - negative string length (elements count)
7988 // mem - scanned string
7989 // rdx - string length (elements count)
7990 // pcmpmask - cmp mode: 11000 (string compare with negated result)
7991 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
7992 // outputs:
7993 // rcx - first mismatched element index
7994 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7995
7996 bind(COMPARE_WIDE_VECTORS);
7997 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7998 movdqu(vec1, Address(str1, result, scale));
7999 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8000 } else {
8001 pmovzxbw(vec1, Address(str1, result, scale1));
8002 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8003 }
8004 // After pcmpestri cnt1(rcx) contains mismatched element index
8005
8006 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
8007 addptr(result, stride);
8008 subptr(cnt2, stride);
8009 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
8010
8011 // compare wide vectors tail
8012 testptr(result, result);
8013 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8014
8015 movl(cnt2, stride);
8016 movl(result, stride);
8017 negptr(result);
8018 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8019 movdqu(vec1, Address(str1, result, scale));
8020 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8021 } else {
8022 pmovzxbw(vec1, Address(str1, result, scale1));
8023 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8024 }
8025 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
8026
8027 // Mismatched characters in the vectors
8028 bind(VECTOR_NOT_EQUAL);
8029 addptr(cnt1, result);
8030 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
8031 subl(result, cnt2);
8032 jmpb(POP_LABEL);
8033
8034 bind(COMPARE_TAIL); // limit is zero
8035 movl(cnt2, result);
8036 // Fallthru to tail compare
8037 }
8038 // Shift str2 and str1 to the end of the arrays, negate min
8039 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8040 lea(str1, Address(str1, cnt2, scale));
8041 lea(str2, Address(str2, cnt2, scale));
8042 } else {
8043 lea(str1, Address(str1, cnt2, scale1));
8044 lea(str2, Address(str2, cnt2, scale2));
8045 }
8046 decrementl(cnt2); // first character was compared already
8047 negptr(cnt2);
8048
8049 // Compare the rest of the elements
8050 bind(WHILE_HEAD_LABEL);
8051 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
8052 subl(result, cnt1);
8053 jccb(Assembler::notZero, POP_LABEL);
8054 increment(cnt2);
8055 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
8056
8057 // Strings are equal up to min length. Return the length difference.
8058 bind(LENGTH_DIFF_LABEL);
8059 pop(result);
8060 if (ae == StrIntrinsicNode::UU) {
8061 // Divide diff by 2 to get number of chars
8062 sarl(result, 1);
8063 }
8064 jmpb(DONE_LABEL);
8065
8066 #ifdef _LP64
8067 if (VM_Version::supports_avx512vlbw()) {
8068
8069 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
8070
8071 kmovql(cnt1, k7);
8072 notq(cnt1);
8073 bsfq(cnt2, cnt1);
8074 if (ae != StrIntrinsicNode::LL) {
8075 // Divide diff by 2 to get number of chars
8076 sarl(cnt2, 1);
8077 }
8078 addq(result, cnt2);
8079 if (ae == StrIntrinsicNode::LL) {
8080 load_unsigned_byte(cnt1, Address(str2, result));
8081 load_unsigned_byte(result, Address(str1, result));
8082 } else if (ae == StrIntrinsicNode::UU) {
8083 load_unsigned_short(cnt1, Address(str2, result, scale));
8084 load_unsigned_short(result, Address(str1, result, scale));
8085 } else {
8086 load_unsigned_short(cnt1, Address(str2, result, scale2));
8087 load_unsigned_byte(result, Address(str1, result, scale1));
8088 }
8089 subl(result, cnt1);
8090 jmpb(POP_LABEL);
8091 }//if (VM_Version::supports_avx512vlbw())
8092 #endif // _LP64
8093
8094 // Discard the stored length difference
8095 bind(POP_LABEL);
8096 pop(cnt1);
8097
8098 // That's it
8099 bind(DONE_LABEL);
8100 if(ae == StrIntrinsicNode::UL) {
8101 negl(result);
8102 }
8103
8104 }
8105
8106 // Search for Non-ASCII character (Negative byte value) in a byte array,
8107 // return true if it has any and false otherwise.
8108 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
8109 // @HotSpotIntrinsicCandidate
8110 // private static boolean hasNegatives(byte[] ba, int off, int len) {
8111 // for (int i = off; i < off + len; i++) {
8112 // if (ba[i] < 0) {
8113 // return true;
8114 // }
8115 // }
8116 // return false;
8117 // }
8118 void MacroAssembler::has_negatives(Register ary1, Register len,
8119 Register result, Register tmp1,
8120 XMMRegister vec1, XMMRegister vec2) {
8121 // rsi: byte array
8122 // rcx: len
8123 // rax: result
8124 ShortBranchVerifier sbv(this);
8125 assert_different_registers(ary1, len, result, tmp1);
8126 assert_different_registers(vec1, vec2);
8127 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
8128
8129 // len == 0
8130 testl(len, len);
8131 jcc(Assembler::zero, FALSE_LABEL);
8132
8133 if ((UseAVX > 2) && // AVX512
8134 VM_Version::supports_avx512vlbw() &&
8135 VM_Version::supports_bmi2()) {
8136
8137 set_vector_masking(); // opening of the stub context for programming mask registers
8138
8139 Label test_64_loop, test_tail;
8140 Register tmp3_aliased = len;
8141
8142 movl(tmp1, len);
8143 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
8144
8145 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
8146 andl(len, ~(64 - 1)); // vector count (in chars)
8147 jccb(Assembler::zero, test_tail);
8148
8149 lea(ary1, Address(ary1, len, Address::times_1));
8150 negptr(len);
8151
8152 bind(test_64_loop);
8153 // Check whether our 64 elements of size byte contain negatives
8154 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
8155 kortestql(k2, k2);
8156 jcc(Assembler::notZero, TRUE_LABEL);
8157
8158 addptr(len, 64);
8159 jccb(Assembler::notZero, test_64_loop);
8160
8161
8162 bind(test_tail);
8163 // bail out when there is nothing to be done
8164 testl(tmp1, -1);
8165 jcc(Assembler::zero, FALSE_LABEL);
8166
8167 // Save k1
8168 kmovql(k3, k1);
8169
8170 // ~(~0 << len) applied up to two times (for 32-bit scenario)
8171 #ifdef _LP64
8172 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
8173 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
8174 notq(tmp3_aliased);
8175 kmovql(k1, tmp3_aliased);
8176 #else
8177 Label k_init;
8178 jmp(k_init);
8179
8180 // We could not read 64-bits from a general purpose register thus we move
8181 // data required to compose 64 1's to the instruction stream
8182 // We emit 64 byte wide series of elements from 0..63 which later on would
8183 // be used as a compare targets with tail count contained in tmp1 register.
8184 // Result would be a k1 register having tmp1 consecutive number or 1
8185 // counting from least significant bit.
8186 address tmp = pc();
8187 emit_int64(0x0706050403020100);
8188 emit_int64(0x0F0E0D0C0B0A0908);
8189 emit_int64(0x1716151413121110);
8190 emit_int64(0x1F1E1D1C1B1A1918);
8191 emit_int64(0x2726252423222120);
8192 emit_int64(0x2F2E2D2C2B2A2928);
8193 emit_int64(0x3736353433323130);
8194 emit_int64(0x3F3E3D3C3B3A3938);
8195
8196 bind(k_init);
8197 lea(len, InternalAddress(tmp));
8198 // create mask to test for negative byte inside a vector
8199 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
8200 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit);
8201
8202 #endif
8203 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit);
8204 ktestq(k2, k1);
8205 // Restore k1
8206 kmovql(k1, k3);
8207 jcc(Assembler::notZero, TRUE_LABEL);
8208
8209 jmp(FALSE_LABEL);
8210
8211 clear_vector_masking(); // closing of the stub context for programming mask registers
8212 } else {
8213 movl(result, len); // copy
8214
8215 if (UseAVX == 2 && UseSSE >= 2) {
8216 // With AVX2, use 32-byte vector compare
8217 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8218
8219 // Compare 32-byte vectors
8220 andl(result, 0x0000001f); // tail count (in bytes)
8221 andl(len, 0xffffffe0); // vector count (in bytes)
8222 jccb(Assembler::zero, COMPARE_TAIL);
8223
8224 lea(ary1, Address(ary1, len, Address::times_1));
8225 negptr(len);
8226
8227 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
8228 movdl(vec2, tmp1);
8229 vpbroadcastd(vec2, vec2);
8230
8231 bind(COMPARE_WIDE_VECTORS);
8232 vmovdqu(vec1, Address(ary1, len, Address::times_1));
8233 vptest(vec1, vec2);
8234 jccb(Assembler::notZero, TRUE_LABEL);
8235 addptr(len, 32);
8236 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8237
8238 testl(result, result);
8239 jccb(Assembler::zero, FALSE_LABEL);
8240
8241 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8242 vptest(vec1, vec2);
8243 jccb(Assembler::notZero, TRUE_LABEL);
8244 jmpb(FALSE_LABEL);
8245
8246 bind(COMPARE_TAIL); // len is zero
8247 movl(len, result);
8248 // Fallthru to tail compare
8249 } else if (UseSSE42Intrinsics) {
8250 // With SSE4.2, use double quad vector compare
8251 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8252
8253 // Compare 16-byte vectors
8254 andl(result, 0x0000000f); // tail count (in bytes)
8255 andl(len, 0xfffffff0); // vector count (in bytes)
8256 jccb(Assembler::zero, COMPARE_TAIL);
8257
8258 lea(ary1, Address(ary1, len, Address::times_1));
8259 negptr(len);
8260
8261 movl(tmp1, 0x80808080);
8262 movdl(vec2, tmp1);
8263 pshufd(vec2, vec2, 0);
8264
8265 bind(COMPARE_WIDE_VECTORS);
8266 movdqu(vec1, Address(ary1, len, Address::times_1));
8267 ptest(vec1, vec2);
8268 jccb(Assembler::notZero, TRUE_LABEL);
8269 addptr(len, 16);
8270 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8271
8272 testl(result, result);
8273 jccb(Assembler::zero, FALSE_LABEL);
8274
8275 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8276 ptest(vec1, vec2);
8277 jccb(Assembler::notZero, TRUE_LABEL);
8278 jmpb(FALSE_LABEL);
8279
8280 bind(COMPARE_TAIL); // len is zero
8281 movl(len, result);
8282 // Fallthru to tail compare
8283 }
8284 }
8285 // Compare 4-byte vectors
8286 andl(len, 0xfffffffc); // vector count (in bytes)
8287 jccb(Assembler::zero, COMPARE_CHAR);
8288
8289 lea(ary1, Address(ary1, len, Address::times_1));
8290 negptr(len);
8291
8292 bind(COMPARE_VECTORS);
8293 movl(tmp1, Address(ary1, len, Address::times_1));
8294 andl(tmp1, 0x80808080);
8295 jccb(Assembler::notZero, TRUE_LABEL);
8296 addptr(len, 4);
8297 jcc(Assembler::notZero, COMPARE_VECTORS);
8298
8299 // Compare trailing char (final 2 bytes), if any
8300 bind(COMPARE_CHAR);
8301 testl(result, 0x2); // tail char
8302 jccb(Assembler::zero, COMPARE_BYTE);
8303 load_unsigned_short(tmp1, Address(ary1, 0));
8304 andl(tmp1, 0x00008080);
8305 jccb(Assembler::notZero, TRUE_LABEL);
8306 subptr(result, 2);
8307 lea(ary1, Address(ary1, 2));
8308
8309 bind(COMPARE_BYTE);
8310 testl(result, 0x1); // tail byte
8311 jccb(Assembler::zero, FALSE_LABEL);
8312 load_unsigned_byte(tmp1, Address(ary1, 0));
8313 andl(tmp1, 0x00000080);
8314 jccb(Assembler::notEqual, TRUE_LABEL);
8315 jmpb(FALSE_LABEL);
8316
8317 bind(TRUE_LABEL);
8318 movl(result, 1); // return true
8319 jmpb(DONE);
8320
8321 bind(FALSE_LABEL);
8322 xorl(result, result); // return false
8323
8324 // That's it
8325 bind(DONE);
8326 if (UseAVX >= 2 && UseSSE >= 2) {
8327 // clean upper bits of YMM registers
8328 vpxor(vec1, vec1);
8329 vpxor(vec2, vec2);
8330 }
8331 }
8332 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
8333 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8334 Register limit, Register result, Register chr,
8335 XMMRegister vec1, XMMRegister vec2, bool is_char) {
8336 ShortBranchVerifier sbv(this);
8337 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
8338
8339 int length_offset = arrayOopDesc::length_offset_in_bytes();
8340 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
8341
8342 if (is_array_equ) {
8343 // Check the input args
8344 cmpptr(ary1, ary2);
8345 jcc(Assembler::equal, TRUE_LABEL);
8346
8347 // Need additional checks for arrays_equals.
8348 testptr(ary1, ary1);
8349 jcc(Assembler::zero, FALSE_LABEL);
8350 testptr(ary2, ary2);
8351 jcc(Assembler::zero, FALSE_LABEL);
8352
8353 // Check the lengths
8354 movl(limit, Address(ary1, length_offset));
8355 cmpl(limit, Address(ary2, length_offset));
8356 jcc(Assembler::notEqual, FALSE_LABEL);
8357 }
8358
8359 // count == 0
8360 testl(limit, limit);
8361 jcc(Assembler::zero, TRUE_LABEL);
8362
8363 if (is_array_equ) {
8364 // Load array address
8365 lea(ary1, Address(ary1, base_offset));
8366 lea(ary2, Address(ary2, base_offset));
8367 }
8368
8369 if (is_array_equ && is_char) {
8370 // arrays_equals when used for char[].
8371 shll(limit, 1); // byte count != 0
8372 }
8373 movl(result, limit); // copy
8374
8375 if (UseAVX >= 2) {
8376 // With AVX2, use 32-byte vector compare
8377 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8378
8379 // Compare 32-byte vectors
8380 andl(result, 0x0000001f); // tail count (in bytes)
8381 andl(limit, 0xffffffe0); // vector count (in bytes)
8382 jcc(Assembler::zero, COMPARE_TAIL);
8383
8384 lea(ary1, Address(ary1, limit, Address::times_1));
8385 lea(ary2, Address(ary2, limit, Address::times_1));
8386 negptr(limit);
8387
8388 bind(COMPARE_WIDE_VECTORS);
8389
8390 #ifdef _LP64
8391 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8392 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
8393
8394 cmpl(limit, -64);
8395 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8396
8397 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8398
8399 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8400 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8401 kortestql(k7, k7);
8402 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8403 addptr(limit, 64); // update since we already compared at this addr
8404 cmpl(limit, -64);
8405 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8406
8407 // At this point we may still need to compare -limit+result bytes.
8408 // We could execute the next two instruction and just continue via non-wide path:
8409 // cmpl(limit, 0);
8410 // jcc(Assembler::equal, COMPARE_TAIL); // true
8411 // But since we stopped at the points ary{1,2}+limit which are
8412 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8413 // (|limit| <= 32 and result < 32),
8414 // we may just compare the last 64 bytes.
8415 //
8416 addptr(result, -64); // it is safe, bc we just came from this area
8417 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8418 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8419 kortestql(k7, k7);
8420 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8421
8422 jmp(TRUE_LABEL);
8423
8424 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8425
8426 }//if (VM_Version::supports_avx512vlbw())
8427 #endif //_LP64
8428
8429 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8430 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8431 vpxor(vec1, vec2);
8432
8433 vptest(vec1, vec1);
8434 jcc(Assembler::notZero, FALSE_LABEL);
8435 addptr(limit, 32);
8436 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8437
8438 testl(result, result);
8439 jcc(Assembler::zero, TRUE_LABEL);
8440
8441 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8442 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8443 vpxor(vec1, vec2);
8444
8445 vptest(vec1, vec1);
8446 jccb(Assembler::notZero, FALSE_LABEL);
8447 jmpb(TRUE_LABEL);
8448
8449 bind(COMPARE_TAIL); // limit is zero
8450 movl(limit, result);
8451 // Fallthru to tail compare
8452 } else if (UseSSE42Intrinsics) {
8453 // With SSE4.2, use double quad vector compare
8454 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8455
8456 // Compare 16-byte vectors
8457 andl(result, 0x0000000f); // tail count (in bytes)
8458 andl(limit, 0xfffffff0); // vector count (in bytes)
8459 jcc(Assembler::zero, COMPARE_TAIL);
8460
8461 lea(ary1, Address(ary1, limit, Address::times_1));
8462 lea(ary2, Address(ary2, limit, Address::times_1));
8463 negptr(limit);
8464
8465 bind(COMPARE_WIDE_VECTORS);
8466 movdqu(vec1, Address(ary1, limit, Address::times_1));
8467 movdqu(vec2, Address(ary2, limit, Address::times_1));
8468 pxor(vec1, vec2);
8469
8470 ptest(vec1, vec1);
8471 jcc(Assembler::notZero, FALSE_LABEL);
8472 addptr(limit, 16);
8473 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8474
8475 testl(result, result);
8476 jcc(Assembler::zero, TRUE_LABEL);
8477
8478 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8479 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8480 pxor(vec1, vec2);
8481
8482 ptest(vec1, vec1);
8483 jccb(Assembler::notZero, FALSE_LABEL);
8484 jmpb(TRUE_LABEL);
8485
8486 bind(COMPARE_TAIL); // limit is zero
8487 movl(limit, result);
8488 // Fallthru to tail compare
8489 }
8490
8491 // Compare 4-byte vectors
8492 andl(limit, 0xfffffffc); // vector count (in bytes)
8493 jccb(Assembler::zero, COMPARE_CHAR);
8494
8495 lea(ary1, Address(ary1, limit, Address::times_1));
8496 lea(ary2, Address(ary2, limit, Address::times_1));
8497 negptr(limit);
8498
8499 bind(COMPARE_VECTORS);
8500 movl(chr, Address(ary1, limit, Address::times_1));
8501 cmpl(chr, Address(ary2, limit, Address::times_1));
8502 jccb(Assembler::notEqual, FALSE_LABEL);
8503 addptr(limit, 4);
8504 jcc(Assembler::notZero, COMPARE_VECTORS);
8505
8506 // Compare trailing char (final 2 bytes), if any
8507 bind(COMPARE_CHAR);
8508 testl(result, 0x2); // tail char
8509 jccb(Assembler::zero, COMPARE_BYTE);
8510 load_unsigned_short(chr, Address(ary1, 0));
8511 load_unsigned_short(limit, Address(ary2, 0));
8512 cmpl(chr, limit);
8513 jccb(Assembler::notEqual, FALSE_LABEL);
8514
8515 if (is_array_equ && is_char) {
8516 bind(COMPARE_BYTE);
8517 } else {
8518 lea(ary1, Address(ary1, 2));
8519 lea(ary2, Address(ary2, 2));
8520
8521 bind(COMPARE_BYTE);
8522 testl(result, 0x1); // tail byte
8523 jccb(Assembler::zero, TRUE_LABEL);
8524 load_unsigned_byte(chr, Address(ary1, 0));
8525 load_unsigned_byte(limit, Address(ary2, 0));
8526 cmpl(chr, limit);
8527 jccb(Assembler::notEqual, FALSE_LABEL);
8528 }
8529 bind(TRUE_LABEL);
8530 movl(result, 1); // return true
8531 jmpb(DONE);
8532
8533 bind(FALSE_LABEL);
8534 xorl(result, result); // return false
8535
8536 // That's it
8537 bind(DONE);
8538 if (UseAVX >= 2) {
8539 // clean upper bits of YMM registers
8540 vpxor(vec1, vec1);
8541 vpxor(vec2, vec2);
8542 }
8543 }
8544
8545 #endif
8546
8547 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8548 Register to, Register value, Register count,
8549 Register rtmp, XMMRegister xtmp) {
8550 ShortBranchVerifier sbv(this);
8551 assert_different_registers(to, value, count, rtmp);
8552 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8553 Label L_fill_2_bytes, L_fill_4_bytes;
8554
8555 int shift = -1;
8556 switch (t) {
8557 case T_BYTE:
8558 shift = 2;
8559 break;
8560 case T_SHORT:
8561 shift = 1;
8562 break;
8563 case T_INT:
8564 shift = 0;
8565 break;
8566 default: ShouldNotReachHere();
8567 }
8568
8569 if (t == T_BYTE) {
8570 andl(value, 0xff);
8571 movl(rtmp, value);
8572 shll(rtmp, 8);
8573 orl(value, rtmp);
8574 }
8575 if (t == T_SHORT) {
8576 andl(value, 0xffff);
8577 }
8578 if (t == T_BYTE || t == T_SHORT) {
8579 movl(rtmp, value);
8580 shll(rtmp, 16);
8581 orl(value, rtmp);
8582 }
8583
8584 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8585 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8586 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8587 // align source address at 4 bytes address boundary
8588 if (t == T_BYTE) {
8589 // One byte misalignment happens only for byte arrays
8590 testptr(to, 1);
8591 jccb(Assembler::zero, L_skip_align1);
8592 movb(Address(to, 0), value);
8593 increment(to);
8594 decrement(count);
8595 BIND(L_skip_align1);
8596 }
8597 // Two bytes misalignment happens only for byte and short (char) arrays
8598 testptr(to, 2);
8599 jccb(Assembler::zero, L_skip_align2);
8600 movw(Address(to, 0), value);
8601 addptr(to, 2);
8602 subl(count, 1<<(shift-1));
8603 BIND(L_skip_align2);
8604 }
8605 if (UseSSE < 2) {
8606 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8607 // Fill 32-byte chunks
8608 subl(count, 8 << shift);
8609 jcc(Assembler::less, L_check_fill_8_bytes);
8610 align(16);
8611
8612 BIND(L_fill_32_bytes_loop);
8613
8614 for (int i = 0; i < 32; i += 4) {
8615 movl(Address(to, i), value);
8616 }
8617
8618 addptr(to, 32);
8619 subl(count, 8 << shift);
8620 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8621 BIND(L_check_fill_8_bytes);
8622 addl(count, 8 << shift);
8623 jccb(Assembler::zero, L_exit);
8624 jmpb(L_fill_8_bytes);
8625
8626 //
8627 // length is too short, just fill qwords
8628 //
8629 BIND(L_fill_8_bytes_loop);
8630 movl(Address(to, 0), value);
8631 movl(Address(to, 4), value);
8632 addptr(to, 8);
8633 BIND(L_fill_8_bytes);
8634 subl(count, 1 << (shift + 1));
8635 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8636 // fall through to fill 4 bytes
8637 } else {
8638 Label L_fill_32_bytes;
8639 if (!UseUnalignedLoadStores) {
8640 // align to 8 bytes, we know we are 4 byte aligned to start
8641 testptr(to, 4);
8642 jccb(Assembler::zero, L_fill_32_bytes);
8643 movl(Address(to, 0), value);
8644 addptr(to, 4);
8645 subl(count, 1<<shift);
8646 }
8647 BIND(L_fill_32_bytes);
8648 {
8649 assert( UseSSE >= 2, "supported cpu only" );
8650 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8651 if (UseAVX > 2) {
8652 movl(rtmp, 0xffff);
8653 kmovwl(k1, rtmp);
8654 }
8655 movdl(xtmp, value);
8656 if (UseAVX > 2 && UseUnalignedLoadStores) {
8657 // Fill 64-byte chunks
8658 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8659 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8660
8661 subl(count, 16 << shift);
8662 jcc(Assembler::less, L_check_fill_32_bytes);
8663 align(16);
8664
8665 BIND(L_fill_64_bytes_loop);
8666 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8667 addptr(to, 64);
8668 subl(count, 16 << shift);
8669 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8670
8671 BIND(L_check_fill_32_bytes);
8672 addl(count, 8 << shift);
8673 jccb(Assembler::less, L_check_fill_8_bytes);
8674 vmovdqu(Address(to, 0), xtmp);
8675 addptr(to, 32);
8676 subl(count, 8 << shift);
8677
8678 BIND(L_check_fill_8_bytes);
8679 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8680 // Fill 64-byte chunks
8681 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8682 vpbroadcastd(xtmp, xtmp);
8683
8684 subl(count, 16 << shift);
8685 jcc(Assembler::less, L_check_fill_32_bytes);
8686 align(16);
8687
8688 BIND(L_fill_64_bytes_loop);
8689 vmovdqu(Address(to, 0), xtmp);
8690 vmovdqu(Address(to, 32), xtmp);
8691 addptr(to, 64);
8692 subl(count, 16 << shift);
8693 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8694
8695 BIND(L_check_fill_32_bytes);
8696 addl(count, 8 << shift);
8697 jccb(Assembler::less, L_check_fill_8_bytes);
8698 vmovdqu(Address(to, 0), xtmp);
8699 addptr(to, 32);
8700 subl(count, 8 << shift);
8701
8702 BIND(L_check_fill_8_bytes);
8703 // clean upper bits of YMM registers
8704 movdl(xtmp, value);
8705 pshufd(xtmp, xtmp, 0);
8706 } else {
8707 // Fill 32-byte chunks
8708 pshufd(xtmp, xtmp, 0);
8709
8710 subl(count, 8 << shift);
8711 jcc(Assembler::less, L_check_fill_8_bytes);
8712 align(16);
8713
8714 BIND(L_fill_32_bytes_loop);
8715
8716 if (UseUnalignedLoadStores) {
8717 movdqu(Address(to, 0), xtmp);
8718 movdqu(Address(to, 16), xtmp);
8719 } else {
8720 movq(Address(to, 0), xtmp);
8721 movq(Address(to, 8), xtmp);
8722 movq(Address(to, 16), xtmp);
8723 movq(Address(to, 24), xtmp);
8724 }
8725
8726 addptr(to, 32);
8727 subl(count, 8 << shift);
8728 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8729
8730 BIND(L_check_fill_8_bytes);
8731 }
8732 addl(count, 8 << shift);
8733 jccb(Assembler::zero, L_exit);
8734 jmpb(L_fill_8_bytes);
8735
8736 //
8737 // length is too short, just fill qwords
8738 //
8739 BIND(L_fill_8_bytes_loop);
8740 movq(Address(to, 0), xtmp);
8741 addptr(to, 8);
8742 BIND(L_fill_8_bytes);
8743 subl(count, 1 << (shift + 1));
8744 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8745 }
8746 }
8747 // fill trailing 4 bytes
8748 BIND(L_fill_4_bytes);
8749 testl(count, 1<<shift);
8750 jccb(Assembler::zero, L_fill_2_bytes);
8751 movl(Address(to, 0), value);
8752 if (t == T_BYTE || t == T_SHORT) {
8753 addptr(to, 4);
8754 BIND(L_fill_2_bytes);
8755 // fill trailing 2 bytes
8756 testl(count, 1<<(shift-1));
8757 jccb(Assembler::zero, L_fill_byte);
8758 movw(Address(to, 0), value);
8759 if (t == T_BYTE) {
8760 addptr(to, 2);
8761 BIND(L_fill_byte);
8762 // fill trailing byte
8763 testl(count, 1);
8764 jccb(Assembler::zero, L_exit);
8765 movb(Address(to, 0), value);
8766 } else {
8767 BIND(L_fill_byte);
8768 }
8769 } else {
8770 BIND(L_fill_2_bytes);
8771 }
8772 BIND(L_exit);
8773 }
8774
8775 // encode char[] to byte[] in ISO_8859_1
8776 //@HotSpotIntrinsicCandidate
8777 //private static int implEncodeISOArray(byte[] sa, int sp,
8778 //byte[] da, int dp, int len) {
8779 // int i = 0;
8780 // for (; i < len; i++) {
8781 // char c = StringUTF16.getChar(sa, sp++);
8782 // if (c > '\u00FF')
8783 // break;
8784 // da[dp++] = (byte)c;
8785 // }
8786 // return i;
8787 //}
8788 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8789 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8790 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8791 Register tmp5, Register result) {
8792
8793 // rsi: src
8794 // rdi: dst
8795 // rdx: len
8796 // rcx: tmp5
8797 // rax: result
8798 ShortBranchVerifier sbv(this);
8799 assert_different_registers(src, dst, len, tmp5, result);
8800 Label L_done, L_copy_1_char, L_copy_1_char_exit;
8801
8802 // set result
8803 xorl(result, result);
8804 // check for zero length
8805 testl(len, len);
8806 jcc(Assembler::zero, L_done);
8807
8808 movl(result, len);
8809
8810 // Setup pointers
8811 lea(src, Address(src, len, Address::times_2)); // char[]
8812 lea(dst, Address(dst, len, Address::times_1)); // byte[]
8813 negptr(len);
8814
8815 if (UseSSE42Intrinsics || UseAVX >= 2) {
8816 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8817 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8818
8819 if (UseAVX >= 2) {
8820 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8821 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8822 movdl(tmp1Reg, tmp5);
8823 vpbroadcastd(tmp1Reg, tmp1Reg);
8824 jmp(L_chars_32_check);
8825
8826 bind(L_copy_32_chars);
8827 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8828 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8829 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8830 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8831 jccb(Assembler::notZero, L_copy_32_chars_exit);
8832 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8833 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8834 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8835
8836 bind(L_chars_32_check);
8837 addptr(len, 32);
8838 jcc(Assembler::lessEqual, L_copy_32_chars);
8839
8840 bind(L_copy_32_chars_exit);
8841 subptr(len, 16);
8842 jccb(Assembler::greater, L_copy_16_chars_exit);
8843
8844 } else if (UseSSE42Intrinsics) {
8845 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8846 movdl(tmp1Reg, tmp5);
8847 pshufd(tmp1Reg, tmp1Reg, 0);
8848 jmpb(L_chars_16_check);
8849 }
8850
8851 bind(L_copy_16_chars);
8852 if (UseAVX >= 2) {
8853 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8854 vptest(tmp2Reg, tmp1Reg);
8855 jcc(Assembler::notZero, L_copy_16_chars_exit);
8856 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8857 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8858 } else {
8859 if (UseAVX > 0) {
8860 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8861 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8862 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8863 } else {
8864 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8865 por(tmp2Reg, tmp3Reg);
8866 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8867 por(tmp2Reg, tmp4Reg);
8868 }
8869 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8870 jccb(Assembler::notZero, L_copy_16_chars_exit);
8871 packuswb(tmp3Reg, tmp4Reg);
8872 }
8873 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8874
8875 bind(L_chars_16_check);
8876 addptr(len, 16);
8877 jcc(Assembler::lessEqual, L_copy_16_chars);
8878
8879 bind(L_copy_16_chars_exit);
8880 if (UseAVX >= 2) {
8881 // clean upper bits of YMM registers
8882 vpxor(tmp2Reg, tmp2Reg);
8883 vpxor(tmp3Reg, tmp3Reg);
8884 vpxor(tmp4Reg, tmp4Reg);
8885 movdl(tmp1Reg, tmp5);
8886 pshufd(tmp1Reg, tmp1Reg, 0);
8887 }
8888 subptr(len, 8);
8889 jccb(Assembler::greater, L_copy_8_chars_exit);
8890
8891 bind(L_copy_8_chars);
8892 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8893 ptest(tmp3Reg, tmp1Reg);
8894 jccb(Assembler::notZero, L_copy_8_chars_exit);
8895 packuswb(tmp3Reg, tmp1Reg);
8896 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8897 addptr(len, 8);
8898 jccb(Assembler::lessEqual, L_copy_8_chars);
8899
8900 bind(L_copy_8_chars_exit);
8901 subptr(len, 8);
8902 jccb(Assembler::zero, L_done);
8903 }
8904
8905 bind(L_copy_1_char);
8906 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
8907 testl(tmp5, 0xff00); // check if Unicode char
8908 jccb(Assembler::notZero, L_copy_1_char_exit);
8909 movb(Address(dst, len, Address::times_1, 0), tmp5);
8910 addptr(len, 1);
8911 jccb(Assembler::less, L_copy_1_char);
8912
8913 bind(L_copy_1_char_exit);
8914 addptr(result, len); // len is negative count of not processed elements
8915
8916 bind(L_done);
8917 }
8918
8919 #ifdef _LP64
8920 /**
8921 * Helper for multiply_to_len().
8922 */
8923 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
8924 addq(dest_lo, src1);
8925 adcq(dest_hi, 0);
8926 addq(dest_lo, src2);
8927 adcq(dest_hi, 0);
8928 }
8929
8930 /**
8931 * Multiply 64 bit by 64 bit first loop.
8932 */
8933 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
8934 Register y, Register y_idx, Register z,
8935 Register carry, Register product,
8936 Register idx, Register kdx) {
8937 //
8938 // jlong carry, x[], y[], z[];
8939 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8940 // huge_128 product = y[idx] * x[xstart] + carry;
8941 // z[kdx] = (jlong)product;
8942 // carry = (jlong)(product >>> 64);
8943 // }
8944 // z[xstart] = carry;
8945 //
8946
8947 Label L_first_loop, L_first_loop_exit;
8948 Label L_one_x, L_one_y, L_multiply;
8949
8950 decrementl(xstart);
8951 jcc(Assembler::negative, L_one_x);
8952
8953 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8954 rorq(x_xstart, 32); // convert big-endian to little-endian
8955
8956 bind(L_first_loop);
8957 decrementl(idx);
8958 jcc(Assembler::negative, L_first_loop_exit);
8959 decrementl(idx);
8960 jcc(Assembler::negative, L_one_y);
8961 movq(y_idx, Address(y, idx, Address::times_4, 0));
8962 rorq(y_idx, 32); // convert big-endian to little-endian
8963 bind(L_multiply);
8964 movq(product, x_xstart);
8965 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
8966 addq(product, carry);
8967 adcq(rdx, 0);
8968 subl(kdx, 2);
8969 movl(Address(z, kdx, Address::times_4, 4), product);
8970 shrq(product, 32);
8971 movl(Address(z, kdx, Address::times_4, 0), product);
8972 movq(carry, rdx);
8973 jmp(L_first_loop);
8974
8975 bind(L_one_y);
8976 movl(y_idx, Address(y, 0));
8977 jmp(L_multiply);
8978
8979 bind(L_one_x);
8980 movl(x_xstart, Address(x, 0));
8981 jmp(L_first_loop);
8982
8983 bind(L_first_loop_exit);
8984 }
8985
8986 /**
8987 * Multiply 64 bit by 64 bit and add 128 bit.
8988 */
8989 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
8990 Register yz_idx, Register idx,
8991 Register carry, Register product, int offset) {
8992 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
8993 // z[kdx] = (jlong)product;
8994
8995 movq(yz_idx, Address(y, idx, Address::times_4, offset));
8996 rorq(yz_idx, 32); // convert big-endian to little-endian
8997 movq(product, x_xstart);
8998 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
8999 movq(yz_idx, Address(z, idx, Address::times_4, offset));
9000 rorq(yz_idx, 32); // convert big-endian to little-endian
9001
9002 add2_with_carry(rdx, product, carry, yz_idx);
9003
9004 movl(Address(z, idx, Address::times_4, offset+4), product);
9005 shrq(product, 32);
9006 movl(Address(z, idx, Address::times_4, offset), product);
9007
9008 }
9009
9010 /**
9011 * Multiply 128 bit by 128 bit. Unrolled inner loop.
9012 */
9013 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
9014 Register yz_idx, Register idx, Register jdx,
9015 Register carry, Register product,
9016 Register carry2) {
9017 // jlong carry, x[], y[], z[];
9018 // int kdx = ystart+1;
9019 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9020 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
9021 // z[kdx+idx+1] = (jlong)product;
9022 // jlong carry2 = (jlong)(product >>> 64);
9023 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
9024 // z[kdx+idx] = (jlong)product;
9025 // carry = (jlong)(product >>> 64);
9026 // }
9027 // idx += 2;
9028 // if (idx > 0) {
9029 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
9030 // z[kdx+idx] = (jlong)product;
9031 // carry = (jlong)(product >>> 64);
9032 // }
9033 //
9034
9035 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9036
9037 movl(jdx, idx);
9038 andl(jdx, 0xFFFFFFFC);
9039 shrl(jdx, 2);
9040
9041 bind(L_third_loop);
9042 subl(jdx, 1);
9043 jcc(Assembler::negative, L_third_loop_exit);
9044 subl(idx, 4);
9045
9046 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
9047 movq(carry2, rdx);
9048
9049 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
9050 movq(carry, rdx);
9051 jmp(L_third_loop);
9052
9053 bind (L_third_loop_exit);
9054
9055 andl (idx, 0x3);
9056 jcc(Assembler::zero, L_post_third_loop_done);
9057
9058 Label L_check_1;
9059 subl(idx, 2);
9060 jcc(Assembler::negative, L_check_1);
9061
9062 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
9063 movq(carry, rdx);
9064
9065 bind (L_check_1);
9066 addl (idx, 0x2);
9067 andl (idx, 0x1);
9068 subl(idx, 1);
9069 jcc(Assembler::negative, L_post_third_loop_done);
9070
9071 movl(yz_idx, Address(y, idx, Address::times_4, 0));
9072 movq(product, x_xstart);
9073 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9074 movl(yz_idx, Address(z, idx, Address::times_4, 0));
9075
9076 add2_with_carry(rdx, product, yz_idx, carry);
9077
9078 movl(Address(z, idx, Address::times_4, 0), product);
9079 shrq(product, 32);
9080
9081 shlq(rdx, 32);
9082 orq(product, rdx);
9083 movq(carry, product);
9084
9085 bind(L_post_third_loop_done);
9086 }
9087
9088 /**
9089 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
9090 *
9091 */
9092 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
9093 Register carry, Register carry2,
9094 Register idx, Register jdx,
9095 Register yz_idx1, Register yz_idx2,
9096 Register tmp, Register tmp3, Register tmp4) {
9097 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
9098
9099 // jlong carry, x[], y[], z[];
9100 // int kdx = ystart+1;
9101 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9102 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
9103 // jlong carry2 = (jlong)(tmp3 >>> 64);
9104 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
9105 // carry = (jlong)(tmp4 >>> 64);
9106 // z[kdx+idx+1] = (jlong)tmp3;
9107 // z[kdx+idx] = (jlong)tmp4;
9108 // }
9109 // idx += 2;
9110 // if (idx > 0) {
9111 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
9112 // z[kdx+idx] = (jlong)yz_idx1;
9113 // carry = (jlong)(yz_idx1 >>> 64);
9114 // }
9115 //
9116
9117 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9118
9119 movl(jdx, idx);
9120 andl(jdx, 0xFFFFFFFC);
9121 shrl(jdx, 2);
9122
9123 bind(L_third_loop);
9124 subl(jdx, 1);
9125 jcc(Assembler::negative, L_third_loop_exit);
9126 subl(idx, 4);
9127
9128 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
9129 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
9130 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
9131 rorxq(yz_idx2, yz_idx2, 32);
9132
9133 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9134 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
9135
9136 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
9137 rorxq(yz_idx1, yz_idx1, 32);
9138 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9139 rorxq(yz_idx2, yz_idx2, 32);
9140
9141 if (VM_Version::supports_adx()) {
9142 adcxq(tmp3, carry);
9143 adoxq(tmp3, yz_idx1);
9144
9145 adcxq(tmp4, tmp);
9146 adoxq(tmp4, yz_idx2);
9147
9148 movl(carry, 0); // does not affect flags
9149 adcxq(carry2, carry);
9150 adoxq(carry2, carry);
9151 } else {
9152 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
9153 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
9154 }
9155 movq(carry, carry2);
9156
9157 movl(Address(z, idx, Address::times_4, 12), tmp3);
9158 shrq(tmp3, 32);
9159 movl(Address(z, idx, Address::times_4, 8), tmp3);
9160
9161 movl(Address(z, idx, Address::times_4, 4), tmp4);
9162 shrq(tmp4, 32);
9163 movl(Address(z, idx, Address::times_4, 0), tmp4);
9164
9165 jmp(L_third_loop);
9166
9167 bind (L_third_loop_exit);
9168
9169 andl (idx, 0x3);
9170 jcc(Assembler::zero, L_post_third_loop_done);
9171
9172 Label L_check_1;
9173 subl(idx, 2);
9174 jcc(Assembler::negative, L_check_1);
9175
9176 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
9177 rorxq(yz_idx1, yz_idx1, 32);
9178 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9179 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9180 rorxq(yz_idx2, yz_idx2, 32);
9181
9182 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
9183
9184 movl(Address(z, idx, Address::times_4, 4), tmp3);
9185 shrq(tmp3, 32);
9186 movl(Address(z, idx, Address::times_4, 0), tmp3);
9187 movq(carry, tmp4);
9188
9189 bind (L_check_1);
9190 addl (idx, 0x2);
9191 andl (idx, 0x1);
9192 subl(idx, 1);
9193 jcc(Assembler::negative, L_post_third_loop_done);
9194 movl(tmp4, Address(y, idx, Address::times_4, 0));
9195 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
9196 movl(tmp4, Address(z, idx, Address::times_4, 0));
9197
9198 add2_with_carry(carry2, tmp3, tmp4, carry);
9199
9200 movl(Address(z, idx, Address::times_4, 0), tmp3);
9201 shrq(tmp3, 32);
9202
9203 shlq(carry2, 32);
9204 orq(tmp3, carry2);
9205 movq(carry, tmp3);
9206
9207 bind(L_post_third_loop_done);
9208 }
9209
9210 /**
9211 * Code for BigInteger::multiplyToLen() instrinsic.
9212 *
9213 * rdi: x
9214 * rax: xlen
9215 * rsi: y
9216 * rcx: ylen
9217 * r8: z
9218 * r11: zlen
9219 * r12: tmp1
9220 * r13: tmp2
9221 * r14: tmp3
9222 * r15: tmp4
9223 * rbx: tmp5
9224 *
9225 */
9226 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
9227 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
9228 ShortBranchVerifier sbv(this);
9229 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
9230
9231 push(tmp1);
9232 push(tmp2);
9233 push(tmp3);
9234 push(tmp4);
9235 push(tmp5);
9236
9237 push(xlen);
9238 push(zlen);
9239
9240 const Register idx = tmp1;
9241 const Register kdx = tmp2;
9242 const Register xstart = tmp3;
9243
9244 const Register y_idx = tmp4;
9245 const Register carry = tmp5;
9246 const Register product = xlen;
9247 const Register x_xstart = zlen; // reuse register
9248
9249 // First Loop.
9250 //
9251 // final static long LONG_MASK = 0xffffffffL;
9252 // int xstart = xlen - 1;
9253 // int ystart = ylen - 1;
9254 // long carry = 0;
9255 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
9256 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
9257 // z[kdx] = (int)product;
9258 // carry = product >>> 32;
9259 // }
9260 // z[xstart] = (int)carry;
9261 //
9262
9263 movl(idx, ylen); // idx = ylen;
9264 movl(kdx, zlen); // kdx = xlen+ylen;
9265 xorq(carry, carry); // carry = 0;
9266
9267 Label L_done;
9268
9269 movl(xstart, xlen);
9270 decrementl(xstart);
9271 jcc(Assembler::negative, L_done);
9272
9273 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
9274
9275 Label L_second_loop;
9276 testl(kdx, kdx);
9277 jcc(Assembler::zero, L_second_loop);
9278
9279 Label L_carry;
9280 subl(kdx, 1);
9281 jcc(Assembler::zero, L_carry);
9282
9283 movl(Address(z, kdx, Address::times_4, 0), carry);
9284 shrq(carry, 32);
9285 subl(kdx, 1);
9286
9287 bind(L_carry);
9288 movl(Address(z, kdx, Address::times_4, 0), carry);
9289
9290 // Second and third (nested) loops.
9291 //
9292 // for (int i = xstart-1; i >= 0; i--) { // Second loop
9293 // carry = 0;
9294 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
9295 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
9296 // (z[k] & LONG_MASK) + carry;
9297 // z[k] = (int)product;
9298 // carry = product >>> 32;
9299 // }
9300 // z[i] = (int)carry;
9301 // }
9302 //
9303 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
9304
9305 const Register jdx = tmp1;
9306
9307 bind(L_second_loop);
9308 xorl(carry, carry); // carry = 0;
9309 movl(jdx, ylen); // j = ystart+1
9310
9311 subl(xstart, 1); // i = xstart-1;
9312 jcc(Assembler::negative, L_done);
9313
9314 push (z);
9315
9316 Label L_last_x;
9317 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
9318 subl(xstart, 1); // i = xstart-1;
9319 jcc(Assembler::negative, L_last_x);
9320
9321 if (UseBMI2Instructions) {
9322 movq(rdx, Address(x, xstart, Address::times_4, 0));
9323 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
9324 } else {
9325 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
9326 rorq(x_xstart, 32); // convert big-endian to little-endian
9327 }
9328
9329 Label L_third_loop_prologue;
9330 bind(L_third_loop_prologue);
9331
9332 push (x);
9333 push (xstart);
9334 push (ylen);
9335
9336
9337 if (UseBMI2Instructions) {
9338 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
9339 } else { // !UseBMI2Instructions
9340 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
9341 }
9342
9343 pop(ylen);
9344 pop(xlen);
9345 pop(x);
9346 pop(z);
9347
9348 movl(tmp3, xlen);
9349 addl(tmp3, 1);
9350 movl(Address(z, tmp3, Address::times_4, 0), carry);
9351 subl(tmp3, 1);
9352 jccb(Assembler::negative, L_done);
9353
9354 shrq(carry, 32);
9355 movl(Address(z, tmp3, Address::times_4, 0), carry);
9356 jmp(L_second_loop);
9357
9358 // Next infrequent code is moved outside loops.
9359 bind(L_last_x);
9360 if (UseBMI2Instructions) {
9361 movl(rdx, Address(x, 0));
9362 } else {
9363 movl(x_xstart, Address(x, 0));
9364 }
9365 jmp(L_third_loop_prologue);
9366
9367 bind(L_done);
9368
9369 pop(zlen);
9370 pop(xlen);
9371
9372 pop(tmp5);
9373 pop(tmp4);
9374 pop(tmp3);
9375 pop(tmp2);
9376 pop(tmp1);
9377 }
9378
9379 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
9380 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
9381 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
9382 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
9383 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
9384 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
9385 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
9386 Label SAME_TILL_END, DONE;
9387 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
9388
9389 //scale is in rcx in both Win64 and Unix
9390 ShortBranchVerifier sbv(this);
9391
9392 shlq(length);
9393 xorq(result, result);
9394
9395 if ((UseAVX > 2) &&
9396 VM_Version::supports_avx512vlbw()) {
9397 set_vector_masking(); // opening of the stub context for programming mask registers
9398 cmpq(length, 64);
9399 jcc(Assembler::less, VECTOR32_TAIL);
9400 movq(tmp1, length);
9401 andq(tmp1, 0x3F); // tail count
9402 andq(length, ~(0x3F)); //vector count
9403
9404 bind(VECTOR64_LOOP);
9405 // AVX512 code to compare 64 byte vectors.
9406 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
9407 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
9408 kortestql(k7, k7);
9409 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
9410 addq(result, 64);
9411 subq(length, 64);
9412 jccb(Assembler::notZero, VECTOR64_LOOP);
9413
9414 //bind(VECTOR64_TAIL);
9415 testq(tmp1, tmp1);
9416 jcc(Assembler::zero, SAME_TILL_END);
9417
9418 bind(VECTOR64_TAIL);
9419 // AVX512 code to compare upto 63 byte vectors.
9420 // Save k1
9421 kmovql(k3, k1);
9422 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
9423 shlxq(tmp2, tmp2, tmp1);
9424 notq(tmp2);
9425 kmovql(k1, tmp2);
9426
9427 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit);
9428 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit);
9429
9430 ktestql(k7, k1);
9431 // Restore k1
9432 kmovql(k1, k3);
9433 jcc(Assembler::below, SAME_TILL_END); // not mismatch
9434
9435 bind(VECTOR64_NOT_EQUAL);
9436 kmovql(tmp1, k7);
9437 notq(tmp1);
9438 tzcntq(tmp1, tmp1);
9439 addq(result, tmp1);
9440 shrq(result);
9441 jmp(DONE);
9442 bind(VECTOR32_TAIL);
9443 clear_vector_masking(); // closing of the stub context for programming mask registers
9444 }
9445
9446 cmpq(length, 8);
9447 jcc(Assembler::equal, VECTOR8_LOOP);
9448 jcc(Assembler::less, VECTOR4_TAIL);
9449
9450 if (UseAVX >= 2) {
9451
9452 cmpq(length, 16);
9453 jcc(Assembler::equal, VECTOR16_LOOP);
9454 jcc(Assembler::less, VECTOR8_LOOP);
9455
9456 cmpq(length, 32);
9457 jccb(Assembler::less, VECTOR16_TAIL);
9458
9459 subq(length, 32);
9460 bind(VECTOR32_LOOP);
9461 vmovdqu(rymm0, Address(obja, result));
9462 vmovdqu(rymm1, Address(objb, result));
9463 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9464 vptest(rymm2, rymm2);
9465 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9466 addq(result, 32);
9467 subq(length, 32);
9468 jccb(Assembler::greaterEqual, VECTOR32_LOOP);
9469 addq(length, 32);
9470 jcc(Assembler::equal, SAME_TILL_END);
9471 //falling through if less than 32 bytes left //close the branch here.
9472
9473 bind(VECTOR16_TAIL);
9474 cmpq(length, 16);
9475 jccb(Assembler::less, VECTOR8_TAIL);
9476 bind(VECTOR16_LOOP);
9477 movdqu(rymm0, Address(obja, result));
9478 movdqu(rymm1, Address(objb, result));
9479 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9480 ptest(rymm2, rymm2);
9481 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9482 addq(result, 16);
9483 subq(length, 16);
9484 jcc(Assembler::equal, SAME_TILL_END);
9485 //falling through if less than 16 bytes left
9486 } else {//regular intrinsics
9487
9488 cmpq(length, 16);
9489 jccb(Assembler::less, VECTOR8_TAIL);
9490
9491 subq(length, 16);
9492 bind(VECTOR16_LOOP);
9493 movdqu(rymm0, Address(obja, result));
9494 movdqu(rymm1, Address(objb, result));
9495 pxor(rymm0, rymm1);
9496 ptest(rymm0, rymm0);
9497 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9498 addq(result, 16);
9499 subq(length, 16);
9500 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9501 addq(length, 16);
9502 jcc(Assembler::equal, SAME_TILL_END);
9503 //falling through if less than 16 bytes left
9504 }
9505
9506 bind(VECTOR8_TAIL);
9507 cmpq(length, 8);
9508 jccb(Assembler::less, VECTOR4_TAIL);
9509 bind(VECTOR8_LOOP);
9510 movq(tmp1, Address(obja, result));
9511 movq(tmp2, Address(objb, result));
9512 xorq(tmp1, tmp2);
9513 testq(tmp1, tmp1);
9514 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9515 addq(result, 8);
9516 subq(length, 8);
9517 jcc(Assembler::equal, SAME_TILL_END);
9518 //falling through if less than 8 bytes left
9519
9520 bind(VECTOR4_TAIL);
9521 cmpq(length, 4);
9522 jccb(Assembler::less, BYTES_TAIL);
9523 bind(VECTOR4_LOOP);
9524 movl(tmp1, Address(obja, result));
9525 xorl(tmp1, Address(objb, result));
9526 testl(tmp1, tmp1);
9527 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9528 addq(result, 4);
9529 subq(length, 4);
9530 jcc(Assembler::equal, SAME_TILL_END);
9531 //falling through if less than 4 bytes left
9532
9533 bind(BYTES_TAIL);
9534 bind(BYTES_LOOP);
9535 load_unsigned_byte(tmp1, Address(obja, result));
9536 load_unsigned_byte(tmp2, Address(objb, result));
9537 xorl(tmp1, tmp2);
9538 testl(tmp1, tmp1);
9539 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9540 decq(length);
9541 jccb(Assembler::zero, SAME_TILL_END);
9542 incq(result);
9543 load_unsigned_byte(tmp1, Address(obja, result));
9544 load_unsigned_byte(tmp2, Address(objb, result));
9545 xorl(tmp1, tmp2);
9546 testl(tmp1, tmp1);
9547 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9548 decq(length);
9549 jccb(Assembler::zero, SAME_TILL_END);
9550 incq(result);
9551 load_unsigned_byte(tmp1, Address(obja, result));
9552 load_unsigned_byte(tmp2, Address(objb, result));
9553 xorl(tmp1, tmp2);
9554 testl(tmp1, tmp1);
9555 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9556 jmpb(SAME_TILL_END);
9557
9558 if (UseAVX >= 2) {
9559 bind(VECTOR32_NOT_EQUAL);
9560 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9561 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9562 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9563 vpmovmskb(tmp1, rymm0);
9564 bsfq(tmp1, tmp1);
9565 addq(result, tmp1);
9566 shrq(result);
9567 jmpb(DONE);
9568 }
9569
9570 bind(VECTOR16_NOT_EQUAL);
9571 if (UseAVX >= 2) {
9572 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9573 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9574 pxor(rymm0, rymm2);
9575 } else {
9576 pcmpeqb(rymm2, rymm2);
9577 pxor(rymm0, rymm1);
9578 pcmpeqb(rymm0, rymm1);
9579 pxor(rymm0, rymm2);
9580 }
9581 pmovmskb(tmp1, rymm0);
9582 bsfq(tmp1, tmp1);
9583 addq(result, tmp1);
9584 shrq(result);
9585 jmpb(DONE);
9586
9587 bind(VECTOR8_NOT_EQUAL);
9588 bind(VECTOR4_NOT_EQUAL);
9589 bsfq(tmp1, tmp1);
9590 shrq(tmp1, 3);
9591 addq(result, tmp1);
9592 bind(BYTES_NOT_EQUAL);
9593 shrq(result);
9594 jmpb(DONE);
9595
9596 bind(SAME_TILL_END);
9597 mov64(result, -1);
9598
9599 bind(DONE);
9600 }
9601
9602 //Helper functions for square_to_len()
9603
9604 /**
9605 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9606 * Preserves x and z and modifies rest of the registers.
9607 */
9608 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9609 // Perform square and right shift by 1
9610 // Handle odd xlen case first, then for even xlen do the following
9611 // jlong carry = 0;
9612 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9613 // huge_128 product = x[j:j+1] * x[j:j+1];
9614 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9615 // z[i+2:i+3] = (jlong)(product >>> 1);
9616 // carry = (jlong)product;
9617 // }
9618
9619 xorq(tmp5, tmp5); // carry
9620 xorq(rdxReg, rdxReg);
9621 xorl(tmp1, tmp1); // index for x
9622 xorl(tmp4, tmp4); // index for z
9623
9624 Label L_first_loop, L_first_loop_exit;
9625
9626 testl(xlen, 1);
9627 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9628
9629 // Square and right shift by 1 the odd element using 32 bit multiply
9630 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9631 imulq(raxReg, raxReg);
9632 shrq(raxReg, 1);
9633 adcq(tmp5, 0);
9634 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9635 incrementl(tmp1);
9636 addl(tmp4, 2);
9637
9638 // Square and right shift by 1 the rest using 64 bit multiply
9639 bind(L_first_loop);
9640 cmpptr(tmp1, xlen);
9641 jccb(Assembler::equal, L_first_loop_exit);
9642
9643 // Square
9644 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
9645 rorq(raxReg, 32); // convert big-endian to little-endian
9646 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
9647
9648 // Right shift by 1 and save carry
9649 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9650 rcrq(rdxReg, 1);
9651 rcrq(raxReg, 1);
9652 adcq(tmp5, 0);
9653
9654 // Store result in z
9655 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9656 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9657
9658 // Update indices for x and z
9659 addl(tmp1, 2);
9660 addl(tmp4, 4);
9661 jmp(L_first_loop);
9662
9663 bind(L_first_loop_exit);
9664 }
9665
9666
9667 /**
9668 * Perform the following multiply add operation using BMI2 instructions
9669 * carry:sum = sum + op1*op2 + carry
9670 * op2 should be in rdx
9671 * op2 is preserved, all other registers are modified
9672 */
9673 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9674 // assert op2 is rdx
9675 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
9676 addq(sum, carry);
9677 adcq(tmp2, 0);
9678 addq(sum, op1);
9679 adcq(tmp2, 0);
9680 movq(carry, tmp2);
9681 }
9682
9683 /**
9684 * Perform the following multiply add operation:
9685 * carry:sum = sum + op1*op2 + carry
9686 * Preserves op1, op2 and modifies rest of registers
9687 */
9688 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9689 // rdx:rax = op1 * op2
9690 movq(raxReg, op2);
9691 mulq(op1);
9692
9693 // rdx:rax = sum + carry + rdx:rax
9694 addq(sum, carry);
9695 adcq(rdxReg, 0);
9696 addq(sum, raxReg);
9697 adcq(rdxReg, 0);
9698
9699 // carry:sum = rdx:sum
9700 movq(carry, rdxReg);
9701 }
9702
9703 /**
9704 * Add 64 bit long carry into z[] with carry propogation.
9705 * Preserves z and carry register values and modifies rest of registers.
9706 *
9707 */
9708 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9709 Label L_fourth_loop, L_fourth_loop_exit;
9710
9711 movl(tmp1, 1);
9712 subl(zlen, 2);
9713 addq(Address(z, zlen, Address::times_4, 0), carry);
9714
9715 bind(L_fourth_loop);
9716 jccb(Assembler::carryClear, L_fourth_loop_exit);
9717 subl(zlen, 2);
9718 jccb(Assembler::negative, L_fourth_loop_exit);
9719 addq(Address(z, zlen, Address::times_4, 0), tmp1);
9720 jmp(L_fourth_loop);
9721 bind(L_fourth_loop_exit);
9722 }
9723
9724 /**
9725 * Shift z[] left by 1 bit.
9726 * Preserves x, len, z and zlen registers and modifies rest of the registers.
9727 *
9728 */
9729 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9730
9731 Label L_fifth_loop, L_fifth_loop_exit;
9732
9733 // Fifth loop
9734 // Perform primitiveLeftShift(z, zlen, 1)
9735
9736 const Register prev_carry = tmp1;
9737 const Register new_carry = tmp4;
9738 const Register value = tmp2;
9739 const Register zidx = tmp3;
9740
9741 // int zidx, carry;
9742 // long value;
9743 // carry = 0;
9744 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9745 // (carry:value) = (z[i] << 1) | carry ;
9746 // z[i] = value;
9747 // }
9748
9749 movl(zidx, zlen);
9750 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9751
9752 bind(L_fifth_loop);
9753 decl(zidx); // Use decl to preserve carry flag
9754 decl(zidx);
9755 jccb(Assembler::negative, L_fifth_loop_exit);
9756
9757 if (UseBMI2Instructions) {
9758 movq(value, Address(z, zidx, Address::times_4, 0));
9759 rclq(value, 1);
9760 rorxq(value, value, 32);
9761 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9762 }
9763 else {
9764 // clear new_carry
9765 xorl(new_carry, new_carry);
9766
9767 // Shift z[i] by 1, or in previous carry and save new carry
9768 movq(value, Address(z, zidx, Address::times_4, 0));
9769 shlq(value, 1);
9770 adcl(new_carry, 0);
9771
9772 orq(value, prev_carry);
9773 rorq(value, 0x20);
9774 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9775
9776 // Set previous carry = new carry
9777 movl(prev_carry, new_carry);
9778 }
9779 jmp(L_fifth_loop);
9780
9781 bind(L_fifth_loop_exit);
9782 }
9783
9784
9785 /**
9786 * Code for BigInteger::squareToLen() intrinsic
9787 *
9788 * rdi: x
9789 * rsi: len
9790 * r8: z
9791 * rcx: zlen
9792 * r12: tmp1
9793 * r13: tmp2
9794 * r14: tmp3
9795 * r15: tmp4
9796 * rbx: tmp5
9797 *
9798 */
9799 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9800
9801 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9802 push(tmp1);
9803 push(tmp2);
9804 push(tmp3);
9805 push(tmp4);
9806 push(tmp5);
9807
9808 // First loop
9809 // Store the squares, right shifted one bit (i.e., divided by 2).
9810 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9811
9812 // Add in off-diagonal sums.
9813 //
9814 // Second, third (nested) and fourth loops.
9815 // zlen +=2;
9816 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9817 // carry = 0;
9818 // long op2 = x[xidx:xidx+1];
9819 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9820 // k -= 2;
9821 // long op1 = x[j:j+1];
9822 // long sum = z[k:k+1];
9823 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9824 // z[k:k+1] = sum;
9825 // }
9826 // add_one_64(z, k, carry, tmp_regs);
9827 // }
9828
9829 const Register carry = tmp5;
9830 const Register sum = tmp3;
9831 const Register op1 = tmp4;
9832 Register op2 = tmp2;
9833
9834 push(zlen);
9835 push(len);
9836 addl(zlen,2);
9837 bind(L_second_loop);
9838 xorq(carry, carry);
9839 subl(zlen, 4);
9840 subl(len, 2);
9841 push(zlen);
9842 push(len);
9843 cmpl(len, 0);
9844 jccb(Assembler::lessEqual, L_second_loop_exit);
9845
9846 // Multiply an array by one 64 bit long.
9847 if (UseBMI2Instructions) {
9848 op2 = rdxReg;
9849 movq(op2, Address(x, len, Address::times_4, 0));
9850 rorxq(op2, op2, 32);
9851 }
9852 else {
9853 movq(op2, Address(x, len, Address::times_4, 0));
9854 rorq(op2, 32);
9855 }
9856
9857 bind(L_third_loop);
9858 decrementl(len);
9859 jccb(Assembler::negative, L_third_loop_exit);
9860 decrementl(len);
9861 jccb(Assembler::negative, L_last_x);
9862
9863 movq(op1, Address(x, len, Address::times_4, 0));
9864 rorq(op1, 32);
9865
9866 bind(L_multiply);
9867 subl(zlen, 2);
9868 movq(sum, Address(z, zlen, Address::times_4, 0));
9869
9870 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9871 if (UseBMI2Instructions) {
9872 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9873 }
9874 else {
9875 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9876 }
9877
9878 movq(Address(z, zlen, Address::times_4, 0), sum);
9879
9880 jmp(L_third_loop);
9881 bind(L_third_loop_exit);
9882
9883 // Fourth loop
9884 // Add 64 bit long carry into z with carry propogation.
9885 // Uses offsetted zlen.
9886 add_one_64(z, zlen, carry, tmp1);
9887
9888 pop(len);
9889 pop(zlen);
9890 jmp(L_second_loop);
9891
9892 // Next infrequent code is moved outside loops.
9893 bind(L_last_x);
9894 movl(op1, Address(x, 0));
9895 jmp(L_multiply);
9896
9897 bind(L_second_loop_exit);
9898 pop(len);
9899 pop(zlen);
9900 pop(len);
9901 pop(zlen);
9902
9903 // Fifth loop
9904 // Shift z left 1 bit.
9905 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
9906
9907 // z[zlen-1] |= x[len-1] & 1;
9908 movl(tmp3, Address(x, len, Address::times_4, -4));
9909 andl(tmp3, 1);
9910 orl(Address(z, zlen, Address::times_4, -4), tmp3);
9911
9912 pop(tmp5);
9913 pop(tmp4);
9914 pop(tmp3);
9915 pop(tmp2);
9916 pop(tmp1);
9917 }
9918
9919 /**
9920 * Helper function for mul_add()
9921 * Multiply the in[] by int k and add to out[] starting at offset offs using
9922 * 128 bit by 32 bit multiply and return the carry in tmp5.
9923 * Only quad int aligned length of in[] is operated on in this function.
9924 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
9925 * This function preserves out, in and k registers.
9926 * len and offset point to the appropriate index in "in" & "out" correspondingly
9927 * tmp5 has the carry.
9928 * other registers are temporary and are modified.
9929 *
9930 */
9931 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
9932 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
9933 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9934
9935 Label L_first_loop, L_first_loop_exit;
9936
9937 movl(tmp1, len);
9938 shrl(tmp1, 2);
9939
9940 bind(L_first_loop);
9941 subl(tmp1, 1);
9942 jccb(Assembler::negative, L_first_loop_exit);
9943
9944 subl(len, 4);
9945 subl(offset, 4);
9946
9947 Register op2 = tmp2;
9948 const Register sum = tmp3;
9949 const Register op1 = tmp4;
9950 const Register carry = tmp5;
9951
9952 if (UseBMI2Instructions) {
9953 op2 = rdxReg;
9954 }
9955
9956 movq(op1, Address(in, len, Address::times_4, 8));
9957 rorq(op1, 32);
9958 movq(sum, Address(out, offset, Address::times_4, 8));
9959 rorq(sum, 32);
9960 if (UseBMI2Instructions) {
9961 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9962 }
9963 else {
9964 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9965 }
9966 // Store back in big endian from little endian
9967 rorq(sum, 0x20);
9968 movq(Address(out, offset, Address::times_4, 8), sum);
9969
9970 movq(op1, Address(in, len, Address::times_4, 0));
9971 rorq(op1, 32);
9972 movq(sum, Address(out, offset, Address::times_4, 0));
9973 rorq(sum, 32);
9974 if (UseBMI2Instructions) {
9975 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9976 }
9977 else {
9978 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9979 }
9980 // Store back in big endian from little endian
9981 rorq(sum, 0x20);
9982 movq(Address(out, offset, Address::times_4, 0), sum);
9983
9984 jmp(L_first_loop);
9985 bind(L_first_loop_exit);
9986 }
9987
9988 /**
9989 * Code for BigInteger::mulAdd() intrinsic
9990 *
9991 * rdi: out
9992 * rsi: in
9993 * r11: offs (out.length - offset)
9994 * rcx: len
9995 * r8: k
9996 * r12: tmp1
9997 * r13: tmp2
9998 * r14: tmp3
9999 * r15: tmp4
10000 * rbx: tmp5
10001 * Multiply the in[] by word k and add to out[], return the carry in rax
10002 */
10003 void MacroAssembler::mul_add(Register out, Register in, Register offs,
10004 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
10005 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
10006
10007 Label L_carry, L_last_in, L_done;
10008
10009 // carry = 0;
10010 // for (int j=len-1; j >= 0; j--) {
10011 // long product = (in[j] & LONG_MASK) * kLong +
10012 // (out[offs] & LONG_MASK) + carry;
10013 // out[offs--] = (int)product;
10014 // carry = product >>> 32;
10015 // }
10016 //
10017 push(tmp1);
10018 push(tmp2);
10019 push(tmp3);
10020 push(tmp4);
10021 push(tmp5);
10022
10023 Register op2 = tmp2;
10024 const Register sum = tmp3;
10025 const Register op1 = tmp4;
10026 const Register carry = tmp5;
10027
10028 if (UseBMI2Instructions) {
10029 op2 = rdxReg;
10030 movl(op2, k);
10031 }
10032 else {
10033 movl(op2, k);
10034 }
10035
10036 xorq(carry, carry);
10037
10038 //First loop
10039
10040 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
10041 //The carry is in tmp5
10042 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
10043
10044 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
10045 decrementl(len);
10046 jccb(Assembler::negative, L_carry);
10047 decrementl(len);
10048 jccb(Assembler::negative, L_last_in);
10049
10050 movq(op1, Address(in, len, Address::times_4, 0));
10051 rorq(op1, 32);
10052
10053 subl(offs, 2);
10054 movq(sum, Address(out, offs, Address::times_4, 0));
10055 rorq(sum, 32);
10056
10057 if (UseBMI2Instructions) {
10058 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10059 }
10060 else {
10061 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10062 }
10063
10064 // Store back in big endian from little endian
10065 rorq(sum, 0x20);
10066 movq(Address(out, offs, Address::times_4, 0), sum);
10067
10068 testl(len, len);
10069 jccb(Assembler::zero, L_carry);
10070
10071 //Multiply the last in[] entry, if any
10072 bind(L_last_in);
10073 movl(op1, Address(in, 0));
10074 movl(sum, Address(out, offs, Address::times_4, -4));
10075
10076 movl(raxReg, k);
10077 mull(op1); //tmp4 * eax -> edx:eax
10078 addl(sum, carry);
10079 adcl(rdxReg, 0);
10080 addl(sum, raxReg);
10081 adcl(rdxReg, 0);
10082 movl(carry, rdxReg);
10083
10084 movl(Address(out, offs, Address::times_4, -4), sum);
10085
10086 bind(L_carry);
10087 //return tmp5/carry as carry in rax
10088 movl(rax, carry);
10089
10090 bind(L_done);
10091 pop(tmp5);
10092 pop(tmp4);
10093 pop(tmp3);
10094 pop(tmp2);
10095 pop(tmp1);
10096 }
10097 #endif
10098
10099 /**
10100 * Emits code to update CRC-32 with a byte value according to constants in table
10101 *
10102 * @param [in,out]crc Register containing the crc.
10103 * @param [in]val Register containing the byte to fold into the CRC.
10104 * @param [in]table Register containing the table of crc constants.
10105 *
10106 * uint32_t crc;
10107 * val = crc_table[(val ^ crc) & 0xFF];
10108 * crc = val ^ (crc >> 8);
10109 *
10110 */
10111 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
10112 xorl(val, crc);
10113 andl(val, 0xFF);
10114 shrl(crc, 8); // unsigned shift
10115 xorl(crc, Address(table, val, Address::times_4, 0));
10116 }
10117
10118 /**
10119 * Fold 128-bit data chunk
10120 */
10121 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
10122 if (UseAVX > 0) {
10123 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
10124 vpclmulldq(xcrc, xK, xcrc); // [63:0]
10125 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
10126 pxor(xcrc, xtmp);
10127 } else {
10128 movdqa(xtmp, xcrc);
10129 pclmulhdq(xtmp, xK); // [123:64]
10130 pclmulldq(xcrc, xK); // [63:0]
10131 pxor(xcrc, xtmp);
10132 movdqu(xtmp, Address(buf, offset));
10133 pxor(xcrc, xtmp);
10134 }
10135 }
10136
10137 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
10138 if (UseAVX > 0) {
10139 vpclmulhdq(xtmp, xK, xcrc);
10140 vpclmulldq(xcrc, xK, xcrc);
10141 pxor(xcrc, xbuf);
10142 pxor(xcrc, xtmp);
10143 } else {
10144 movdqa(xtmp, xcrc);
10145 pclmulhdq(xtmp, xK);
10146 pclmulldq(xcrc, xK);
10147 pxor(xcrc, xbuf);
10148 pxor(xcrc, xtmp);
10149 }
10150 }
10151
10152 /**
10153 * 8-bit folds to compute 32-bit CRC
10154 *
10155 * uint64_t xcrc;
10156 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
10157 */
10158 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
10159 movdl(tmp, xcrc);
10160 andl(tmp, 0xFF);
10161 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
10162 psrldq(xcrc, 1); // unsigned shift one byte
10163 pxor(xcrc, xtmp);
10164 }
10165
10166 /**
10167 * uint32_t crc;
10168 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
10169 */
10170 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
10171 movl(tmp, crc);
10172 andl(tmp, 0xFF);
10173 shrl(crc, 8);
10174 xorl(crc, Address(table, tmp, Address::times_4, 0));
10175 }
10176
10177 /**
10178 * @param crc register containing existing CRC (32-bit)
10179 * @param buf register pointing to input byte buffer (byte*)
10180 * @param len register containing number of bytes
10181 * @param table register that will contain address of CRC table
10182 * @param tmp scratch register
10183 */
10184 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
10185 assert_different_registers(crc, buf, len, table, tmp, rax);
10186
10187 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
10188 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
10189
10190 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
10191 // context for the registers used, where all instructions below are using 128-bit mode
10192 // On EVEX without VL and BW, these instructions will all be AVX.
10193 if (VM_Version::supports_avx512vlbw()) {
10194 movl(tmp, 0xffff);
10195 kmovwl(k1, tmp);
10196 }
10197
10198 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
10199 notl(crc); // ~crc
10200 cmpl(len, 16);
10201 jcc(Assembler::less, L_tail);
10202
10203 // Align buffer to 16 bytes
10204 movl(tmp, buf);
10205 andl(tmp, 0xF);
10206 jccb(Assembler::zero, L_aligned);
10207 subl(tmp, 16);
10208 addl(len, tmp);
10209
10210 align(4);
10211 BIND(L_align_loop);
10212 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10213 update_byte_crc32(crc, rax, table);
10214 increment(buf);
10215 incrementl(tmp);
10216 jccb(Assembler::less, L_align_loop);
10217
10218 BIND(L_aligned);
10219 movl(tmp, len); // save
10220 shrl(len, 4);
10221 jcc(Assembler::zero, L_tail_restore);
10222
10223 // Fold crc into first bytes of vector
10224 movdqa(xmm1, Address(buf, 0));
10225 movdl(rax, xmm1);
10226 xorl(crc, rax);
10227 if (VM_Version::supports_sse4_1()) {
10228 pinsrd(xmm1, crc, 0);
10229 } else {
10230 pinsrw(xmm1, crc, 0);
10231 shrl(crc, 16);
10232 pinsrw(xmm1, crc, 1);
10233 }
10234 addptr(buf, 16);
10235 subl(len, 4); // len > 0
10236 jcc(Assembler::less, L_fold_tail);
10237
10238 movdqa(xmm2, Address(buf, 0));
10239 movdqa(xmm3, Address(buf, 16));
10240 movdqa(xmm4, Address(buf, 32));
10241 addptr(buf, 48);
10242 subl(len, 3);
10243 jcc(Assembler::lessEqual, L_fold_512b);
10244
10245 // Fold total 512 bits of polynomial on each iteration,
10246 // 128 bits per each of 4 parallel streams.
10247 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
10248
10249 align(32);
10250 BIND(L_fold_512b_loop);
10251 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10252 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
10253 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
10254 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
10255 addptr(buf, 64);
10256 subl(len, 4);
10257 jcc(Assembler::greater, L_fold_512b_loop);
10258
10259 // Fold 512 bits to 128 bits.
10260 BIND(L_fold_512b);
10261 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10262 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
10263 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
10264 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
10265
10266 // Fold the rest of 128 bits data chunks
10267 BIND(L_fold_tail);
10268 addl(len, 3);
10269 jccb(Assembler::lessEqual, L_fold_128b);
10270 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10271
10272 BIND(L_fold_tail_loop);
10273 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10274 addptr(buf, 16);
10275 decrementl(len);
10276 jccb(Assembler::greater, L_fold_tail_loop);
10277
10278 // Fold 128 bits in xmm1 down into 32 bits in crc register.
10279 BIND(L_fold_128b);
10280 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
10281 if (UseAVX > 0) {
10282 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
10283 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
10284 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
10285 } else {
10286 movdqa(xmm2, xmm0);
10287 pclmulqdq(xmm2, xmm1, 0x1);
10288 movdqa(xmm3, xmm0);
10289 pand(xmm3, xmm2);
10290 pclmulqdq(xmm0, xmm3, 0x1);
10291 }
10292 psrldq(xmm1, 8);
10293 psrldq(xmm2, 4);
10294 pxor(xmm0, xmm1);
10295 pxor(xmm0, xmm2);
10296
10297 // 8 8-bit folds to compute 32-bit CRC.
10298 for (int j = 0; j < 4; j++) {
10299 fold_8bit_crc32(xmm0, table, xmm1, rax);
10300 }
10301 movdl(crc, xmm0); // mov 32 bits to general register
10302 for (int j = 0; j < 4; j++) {
10303 fold_8bit_crc32(crc, table, rax);
10304 }
10305
10306 BIND(L_tail_restore);
10307 movl(len, tmp); // restore
10308 BIND(L_tail);
10309 andl(len, 0xf);
10310 jccb(Assembler::zero, L_exit);
10311
10312 // Fold the rest of bytes
10313 align(4);
10314 BIND(L_tail_loop);
10315 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10316 update_byte_crc32(crc, rax, table);
10317 increment(buf);
10318 decrementl(len);
10319 jccb(Assembler::greater, L_tail_loop);
10320
10321 BIND(L_exit);
10322 notl(crc); // ~c
10323 }
10324
10325 #ifdef _LP64
10326 // S. Gueron / Information Processing Letters 112 (2012) 184
10327 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
10328 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
10329 // Output: the 64-bit carry-less product of B * CONST
10330 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
10331 Register tmp1, Register tmp2, Register tmp3) {
10332 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10333 if (n > 0) {
10334 addq(tmp3, n * 256 * 8);
10335 }
10336 // Q1 = TABLEExt[n][B & 0xFF];
10337 movl(tmp1, in);
10338 andl(tmp1, 0x000000FF);
10339 shll(tmp1, 3);
10340 addq(tmp1, tmp3);
10341 movq(tmp1, Address(tmp1, 0));
10342
10343 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10344 movl(tmp2, in);
10345 shrl(tmp2, 8);
10346 andl(tmp2, 0x000000FF);
10347 shll(tmp2, 3);
10348 addq(tmp2, tmp3);
10349 movq(tmp2, Address(tmp2, 0));
10350
10351 shlq(tmp2, 8);
10352 xorq(tmp1, tmp2);
10353
10354 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10355 movl(tmp2, in);
10356 shrl(tmp2, 16);
10357 andl(tmp2, 0x000000FF);
10358 shll(tmp2, 3);
10359 addq(tmp2, tmp3);
10360 movq(tmp2, Address(tmp2, 0));
10361
10362 shlq(tmp2, 16);
10363 xorq(tmp1, tmp2);
10364
10365 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10366 shrl(in, 24);
10367 andl(in, 0x000000FF);
10368 shll(in, 3);
10369 addq(in, tmp3);
10370 movq(in, Address(in, 0));
10371
10372 shlq(in, 24);
10373 xorq(in, tmp1);
10374 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10375 }
10376
10377 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10378 Register in_out,
10379 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10380 XMMRegister w_xtmp2,
10381 Register tmp1,
10382 Register n_tmp2, Register n_tmp3) {
10383 if (is_pclmulqdq_supported) {
10384 movdl(w_xtmp1, in_out); // modified blindly
10385
10386 movl(tmp1, const_or_pre_comp_const_index);
10387 movdl(w_xtmp2, tmp1);
10388 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10389
10390 movdq(in_out, w_xtmp1);
10391 } else {
10392 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10393 }
10394 }
10395
10396 // Recombination Alternative 2: No bit-reflections
10397 // T1 = (CRC_A * U1) << 1
10398 // T2 = (CRC_B * U2) << 1
10399 // C1 = T1 >> 32
10400 // C2 = T2 >> 32
10401 // T1 = T1 & 0xFFFFFFFF
10402 // T2 = T2 & 0xFFFFFFFF
10403 // T1 = CRC32(0, T1)
10404 // T2 = CRC32(0, T2)
10405 // C1 = C1 ^ T1
10406 // C2 = C2 ^ T2
10407 // CRC = C1 ^ C2 ^ CRC_C
10408 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10409 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10410 Register tmp1, Register tmp2,
10411 Register n_tmp3) {
10412 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10413 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10414 shlq(in_out, 1);
10415 movl(tmp1, in_out);
10416 shrq(in_out, 32);
10417 xorl(tmp2, tmp2);
10418 crc32(tmp2, tmp1, 4);
10419 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10420 shlq(in1, 1);
10421 movl(tmp1, in1);
10422 shrq(in1, 32);
10423 xorl(tmp2, tmp2);
10424 crc32(tmp2, tmp1, 4);
10425 xorl(in1, tmp2);
10426 xorl(in_out, in1);
10427 xorl(in_out, in2);
10428 }
10429
10430 // Set N to predefined value
10431 // Subtract from a lenght of a buffer
10432 // execute in a loop:
10433 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10434 // for i = 1 to N do
10435 // CRC_A = CRC32(CRC_A, A[i])
10436 // CRC_B = CRC32(CRC_B, B[i])
10437 // CRC_C = CRC32(CRC_C, C[i])
10438 // end for
10439 // Recombine
10440 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10441 Register in_out1, Register in_out2, Register in_out3,
10442 Register tmp1, Register tmp2, Register tmp3,
10443 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10444 Register tmp4, Register tmp5,
10445 Register n_tmp6) {
10446 Label L_processPartitions;
10447 Label L_processPartition;
10448 Label L_exit;
10449
10450 bind(L_processPartitions);
10451 cmpl(in_out1, 3 * size);
10452 jcc(Assembler::less, L_exit);
10453 xorl(tmp1, tmp1);
10454 xorl(tmp2, tmp2);
10455 movq(tmp3, in_out2);
10456 addq(tmp3, size);
10457
10458 bind(L_processPartition);
10459 crc32(in_out3, Address(in_out2, 0), 8);
10460 crc32(tmp1, Address(in_out2, size), 8);
10461 crc32(tmp2, Address(in_out2, size * 2), 8);
10462 addq(in_out2, 8);
10463 cmpq(in_out2, tmp3);
10464 jcc(Assembler::less, L_processPartition);
10465 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10466 w_xtmp1, w_xtmp2, w_xtmp3,
10467 tmp4, tmp5,
10468 n_tmp6);
10469 addq(in_out2, 2 * size);
10470 subl(in_out1, 3 * size);
10471 jmp(L_processPartitions);
10472
10473 bind(L_exit);
10474 }
10475 #else
10476 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10477 Register tmp1, Register tmp2, Register tmp3,
10478 XMMRegister xtmp1, XMMRegister xtmp2) {
10479 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10480 if (n > 0) {
10481 addl(tmp3, n * 256 * 8);
10482 }
10483 // Q1 = TABLEExt[n][B & 0xFF];
10484 movl(tmp1, in_out);
10485 andl(tmp1, 0x000000FF);
10486 shll(tmp1, 3);
10487 addl(tmp1, tmp3);
10488 movq(xtmp1, Address(tmp1, 0));
10489
10490 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10491 movl(tmp2, in_out);
10492 shrl(tmp2, 8);
10493 andl(tmp2, 0x000000FF);
10494 shll(tmp2, 3);
10495 addl(tmp2, tmp3);
10496 movq(xtmp2, Address(tmp2, 0));
10497
10498 psllq(xtmp2, 8);
10499 pxor(xtmp1, xtmp2);
10500
10501 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10502 movl(tmp2, in_out);
10503 shrl(tmp2, 16);
10504 andl(tmp2, 0x000000FF);
10505 shll(tmp2, 3);
10506 addl(tmp2, tmp3);
10507 movq(xtmp2, Address(tmp2, 0));
10508
10509 psllq(xtmp2, 16);
10510 pxor(xtmp1, xtmp2);
10511
10512 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10513 shrl(in_out, 24);
10514 andl(in_out, 0x000000FF);
10515 shll(in_out, 3);
10516 addl(in_out, tmp3);
10517 movq(xtmp2, Address(in_out, 0));
10518
10519 psllq(xtmp2, 24);
10520 pxor(xtmp1, xtmp2); // Result in CXMM
10521 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10522 }
10523
10524 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10525 Register in_out,
10526 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10527 XMMRegister w_xtmp2,
10528 Register tmp1,
10529 Register n_tmp2, Register n_tmp3) {
10530 if (is_pclmulqdq_supported) {
10531 movdl(w_xtmp1, in_out);
10532
10533 movl(tmp1, const_or_pre_comp_const_index);
10534 movdl(w_xtmp2, tmp1);
10535 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10536 // Keep result in XMM since GPR is 32 bit in length
10537 } else {
10538 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10539 }
10540 }
10541
10542 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10543 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10544 Register tmp1, Register tmp2,
10545 Register n_tmp3) {
10546 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10547 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10548
10549 psllq(w_xtmp1, 1);
10550 movdl(tmp1, w_xtmp1);
10551 psrlq(w_xtmp1, 32);
10552 movdl(in_out, w_xtmp1);
10553
10554 xorl(tmp2, tmp2);
10555 crc32(tmp2, tmp1, 4);
10556 xorl(in_out, tmp2);
10557
10558 psllq(w_xtmp2, 1);
10559 movdl(tmp1, w_xtmp2);
10560 psrlq(w_xtmp2, 32);
10561 movdl(in1, w_xtmp2);
10562
10563 xorl(tmp2, tmp2);
10564 crc32(tmp2, tmp1, 4);
10565 xorl(in1, tmp2);
10566 xorl(in_out, in1);
10567 xorl(in_out, in2);
10568 }
10569
10570 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10571 Register in_out1, Register in_out2, Register in_out3,
10572 Register tmp1, Register tmp2, Register tmp3,
10573 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10574 Register tmp4, Register tmp5,
10575 Register n_tmp6) {
10576 Label L_processPartitions;
10577 Label L_processPartition;
10578 Label L_exit;
10579
10580 bind(L_processPartitions);
10581 cmpl(in_out1, 3 * size);
10582 jcc(Assembler::less, L_exit);
10583 xorl(tmp1, tmp1);
10584 xorl(tmp2, tmp2);
10585 movl(tmp3, in_out2);
10586 addl(tmp3, size);
10587
10588 bind(L_processPartition);
10589 crc32(in_out3, Address(in_out2, 0), 4);
10590 crc32(tmp1, Address(in_out2, size), 4);
10591 crc32(tmp2, Address(in_out2, size*2), 4);
10592 crc32(in_out3, Address(in_out2, 0+4), 4);
10593 crc32(tmp1, Address(in_out2, size+4), 4);
10594 crc32(tmp2, Address(in_out2, size*2+4), 4);
10595 addl(in_out2, 8);
10596 cmpl(in_out2, tmp3);
10597 jcc(Assembler::less, L_processPartition);
10598
10599 push(tmp3);
10600 push(in_out1);
10601 push(in_out2);
10602 tmp4 = tmp3;
10603 tmp5 = in_out1;
10604 n_tmp6 = in_out2;
10605
10606 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10607 w_xtmp1, w_xtmp2, w_xtmp3,
10608 tmp4, tmp5,
10609 n_tmp6);
10610
10611 pop(in_out2);
10612 pop(in_out1);
10613 pop(tmp3);
10614
10615 addl(in_out2, 2 * size);
10616 subl(in_out1, 3 * size);
10617 jmp(L_processPartitions);
10618
10619 bind(L_exit);
10620 }
10621 #endif //LP64
10622
10623 #ifdef _LP64
10624 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10625 // Input: A buffer I of L bytes.
10626 // Output: the CRC32C value of the buffer.
10627 // Notations:
10628 // Write L = 24N + r, with N = floor (L/24).
10629 // r = L mod 24 (0 <= r < 24).
10630 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10631 // N quadwords, and R consists of r bytes.
10632 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10633 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10634 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10635 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10636 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10637 Register tmp1, Register tmp2, Register tmp3,
10638 Register tmp4, Register tmp5, Register tmp6,
10639 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10640 bool is_pclmulqdq_supported) {
10641 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10642 Label L_wordByWord;
10643 Label L_byteByByteProlog;
10644 Label L_byteByByte;
10645 Label L_exit;
10646
10647 if (is_pclmulqdq_supported ) {
10648 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10649 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10650
10651 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10652 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10653
10654 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10655 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10656 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10657 } else {
10658 const_or_pre_comp_const_index[0] = 1;
10659 const_or_pre_comp_const_index[1] = 0;
10660
10661 const_or_pre_comp_const_index[2] = 3;
10662 const_or_pre_comp_const_index[3] = 2;
10663
10664 const_or_pre_comp_const_index[4] = 5;
10665 const_or_pre_comp_const_index[5] = 4;
10666 }
10667 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10668 in2, in1, in_out,
10669 tmp1, tmp2, tmp3,
10670 w_xtmp1, w_xtmp2, w_xtmp3,
10671 tmp4, tmp5,
10672 tmp6);
10673 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10674 in2, in1, in_out,
10675 tmp1, tmp2, tmp3,
10676 w_xtmp1, w_xtmp2, w_xtmp3,
10677 tmp4, tmp5,
10678 tmp6);
10679 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10680 in2, in1, in_out,
10681 tmp1, tmp2, tmp3,
10682 w_xtmp1, w_xtmp2, w_xtmp3,
10683 tmp4, tmp5,
10684 tmp6);
10685 movl(tmp1, in2);
10686 andl(tmp1, 0x00000007);
10687 negl(tmp1);
10688 addl(tmp1, in2);
10689 addq(tmp1, in1);
10690
10691 BIND(L_wordByWord);
10692 cmpq(in1, tmp1);
10693 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10694 crc32(in_out, Address(in1, 0), 4);
10695 addq(in1, 4);
10696 jmp(L_wordByWord);
10697
10698 BIND(L_byteByByteProlog);
10699 andl(in2, 0x00000007);
10700 movl(tmp2, 1);
10701
10702 BIND(L_byteByByte);
10703 cmpl(tmp2, in2);
10704 jccb(Assembler::greater, L_exit);
10705 crc32(in_out, Address(in1, 0), 1);
10706 incq(in1);
10707 incl(tmp2);
10708 jmp(L_byteByByte);
10709
10710 BIND(L_exit);
10711 }
10712 #else
10713 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10714 Register tmp1, Register tmp2, Register tmp3,
10715 Register tmp4, Register tmp5, Register tmp6,
10716 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10717 bool is_pclmulqdq_supported) {
10718 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10719 Label L_wordByWord;
10720 Label L_byteByByteProlog;
10721 Label L_byteByByte;
10722 Label L_exit;
10723
10724 if (is_pclmulqdq_supported) {
10725 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10726 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10727
10728 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10729 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10730
10731 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10732 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10733 } else {
10734 const_or_pre_comp_const_index[0] = 1;
10735 const_or_pre_comp_const_index[1] = 0;
10736
10737 const_or_pre_comp_const_index[2] = 3;
10738 const_or_pre_comp_const_index[3] = 2;
10739
10740 const_or_pre_comp_const_index[4] = 5;
10741 const_or_pre_comp_const_index[5] = 4;
10742 }
10743 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10744 in2, in1, in_out,
10745 tmp1, tmp2, tmp3,
10746 w_xtmp1, w_xtmp2, w_xtmp3,
10747 tmp4, tmp5,
10748 tmp6);
10749 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10750 in2, in1, in_out,
10751 tmp1, tmp2, tmp3,
10752 w_xtmp1, w_xtmp2, w_xtmp3,
10753 tmp4, tmp5,
10754 tmp6);
10755 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10756 in2, in1, in_out,
10757 tmp1, tmp2, tmp3,
10758 w_xtmp1, w_xtmp2, w_xtmp3,
10759 tmp4, tmp5,
10760 tmp6);
10761 movl(tmp1, in2);
10762 andl(tmp1, 0x00000007);
10763 negl(tmp1);
10764 addl(tmp1, in2);
10765 addl(tmp1, in1);
10766
10767 BIND(L_wordByWord);
10768 cmpl(in1, tmp1);
10769 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10770 crc32(in_out, Address(in1,0), 4);
10771 addl(in1, 4);
10772 jmp(L_wordByWord);
10773
10774 BIND(L_byteByByteProlog);
10775 andl(in2, 0x00000007);
10776 movl(tmp2, 1);
10777
10778 BIND(L_byteByByte);
10779 cmpl(tmp2, in2);
10780 jccb(Assembler::greater, L_exit);
10781 movb(tmp1, Address(in1, 0));
10782 crc32(in_out, tmp1, 1);
10783 incl(in1);
10784 incl(tmp2);
10785 jmp(L_byteByByte);
10786
10787 BIND(L_exit);
10788 }
10789 #endif // LP64
10790 #undef BIND
10791 #undef BLOCK_COMMENT
10792
10793 // Compress char[] array to byte[].
10794 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
10795 // @HotSpotIntrinsicCandidate
10796 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
10797 // for (int i = 0; i < len; i++) {
10798 // int c = src[srcOff++];
10799 // if (c >>> 8 != 0) {
10800 // return 0;
10801 // }
10802 // dst[dstOff++] = (byte)c;
10803 // }
10804 // return len;
10805 // }
10806 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10807 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10808 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10809 Register tmp5, Register result) {
10810 Label copy_chars_loop, return_length, return_zero, done, below_threshold;
10811
10812 // rsi: src
10813 // rdi: dst
10814 // rdx: len
10815 // rcx: tmp5
10816 // rax: result
10817
10818 // rsi holds start addr of source char[] to be compressed
10819 // rdi holds start addr of destination byte[]
10820 // rdx holds length
10821
10822 assert(len != result, "");
10823
10824 // save length for return
10825 push(len);
10826
10827 if ((UseAVX > 2) && // AVX512
10828 VM_Version::supports_avx512vlbw() &&
10829 VM_Version::supports_bmi2()) {
10830
10831 set_vector_masking(); // opening of the stub context for programming mask registers
10832
10833 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero;
10834
10835 // alignement
10836 Label post_alignement;
10837
10838 // if length of the string is less than 16, handle it in an old fashioned
10839 // way
10840 testl(len, -32);
10841 jcc(Assembler::zero, below_threshold);
10842
10843 // First check whether a character is compressable ( <= 0xFF).
10844 // Create mask to test for Unicode chars inside zmm vector
10845 movl(result, 0x00FF);
10846 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
10847
10848 // Save k1
10849 kmovql(k3, k1);
10850
10851 testl(len, -64);
10852 jcc(Assembler::zero, post_alignement);
10853
10854 movl(tmp5, dst);
10855 andl(tmp5, (32 - 1));
10856 negl(tmp5);
10857 andl(tmp5, (32 - 1));
10858
10859 // bail out when there is nothing to be done
10860 testl(tmp5, 0xFFFFFFFF);
10861 jcc(Assembler::zero, post_alignement);
10862
10863 // ~(~0 << len), where len is the # of remaining elements to process
10864 movl(result, 0xFFFFFFFF);
10865 shlxl(result, result, tmp5);
10866 notl(result);
10867 kmovdl(k1, result);
10868
10869 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10870 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10871 ktestd(k2, k1);
10872 jcc(Assembler::carryClear, restore_k1_return_zero);
10873
10874 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10875
10876 addptr(src, tmp5);
10877 addptr(src, tmp5);
10878 addptr(dst, tmp5);
10879 subl(len, tmp5);
10880
10881 bind(post_alignement);
10882 // end of alignement
10883
10884 movl(tmp5, len);
10885 andl(tmp5, (32 - 1)); // tail count (in chars)
10886 andl(len, ~(32 - 1)); // vector count (in chars)
10887 jcc(Assembler::zero, copy_loop_tail);
10888
10889 lea(src, Address(src, len, Address::times_2));
10890 lea(dst, Address(dst, len, Address::times_1));
10891 negptr(len);
10892
10893 bind(copy_32_loop);
10894 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
10895 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10896 kortestdl(k2, k2);
10897 jcc(Assembler::carryClear, restore_k1_return_zero);
10898
10899 // All elements in current processed chunk are valid candidates for
10900 // compression. Write a truncated byte elements to the memory.
10901 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
10902 addptr(len, 32);
10903 jcc(Assembler::notZero, copy_32_loop);
10904
10905 bind(copy_loop_tail);
10906 // bail out when there is nothing to be done
10907 testl(tmp5, 0xFFFFFFFF);
10908 // Restore k1
10909 kmovql(k1, k3);
10910 jcc(Assembler::zero, return_length);
10911
10912 movl(len, tmp5);
10913
10914 // ~(~0 << len), where len is the # of remaining elements to process
10915 movl(result, 0xFFFFFFFF);
10916 shlxl(result, result, len);
10917 notl(result);
10918
10919 kmovdl(k1, result);
10920
10921 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10922 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10923 ktestd(k2, k1);
10924 jcc(Assembler::carryClear, restore_k1_return_zero);
10925
10926 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10927 // Restore k1
10928 kmovql(k1, k3);
10929 jmp(return_length);
10930
10931 bind(restore_k1_return_zero);
10932 // Restore k1
10933 kmovql(k1, k3);
10934 jmp(return_zero);
10935
10936 clear_vector_masking(); // closing of the stub context for programming mask registers
10937 }
10938 if (UseSSE42Intrinsics) {
10939 Label copy_32_loop, copy_16, copy_tail;
10940
10941 bind(below_threshold);
10942
10943 movl(result, len);
10944
10945 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
10946
10947 // vectored compression
10948 andl(len, 0xfffffff0); // vector count (in chars)
10949 andl(result, 0x0000000f); // tail count (in chars)
10950 testl(len, len);
10951 jccb(Assembler::zero, copy_16);
10952
10953 // compress 16 chars per iter
10954 movdl(tmp1Reg, tmp5);
10955 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10956 pxor(tmp4Reg, tmp4Reg);
10957
10958 lea(src, Address(src, len, Address::times_2));
10959 lea(dst, Address(dst, len, Address::times_1));
10960 negptr(len);
10961
10962 bind(copy_32_loop);
10963 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
10964 por(tmp4Reg, tmp2Reg);
10965 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
10966 por(tmp4Reg, tmp3Reg);
10967 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
10968 jcc(Assembler::notZero, return_zero);
10969 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
10970 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
10971 addptr(len, 16);
10972 jcc(Assembler::notZero, copy_32_loop);
10973
10974 // compress next vector of 8 chars (if any)
10975 bind(copy_16);
10976 movl(len, result);
10977 andl(len, 0xfffffff8); // vector count (in chars)
10978 andl(result, 0x00000007); // tail count (in chars)
10979 testl(len, len);
10980 jccb(Assembler::zero, copy_tail);
10981
10982 movdl(tmp1Reg, tmp5);
10983 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10984 pxor(tmp3Reg, tmp3Reg);
10985
10986 movdqu(tmp2Reg, Address(src, 0));
10987 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
10988 jccb(Assembler::notZero, return_zero);
10989 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
10990 movq(Address(dst, 0), tmp2Reg);
10991 addptr(src, 16);
10992 addptr(dst, 8);
10993
10994 bind(copy_tail);
10995 movl(len, result);
10996 }
10997 // compress 1 char per iter
10998 testl(len, len);
10999 jccb(Assembler::zero, return_length);
11000 lea(src, Address(src, len, Address::times_2));
11001 lea(dst, Address(dst, len, Address::times_1));
11002 negptr(len);
11003
11004 bind(copy_chars_loop);
11005 load_unsigned_short(result, Address(src, len, Address::times_2));
11006 testl(result, 0xff00); // check if Unicode char
11007 jccb(Assembler::notZero, return_zero);
11008 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
11009 increment(len);
11010 jcc(Assembler::notZero, copy_chars_loop);
11011
11012 // if compression succeeded, return length
11013 bind(return_length);
11014 pop(result);
11015 jmpb(done);
11016
11017 // if compression failed, return 0
11018 bind(return_zero);
11019 xorl(result, result);
11020 addptr(rsp, wordSize);
11021
11022 bind(done);
11023 }
11024
11025 // Inflate byte[] array to char[].
11026 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
11027 // @HotSpotIntrinsicCandidate
11028 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
11029 // for (int i = 0; i < len; i++) {
11030 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
11031 // }
11032 // }
11033 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
11034 XMMRegister tmp1, Register tmp2) {
11035 Label copy_chars_loop, done, below_threshold;
11036 // rsi: src
11037 // rdi: dst
11038 // rdx: len
11039 // rcx: tmp2
11040
11041 // rsi holds start addr of source byte[] to be inflated
11042 // rdi holds start addr of destination char[]
11043 // rdx holds length
11044 assert_different_registers(src, dst, len, tmp2);
11045
11046 if ((UseAVX > 2) && // AVX512
11047 VM_Version::supports_avx512vlbw() &&
11048 VM_Version::supports_bmi2()) {
11049
11050 set_vector_masking(); // opening of the stub context for programming mask registers
11051
11052 Label copy_32_loop, copy_tail;
11053 Register tmp3_aliased = len;
11054
11055 // if length of the string is less than 16, handle it in an old fashioned
11056 // way
11057 testl(len, -16);
11058 jcc(Assembler::zero, below_threshold);
11059
11060 // In order to use only one arithmetic operation for the main loop we use
11061 // this pre-calculation
11062 movl(tmp2, len);
11063 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
11064 andl(len, -32); // vector count
11065 jccb(Assembler::zero, copy_tail);
11066
11067 lea(src, Address(src, len, Address::times_1));
11068 lea(dst, Address(dst, len, Address::times_2));
11069 negptr(len);
11070
11071
11072 // inflate 32 chars per iter
11073 bind(copy_32_loop);
11074 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
11075 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
11076 addptr(len, 32);
11077 jcc(Assembler::notZero, copy_32_loop);
11078
11079 bind(copy_tail);
11080 // bail out when there is nothing to be done
11081 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
11082 jcc(Assembler::zero, done);
11083
11084 // Save k1
11085 kmovql(k2, k1);
11086
11087 // ~(~0 << length), where length is the # of remaining elements to process
11088 movl(tmp3_aliased, -1);
11089 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
11090 notl(tmp3_aliased);
11091 kmovdl(k1, tmp3_aliased);
11092 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit);
11093 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit);
11094
11095 // Restore k1
11096 kmovql(k1, k2);
11097 jmp(done);
11098
11099 clear_vector_masking(); // closing of the stub context for programming mask registers
11100 }
11101 if (UseSSE42Intrinsics) {
11102 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
11103
11104 movl(tmp2, len);
11105
11106 if (UseAVX > 1) {
11107 andl(tmp2, (16 - 1));
11108 andl(len, -16);
11109 jccb(Assembler::zero, copy_new_tail);
11110 } else {
11111 andl(tmp2, 0x00000007); // tail count (in chars)
11112 andl(len, 0xfffffff8); // vector count (in chars)
11113 jccb(Assembler::zero, copy_tail);
11114 }
11115
11116 // vectored inflation
11117 lea(src, Address(src, len, Address::times_1));
11118 lea(dst, Address(dst, len, Address::times_2));
11119 negptr(len);
11120
11121 if (UseAVX > 1) {
11122 bind(copy_16_loop);
11123 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
11124 vmovdqu(Address(dst, len, Address::times_2), tmp1);
11125 addptr(len, 16);
11126 jcc(Assembler::notZero, copy_16_loop);
11127
11128 bind(below_threshold);
11129 bind(copy_new_tail);
11130 if ((UseAVX > 2) &&
11131 VM_Version::supports_avx512vlbw() &&
11132 VM_Version::supports_bmi2()) {
11133 movl(tmp2, len);
11134 } else {
11135 movl(len, tmp2);
11136 }
11137 andl(tmp2, 0x00000007);
11138 andl(len, 0xFFFFFFF8);
11139 jccb(Assembler::zero, copy_tail);
11140
11141 pmovzxbw(tmp1, Address(src, 0));
11142 movdqu(Address(dst, 0), tmp1);
11143 addptr(src, 8);
11144 addptr(dst, 2 * 8);
11145
11146 jmp(copy_tail, true);
11147 }
11148
11149 // inflate 8 chars per iter
11150 bind(copy_8_loop);
11151 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
11152 movdqu(Address(dst, len, Address::times_2), tmp1);
11153 addptr(len, 8);
11154 jcc(Assembler::notZero, copy_8_loop);
11155
11156 bind(copy_tail);
11157 movl(len, tmp2);
11158
11159 cmpl(len, 4);
11160 jccb(Assembler::less, copy_bytes);
11161
11162 movdl(tmp1, Address(src, 0)); // load 4 byte chars
11163 pmovzxbw(tmp1, tmp1);
11164 movq(Address(dst, 0), tmp1);
11165 subptr(len, 4);
11166 addptr(src, 4);
11167 addptr(dst, 8);
11168
11169 bind(copy_bytes);
11170 }
11171 testl(len, len);
11172 jccb(Assembler::zero, done);
11173 lea(src, Address(src, len, Address::times_1));
11174 lea(dst, Address(dst, len, Address::times_2));
11175 negptr(len);
11176
11177 // inflate 1 char per iter
11178 bind(copy_chars_loop);
11179 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
11180 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
11181 increment(len);
11182 jcc(Assembler::notZero, copy_chars_loop);
11183
11184 bind(done);
11185 }
11186
11187 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
11188 switch (cond) {
11189 // Note some conditions are synonyms for others
11190 case Assembler::zero: return Assembler::notZero;
11191 case Assembler::notZero: return Assembler::zero;
11192 case Assembler::less: return Assembler::greaterEqual;
11193 case Assembler::lessEqual: return Assembler::greater;
11194 case Assembler::greater: return Assembler::lessEqual;
11195 case Assembler::greaterEqual: return Assembler::less;
11196 case Assembler::below: return Assembler::aboveEqual;
11197 case Assembler::belowEqual: return Assembler::above;
11198 case Assembler::above: return Assembler::belowEqual;
11199 case Assembler::aboveEqual: return Assembler::below;
11200 case Assembler::overflow: return Assembler::noOverflow;
11201 case Assembler::noOverflow: return Assembler::overflow;
11202 case Assembler::negative: return Assembler::positive;
11203 case Assembler::positive: return Assembler::negative;
11204 case Assembler::parity: return Assembler::noParity;
11205 case Assembler::noParity: return Assembler::parity;
11206 }
11207 ShouldNotReachHere(); return Assembler::overflow;
11208 }
11209
11210 SkipIfEqual::SkipIfEqual(
11211 MacroAssembler* masm, const bool* flag_addr, bool value) {
11212 _masm = masm;
11213 _masm->cmp8(ExternalAddress((address)flag_addr), value);
11214 _masm->jcc(Assembler::equal, _label);
11215 }
11216
11217 SkipIfEqual::~SkipIfEqual() {
11218 _masm->bind(_label);
11219 }
11220
11221 // 32-bit Windows has its own fast-path implementation
11222 // of get_thread
11223 #if !defined(WIN32) || defined(_LP64)
11224
11225 // This is simply a call to Thread::current()
11226 void MacroAssembler::get_thread(Register thread) {
11227 if (thread != rax) {
11228 push(rax);
11229 }
11230 LP64_ONLY(push(rdi);)
11231 LP64_ONLY(push(rsi);)
11232 push(rdx);
11233 push(rcx);
11234 #ifdef _LP64
11235 push(r8);
11236 push(r9);
11237 push(r10);
11238 push(r11);
11239 #endif
11240
11241 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
11242
11243 #ifdef _LP64
11244 pop(r11);
11245 pop(r10);
11246 pop(r9);
11247 pop(r8);
11248 #endif
11249 pop(rcx);
11250 pop(rdx);
11251 LP64_ONLY(pop(rsi);)
11252 LP64_ONLY(pop(rdi);)
11253 if (thread != rax) {
11254 mov(thread, rax);
11255 pop(rax);
11256 }
11257 }
11258
11259 #endif